Lenovo ThinkPad T480 Schematic

5

4

WD-2 Logic Schematics

3

2

1

1.TITLE PAGE

2.EC HISTORY

D D

3.CPU(1/16) : DDI/EDP

4.CPU(2/16) : DDR CHANNEL-A

5.CPU(3/16) : DDR CHANNEL-B

6.CPU(4/16) : MISC/JTAG

7.CPU(5/16) : LPC/SPI/SMBUS/C-LINK

8.CPU(6/16) : LPSS/ISH

9.CPU(7/16) : AUDIO/SDXC

10.CPU(8/16) : PCIE/USB/SATA

11.CPU(9/16) : CSI-2/EMMC

12.CPU(10/16) : CLOCK SIGNALS

13.CPU(11/16) : SYSTEM PM

C C

14.CPU(12/16) : CPU POWER (1/2)

15.CPU(13/16) : CPU POWER (2/2)

16.CPU(14/16) : PCH POWER

17.CPU(15/16) : GND

18.CPU(16/16) : CFG/RESERVED

19.XDP CONNECTOR

20.RTC BATTERY

21.SPI FLASH

22.DDR4 SO DIMM CHANNEL-A (1/2)

23.DDR4 SO DIMM CHANNEL-A (2/2)

B B

24.DDR4 SO DIMM CHANNEL-B (1/2)

25.DDR4 SO DIMM CHANNEL-B (2/2)

26.LCD/LID/MIC/CAMERA/PWR SW

27.BLANK

28.DDI DEMULTIPLEXER

29.USB TYPE-C SWITCH

30.BLANK

31.ALPINE RIDGE (1/2)

32.ALPINE RIDGE (2/2)

33.USB PD CONTROLLER(1/2)

34.USB PD CONTROLLER(1/2)

A A

35.DOCKING CONNECTOR

36.USB TYPE-C CONNECTOR

37.HDMI CONNECTOR

38.STORAGE I/F REDRIVER

39.SATA EXPRESS CONNECTOR

40.USB POWER/CONN

41.GBE JACKSONVILLE

42.GBE LAN SWITCH

43.GBE MAGNETICS

44.RJ45 CONNECTOR

45.M.2 SOCKET 1 MODULE I/F

46.M.2 SOCKET 2 MODULE I/F

47.MEDIA CARD CONTROLLER

48.MEDIA CARD INTERFACE

49.AUDIO ALC3287-CG

50.AUDIO CONNECTOR

51.BLANK

52.AUDIO EXT MIC I/F

53.AUDIO SPEAKER

54.AUDIO BEEP

55.MEC1653(1/3)

56.MEC1653(2/3)

57.MEC1653(3/3)

58.KEYBOARD/TRACK POINT

59.TOUCH PAD/NFC/FPR/SCR

60.BLANK

61.FAN CONNECTOR

62.APS G-SENSOR

63.DISCRETE TPM 2.0

64.SMBUS SWITCH/LPC DEBUG PORT

65.THINK ENGINE-2(1/2)

66.THINK ENGINE-2(2/2)

67.DC-IN

68.BATTERY INPUT

69.BATTERY CHARGER(BQ25700A)

70.CHARGER SELECTOR

71.DC/DC VCC5M/VCC3M (TPS71285B-1)

72.DC/DC IMVP8 (NCP81218)

73.DC/DC CPUCORE(NCP302035)

74.DC/DC VCCGFXCORE_I(NCP302035)

75.DC/DC VCCSA(NCP302035)

76.BLANK

77.BLANK

78.DC/DC VCC1R0_SUS(TPS51367RV)

79.LOAD SW VCCST & VCCSTG

80.DC/DC VCC1R2A/0R6B/2R5A(NB687)

81.BLANK

82.BLANK

83.DC/DC VCC1R8_SUS(BU90104GWZ)

84.BLANK

85.BLANK

86.BLANK

87.LOAD SW PCH SUS/TRACK POINT

88.LOAD SW LAN

89.LOAD SW B

90.LOAD SW WWAN & WLAN

91.SCREW

92.N17S-G1 (1/6) : PEG I/F

93.N17S-G1 (2/6) : VRAM I/F

94.N17S-G1 (3/6) : POWER 1

95.N17S-G1 (4/6) : POWER 2

96.N17S-G1 (5/6) : GND

97.N17S-G1 (6/6) : GPIO / XTAL

98.VRAM CHANNEL-A

99.MEMORY TERMINATION

100.DC/DC VCC1R0VIDEO(BD9B304QWZ)

101.DC/DC VCCGFXCORE_D(NCP81278T)

102.DC/DC VCC1R35VIDEO(NB693)

103.DC/DC VCC1R8VIDEO_AON(BD9B304QWZ)

104.LOAD SW VIDEO

Title

Security Classification

LCFC CONFIDENTION

5

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

TITLE PAGE

Size

Document Number Re v

Document Number Rev

Custom

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

1 104

0.1

of

5

4

3

2

1

DDR4 / 1.2V

DDR4

SO-DIMMA

DDR4

SO-DIMMB

CPU XDP

NFC

C-Link

PCI Express x 8 ports

HDA

SPI Flash

64Mbits

(SPI1)

W25Q128FVSIQ

63

22,23

24,25

19

59

21

Stereo

Speaker

ALC3287-CG HDA CODEC

53

Microphone Headphone

49,50

50

Audio Combo Jack

Different with Windu-1

External Connector/Socket

VRAM GDDR 5 32 bit

98,99

D D

HDMI Conn

USB TYPE-C

WiGig

(M.2 WLAN Card)

USB3.0 CONN (USB1)

USB3.0 AOU (USB2)

C C

USB2.0 Smart Cart

USB TYPE-C

USB2.0

IR Camera

USB2.0 M.2 WWAN Slot

USB2.0 M.2 WLAN Slot (BT)

USB2.0 2D Camera

USB2.0 Fingerprint

USB2.0 Touch Panel

B B

40

59

36

26

46

45

26

59

26

Fingerprint

Reader

GDDR5

USB3.0 CH1 USB2.0 CH1

USB3.0 CH2 USB2.0 CH2

USB2.0 CH3

USB2.0 CH4

USB2.0 CH5

USB2.0 CH6

USB2.0 CH7

USB2.0 CH8

USB2.0 CH9

USB2.0 CH10

LED for ThinkPad Logos

USB2.0

Port 9

59

NVIDIA N17S-G1

92,93,94,9 5,96,97

LCD CONN eDP 14"

HD/FHD

DP

37

Mux

PS8349BQFN66GTR-A0

36

45

USB x 10 ports

RTC Battery

FAN

G-Sensor

KX022-1020

Thermal Sensor

SMB-MB/SB

SM Bus

ClickPad

20

64

65

PECI 3.0

Keyboard

26

28

PCIE x 4

Port 1,2,3,4

eDPx4

DDI x4

5859

10

Embedded

Controller MEC1653

CPU

Channel A

DDR4

Intel

Kaby Lake Kaby Lake-R

Platform

BGA14 40

15W

3,4,5,6,7, 8,9,10,11,12 13,14,15,1 6,17,18

LPC Bus 33MHz

55,56,57 65,66

Power Button

26

Channel B

DDR4

SM Bus

10

TPM 2.0

Lenovo ASIC ThinkEngine

BD4178GSW-ZE2

Internal Connector/Socket

Internal Switch

A A

Windu Block Diagram

Project Code: ET480

Antenna

(M.2 WLAN Card)

Type-A M.2 Card

Internal

Mic

26

USB3.0 CH03

Bluetoot h

USB

Port 7

49

MAGNETICS

RJ45

Multi-Media Controlle r

Real tek RTS53 44-GR

45

Port 6 (X1)

Port 5 (X1)

Intel GbE PHY JACKSONV ILLE

WGI219LM-SLKJ2-A0

43,44

LAN

SWITCH

PI3L720ZHE+CX

47

41

42

Side Dock

(CS18)

PCIE MUX CBTL0204 3ABQ

Port 11 (X1)

DP x4

SM Bus

35

SD Card Slot

2017 Feb ' 20

(M.2 WWAN Card)

10

Type-B M.2 Card

Micro SIM Card Slot

Port 12 (X1)

Port 9,10 (X2)

Alpine Ridge-LP

31,32

SPI Flash TBT

4M

48

Antenna

46

USB

49

Port 6

Port 7,8 (X2)

PD Conntroller TI TPS65988

SM Bus x2

DDI CH02

USB3.0 CH04

TABLE: Chip Capacitor Tolerance

Toleran ce

+/-0.25pF +/-0.5pF

+/-5% +/-10% +/-20% +80/-20%

TYPE-C SW PS8743

Code

C D

J

K M

Z

TABLE: Chip Capacitor Thermal Characteristics

-55 to 150degC

-55 to 125degC

-55 to 105degC

-55 to 85degC

SBU SW TS3DS10224

33

29

+/-30ppm/degC +/-30ppm/degC

+/-15% +/-22% +/-15%

Re-Driver

38

34

TABLE: Chip Part Dimension

Size [mm]

0.40 x 0.20

0.60 x 0.30

1.00 x 0.50

1.60 x 0.80

2.00 x 1.25

2.00 x 1.60

2.50 x 2.00

3.20 x 1.60

3.20 x 2.50

4.50 x 1.60

4.50 x 2.50

4.50 x 3.20

5.00 x 2.50

6.40 x 3.20

mm Size Code Inch Siz e Code

0402 0603 1005 1608 2125 2016 2520 3216 3225 4516 4525 4532 5025 6432

HDD CONN SSD

Side Dock

(CS18)

USB TYPE-C

Code

NPO

C0G

X7R X6S X5R

39

35

36

01005 0201 0402 0603 0805 0806 1008 1206 1210 1806 1810 1812 2010 2512

LOGIC

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

BLOCK DIAGRAM

Size

Document Number Re v

Document Number Rev

Custom

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

2 104

0.1

of

5

D D

4

VCCCPUIOVCC3_SUS

3

2

1

12

DDIP1_0N<31> DDIP1_0P<31> DDIP1_1N<31> DDIP1_1P<31> DDIP1_2N<31> DDIP1_2P<31> DDIP1_3N<31> DDIP1_3P<31>

DDIP2_0N<28> DDIP2_0P<28>

C C

TABLE : Functional Strap

DDIP2_1N<28> DDIP2_1P<28> DDIP2_2N<28> DDIP2_2P<28> DDIP2_3N<28> DDIP2_3P<28>

DDIP2_CTRLCLK<28> DDIP2_CTRLDATA<28>

-GPU_RST<92> 1R8VIDEO_AON_ON<97,103>

DDPB_CTRLDATA

HIGH

Port B is detected.

LOW

Port B is not detected.

DDIP1_0N DDIP1_0P DDIP1_1N DDIP1_1P DDIP1_2N DDIP1_2P DDIP1_3N DDIP1_3P

DDIP2_0N DDIP2_0P DDIP2_1N DDIP2_1P DDIP2_2N DDIP2_2P DDIP2_3N DDIP2_3P

DDIP2_CTRLCLK DDIP2_CTRLDATA

-GPU_RST 1R8VIDEO_AON_ON

12

SWG@

R10252 1M_0201_5%

R10131

2.2K_0201_5%

12

SWG@

R10469 1M_0201_5%

12

R5

24.9_0201_1%

EDP_COMP

U58A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

KBL_R_U42_BGA1356

@

SKL_ULT

DDI

DISPLAY SIDEBANDS

1 OF 20

EDP

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

12

R433

100K_0201_5%

12

100K_0201_5%

12

R138

R8 100K_0201_5%

12

R10228 100K_0201_5%

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

DDIP1_AUXN DDIP1_AUXP DDIP2_AUXN DDIP2_AUXP

DDIP1_HPD DDIP2_HPD

12

R10229 100K_0201_5%

EDP_TXN0 <26> EDP_TXP0 <26> EDP_TXN1 <26> EDP_TXP1 <26> EDP_TXN2 <26> EDP_TXP2 <26> EDP_TXN3 <26> EDP_TXP3 <26>

EDP_AUXN <26> EDP_AUXP <26>

DDIP1_AUXN <31> DDIP1_AUXP <31> DDIP2_AUXN <28> DDIP2_AUXP <28>

DDIP1_HPD <31> DDIP2_HPD <28>

EDP_HPD <26>

VGA_BLON <55> PANEL_BKLT_CTRL <26> PANEL_POWER_ON <66>

DDPC_CTRLDATA

HIGH

Port C is detected.

Port C is not detected.

B B

LOW

PCB KabyLake (MP) KabyLake-R (MP)

A A

LCFC CONFIDENTION

5

4

3

ZZZ2

NM-B501 REV1

DAZ16900100

SVT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

U58

i3-7130U non-vPro

SA00008LM20

I3NV@

2015/11/02

U58

i5-7300U vPro

SA000086M10

I5V@

LC Future Center Secret Data

2

Deciphered Date

U58

i5-7200U non-vPro

SA000080320

I5NV@

2015/8/10

U58

I5-8350U vPRO

SA00008JB10

RI5V@

U58

I7-8650U vPRO

SA00008JC10

RI7V@

Title

CPU(1/16) : DDI/EDP

Size

Document Number Rev

Custom

C

Date: Sheet

U58

I5-8250U non-vPRO

SA00008J520

R5NV@

Windu-2

Thursday, November 09, 2017

1

3 104

U58

I7-8550U non-vPRO

SA00008J620

R7NV@

of

0.1

5

M_A_DQ[63:0]<22>

TABLE

D D

Block 0

C C

Block 2

Block 4

B B

Block 6

A A

AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69

BB65

AW65 AW63 AY63 BA65 AY65 BA63 BB6 3 BA61 AW61 BB5 9 AW59 BB6 1 AY61 BA59 AY59

AY39

AW39 AY37 AW37 BB3 9 BA39 BA37 BB3 7 AY35 AW35 AY33 AW33 BB3 5 BA35 BA33 BB3 3

AY31

AW31 AY29 AW29 BB3 1 BA31 BA29 BB2 9 AY27 AW27 AY25 AW25 BB2 7 BA27 BA25 BB2 5

Interleav e

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9]

DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31]

DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47]

DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

Non-Interleave

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9]

DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47]

DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9]

DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15]

DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

4

U58B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

KBL_R_U42_BGA1356

@

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

TABLE

Block 0

Block 2

Block 4

Block 6

AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60

BA38 AY38 AY34 BA34

BA30 AY30 AY26 BA26

Interleav e

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_DQSN[2] DDR0_DQSP[2] DDR0_DQSN[3] DDR0_DQSP[3]

DDR0_DQSN[4] DDR0_DQSP[4] DDR0_DQSN[5] DDR0_DQSP[5]

DDR0_DQSN[6] DDR0_DQSP[6] DDR0_DQSN[7] DDR0_DQSP[7]

3

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

Non-Interleave

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_DQSN[4] DDR0_DQSP[4] DDR0_DQSN[5] DDR0_DQSP[5]

DDR1_DQSN[0] DDR1_DQSP[0] DDR1_DQSN[1] DDR1_DQSP[1]

DDR1_DQSN[4] DDR1_DQSP[4] DDR1_DQSN[5] DDR1_DQSP[5]

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

-M_A_DDRCLK0_1066M M_A_DDRCLK0_1066M

-M_A_DDRCLK1_1066M M_A_DDRCLK1_1066M

M_A_CKE0 M_A_CKE1

-M_A_CS0

-M_A_CS1 M_A_ODT0 M_A_ODT1

M_A_A5 M_A_A9 M_A_A6 M_A_A8 M_A_A7

M_A_BG0 M_A_A12 M_A_A11

M_A_BG1

M_A_A13 M_A_A15 M_A_A14 M_A_A16

M_A_BS0 M_A_A2

M_A_BS1 M_A_A10 M_A_A1 M_A_A0 M_A_A3 M_A_A4

-M_A_DQS0 M_A_DQS0

-M_A_DQS1 M_A_DQS1

-M_A_DQS2 M_A_DQS2

-M_A_DQS3 M_A_DQS3

-M_A_DQS4 M_A_DQS4

-M_A_DQS5 M_A_DQS5

-M_A_DQS6 M_A_DQS6

-M_A_DQS7 M_A_DQS7

DDR_PG_CTRL

-M_A_ACT

12

VCC1R2A

@

R1858 10K_0201_5%

-M_A_DDRCLK0_1066M <22> M_A_DDRCLK0_1066M <22>

-M_A_DDRCLK1_1066M <22> M_A_DDRCLK1_1066M <22>

M_A_CKE0 <22> M_A_CKE1 <22>

-M_A_CS0 <22>

-M_A_CS1 <22> M_A_ODT0 <22> M_A_ODT1 <22>

M_A_BG0 <22>

-M_A_ACT <22> M_A_BG1 <22>

M_A_BS0 <22>

M_A_BS1 <22>

-M_A_ALERT <22>

M_A_PARITY <22>

M_A_VREF_CA_CPU <22>

M_B_VREF_CA_CPU <24>

VCC3M

12

R1838 100K_0201_5%

1

2

Q170 DTC015TMT2L_VMT3

3

M_A_A[16:0] <22>

-M_A_DQS[7:0] <22>

M_A_DQS[7:0] <22>

DDR_VTT_PG_CTRL

2

DDR_VTT_PG_CTRL <80>

TABLE

BA51 BB5 4 BA52 AY52

AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB5 0 AY50 BA50 BB5 2

DDR3L LPDDR3

DDR0_MA[5] DDR0_MA[9] DDR0_MA[6] DDR0_MA[8] DDR0_MA[7]

DDR0_BA[2] DDR0_MA[12] DDR0_MA[11] DDR0_MA[15] DDR0_MA[14]

DDR0_MA[13]

DDR0_CAS# DDR0_WE# DDR0_RAS# DDR0_BA[0] DDR0_MA[2] DDR0_BA[1] DDR0_MA[10] DDR0_MA[1] DDR0_MA[0] DDR0_MA[3] DDR0_MA[4]

DDR0_CAA[0] DDR0_CAA[1] DDR0_CAA[2] DDR0_CAA[3] DDR0_CAA[4] DDR0_CAA[5] DDR0_CAA[6] DDR0_CAA[7] DDR0_CAA[8] DDR0_CAA[9]

DDR0_CAB[0] DDR0_CAB[1] DDR0_CAB[2] DDR0_CAB[3] DDR0_CAB[4] DDR0_CAB[5] DDR0_CAB[6] DDR0_CAB[7] DDR0_CAB[8] DDR0_CAB[9] Not Used Not Used

1

DDR4

DDR0_MA[5] DDR0_MA[9] DDR0_MA[6] DDR0_MA[8] DDR0_MA[7] DDR0_BG[0 ] DDR0_MA[12] DDR0_MA[11] DDR0_ACT# DDR0_BG[1 ]

DDR0_MA[13] DDR0_MA[15] DDR0_MA[14] DDR0_MA[16]

DDR0_BA[0] DDR0_MA[2] DDR0_BA[1] DDR0_MA[10] DDR0_MA[1] DDR0_MA[0] DDR0_MA[3] DDR0_MA[4]

LOGIC

Title

Security Classification

LOGIC

LCFC CONFIDENTION

5

4

LOGIC

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(2/16) : DDR CHANNEL-A

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

4 104

0.1

of

5

4

3

2

1

TABLE

Block 1

Block 3

Block 5

Block 7

AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69

AT66

AU66

AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60

AU40 AT40 AT37 AU37 AR40

AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30

AU27 AT27 AT25 AU25

AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

D D

C C

B B

A A

Interleav e

DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9]

DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15]

DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31]

DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

Non-Interleave

DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31]

DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

M_B_DQ[63:0]<24>

SKL_ULT

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR CH - B

3 OF 20

DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DDR1_PAR

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

-M_B_DDRCLK0_1066M

-M_B_DDRCLK1_1066M M_B_DDRCLK0_1066M M_B_DDRCLK1_1066M

M_B_CKE0 M_B_CKE1

-M_B_CS0

-M_B_CS1 M_B_ODT0 M_B_ODT1

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7

M_B_BG0 M_B_A12 M_B_A11

M_B_BG1

M_B_A13 M_B_A15 M_B_A14 M_B_A16

M_B_BS0 M_B_A2

M_B_BS1 M_B_A10 M_B_A1 M_B_A0 M_B_A3 M_B_A4

-M_B_DQS0 M_B_DQS0

-M_B_DQS1 M_B_DQS1

-M_B_DQS2 M_B_DQS2

-M_B_DQS3 M_B_DQS3

-M_B_DQS4 M_B_DQS4

-M_B_DQS5 M_B_DQS5

-M_B_DQS6 M_B_DQS6

-M_B_DQS7 M_B_DQS7

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

-M_B_DDRCLK0_1066M <24>

-M_B_DDRCLK1_1066M <24> M_B_DDRCLK0_1066M <24> M_B_DDRCLK1_1066M <24>

M_B_CKE0 <24> M_B_CKE1 <24>

-M_B_CS0 <24>

-M_B_CS1 <24> M_B_ODT0 <24> M_B_ODT1 <24>

-M_B_ACT

1 2

R7 121_0201_1%

1 2

R84 80.6_0201_1%

1 2

R576 100_0201_1%

M_B_BG0 <24>

-M_B_ACT <24> M_B_BG1 <24>

M_B_BS0 <24>

M_B_BS1 <24>

M_B_A[16:0] <24>

-M_B_DQS[7:0] <24>

M_B_DQS[7:0] <24>

VCC1R2A

12

R1726 470_0201_5%

-M_B_ALERT M_B_PARITY

-DRAMRST

TABLE

-M_B_ALERT <24> M_B_PARITY <24>

-DRAMRST <22,24>

AY48

AP50 BA48 BB4 8 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44

AW44 BB4 4 AY47 BA44 AW46 AY46 BA46 BB4 6 BA47

DDR3L LPDDR3 DDR4

DDR1_MA[5] DDR1_MA[9] DDR1_MA[6] DDR1_MA[8] DDR1_MA[7]

DDR1_BA[2] DDR1_MA[12] DDR1_MA[11] DDR1_MA[15] DDR1_MA[14]

DDR1_MA[13]

DDR1_CAS# DDR1_WE# DDR1_RAS# DDR1_BA[0] DDR1_MA[2] DDR1_BA[1] DDR1_MA[10] DDR1_MA[1] DDR1_MA[0] DDR1_MA[3] DDR1_MA[4]

DDR1_CAA[0] DDR1_CAA[1] DDR1_CAA[2] DDR1_CAA[3] DDR1_CAA[4] DDR1_CAA[5] DDR1_CAA[6] DDR1_CAA[7] DDR1_CAA[8] DDR1_CAA[9]

DDR1_CAB[0] DDR1_CAB[1] DDR1_CAB[2] DDR1_CAB[3] DDR1_CAB[4] DDR1_CAB[5] DDR1_CAB[6] DDR1_CAB[7] DDR1_CAB[8] DDR1_CAB[9] Not Used Not Used

DDR1_MA[5] DDR1_MA[9] DDR1_MA[6] DDR1_MA[8] DDR1_MA[7] DDR1_BG[0 ] DDR1_MA[12] DDR1_MA[11] DDR1_ACT# DDR1_BG[1 ]

DDR1_MA[13] DDR1_MA[15] DDR1_MA[14] DDR1_MA[16]

DDR1_BA[0] DDR1_MA[2] DDR1_BA[1] DDR1_MA[10] DDR1_MA[1] DDR1_MA[0] DDR1_MA[3] DDR1_MA[4]

LOGIC

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

U58C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

KBL_R_U42_BGA1356

@

TABLE

Block 1

Block 3

Block 5

Block 7

AH66 AH65 AG69 AG70

AR66 AR65 AR61 AR60

AT38

AR38 AT32 AR32

AR25 AR27 AR22 AR21

Interleav e

DDR1_DQSN[0] DDR1_DQSP[0] DDR1_DQSN[1] DDR1_DQSP[1]

DDR1_DQSN[2] DDR1_DQSP[2] DDR1_DQSN[3] DDR1_DQSP[3]

DDR1_DQSN[4] DDR1_DQSP[4] DDR1_DQSN[5] DDR1_DQSP[5]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

Non-Interleave

DDR0_DQSN[2] DDR0_DQSP[2] DDR0_DQSN[3] DDR0_DQSP[3]

DDR0_DQSN[6] DDR0_DQSP[6] DDR0_DQSN[7] DDR0_DQSP[7]

DDR1_DQSN[2] DDR1_DQSP[2] DDR1_DQSN[3] DDR1_DQSP[3]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

LOGIC

LCFC CONFIDENTION

5

4

LOGIC

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(3/16) : DDR CHANNEL-B

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

5 104

0.1

of

5

D D

VCCSTG VCCST VCCST

12

C C

PECI<56>

-PROCHOT<55,56,69,72>

-WWAN_DISABLE<46,55,57>

-TBT_PLUG_EVENT<31>

PECI

-PROCHOT

4

R64 1K_0201_5%

1 2

R85 499_0201_1%

1 2

R10623 0_0201_5%@

1 2

R2126 49.9_0201_1%

1 2

R2127 49.9_0201_1%

1 2

R2128 49.9_0201_1%

1 2

R2129 49.9_0201_1%

12

R9055 1K_0201_5%

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

12

R10334 1K_0201_5%

U58D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

KBL_R_U42_BGA1356

@

SKL_ULT

CPU MISC

4 OF 20

3

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

2

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

R2 51_0201_5%

1 2

XDP_TCK0 XDP_TDI XDP_TDO XDP_TMS

-XDP_TRST

XDP_TCK0 <19> XDP_TDI <19> XDP_TDO <19> XDP_TMS <19>

-XDP_TRST <19>

PCH_TCK <19>

1

B B

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(4/16) : MISC/JTAG

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

6 104

0.1

of

5

4

3

2

1

TABLE : Functional Strap

SPI0_MOSI (Boot Halt)

D D

C C

B B

HIGH

Disabled (Default)

LOW

Enabled

TABLE : Functional Strap

SPI0_MISO (JTAG ODT Disable)

HIGH

Enabled (Default)

LOW

Disabled

TABLE : Functional Strap

SPI0_IO2 (Consent Strap)

HIGH

Enabled (Default) Disabled

LOW

TABLE : Functional Strap

SPI0_IO3 (A0 Personality Strap)

HIGH

Disabled (Default) Enabled

LOW

VCC3_SUSVCC3B

12

SPI_CLK<21,63> SPI_MISO_IO1<21,63> SPI_MOSI_IO0<21,63> SPI_IO2<21> SPI_IO3<21>

-SPI_CS0<21>

-SPI_CS2<63>

-NFC_DTCT<59>

CL_CLK_WLAN<45> CL_DATA_WLAN<45>

-CL_RST_WLAN<45>

-KBRC<55>

IRQSER<55,64>

CL_CLK_WLAN CL_DATA_WLAN

-CL_RST_WLAN

R860

8.2K_0201_5%

12

@

R2559 1K_0201_5%

@

R272 10K_0201_5%

U58E

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

KBL_R_U42_BGA1356

@

SPI - FLASH

SPI - TOUCH

C LINK

SKL_ULT

SMBUS, SMLINK

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

5 OF 20

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

TABLE : Functional Strap

GPP_C5/SML0ALERT # (LPC or eSPI)

HIGH

eSPI is selected LPC is selected (Default)

LOW

TABLE : Functional Strap

GPP_C2/SMBALERT# (TLS Confidentiality)

HIGH

Enable ME Crypto TLS with Confidentiality

LOW

Disable ME Crypto TLS (Default)

VCC3_SUS VCC3B

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

12

R226 1K_0201_5%

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPCCLK_0 LPCCLK_1

12

R106 499_0201_1%

R193 33_0201_5%EMC@ R220 0_0201_5%@

12

R107 499_0201_1%

1 2 1 2

12

R394

4.7K_0201_5%

LOGIC

12

R397

4.7K_0201_5%

LPC_AD[3:0] <55,64>

-LPC_FRAME <55,64>

-SUS_STAT <55,64>

LPCCLK_EC_24M <55> LPCCLK_DEBUG_24M <64>

LOGIC

12

R28

8.2K_0201_5%

SMB_CLK SMB_DATA

SML0_CLK SML0_DATA

EC_SCL2 EC_SDA2

SMB_CLK <64> SMB_DATA <64>

SML0_CLK <41> SML0_DATA <41>

EC_SCL2 <56> EC_SDA2 <56>

-CLKRUN <55,64>

LPCCLK_EC_24M LPCCLK_DEBUG_24M

1

RF@

C9091 22P_0201_25V8-J

2

A A

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

1

@

C9092 22P_0201_25V8-J

2

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(5/16) : LPC/SPI/SMBUS/C-LINK

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

7 104

0.1

of

5

4

3

2

1

D D

12

R884 10K_0201_5%

R2340 10K_0201_5%

NFC_DLREQ<59>

C C

EPRIVACY_ON<26> TBT_FORCE_PWR<31>

-EC_SCI<55>

-EC_WAKE<55>

I2C0_DATA<59> I2C0_CLK<59>

-WWAN_RESET<46>

-INT_MIC_DTCT<26>

WWAN_CFG0<46> WWAN_CFG1<46>

R10676

B B

100K_0201_5%

-MIC_HW_EN

12

R961 0_0201_5%

@

VCC3_SUS

12

R65 1K_0201_5%

@

AH10

AH11 AH12

AF11 AF12

AN8 AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

AB3

AD1 AD2 AD3 AD4

AH9

TABLE : Functional Strap

GPP_B22/GSPI1_MOSI (Boot BIOS Destination)

HIGH

Boot BIOS from LPC

LOW

Boot BIOS from SPI (Default)

TABLE : Functional Strap

GPP_B18/GSPI0_MOSI (No Reboot)

HIGH

Enable "No Reboot" Mode

LOW

Disable "No Reboot" Mode (Default)

U58F

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

KBL_R_U42_BGA1356

@

LPSS ISH

SKL_ULT

6 OF 20

LOGIC

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

Mode l

SWG

UMA

R101 26

ASM

NO ASM

-DISCRETE_PRESENCE

DGFX_VRAM_ID0 DGFX_VRAM_ID1

-DISCRETE_PRESENCE

DGFX_VRAM_ID0

DGFX_VRAM_ID1

TABLE : DGFX_VRAM_IDTABLE : -DISCRETE_PRESENCE

DFX_V RAM_ID[1 ..0]

00B

01B

10B

11B

WWAN_CFG2 <46> WWAN_CFG3 <46>

1GB

2GB

4GB

N/A

1 2

R10126 0_0201_5%SWG@

1 2

R10127 0_0201_5%@

1 2

R10128 0_0201_5%SWG@

LOGIC

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(6/16) : LPSS/ISH

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

8 104

0.1

of

5

D D

4

3

2

1

VCC3_SUS

1 2

R846 1K_0201_5%

VCC3_SUS

12

@

R1009 1K_0201_5%

C C

B B

HDA_SYNC<49> HDA_BCLK<49> HDA_SDO<49>

HDA_SDIN0<49>

DDI_PRIORITY1<28> -SC_DTCT <59>

PCH_SPKR<54>

1

2

1 2

R423 33_0201_5%

1 2

R60 33_0201_5%EMC@

1 2

R74 33_0201_5%

EMC@

C38 22P_0201_25V8-J

GC6_FB_EN<97,102> NFC_ACTIVE<59>

-GPU_EVENT<97>

DGFX_PWRGD<92>

HDA_SYNC_CPU HDA_BCLK_CPU HDA_SDO_CPU

PLACE ON TOP SIDE

R566 0_0603_5%@

VCC3_SUS

TP901

Test_Point_20MIL

1

@

TEST PAD BOTTOM SIDE DO NOT MOVE AFTER FIX

1 2

R9133 0_0201_5%@

1 2

TP900

Test_Point_20MIL

1

@

GC6_FB_EN NFC_ACTIVE_R

-GPU_EVENT DGFX_PWRGD

PCH_SPKR

TABLE : Functional Strap

HDA_SDO/I2S0_TXD

Flash Descriptor Security Override

HIGH

Disable Flash Descriptor Security (Override)

LOW

Enable Flash Descriptor Security (Default)

U58G

AUDIO

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

KBL_R_U42_BGA1356

@

TABLE : Functional Strap

GPP_B14/SPKR (Top Swap Override)

HIGH

Enable "Top Swap" Mode

LOW

Disable "Top Swap" Mode (Default)

SKL_ULT

7 OF 20

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

LOGIC

SD_RCOMP

1 2

R2131 200_0201_1%

TBT_RTD3_PWR_EN <31> TBT_FORCE_USB_PWR <31>

-TBT_PERST <31>

-TBT_PCIE_WAKE <31>

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(7/16) : AUDIO/SDXC

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

9 104

0.1

of

5

USB3 1 USB3 2 USB3 3 USB3P2 USB3 4

PCIE 1 (x4) PCIE 2 (x4) PCIE 3 (x4) PCIE 4 (x4)

PCIE 5 (GbE)

PCIE 6

PCIE 7 (x2) GPIO STRAP PCIE 9 (x2) PCIE 9 (x2) PCIE 11 (x2) GPIO STRAP

PCIE0_L0_RXN<92> PCIE0_L0_RXP<92> PCIE0_L0_TXN<92> PCIE0_L0_TXP<92>

PCIE0_L1_RXN<92> PCIE0_L1_RXP<92> PCIE0_L1_TXN<92> PCIE0_L1_TXP<92>

PCIE0_L2_RXN<92> PCIE0_L2_RXP<92> PCIE0_L2_TXN<92> PCIE0_L2_TXP<92>

PCIE0_L3_RXN<92> PCIE0_L3_RXP<92> PCIE0_L3_TXN<92> PCIE0_L3_TXP<92>

PCIE4_RXN<41> PCIE4_RXP<41> PCIE4_TXN<41> PCIE4_TXP<41>

PCIE5_RXN<45> PCIE5_RXP<45> PCIE5_TXN<45> PCIE5_TXP<45>

PCIE6_L1_RXN<46> PCIE6_L1_RXP<46> PCIE6_L1_TXN<46> PCIE6_L1_TXP<46>

PCIE6_L0_SATA1_RXN<46> PCIE6_L0_SATA1_RXP<46> PCIE6_L0_SATA1_TXN<46> PCIE6_L0_SATA1_TXP<46>

PCIE8_L0_RXN<31> PCIE8_L0_RXP<31> PCIE8_L0_TXN<31> PCIE8_L0_TXP<31>

PCIE8_L1_RXN<31> PCIE8_L1_RXP<31> PCIE8_L1_TXN<31> PCIE8_L1_TXP<31>

-XDP_PRDY<19>

-XDP_PREQ<19>

-TPM_IRQ<63>

PCIE10_L0_RXN<38> PCIE10_L0_RXP<38>

PCIE10_L0_TXN<38> PCIE10_L0_TXP<38> PCIE10_L1_SATA2_RXN<38> PCIE10_L1_SATA2_RXP<38> PCIE10_L1_SATA2_TXN<38> PCIE10_L1_SATA2_TXP<38>

USB3P0 USB3P1

USB3P3

PCIE0 PCIE0 PCIE0 PCIE0 PCIE4 PCIE5 PCIE6_L1

PCIE6_L0_SATA1

PCIE8_L0 PCIE8_L1

PCIE10_L0

PCIE10_L1_SATA2

PCIE6_L0_SATA1_RXN PCIE6_L0_SATA1_RXP PCIE6_L0_SATA1_TXN PCIE6_L0_SATA1_TXP

-XDP_PRDY

-XDP_PREQ

-TPM_IRQ

PCIe Port Assignment

Discrete GPU

0 (x4)

4

GbE PHY

5

M.2 WLAN Slot Port 0 Optane x2

6 (x2)

(M.2 WWAN Slot) Alpine Ridge-LP

8 (x2)

10 (x2)

Main Storage x 2

Cap near U58 side

1 2

C2472 0.22U_0201_6.3V6M SWG@

1 2

C2473 0.22U_0201_6.3V6M SWG@

1 2

C2474 0.22U_0201_6.3V6M SWG@

1 2

C2475 0.22U_0201_6.3V6M SWG@

1 2

C2476 0.22U_0201_6.3V6M SWG@

1 2

C2477 0.22U_0201_6.3V6M SWG@

1 2

C2478 0.22U_0201_6.3V6M SWG@

1 2

C2479 0.22U_0201_6.3V6M SWG@

1 2

R8964 100_0201_1%

1 2

R529 0_0201_5%_SM

1 2

R530 0_0201_5%_SM

USB3 1

USB3 2/SSIC

USB3 3 USB3 4

USB3 5/PCIE 1 USB3 6/PCIE 2

PCIE 3 (GbE) PCIE 4 (GbE) PCIE 5 (GbE)

PCIE 6

PCIE 7/SATA 0 PCIE 8/SATA 1A

PCIE 9 (GbE)

PCIE 10 (GbE)

PCIE 11/SATA 1B PCIE 12/SATA 2

VCC3_SUS

R2341 10K_0201_5%

1 2

-TPM_IRQ

Flexible I/O Configuration

I/O High Speed Signals Configuration Net Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7

D D

Port 8 Port 9

Port 10

Port 11

Port 12 Port 13 Port 14 Port 15 Port 16

C C

B B

4

PCIE0_L0_TXN_C PCIE0_L0_TXP_C

PCIE0_L1_TXN_C PCIE0_L1_TXP_C

PCIE0_L2_TXN_C PCIE0_L2_TXP_C

PCIE0_L3_TXN_C PCIE0_L3_TXP_C

SATA Port Assignment

0

(PCIE 7)

1A

SATA SSD on WWAN slot

1B

(PCIE 11)

2

SATA SSD Main Storage

PCIE_RCOMPN PCIE_RCOMPP

BB11

U58H

PCIE/USB 3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ# GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

KBL_R_U42_BGA1356

SKL_ULT

8 OF 20

3

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN USB3_1_RXP

USB3_1_TXN USB3_1_TXP

USB3_4_RXN USB3_4_RXP

USB3_4_TXN USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

USB3P0_RXN USB3P0_RXP USB3P0_TXN USB3P0_TXP

USB3P2_TXN_C USB3P2_TXP_C

USBP0USBP0+

USBCOMP

-WWAN_SATA_DTCT

-PE_DTCT

VCC3_SUS

12

R248 10K_0201_5%

R648 10K_0201_5%

1 2

C9424 0.1U_0201_6.3V6-K

1 2

C9425 0.1U_0201_6.3V6-K

R564 113_0201_1% R2573 0_0201_5% R2580 1K_0201_5%

1

TP938 Test_Point_12MIL

1 2 1 2 1 2

2

USB3P0_RXN <40> USB3P0_RXP <40> USB3P0_TXN <40> USB3P0_TXP <40>

USB3P1_RXN_AOU <40> USB3P1_RXP_AOU <40> USB3P1_TXN_AOU <40> USB3P1_TXP_AOU <40>

USB3P2_RXN <47> USB3P2_RXP <47> USB3P2_TXN <47> USB3P2_TXP <47>

USB3P3_RXN_XBAR <29> USB3P3_RXP_XBAR <29> USB3P3_TXN_XBAR <29> USB3P3_TXP_XBAR <29>

USBP0- <40> USBP0+ <40>

USBP1-_AOU <40> USBP1+_AOU <40>

USBP2- <59> USBP2+ <59>

USBP3- <36> USBP3+ <36>

USBP4- <26> USBP4+ <26>

USBP5- <46> USBP5+ <46>

USBP6- <45> USBP6+ <45>

USBP7- <26> USBP7+ <26>

USBP8- <59> USBP8+ <59>

USBP9- <26> USBP9+ <26>

-USB_PORT0_OC0 <40>

-USB_PORT1_OC1 <40>

NFC_INT <59>

WIGIG_DISABLE

-WWAN_SSD_DTCT

SEL(U189)

XSD(U189)

PCIE6_L0_SATA1

L

To M.2 Socket2

12

Optane

To M.2 Socket2

R44 10K_0201_5%

SATA Cache

H

L

LLL

L

To M.2

Socket2

USB 2.0 Port Assignment

0

USB 3.0 System Port

1

USB 3.0 System Port (AOU)

2

Smart Cart Slot

3

USB Type-C Port

4

IR Camera

5

M.2 WWAN Slot

6

NGFF WLAN Slot

7

USB Camera

8

Fingerprint Reader

9

Touch Panel

USB 3.0 Port Assignment

0

USB 3.0 System Port

1

USB 3.0 System Port (AOU)

2

Media Card Controller

3

USB Type-C Port

4

(PCIE 1)

5

(PCIE 2)

VCC3_SUS

12

R2745 10K_0201_5%

H

LL

L

WWAN Slot

1

WWAN Card

H

L

HHH

H

L

To M.2

Disconnect

Socket1

NFC_ON <59>

SATA2_DEVSLP <39>

-PE_DTCT <39>

L

HHH

L

To M.2 Socket1

None

H

Disconnect

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(8/16) : PCIE/USB/SATA

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

10 104

0.1

of

5

D D

C C

4

CSI-2

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKL_ULT

9 OF 20

U58I

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

KBL_R_U42_BGA1356

@

3

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

2

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

PLANARID1 PLANARID2 PLANARID3

PLANARID0

-INTRUDER_PCH <13>

1

TABLE

LEVEL

1

0

PLANARID3 PLANARID2 PLANARID1 PLANARID0

12

B B

R43 0_0201_5%

@

R47 0_0201_5%

R113 0_0201_5%

12

R48 0_0201_5%

TABLE

LEVEL

SDV

FVT

SIT

SIT-R

SVT

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

Size

Custom

Date: Sheet

PLANAR ID

R113

R48

0123

R43 R47

NA

NA NA NA

ASM ASM ASM ASM

PLANARID[3..0]

0000B

0001B

0010B

1010B(For RTD3 rework)

0011B

0100B

CPU(9/16) : CSI-2/EMMC

Document Number Rev

C

Windu-2

Thursday, November 09, 2017

1

of

11 104

0.1

5

D D

VCC3B

12

R10615 10K_0201_5%

-PCIE0_CLK_100M<92> PCIE0_CLK_100M<92>

C C

B B

-CLKREQ_PCIE0<92>

-PCIE4_CLK_100M<41> PCIE4_CLK_100M<41>

-CLKREQ_PCIE4<41>

-PCIE5_CLK_100M<45> PCIE5_CLK_100M<45>

-CLKREQ_PCIE5<45>

-PCIE6_CLK_100M<46> PCIE6_CLK_100M<46>

-CLKREQ_PCIE6<46>

-PCIE8_CLK_100M<31> PCIE8_CLK_100M<31>

-CLKREQ_PCIE8<31>

-PCIE10_CLK_100M<39> PCIE10_CLK_100M<39>

-CLKREQ_PCIE10<39>

12

@

R10146 100K_0201_5%

-CLKREQ_PCIE8

-PCIE6_CLK_100M PCIE6_CLK_100M

-CLKREQ_PCIE6

AR10

AT10

D42 C42

B42 A42 AT7

D41 C41 AT8

D40 C40

B40 A40

AU8

E40 E38 AU7

4

U58J

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

KBL_R_U42_BGA1356

@

SKL_ULT

CLOCK SIGNALS

10 OF 20

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

XTAL24_IN XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

3

VCC1R0_SUS

12

R609

2.71K_0402_0.5%

SUSCLK_32K <45,55>

1 2

R10626 0_0201_5%U22@

1 2

R10627 0_0201_5%U22@

Follow Design Guide Routing

-SRTCRST <20>

-RTCRST <17,20>

12

XTAL24_IN_U22 XTAL24_OUT_U22

12

R351 10M_0201_5%

1 2

Y6 CRYSTAL 32.768KHZ 9PF 20PPM

Vendor P/N

9H03280012

TXC

1TJF090DJ1A000B

KDS

2

U22@

R308 1M_0201_5%

U22@

1 2

R133 0_0201_5%

1 2

C348 6.8P_0201_25V8-C

Y6

32.768KHZ 9PF 20PPM 9H03280012

1 2

C326 6.8P_0201_25V8-C

LCFC P/N

SJ10000J900

SJ100069400

XTAL24_OUT_R

1

U22@

C205

8.2P_0402_50V8-C

2

Vendor P/N TXC

KDS

U22@

Y5 24MHZ_8PF_8Y24080002

1

Y5 CRYSTAL - 24MHZ 8PF +-30PPM

8Y24080002

1ZZHAE24000CC0D

1

3

GND1

2

3

GND2

4

LCFC P/N

SJ10000HI00

SJ10000P200

1

U22@

C206

8.2P_0402_50V8-C

2

1

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(10/16) : CLOCK SIGNALS

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

12 104

0.1

of

5

1 2

-PLTRST_NEAR<31>

-PLTRST_FAR<39,41,45,46,55,63,64,65,92>

D D

C460

100P_0201_25V8-J

R991 33_0201_5%

R993 33_0201_5%

1

C46 100P_0201_25V8-J

2

1 2

VCC3M

4

U73

5

VCC

4

OUT_Y

TC7SG17FE_SON5

3

1

NC

2

IN_A

GND

-PLTRST

3

2

1

Vendor P/N

TOSHIBA

ON TI

C C

-XDP_DBR<17,19>

-RSMRST<19,56>

BPWRG<49,56,59,64,66> CPUCORE_PWRGD<72> MPWRG<56,66>

-PCIE_WAKE<31,45,65>

-LANWAKE<41> LANPHYPC<41>

B B

TABLE of U73

TC7SG17FE

NL17SZ17XV5T2G

SN74LVC1G17DRLR

MPWRG

4.7K_0201_5%

LCFC P/N

SA00005T00J

SA00005OU00

SA00005MG00

VCC3M

12

R19

VCC3M

12

R612 1K_0201_5%

TP160 Test_Point_20MIL

-SUSWARN

CPU_PWRGD

1

VCCST_PWRGD

1 2

R21 0_0201_5%_SM

1 2

R617 0_0201_5%_SM

1 2

R203 0_0201_5%_SM

1 2

R1884 0_0201_5%_SM

RTCVCC VCC3M

12

R646

U58K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

KBL_R_U42_BGA1356

@

-INTRUDER_PCH<11>

R10314 0_0201_5%_SM

SKL_ULT

SYSTEM POWER MANAGEMENT

1 2

11 OF 20

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

S3

1

4

2

3

SPVR310100_4P

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

-INTRUDER

AM10 AM11

1 2

R10 0_0201_5%_SM

1M_0201_5%

1

@

C7 1000P_0201_25V7-K

2

12

@

R614 10K_0201_5%

D5

1 2

RB520CM-30T2R_VMN2M2

-PCH_SLP_S0 <17,79>

-PCH_SLP_S3 <17,31,56,65,89>

-PCH_SLP_S4 <17,56,65,80>

-PCH_SLP_S5 <17,65>

-PCH_SLP_SUS <56>

-PCH_SLP_LAN <57>

-PCH_SLP_WLAN <56>

-PCH_SLP_M <17,65>

-PWRSW_EC <56>

AC_PRESENT <56>

-BATLOW <31,57>

-INTRUDER_EC

-INTRUDER_EC <57>

D5:SCS00007M00(RB520CM)

VCC3_SUS VCC1R0_SUS

12

R2324 10K_0201_5%

12

R2325 10K_0201_5%

VCCST_PWRGD

13

D

2

13

CPUCORE_ON<65,72>

A A

CPUCORE_ON

2

G

D

Q194 LSK3541G1ET2L_VMT3

S

LCFC CONFIDENTION

5

4

G

Q195 LSK3541G1ET2L_VMT3

S

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(11/16) : SYSTEM PM

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

13 104

0.1

of

5

D D

4

3

R769

1 2

0.01_0603_LE_1%

2

VCCSTG_CPUVCCSTG

1

VCCCPUCORE

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40

AM32

C C

B B

AM33 AM35 AM37 AM38

AK32

AB62

AC63 AE63

AE62 AG62

G30

K32

P62

V62

H63

G61

AL63 AJ62

SKL_ULT

U58L

CPU POWER 1 OF 4

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO_AE62 VCCEOPIO_AG62

VCCEOPIO_SENSE VSSEOPIO_SENSE

KBL_R_U42_BGA1356

@

12 OF 20

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

VCCCPUCORE

VCCSTG_CPU

VCCCPUCORE

12

R9 100_0201_1%

1 2

R781 220_0201_5%

12

R70 100_0201_1%

VCCST

12

R374

56_0201_5%

12

@

R2576

R782

100_0201_5%

VCC_SENSE VSS_SENSE

-SVID_ALERT SVID_CLK SVID_DATA

VCC_SENSE <72> VSS_SENSE <72>

-SVID_ALERT <72> SVID_CLK <72> SVID_DATA <72>

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(12/16) : CPU POWER (1/2)

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

14 104

0.1

of

5

4

3

2

1

VCCP LL VDDQ C VCCP LL_OCVDDQ

R10186

VCCCPUCORE_GT

2

C9572

1

D D

2

C9574

C9573

1

1U_0201_6.3V6-M

2

C9576

C9575

1

1U_0201_6.3V6-M

1 2

0.01_0603_LE_1%

VCCST_CPUVCCSTG_CPU

2

1

2

C2423

1U_0402_6.3V6-K

C2422

1

1U_0402_6.3V6-K

VCC1R2A VCC1R2AVCCST_CPUVCCST

C2424

1U_0402_6.3V6-K

2

C1184

1

2

C1829

1

10U_0402_6.3V6-M

2

C1830

C1831

1

10U_0402_6.3V6-M

2

C840

C9492

1

10U_0402_6.3V6-M

2

22U_0603_6.3V6-M

VCCCPUIO

2

C844

C9493

1

22U_0603_6.3V6-M

2

C842

1

22U_0603_6.3V6-M

VCC1R2A VCC1R2A

2

22U_0603_6.3V6-M

1

C2426

10U_0402_6.3V6-M

2

C2427

1

1U_0402_6.3V6-K

VCCCPUCORE

1 2

R10335 0_0805_0.2mMax_31.6AU42@

VCCGFXCORE_I

1 2

R10336 0_0805_0.2mMax_31.6AU22@

C C

B B

A A

TABLE R10335,R10336 KOA : TLRZ2ATTD VISHAY : WSL080500000ZEA9 TA-I : RLM10JTSR000L YAGEO : PA0805-R-470RL

VCCGFXCORE_I

1 2

R10337 0_0402_5%U22@

VCCGT_SENSE<72> VSSGT_SENSE<72>

VCCGT_SENSE VSSGT_SENSE

VCCCPUCORE_GT

VCCGFXCORE_I

R2152 100_0201_1%

1 2

R2153 100_0201_1%

1 2

VCCGFXCORE_I

U58M

A48

VCCGT_A48

A53

VCCGT_A53

A58

VCCGT_A58

A62

VCCGT_A62

A66

VCCGT_A66

AA63

VCCGT_AA63

AA64

VCCGT_AA64

AA66

VCCGT_AA66

AA67

VCCGT_AA67

AA69

VCCGT_AA69

AA70

VCCGT_AA70

AA71

VCCGT_AA71

AC64

VCCGT_AC64

AC65

VCCGT_AC65

AC66

VCCGT_AC66

AC67

VCCGT_AC67

AC68

VCCGT_AC68

AC69

VCCGT_AC69

AC70

VCCGT_AC70

AC71

VCCGT_AC71

J43

VCCGT_J43

J45

VCCGT_J45

J46

VCCGT_J46

J48

VCCGT_J48

J50

VCCGT_J50

J52

VCCGT_J52

J53

VCCGT_J53

J55

VCCGT_J55

J56

VCCGT_J56

J58

VCCGT_J58

J60

VCCGT_J60

K48

VCCGT_K48

K50

VCCGT_K50

K52

VCCGT_K52

K53

VCCGT_K53

K55

VCCGT_K55

K56

VCCGT_K56

K58

VCCGT_K58

K60

VCCGT_K60

L62

VCCGT_L62

L63

VCCGT_L63

L64

VCCGT_L64

L65

VCCGT_L65

L66

VCCGT_L66

L67

VCCGT_L67

L68

VCCGT_L68

L69

VCCGT_L69

L70

VCCGT_L70

L71

VCCGT_L71

M62

VCCGT_M62

N63

VCCGT_N63

N64

VCCGT_N64

N66

VCCGT_N66

N67

VCCGT_N67

N69

VCCGT_N69

J70

VCCGT_SENSE

J69

VSSGT_SENSE

KBL_R_U42_BGA1356

@

SKL_ULT

CPU POWER 2 OF 4

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71 VCCGT_T62 VCCGT_U65 VCCGT_U68

VCCGT_U71 VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71

VCCGT_Y62

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE VSSGTX_SENSE

13 OF 20

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

VCCGFXCORE_I

VCCCPUCORE

1

VCCSA

2

1

TP953 Test_Point_20MIL

2

1

C9494 10U_0402_6.3V6-M

C9495 10U_0402_6.3V6-M

2

C504

1

VCC1R2A

SKL_ULT

U58N

CPU POWER 3 OF 4

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

VCCST_CPUVCCSTG_CPU

VCCSA

2

1

C9603 10U_0402_6.3V6-M

C9604 10U_0402_6.3V6-M

2

1

C9606 1U_0201_6.3V6-M

C9605 10U_0402_6.3V6-M

C9607 1U_0201_6.3V6-M

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

KBL_R_U42_BGA1356

@

2

1

C9608 1U_0201_6.3V6-M

C9609 1U_0201_6.3V6-M

C9610 1U_0201_6.3V6-M

2

1U_0402_6.3V6-K

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

14 OF 20

C506

1

1U_0402_6.3V6-K

VCCIO_AK28 VCCIO_AK30 VCCIO_AL30

VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

VCCSA_AK23 VCCSA_AK25

VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28 VCCSA_J22 VCCSA_J23 VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

2

C507

1

1U_0402_6.3V6-K

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

Logic

Page 12

Page 18

Page 15

VCCCPUIO

VCCSA

VCCCPUIO

R2291 100_0201_1%

1 2

Ref Des KBL-R U42 KBL-R U22

Y5 R133 R308 C205 C206

Y8 R10339 R10340 C9498 C9499

R10335 R10336 R10337

R2290 100_0201_1%

1 2

NO_ASM NO_ASM NO_ASM NO_ASM NO_ASM

ASM ASM ASM ASM ASM

ASM NO ASM NO ASM

R2155 100_0201_1%

1 2

VCCSA

R2154 100_0201_1%

1 2

ASM ASM ASM ASM ASM

NO_ASM NO_ASM NO_ASM NO_ASM NO_ASM

NO ASM ASM ASM

VSSSA_SENSE VCCSA_SENSE

VSSSA_SENSE <72> VCCSA_SENSE <72>

C505

1

1U_0402_6.3V6-K

Logic

Title

Security Classification

LCFC CONFIDENTION

5

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(13/16) : CPU POWER (2/2)

Size

Document Number R ev

Custom

Date: Sheet

C

Windu-2

Thursday, November 09, 2017

1

15 104

0.1

of

5

VCCMPHY_GATEVCC1R0_SUS

1 2

R10187 0.01_0603_LE_1%

VCC1R0_SUS VCC1R0_SUS_PRIM

1 2

R10221 0.01_0603_LE_1%

VCC1R0_SUS VCCPCHCORE

1 2

D D

R10222 0.01_0603_LE_1%

VCC3M VCC3M_PCH

1 2

R10220 0.01_0603_LE_1%

VCC1R0_SUS VCCMPHY_GATE

4

VCCMPHY_GATE

1

C2433 1U_0402_6.3V6-K

2

1

C2435 1U_0402_6.3V6-K

2

1

C2439 1U_0402_6.3V6-K

2

NEAR K17 NEAR N15 NEAR N18

VCC1R8_SUS

1

2

C2444 1U_0402_6.3V6-K

NEAR AA1

3

VCC3_SUS VCC1R8_SUS VCC1R0_SUS VCC1R0_SUS

1

C2428 47U_0805_6.3V6-M

2

1

C2429 47U_0805_6.3V6-M

2

1

C2430 47U_0805_6.3V6-M

2

1

2

C2431 47U_0805_6.3V6-M

1

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

VCC3_SUS

VCC1R8_SUS

VCC1R0_SUS_PRIM

VCC1R0_SUS

0.1U_0201_6.3V6-K

C795

1 2

1

C763

0.1U_0201_6.3V6-K

2

RTCVCC

1

C731 1U_0402_6.3V6-K

2

VCC3_SUS

1

C380 1U_0402_6.3V6-K

2

1

C503

0.1U_0201_6.3V6-K

2

VCC1R0_SUS_CLK2

1

@

C2450 22U_0603_6.3V6-M

2

VCC1R0_SUS_CLK4

1

@

C2452 22U_0603_6.3V6-M

2

VCC1R0_SUS_CLK5

1

@

C2454 22U_0603_6.3V6-M

2

1

@

C2451 22U_0603_6.3V6-M

2

1

@

C2453 22U_0603_6.3V6-M

2

1

@

C2455 22U_0603_6.3V6-M

2

R10190

1 2

0.01_0603_LE_1%

R10191

1 2

0.01_0603_LE_1%

R10192

1 2

0.01_0603_LE_1%

VCC1R0_SUS

VCC1R0_SUS_PRIM

VCCPCHCORE

AB19 AB20

C C

VCCMPHY_GATE

B B

VCC1R0_SUS

1

C9879

0.1U_0201_6.3V6-K

2

NEAR V15

R10188

1 2

0.01_0603_LE_1%

@

R10189

1 2

0.01_0603_LE_1%

FL77

1 2

MMZ0603AFY560VT_2P

1

@

C2447 22U_0603_6.3V6-M

2

1

2

C2655

0.1U_0201_6.3V6-K

NEAR V15

VCCMPHY_GATE_PLL

1

@

C2446 22U_0603_6.3V6-M

2

VCC1R0_SUS_PLL

VCC3_SUS

NEAR AJ19

1 2

FL75 MMZ0603AFY560VT_2P

1 2

R10338 0_0201_5%@

1

C9496

0.1U_0201_6.3V6-K

2

NEAR AJ19 NEAR AJ19

1

C620 1U_0402_6.3V6-K

2

VCC3M_PCH

1

C9497

0.1U_0201_6.3V6-K

2

VCCMPHY_GATE

AF18 AF19

AB17

AD17 AD18 AJ17

AJ19

AJ16

AF20 AF21

AJ21

AK20

P18

V20 V21

AL1

K17

L1

N15 N16 N17 P15 P16

K15 L15

V15

Y18

T19 T20

N18

SKL_ULT

U58O

CPU POWER 4 OF 4

VCCPRIM_1P0_AB19 VCCPRIM_1P0_AB20 VCCPRIM_1P0_P18

VCCPRIM_CORE_AF18 VCCPRIM_CORE_AF19 VCCPRIM_CORE_V20 VCCPRIM_CORE_V21

DCPDSW_1P0

VCCMPHYAON_1P0_K17 VCCMPHYAON_1P0_L1

VCCMPHYGT_1P0_N15 VCCMPHYGT_1P0_N16 VCCMPHYGT_1P0_N17 VCCMPHYGT_1P0_P15 VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0_K15 VCCAMPHYPLL_1P0_L15

VCCAPLL_1P0

VCCPRIM_1P0_AB17 VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17 VCCDSW_3P3_AD18 VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0_AF20 VCCSRAM_1P0_AF21 VCCSRAM_1P0_T19 VCCSRAM_1P0_T20

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

KBL_R_U42_BGA1356

@

15 OF 20

VCCPGPPA

VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

LCFC CONFIDENTION

5

4

3

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(14/16) : PCH POWER

Size

Document Number Re v

Custom

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

16 104

0.1

of

5

D D

4

3

2

1

APS/PETS Interface

VCC3_SUS VCC3M

-PCH_SLP_S0<13,79>

-XDP_DBR<13,19>

-PWRSWITCH<26,35,64,65>

-RTCRST<12,20>

-PCH_SLP_M<13,65>

-PCH_SLP_S4<13,56,65,80>

-PCH_SLP_S5<13,65>

-PCH_SLP_S3<13,31,56,65,89>

SKL_ULT

U58P

C C

B B

A A

1

TP931Test_Point_16MIL

1

TP932Test_Point_16MIL

1

TP933Test_Point_16MIL

A5

VSS_A5

A67

VSS_A67

A70

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD13

AD16

VSS_AD16

AD19

VSS_AD19

AD20

VSS_AD20

AD21

VSS_AD21

AD62

VSS_AD62

AD8

VSS_AD8

AE64

VSS_AE64

AE65

VSS_AE65

AE66

VSS_AE66

AE67

VSS_AE67

AE68

VSS_AE68

AE69

VSS_AE69

AF1

VSS_AF1

AF10

VSS_AF10

AF15

VSS_AF15

AF17

VSS_AF17

AF2

VSS_AF2

AF4

VSS_AF4

AF63

VSS_AF63

AG16

VSS_AG16

AG17

VSS_AG17

AG18

VSS_AG18

AG19

VSS_AG19

AG20

VSS_AG20

AG21

VSS_AG21

AG71

VSS_AG71

AH13

VSS_AH13

AH6

VSS_AH6

AH63

VSS_AH63

AH64

VSS_AH64

AH67

VSS_AH67

AJ15

VSS_AJ15

AJ18

VSS_AJ18

AJ20

VSS_AJ20

AJ4

VSS_AJ4

AK11

VSS_AK11

AK16

VSS_AK16

AK18

VSS_AK18

AK21

VSS_AK21

AK22

VSS_AK22

AK27

VSS_AK27

AK63

VSS_AK63

AK68

VSS_AK68

AK69

VSS_AK69

AK8

VSS_AK8

AL2

VSS_AL2

AL28

VSS_AL28

AL32

VSS_AL32

AL35

VSS_AL35

AL38

VSS_AL38

AL4

VSS_AL4

AL45

VSS_AL45

AL48

VSS_AL48

AL52

VSS_AL52

AL55

VSS_AL55

AL58

VSS_AL58

AL64

VSS_AL64

KBL_R_U42_BGA1356

@

GND 1 OF 3

16 OF 20

VSS_AL65

VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71

VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63

VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68

VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48

VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63

VSS_AR8

VSS_AT2 VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35

VSS_AT4 VSS_AT42 VSS_AT56 VSS_AT58

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

AT63 AT68 AT71 AU10 AU15 AU20 AU32

1

TP929Test_Point_16MIL

1

TP926Test_Point_16MIL

1

TP934Test_Point_16MIL

1

TP927Test_Point_16MIL

1

TP928Test_Point_16MIL

AU38

AV68 AV69 AV70

AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW60 AW62 AW64 AW66

AY66

BA10

BA14

BA18

BA23

BA28

BA32

BA36

BA45

AV1

AW6

AW8

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1

BA2

F68

U58Q

SKL_ULT

GND 2 OF 3

VSS_AT63 VSS_AT68 VSS_AT71 VSS_AU10 VSS_AU15 VSS_AU20 VSS_AU32 VSS_AU38 VSS_AV1 VSS_AV68 VSS_AV69 VSS_AV70 VSS_AV71 VSS_AW10 VSS_AW12 VSS_AW14 VSS_AW16 VSS_AW18 VSS_AW21 VSS_AW23 VSS_AW26 VSS_AW28 VSS_AW30 VSS_AW32 VSS_AW34 VSS_AW36 VSS_AW38 VSS_AW41 VSS_AW43 VSS_AW45 VSS_AW47 VSS_AW49 VSS_AW51 VSS_AW53 VSS_AW55 VSS_AW57 VSS_AW6 VSS_AW60 VSS_AW62 VSS_AW64 VSS_AW66 VSS_AW8 VSS_AY66 VSS_B10 VSS_B14 VSS_B18 VSS_B22 VSS_B30 VSS_B34 VSS_B39 VSS_B44 VSS_B48 VSS_B53 VSS_B58 VSS_B62 VSS_B66 VSS_B71 VSS_BA1 VSS_BA10 VSS_BA14 VSS_BA18 VSS_BA2 VSS_BA23 VSS_BA28 VSS_BA32 VSS_BA36 VSS_F68 VSS_BA45

17 OF 20

KBL_R_U42_BGA1356

@

VSS_BA49 VSS_BA53 VSS_BA57

VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55

VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70

VSS_C1

VSS_C25

VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58

VSS_D6 VSS_D62 VSS_D66 VSS_D69 VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56

VSS_E6 VSS_E65 VSS_E71

VSS_F1

VSS_F13

VSS_F2

VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38

VSS_F4

VSS_F40 VSS_F42

VSS_BA41

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

1

TP925 Test_Point_16MIL

1

TP924 Test_Point_16MIL

1

TP923 Test_Point_16MIL

1

TP930 Test_Point_16MIL

1

TP935 Test_Point_16MIL

SKL_ULT

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

VSS_K63

K64

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

KBL_R_U42_BGA1356

@

GND 3 OF 3

U58R

18 OF 20

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21

VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13

VSS_R6 VSS_T15 VSS_T17 VSS_T18

VSS_T2 VSS_T21

VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18

VSS_W13

VSS_W6 VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

J41 FCI_10051922-1810ELF

18

NC1

17

NC2

16

NC3

15

SLP_S0#

14

GND1

13

SYS_RESET#

12

GND2

11

PWRBTN#

10

GND3

9

RTCRST#

8

GND4

7

+V3.3DS

6

SLP_A#

5

SLP_S4#

4

SLP_S5#

3

VccDSW3_3

2

SLP_S3#

1

VccSus3_3

@

PEG2 PEG1

20 19

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(15/16) : GND

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

17 104

0.1

of

5

4

3

2

1

TABLE

CFG0 : Stall Reset Sequence

after PCU PLL Lock until de-asserted

1 : No Stall

D D

0 : Stall

CFG3 : MSR Privacy Bit Feature

1 : MSR (C80h) bit[0] setting 0 : MSR (C80h) bit[0] overridden

CFG4 : eDP Enable

1 : Disabled 0 : Enabled

CFG9 : SVID Bus Communication 1 : Enabled 0 : Disabled

U58S

C C

1 2

CFG3<19>

ITP_PMODE<19>

B B

R527 0_0201_5%_SM

1 2

R528 0_0201_5%_SM

12

@

R1892 1K_0201_5%

12

@

R8965

R1891

1K_0201_5%

1 2

R8898 49.9_0201_1%

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

KBL_R_U42_BGA1356

@

SKL_ULT

RESERVED SIGNALS-1

19 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

R2287 0_0201_5%

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71

R2288 0_0201_5%

AR56

AW71 AW70

AP56 C64

1 2

R2289 100K_0201_5%

VCCST

SKL_ULT

U58T

AW69 AW68 AU56 AW48

C7 U12 U11 H11

XTAL24_OUT_U42 XTAL24_IN_U42

12

U42@

R10340 0_0201_5%

XTAL24_OUT_U42_R

1

U42@

C9498 6P_0201_25V8-D

2

Y5 CRYSTAL - 24MHZ 8PF +-30PPM

Vendor P/N TXC

KDS

SPARE

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

KBL_R_U42_BGA1356

@

U42@

1 2

R10339 1M_0201_5%

U42@

Y8 24MHZ_8PF_8Y24080002

1

8Y24080002

1ZZHAE24000CC0D

GND1

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

20 OF 20

3

GND2

2

4

F6 E3 C11 B11 A11 D12 C12 F52

LCFC P/N

SJ10000HI00

SJ10000P200

1

U42@

C9499 6P_0201_25V8-D

2

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(16/16) : CFG/RESERVED

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

18 104

0.1

of

5

D D

C C

XDP_TCK0<6>

PCH_TCK<6> XDP_TMS<6> XDP_TDI<6>

-XDP_TRST<6>

XDP_TDO<6>

-XDP_DBR<13,17>

ITP_PMODE<18>

-RSMRST<13,56>

CFG3<18>

XDP_TCK0

PCH_TCK XDP_TMS XDP_TDI

-XDP_TRST XDP_TDO

-XDP_DBR ITP_PMODE

-RSMRST

4

1 2

R2494 0_0201_5%@

1 2

R531 0_0201_5%_SM

1 2

R594 1K_0201_5%@

-XDP_PRDY<10>

-XDP_PREQ<10>

VCC1R0_SUS VCCSTG VCC1R0_SUSVCC3B

12

@

R588

1.5K_0201_1%

XDP_TCK1

-XDP_PRDY

-XDP_PREQ

12

R491 1K_0201_5%

12

R475 51_0201_5%

3

1

@

C8320

0.1U_0201_6.3V6-K

2

26 25

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

@

JXDP1

26

GND2

25 2424GND1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

MOLEX_52435-2671

2

28 27

TABLE

Logic Page 6 Page 7 Page 18

Page 19

Ref Des

R2

R2559

R1892

JXDP1

C8320

R475

R491

R588

R594

R2494

Merged

ASM ASM ASM ASM ASM ASM ASM ASM ASM ASM ASM

DCI 2.0

NO_ASM NO_ASM NO_ASM NO_ASM

ASM ASM

NO_ASM NO_ASM NO_ASM

1

B B

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

XDP CONNECTOR

Size

Document Number Rev

Custom

C

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

19 104

0.1

of

5

D D

4

3

2

1

VCC3SW

@

R2577

1.5K_0201_1%

1 2

@

R2578 47K_0201_5%

1 2

D3

C C

R4 1K_0201_5%

1 2

JRTC1

@

1

2

3

GND1

4

GND2

HIGHS_WS33020-S0351-HF

B B

12

RB520CM-30T2R_VMN2M2

VCC3SW

D290 RB520CM-30T2R_VMN2M2

1 2

D6 RB520CM-30T2R_VMN2M2

1 2

RTCVCC

R620

1 2

20K_0201_5%

R250

1 2

20K_0201_5%

2

C287 1U_0402_6.3V6-K

@

1

2

C459 1U_0402_6.3V6-K

1

2

C285 1U_0402_6.3V6-K

1

-RTCRST

-SRTCRST

-RTCRST <12,17>

-SRTCRST <12>

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

RTC BATTERY

Size

Document Number Rev

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

20 104

0.1Custom

of

5

D D

4

VCC3_SUS

D12 RB520CM-30T2R_VMN2M2

1 2

VCC3_SUS_SPI

3

2

1

C429

0.1U_0201_6.3V6-K

2

C C

B B

SPI_IO3<7>

SPI_CLK<7,63>

SPI_MOSI_IO0<7,63>

SPI_CLK

1 2

R8981 33_0201_5%

1 2

R681 33_0201_5%EMC@

1 2

R674 33_0201_5%

1

C629

0.1U_0201_6.3V6-K

2

SPI_IO3_0_RSPI_IO3

SPI_CLK_0_R

SPI_MOSI_IO0_0_RSPI_MOSI_IO0

1

EMC@

C575 33P_0201_25V8-J

2

Vendor P/N

WINBOND

MXIC

U49

8

VCC

7

/HOLD/RESET(IO3)

6

CLK

5

DI(IO0)

W25Q128JVSIQ_SO8

1

EMC@

C576 33P_0201_25V8-J

2

TABLE

SF100 PIN HEADER INTERFACE (TOP VIEW)

D12.1

1

VCC

R322.2

3

CS#

R694.2

5

MISO

N/A

7

(KEY)

TABLE of SPI ROM (U49)

W25Q128JVSIQ

MX25L12873FM2I-10

-SPI_CS0_R -SPI_CS0

1

DO(IO1)

/WP(IO2)

GND R681.2 R674.2 N/A

/CS

GND

SPI_MISO_IO1_0_R SPI_MISO_IO1

2

3

4

2

GND

4

CLK

6

MOSI

8

(RESET)

LCFC P/N

SA00008A300

SA00005VM00

1

EMC@

C577 33P_0201_25V8-J

2

1 2

R32233_0201_5%

R69433_0201_5%

SPI_IO2SPI_IO2_0_R

R898033_0201_5%

-SPI_CS0 <7>

SPI_MISO_IO1 <7,63>

SPI_IO2 <7>

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

SPI FLASH

Size

Document Number Rev

Custom

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

21 104

0.1

of

5

4

3

2

1

M_A_DQ[63:0]<4>

-M_A_DQS[7:0]<4>

M_A_DQS[7:0]<4>

M_A_A[16:0]<4>

D D

VCC1R2A VCC1R2A

M_A_DQ5

M_A_DQ1 M_A_DQ4

-M_A_DQS0 M_A_DQS0

M_A_DQ2

M_A_DQ7

M_A_DQ9

M_A_DQ12

M_A_DQ10

M_A_DQ15

M_A_DQ16

M_A_DQ20

-M_A_DQS2

C C

M_A_CKE0<4>

M_A_BG1<4> M_A_BG0<4>

B B

M_A_DQS2

M_A_DQ23

M_A_DQ18

M_A_DQ25

M_A_DQ24

M_A_DQ30

M_A_DQ26

M_A_CKE0

M_A_BG1 M_A_BG0

M_A_A12 M_A_A9

M_A_A8 M_A_A6

JDDR1A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4RB-7H

@

VSS_2

VSS_4

VSS_6

DM0_n/DBl0_n

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15 DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24 VSS_35 DQS3_c

DQS3_t

VSS_38

DQ31 VSS_40

DQ27 VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

DM8_n/DBl8_n/NC

VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

CKE1

VDD_2 ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

2 4

DQ4

6 8

DQ0

10 12 14 16

DQ6

18 20

DQ2

22 24 26 28

DQ8

30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130

M_A_DQ0

M_A_DQ6

M_A_DQ3

M_A_DQ8

M_A_DQ13

-M_A_DQS1 M_A_DQS1

M_A_DQ11

M_A_DQ14

M_A_DQ17

M_A_DQ21

M_A_DQ22

M_A_DQ19

M_A_DQ29

M_A_DQ28

-M_A_DQS3 M_A_DQS3

M_A_DQ31

M_A_DQ27

-DRAMRST M_A_CKE1

-M_A_ACT

-M_A_ALERT

M_A_A11 M_A_A7

M_A_A5 M_A_A4

M_A_CKE1 <4>

-M_A_ACT <4>

-M_A_ALERT <4>

@

C27030.1U_0201_6.3V6-K

2

1

M_A_A1

M_A_DDRCLK0_1066M<4>

-M_A_DDRCLK0_1066M<4>

M_A_PARITY<4>

M_A_BS1<4>

-M_A_CS0<4>

M_A_ODT0<4>

-M_A_CS1<4>

M_A_ODT1<4>

-DRAMRST <5,24>

VCC3BVCC2R5A VCC0R6B

M_A_DDRCLK0_1066M

-M_A_DDRCLK0_1066M

M_A_PARITY

M_A_BS1

-M_A_CS0 M_A_A14

M_A_ODT0

-M_A_CS1

M_A_ODT1

SMB_CLK_3B<24,59,64> SMB_DATA_3B <24,59,64>

VCC1R2A VCC1R2A

JDDR1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

A14/WE_n

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

M_A_DQ37

M_A_DQ32

-M_A_DQS4 M_A_DQS4

M_A_DQ38

M_A_DQ39

M_A_DQ40

M_A_DQ44

M_A_DQ43

M_A_DQ46

M_A_DQ49

M_A_DQ52

-M_A_DQS6 M_A_DQS6

M_A_DQ50

M_A_DQ55

M_A_DQ56

M_A_DQ60

M_A_DQ59

M_A_DQ58

SMB_CLK_3B SMB_DATA_3B

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQS5

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4RB-7H

@

EVENT_n/NF

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41 VSS_67 DQS5_c

DQS5_t

VSS_70

DQ47 VSS_72

DQ43 VSS_74

DQ53 VSS_76

DQ48 VSS_78

DM6_n/DBl6_n

VSS_79

DQ54 VSS_81

DQ50 VSS_83

DQ60 VSS_85

DQ57 VSS_87 DQS7_c

DQS7_t

VSS_90

DQ63 VSS_92

DQ59 VSS_94

GND_2

132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

M_A_A2M_A_A3

M_A_DDRCLK1_1066M

-M_A_DDRCLK1_1066M

M_A_A0

M_A_A10

M_A_BS0 M_A_A16

M_A_A15 M_A_A13

M_A_DQ33

M_A_DQ36

M_A_DQ35

M_A_DQ34

M_A_DQ41

M_A_DQ45

-M_A_DQS5 M_A_DQS5

M_A_DQ42

M_A_DQ47

M_A_DQ48

M_A_DQ53

M_A_DQ54

M_A_DQ51

M_A_DQ57

M_A_DQ61

-M_A_DQS7 M_A_DQS7

M_A_DQ63

M_A_DQ62

M_A_DDRCLK1_1066M <4>

-M_A_DDRCLK1_1066M <4>

M_A_BS0 <4>

SPD ADDRESS: 50H

M_A_VREF_CA

VCC1R2A

2

C9093 47P_0201_25V8-J

RF@

1

VCC2R5A

2

C9094 47P_0201_25V8-J

RF@

1

VCC3B

2

C9095 47P_0201_25V8-J

RF@

1

2

C9104 100P_0201_50V8-J

RF@

1

2

C9105 100P_0201_50V8-J

RF@

1

2

C9106 100P_0201_50V8-J

RF@

1

VCC1R2A

R2583 1K_0201_1%

M_A_VREF_CA

1 2

R2582

M_A_VREF_CA_CPU<4>

A A

1 2

2_0201_1%

2

C2659

0.022U_0402_25V7-K

1

R2581

24.9_0201_1%

1 2

R2584 1K_0201_1%

1 2

2.2U_0402_6.3V6-K

LCFC CONFIDENTION

5

4

VCC3B M_A_VREF_CA VCC2R5A

C2660

2

1

2

C2661

0.1U_0201_6.3V6-K

1

2.2U_0402_6.3V6-K

3

C2662

2

C2663

0.1U_0201_6.3V6-K

@

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

10U_0402_6.3V6-M

2015/11/02

2

C2664

1

LC Future Center Secret Data

2

C2665 1U_0402_6.3V6-K

1

Deciphered Date

2

2015/08/10

Title

DDR4 SO DIMM CHANNEL-A (1/2)

Size

Document Number Rev

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

22 104

0.1Custom

of

5

D D

VCC1R2A

4

3

2

1

2

C2671 1U_0402_6.3V6-K

1

C C

B B

VCC1R2A

2

1

VCC0R6B

2

1

VCC0R6B

2

1

C2684 10U_0402_6.3V6-M

C2697 1U_0402_6.3V6-K

C2701 10U_0402_6.3V6-M

2

C2672 1U_0402_6.3V6-K

1

2

C2685 10U_0402_6.3V6-M

1

2

C2698 1U_0402_6.3V6-K

1

2

C2702 10U_0402_6.3V6-M

1

2

C2673 1U_0402_6.3V6-K

1

2

C2686 10U_0402_6.3V6-M

1

2

C2674 1U_0402_6.3V6-K

1

2

C2687 10U_0402_6.3V6-M

1

2

C2675 1U_0402_6.3V6-K

1

2

C2688 10U_0402_6.3V6-M

1

2

C2676 1U_0402_6.3V6-K

1

2

C2689 10U_0402_6.3V6-M

1

2

C2677 1U_0402_6.3V6-K

1

2

C2690 10U_0402_6.3V6-M

1

2

C2678 1U_0402_6.3V6-K

1

2

C2691 10U_0402_6.3V6-M

1

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

DDR4 SO DIMM CHANNEL-A (2/2)

Size

Document Number Rev

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

23 104

0.1Custom

of

5

4

3

2

1

M_B_DQ[63:0]<5>

-M_B_DQS[7:0]<5>

M_B_DQS[7:0]<5>

M_B_A[16:0]<5>

D D

VCC1R2A VCC1R2A

M_B_DQ13

M_B_DQ12

-M_B_DQS1 M_B_DQS1

M_B_DQ10

M_B_DQ14

M_B_DQ4

M_B_DQ0

M_B_DQ6

M_B_DQ2

M_B_CKE0

M_B_BG1 M_B_BG0

M_B_A12 M_B_A9

M_B_A8 M_B_A6

M_B_DQ21

M_B_DQ16

-M_B_DQS2 M_B_DQS2

M_B_DQ18

M_B_DQ22

M_B_DQ29

M_B_DQ25

M_B_DQ30

M_B_DQ26

C C

M_B_CKE0<5>

M_B_BG1<5> M_B_BG0<5>

B B

JDDR2A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4SB-7H

@

VSS_2

VSS_4

VSS_6

DM0_n/DBIO_n

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15 DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24 VSS_35 DQS3_c

DQS3_t

VSS_38

DQ31 VSS_40

DQ27 VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

DBI8_n VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

CKE1

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

2 4

DQ4

6 8

DQ0

10 12 14 16

DQ6

18 20

DQ2

22 24 26 28

DQ8

30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130

M_B_DQ8

M_B_DQ9

M_B_DQ15

M_B_DQ11

M_B_DQ1

M_B_DQ5

-M_B_DQS0 M_B_DQS0

M_B_DQ3

M_B_DQ7

M_B_DQ20

M_B_DQ17

M_B_DQ23

M_B_DQ19

M_B_DQ28

M_B_DQ24

-M_B_DQS3 M_B_DQS3

M_B_DQ31

M_B_DQ27

M_B_CKE1

-M_B_ACT

-M_B_ALERT

M_B_A11 M_B_A7

M_B_A5 M_B_A4

-DRAMRST

M_B_CKE1 <5>

-M_B_ACT <5>

-M_B_ALERT <5>

M_B_A1

M_B_DDRCLK0_1066M<5>

-M_B_DDRCLK0_1066M<5>

M_B_PARITY<5>

M_B_BS1<5>

-M_B_CS0<5>

M_B_ODT0<5>

-M_B_CS1<5>

M_B_ODT1<5>

-DRAMRST <5,22>

VCC3BVCC2R5A VCC0R6B

SMB_CLK_3B<22,59,64> SMB_DATA_3B <22,59,64>

M_B_DDRCLK0_1066M

-M_B_DDRCLK0_1066M

M_B_PARITY

M_B_BS1

-M_B_CS0 M_B_A14

M_B_ODT0

-M_B_CS1

M_B_ODT1

SMB_CLK_3B SMB_DATA_3B

VCC1R2A VCC1R2A

JDDR2B

131

M_B_DQ37

M_B_DQ33

-M_B_DQS4 M_B_DQS4

M_B_DQ34

M_B_DQ38

M_B_DQ41

M_B_DQ40

M_B_DQ43

M_B_DQ47

M_B_DQ53

M_B_DQ48

-M_B_DQS6 M_B_DQS6

M_B_DQ50

M_B_DQ55

M_B_DQ60

M_B_DQ61

M_B_DQ59

M_B_DQ58

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4SB-7H

@

EVENT_n

VDD_10

CK1_t CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41 VSS_67 DQS5_c DQS5_t VSS_70

DQ47 VSS_72

DQ43 VSS_74

DQ53 VSS_76

DQ48 VSS_78

DM6_n/DBl6_n

VSS_79

DQ54 VSS_81

DQ50 VSS_83

DQ60 VSS_85

DQ57 VSS_87 DQS7_c DQS7_t VSS_90

DQ63 VSS_92

DQ59 VSS_94

GND_2

A2

A0

BA0

A13

RFU

SDA

SA0

Vtt

SA1

132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260

262

M_B_A2M_B_A3

M_B_DDRCLK1_1066M

-M_B_DDRCLK1_1066M

M_B_A0

M_B_A10

M_B_BS0 M_B_A16

M_B_A15 M_B_A13

M_B_DQ36

M_B_DQ32

M_B_DQ35

M_B_DQ39

M_B_DQ45

M_B_DQ44

-M_B_DQS5 M_B_DQS5

M_B_DQ42

M_B_DQ46

M_B_DQ52

M_B_DQ49

M_B_DQ51

M_B_DQ54

M_B_DQ56

M_B_DQ57

-M_B_DQS7 M_B_DQS7

M_B_DQ62

M_B_DQ63

M_B_DDRCLK1_1066M <5>

-M_B_DDRCLK1_1066M <5>

M_B_BS0 <5>

M_B_VREF_CA

SPD ADDRESS: 51H

VCC3B

1 2

R2066 10K_0201_5%

VCC1R2A

2

C9096 47P_0201_25V8-J

RF@

1

VCC2R5A

2

C9097 47P_0201_25V8-J

RF@

1

VCC3B

2

C9098 47P_0201_25V8-J

RF@

1

2

C9107 100P_0201_50V8-J

RF@

1

2

C9108 100P_0201_50V8-J

RF@

1

2

C9109 100P_0201_50V8-J

RF@

1

VCC1R2A

R2069 1K_0201_1%

M_B_VREF_CA

1 2

R2073

M_B_VREF_CA_CPU<4>

A A

1 2

2_0201_1%

2

0.022U_0402_25V7-K C2119

1

R2074

24.9_0201_1%

1 2

R2070 1K_0201_1%

1 2

2.2U_0402_6.3V6-K

LCFC CONFIDENTION

5

4

VCC3B M_B_VREF_CA

2

1

2

C2118

0.1U_0201_6.3V6-K

1

2.2U_0402_6.3V6-K

3

C2117

C2120

2

C2121

0.1U_0201_6.3V6-K

@

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

10U_0402_6.3V6-M

C2122

VCC2R5A

2015/11/02

2

1

2

C2123 1U_0402_6.3V6-K

1

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

DDR4 SO DIMM CHANNEL-B (1/2)

Size

Document Number Rev

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

24 104

0.1Custom

of

5

D D

VCC1R2A

4

3

2

1

2

C2124 1U_0402_6.3V6-K

1

VCC1R2A

2

C C

B B

1

VCC0R6B

2

1

VCC0R6B

2

1

C2132 10U_0402_6.3V6-M

C2140 1U_0402_6.3V6-K

C2144 10U_0402_6.3V6-M

2

C2125 1U_0402_6.3V6-K

1

2

C2133 10U_0402_6.3V6-M

1

2

C2141 1U_0402_6.3V6-K

1

2

C2145 10U_0402_6.3V6-M

1

2

C2126 1U_0402_6.3V6-K

1

2

C2134 10U_0402_6.3V6-M

1

2

C2127 1U_0402_6.3V6-K

1

2

C2135 10U_0402_6.3V6-M

1

2

C2128 1U_0402_6.3V6-K

1

2

C2136 10U_0402_6.3V6-M

1

2

C2129 1U_0402_6.3V6-K

1

2

C2137 10U_0402_6.3V6-M

1

2

C2130 1U_0402_6.3V6-K

1

2

C2138 10U_0402_6.3V6-M

1

2

C2131 1U_0402_6.3V6-K

1

2

C2139 10U_0402_6.3V6-M

1

A A

Title

Security Classification

Issued Date

LCFC CONFIDENTION

5

4

3

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

DDR4 SO DIMM CHANNEL-B (2/2)

Size

Document Number Rev

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

25 104

0.1Custom

of

5

VCC3M VCC3P

5486

72

Q22 TPCF8004_2-3U1S

3

VCC3P_DRV

-LID_CLOSE USBP9USBP9+

PANEL_BKLT_CTRL<3> BACKLIGHT_ON<55>

1

12

R76 100_0201_5%

1

C603

0.1U_0402_25V6-K

2

1 2

D743 RB521CM-30T2R_VMN2M@

1 2

D742 RB521CM-30T2R_VMN2M

1 2

R2078 0_0201_5%_SM

1 2

R2079 0_0201_5%_SM

EDP_AUXN<3> EDP_AUXP<3>

EDP_TXP0<3> EDP_TXN0<3>

EDP_TXP1<3> EDP_TXN1<3>

EDP_TXP2<3> EDP_TXN2<3>

EDP_TXP3<3> EDP_TXN3<3>

EPRIVACY_ON<8>

EDP_HPD<3>

D D

VCC3P_DRV<66>

C C

TOUCH_EN<57>

USBP9-<10> USBP9+<10>

B B

A A

12

R361 47_0201_5%

D63 RB521CM-30T2R_VMN2M

1 2

12

R714 47K_0201_5%

12

R38 100K_0201_5%

PANEL_BKLT_CTRL BACKLIGHT_ON

1 2

C8289 0.1U_0201_6.3V6-K

1 2

C8290 0.1U_0201_6.3V6-K

1 2

C8299 0.1U_0201_6.3V6-K

1 2

C8298 0.1U_0201_6.3V6-K

1 2

C8296 0.1U_0201_6.3V6-K

1 2

C8295 0.1U_0201_6.3V6-K

1 2

C9507 0.1U_0201_6.3V6-K

1 2

C9506 0.1U_0201_6.3V6-K

1 2

C9504 0.1U_0201_6.3V6-K

1 2

C9505 0.1U_0201_6.3V6-K

VCC3LCDVCC3B

12

R668 10K_0201_5%

USBP9+_CONN

C9472 1000P_0201_25V7-KEMC_NS@

C9473 1000P_0201_25V7-KEMC_NS@

C2610 1000P_0201_25V7-KEMC_NS@

1

2

LCFC CONFIDENTION

5

VCC3B

F39

0.5A_32V_ERBRD0R50X

2 1

TOUCH_EN_R

USBP9-_CONN

D311

1

EMC@

1

2

PESD5V0H1BSF_SOD962-2

RF@

1

C9887 47P_0402_50V8-J

2

1

C9886

33P_0402_50V8-J

2

RF@

EDP_AUXN_CONN EDP_AUXP_CONN

EDP_TXP0_CONN EDP_TXN0_CONN

EDP_TXP1_CONN EDP_TXN1_CONN

EDP_TXP2_CONN EDP_TXN2_CONN

EDP_TXP3_CONN EDP_TXN3_CONN

D312

1

EMC@

1

2

PESD5V0H1BSF_SOD962-2

4

1

C311

0.1U_0201_6.3V6-K

2

LCD CONNECTOR

-LID_CLOSE USBP7-_CONN USBP7+_CONN

1

EMC@

C9127 10P_0201_25V8-J

2

@

JLCD1

50

GND4

49

GND3

48

GND2

48

47

GND1

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

I-PEX_20455-050E-02

D91

1

EMC@

1

2

4

1

C315 1U_0402_6.3V6-K

2

54 53 52 51

PESD5V0H1BSF_SOD962-2

1

C308

0.01U_0201_6.3V7-K

2

3

0.9A

F3

VCC3P

21

VBL20

1

RF@

C9101 47P_0201_25V8-J

2

VCC3LCD

1

RF@

C9117 100P_0201_50V8-J

2

3A_32V_ERBRD3R00X

1.2A

1

C307

0.01U_0402_25V7-K

2

USBP7-<10>

USBP7+<10>

D92

1

EMC@

1

USBP4-<10>

USBP4+<10>

2

PESD5V0H1BSF_SOD962-2

1

C310

0.1U_0402_25V6-K

2

-LED_LOGO<55>

-INT_MIC_DTCT<8> MIC_DATA<49> MIC_CLK<49>

-LID_CLOSE<56>

USBP7-

USBP7+

USBP4-

USBP4+

3

1

C313 1U_0603_25V6-K

2

-LED_LOGO

R102 3.9K_0402_5%

MIC_DATA MIC_CLK

1 2

R786 0_0402_5%_SM

L10

EMC_NS@

112

4

3

4

DLW21SN900HQ2L_4P

SM070003100

1 2

R785 0_0402_5%_SM

1 2

R9119 0_0402_5%_SM

L15

EMC_NS@

112

4

3

4

DLW21SN900HQ2L_4P

SM070003100

1 2

R9120 0_0402_5%_SM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

R513 33_0402_5%EMC@ R514 33_0402_5%EMC@

2

3

2

3

1

RF@

C9103 47P_0201_25V8-J

2

1 2 1 2

USBP7-_CONN

USBP7+_CONN

USBP4-_CONN

USBP4+_CONN

2015/11/02

2

1

RF@

C9119 100P_0201_50V8-J

2

1

EMC_NS@

C33

0.1U_0402_25V6-K

2

Power LED Board

-PWRSWITCH<17,35,64,65>

-LED_PWR<55>

LC Future Center Secret Data

Deciphered Date

2

1 2

R8954 100K_0201_5%

EMC@

33P_0201_25V8-J

1

C724

0.01U_0402_25V7-K

2

21

F16

0.5A_32V_ERBRD0R50X

1

C815

2

-PWRSWITCH

-LED_PWR

2012/06/21

F7

21

3A_32V_ERBRD3R00X

21

1

EMC@

C817 33P_0201_25V8-J

2

R13

1

VBL20VSYS

2

C9102 47P_0201_25V8-J

RF@

1

2

C9118 100P_0201_50V8-J

RF@

1

For IR_LED

VCC3BVCC3BVCC3SWVCC3SW VCC3MVCC3SW

21

F26

F24

2

1

0.1U_0201_6.3V6-K

C2578

0.5A_32V_ERBRD0R50X

USBP4-_CONN USBP4+_CONN

USBP7-_CONN USBP7+_CONN

-INT_MIC_DTCT

-LID_CLOSE

1 2

680_0402_1%

AZ5125-02S.R7G_SOT23-3

0.1U_0201_6.3V6-K

C2579

JCAM1

30

29

1A_32V_ERBRD1R00X

29

28

27

26

25

24

23

22

21

2020GND1

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

I-PEX_20525-030E-02

@

VCC3M

2 1

2

3

EMC@

D93

1

Title

LCD/LID/MIC/CAMERA/PWR SW

Size

Document Number Re v

Date: Sheet o f

Windu-2

Thursday, November 09, 2017

1

RF

41

GND11

40

GND10

39

GND9

38

GND8

37

GND7

36

GND6

35

GND5

34

GND4

33

GND3 GND23221

31

F31

0.5A_32V_ERBRD0R50X

JPWR1

1

2

3

4

5

6

7

GND1

8

GND2

HIGHS_FC1AF061-2201H

26 104

0.1Custom

5

D D

C C

4

3

2

1

BLANK

B B

A A

LCFC CONFIDENTION

5

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

LC Future Center Secret Data

Deciphered Date

2

Title

BLANK

Size

Document Number Rev

Custom

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

27 104

0.1

of

5

VCC3B

D D

R105904.7K_0402_5%

R237810K_0201_5%

R237910K_0201_5%

12

@

DDIP2_CTRLCLK<3> DDIP2_CTRLDATA<3>

DDI_PRIORITY1<9>

I2C_DATA_PD

1 2

I2C_DATA_PD<29,33,57>

VCC3B

R10593

1 2

C C

1M_0201_5%

I2C_CLK_PD<29,33,57>

DDIP2_AUXN_C

@

R10686 0_0201_5%

I2C_CLK_PD

R10687 0_0201_5%

1 2

@

12

@

2

1

R106884.7K_0201_5%

C2576

0.1U_0402_10V6-K

DDIP2_0P<3> DDIP2_0N<3> DDIP2_1P<3> DDIP2_1N<3> DDIP2_2P<3> DDIP2_2N<3> DDIP2_3P<3> DDIP2_3N<3>

DDIP2_AUXP<3> DDIP2_AUXN<3>

PS8337B_DP_CFG0

2

C2543

0.1U_0402_10V6-K

1

4

2

C2545 .01U_0402_25V7-K

1

C2522 0.1U_0201_6.3V6-K C2523 0.1U_0201_6.3V6-K C2524 0.1U_0201_6.3V6-K C2525 0.1U_0201_6.3V6-K C2526 0.1U_0201_6.3V6-K C2527 0.1U_0201_6.3V6-K C2528 0.1U_0201_6.3V6-K C2529 0.1U_0201_6.3V6-K

DDIP2_AUXP

C2530 0.1U_0201_6.3V6-K

DDIP2_AUXN

C2531 0.1U_0201_6.3V6-K

USBC_HPD<29,33>

HDMI_HPD_CONN<37>

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

2

1

C2546

0.1U_0402_10V6-K

PS8337B_MODE

USBC_HPD

PS8337B_TMDS_DDCBUF HDMI_HPD_CONN

PS8337B_DP_CFG1

2

C2544

0.01U_0201_6.3V7-K

1

DDIP2_0P_C DDIP2_0N_C DDIP2_1P_C DDIP2_1N_C DDIP2_2P_C DDIP2_2N_C DDIP2_3P_C DDIP2_3N_C

DDIP2_AUXP_C DDIP2_AUXN_C

C25872.2U_0402_6.3V6-K

3

U147

14

VDD33_1

28

VDD33_2

41

VDD33_3

56

VDD33_4

3

IN_D0p

4

IN_D0n

6

IN_D1p

7

IN_D1n

9

IN_D2P

10

IN_D2n

12

IN_D3p

13

IN_D3n

50

IN_DDC_SCL

49

IN_DDC_SDA

45

SW/SDA_CTL

46

PD

52

IN_AUXp

51

IN_AUXn

38

I2C_CTL_EN

53

MODE

1

CEXT

27

REXT

32

DP_HPD

42

DP_CA_DET

2

TMDS_DDCBUF

17

TMDS_HPD

44

DP_CFG0/SCL_CTL

29

DP_CFG1

R25155.6K_0201_1%

R105911M_0201_5%12R1059227K_0201_5%

12

1

2

@

PS8337BQFN56GTR2-A2_QFN56_7X7

IN_CA_DET

DP_D0p DP_D0n DP_D1p DP_D1n DP_D2p DP_D2n DP_D3p DP_D3n

DP_AUXp_SCL DP_AUXn_SDA

TMDS_CLKp TMDS_CLKn

TMDS_CH0p TMDS_CH0n TMDS_CH1p TMDS_CH1n TMDS_CH2p TMDS_CH2n

TMDS_SCL TMDS_SDA

TMDS_PRE

TMDS_RT

PEQ

IN_HPD

GND1 GND2 GND3 EPAD

8

5 11

40 39 37 36 34 33 31 30

55 54

16 15

19 18 22 21 25 24

48 47

20

23

26 35 43 57

PS8337B_PEQ

XBAR_DDIP2_0P XBAR_DDIP2_0N XBAR_DDIP2_1P XBAR_DDIP2_1N XBAR_DDIP2_2P XBAR_DDIP2_2N XBAR_DDIP2_3P XBAR_DDIP2_3N

XBAR_DDIP2_AUXP XBAR_DDIP2_AUXN

HDMI_CLKP HDMI_CLKN

HDMI_DATA0P HDMI_DATA0N HDMI_DATA1P HDMI_DATA1N HDMI_DATA2P HDMI_DATA2N

HDMI_DDC_CLK HDMI_DDC_DATA

PS8337B_TMDS_PRE

PS8337B_TMDS_RT

HDMI_DDC_DATA HDMI_DDC_CLK

DDIP2_HPD USBC_HPD

2

1

2

DDIP2_HPD <3>

XBAR_DDIP2_0P <29> XBAR_DDIP2_0N <29> XBAR_DDIP2_1P <29> XBAR_DDIP2_1N <29> XBAR_DDIP2_2P <29> XBAR_DDIP2_2N <29> XBAR_DDIP2_3P <29> XBAR_DDIP2_3N <29>

HDMI_CLKP <37> HDMI_CLKN <37>

HDMI_DATA0P <37> HDMI_DATA0N <37> HDMI_DATA1P <37> HDMI_DATA1N <37> HDMI_DATA2P <37> HDMI_DATA2N <37>

HDMI_DDC_CLK <37> HDMI_DDC_DATA <37>

EMC_NS@

C2729 47P_0201_25V8-J

1 1

@

EMC_NS@

2

C2730 47P_0201_25V8-J

1

TP949Test_Point_20MIL TP950Test_Point_20MIL

VCC3B

@

R10440 100K_0201_5%

1 2

XBAR_DDIP2_AUXP <29> XBAR_DDIP2_AUXN <29>

@

R10441 100K_0201_5%

1 2

TABLE: Automat ic S wit chi ng Mode ( MODE= H, M)

SW(DDI_PRIORITY1)

DP Port has higher priority when both ports are plugged

L

TMDS Port has higher priority when both ports are pulgged

H

DEFAULT

B B

A A

MODE =

H : Automatic Switching mode,HDMI ID Disabled

M : Automatic Switching mode,HDMI ID Enable

L : Control Switching mode,HDMI ID Disabled

d

DEFAULT

LCFC CONFIDENTION

5

4

VCC3B

1 2

R2531 4.7K_0402_5%

1 2

R2523 4.7K_0402_5%

1 2

R2527 4.7K_0402_5%

1 2

R2529 4.7K_0402_5%

1 2

R146 4.7K_0402_5%

1 2

R2561 4.7K_0402_5%

1 2

R1877 4.7K_0402_5%@

PS8337B_DP_CFG0

@

PS8337B_DP_CFG1

PS8337B_MODE

PS8337B_TMDS_RT

PS8337B_PEQ

PS8337B_TMDS_PRE

PS8337B_TMDS_DDCBUF

3

1 2

R10610 4.7K_0402_5%

@

1 2

R2524 4.7K_0402_5%

1 2

R2528 4.7K_0402_5%

1 2

R147 4.7K_0402_5%

@

1 2

R2562 4.7K_0402_5%

@

1 2

R1899 4.7K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

DDI DEMUX/HDMI LEVEL SHIFTE

Size

Document Number Rev

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

28 104

0.1Custom

of

5

4

3

2

1

VCC3_SUS VCC3_PS8747

R10349

1 2

0.01_0603_LE_1%

D D

XBAR_DDIP2_0P<28> XBAR_DDIP2_0N<28> XBAR_DDIP2_3P<28> XBAR_DDIP2_3N<28>

USB3P3_RXP_XBAR<10> USB3P3_RXN_XBAR<10>

C C

USB3P3_TXP_XBAR<10> USB3P3_TXN_XBAR<10>

XBAR_DDIP2_2P<28> XBAR_DDIP2_2N<28> XBAR_DDIP2_1P<28> XBAR_DDIP2_1N<28>

XBAR_DDIP2_AUXP<28> XBAR_DDIP2_AUXN<28>

I2C_CLK_PD<28,33,57> I2C_DATA_PD<28,33,57>

I2C_CLK_TBT<31,33> I2C_DATA_TBT<31,33>

2

C9527

0.1U_0201_6.3V6-K

1

2

C9526

0.1U_0201_6.3V6-K

1

1 2

C9508 0.1U_0201_6.3V6-K

1 2

C9509 0.1U_0201_6.3V6-K

1 2

C9510 0.1U_0201_6.3V6-K

1 2

C9511 0.1U_0201_6.3V6-K

1 2

C9512 0.1U_0201_6.3V6-K

1 2

C9513 0.1U_0201_6.3V6-K

1 2

C9515 0.1U_0201_6.3V6-K

1 2

C9514 0.1U_0201_6.3V6-K

1 2

C9516 0.1U_0201_6.3V6-K

1 2

C9517 0.1U_0201_6.3V6-K

1 2

C9519 0.1U_0201_6.3V6-K

1 2

C9518 0.1U_0201_6.3V6-K

1 2

R10611 0_0201_5%_SM

1 2

R10612 0_0201_5%_SM

1 2

R10448 0_0201_5%@

1 2

R10449 0_0201_5%@

1 2

R10446 0_0201_5%@

1 2

R10447 0_0201_5%@

2

C9525

0.1U_0201_6.3V6-K

1

2

C9524

0.1U_0201_6.3V6-K

1

XBAR_DDIP2_0P_C XBAR_DDIP2_0N_C XBAR_DDIP2_3P_C XBAR_DDIP2_3N_C

PS8747_SSDE PS8747_CDE

USB3P3_RXP_XBAR_C USB3P3_RXN_XBAR_C USB3P3_TXP_XBAR_C USB3P3_TXN_XBAR_C

XBAR_DDIP2_2P_C XBAR_DDIP2_2N_C XBAR_DDIP2_1P_C XBAR_DDIP2_1N_C

XBAR_DDIP2_AUXP_C XBAR_DDIP2_AUXN_C

PS8747_I2C_CTL PS8747_DCICFG_ADDR

PS8747_DPEQ_SCL PS8747_CEQ_SDA

R10348

4.99K_0201_1%

1 2

2

C9523

0.1U_0201_6.3V6-K

1

U197

9

ML0P

10

ML0N

18

ML3P

19

ML3N

11

SSDE/DCI_DATA

14

CDE/DCI_CLK

5

SSRXP

4

SSRXN

8

SSTXP

7

SSTXN

15

ML2P

16

ML2N

12

ML1P

13

ML1N

24

AUXP

25

AUXN

29

I2C_EN

3

DCICFG/ADDR

21

DPEQ/CSCL

22

CEQ/CSDA

2

PS8747BQFN40GTR-B1_QFN40_6X4

REXT

VCC3_PS8747

28

VDD33_16VDD33_220VDD33_3

41

EPAD

17

VDD_DCI

RX1P RX1N RX2P RX2N

TX1P

TX1N

TX2P

TX2N

CEXT

CE_DP

CE_USB

FLIP SBU1 SBU2

IN_HPD

30 31 40 39

33 34 37 36

1 23 35 38 27 26 32

2

C9528

0.01U_0201_6.3V7-K

1

2

C9522

2.2U_0402_6.3V6-K

1

2

C9529

0.01U_0201_6.3V7-K

1

2

C9530

0.01U_0201_6.3V7-K

1

USBC_RX1P <36> USBC_RX1N <36> USBC_RX2P <36> USBC_RX2N <36>

USBC_TX1P <36> USBC_TX1N <36> USBC_TX2P <36> USBC_TX2N <36>

USBC_DP_MODE <33> USBC_USB_MODE <33> USBC_POL <33> USBC_SBU1 <36> USBC_SBU2 <36> USBC_HPD <28,33>

B B

A A

VCC3_SUS

1 2

R10613 100K_0201_1%

1 2

R10614 100K_0201_1%

LCFC CONFIDENTION

5

XBAR_DDIP2_AUXN_C

XBAR_DDIP2_AUXP_C

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

VCC3_SUS

R10363 4.7K_0402_5%

R10354 4.7K_0402_5%

R10356 4.7K_0402_5%@

R10355 4.7K_0402_5%

R10357 4.7K_0402_5%

R10364 4.7K_0402_5%

R10443 20K_0201_5%

LC Future Center Secret Data

1 2

@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

Deciphered Date

PS8747_DPEQ_SCL

PS8747_CEQ_SDA

PS8747_I2C_CTL

PS8747_DCICFG_ADDR

PS8747_SSDE

PS8747_CDE

USBC_USB_MODE

2

1 2

R10362 4.7K_0402_5%@

1 2

R10353 4.7K_0402_5%@

1 2

R10359 4.7K_0402_5%

1 2

R10442 4.7K_0402_5%@

Title

USB TYPE-C SWITCH

Size

Document Number R ev

Custom

Thursday, November 09, 2017

Date : Sheet

Windu-2

29 104

1

0.1

of

5

D D

C C

4

3

2

1

BLANK

B B

A A

LCFC CONFIDENTION

5

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

LC Future Center Secret Data

Deciphered Date

2

Title

BLANK

Size

Document Number Rev

Custom

Date: Sheet

Windu-2

Thursday, November 09, 2017

1

30 104

0.1

of

Lenovo ThinkPad T480 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual