Lenovo THINKPAD T470 Schematics

5

T470P

D D

Docking CS13

60

LAN RJ45 CONN

C C

B B

AUDIO BOARD HDMI BOARD USB BOARD AUDIO CONN LID SW

A A

DOCK MDI SYS MDI

T460P MAIN BOARD

BTB BTB WTB

POWER BOTTON POWER LED PS8407 HDMI CONN

5

DDI3 GPP I2S USB2.0&USB3.0

LAN SWITCH PI3L720ZHEX

SPK Conn.

AUDIO Conn

AUDIO BOARD

SP_OUTL

50

SLEEVE/RING

47

USB CHARGE TPS2546RTER

USB CONN

mDP

5253

I2S

4

eDP CONN 14" FHD/WQHD

HDMI Conn

HDMI BOARD

PS8330 REPEATERmDP Conn.

LAN Intel WGI219LM Vpro

NGFF Card WLAN vPro+non-vPro M.2

NGFF CARD WWAN

Codec ALC3268

Cardreader RTS5232S-GR

SATA HDD SATA HDD

SPI ROM 8+8 RTC BATTERY

45,46,48,49

TPM

4

56

57

5859

51

62

54

61

55

eDPx4

DDI1

DDI2

DDI3 GPP

PCIE Gen1 X1MDI

PCIE Gen1 X2 USB2.0

PCIE Gen3 X2 USB2.0 SATA

HDA AUDIO

USB2.0&USB3.0

PCIE Gen1 X1

SPI

Lenovo ASIC ThinkEngine

40,41

POWER BOTTON

67

3

CPU Intel

Kabylake_H

BGA1440

35W

3,4,5,6,7,8,9, 10,11,12,13

DMI X4

PCH

Intel

Skylake-QM170

DDR 2166

PEG X4

PROC XDP CONN

USB2.0&USB3.0

vPro

USB2.0

14,15,16,17,18 19,20,21,22,23

LPC BUS

Embedded Controller MEC1653L

42,43,44

FAN KEYBOARD

TRACK POINT CONN

65 66 67

3

I2C

USB2.0

RTCRST

G-Sensor

55

Click Pad

UNBUFFERED DDR4 SO-DIMMA1 Channel A

UNBUFFERED DDR4 SO-DIMMB1 Channel B

nVidia GPU N16S-GTR

31-39

USB3.0 CONN USB1&USB2

USB3.0 CONN USB3

USB BOARD

USB2.0 Camera

USB2.0 Smart Card Slot

USB2.0 Fingerprint

USB2.0 Touch Panel

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2015/07/16

2

27

28

GDDR5 VRAM 256X32 2GB

24

63

64

56

65

67

56

2526

LC Future Center Secret Data

2

37

Deciphered Date

1

Page:03~13==>CPU KBL-H Page:14~23==>PCH SKL-H Page:24=====>XDP CONNECTOR Page:25=====>RTC BATTERY Page:26=====>SPI FLASH Page:27~28==>DDR4 MEMORY Page:29==>Intel ME debug port Page:31~36==>N16S-GTR Page:37==>GDDR5 VRAM Page:40~41==>THINK ENGINE Page:42~44==>MEC1653L Page:45~50==>AUDIO ALC3268-CG Page:51~53==>LAN WGI219LM Page:54=====>CARD_READER RTS5232S-GR Page:55=====>THERMAL SENSOR/G SENSOR/TPM Page:56=====>eDP/CMOS/LOGO-LED CONN. Page:57=====>HDMI BTB CONN. Page:58=====>PS8330B REPEATER DP Page:59=====>MINI-DP CONN. Page:60=====>CS13 DOCKING CONN. Page:61=====>SATA HDD CONN. Page:62=====>WLAN/WWAN/SIM CONN. Page:63=====>USB3 P1/2 CONN. Page:64=====>USB3 P3 CONN. Page:65=====>FAN/SC CONN Page:66=====>KEYBOARD/TRACK POINT CONN Page:67=====>Click Pad/FPR/PBTN Page:68=====>SMBUS SWITCH/LPC DEBUG PORT Page:69=====>EMC solution for BDW ESD Page:70=====>LOAD SW VCCST/VCCSTG Page:71=====>LOAD SW LOAD SW PCH SUS/TRA Page:72=====>LOAD SW LAN Page:73=====>LOAD SW B Page:74=====>LOAD SW WWAN&WLAN Page:75=====>LOAD SW HDMI/CODEC Page:76=====>DISCHARGE CIRCUIT VIDEO Page:79=====>SCREW HOLE Page:80=====>DC-IN Page:81=====>BATTERY INPUT Page:82=====>BATTERY CHARGER(BQ24780S) Page:83=====>DC/DC VCC5M/VCC3M Page:84=====>DC/DC IMVP8 Page:85=====>DC/DC VCCPUCORE Page:86=====>DC/DC VCCGFXCORE_I Page:87=====>DC/DC VCCSA Page:88=====>CPU PROCESSOR DECOUPLING Page:89=====>DC/DC VCCCPUIO Page:90=====>DC/DC VCC1R0_SUS Page:91=====>DC/DC VCC1R2A/VCC0R6B Page:92=====>DC/DC VCC2R5A Page:93=====>DC/DC GFXCORE_D Page:94=====>DC/DC VCC1R5VIDEO Page:95=====>DC/DC VCC1R05VIDEO_PLL

Title

2016/01/16

Title

TITLE PAGE

Size Document Number Re v

Custom

Wednesday, October 12, 2016

Date: Sheet of

1

NM-B071

1 99

0.2

NMB071_T470P_SVT_1114_for SMT

5

4

3

2

1

TABLE: SYSTEM POWER STATE

Gx State (System State)

D D

G0 S0 M0

G1

G2

G3 --- --- OFF OFF OFF OFF OFF OFF

Schematics Mark Definition

C C

Sx State (System State)

Mx State (System State)SWPowerMPower

SUS

AMT

Power

PowerAPowerBPower

ON ON ON ON ON ON

S3

M3 M-OFF

ON ON ON ON ON OFF ON ON ON OFF ON OFF

Deep S3 M-OFF ON ON OFF OFF ON OFF S4 M3 ON ON ON ON OFFOFF Deep S4 M-OFF ON ON ONOFF OFF OFF S5 Deep S5 S5 EC OFF

M3 M-OFF M-OFF

ONONON ON

ON

OFF OFF OFF OFF OFF

ON

OFF OFFON ON

User Observation Chipset

System Operating Standby Standby

with USB wake enabled Standby

Hibernation with RTC wakeup

Hibernation or Shutdown

OFFOFFOFF

No Power

Full On

Suspend-to-RAM (STR)

Suspend-to-Disk (STD)

Soft Off

Mechanical Off

Device

Smart Battery

Address

0001 011X b

EC SMBus2 address

Device

Charge Controller

Address

0001 0010

PCH SM Bus address

CH-A CH-B

Device

DDR DIMM1 DDR DIMM2

Address

1001 0000b 1001 0010b

EC SMBus0 address

EC SMBus1 address

Device

G-Senor (LIS3DH) G-Senor (KX023)

Address

0011 000Xb 0011 110Xb

EC SMBus10 address

Device

Master VGA

Address

0x9E

PCH SM Bus0 address

Device

Intel Lan_I219

Address

0XC8

BOM Structure Table

BOM Structure

DEBUG@ For EE DEBUG DPRE@ DP re-driver function NODPRE@ Disable DP re-driver

For GC6 functionGC6@

NGC6@ NON GC6 function

Capacitor Naming Note

B B

A A

Ceramic Capacitors:

0.1U_0402_6.3VXX

Tolera nc e Temperature Characteristics Rated Voltage Package Size

Temperature Characteristics:

Symbol

Code Z5VZ5U Y5UZ5P Y5PY5V

B

0 1 32 54 76 98 A

X5R NPOX7R X6SCOG

C FED HG KJI

CJCHBJ SJSHCK UJ X5SSLUK

L

NOJ

Tolerance:

Symbol

A B DC GF JH MK N

+-0.05PF

+-0.25PF+-0.1PF +-1%+-0.5PF

+-2% +-3%Tolerance +-10%+-5% +-30%+-20%

NMB071_T470P_SVT_1114_for SMT

Symbol P Q ZXV YS

+30,-10%+100,-0%Tolerance

5

+40,-20%+20,-10% +50,-20%+80,-20%

ZZZ1

PCB@

DT473

DAZ13700100

SR32S@

CL8067702870309 SR32S

SA000087220

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

-30% ~ 10%

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

UL5101

NVPRO@

S IC WGI219V SLKJ4 A0 QFN LAN PHY 01!

SA000072Z10

UC1

SR32R@UC1

CL8067702870214 SR32R

SA000087110

2015/07/16

3

LC Future Center Secret Data

Deciphered Date

ME@ ME Connector

For EMI SolutionEMC@ RF@ For RF Solution VSE2G@ VME2G@ VHC2G@ X76_VSE2G@ X76_VME2G@ X76_VHC2G@

For SAMSUNG VRAM Setting

For Micron VRAM Setting

For RF HYNIX VRAM Setting

K4W4G1646E-BC1A x4 + 24.9K

MT41J256M16HA-093G x4 +10k

H5TC4G63CFR-N0C x4 +30.1k CS@ For CURRENT SENSE UMA@ DIS@

For UMA

For DIS UC1@ For CPU

Title

EC HISTORY

Size Document Number Re v

Custom

Date: Sheet of

2

2016/01/16

NOTE

Wednesday, November 09, 2016

1

NM-B071

2 99

0.2

5

4

3

2

1

D D

M_A_DQ[0..63][27]

C C

B B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

UC1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CLKP[2]

DDR0_CLKN[2]

DDR0_CLKP[3]

DDR0_CLKN[3]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_CS#[2] DDR0_CS#[3]

DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

DDR0_DQSP[0] DDR0_DQSP[1]

DDR0_DQSP[8] DDR0_DQSN[8]

AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3 BG3 BD3 AB3 V3 R3 M3

BP5 BK3 BF3 BC3 AA3 U3 P3 L3

AY3 BA3

M_A_DDRCLK0_1066M

-M_A_DDRCLK0_1066M

-M_A_DDRCLK1_1066M M_A_DDRCLK1_1066M

M_A_CKE0 M_A_CKE1

-M_A_CS0

-M_A_CS1

M_A_ODT0 M_A_ODT1

M_A_BA0 M_A_BA1 M_A_BG0

M_A_A16_RAS_N M_A_A14_WE_N M_A_A15_CAS_N

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10_AP M_A_A11 M_A_A12 M_A_A13 M_A_BG1

-M_A_ACT M_A_PARITY

-M_A_ALERT

-M_A_DQS0

-M_A_DQS1

-M_A_DQS2

-M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3

-M_A_DQS4

-M_A_DQS5

-M_A_DQS6

-M_A_DQS7

M_A_DDRCLK0_1066M [27]

-M_A_DDRCLK0_1066M [27]

-M_A_DDRCLK1_1066M [27] M_A_DDRCLK1_1066M [27]

M_A_CKE0 [27] M_A_CKE1 [27]

-M_A_CS0 [27]

-M_A_CS1 [27]

M_A_ODT0 [27] M_A_ODT1 [27]

M_A_BA0 [27] M_A_BA1 [27] M_A_BG0 [27]

M_A_A16_RAS_N [27] M_A_A14_WE_N [27] M_A_A15_CAS_N [27]

M_A_A10_AP [27] M_A_A11 [27] M_A_A12 [27] M_A_A13 [27] M_A_BG1 [27]

-M_A_ACT [27] M_A_PARITY [27]

-M_A_ALERT [27]

-M_A_DQS[0..7] [27] M_A_DQS[0..7] [27]

M_A_A[0..9] [27]

DDR CHANNEL

A

KABYLAKE-H-CPU_BGA1440

SR32Q@

A A

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

Issued Date

1 OF 14

DDR4 INTERLEAVE IMPLEMENTATION

Title

LC Future Center Secret Data

Deciphered Date

2015/07/16

3

Deciphered Date

2

2016/01/16

Title

CPU KBL-H : DDR4 CH-A

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, November 08, 2016

NM-B071

1

3 99

0.2

5

4

3

2

1

D D

M_B_DQ[0..63][28]

C C

B B

RC0301 121_0402_1% RC0302 75_0402_1% RC0303 100_0402_1%

12 12 12

PLACE CLOSE TO CPU

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

UC1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

KABYLAKE-H-CPU_BGA1440

DDR CHANNEL B

SKYLAKE_HAL O

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_CS#[2]

DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11

AT8 AT10 AT7 AT11

AF11 AE7 AF10 AE10

AF7 AE8 AE9 AE11

AH10 AH11 AF8

AH8 AH9 AR9

AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9

AJ7 AR8

BP9 BL9 BG9 BC9 AC9 W9 R9 M9

BR9 BJ9 BF9 BB9 AA9 V9 P9 L9

AW9 AY9

BN13 BP13 BR13

M_B_DDRCLK0_1066M

-M_B_DDRCLK0_1066M

-M_B_DDRCLK1_1066M M_B_DDRCLK1_1066M

M_B_CKE0 M_B_CKE1

-M_B_CS0

-M_B_CS1

M_B_ODT0 M_B_ODT1

M_B_A16_RAS_N M_B_A14_WE_N M_B_A15_CAS_N

M_B_BA0 M_B_BA1 M_B_BG0

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10_AP M_B_A11 M_B_A12 M_B_A13 M_B_BG1

-M_B_ACT M_B_PARITY

-M_B_ALERT

-M_B_DQS0

-M_B_DQS1

-M_B_DQS2

-M_B_DQS3

-M_B_DQS4

-M_B_DQS5

-M_B_DQS6

-M_B_DQS7 M_B_DQS0

M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_A_VREF_CA_CPU M_B_VREF_DQ_CPU

M_B_DDRCLK0_1066M [28]

-M_B_DDRCLK0_1066M [28]

-M_B_DDRCLK1_1066M [28] M_B_DDRCLK1_1066M [28]

M_B_CKE0 [28] M_B_CKE1 [28]

-M_B_CS0 [28]

-M_B_CS1 [28]

M_B_ODT0 [28] M_B_ODT1 [28]

M_B_A16_RAS_N [28] M_B_A14_WE_N [28] M_B_A15_CAS_N [28]

M_B_BA0 [28] M_B_BA1 [28] M_B_BG0 [28]

M_B_A10_AP [28] M_B_A11 [28] M_B_A12 [28] M_B_A13 [28] M_B_BG1 [28]

-M_B_ACT [28] M_B_PARITY [28]

-M_B_ALERT [28]

M_A_VREF_CA_CPU [27] M_B_VREF_DQ_CPU [28]

M_B_A[0..9] [28]

-M_B_DQS[0..7] [28]

M_B_DQS[0..7] [28]

DDR_VREF_CA : Connected to VREF_CA on DIMM CH-A DDR0_VREF_DQ : NC

A A

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

DDR1_VREF_DQ : Connected to VREF_CA on DIMM CH-B

Title

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

CPU KBL-H : DDR4 CH-B

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, November 08, 2016

NM-B071

1

4 99

0.2

5

www.vinaﬁx.com

PEG_RXP[3:0][31] PEG_RXN[3:0][31]

PEG_RXP3 PEG_RXN3

PEG_RXP2 PEG_RXN2

PEG_RXP1

RC0501

24.9_0402_1%

1 2

PEG_RXN1 PEG_RXP0

PEG_RXN0

D D

C C

VCCCPUIO

4

PEG_COMP_W12mil

E25 D25

E24 F24

E23 D23

E22 F22

E21 D21

E20 F20

E19 D19

E18 F18

D17 E17

F16 E16

D15 E15

F14 E14

D13 E13

F12 E12

D11 E11

F10 E10

G2

UC1C

PEG_RXP[0] PEG_RXN[0]

PEG_RXP[1] PEG_RXN[1]

PEG_RXP[2] PEG_RXN[2]

PEG_RXP[3] PEG_RXN[3]

PEG_RXP[4] PEG_RXN[4]

PEG_RXP[5] PEG_RXN[5]

PEG_RXP[6] PEG_RXN[6]

PEG_RXP[7] PEG_RXN[7]

PEG_RXP[8] PEG_RXN[8]

PEG_RXP[9] PEG_RXN[9]

PEG_RXP[10] PEG_RXN[10]

PEG_RXP[11] PEG_RXN[11]

PEG_RXP[12] PEG_RXN[12]

PEG_RXP[13] PEG_RXN[13]

PEG_RXP[14] PEG_RXN[14]

PEG_RXP[15] PEG_RXN[15]

PEG_RCOMP

SKYLAKE_HAL O

BGA1440

PEG_TXP[0] PEG_TXN[0]

PEG_TXP[1] PEG_TXN[1]

PEG_TXP[2] PEG_TXN[2]

PEG_TXP[3] PEG_TXN[3]

PEG_TXP[4] PEG_TXN[4]

PEG_TXP[5] PEG_TXN[5]

PEG_TXP[6] PEG_TXN[6]

PEG_TXP[7] PEG_TXN[7]

PEG_TXP[8] PEG_TXN[8]

PEG_TXP[9] PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

3

PEG_TXP3_C

B25

PEG_TXN3_C

A25

PEG_TXP2_C

B24

PEG_TXN2_C

C24

PEG_TXP1_C

B23

PEG_TXN1_C

A23

PEG_TXP0_C

B22

PEG_TXN0_C

C22 B21

A21 B20

C20 B19

A19 B18

C18 A17

B17 C16

B16 A15

B15 C14

B14 A13

B13 C12

B12 A11

B11 C10

B10

1 2

C10104 0.22U_0201_6.3V6-KDIS@

1 2

C9057 0.22U_0201_6.3V6-KDIS@

1 2

C9055 0.22U_0201_6.3V6-KDIS@

1 2

C9058 0.22U_0201_6.3V6-KDIS@

1 2

C9054 0.22U_0201_6.3V6-KDIS@

1 2

C9059 0.22U_0201_6.3V6-KDIS@

1 2

C9053 0.22U_0201_6.3V6-KDIS@

1 2

C9060 0.22U_0201_6.3V6-KDIS@

PEG_TXP3 PEG_TXN3

PEG_TXP2 PEG_TXN2

PEG_TXP1 PEG_TXN1

PEG_TXP0 PEG_TXN0

2

PEG_TXP[3:0] [31] PEG_TXN[3:0] [31]

1

DMI_TXP0[15] DMI_TXN0[15]

DMI_TXP1[15] DMI_TXN1[15]

DMI_TXP2[15] DMI_TXN2[15]

DMI_TXP3[15] DMI_TXN3[15]

B B

A A

DMI_TXP0 DMI_TXN0

DMI_TXP1 DMI_TXN1

DMI_TXP2 DMI_TXN2

DMI_TXP3 DMI_TXN3

D8

DMI_RXP[0]

E8

DMI_RXN[0]

E6

DMI_RXP[1]

F6

DMI_RXN[1]

D5

DMI_RXP[2]

E5

DMI_RXN[2]

J8

DMI_RXP[3]

J9

DMI_RXN[3]

KABYLAKE-H-CPU_BGA1440

3 OF 14

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2] DMI_TXN[2]

DMI_TXP[3] DMI_TXN[3]

B8 A8

C6 B6

B5 A5

D4 B4

NMB071_T470P_SVT_1114_for SMT

5

4

DMI_RXP0 DMI_RXN0

DMI_RXP1 DMI_RXN1

DMI_RXP2 DMI_RXN2

DMI_RXP3 DMI_RXN3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

DMI_RXP0 [15] DMI_RXN0 [15]

DMI_RXP1 [15] DMI_RXN1 [15]

DMI_RXP2 [15] DMI_RXN2 [15]

DMI_RXP3 [15] DMI_RXN3 [15]

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

CPU KBL-H : PEG/DMI

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, November 08, 2016

NM-B071

1

5 99

0.2

5

D D

4

3

2

1

HDMI_DDIP1_2P[57] HDMI_DDIP1_2N[57] HDMI_DDIP1_1P[57] HDMI_DDIP1_1N[57]

HDMI PORT

C C

mDP PORT

DOCKING PORT

B B

HDMI_DDIP1_0P[57] HDMI_DDIP1_0N[57] HDMI_DDIP1_CLK_DP[57] HDMI_DDIP1_CLK_DN[57]

MDP_DDI2_P0[58] MDP_DDI2_N0[58] MDP_DDI2_P1[58] MDP_DDI2_N1[58] MDP_DDI2_P2[58] MDP_DDI2_N2[58] MDP_DDI2_P3[58] MDP_DDI2_N3[58]

MDP_DDIP2_AUXP[58]

MDP_DDIP2_AUXN[58] DOCK_DDIP3_0P[60]

DOCK_DDIP3_0N[60]

DOCK_DDIP3_1P[60]

DOCK_DDIP3_1N[60]

DOCK_DDIP3_2P[60]

DOCK_DDIP3_2N[60]

DOCK_DDIP3_3P[60]

DOCK_DDIP3_3N[60] DOCK_DDIP3_AUXP[60]

DOCK_DDIP3_AUXN[60]

HDMI_DDIP1_2P HDMI_DDIP1_2N HDMI_DDIP1_1P HDMI_DDIP1_1N HDMI_DDIP1_0P HDMI_DDIP1_0N HDMI_DDIP1_CLK_DP HDMI_DDIP1_CLK_DN

MDP_DDI2_P0 MDP_DDI2_N0 MDP_DDI2_P1 MDP_DDI2_N1 MDP_DDI2_P2 MDP_DDI2_N2 MDP_DDI2_P3 MDP_DDI2_N3

MDP_DDIP2_AUXP MDP_DDIP2_AUXN

DOCK_DDIP3_0P DOCK_DDIP3_0N DOCK_DDIP3_1P DOCK_DDIP3_1N DOCK_DDIP3_2P DOCK_DDIP3_2N DOCK_DDIP3_3P DOCK_DDIP3_3N

DOCK_DDIP3_AUXP DOCK_DDIP3_AUXN

UC1D

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

KABYLAKE-H-CPU_BGA1440

SKYLAKE_HAL O

BGA1440

4 OF 14

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

CPU_EDP_TX0+

D29

CPU_EDP_TX0-

E29

CPU_EDP_TX1+

F28

CPU_EDP_TX1-

E28

CPU_EDP_TX2-

B29

CPU_EDP_TX2+

A29

CPU_EDP_TX3-

B28

CPU_EDP_TX3+

C28

CPU_EDP_AUX

C26

CPU_EDP_AUX#

B26

A33

Leave EDP_DISP_UTIL NC

EDP_RCOMP_W12mil

D37

PROC_AUDIO_CLK_CPU

G27

PROC_AUDIO_SDO_CPU

G25

PROC_AUDIO_SDI_CPU_R

G29

CPU_EDP_TX0+ [56] CPU_EDP_TX0- [56] CPU_EDP_TX1+ [56] CPU_EDP_TX1- [56] CPU_EDP_TX2- [56] CPU_EDP_TX2+ [56] CPU_EDP_TX3- [56] CPU_EDP_TX3+ [56]

CPU_EDP_AUX [56] CPU_EDP_AUX# [56]

1 2

RC0602 20_0402_1%

Place near CPU.

VCCCPUIO

RC0603 0_0402_5%

EMC_NS@

1 2

1

CC0601

0.1U_0402_10V6-K

2

@

12

RC0601

24.9_0402_1%

PROC_AUDIO_CLK_CPU [17] PROC_AUDIO_SDO_CPU [17]

PROC_AUDIO_SDI_CPU [17]

EMI

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

CPU KBL-H : DDI/EDP

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, November 08, 2016

NM-B071

1

6 99

0.2

5

VCC1R2A VCC3BVCC3M

UC0701

DDR_PG_CTRL

D D

C C

2 3

74AUP1G07GF_SOT891-6_1X1

PROCPWRGD From PCH to CPU RESET# From PCH to CPU

NC11Vcc A

NC2

GND

VCC1R2A

@

6 5 4

Y

2

1

CC0727

0.1U_0402_10V7-K

2

1

QC0703 RN1105MFV_21L1A

3

RC0729 10K_0402_5%

@

1 2

RC0726

RC0723

1 2

@

100K_0402_5%

-SVID_ALERT[84] SVID_CLK[84]

SVID_DATA[84]

-PROCHOT[43,84]

EMI SOLUTION

PROCPWRGD_CPU

-PCH_PLTRST_PROC PM_SYNC PM_DOWN

1

CC0728 22P_0402_50V8-J

2

EMC_NS@

1

CC0729 22P_0402_50V8-J

2

EMC_NS@

1

CC0730 22P_0402_50V8-J

2

EMC_NS@

1

CC0731 22P_0402_50V8-J

2

EMC_NS@

4

DDR_VTT_PG_CTRL [91]

CPU_BCLK_100M[20]

-CPU_BCLK_100M[20] CPU_PCI_BCLK_100M[20]

-CPU_PCI_BCLK_100M[20] CPU_REFCLK_24M[20]

-CPU_REFCLK_24M[20]

-SVID_ALERT SVID_CLK SVID_DATA

-PROCHOT

PROCPWRGD_CPU[17]

-PCH_PLTRST_PROC[16] PM_SYNC[16]

PM_DOWN[16]

PECI[16,43]

-THERMTRIP[16,34]

-SVID_ALERT SVID_CLK SVID_DATA

-PROCHOT

1 2

RC0712 220_0402_5%

1 2

RC0724 0_0402_5%

1 2

RC0725 0_0402_5%

1 2

RC0713 499_0402_1%

DDR_PG_CTRL

VCCST_PWRGD

PROCPWRGD_CPU

VCCST

1 2

RC0722 60.4_0402_1%

RC0714 0_0402_5%

1 2

Follow CRB have stuff

RC0720 10K_0402_5%

12

The pin is Open Drain can leave as NC

1 2

RC072820_0402_1%

12

-SVID_ALERT_R SVID_CLK_R SVID_DATA_R

-PROCHOT_R

VCCST_PWRGD_R

PM_DOWN_R

-CATERR_R

3

RC0701

56.2_0402_1%

UC1E

B31

BCLKP

A32

BCLKN

D35

PCI_BCLKP

C36

PCI_BCLKN

E31

CLK24P

D31

CLK24N

BH31

VIDALERT#

BH32

VIDSCK

BH29

VIDSOUT

BR30

PROCHOT#

BT13

DDR_VTT_CNTL

H13

VCCST_PWRGD

BT31

PROCPWRGD

BP35

RESET#

BM34

PM_SYNC

BP31

PM_DOWN

BT34

PECI

J31

THERMTRIP#

BR33

SKTOCC#

BN1

PROC_SELECT#

BM30

CATERR#

KABYLAKE-H-CPU_BGA1440

CFG[19:8] : Reserved

RC0702 100_0402_5%

@

1 2

SKYLAKE_HALO

BGA1440

5 OF 14

RC0703 100_0402_5%

1 2

CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[17] CFG[16] CFG[19] CFG[18]

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PROC_TDO

PROC_TDI PROC_TMS PROC_TCK

PROC_TRST# PROC_PREQ# PROC_PRDY#

CFG_RCOMP

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9]

VCCSTGVCCST

BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19

BN23 BP23 BP22 BN22

BR27 BT27 BM31 BT30

BT28 BL32 BP28 BR28

BP30 BL30 BP27

BT25

RC0704 1K_0402_1%

1 2

CFG0 CFG2

CFG3 CFG4 CFG5 CFG6 CFG7

IST_TRIG

CFG_RCOMP

2

1 2

1

1 1 1 1 1 1 1 1

1 1 1 1

RC0715

49.9_0402_1%

TP0718Test_Point_32MIL

TP0701Test_Point_32MIL TP0702Test_Point_32MIL TP0703Test_Point_32MIL TP0704Test_Point_32MIL

12

TP0705Test_Point_32MIL TP0706Test_Point_32MIL TP0708Test_Point_32MIL TP0709Test_Point_32MIL

TP0710Test_Point_32MIL TP0711Test_Point_32MIL TP0712Test_Point_32MIL TP0713Test_Point_32MIL

TP0714 Test_Point_32MIL TP0715 Test_Point_32MIL TP0716 Test_Point_32MIL TP0717 Test_Point_32MIL

RC0705 1K_0402_1%

@

RC0716 51_0402_1%

@

1 2

CFG3 [24]

12

RC0706 1K_0402_1%

RC0721 51_0402_1%

@

1 2

12

RC0708 1K_0402_1%

XDP_TDO [24] XDP_TDI [24] XDP_TMS [24] XDP_TCK [24]

-XDP_TRST [24]

-XDP_PREQ [24]

-XDP_PRDY [24]

12

RC0709 1K_0402_1%

1

RC0710 1K_0402_1%

12

RC0711 1K_0402_1%

@

12

B B

2

G

VCC1R0_SUS

RC0718 10K_0402_5%

1 2

13

D

QC0702 LSK3541G1ET2L_VMT3

S

VCCST_PWRGD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

VCC3_SUS

RC0717 10K_0402_5%

1 2

13

CPUCORE_ON[40,84]

A A

CPUCORE_ON

D

2

G

QC0701 LSK3541G1ET2L_VMT3

S

NMB071_T470P_SVT_1114_for SMT

5

4

TABLE

CFG[19:0] pin has internal Pull up to VCCCPUIO with 5-8 k ohm.

CFG[0] : Stall reset sequence after CPU PLL lock until de-asserted:

1 : No Stall 0 : Stall

CFG[2] : PEG Static Lane Reversal

1 : Normal Operation 0 : Lane Reversal

CFG[4] : eDP enable

1 : Disabled 0 : Enabled

CFG[6:5] : PEG Bifurcation, bus#:dev#:func#=0:1:2(CONFIRM BIOS)

00 : 1x4

CFG[7] : PEG Training(CONFIRM BIOS)

1 : PEG Train immediately following RESET# deassertion 0 : PEG Wait for BIOS for training

<----------- LOGIC

CFG[19:8] : Reserved

For x16 Reversal Lanes - CFG[6/5/2] setting is 110 For x4 Reversal Lanes - CFG[6/5/2] setting is 000 For x4 Normal Lanes - CFG[6/5/2] setting is 001

Title

CPU KBL-H : MISC/CLK/JTAG/CFG

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, November 08, 2016

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

NM-B071

1

7 99

0.2

5

4

3

2

1

SKYLAKE_HAL O

D D

C C

B B

UC1F

Y38

VSS_1

Y37

VSS_2

Y14

VSS_3

Y13

VSS_4

Y11

VSS_5

Y10

VSS_6

Y9

VSS_7

Y8

VSS_8

Y7

VSS_9

W34

VSS_10

W33

VSS_11

W12

VSS_12

W5

VSS_13

W4

VSS_14

W3

VSS_15

W2

VSS_16

W1

VSS_17

V30

VSS_18

V29

VSS_19

V12

VSS_20

V6

VSS_21

U38

VSS_153

U37

VSS_22

U6

VSS_23

T34

VSS_24

T33

VSS_25

T14

VSS_26

T13

VSS_27

T12

VSS_28

T11

VSS_29

T10

VSS_30

T9

VSS_31

T8

VSS_32

T7

VSS_33

T5

VSS_34

T4

VSS_35

T3

VSS_36

T2

VSS_37

T1

VSS_38

R30

VSS_39

R29

VSS_40

R12

VSS_41

P38

VSS_42

P37

VSS_43

P12

VSS_44

P6

VSS_45

N34

VSS_46

N33

VSS_47

N12

VSS_48

N11

VSS_49

N10

VSS_50

N9

VSS_51

N8

VSS_52

N7

VSS_53

N6

VSS_54

N5

VSS_55

N4

VSS_56

N3

VSS_57

N2

VSS_58

N1

VSS_59

M14

VSS_60

M13

VSS_61

M12

VSS_62

M6

VSS_63

L34

VSS_64

L33

VSS_65

L30

VSS_66

L29

VSS_67

K38

VSS_68

K11

VSS_69

K10

VSS_70

K9

VSS_71

K8

VSS_72

K7

VSS_73

K5

VSS_74

K4

VSS_75

K3

VSS_76

K2

VSS_77

KABYLAKE-H-CPU_BGA1440

BGA1440

6 OF 14

VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152

NCTFVSS_1

BT32 BT26 BT24 BT21 BT18 BT14 BT12

BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12

BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12

BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12

BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12

BM9 BM6

BM2 BL29 BK29 BK15 BK14 BJ32 BJ31 BJ25 BJ22

BH14 BH12

BH9

BH8

BH5

BH4

BH1

BG38 BG13 BG12

BF33 BF12 BE29

BD9

BC34 BC12

BB12

C17 C13

BT9 BT5

BR7

BP7

BN9 BN7 BN4 BN2

BE6

C9

K1 J36 J33 J32 J25 J22 J18 J10 J7 J4 H35 H32 H25 H22 H18 H12 H11 G28 G26 G24 G23 G22 G20 G18 G16 G14 G12 G10 G9 G8 G6 G5 G4 F36 F31 F29 F27 F25 F23 F21 F19 F17 F15 F13 F11 F9 F8 F5 F4 F3 F2 E38 E35 E34 E9 E4 D33 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D9 D6 D3 C37 C31 C29 C27

D38

SKYLAKE_HAL O

UC1L

KABYLAKE-H-CPU_BGA1440

VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238

BGA1440

12 OF 14

VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299

NCTFVSS_2 NCTFVSS_3 NCTFVSS_4 NCTFVSS_5 NCTFVSS_6 NCTFVSS_7

C25 C23 C21 C19 C15 C11 C8 C5 BM29 BM25 BM18 BM11 BM8 BM7 BM5 BM3 BL38 BL35 BL13 BL6 BK25 BK22 BK13 BK6 BJ30 BJ29 BJ15 BJ12 BH11 BH10 BH7 BH6 BH3 BH2 BG37 BG14 BG6 BF34 BF6 BE30 BE5 BE4 BE3 BE2 BE1 BD38 BD37 BD12 BD11 BD10 BD8 BD7 BD6 BC33 BC14 BC13 BC6 BB30 BB29 BB6 BB5

C2 BT36 BT35 BT4 BT3 BR38

UC1M

BB4

VSS_300

BB3

VSS_301

BB2

VSS_302

BB1

VSS_303

BA38

VSS_304

BA37

VSS_305

BA12

VSS_306

BA11

VSS_307

BA10

VSS_308

BA9

VSS_309

BA8

VSS_310

BA7

VSS_311

BA6

VSS_312

B9

VSS_313

AY34

VSS_314

AY33

VSS_315

AY14

VSS_316

AY12

VSS_317

AW30

VSS_318

AW29

VSS_319

AW12

VSS_320

AW5

VSS_321

AW4

VSS_322

AW3

VSS_323

AW2

VSS_324

AW1

VSS_325

AV38

VSS_326

AV37

VSS_327

AU34

VSS_328

AU33

VSS_329

AU12

VSS_330

AU11

VSS_331

AU10

VSS_332

AU9

VSS_333

AU8

VSS_334

AU7

VSS_335

AU6

VSS_336

AT30

VSS_337

AT29

VSS_338

AT6

VSS_339

AR38

VSS_340

AR37

VSS_341

AR14

VSS_342

AR13

VSS_343

AR5

VSS_344

AR4

VSS_345

AR3

VSS_346

AR2

VSS_347

AR1

VSS_348

AP34

VSS_349

AP33

VSS_350

AP12

VSS_351

AP11

VSS_352

AP10

VSS_353

AP9

VSS_354

AP8

VSS_355

AN30

VSS_356

AN29

VSS_357

AN12

VSS_358

AN6

VSS_359

AN5

VSS_360

AM38

VSS_361

AM37

VSS_362

AM12

VSS_363

AM5

VSS_364

AM4

VSS_365

AM3

VSS_366

AM2

VSS_367

AM1

VSS_368

AL34

VSS_369

AL33

VSS_370

AL14

VSS_371

AL12

VSS_372

AL10

VSS_373

AL9

VSS_374

AL8

VSS_375

AL7

VSS_376

AL4

VSS_377

KABYLAKE-H-CPU_BGA1440

SKYLAKE_HAL O

BGA1440

13 OF 14

VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433 VSS_434 VSS_435 VSS_436 VSS_437 VSS_438 VSS_439 VSS_440 VSS_441 VSS_442 VSS_443 VSS_444 VSS_445 VSS_446

NCTFVSS_8

NCTFVSS_9 NCTFVSS_10 NCTFVSS_11 NCTFVSS_12

AK30 AK29 AK4 AJ38 AJ37 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH34 AH33 AH12 AH6 AG30 AG29 AG11 AG10 AG8 AG7 AG6 AF14 AF13 AF12 AF4 AF3 AF2 AF1 AE34 AE33 AE6 AD30 AD29 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AC38 AC37 AC12 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AB6 AA30 AA29 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6

B37 B3 A34 A4 A3

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

CPU KBL-H : GND

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, November 08, 2016

NM-B071

1

8 99

0.2

5

4

3

2

1

VCCCPUCORE

1

CC0901 10U_0402_6.3V6-M

D D

VCCCPUCORE VCCCPUCORE

SKYLAKE_HAL O

UC1G

AA13 AA31 AA32

C C

B B

A A

AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38

K13 K14 L13 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13

BGA1440

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63

VCC_SENSE VSS_SENSE

KABYLAKE-H-CPU_BGA1440

7 OF 14

VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98

VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110 VCC_111 VCC_112 VCC_113 VCC_114 VCC_115 VCC_116 VCC_117 VCC_118 VCC_119 VCC_120 VCC_121 VCC_122 VCC_123 VCC_124 VCC_125 VCC_126

V32 V33 V34 V35 V36 V37 V38 W13 W14 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 L14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 P14

AG37 AG38

2

VCCCPUCORE

1

CC0917 10U_0402_6.3V6-M

2

VCCCPUCORE

1

CC0929 1U_0201_6.3V6-K

2

VCCCPUCORE

1

CC0943 1U_0201_6.3V6-K

2

VCCCPUCORE

1

CC0957 1U_0201_6.3V6-K

2

VCCCPUCORE

1

CC0970 1U_0201_6.3V6-K

2

VCCCPUCORE

1

CC0986 1U_0201_6.3V6-K

2

NEAR PROCESSOR PINS

1 2

RC0903 0_0402_5%

1 2

RC0904 0_0402_5%

1

CC0908 10U_0402_6.3V6-M

2

1

CC0914 10U_0402_6.3V6-M

2

1

CC0930 1U_0201_6.3V6-K

2

CD@

1

CC0944 1U_0201_6.3V6-K

2

1

CC0958 1U_0201_6.3V6-K

2

1

CC0971 1U_0201_6.3V6-K

2

1

CC0984 1U_0201_6.3V6-K

2

VCCCPUCORE

12

NMB071_T470P_SVT_1114_for SMT

5

4

1

CC0931 1U_0201_6.3V6-K

2

1

CC0945 1U_0201_6.3V6-K

2

1

CC0959 1U_0201_6.3V6-K

2

1

CC0972 1U_0201_6.3V6-K

2

1

CC0988 1U_0201_6.3V6-K

2

RC0901 100_0402_1%

RC0902 100_0402_1%

1

CC0907 10U_0402_6.3V6-M

2

1

CC0915 10U_0402_6.3V6-M

2

1

CC0932 1U_0201_6.3V6-K

2

1

CC0946 1U_0201_6.3V6-K

2

1

CC0960 1U_0201_6.3V6-K

2

1

CC0973 1U_0201_6.3V6-K

2

1

CC0985 1U_0201_6.3V6-K

2

VCCCORE_SENSE [84] VSSCORE_SENSE [84]

1

CC0910 10U_0402_6.3V6-M

2

CD@

1

CC0912 10U_0402_6.3V6-M

2

1

CC0906 10U_0402_6.3V6-M

2

1

CC0913 10U_0402_6.3V6-M

2

1

CC0933 1U_0201_6.3V6-K

2

1

CC0947 1U_0201_6.3V6-K

2

1

CC0961 1U_0201_6.3V6-K

2

1

CC0975 1U_0201_6.3V6-K

2

1

CC0987 1U_0201_6.3V6-K

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

10uF 28pcs

1

CC0905 10U_0402_6.3V6-M

2

1

CC0918 10U_0402_6.3V6-M

2

1uF 64pcs

1

CC0934 1U_0201_6.3V6-K

2

1

CC0948 1U_0201_6.3V6-K

2

1

CC0962 1U_0201_6.3V6-K

2

1

CC0974 1U_0201_6.3V6-K

2

1

CC0989 1U_0201_6.3V6-K

2

Issued Date

3

1

CC0904 10U_0402_6.3V6-M

2

1

CC0927 10U_0402_6.3V6-M

2

1

CC0935 1U_0201_6.3V6-K

2

1

CC0949 1U_0201_6.3V6-K

2

1

CC0963 1U_0201_6.3V6-K

2

1

CC0977 1U_0201_6.3V6-K

2

1

CC0990 1U_0201_6.3V6-K

2

1

2

1

2

1

2

1

2

1

2

2015/07/16

1

CC0902 10U_0402_6.3V6-M

2

1

CC0928 10U_0402_6.3V6-M

2

CC0936 1U_0201_6.3V6-K

CC0950 1U_0201_6.3V6-K

CC0964 1U_0201_6.3V6-K

CC0976 1U_0201_6.3V6-K

CC0991 1U_0201_6.3V6-K

1

CC0937 1U_0201_6.3V6-K

2

1

CC0951 1U_0201_6.3V6-K

2

1

CC0965 1U_0201_6.3V6-K

2

1

CC0979 1U_0201_6.3V6-K

2

LC Future Center Secret Data

Deciphered Date

1

CC0903 10U_0402_6.3V6-M

2

1

CC0926 10U_0402_6.3V6-M

2

1

CC0909 10U_0402_6.3V6-M

2

1

CC0925 10U_0402_6.3V6-M

2

1

CC0938 1U_0201_6.3V6-K

2

1

CC0952 1U_0201_6.3V6-K

2

1

CC0966 1U_0201_6.3V6-K

2

CD@

1

CC0978 1U_0201_6.3V6-K

2

1

CC0939 1U_0201_6.3V6-K

2

1

CC0953 1U_0201_6.3V6-K

2

1

CC0992 1U_0201_6.3V6-K

2

1

CC0980 1U_0201_6.3V6-K

2

2016/01/16

1

CC0911 10U_0402_6.3V6-M

2

1

CC0922 10U_0402_6.3V6-M

2

1

CC0919 10U_0402_6.3V6-M

2

1

CC0924 10U_0402_6.3V6-M

2

1

CC0940 1U_0201_6.3V6-K

2

1

CC0954 1U_0201_6.3V6-K

2

CD@

1

CC0967 1U_0201_6.3V6-K

2

1

CC0982 1U_0201_6.3V6-K

2

Title

CPU KBL-H : VCC

Size Document Number Re v

Custom

Date: Sheet of

1

CC0916 10U_0402_6.3V6-M

2

1

CC0921 10U_0402_6.3V6-M

2

1

CC0941 1U_0201_6.3V6-K

2

1

CC0955 1U_0201_6.3V6-K

2

1

CC0968 1U_0201_6.3V6-K

2

1

CC0981 1U_0201_6.3V6-K

2

Tuesday, November 08, 2016

1

2

1

2

1

2

1

2

1

CC0920 10U_0402_6.3V6-M

2

CD@

1

CC0923 10U_0402_6.3V6-M

2

CC0942 1U_0201_6.3V6-K

CC0956 1U_0201_6.3V6-K

CD@

CC0969 1U_0201_6.3V6-K

CC0983 1U_0201_6.3V6-K

NM-B071

1

9 99

0.2

5

4

3

2

1

VCCGFXCORE_I

1

CC1001 10U_0402_6.3V6-M

2

1

CC1013 10U_0402_6.3V6-M

2

CD@

1

CC1036 1U_0201_6.3V6-K

2

1

CC1056 1U_0201_6.3V6-K

2

1

CC1075 1U_0201_6.3V6-K

2

1

CC1095 1U_0201_6.3V6-K

2

1 2 1 2

2

1

2

1

CC1037 1U_0201_6.3V6-K

2

1

CC1057 1U_0201_6.3V6-K

2

1

CC1078 1U_0201_6.3V6-K

2

1

CC1097 1U_0201_6.3V6-K

2

CD@

D D

VCCGFXCORE_IVCCGFXCORE_I VCCGFXCORE_I

SKYLAKE_HALO

UC1H

BGA1440

BG34

VCCGT_1

BG35

VCCGT_2

BG36

VCCGT_3

BH33

VCCGT_4

BH34

VCCGT_5

BH35

VCCGT_6

BH36

VCCGT_7

BH37

VCCGT_8

BH38

VCCGT_9

BJ37

VCCGT_10

BJ38

VCCGT_11

BL36

VCCGT_12

BL37

VCCGT_13

BM36

VCCGT_14

BM37

VCCGT_15

BN36

VCCGT_16

C C

BN37

VCCGT_17

BN38

VCCGT_18

BP37

VCCGT_19

BP38

VCCGT_20

BR37

VCCGT_21

BT37

VCCGT_22

BE38

VCCGT_23

BF13

VCCGT_24

BF14

VCCGT_25

BF29

VCCGT_26

BF30

VCCGT_27

BF31

VCCGT_28

BF32

VCCGT_29

BF35

VCCGT_30

BF36

VCCGT_31

BF37

VCCGT_32

BF38

VCCGT_33

BG29

VCCGT_34

BG30

VCCGT_35

BG31

VCCGT_36

BG32

VCCGT_37

BG33

VCCGT_38

BC36

VCCGT_39

BC37

VCCGT_40

BC38

VCCGT_41

BD13

VCCGT_42

BD14

VCCGT_43

BD29

VCCGT_44

BD30

VCCGT_45

BD31

VCCGT_46

BD32

VCCGT_47

BD33

VCCGT_48

B B

BD34

VCCGT_49

BD35

VCCGT_50

BD36

VCCGT_51

BE31

VCCGT_52

BE32

VCCGT_53

BE37

VCCGT_54

KABYLAKE-H-CPU_BGA1440

A A

8 OF 14

VCCGT_55 VCCGT_56 VCCGT_57 VCCGT_58 VCCGT_59 VCCGT_60 VCCGT_61 VCCGT_62 VCCGT_63 VCCGT_64 VCCGT_65 VCCGT_66 VCCGT_67 VCCGT_68 VCCGT_69 VCCGT_70 VCCGT_71 VCCGT_72 VCCGT_73 VCCGT_74 VCCGT_75 VCCGT_76 VCCGT_77 VCCGT_78 VCCGT_79 VCCGT_80 VCCGT_81 VCCGT_82 VCCGT_83 VCCGT_84 VCCGT_85 VCCGT_86 VCCGT_87 VCCGT_88 VCCGT_89 VCCGT_90 VCCGT_91 VCCGT_92 VCCGT_93 VCCGT_94 VCCGT_95 VCCGT_96 VCCGT_97 VCCGT_98

VCCGT_99 VCCGT_100 VCCGT_101 VCCGT_102 VCCGT_103 VCCGT_104 VCCGT_105 VCCGT_106 VCCGT_107 VCCGT_108

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 AJ36 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AL13 AL29 AL30 AL31 AL32 AL35 AL36 AL37

AL38 AM13 AM14 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN13 AN14 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38

AP13

AP14

AP29

AP30

AP31

AP32

AP35

AP36

AP37

AP38 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36

AT14

AT31

AT32

AT33

AT34

AT35

AT36

AT37

AT38 AU14 AU29 AU30 AU31 AU32 AU35 AU36 AU37 AU38

5

SKYLAKE_HA LO

UC1N

VCCGT_109 VCCGT_110 VCCGT_111 VCCGT_112 VCCGT_113 VCCGT_114 VCCGT_115 VCCGT_116 VCCGT_117 VCCGT_118 VCCGT_119 VCCGT_120 VCCGT_121 VCCGT_122 VCCGT_123 VCCGT_124 VCCGT_125 VCCGT_126 VCCGT_127 VCCGT_128 VCCGT_129 VCCGT_130 VCCGT_131 VCCGT_132 VCCGT_133 VCCGT_134 VCCGT_135 VCCGT_136 VCCGT_137 VCCGT_138 VCCGT_139 VCCGT_140 VCCGT_141 VCCGT_142 VCCGT_143 VCCGT_144 VCCGT_145 VCCGT_146 VCCGT_147 VCCGT_148 VCCGT_149 VCCGT_150 VCCGT_151 VCCGT_152 VCCGT_153 VCCGT_154 VCCGT_155 VCCGT_156 VCCGT_157 VCCGT_158 VCCGT_159 VCCGT_160 VCCGT_161 VCCGT_162 VCCGT_163 VCCGT_164 VCCGT_165 VCCGT_166 VCCGT_167 VCCGT_168 VCCGT_169 VCCGT_170 VCCGT_171 VCCGT_172 VCCGT_173 VCCGT_174 VCCGT_175 VCCGT_176 VCCGT_177 VCCGT_178 VCCGT_179 VCCGT_180 VCCGT_181 VCCGT_182 VCCGT_183 VCCGT_184 VCCGT_185 VCCGT_186 VCCGT_187 VCCGT_188 VCCGT_189

KABYLAKE-H-CPU_BGA1440

BGA1440

14 OF 14

VCCGTX_1 VCCGTX_2 VCCGTX_3 VCCGTX_4 VCCGTX_5 VCCGTX_6 VCCGTX_7 VCCGTX_8

VCCGTX_9 VCCGTX_10 VCCGTX_11 VCCGTX_12 VCCGTX_13 VCCGTX_14 VCCGTX_15 VCCGTX_16 VCCGTX_17 VCCGTX_18 VCCGTX_19 VCCGTX_20 VCCGTX_21 VCCGTX_22

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

VCCGFXCORE_I

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14

VCCGFXCORE_I AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32

VCCGFXCORE_I AJ13 AJ14

VCCGFXCORE_I

AH38

RC1003 0_0402_5%

AH35 AH37

RC1004 0_0402_5%

AH36

CC1008 10U_0402_6.3V6-M

CC1018 10U_0402_6.3V6-M

VCCGFXCORE_I

12

100_0402_5% RC1001

12

100_0402_5% RC1002

4

1

CC1007 10U_0402_6.3V6-M

2

1

CC1028 10U_0402_6.3V6-M

2

CD@

1

CC1038 1U_0201_6.3V6-K

2

1

CC1058 1U_0201_6.3V6-K

2

1

CC1077 1U_0201_6.3V6-K

2

1

CC1098 1U_0201_6.3V6-K

2

1

CC1039 1U_0201_6.3V6-K

2

1

CC1059 1U_0201_6.3V6-K

2

1

CC1080 1U_0201_6.3V6-K

2

1

CC1099 1U_0201_6.3V6-K

2

VCCGT_SENSE [84] VSSGT_SENSE [84]

1

CC1010 10U_0402_6.3V6-M

2

1

CC1023 10U_0402_6.3V6-M

2

1

CC1041 1U_0201_6.3V6-K

2

1

CC1060 1U_0201_6.3V6-K

2

1

CC1079 1U_0201_6.3V6-K

2

1

C10101 1U_0201_6.3V6-K

2

1

CC1006 10U_0402_6.3V6-M

2

1

CC1026 10U_0402_6.3V6-M

2

1

CC1040 1U_0201_6.3V6-K

2

1

CC1061 1U_0201_6.3V6-K

2

1

CC1082 1U_0201_6.3V6-K

2

1

C10102 1U_0201_6.3V6-K

2

1

CC1005 10U_0402_6.3V6-M

2

1

CC1027 10U_0402_6.3V6-M

2

1

CC1043 1U_0201_6.3V6-K

2

1

CC1062 1U_0201_6.3V6-K

2

1

CC1083 1U_0201_6.3V6-K

2

1

C10103 1U_0201_6.3V6-K

2

Near CPU

10uF 35pcs

1

CC1004 10U_0402_6.3V6-M

2

1

CC1022 10U_0402_6.3V6-M

2

1uF 68pcs

1

CC1042 1U_0201_6.3V6-K

2

1

CC1063 1U_0201_6.3V6-K

2

1

CC1081 1U_0201_6.3V6-K

2

1

C10100 1U_0201_6.3V6-K

2

1

CC1002 10U_0402_6.3V6-M

2

1

CC1025 10U_0402_6.3V6-M

2

1

CC1044 1U_0201_6.3V6-K

2

1

CC1064 1U_0201_6.3V6-K

2

1

CC1085 1U_0201_6.3V6-K

2

3

1

CC1003 10U_0402_6.3V6-M

2

1

CC1021 10U_0402_6.3V6-M

2

1

CC1046 1U_0201_6.3V6-K

2

CD@

1

CC1066 1U_0201_6.3V6-K

2

1

CC1084 1U_0201_6.3V6-K

2

1

CC1009 10U_0402_6.3V6-M

2

1

CC1024 10U_0402_6.3V6-M

2

1

CC1045 1U_0201_6.3V6-K

2

1

CC1065 1U_0201_6.3V6-K

2

1

CC1087 1U_0201_6.3V6-K

2

1

CC1011 10U_0402_6.3V6-M

2

1

CC1031 10U_0402_6.3V6-M

2

1

CC1048 1U_0201_6.3V6-K

2

1

CC1068 1U_0201_6.3V6-K

2

1

CC1086 1U_0201_6.3V6-K

2

1

CC1019 10U_0402_6.3V6-M

2

1

CC1035 10U_0402_6.3V6-M

2

1

CC1050

CC1047

1U_0201_6.3V6-K

2

CD@

1

CC1067

CC1070

1U_0201_6.3V6-K

2

1

CC1088

CC1090

1U_0201_6.3V6-K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTI AL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTI AL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT O F LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT O F LC FUTURE CENTER.

CC1016 10U_0402_6.3V6-M

2

1

CC1034 10U_0402_6.3V6-M

2

1

CC1049 1U_0201_6.3V6-K

2

1

CC1069 1U_0201_6.3V6-K

2

1

CC1089 1U_0201_6.3V6-K

2

1

CC1020 10U_0402_6.3V6-M

2

1

CC1030 10U_0402_6.3V6-M

2

2015/07/16

1

CC1051 1U_0201_6.3V6-K

2

1

CC1072 1U_0201_6.3V6-K

2

1

CC1091 1U_0201_6.3V6-K

2

1

CC1017

10U_0402_6.3V6-M

2

1

CC1032 10U_0402_6.3V6-M

2

CC1014 10U_0402_6.3V6-M

2

CD@

1

CC1029 10U_0402_6.3V6-M

2

1

CC1053 1U_0201_6.3V6-K

2

CD@

1

CC1071 1U_0201_6.3V6-K

2

1

CC1094 1U_0201_6.3V6-K

2

LC Future Center Secret Data

Deciphered Date

1

2

1

2

1

2

CC1052 1U_0201_6.3V6-K

CC1074 1U_0201_6.3V6-K

CC1092 1U_0201_6.3V6-K

1

CC1015 10U_0402_6.3V6-M

2

1

CC1033 10U_0402_6.3V6-M

2

1

2

1

2

1

2

2016/01/16

1

CC1012 10U_0402_6.3V6-M

2

1

CC1054

CC1055

1U_0201_6.3V6-K

2

1

CC1073

CC1076

1U_0201_6.3V6-K

2

1

CC1096

CC1093

1U_0201_6.3V6-K

2

Title

CPU KBL-H : VCCGT/VCCGTX

Size

Document Number Re v

Custom

Custom Date: Sheet of

Date: Sheet of

Tuesday, November 08, 2016

1

NM-B071

10 99

0.2

NMB071_T470P_SVT_1114_for SMT

5

www.vinaﬁx.com

4

3

2

1

VCCSA

10uF 7pcs

1

CC1125 10U_0402_6.3V6-M

2

D D

VCCSA

1

CC1130 10U_0402_6.3V6-M

2

VCCSA DECOUPLING

1

CC1129 10U_0402_6.3V6-M

2

1

CC1131 10U_0402_6.3V6-M

2

1

CC1128 10U_0402_6.3V6-M

2

1

CC1127 10U_0402_6.3V6-M

2

1

CC1126 10U_0402_6.3V6-M

2

1uF 3pcs

1

CC1133 1U_0402_6.3V6-K

2

C C

VCCCPUIO

B B

1

CC1108 10U_0603_6.3V6-M

2

1

CC1132 1U_0402_6.3V6-K

2

1

2

1

CC1109 10U_0603_6.3V6-M

2

CC1134 1U_0402_6.3V6-K

1

CC1110 10U_0603_6.3V6-M

2

VCCSA

UC1I

J30

VCCSA_1

K29

VCCSA_2

K30

VCCSA_3

K31

VCCSA_4

K32

VCCSA_5

K33

VCCSA_6

K34

VCCSA_7

K35

VCCSA_8

L31

VCCSA_9

L32

VCCSA_10

L35

VCCSA_11

L36

VCCSA_12

L37

VCCSA_13

L38

VCCSA_14

M29

VCCSA_15

M30

VCCSA_16

M31

VCCSA_17

M32

VCCSA_18

M33

VCCSA_19

M34

VCCSA_20

M35

VCCSA_21

M36

VCCSA_22

AG12

VCCIO_1

G15

VCCIO_2

G17

VCCIO_3

G19

VCCIO_4

G21

VCCIO_5

H15

VCCIO_6

H16

VCCIO_7

H17

VCCIO_8

H19

VCCIO_9

H20

VCCIO_10

H21

VCCIO_11

H26

VCCIO_12

H27

VCCIO_13

J15

VCCIO_14

J16

VCCIO_15

J17

VCCIO_16

J19

VCCIO_17

J20

VCCIO_18

J21

VCCIO_19

J26

VCCIO_20

J27

VCCIO_21

KABYLAKE-H-CPU_BGA1440

SKYLAKE_HAL O

BGA1440

9 OF 14

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19 VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24

VDDQC

VCCPLL_OC_1 VCCPLL_OC_2

VCCST VCCSTG_1 VCCSTG_2

VCCPLL_1 VCCPLL_2

VCCSA_SENSE VSSSA_SENSE

VCCIO_SENSE VSSIO_SENSE

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12 BH13

G11

H30 H29 G30 H28

J28

M38 M37

H14 J14

VCC1R2A

10uF 10pcs

1

CC1111 10U_0402_6.3V6-M

2

VCC1R2A

1

CC1121 22U_0603_6.3V6M

2

VDDQC : Memory Control Clock Power VCCPLL_OC : CPU digital PLL power rails

VCC1R2A VCCST VCCSTG

1

CC1107 10U_0603_6.3V6-M

2

RC1115 0_0402_5% RC1116 0_0402_5%

VCCST

1

CC1112 10U_0402_6.3V6-M

2

22uF 4pcs

1

CC1122 22U_0603_6.3V6M

2

1 2 1 2

CC1104 1U_0402_6.3V6-K

VDDQ DECOUPLING

1

CC1113 10U_0402_6.3V6-M

2

CC1105 1U_0402_6.3V6-K

1

2

1

CC1123 22U_0603_6.3V6M

2

VCC1R2A

12

RC1111 100_0402_1%

12

RC1113 100_0402_1%

CC1114 10U_0402_6.3V6-M

1

CC1124 22U_0603_6.3V6M

2

CC1106 1U_0402_6.3V6-K

VCCSAVCCCPUIO

12

RC1112 100_0402_1%

12

RC1114 100_0402_1%

1

CC1115 10U_0402_6.3V6-M

2

1

CC1116 10U_0402_6.3V6-M

2

CC1101 1U_0402_6.3V6-K

VCCSA_SENSE [84] VSSSA_SENSE [84]

VCCCPUIO_SENSE [89] VSSCPUIO_SENSE [89]

1

CC1117 10U_0402_6.3V6-M

2

CC1102 1U_0402_6.3V6-K

1

CC1118 10U_0402_6.3V6-M

2

CC1103 1U_0402_6.3V6-K

1

CC1119 10U_0402_6.3V6-M

2

1

CC1120 10U_0402_6.3V6-M

2

RESISTORS CLOSE TO CPU PINS

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

CPU KBL-H : VCCSA/VCCIO/VDDQ

Size Document Number Re v

Custom

Tuesday, November 08, 2016

Date: Sheet of

Tuesday, November 08, 2016

NM-B071

1

11 99

0.2

5

4

3

2

1

D D

UC1J

BJ17 BJ19

BJ20 BK17 BK19 BK20

BL16

BL17

BL18

BL19

BL20

BL21

BM17

BN17

BJ23

BJ26

BJ27 BK23 BK26 BK27

BL23

BL24

BL25

BL26

BL27

C C

B B

OPC_RCOM Support 4+4e If not use can"t conector

BL28

BM24

BL15

BM16

BL22

BM22

BP15 BR15 BT15

BP16 BR16 BT16

BN15

BM15

BP17 BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13 AY13

BT29 BR25 BP25

KABYLAKE-H-CPU_BGA1440

SKYLAKE_HALO

VCCOPC_1 VCCOPC_2 VCCOPC_3 VCCOPC_4 VCCOPC_5 VCCOPC_6 VCCOPC_7 VCCOPC_8 VCCOPC_9 VCCOPC_10 VCCOPC_11 VCCOPC_12 VCCOPC_13 VCCOPC_14

RSVD_1 RSVD_2 RSVD_3 RSVD_4 RSVD_5 RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11 RSVD_12 RSVD_13

VCCOPC_SENSE VSSOPC_SENSE

RSVD_14 RSVD_15

VCCEOPIO_1 VCCEOPIO_2 VCCEOPIO_3

RSVD_16 RSVD_17 RSVD_18

VCCEOPIO_SENSE VSSEOPIO_SENSE

RSVD_19 RSVD_20

VCC_OPC_1P8_1 VCC_OPC_1P8_2

RSVD_21 RSVD_22

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2

BGA1440

10 OF 14

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

CPU KBL-H : VCCOPC/RSVD

Size Document Number Re v

Custom

Tuesday, November 08, 2016

Date: Sheet of

Tuesday, November 08, 2016

NM-B071

1

12 99

0.2

5

D D

4

3

2

1

UC1K

D1

RSVD_TP_1

E1

RSVD_TP_2

E3

RSVD_TP_3

E2

RSVD_TP_4

BR1

RSVD_TP_5

BT2

RSVD_TP_6

BN35

RSVD_23

J24

RSVD_24

H24

C C

Follow Intel Spec document Rev. 0.75. A36,A37 change to VSS

PCH_2_CPU_TRIGGER[22]

CPU_2_PCH_TRIGGER[22]

B B

RC1301 30_0402_1%

12

CPU_2_PCH_TRIGGER_R

RSVD_25

BN33

RSVD_26

BL34

RSVD_27

N29

RSVD_28

R14

RSVD_29

AE29

RSVD_30

AA14

RSVD_31

A36

RSVD_32

A37

RSVD_33

H23

PROC_TRIGIN

J23

PROC_TRIGOUT

F30

RSVD_34

E30

RSVD_35

B30

RSVD_36

C30

RSVD_37

G3

RSVD_38

J3

RSVD_39

BR35

RSVD_40

BR31

RSVD_41

BH30

RSVD_42

KABYLAKE-H-CPU_BGA1440

SKYLAKE_HAL O

BGA1440

11 OF 14

RSVD_TP_7 RSVD_TP_8

RSVD_TP_9

RSVD_TP_10

RSVD_43 RSVD_44

VSS_447

RSVD_TP_11 RSVD_TP_12

RSVD_TP_13 RSVD_TP_14

RSVD_45 RSVD_46

RSVD_47 RSVD_48

VSS_448

RSVD_TP_15 RSVD_TP_16

RSVD_49 RSVD_50 RSVD_51

NCTF_1 NCTF_2 NCTF_3 NCTF_4 NCTF_5 NCTF_6

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18 BJ16

BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18 BJ34

BJ33

G13 AJ8 BL31

B2 B38 BP1

TP1303 Test_Point_20MIL

BR2 C1

TP1304 Test_Point_20MIL

C38

1 1

Follow Walter

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

CPU KBL-H : RSVD

Size Document Number Re v

Custom

Tuesday, November 08, 2016

Date: Sheet of

Tuesday, November 08, 2016

NM-B071

1

13 99

0.2

5

D D

4

3

2

1

VCC3_SUS

12

RH1408 10K_0402_5%

@

C C

SPI_MOSI_IO0[26,55] SPI_MISO_IO1[26,55]

-SPI_CS0[26] SPI_CLK[26,55]

SPI_IO2[26] SPI_IO3[26]

-SPI_CS2[55]

DOCKID[3:0][60]

CS0# for SPI ROM, CS2# for dTPM

1 2

RH1407 0_0402_5%

DOCKID1 DOCKID0 DOCKID3 DOCKID2

from Docking Connector

B B

All of NC pins should be set "GPO LOW" as default

SPT-H_PCH

1 OF 12

SPVR310100_4P

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

SW1401

2

1

3

4

BB27

P43 R39 R36 R42 R41

AF41 AE44 BC23 BD24

BC36 BE34 BD39 BB36 BA35 BC35 BD35 AW35 BD34

BE11

SPI_CLK_C

UH1A

BD17

GPP_A11/PME#

AG15

RSVD_1

AG14

RSVD_2

AF17

RSVD_3

AE17

RSVD_4

AR19

TP2

AN17

TP1

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

SKYLAKE-H-PCH_FCBGA837

-TAMPER_SW_DTCT[18]

U1401

1

-INTRUDER

1M_0402_5%

2 3

TC7SG17FE_SON5

RH1409 0_0402_5%@

TP1401

RH1403

-PLTRST

1 2

RH1404 0_0402_5%

NC IN_A GND

1 2

RTCVCC

12

2

1

CH1403 1000P_0402_25V7-K

VCC

OUT_Y

VCC3M

Need to check target device position to assign

5

-PLTRST_R

4

1 2

DH1401

RB521CS-30GT2RA_VMN2-2

SCS00006V00

RH1401

RH1402

1 2

33_0402_5%

1

CH1401 100P_0402_50V8-J

2

-INTRUDER_EC [44]

-PLTRST_FAR [24,54,61]

-PLTRST_NEAR [34,40,42,51,55,62,68]

1

CH1402 100P_0402_50V8-J

2

DOOR SWITCH -INTRUDER

CLOSE

OPEN

A A

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

OPEN

CLOSE

3

HIGH

LOW (ACTIVE)

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCH SKL-H : SPI

Size Document Number Re v

Custom

Tuesday, November 01, 2016

Date: Sheet of

Tuesday, November 01, 2016

NM-B071

1

14 99

0.2

5

4

3

2

1

D D

USB2 #1 USB2 #2 USB2 #3 USB2 #4 USB2 #5 USB2 #6 USB2 #7 USB2 #8 USB2 #9 USB2 #10 USB2 #11 USB2 #12

DMI_RXN0[5]

C C

WLAN

B B

LAN

Card Reader

PCIE1_CTX_C_DRX_N[62] PCIE1_CTX_C_DRX_P[62]

PCIE4_CTX_C_DRX_N[51] PCIE4_CTX_C_DRX_P[51]

PCIE5_CTX_C_DRX_N[54] PCIE5_CTX_C_DRX_P[54]

DMI_RXP0[5] DMI_TXN0[5] DMI_TXP0[5] DMI_RXN1[5] DMI_RXP1[5] DMI_TXN1[5] DMI_TXP1[5] DMI_RXN2[5] DMI_RXP2[5] DMI_TXN2[5] DMI_TXP2[5] DMI_RXN3[5] DMI_RXP3[5] DMI_TXN3[5] DMI_TXP3[5]

PCIE1_CRX_DTX_N[62] PCIE1_CRX_DTX_P[62]

PCIE4_CRX_DTX_N[51] PCIE4_CRX_DTX_P[51]

PCIE5_CRX_DTX_N[54] PCIE5_CRX_DTX_P[54]

DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3

RH1508

100_0402_1%

CH1505 0.1U_0402_10V7-K CH1506 0.1U_0402_10V7-K

CH1503 0.1U_0402_10V7-K CH1504 0.1U_0402_10V7-K

CH1509 0.1U_0402_10V7-K CH1510 0.1U_0402_10V7-K

1 2 1 2

12

PCIE_RCOMPN PCIE_RCOMPP

PCIE1_CRX_DTX_N PCIE1_CRX_DTX_P PCIE1_CTX_DRX_N PCIE1_CTX_DRX_P

PCIE4_CRX_DTX_N PCIE4_CRX_DTX_P PCIE4_CTX_DRX_N PCIE4_CTX_DRX_P PCIE5_CRX_DTX_N PCIE5_CRX_DTX_P PCIE5_CTX_DRX_N PCIE5_CTX_DRX_P

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKYLAKE-H-PCH_FCBGA837

Port Assignment

Non-AOU port 1 Non-AOU port 2 Docking USB2 AOU port WWAN Finger printer BT Camera Smart card reader Touch panel

SPT-H_PCH

DMI

PCIe/USB 3

2 OF 12

OC#USB2.0

OC0# OC0#

OC1#

USB 2.0

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

GPD7/RSVD

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6 USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9

USB2P_9 USB2N_10 USB2P_10 USB2N_11 USB2P_11 USB2N_12 USB2P_12 USB2N_13 USB2P_13 USB2N_14 USB2P_14

USB2_ID

AF5 AG7 AD5 AD7 AG8 AG10 AE1 AE2 AC2 AC3 AF2 AF3 AB3 AB2 AL8 AL7 AA1 AA2 AJ8 AJ7 W2 W3 AD3 AD2 V2 V1 AJ11 AJ13

-USB_OC0

AD43

-USB_OC1

AD42

-USB_OC2

AD39

-USB_OC3

AC44 Y43

PLANARID3

Y41

PLANARID2

-USB_OC6

W44

-USB_OC7

W43

USB2_COMP

AG3 AD10

Leave RSVD_AB13 NC

AB13 AG2

BD14

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5_FP USB20_P5_FP USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8_SMART_CARD USB20_P8_SMART_CARD USB20_N9_TP USB20_P9_TP

RH1509 113_0402_1% RH1510 1K_0402_1%

RH1511 1K_0402_1%

1 2 1 2

1 2

USB20_N0 [63] USB20_P0 [63] USB20_N1 [63] USB20_P1 [63] USB20_N2 [60] USB20_P2 [60] USB20_N3 [64] USB20_P3 [64] USB20_N4 [62] USB20_P4 [62] USB20_N5_FP [67] USB20_P5_FP [67] USB20_N6 [62] USB20_P6 [62] USB20_N7 [56]

USB20_P7 [56] USB20_N8_SMART_CARD [65] USB20_P8_SMART_CARD [65] USB20_N9_TP [56] USB20_P9_TP [56]

System Port 1 (Right-Front)

System Port 2 (Right-Back)

DOCKING

S/B (AOU Port)

WWAN

FP

BT

CAMERA

SMART CARD

Touch Panel(OPT)

FOLLOW L450 NEED DOUBLE CONFIRM

-USB_OC0 [63]

-USB_OC1 [64]

PLANARID3 [18] PLANARID2 [18]

-USB_OC3

-USB_OC1

-USB_OC0

-USB_OC2

-USB_OC6

-USB_OC7

RP1501

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

RP1502

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

@

VCC3_SUS

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCH SKL-H : DMI/PCIE/USB

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, November 01, 2016

NM-B071

1

15 99

0.2

5

4

3

2

1

Flexible I/OPort# Configration Port Assignment

PCIe #16

22

PCIe #15

21

PCIe #14

20

PCIe #13

19

PCIe #12

VCC3_SUS

12

18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

RH1601 10K_0402_5%

@

PCIe #11 PCIe #10 PCIe #9 PCIe #8 PCIe #7 PCIe #6 PCIe #5

USB3 #10 USB3 #9 USB3 #8 USB3 #7 USB3 #6 USB3 #5 USB3 #4 USB3 #3 USB3 #2 USB3 #1

D D

C C

B B

A A

from / to WLAN

CL_CLK_WLAN[62] CL_DATA_WLAN[62]

-CL_RST_WLAN[62]

-WWAN_CFG2[19,62]

-WWAN_CFG3[62] PLANARID1[18] PLANARID0[18]

SATA #3 SATA #2 SATA #1 SATA #0

SATA #1 SATA #0

PCIe #4 PCIe #3 PCIe #2 PCIe #1

UH1C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKYLAKE-H-PCH_FCBGA837

SATA #3 /PCIe #13 PCIe #14(Reversal)

GbE GbE

PCIe #10 SATA #0/PCIe #9

GbE

PCIe #5

GbE

PCIe #4

GbE

PCIe #1

USB3 #4 USB3 #3 USB3 #2 USB3 #1

CLINK

FAN

SPT-H_PCH

HOST

3 OF 12

M.2 SATA SSD / Optane Optane

SATA-Express SATA-Express

Card reader GbE PHY

WLAN

Docking USB3 USB AOU port USB non AOU port USB non AOU port

PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP PCIE10_TXN/SATA1A_TXN

PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED# GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PM_SYNC

PLTRST_PROC#

PM_DOWN

PECI

SATA_PRX_DTX_N0

G31

SATA_PRX_DTX_P0

H31

SATA_PTX_DRX_N0

C31

SATA_PTX_DRX_P0

B31

PCIE3_CRX_DTX_N

G29

PCIE3_CRX_DTX_P

E29

PCIE3_CTX_C_DRX_N

C32

PCIE3_CTX_C_DRX_P

B32

PCIE15_CRX_DTX_N

F41

PCIE15_CRX_DTX_P

E41

PCIE15_CTX_DRX_N

B39

PCIE15_CTX_DRX_P

A39

SATA2_PCIE16_CRX_DTX_N

D43

SATA2_PCIE16_CRX_DTX_P

E42

SATA2_PCIE16_CTX_DRX_N

A41

SATA2_PCIE16_CTX_DRX_P

A40 H42

H40 E45 F45

K37 G37 G45 G44

AD44

-PE_DTCT

AG36 AG35

SATAGP1

AG39

SATAGP2

-PE_DTCT_M2

AD35 AD31

SATAGP4

AD38

SATAGP5

-MIC_HW_EN

AC43 AB44

W36 W35 W42

-THERMTRIP_L

AJ3

PECI_L

AL3

PM_SYNC_L

AJ4 AK2 AH2

12

RH1610 10K_0402_5%

@

12

RH1611 10K_0402_5%

@

VCC3_SUS

12

RH1612 10K_0402_5%

CD@

12

RH1617 10K_0402_5%

@

12

10K_0402_5%

12

RH1613 100K_0402_5%

RH2319

@

12

RH1602 10K_0402_5%

@

12

RH1614 100K_0402_5%

VCC3BVCC3B

12

RH1618 10K_0402_5%

1 2 1 2 1 2

RH1607620_0402_1% RH161613_0402_1% RH160830_0402_1%

SATAGP1 SATAGP4 SATAGP2

VCCSTVCC3_SUS

12

RH1606 1K_0402_5%

SATA_PRX_DTX_N0 [61] SATA_PRX_DTX_P0 [61]

SATA2_PCIE16_CRX_DTX_N [62] SATA2_PCIE16_CRX_DTX_P [62]

-WWANRST [62]

PANEL_BKLT_CTRL [56] VGA_BLON [42] PANEL_POWER_ON [41]

-THERMTRIP [7,34] PECI [7,43] PM_SYNC [7]

-PCH_PLTRST_PROC [7] PM_DOWN [7]

RP1601

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

@

SATA_PTX_DRX_N0 [61] SATA_PTX_DRX_P0 [61]

PCIE3_CRX_DTX_N [61]

PCIE3_CRX_DTX_P [61]

PCIE3_CTX_C_DRX_N [61] PCIE3_CTX_C_DRX_P [61]

PCIE15_CRX_DTX_N [62] PCIE15_CRX_DTX_P [62]

PCIE15_CTX_DRX_N [62] PCIE15_CTX_DRX_P [62]

SATA2_PCIE16_CTX_DRX_N [62] SATA2_PCIE16_CTX_DRX_P [62]

-PE_DTCT [61]

-PE_DTCT_M2 [62]

VCC3_SUS

SATA-Express HDD

M2 SATA(PCIE)

To eDP

Title

Security Classification

Issued Date

NMB071_T470P_SVT_1114_for SMT

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

Issued Date

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCHSKL-H : SATA/PCIE

Size Document Number Re v

Custom

Tuesday, November 01, 2016

Date : Sheet of

1

NM-B071

16 99

0.2

5

www.vinaﬁx.com

TABLE : Functional Strap

HDA_SDO

Flash Descriptor Security Override

HIGH

Disable Flash Descriptor Security (Override)

LOW

Enable Flash Descriptor Security (Default)

HDA_SDO is used to update the Descriptor and/or the

D D

C C

B B

ME regions of the SPI after MFG Done bit is set.

PCH_HDA_BCLK[45]

PCH_HDA_RST#[45] PCH_HDA_SDOUT[45] PCH_HDA_SYNC[45]

PCH_HDA_SDIN0[45]

20140730: As of now, we cannot get information about these pins from SKL-H RVP and other documents. We need to confirm about them later.

PROC_AUDIO_SDO_CPU[6]

PROC_AUDIO_SDI_CPU[6]

PROC_AUDIO_CLK_CPU[6]

From RTC Reset circuits From CPU DCDC From ASIC From ASIC From/to DIMM

and TP From/to GBE

From/to EC

VCC3_SUS

12

RH1726

4.7K_0402_5%

PCH_HDA_BCLK PCH_HDA_RST# PCH_HDA_SDOUT PCH_HDA_SYNC

PROC_AUDIO_SDO_CPU PROC_AUDIO_SDI_CPU PROC_AUDIO_CLK_CPU PROC_AUDIO_CLK_PCH

-RTCRST[25,29]

-SRTCRST[25] CPUCORE_PWRGD[24,84]

-RSMRST[24,43] MPWRG[41,43]

SMB_CLK[68] SMB_DATA[68]

SML0_CLK[51] SML0_DATA[51]

EC_SCL2[43]

12

RH1725

4.7K_0402_5%

EC_SDA2[43]

12

RH1715

2.2K_0402_5%

FOLLOW WALTER CONNECTER TO GBE

RP1701

33_0804_8P4R_5%

1 8 2 7 3 6 4 5

2

CH1701 47P_0402_50V8-J

1

EMC_NS@

RH1709 30_0402_1% RH1710 30_0402_1%

1

TP1704Test_Point_32MIL

RH1713 0_0402_5%

RH1714 0_0402_5%

12

RH1716 499_0402_1%

HDA_BCLK_R

-HDA_RST_R HDA_SDO_R HDA_SYNC_R

HDA_BCLK_R

-HDA_RST_R PCH_HDA_SDIN0

HDA_SDO_R HDA_SYNC_R

PLACE NEAR PCH

DDI_PRIORITY2

1 2

12

RH1717 499_0402_1%

12 12

-SMB_ALERT SMB_CLK SMB_DATA

-SML0_ALERT SML0_CLK SML0_DATA

PCHHOT# EC_SCL2

EC_SDA2

12

RH1718

2.2K_0402_5%

Pullups on SMB are located in SMBUS Switch page.

A A

VCC3_SUS

RH1739 Pull up 150K follow MOW

INTEL FAE ADVICE

1 2

RH1738 2.2K_0402_5%@ RH1739 150K_0402_5%

12

NMB071_T470P_SVT_1114_for SMT

5

-SML0_ALERT

PCHHOT#

4

VCC3_SUS

12

RH1704 1K_0402_5%

Leave RSVD_BD1/BE2 NC

PROC_AUDIO_SDO_PCH

12

RH1719

2.2K_0402_5%

4

PLACE ON BOTTOM SIDE

RH1702 1K_0402_5%

1 2

1

Test_Point_20MIL

TEST PAD BOTTOM SIDE DO NOT MOVE AFTER FIX

AL42 AN42 AM43

AJ33 AH44

AJ35

AJ38

AJ42

BC10 BB10

AW11

BA11 AV11

BB41

AW44

BB43 BA40

AY44 BB39

AT27

AW42 AW45

RH1703 0_0402_5%

1 2

TP1701

TP1702

Test_Point_20MIL

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK GPP_D8/I2S0_SCLK

GPP_D7/I2S0_RXD GPP_D6/I2S0_TXD GPP_D5/I2S0_SFRM GPP_D20/DMIC_DATA0 GPP_D19/DMIC_CLK0 GPP_D18/DMIC_DATA1 GPP_D17/DMIC_CLK1

RTCRST# SRTCRST#

PCH_PWROK RSMRST#

DSW_PWROK GPP_C2/SMBALERT# GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C5/SML0ALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_B23/SML1ALERT#/PCHHOT# GPP_C6/SML1CLK GPP_C7/SML1DATA

SKYLAKE-H-PCH_FCBGA837

SMB_CLK SMB_DATA

SML0_CLK SML0_DATA

-SMB_ALERT

EC_SCL2 EC_SDA2

@

1

important

3

TABLE : Functional Strap

GPP_C5/SML0ALERT#(LPC or SPI)

HIGH

eSPI is selected

LOW

LPC is selected(Default)

TABLE : Functional Strap

GPP_C5/SML0ALERT#(TLS Confidentiality)

HIGH

Enable ME Crypto TLS with Confldentlality

LOW

Disable ME Crypto TLS(Default)

SPT-H_PCH

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

AUDIO

GPP_A13/SUSWARN#/SUSPWRDNACK

SMBUS

JTAG

4 OF 12

-SML0_ALERT

12

RH1727 1K_0402_5%

@

LPC is selected for EC. (Default) This PD is insurance in case internal PD doesn't work well.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

GPP_A8/CLKRUN# GPD11/LANPHYPC GPD9/SLP_WLAN#

GPP_B2/VRALERT#

GPP_G17/ADR_COMPLETE

GPP_B12/SLP_S0#

GPD10/SLP_S5#

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE# GPD1/ACPRESENT

GPD3/PWRBTN#

2015/07/16

DRAM_RESET#

GPP_B1 GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD8/SUSCLK

SLP_SUS#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAGX JTAG_TMS JTAG_TDO

JTAG_TDI

JTAG_TCK

VCC3B

12

RH1740 10K_0402_5%

BB17 AW22

-CLKRUN

AR15 AV13 BC14

-DRAMRST

BD23 AL27 AR27

-GPU_EVENT

N44 AN24 AY1

-PCIE_WAKE_R

BC13 BC15

-PCH_SLP_LAN_R

AV15 BC26 AW15 BD15 BA13

AN15 BD13 BB19

-SUSACK

BD19

-SUSWARN

Tied together For Deep Sx

BD11

-LANWAKE

BB15 BB13 AT13

-XDP_DBR

AW1 BD26

PROCPWRGD_PCH

AM3 AT2

AR3 AR2 AP1 AP2 AN3

12

RH1721 470_0402_5%

1

CH1702 22P_0402_50V8-J

2

EMC_NS@

LC Future Center Secret Data

Deciphered Date

@

RH1711 0_0402_5% RH1728 0_0402_5%

RH1729 0_0201_5% RH1730 0_0402_5% RH1731 0_0402_5% RH1732 0_0402_5% RH1733 0_0402_5% RH1734 0_0402_5%

RH1735 0_0402_5% RH1712 0_0201_5%

RH1736 0_0201_5% RH1737 0_0402_5%

RH1720 0_0402_5%

1

TP1703Test_Point_32MIL

RH1744 51_0402_1%

@

1 2

RH1722

8.2K_0402_5%

1 2

2

1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

1 2

2

VCC3M VCC3M

12

RH1742 10K_0402_5%

@

TABLE : Functional Strap

GPP_B14/SPKR(Top Swap Owerride)

HIGH LOW

VCC3B

12

RH1741 3K_0402_5%

@

1

CH1703

0.1U_0402_25V6-K

2

@

2016/01/16

12

RH1743 10K_0402_5%

@

Enable "TOP Swap" Mode Disable "TOP Swap" Mode (Default by Internal PD)

VCC3_SUS

12

RH1745 10K_0402_5%

Title

PCH SKL-H : AUDIO/SMBUS/JTAG

Size Document Number Re v

Custom

Date: Sheet of

-CLKRUN [42,68] LANPHYPC [51]

-PCH_SLP_WLAN [43]

-DRAMRST [27,28]

-GPU_EVENT [34]

BPWRG [24,41,43]

-PCIE_WAKE [40,62]

-PCH_SLP_M [29,40]

-PCH_SLP_LAN [44]

-PCH_SLP_S0 [29,70]

-PCH_SLP_S3 [29,40,43,89]

-PCH_SLP_S4 [29,40,43]

-PCH_SLP_S5 [29,40] SUSCLK_32K [42,62]

-BATLOW [44]

-LANWAKE [51] AC_PRESENT [43]

-PCH_SLP_SUS [43]

-PWRSW_EC [43]

-XDP_DBR [24,29] PCH_SPKR [46] PROCPWRGD_CPU [7]

JTAGX [24] PCH_TMS [24] PCH_TDO [24] PCH_TDI [24] PCH_TCK [24]

VCC3MVCC1R2A VCC3B

12

Tuesday, November 01, 2016

RH1723 10K_0402_5%

@

-XDP_DBR

-CLKRUN

-DRAMRST

12

RH1724 1K_0402_5%

1

from LPC Device(EC) to GBE

to M.2 WLAN

to DIMM/SMBU SW

SKL-H PCH doenn't require CORE VDD

to PHY PLL power FET from ASIC

from M.2 WLAN Slot to ASIC to ASIC

to EC/FPR/ASIC/DebugPort to EC/ASIC/DebugPort to ASIC

to EC/ASIC/WLAN from ASIC

from GBE from ASIC to EC from EC from XDP port to Audio Mixer

to/from debug port

-PCIE_WAKE_R

-PCH_SLP_LAN_R

NM-B071

17 99

1

17 99

0.2

5

4

3

2

1

to be confirm on SDV

RH1816 100K_0402_5%@ RH1814 100K_0402_5%NODPRE@ RH1817 100K_0402_5% RH1815 100K_0402_5%

D D

1 2 1 2 1 2 1 2

DDIP2_HPD : PS8330 has Int.PD 150K

HDMI_DDIP1_HPD MDP_DDIP2_HPD DOCK_DDIP3_HPD CPU_EDP_HPD

12

RH1818

2.2K_0402_5%

@

VCC3B

12

RH1812

2.2K_0402_5%

12

RH1813

2.2K_0402_5%

12

RH1807

2.2K_0402_5%

@

-SC_DTCT [65]

-TAMPER_SW_DTCT [14]

12

SmartCard

RH1806

2.2K_0402_5%

@

12

RH1810

2.2K_0402_5%

12

RH1811

2.2K_0402_5%

VCC3_SUS

12

RH1808 10K_0402_5%

@

12

RH1809 10K_0402_5%

@

MDP_DDIP2_CTRLCLK [58,59]

MDP_DDIP2_CTRLDATA [58,59]

HDMI_DDIP1_CTRLCLK [57]

HDMI_DDIP1_CTRLDATA [57]

DOCK_DDIP3_CTRLCLK [60]

DOCK_DDIP3_CTRLDATA [60]

VCC3B

UH1E

1 2

C C

VCC3B

B B

HDMI_DDIP1_HPD[57] MDP_DDIP2_HPD[58,59] DOCK_DDIP3_HPD[60]

CPU_EDP_HPD[56]

Modify PLANARID[3:0] to Int. PU 20K

1 2

RH1801 10K_0402_5%@

1 2

RH1802 10K_0402_5%@

1 2

RH1803 10K_0402_5%@

1 2

RH1804 10K_0402_5%@

1 2

RH1819 0_0402_5%@

1 2

RH1822 0_0402_5%@

1 2

RH1820 0_0402_5%@

1 2

RH1821 0_0402_5%@

RH1805 0_0402_5%

1 2

RH1823 0_0402_5%

PLANARID0 PLANARID1 PLANARID2 PLANARID3

PLANARID0 [16] PLANARID1 [16] PLANARID2 [15] PLANARID3 [15]

EXT_DP_HPD_I

TABLE

SDV FVT SIT SVT

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKYLAKE-H-PCH_FCBGA837

3 0

1 1 1 1

SPT-H_PCH

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

5 OF 12

PLANAR ID

2 1 0 0 0 0 0 100

0100

GPP_F14 GPP_F23 GPP_F22

GPP_G23 GPP_G22 GPP_G21 GPP_G20 GPP_H23

BB3 BD6 BA5 BC4 BE5 BE6

Y44 V44 W39

L43 L44 U35 R35 BD36

SVT internal PU

-DGFX_WITH_DISPLAYOUT

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCH SKL-H : DDI CONTROL

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, November 01, 2016

NM-B071

1

18 99

0.2

5

4

3

2

1

VCC3_SUS_SPI

D D

USB3P1_TXN[63]

System Port 1 (Right-Front)

System Port 2 (Right-Back)

C C

Small Board

DOCKING

USB3P1_TXP[63] USB3P1_RXN[63] USB3P1_RXP[63] USB3P2_TXN[63]

USB3P2_TXP[63] USB3P2_RXN[63] USB3P2_RXP[63]

USB3P3_TXP[64] USB3P3_TXN[64]

USB3P3_RXP[64] USB3P3_RXN[64]

USB3P4_TXP_DOCK[60]

USB3P4_TXN_DOCK[60] USB3P4_RXP_DOCK[60] USB3P4_RXN_DOCK[60]

USB3P1_TXN USB3P1_TXP USB3P1_RXN USB3P1_RXP USB3P2_TXN USB3P2_TXP USB3P2_RXN USB3P2_RXP

USB3P3_TXP USB3P3_TXN USB3P3_RXP USB3P3_RXN

USB3P4_TXP_DOCK USB3P4_TXN_DOCK USB3P4_RXP_DOCK USB3P4_RXN_DOCK

UH1F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

LPC/eSPI

USB

SATA

6 OF 12

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI# GPP_G18/NMI#

GPP_E6/DEVSLP2 GPP_E5/DEVSLP1 GPP_E4/DEVSLP0 GPP_F9/DEVSLP7 GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4 GPP_F5/DEVSLP3

AT22 AV22 AT19 BD16

BE16 BA17 AW17 AT17 BC18

BC17

RH1928 22_0402_5% EMC@

AV19

RH1929 22_0402_5% EMC_NS@

M45 N43

AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

1 2 1 2

DEVSLP2 DEVSLP1

SATA0_DEVSLP0

-WWAN_CFG1

-WWAN_CFG0 DEVSLP5

TS_EN SSD_DEVSLP3

12

RH1932 10K_0402_5%

@

1 2

RH1931 0_0402_5%

1

CH1901 47P_0402_50V8-J

2

RF@

-WWAN_CFG2[16,62]

VCC3B

12

RH1930

8.2K_0201_1%

DEVSLP1 DEVSLP5

DEVSLP2

SATA0_DEVSLP0

-WWAN_CFG2 SSD_DEVSLP3

-WWAN_CFG1

LPC_AD0 [42,68] LPC_AD1 [42,68] LPC_AD2 [42,68] LPC_AD3 [42,68]

-LPC_FRAME [42,68] IRQSER [42,68]

-TPM_IRQ [55]

-KBRC [42]

-SUS_STAT [42,68]

LPCCLK_EC_24M [42] LPCCLK_DEBUG_24M [68]

SATA0_DEVSLP0 [61]

-WWAN_CFG1 [62]

-WWAN_CFG0 [62] TS_EN [56]

SSD_DEVSLP3 [62]

RP1901

1 8 2 7 3 6 4 5

10K_0804_8P4R_5% @

RP1902

1 8 2 7 3 6 4 5

10K_0804_8P4R_5% @

VCC3B

B B

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCH SKL-H : USB3/LPC

Size Document Number Re v

Date: Sheet of

NM-B071

Tuesday, November 01, 2016

19 99

1

19 99

0.2Custom

5

4

3

2

1

D D

CPU_REFCLK_24M[7]

-CPU_REFCLK_24M[7] CPU_BCLK_100M[7]

-CPU_BCLK_100M[7]

C C

VCC3B

RP2001

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

1 2

RH2012 10K_0402_5%

1 2

RH2018 10K_0402_5%

CLKREQ_PCIE0_WLAN# CLKREQ_PCIE1_SATA# CLKREQ_PCIE6_CACHE# CLKREQ_PCIE3_LAN#

CLKREQ_PCIE4_CR# CLKREQ_PCIE5_VGA#

VCC1R0_SUS

1 2

RH2005 2.71K_0402_0.5%

CLKREQ_PCIE0_WLAN#[62] CLKREQ_PCIE1_SATA#[61]

CLKREQ_PCIE3_LAN#[51] CLKREQ_PCIE4_CR#[54] CLKREQ_PCIE5_VGA#[31] CLKREQ_PCIE6_CACHE#[62]

XTAL24_OUT XTAL24_IN

XCLK_BIASREF

RTCX1 RTCX2

CLKREQ_PCIE0_WLAN# CLKREQ_PCIE1_SATA#

CLKREQ_PCIE3_LAN# CLKREQ_PCIE5_VGA#

CLKREQ_PCIE6_CACHE#

UH1G

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

7 OF 12

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10 CLKOUT_PCIE_P10

CLKOUT_PCIE_N11 CLKOUT_PCIE_P11

L1 L2

J1 J2

N7 N8

L7 L5

D3 F2

E5 G4

D5 E6

D8 D7

R8 R7

U5 U7

W10 W11

N3 N2

P3 P2

R3 R4

-CPU_PCI_BCLK_100M CPU_PCI_BCLK_100M

CLK_PCIE_WLAN# CLK_PCIE_WLAN

CLK_PCIE_SATA# CLK_PCIE_SATA

CLK_PCIE_LAN# CLK_PCIE_LAN

CLK_PCIE_CR#CLKREQ_PCIE4_CR# CLK_PCIE_CR

CLK_PCIE_VGA# CLK_PCIE_VGA

CLK_PCIE_WWAN# CLK_PCIE_WWAN

-CPU_PCI_BCLK_100M [7] CPU_PCI_BCLK_100M [7]

CLK_PCIE_WLAN# [62]

CLK_PCIE_WLAN [62]

CLK_PCIE_SATA# [61]

CLK_PCIE_SATA [61]

CLK_PCIE_LAN# [51]

CLK_PCIE_LAN [51]

CLK_PCIE_CR# [54]

CLK_PCIE_CR [54] CLK_PCIE_VGA# [31]

CLK_PCIE_VGA [31]

CLK_PCIE_WWAN# [62]

CLK_PCIE_WWAN [62]

WLAN

SATA PCIE

LAN

CR

VGA

Optane

PCIE Clock Assignment Clock Request

RP2002

@ 1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

1 2

B B

RH2015 10K_0402_5%@

1 2

RH2013 10K_0402_5%@

CLKREQ_PCIE0_WLAN# CLKREQ_PCIE1_SATA# CLKREQ_PCIE6_CACHE# CLKREQ_PCIE3_LAN#

CLKREQ_PCIE4_CR# CLKREQ_PCIE5_VGA#

Clock 0 : WLAN Clock 1 : SATA-Express Clock 3 : Giga LAN Clock 4 : CARD READER Clock 5 : GPU N16S-GTR Clock 6 : Optane

CLKREQ0# CLKREQ1# CLKREQ3# CLKREQ4# CLKREQ5# CLKREQ6#

CH2001 15P_0402_50V8-J

1 2

Y2001

32.768KHZ_12.5PF_9H03200042

CH2002

1 2

12P_0402_50V8-J

1 2

CH2003 4.7P_0402_50V8-J

A A

1 2

24MHZ_6PF_8Y24000009

CH2004

4.7P_0402_50V8-J

NMB071_T470P_SVT_1114_for SMT

5

Y2002

1

4 2

3

12

RH2006 10M_0402_5%

12

RH2007 1M_0402_5%

RTCX1

RTCX2

0_0402_5%

1 2

RH2323

0_0402_5%

1 2

RH2324

XTAL24_OUT

XTAL24_IN

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCH SKL-H : CLK

Size Document Number Re v

Custom

Tuesday, November 01, 2016

Date: Sheet of

Tuesday, November 01, 2016

NM-B071

1

20 99

0.2

5

D D

4

3

2

VCC3_SUS

1

3.137A

1.0V

VCC1R0_SUS

1

CH2101 22U_0603_6.3V6M

2

@

C C

4.110A

1.0V

VCC1R0_SUS

1

CH2111 22U_0603_6.3V6M

2

1

CH2112 1U_0402_10V6-K

2

1

CH2102 22U_0603_6.3V6M

2

@

VCCMPHYPLL_1P0

1

CH2103 22U_0603_6.3V6M

2

@

1

CH2110 1U_0402_6.3V6-K

2

SE000000KMT

NEAR K2

NEAR BA29

NEAR PCH PKG

VCCAPLLEBB_1P0 VCCUSB2PLL_1P0

VCC3M

VCCHDAPLL_1P0

VCC3_SUS

1

CH2115

0.1U_0402_25V6-K

2

@

NEAR

B B

W15

1

CH2127

0.1U_0201_6.3V6-K

2

RF@

0.11A

1.0V

VCC1R0_SUS

1 2

RH2101 0_0603_5%

1

CH2116 22U_0603_6.3V6M

2

@

VCCMPHYPLL_1P0 VCCAPLLEBB_1P0 VCCUSB2PLL_1P0 VCCHDAPLL_1P0

1

CH2117 22U_0603_6.3V6M

2

@

1

CH2125 1U_0402_10V6-K

2

@

1

CH2128

0.1U_0201_6.3V6-K

2

RF@

0.03A

1.0V

VCC1R0_SUS

UH1H

AA23

VCCPRIM_1P0_1

AA26

VCCPRIM_1P0_2

AA28

VCCPRIM_1P0_3

AC23

VCCPRIM_1P0_4

AC26

VCCPRIM_1P0_5

AC28

VCCPRIM_1P0_6

AE23

VCCPRIM_1P0_7

AE26

VCCPRIM_1P0_8

Y23

VCCPRIM_1P0_9

Y25

VCCPRIM_1P0_10

BA29

DCPDSW_1P0

N17

VCCCLK1_1

R19

VCCCLK3_2

U20

VCCCLK4_3

V17

VCCCLK2_4

R17

VCCCLK2_5

K2

VCCCLK5_6

K3

VCCCLK5_7

U21

VCCMPHY_1P0_1

U23

VCCMPHY_1P0_2

U25

VCCMPHY_1P0_3

U26

VCCMPHY_1P0_4

V26

VCCMPHY_1P0_5

A43

VCCMPHYPLL_1P0_1

B43

VCCMPHYPLL_1P0_2

C44

VCCPCIE3PLL_1P0_1

C45

VCCPCIE3PLL_1P0_2

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0_16

AJ5

VCCUSB2PLL_1P0_1

AL5

VCCUSB2PLL_1P0_2

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3_1

SKYLAKE-H-PCH_FCBGA837

1 2

RH2102 0_0603_5%

SPT-H_PCH

CORE

MPHY

USB

8 OF 12

VCCGPIO

VCCPRIM_1P0_17

VCCDSW_3P3_2

VCCPGPPA

VCCPGPPBCH_1 VCCPGPPBCH_2

VCCPGPPEF_1 VCCPGPPEF_2

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0_15

VCCATS

VCCRTCPRIM_3P3

VCCRTC DCPRTC

VCCPRIM_1P0_11 VCCPRIM_1P0_12 VCCPRIM_1P0_13 VCCPRIM_1P0_14

VCCSPI_1 VCCSPI_2

VCCSPI_3 VCCPGPPD_1 VCCPGPPD_2 VCCPGPPD_3 VCCPGPPD_4

VCCPRIM_3P3_1 VCCPRIM_3P3_2 VCCPRIM_3P3_3

0.012A

1 2

RH2103 0_0603_5%

AL22 BA24

BA31 BC42

BD40 AJ41 AL41 AD41 AN5

AD15 AD13 BA20 BA22 BA26

AJ20 AJ21 AJ23 AJ25

BE41 BE43 BE42 BC44 BA45 BC45 BB45

BD3 BE3 BE4

VCC1R0_SUS

0.195A

VCC3M

0.029A

VCC3_SUS

1

CH2119 1U_0402_10V6-K

2

NEAR PCH PKG NEAR PCH PKG

1

CH2104

0.1U_0402_25V6-K

2

@

1

CH2113

0.1U_0402_25V6-K

2

NEAR BA26

0.033A

VCC1R0_SUSVCC1R0_SUS

1

CH2123

0.1U_0402_16V7-K

2

NEAR BA31

NEAR BC42

1

2

RH2104 0_0603_5%

1

CH2105

0.1U_0402_25V6-K

2

@

NEAR AJ41

CH2114

0.1U_0402_25V6-K

NEAR BA22

0.007A

VCC3B

1 2

1

CH2124

0.1U_0402_16V7-K

2

NEAR BA31

RTCVCC

1

CH2121 1U_0402_6.3V6-K

2

NEAR

1

AD13

CH2122 1U_0402_6.3V6-K

2

1

CH2120 1U_0402_10V6-K

2

1

CH2106

0.1U_0402_25V6-K

2

@

NEAR AD41

1

CH2107

0.1U_0402_25V6-K

2

@

NEAR AN5

1

CH2108

0.1U_0402_25V6-K

2

NEAR BA20

0.746A

VCC3_SUS

1

2

CH2109

0.1U_0402_25V6-K

NEAR AD13

NEAR PCH PIN

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCH SKL-H : POWER

Size Document Number Re v

T460P

Tuesday, November 01, 2016

Date: Sheet of

Tuesday, November 01, 2016

NM-B071

1

21 99

0.2Custom

5

D D

4

3

2

1

SPT-H_PCH

UH1I

AC18

VSS_1

AN4

VSS_2

AN10

VSS_3

BE14

VSS_4

BE18

VSS_5

BE23

VSS_6

BE28

VSS_7

BE32

VSS_8

BE37

VSS_9

BE40

VSS_10

BE9

VSS_11

C10

VSS_12

C2

VSS_13

C28

VSS_14

C37

VSS_15

J7

VSS_16

K10

VSS_17

K27

VSS_18

K33

VSS_19

K36

VSS_20

K4

VSS_21

K42

VSS_22

K43

VSS_23

L12

VSS_24

L13

C C

B B

VSS_25

L15

VSS_26

L4

VSS_27

L41

VSS_28

L8

VSS_29

M35

VSS_30

M42

VSS_31

N10

VSS_32

N15

VSS_33

N19

VSS_34

N22

VSS_35

N24

VSS_36

N35

VSS_37

N36

VSS_38

N4

VSS_39

N41

VSS_40

N5

VSS_41

P17

VSS_42

P19

VSS_43

P22

VSS_44

P45

VSS_45

R10

VSS_46

R14

VSS_47

R22

VSS_48

R29

VSS_49

R33

VSS_50

R38

VSS_51

R5

VSS_52

T1

VSS_53

T2

VSS_54

T4

VSS_55

Y18

VSS_56

Y20

VSS_57

Y21

VSS_58

Y26

VSS_59

Y28

VSS_60

Y29

VSS_61

A18

VSS_62

A25

VSS_63

A32

VSS_64

A37

VSS_65

AA17

VSS_66

AA18

VSS_67

AA20

VSS_68

AA21

VSS_69

AA25

VSS_70

AA29

VSS_71

AA4

VSS_72

AA42

VSS_73

AB10

VSS_74

9 OF 12

SKYLAKE-H-PCH_FCBGA837

VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98

VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148

AR5 AR7 U15 AL4 AE29 AE4 AE42 AF18 AF20 AF21 AF23 AF25 AF26 AF28 AF29 AG11 AG13 AG31 AG32 AG33 AG38 AG4 AH1 AH17 AH18 AH20 AH21 AH23 AH25 AH26 AH28 AH29 AH45 AJ10 AJ14 AJ15 AJ17 AJ18 AJ26 AJ28 AJ29 AJ31 AJ32 AJ36 AK4 AK42 AU7 AV17 AV24 AV27 AV31 AV33 AV6 AW13 AW19 AW29 AW37 AW9 AY38 AY45 B25 B3 B37 B40 B6 BA1 BB11 BB16 BB21 BB25 BB30 BB34 BC2 BD43

SPT-H_PCH

UH1L

C42

VSS_149

D10

VSS_150

D12

VSS_151

D15

VSS_152

D16

VSS_153

D17

VSS_154

D19

VSS_155

D21

VSS_156

D24

VSS_157

D25

VSS_158

D27

VSS_159

D29

VSS_160

D30

VSS_161

D31

VSS_162

D33

VSS_163

D35

VSS_164

D36

VSS_165

E13

VSS_166

E15

VSS_167

E31

VSS_168

E33

VSS_169

F44

VSS_170

F8

VSS_171

G42

VSS_172

G9

VSS_173

H17

VSS_174

H19

VSS_175

H22

VSS_176

H24

VSS_177

H27

VSS_178

H29

VSS_179

H3

VSS_180

H35

VSS_181

J10

VSS_182

J11

VSS_183

J3

VSS_184

J39

VSS_185

J5

VSS_186

T42

VSS_187

U10

VSS_188

U11

VSS_189

U14

VSS_190

U17

VSS_191

U18

VSS_192

U28

VSS_193

U29

VSS_194

U31

VSS_195

U32

VSS_196

U33

VSS_197

U38

VSS_198

U4

VSS_199

U8

VSS_200

V18

VSS_201

V20

VSS_202

V21

VSS_203

V23

VSS_204

V25

VSS_205

V29

VSS_206

V3

VSS_207

V45

VSS_208

W14

VSS_209

W31

VSS_210

W32

VSS_211

W33

VSS_212

W38

VSS_213

W4

VSS_214

W8

VSS_215

Y17

VSS_216

12 OF 12

SKYLAKE-H-PCH_FCBGA837

VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285

AB11 AB7 AB14 AB31 AB32 AB38 AB4 AB5 AC1 AC20 AC21 AC25 AC29 AC45 AB8 AD11 AD14 AB15 AD32 AD33 AD36 AD4 AD8 AE18 AE20 AE21 AE25 AE28 AL10 AL11 AL13 AL17 AL19 AL24 AL29 AL32 AL33 AL38 AM15 AM17 AM19 AM22 AM24 AM27 AM29 AM45 AN11 AN22 AN27 AN31 AN39 AN7 AN8 AP11 AP4 AR33 AR34 AR42 AR9 AT10 AT15 AT36 AT9 AU1 AU35 AU36 AU39 AU45 C4

UH1J

BD2

VSS_286

BD45

VSS_287

BD44

VSS_288

BE44

VSS_289

D45

VSS_290

A42

VSS_291

B45

VSS_292

B44

VSS_293

A4

VSS_294

A3

VSS_295

B2

VSS_296

A2

VSS_297

B1

VSS_298

BB1

VSS_299

BC1

VSS_300

A44

VSS_301

C1

RSVD_5

D1

RSVD_6

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

10 OF 12

RSVD_7 RSVD_8

RSVD_9 RSVD_10 RSVD_11

RSVD_12 RSVD_13 RSVD_14 RSVD_15 RSVD_16 RSVD_17 RSVD_18

PREQ# PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

AR22 W13 U13 P31 N31

Leave as NC

P27 R27 N29 P29 AN29 R24 P24

AT3 AT4 AY5

PCH_2_CPU_TRIGGER_L

AL2 AK1

-PCH_PREQ [24]

-PCH_PRDY [24]

-CPU_TRST [24]

RH2201 30_0402_1%

12

CPU_2_PCH_TRIGGER [13]

PCH_2_CPU_TRIGGER [13]

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCH SKL-H : GND/RSVD

Size Document Number Re v

Custom

Tuesday, November 01, 2016

Date: Sheet of

Tuesday, November 01, 2016

NM-B071

1

22 99

0.2

5

D D

4

3

2

1

VCC3B

GPP_B18_NO_REBOOT[24]

C C

From EC

B B

-EC_WAKE[42]

-EC_SCI[42]

RH2313~2316 FOR BIOS DEBUG, SS REMOVE

12

RH2314 10K_0402_5%

@

12

RH2313 10K_0402_5%

@

12

RH2315 10K_0402_5%

@

12

RH2316 10K_0402_5%

@

12

RH2320 10K_0402_5%

@

12

RH2321

VPRO@

0_0402_5%

GPP_B18_NO_REBOOT

1 2

RH2309 0_0402_5%

1 2

RH2310 0_0402_5%

1 2

RH2311 0_0201_5%

1 2

RH2312 0_0402_5%

Leave as NC

UH1K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

GPP_D9 GPP_D10 GPP_D11

GPP_D16/ISH_UART0_CTS#

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

GPP_D15/ISH_UART0_RTS#

11 OF 12

GPP_D12

GPP_H20/ISH_I2C0_SCL

GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL

GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0 GPP_A17/ISH_GP7

-DISCRETE_PRESENCE

AL44 AL36

WALTER_P_T

AL35

PCH_3VIDEO_ON

AJ39

FB_GC6_EN_R-VPRO_SUPPORT

AJ43 AL43 AK44 AK45

BC38 BB38

BD38 BE39

BC22 BD18 BE21 BD22

Leave as NC

BD21 BB22 BC19

GPP_ D9

VCC3_SUS

12

RH2301 10K_0402_5%

DIS@

12

RH2305 10K_0402_5%

@

12

RH2307 10K_0402_5%

GC6@

12

RH2306 10K_0402_5%

DIS@

12

RH2308 10K_0402_5%

DIS@

HIGHLOW

12

RH2303 10K_0402_5%

DIS@

12

RH2304 10K_0402_5%

@

12

RH2317 10K_0402_5%

UMA@

12

RH2302 10K_0402_5%

DIS@

GPU_ALL_PGOOD [31,34]

PCH_3VIDEO_ON [35,93]

FB_GC6_EN_R [34]

-PCH_GPU_RST [34]

DIS UMA

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

PCH SKL-H : GSPI/UART/I2C

Size Document Number Re v

Custom

Tuesday, November 01, 2016

Date: Sheet of

Tuesday, November 01, 2016

NM-B071

1

23 99

0.2

5

4

3

2

1

R2420,R2422,R2423,R2407,R2410,R2413,R2415,R2401 NEAR BY PCH

R2416 100_0402_1%

1 2

R2417 0_0402_5%@ R2418 0_0402_5%@

R2420 0_0402_5%@ R2419 0_0402_5%@ R2421 0_0402_5%@ R2431 0_0402_5%@ R2424 0_0402_5%@

R2430 0_0402_5%@ R2403 1K_0402_5%@ R2425 1K_0402_5%@

R2426 0_0402_5%@

R2404 1K_0402_5%@ R2427 0_0402_5%@

R2428 0_0402_5%@ R2429 0_0402_5%@

XDP_TCK_R

-XDP_TRST_R

1 2

1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2

1 2

1 2 1 2

VCC3B VCC1R0_SUSVCCST

2

C2401

0.1U_0402_25V6-K R2402 1K_0402_5%

@

1 2

12

TDI TDO

12

R2405 1K_0402_1%

@

XDP_TCK_R

-XDP_TRST_R

-XDP_PRDY_R

-XDP_PREQ_R

1

@

JXDP1

26

25

25 2424GND_1

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

MOLEX_52435-2671

ME@

GND_2

28 27

SP011004281

R2407 0_0402_5%@

JTAGX[17]

VCC1R0_SUS

R2433 51_0402_1%

@

1 2

PCH_TMS[17] PCH_TDI[17]

-CPU_TRST[22] PCH_TDO[17]

-PCH_PRDY[22]

-PCH_PREQ[22]

PCH_TMS

-RSMRST

TABLE : CPU ITP DEBUG REPORT

No use

D D

R591 R593 R594 R595 R596 R657 R658

R102 R597 R9907

JXDP1

C70 R96 R101 ASM R9909

C C

R9910 R9916 R99 R9912 ASMASM R9934 R9930 R9931 R9932 R9933

NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM

NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM

LOGIC

Individual Port

NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM

ASM ASM ASM ASM ASM ASM

ASM ASM ASM ASM

ASM ASM ASM ASM ASM

TABLE : PCH ITP DEBUG REPORT

No use DCI 2.0

B B

R93

JXDP1

R9917 R101 R9908

R9911

R9913 R9915

NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM

Individual Port

ASM ASM ASM ASM ASM ASM ASM ASM

DCI 2.0

w/o connector

ASM ASM ASM ASM ASM ASM ASM

NO ASM NO ASM

ASM

NO ASM NO ASM NO ASM NO ASM

ASM ASM ASM ASM

ASM ASM ASM ASM ASM

w/o connector

NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM NO ASM

PCH_TDI PCH_TDO

PCH_TCK[17] XDP_TCK[7]

XDP_TMS[7] XDP_TDI[7]

-XDP_TRST[7] XDP_TDO[7]

-XDP_DBR[17,29]

-PLTRST_FAR[14,54,61] CPUCORE_PWRGD[17,84]

BPWRG[17,41,43]

-RSMRST[17,43] CFG3[7]

-XDP_PRDY[7]

-XDP_PREQ[7]

JTAGX

PCH_TMS PCH_TDI

-CPU_TRST PCH_TDO

-PCH_PRDY -XDP_PRDY_R

-PCH_PREQ -XDP_PREQ_R

VCC1R0_SUS

R2401 51_0402_1%

@

1 2

R2422 0_0402_5%@ R2423 0_0402_5%@

1 2

R2410 0_0402_5%@

1 2

R2413 0_0402_5%@ R2415 0_0402_5%@

1 2

VCCST

R2432 51_0402_1%

@

1 2

TDI TDO

LOGIC

TABLE : Functional Strap

GPP_B18/GSPI0_MOSI (No Reboot)

Enable "No Reboot" Mode

HIGH LOW Disable "No Reboot" Mode (Default )

A A

R2406

ASM NO ASM

NMB071_T470P_SVT_1114_for SMT

5

LOGIC

VCC3_SUS

12

R2406 1K_0402_5%

@

GPP_B18_NO_REBOOT

4

Place near PCH

GPP_B18_NO_REBOOT [23]

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

XDP CONNECTOR

Size Document Number Re v

T470P

Wednesday, October 12, 2016

Date : Sheet of

1

NM-B071

24 99

0.2Custom

5

D D

C C

Max 3.4x[43/(3.01+43)]=3.17V

4

VCC3SW

12

R2504

3.01K_0402_1%

12

R2505 43K_0402_1%

12

D2502 RB520CS-30GT2RA_VMN2-2

R2501 1K_0402_5%

1 2

3

D2501 RB520CS-30GT2RA_VMN2-2

1 2

RTCVCC

1

C2501 1U_0402_10V6K

2

@

2

RTCVCC must be less than 3.2V from SKL. Need to consider voltage divider etc.

Use Screened ROHM and Toshiba, and change VCC3SW 1uF to 2.2uF and remove one 1uF on RTCVCC

1

JRTC1

1

2

3

GND1

4

GND2

TE_2041180-2

ME@

SP011309101

B B

A A

R2502 33K_0402_1%

1 2

R2503 33K_0402_1%

1 2

1

C2502 1U_0402_10V6K

2

1

C2503 1U_0402_10V6K

2

-RTCRST

-SRTCRST

JCMOS1 SHORT PADS

1 2

@

JME1 SHORT PADS

1 2

@

-RTCRST [17,29]

-SRTCRST [17]

RF

RTCVCC RTCVCC

1

C2505 100P_0402_50V8J

2

RF@

1

2

C2504 47P_0402_50V8-J

RF_NS@

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

RTC BATTERY

Size Document Number Re v

Custom

Wednesday, October 12, 2016

Date: Sheet of

Wednesday, October 12, 2016

NM-B071

1

25 99

0.2

5

Need to Pull Down 1K to IO3(hold funct i on)

D D

4

3

U2601 SPI ROM

2

1

vPRO model(16MB)

WINBOND W25Q128FVSIQ MACRONIX MX25L12873FM2I-10G MICRON N25Q128A13ESEC0F

VCC3_SUS

VCC3_SUS_SPI

C C

12

R2611

VCC3_SUS_SPI

R2610 1K_0402_1%

@

12

SPI_CLK[14,55]

SPI_MOSI_IO0[14,55]

SPI_MISO_IO1[14,55]

SPI_IO2[14]

B B

SPI_CLK SPI_MOSI_IO0 SPI_MISO_IO1 SPI_IO2

R2609 1K_0402_1%

@

12

R2602 1K_0402_1%

12

R597 1K_0402_1%

@

RP2601

18 27 36 45

33_0804_8P4R_5%

SPI_CLK_R SPI_MOSI_IO0_R SPI_MISO_IO1_R SPI_IO2_R

SPI_IO3[14]

SPI_IO3

SDV use ES sample for CPU and PCH,

1K_0402_1%

12

R2601 1K_0402_1%

@

1 2

R2604 33_0402_5%

1 2

1

2

1 2

R2612 0_0402_5%

EMC_NS@

EMI

C2603

0.1U_0402_10V6-K

EMC_NS@

D2601 RB520CS-30GT2RA_VMN2-2

1

C2601

0.1U_0402_25V6-K

2

VCC3_SUS_SPI -SPI_CS0_R SPI_IO3_R SPI_CLK_R SPI_MOSI_IO0_R

1

C2602

0.1U_0402_25V6-K

2

U2601

8

VCC

7

/HOLD/RESET(IO3)

6

CLK

5

DI(IO0)

W25Q128FVSIQ_SO8

SA00005LW00

DO(IO1)

/WP(IO2)

GND

1

/CS

SPI_MISO_IO1_R

2

SPI_IO2_R

3 4

1 2

R2603 0_0402_5%

-SPI_CS0 [14]

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

SPI FLASH

Size Document Number Re v

Custom

Wednesday, November 09, 2016

Date: Sheet of

Wednesday, November 09, 2016

NM-B071

1

26 99

0.2

5

M_A_DQ[0..63] [3] M_A_A[0..9] [3]

-M_A_DQS[0..7] [3] M_A_DQS[0..7] [3]

R2709 2_0402_1%

M_A_VREF_CA_CPU[4]

D D

1 2

1

C2727

0.022U_0402_25V7-K

2

12

R2711

24.9_0402_1%

VCC1R2A

12

R2708

1K_0402_1%

M_A_VREF_CA_CHA_DIMM

12

R2710

1K_0402_1%

12

4

VCC1R2A VCC2R5A

VCC1R2A

C2731

0.1U_0402_16V7-K

1

C2701 10U_0402_6.3V6-M

2

C2716 1U_0402_6.3V6-K

1

C2702 10U_0402_6.3V6-M

2

C2717 1U_0402_6.3V6-K

1

C2703 10U_0402_6.3V6-M

2

C2718 1U_0402_6.3V6-K

3

1

C2704 10U_0402_6.3V6-M

2

C2719 1U_0402_6.3V6-K

1

C2705 10U_0402_6.3V6-M

2

C2720 1U_0402_6.3V6-K

1

C2706 10U_0402_6.3V6-M

2

C2721 1U_0402_6.3V6-K

1

2

C2722 1U_0402_6.3V6-K

C2707 10U_0402_6.3V6-M

C2723 1U_0402_6.3V6-K

2

1

C2708 10U_0402_6.3V6-M

2

1

+

C2724 330U_D2_2VM_R9M

2

1

C2709 10U_0402_6.3V6-M

2

VCC0R6B

1

C2713 10U_0402_6.3V6-M

2

1

C2710 10U_0402_6.3V6-M

2

1

C2714 10U_0402_6.3V6-M

2

1

C2711 1U_0402_6.3V6-K

C2715 1U_0402_6.3V6-K

C2712 1U_0402_6.3V6-K

VCC1R2A VCC1R2A

M_A_DQ4 M_A_DQ0

-M_A_DQS0

C2734 68P_0402_50V8-J

RF@

5

M_A_DQS0 M_A_DQ7 M_A_DQ3 M_A_DQ13 M_A_DQ12

M_A_DQ15 M_A_DQ14 M_A_DQ21 M_A_DQ20

-M_A_DQS2 M_A_DQS2

M_A_DQ22 M_A_DQ18 M_A_DQ29 M_A_DQ28

M_A_DQ27 M_A_DQ30

M_A_BG1 M_A_BG0

M_A_A12 M_A_A9

M_A_A8 M_A_A6

1

NMB071_T470P_SVT_1114_for SMT

C2735 68P_0402_50V8-J

2

RF@

C C

B B

M_A_CKE0[3] M_A_BG1[3]

M_A_BG0[3] M_A_A12[3]

A A

RF

VCC1R2A VCC1R2A VCC0R6B

1

C2732 68P_0402_50V8-J

2

RF@

1

2

JDIMM1A

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129

FOX_AS0A826-H4RB-7H

SP071407021

1

C2736 68P_0402_50V8-J

2

RF@

VSS_1 DQ5 VSS_3 DQ1 VSS_5 DQS0_C DQS0_t VSS_8 DQ7 VSS_10 DQ3 VSS_12 DQ13 VSS_14 DQ9 VSS_16 DM1_n/DBl1_n VSS_17 DQ15 VSS_19 DQ10 VSS_21 DQ21 VSS_23 DQ17 VSS_25 DQS2_c DQS2_t VSS_28 DQ23 VSS_30 DQ19 VSS_32 DQ29 VSS_34 DQ25 VSS_36 DM3_n/DBl3_n VSS_37 DQ30 VSS_39 DQ26 VSS_41 CB5/NC VSS_43 CB1/NC VSS_45 DQS8_c DQS8_t VSS_48 CB2/NC VSS_50 CB3/NC VSS_52 CKE0 VDD_1 BG1 BG0 VDD_3 A12 A9 VDD_5 A8 A6 VDD_7

VSS_2 VSS_4 VSS_6

DM0_n/DBl0_n

VSS_7 VSS_9

VSS_11

DQ12

VSS_13 VSS_15

DQS1_c

DQS1_t VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24

VSS_35

DQS3_c

DQS3_t VSS_38

DQ31

VSS_40

DQ27 VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

DM8_n/DBl8_n/NC

VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

CKE1

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

1

C2733 100P_0402_50V8J

2

RF@

ME@

DQ4 DQ0

DQ6 DQ2

DQ8

A11

A7 A5

A4

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

1

C2737 68P_0402_50V8-J

2

RF@

M_A_DQ1 M_A_DQ5

M_A_DQ6 M_A_DQ2 M_A_DQ9 M_A_DQ8

-M_A_DQS1 M_A_DQS1

M_A_DQ10 M_A_DQ11 M_A_DQ16 M_A_DQ17

M_A_DQ19 M_A_DQ23 M_A_DQ24 M_A_DQ25

-M_A_DQS3 M_A_DQS3

M_A_DQ26 M_A_DQ31

M_A_DDRCLK0_1066M[3]

-M_A_DDRCLK0_1066M[3]

VCC3B VCC3B VCC3B

12

R2701 0_0402_5%

@

SA0_CHA_P SA1_CHA_P SA2_CHA_P

12

R2704 0_0402_5%

12

R2702 0_0402_5%

@

12

R2705 0_0402_5%

M_A_PARITY[3]

M_A_BA1[3]

-M_A_CS0[3]

M_A_A14_WE_N[3]

M_A_ODT0[3]

-M_A_CS1[3] M_A_ODT1[3]

12

R2703 0_0402_5%

@

R2706 0_0402_5%

M_A_DDRCLK0_1066M

-M_A_DDRCLK0_1066M

SPD Address = 0H

-DRAMRST M_A_CKE1M_A_CKE0

-M_A_ACT

-M_A_ALERT M_A_A11

M_A_A7 M_A_A5

M_A_A4

1

C2739 100P_0402_50V8J

2

RF@

4

-DRAMRST [17,28] M_A_CKE1 [3]

-M_A_ACT [3]

-M_A_ALERT [3] M_A_A11 [3]

1

C2728

0.1U_0402_10V7-K

2

@

1

C2738 68P_0402_50V8-J

2

RF@

VCC3B

R2707 0_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

SMB_CLK_3B[28,67,68]

1

C2725

0.1U_0402_10V7-K

2

2015/07/16

3

VCC1R2A

M_A_A3 M_A_A1

M_A_PARITY

M_A_BA1

-M_A_CS0

M_A_A14_WE_N

M_A_ODT0

-M_A_CS1 M_A_ODT1

M_A_DQ33 M_A_DQ37

-M_A_DQS4 M_A_DQS4

M_A_DQ38 M_A_DQ39 M_A_DQ44 M_A_DQ41

M_A_DQ43 M_A_DQ46 M_A_DQ50 M_A_DQ52

-M_A_DQS6 M_A_DQS6

M_A_DQ54 M_A_DQ51 M_A_DQ57 M_A_DQ61

M_A_DQ62 M_A_DQ58

SMB_CLK_3B

1

C2726

2.2U_0402_6.3V6-M

2

LC Future Center Secret Data

VCC1R2AVCC2R5A

Deciphered Date

JDIMM1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

A14/WE_n

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQS5

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4RB-7H

SP071407021

2016/01/16

2

EVENT_n/NF

CK1_c/NF

A16/RAS_n A15/CAS_n

C0/CS2_n/NC

DM4_n/DBl4_n

DM6_n/DBl6_n

VDD_10

CK1_t/NF

VDD_12

A10/AP

VDD_14

VDD_16

VDD_18

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58 VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78 VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

ME@

BA0

A13

SA2

SDA SA0 VTT SA1

132

A2

134 136 138 140 142 144

A0

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260

262

VCC1R2A VCC0R6B

M_A_A2

M_A_DDRCLK1_1066M

-M_A_DDRCLK1_1066M M_A_A0

M_A_A10_AP M_A_BA0

M_A_A16_RAS_N M_A_A15_CAS_N

M_A_A13

M_A_VREF_CA_CHA_DIMM SA2_CHA_P

M_A_DQ36 M_A_DQ32

M_A_DQ35 M_A_DQ34 M_A_DQ40 M_A_DQ45

-M_A_DQS5 M_A_DQS5

M_A_DQ47 M_A_DQ42 M_A_DQ48 M_A_DQ49

M_A_DQ53 M_A_DQ55 M_A_DQ56 M_A_DQ60

-M_A_DQS7 M_A_DQS7

M_A_DQ59 M_A_DQ63 SMB_DATA_3B

SA0_CHA_P SA1_CHA_P

RF

Title

DDR4 CH-A PRIMARY

Size Document Number Re v

Wednesday, October 12, 2016

Date: Sheet of

Wednesday, October 12, 2016

VCC1R2A

R2712 240_0402_1%

1 2

M_A_A10_AP [3] M_A_BA0 [3]

M_A_A16_RAS_N [3] M_A_A15_CAS_N [3]

M_A_A13 [3]

VCC1R2A

1

C2730

2.2U_0402_6.3V6-M

2

@

VCC1R2A

SMB_DATA_3B [28,67,68]

1

M_A_DDRCLK1_1066M [3]

-M_A_DDRCLK1_1066M [3]

2

C2729

0.1U_0402_10V7-K

1

NM-B071

27 99

0.2Custom

5

M_B_DQ[0..63] [4] M_B_A[0..9] [4]

-M_B_DQS[0..7] [4] M_B_DQS[0..7] [4]

VCC1R2A

12

D D

M_B_VREF_DQ_CPU[4]

C C

B B

M_B_CKE0[4] M_B_BG1[4]

M_B_BG0[4] M_B_A12[4]

A A

VCC2R5A

RF

1

C2834 100P_0402_50V8J

2

RF_NS@

1

C2835 100P_0402_50V8J

2

RF_NS@

5

R2809 2_0402_1%

1 2

1

C2829

0.022U_0402_25V7-K

2

12

R2811

24.9_0402_1%

VCC1R2A VCC1R2A

M_B_DQ2 M_B_DQ5

-M_B_DQS0 M_B_DQS0

M_B_DQ6 M_B_DQ3 M_B_DQ10 M_B_DQ14

M_B_DQ12 M_B_DQ13 M_B_DQ22 M_B_DQ18

-M_B_DQS2 M_B_DQS2

M_B_DQ20 M_B_DQ19 M_B_DQ27 M_B_DQ31

M_B_DQ30 M_B_DQ24

M_B_BG1 M_B_BG0

M_B_A12 M_B_A9

M_B_A8 M_B_A6

1

NMB071_T470P_SVT_1114_for SMT

C2836 47P_0402_50V8-J

2

RF_NS@

R2808 1K_0402_1%

M_B_VREF_CA_CHB_DIMM

12

R2810 1K_0402_1%

JDIMM2A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4SB-7H

SP071407011

1

C2833 47P_0402_50V8-J

2

RF_NS@

12

C2827

0.1U_0402_16V7-K

DM0_n/DBIO_n

DM2_n/DBl2_n

RESET_n

ALERT_n

VSS_2

DQ4

VSS_4

DQ0

VSS_6 VSS_7

DQ6

VSS_9

DQ2

VSS_11

DQ12

VSS_13

DQ8

VSS_15

DQS1_c

DQS1_t VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26 VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24

VSS_35

DQS3_c

DQS3_t VSS_38

DQ31

VSS_40

DQ27 VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

DBI8_n VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

CKE1

VDD_2

ACT_n

VDD_4

VDD_6

VDD_8

ME@

A11

A7 A5

A4

4

VCC0R6B

VCC2R5A

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

4

1

2

1

2

C2813 10U_0402_6.3V6-M

C2809 10U_0402_6.3V6-M

M_B_DQ4 M_B_DQ0

M_B_DQ1 M_B_DQ7 M_B_DQ8 M_B_DQ9

-M_B_DQS1 M_B_DQS1

M_B_DQ11 M_B_DQ15 M_B_DQ17 M_B_DQ16

M_B_DQ23 M_B_DQ21 M_B_DQ28 M_B_DQ25

-M_B_DQS3 M_B_DQS3

M_B_DQ26 M_B_DQ29

-DRAMRST M_B_CKE1M_B_CKE0

-M_B_ACT

-M_B_ALERT M_B_A11

M_B_A7 M_B_A5

M_B_A4

1

C2814 10U_0402_6.3V6-M

2

1

C2810 10U_0402_6.3V6-M

2

1

C2830

0.1U_0402_10V7-K

2

@

3

VCC1R2A

C2815 1U_0402_6.3V6-K

C2811 1U_0402_6.3V6-K

VCC3B

12

R2801 0_0402_5%

@

SA0_CHB_P SA1_CHB_P SA2_CHB_P

12

R2804 0_0402_5%

C2812 1U_0402_6.3V6-K

M_B_DDRCLK0_1066M[4]

-M_B_DDRCLK0_1066M[4]

VCC3B VCC3B

12

R2805 0_0402_5%

12

R2802 0_0402_5%

@

1

2

VCC1R2A

M_B_A14_WE_N[4]

SPD Address = 2H

VCC3B

-DRAMRST [17,27] M_B_CKE1 [4]

-M_B_ACT [4]

-M_B_ALERT [4] M_B_A11 [4] SMB_CLK_3B[27,67,68]

R2807 0_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

C2801 10U_0402_6.3V6-M

C2816 1U_0402_6.3V6-K

M_B_PARITY[4]

M_B_BA1[4]

-M_B_CS0[4]

M_B_ODT0[4]

-M_B_CS1[4] M_B_ODT1[4]

12

R2803 0_0402_5%

@

12

R2806 0_0402_5%

1

C2825

0.1U_0402_10V7-K

2

1

C2802 10U_0402_6.3V6-M

2

C2817 1U_0402_6.3V6-K

M_B_DDRCLK0_1066M

-M_B_DDRCLK0_1066M M_B_PARITY

M_B_A14_WE_N

SMB_CLK_3B

2015/07/16

1

C2803 10U_0402_6.3V6-M

2

C2818 1U_0402_6.3V6-K

VCC1R2AVCC2R5A

VCC1R2A

M_B_A3 M_B_A1

M_B_BA1

-M_B_CS0

M_B_ODT0

-M_B_CS1 M_B_ODT1

M_B_DQ38 M_B_DQ35

-M_B_DQS4 M_B_DQS4

M_B_DQ33 M_B_DQ32 M_B_DQ40 M_B_DQ41

M_B_DQ42 M_B_DQ46 M_B_DQ52 M_B_DQ48

-M_B_DQS6 M_B_DQS6

M_B_DQ50 M_B_DQ51 M_B_DQ57 M_B_DQ61

M_B_DQ56 M_B_DQ60

1

C2826

2.2U_0402_6.3V6-M

2

LC Future Center Secret Data

Deciphered Date

2

1

C2804 10U_0402_6.3V6-M

2

C2819 1U_0402_6.3V6-K

JDIMM2B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4SB-7H

SP071407011

2

C2820 1U_0402_6.3V6-K

EVENT_n

RAS_n/A16 CAS_n/A15

C0/CS2_n/NC

VREFCA

DM4_n/DBl4_n

DM6_n/DBl6_n

2016/01/16

1

C2805 10U_0402_6.3V6-M

2

ME@

A2

VDD_10

CK1_t

CK1_c

VDD_12

A0

A10/AP

VDD_14

BA0

VDD_16

A13

VDD_18

RFU

VSS_54

DQ36

VSS_56

DQ32

VSS_58 VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78 VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t VSS_90

DQ63

VSS_92

DQ59

VSS_94

SDA SA0

Vtt

SA1

GND_2

1

C2806

2

10U_0402_6.3V6-M

C2821 1U_0402_6.3V6-K

VCC1R2A VCC0R6B

132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260

262

M_B_A2

M_B_DDRCLK1_1066M

-M_B_DDRCLK1_1066M M_B_A0

M_B_A10_AP M_B_BA0

M_B_A16_RAS_N M_B_A15_CAS_N

M_B_A13

M_B_VREF_CA_CHB_DIMM SA2_CHB_P

M_B_DQ34 M_B_DQ39

M_B_DQ36 M_B_DQ37 M_B_DQ44 M_B_DQ45

-M_B_DQS5 M_B_DQS5

M_B_DQ47 M_B_DQ43 M_B_DQ54 M_B_DQ55

M_B_DQ53 M_B_DQ49 M_B_DQ59 M_B_DQ62

-M_B_DQS7 M_B_DQS7

M_B_DQ63 M_B_DQ58 SMB_DATA_3B

SA0_CHB_P SA1_CHB_P

Title

DDR4 CH-B PRIMARY

Size Document Number Re v

Date: Sheet of

1

C2807 10U_0402_6.3V6-M

2

C2822 1U_0402_6.3V6-K

Wednesday, October 12, 2016

C2823 1U_0402_6.3V6-K

VCC1R2A

12

VCC1R2A

R2812 240_0402_1%

M_B_DDRCLK1_1066M [4]

-M_B_DDRCLK1_1066M [4]

M_B_A10_AP [4] M_B_BA0 [4]

M_B_A16_RAS_N [4] M_B_A15_CAS_N [4]

M_B_A13 [4]

1

C2832

2.2U_0402_6.3V6-M

2

@

SMB_DATA_3B [27,67,68]

NM-B071

1

C2808 10U_0402_6.3V6-M

2

1

+

C2824 330U_D2_2VM_R9M@

2

28 99

1

C2831

0.1U_0402_10V7-K

2

0.2Custom

5

www.vinaﬁx.com

D D

4

3

2

1

APS/PETS interface

TP49Test_Point_40MIL @

1

TP46Test_Point_40MIL @

1

TP44Test_Point_40MIL @ TP47Test_Point_40MIL @

TP42Test_Point_40MIL @

1

TP43Test_Point_40MIL @

TP48Test_Point_40MIL @

TP45Test_Point_40MIL @

-PCH_SLP_S0[17,70]

-XDP_DBR[17,24]

-PWRSWITCH[40,57,60,67,68]

-RTCRST[17,25]

-PCH_SLP_M[17,40]

-PCH_SLP_S4[17,40,43]

-PCH_SLP_S5[17,40]

C C

-PCH_SLP_S3[17,40,43,89]

VCC3_SUS

VCC3M

1 1

1

ME@

J2901 FCI_10051922-1810ELF

18

NC1

17

NC2

16

NC3

15

SLP_S0#

14

GND1

13

SYS_RESET#

12

GND2

11

PWRBTN#

10

GND3

9

RTCRST#

8

GND4

7

+V3.3DS

6

SLP_A#

5

SLP_S4#

4

SLP_S5#

3

VccDSW3_3

2

SLP_S3#

1

VccSus3_3

PEG2 PEG1

20 19

Connector

J2901

Planar

ASM

Box

NO ASM

B B

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

4

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

Size Document Number Re v

Wednesday, October 12, 2016

Date: Sheet of

Wednesday, October 12, 2016

NM-B071

1

29 99

0.2Custom

5

D D

C C

4

3

2

1

B B

A A

Title

NMB071_T470P_SVT_1114_for SMT

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/07/16

LC Future Center Secret Data

Deciphered Date

2

2016/01/16

Title

Size Document Number Re v

Wednesday, October 12, 2016

Date: Sheet of

Wednesday, October 12, 2016

NM-B071

1

30 99

0.2Custom

Lenovo THINKPAD T470 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual