Lenovo Thinkpad T470 Schematic

5

4

CS16 T14 Logic Schematics

3

2

1

1.TITLE PAGE

2.EC HISTORY

D D

3.CPU(1/16) : DDI/EDP

4.CPU(2/16) : DDR CHANNEL-A

5.CPU(3/16) : DDR CHANNEL-B

6.CPU(4/16) : MISC/JTAG

7.CPU(5/16) : LPC/SPI/SMBUS/C-LINK

8.CPU(6/16) : LPSS/ISH

9.CPU(7/16) : AUDIO/SDXC

10.CPU(8/16) : PCIE/USB/SATA

11.CPU(9/16) : CSI-2/EMMC

12.CPU(10/16) : CLOCK SIGNALS

C C

13.CPU(11/16) : SYSTEM PM

14.CPU(12/16) : CPU POWER (1/2)

15.CPU(13/16) : CPU POWER (2/2)

16.CPU(14/16) : PCH POWER

17.CPU(15/16) : GND

18.CPU(16/16) : CFG/RESERVED

19.XDP CONNECTOR

20.RTC BATTERY

21.SPI FLASH

B B

22.DDR4 SO DIMM CHANNEL-A (1/2)

23.DDR4 SO DIMM CHANNEL-A (2/2)

24.DDR4 SO DIMM CHANNEL-B (1/2)

25.DDR4 SO DIMM CHANNEL-B (2/2)

26.LCD/LID/MIC/CAMERA/PWR SW

27.ALPINE RIDGE (1/2)

28.ALPINE RIDGE (2/2)

29.USB-C/CONN

30.DDI DEMULTIPLEXER

31.HDMI CONNECTOR

A A

32.STORAGE I/F REDRIVER

33.SATA EXPRESS CONNECTOR

34.USB POWER/CONN(1/2)

35.USB POWER/CONN(2/2)

5

36.GBE JACKSONVILLE

37.GBE LAN SWITCH

38.GBE MAGNETICS

39.RJ45 CONNECTOR

40.N16S-GTR (1/6) : PEG I/F

41.N16S-GTR (2/6) : DIGITAL OUT I/F

42.N16S-GTR (3/6) : VRAM I/F

43.N16S-GTR (4/6) : GPIO

44.N16S-GTR (5/6) : POWER

45.N16S-GTR (6/6) : GND

46.VRAM CHANNEL-A

47.MEMORY TERMINATION

48.M.2 SOCKET 1 MODULE I/F

49.M.2 SOCKET 2 MODULE I/F

50.MEDIA CARD CONTROLLER

51.MEDIA CARD INTERFACE

52.AUDIO ALC3268-CG

53.AUDIO CONNECTOR

54.AUDIO JACK SENSE

55.AUDIO EXT MIC I/F

56.AUDIO SPEAKER

57.AUDIO BEEP

58.DOCKING CONNECTOR

59.MEC1653(1/3)

60.MEC1653(2/3)

61.MEC1653(3/3)

62.KEYBOARD/TRACK POINT

63.TOUCH PAD/NFC/FPR/SCR

64.FAN CONNECTOR

65.APS G-SENSOR

66.DISCRETE TPM 2.0

67.SMBUS SWITCH/LPC DEBUG PORT

68.THINK ENGINE-2(1/2)

69.THINK ENGINE-2(2/2)

70.DC-IN

4

3

71.BLANK

72.BATTERY INPUT

73.BATTERY CHARGER(BQ24780S)

74.CHARGER SELECTOR

75.DC/DC VCC5M/VCC3M (TPS51285B)

76.DC/DC IMVP8 CONTROLLER(NCP81208)

77.DC/DC VCCCPUCORE(NCP81382)

78.DC/DC VCCGFXCORE_I(NCP81382)

79.DC/DC VCCSA(NCP81382)

80.BLANK

81.BLANK

82.DC/DC VCC1R0_SUS(BD91364BMUU)

83.LOAD SW VCCST & VCCSTG

84.DC/DC VCC1R2A(SN1409027)

85.DC/DC VCC0R6B(TPS51206)

86.DC/DC VCC2R5A(TLV62080)

87.DC/DC VCC1R8_SUS(BU90104GWZ)

88.DC/DC VCCPCHCORE(NB682)

89.BLANK

90.BLANK

91.DC/DC VCCGFXCORE_D (NCP81172)

92.DC/DC VCC1R35VIDEO (SN1409027)

93.LOAD SW PCH SUS

94.LOAD SW LAN

95.LOAD SW VIDEO

96.LOAD SW B

97.LOAD SW WWAN & WLAN

98.PTH FOR SCREW HOLES

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

TITLE PAGE

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

1 98

0.1

5

4

3

2

1

VRAM GDDR5 32 bit

D D

46,47

HDMI Conn

DisplayPort (Docking)

WiGig (M.2 WLAN Card)

USB3.0 CONN (USB1)

USB3.0 AOU (USB2)

C C

USB3.0 Multi-Media

USB3.0 CONN (USB3)

USB2.0 Smart Cart

USB2.0 IR Camera

USB2.0 M.2 WWAN Slot

USB2.0 M.2 WLAN Slot (BT)

USB2.0 2D Camera

USB2.0

B B

Fingerprint

USB2.0 Touch Panel

34

50

35

63

26

49

48

26

63

26

Fingerprint Reader

NVIDIA N16S-GTR

GDDR5

40,41,42,43,44,45

31

58

48

USB3.0 CH1 USB2.0 CH1

USB3.0 CH2 USB2.0 CH2

USB3.0 CH3

USB3.0 CH4 USB2.0 CH4

USB2.0 CH3

USB2.0 CH5

USB2.0 CH6

USB2.0 CH7

USB2.0 CH8

USB2.0 CH9

USB2.0 CH10

LED for ThinkPad Logos

USB2.0

Port 9

63

LCD CONN eDP 14" HD/FHD

DP Mux

PS8349BQFN66GTR-A0

USB x 10 ports

RTC Battery

FAN

G-Sensor

KX022-1020

Thermal Sensor

SMB-MB/SB

SM Bus

ClickPad

20

64

65

PECI 3.0

Keyboard

26

30

PCIE x 4

Port 1,2,3,4

eDPx2

DDI x4

6263

10

Embedded Controller MEC1653

CPU

Channel A

DDR4

Intel

Kaby Lake

Platform

BGA1440

15W

3,4,5,6,7,8,9,10,11,12 13,14,15,16,17,18

LPC Bus 33MHz

59,60,61 68,69

Power Button

26

Channel B

DDR4

SM Bus

10

TPM 2.0

Lenovo ASIC ThinkEngine

BD4178GSW-ZE2

DDR4 / 1.2V

DDR4 SO-DIMMA

DDR4 SO-DIMMB

CPU XDP

NFC

C-Link

PCI Express x 8 ports

HDA

SPI Flash 64Mbits (SPI1)

W25Q128FVSIQ

66

22,23

24,25

19

63

21

Stereo Speaker

External Connector/Socket

ALC3268-CG HDA CODEC

56

Microphone Headphone

52,53

53

Audio Combo Jack

Different with Cobain3

Audio (Docking)

Internal Connector/Socket

Internal Switch

EC SMBus0 address

A A

G-Senor (KX023)

AddressDevice

0011 110Xb

Windu Block Diagram

Project Code: CT470

Antenna

(M.2 WLAN Card)

Type-A M.2 Card

I2S

Internal Mic

58

USB3.0 CH03

Bluetooth

USB

Port 7

52

26

MAGNETICS RJ45

Multi-Media Controller

Realtek RTS5344-GR

48

Port 6 (X1)

Port 5 (X1)

Intel GbE PHY JACKSONVILLE

WGI219LM-SLKJ2-A0

LAN SWITCH

PI3L720ZHE+CX

37

Docking

38,39

50

36

PCIE MUX CBTL02043ABQ

Port 11 (X1)

DP x4

SM Bus

58

SD Card Slot

2015 Dec ' 16

(M.2 WWAN Card)

10

Type-B M.2 Card

Micro SIM Card Slot

Port 12 (X1)

Port 9,10 (X2)

Alpine Ridge-LP

27,28

TBT-PWR SW TI TPS65982 /USB Type-C

29

51

Antenna

49

USB

Port 6

SPI Flash TBT 4M

TABLE: Chip Capacitor Thermal Characteristics

Port 7,8 (X2)

-55 to 150degC

-55 to 125degC

-55 to 105degC

-55 to 85degC

+/-30ppm/degC +/-30ppm/degC

+/-15% +/-22% +/-15%

Re-Driver

32

HDD CONN SSD

33

TABLE: Chip Capacitor Tolerance

Tolerance

+/-0.25pF +/-0.5pF

+/-5% +/-10% +/-20% +80/-20%

TABLE: Chip Part Dimension

Size [mm]

0.40 x 0.20

0.60 x 0.30

1.00 x 0.50

1.60 x 0.80

2.00 x 1.25

2.00 x 1.60

2.50 x 2.00

3.20 x 1.60

3.20 x 2.50

4.50 x 1.60

4.50 x 2.50

4.50 x 3.20

5.00 x 2.50

6.40 x 3.20

mm Size Code Inch Size Code

0402 0603 1005 1608 2125 2016 2520 3216 3225 4516 4525 4532 5025 6432

Code

NPO C0G

X7R X6S X5R

Code

C D

J K M Z

01005 0201 0402 0603 0805 0806 1008 1206 1210 1806 1810 1812 2010 2512

PCH SM Bus address

Device Address

DDR DIMM0 (J53)

CH-A

CH-B

DDR DIMM1 (J43)

1001 0000b

1001 0001b

5

PCH SM Bus0 address

Device

Intel Lan_I219

Address

0XC8

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

BLOCK DIAGRAM

Size Document Number Rev

Custom

C

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

Date: Sheet

1

LOGIC

of

2 98

0.1

5

D D

DDIP1_0N<27> DDIP1_0P<27> DDIP1_1N<27> DDIP1_1P<27> DDIP1_2N<27> DDIP1_2P<27> DDIP1_3N<27> DDIP1_3P<27>

DDIP2_0N<30> DDIP2_0P<30>

C C

TABLE : Functional Strap

DDIP2_1N<30> DDIP2_1P<30> DDIP2_2N<30> DDIP2_2P<30> DDIP2_3N<30> DDIP2_3P<30>

DDIP2_CTRLCLK<30> DDIP2_CTRLDATA<30>

-GPU_RST<40> 3VIDEO_AON_ON<69>

DDPB_CTRLDATA

Port B is detected.

HIGH

LOW

Port B is not detected.

DDIP1_0N DDIP1_0P DDIP1_1N DDIP1_1P DDIP1_2N DDIP1_2P DDIP1_3N DDIP1_3P

DDIP2_0N DDIP2_0P DDIP2_1N DDIP2_1P DDIP2_2N DDIP2_2P DDIP2_3N DDIP2_3P

DDIP2_CTRLCLK DDIP2_CTRLDATA

-GPU_RST 3VIDEO_AON_ON

4

VCCCPUIOVCC3_SUSVCC3VIDEO_AON

SWG@

R10251 10K_0201_5%

1 2

12

R10252 1M_0201_5%

SWG@

R10131

2.2K_0201_5%

1 2

R5

24.9_0201_1%

1 2

EDP_COMP

U58A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

3

SKL_ULT

DDI

DISPLAY SIDEBANDS

1 OF 20

EDP

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

2

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

R433

100K_0201_5%

1 2

R138

100K_0201_5%

1 2

R8 100K_0201_5%

1 2

R10228 100K_0201_5%

1 2

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_AUXN EDP_AUXP

DDIP1_AUXN DDIP1_AUXP DDIP2_AUXN DDIP2_AUXP

DDIP1_HPD DDIP2_HPD

R10229 100K_0201_5%

1 2

EDP_TXN0 <26> EDP_TXP0 <26> EDP_TXN1 <26> EDP_TXP1 <26>

EDP_AUXN <26> EDP_AUXP <26>

DDIP1_AUXN <27> DDIP1_AUXP <27> DDIP2_AUXN <30> DDIP2_AUXP <30>

DDIP1_HPD <27> DDIP2_HPD <30>

-GPU_EVENT <43> GC6_FB_EN <43,92> EDP_HPD <26>

VGA_BLON <59> PANEL_BKLT_CTRL <26> PANEL_POWER_ON <69>

1

DDPC_CTRLDATA

Port C is detected.

HIGH

Port C is not detected.

B B

A A

LOW

U58

I5

SA00007GP30

S_I5@

U58

I7-7500U

SA000080420

K_I7@

2015/8/10

SkyLake

U58

I7

SA00007GM30

S_I7@

KabyLake

U58

I5-7200U

SA000080320

K_I5@

CPU_VPRO

U58

I7_VPRO

SA00007GL30

S_I7V@

U58

I5-7300U_VPRO

SA000086M10

K_I5V@

3 98

of

U58

I5_VPRO

SA00007GN20

S_I5V@

U58

I3-7100U

SA000080720

K_I3@

Title

CPU(1/16) : DDI/EDP

Size Document Number Rev

Custom

Date: Sheet

C

Wednesday, November 02, 2016

U58

I7-7600U_VPRO

SA000086N10

K_I7V@

Windu-1

Windu-1Windu-1

1

0.1

Non-VPROPCB

ZZZ

NM-A931

DAA00007520

SKY@

PCB Non-VPRO CPU_VPRO

ZZZ

NM-A931

DAZ12D00100

KABY@

M/B -> DAA00007510 PWR/B -> DAA00007710

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

CAM/B -> DAA00007810

LC Future Center Secret Data

Deciphered Date

2

5

M_A_DQ[63:0]<22>

TABLE

D D

Block 0

C C

Block 2

Block 4

B B

Block 6

A A

AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69

BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59

AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33

AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25

Interleave

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31]

DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47]

DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

Non-Interleave

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15]

DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47]

DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15]

DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

4

U58B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

TABLE

InterleavePin Non-Interleave

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_DQSN[2] DDR0_DQSP[2] DDR0_DQSN[3] DDR0_DQSP[3]

DDR0_DQSN[4] DDR0_DQSP[4] DDR0_DQSN[5] DDR0_DQSP[5]

DDR0_DQSN[6] DDR0_DQSP[6] DDR0_DQSN[7] DDR0_DQSP[7]

Block 0

Block 2

Block 4

Block 6

AM70 AM69 AT69 AT70

BA64 AY64 AY60 BA60

BA38 AY38 AY34 BA34

BA30 AY30 AY26 BA26

3

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_DQSN[4] DDR0_DQSP[4] DDR0_DQSN[5] DDR0_DQSP[5]

DDR1_DQSN[0] DDR1_DQSP[0] DDR1_DQSN[1] DDR1_DQSP[1]

DDR1_DQSN[4] DDR1_DQSP[4] DDR1_DQSN[5] DDR1_DQSP[5]

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

DDR_PG_CTRL

-M_A_DDRCLK0_1066M M_A_DDRCLK0_1066M

-M_A_DDRCLK1_1066M M_A_DDRCLK1_1066M

M_A_CKE0 M_A_CKE1

-M_A_CS0

-M_A_CS1 M_A_ODT0 M_A_ODT1

M_A_A5 M_A_A9 M_A_A6 M_A_A8 M_A_A7

M_A_A12 M_A_A11

M_A_A13 M_A_A15 M_A_A14 M_A_A16

M_A_A2

M_A_A10 M_A_A1 M_A_A0 M_A_A3 M_A_A4

-M_A_DQS0 M_A_DQS0

-M_A_DQS1 M_A_DQS1

-M_A_DQS2 M_A_DQS2

-M_A_DQS3 M_A_DQS3

-M_A_DQS4 M_A_DQS4

-M_A_DQS5 M_A_DQS5

-M_A_DQS6 M_A_DQS6

-M_A_DQS7 M_A_DQS7

VCC1R2A

R1858 10K_0201_5%

@

1 2

-M_A_DDRCLK0_1066M <22> M_A_DDRCLK0_1066M <22>

-M_A_DDRCLK1_1066M <22> M_A_DDRCLK1_1066M <22>

M_A_CKE0 <22> M_A_CKE1 <22>

-M_A_CS0 <22>

-M_A_CS1 <22> M_A_ODT0 <22> M_A_ODT1 <22>

M_A_BG0

-M_A_ACT M_A_BG1

M_A_BS0

M_A_BS1

-M_A_ALERT <22>

M_A_PARITY <22>

M_A_VREF_CA_CPU <22>

M_B_VREF_CA_CPU <24>

VCC3M

R1838 100K_0201_5%

1 2

1

Q170

2

DTC015TMT2L_VMT3

3

M_A_BG0 <22>

-M_A_ACT <22> M_A_BG1 <22>

M_A_BS0 <22>

M_A_BS1 <22>

M_A_A[16:0] <22>

-M_A_DQS[7:0] <22>

M_A_DQS[7:0] <22>

DDR_VTT_PG_CTRL

2

DDR_VTT_PG_CTRL <84>

TABLE

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

DDR3L LPDDR3

DDR0_MA[5] DDR0_MA[9] DDR0_MA[6] DDR0_MA[8] DDR0_MA[7] DDR0_BA[2] DDR0_MA[12] DDR0_MA[11] DDR0_MA[15] DDR0_MA[14]

DDR0_MA[13] DDR0_CAS# DDR0_WE# DDR0_RAS# DDR0_BA[0] DDR0_MA[2] DDR0_BA[1] DDR0_MA[10] DDR0_MA[1] DDR0_MA[0] DDR0_MA[3] DDR0_MA[4]

DDR0_CAA[0] DDR0_CAA[1] DDR0_CAA[2] DDR0_CAA[3] DDR0_CAA[4] DDR0_CAA[5] DDR0_CAA[6] DDR0_CAA[7] DDR0_CAA[8] DDR0_CAA[9]

DDR0_CAB[0] DDR0_CAB[1] DDR0_CAB[2] DDR0_CAB[3] DDR0_CAB[4] DDR0_CAB[5] DDR0_CAB[6] DDR0_CAB[7] DDR0_CAB[8] DDR0_CAB[9] Not Used Not Used

1

DDR4

DDR0_MA[5] DDR0_MA[9] DDR0_MA[6] DDR0_MA[8] DDR0_MA[7] DDR0_BG[0] DDR0_MA[12] DDR0_MA[11] DDR0_ACT# DDR0_BG[1]

DDR0_MA[13] DDR0_MA[15] DDR0_MA[14] DDR0_MA[16] DDR0_BA[0] DDR0_MA[2] DDR0_BA[1] DDR0_MA[10] DDR0_MA[1] DDR0_MA[0] DDR0_MA[3] DDR0_MA[4]

LOGIC

5

LOGIC

Title

Security Classification

LOGIC

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(2/16) : DDR CHANNEL-A

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

4 98

0.1

5

4

3

2

1

TABLE

Block 1

Block 3

Block 5

Block 7

AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69

AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60

AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30

AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

D D

C C

B B

A A

Interleave

DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15]

DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31]

DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

Non-Interleave

DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31]

DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63]

DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31]

DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

M_B_DQ[63:0]<24>

SKL_ULT

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR CH - B

3 OF 20

DDR1_ODT[1]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2

-M_B_DDRCLK0_1066M

-M_B_DDRCLK1_1066M M_B_DDRCLK0_1066M M_B_DDRCLK1_1066M

M_B_CKE0 M_B_CKE1

-M_B_CS0

-M_B_CS1 M_B_ODT0 M_B_ODT1

M_B_A5 M_B_A9 M_B_A6 M_B_A8 M_B_A7 M_B_BG0 M_B_A12 M_B_A11

-M_B_ACT M_B_BG1

M_B_A13 M_B_A15 M_B_A14 M_B_A16 M_B_BS0 M_B_A2 M_B_BS1 M_B_A10 M_B_A1 M_B_A0 M_B_A3 M_B_A4

-M_B_DQS0 M_B_DQS0

-M_B_DQS1 M_B_DQS1

-M_B_DQS2 M_B_DQS2

-M_B_DQS3 M_B_DQS3

-M_B_DQS4 M_B_DQS4

-M_B_DQS5 M_B_DQS5

-M_B_DQS6 M_B_DQS6

-M_B_DQS7 M_B_DQS7

1 2

R7 121_0201_1%

1 2

R84 80.6_0201_1%

1 2

R576 100_0201_1%

-M_B_DDRCLK0_1066M <24>

-M_B_DDRCLK1_1066M <24> M_B_DDRCLK0_1066M <24> M_B_DDRCLK1_1066M <24>

M_B_CKE0 <24> M_B_CKE1 <24>

-M_B_CS0 <24>

-M_B_CS1 <24> M_B_ODT0 <24> M_B_ODT1 <24>

M_B_BG0 <24>

-M_B_ACT <24> M_B_BG1 <24>

M_B_BS0 <24>

M_B_BS1 <24>

M_B_A[16:0] <24>

-M_B_DQS[7:0] <24>

M_B_DQS[7:0] <24>

VCC1R2A

R1726 470_0201_5%

1 2

-M_B_ALERT M_B_PARITY

-DRAMRST

TABLE

-M_B_ALERT <24> M_B_PARITY <24>

-DRAMRST <22,24>

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

DDR3L LPDDR3 DDR4

DDR1_MA[5] DDR1_MA[9] DDR1_MA[6] DDR1_MA[8] DDR1_MA[7] DDR1_BA[2] DDR1_MA[12] DDR1_MA[11] DDR1_MA[15] DDR1_MA[14]

DDR1_MA[13] DDR1_CAS# DDR1_WE# DDR1_RAS# DDR1_BA[0] DDR1_MA[2] DDR1_BA[1] DDR1_MA[10] DDR1_MA[1] DDR1_MA[0] DDR1_MA[3] DDR1_MA[4]

DDR1_CAA[0] DDR1_CAA[1] DDR1_CAA[2] DDR1_CAA[3] DDR1_CAA[4] DDR1_CAA[5] DDR1_CAA[6] DDR1_CAA[7] DDR1_CAA[8] DDR1_CAA[9]

DDR1_CAB[0] DDR1_CAB[1] DDR1_CAB[2] DDR1_CAB[3] DDR1_CAB[4] DDR1_CAB[5] DDR1_CAB[6] DDR1_CAB[7] DDR1_CAB[8] DDR1_CAB[9] Not Used Not Used

DDR1_MA[5] DDR1_MA[9] DDR1_MA[6] DDR1_MA[8] DDR1_MA[7] DDR1_BG[0] DDR1_MA[12] DDR1_MA[11] DDR1_ACT# DDR1_BG[1]

DDR1_MA[13] DDR1_MA[15] DDR1_MA[14] DDR1_MA[16] DDR1_BA[0] DDR1_MA[2] DDR1_BA[1] DDR1_MA[10] DDR1_MA[1] DDR1_MA[0] DDR1_MA[3] DDR1_MA[4]

LOGIC

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

U58C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U_BGA1356

TABLE

InterleavePin Non-Interleave

AH66

Block 1

Block 3

Block 5

Block 7

AH65 AG69 AG70

AR66 AR65 AR61 AR60

AT38 AR38 AT32 AR32

AR25 AR27 AR22 AR21

DDR1_DQSN[0] DDR1_DQSP[0] DDR1_DQSN[1] DDR1_DQSP[1]

DDR1_DQSN[2] DDR1_DQSP[2] DDR1_DQSN[3] DDR1_DQSP[3]

DDR1_DQSN[4] DDR1_DQSP[4] DDR1_DQSN[5] DDR1_DQSP[5]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR0_DQSN[2] DDR0_DQSP[2] DDR0_DQSN[3] DDR0_DQSP[3]

DDR0_DQSN[6] DDR0_DQSP[6] DDR0_DQSN[7] DDR0_DQSP[7]

DDR1_DQSN[2] DDR1_DQSP[2] DDR1_DQSN[3] DDR1_DQSP[3]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

LOGIC

5

LOGIC

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(3/16) : DDR CHANNEL-B

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

5 98

0.1

5

D D

4

VCCSTG VCCST

3

2

1

R64 1K_0201_5%

C C

B B

PECI<60>

-PROCHOT<59,60,73,76>

WIGIG_DISABLE<10>

PECI

-PROCHOT

1 2

R85 510_0201_5%

1 2

R2126 49.9_0201_1%

1 2

R2127 49.9_0201_1%

1 2

R2128 49.9_0201_1%

1 2

R2129 49.9_0201_1%

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

R9055 1K_0201_5%

1 2

AT16 AU16

D63 A54 C65 C63 A65

C55 D55 B54 C56

A6

A7 BA5 AY5

H66 H65

U58D

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

SKYLAKE-U_BGA1356

SKL_ULT

4 OF 20

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

EMC

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

R2 51_0201_5%

1 2

R521 0_0201_5%@ R523 0_0201_5%@ R524 0_0201_5%@ R525 0_0201_5%@ R526 0_0201_5%@

1 2 1 2 1 2 1 2 1 2

XDP_TCK0 XDP_TDI XDP_TDO XDP_TMS

-XDP_TRST

XDP_TCK0 <19> XDP_TDI <19> XDP_TDO <19> XDP_TMS <19>

-XDP_TRST <19>

PCH_TCK <19>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(4/16) : MISC/JTAG

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

6 98

0.1

5

TABLE : Functional Strap

SPI0_MOSI (Boot Halt)

Disabled (Default)

HIGH

Enabled

D D

C C

B B

LOW

TABLE : Functional Strap

SPI0_MISO (JTAG ODT Disable)

Enabled (Default)

HIGH

Disabled

LOW

SPI_CLK<21,66> SPI_MISO_IO1<21,66> SPI_MOSI_IO0<21,66> SPI_IO2<21> SPI_IO3<21>

-SPI_CS0<21>

-SPI_CS2<66>

DOCKID[3:0]<58>

-DOCK_CAP_ID<58>

-NFC_DTCT<63>

CL_CLK_WLAN<48> CL_DATA_WLAN<48>

-CL_RST_WLAN<48>

IRQSER<59,67>

-DOCK_CAP_ID

2

C9126

0.1U_0402_25V6-K

EMC@

1

DOCKID1 DOCKID2 DOCKID3

DOCKID0

CL_CLK_WLAN

CL_DATA_WLAN

-CL_RST_WLAN

-KBRC<59>

R860

8.2K_0201_5%

1 2

R2559 1K_0201_5%

@

1 2

4

VCC3_SUSVCC3B

R272 10K_0201_5%

@

1 2

AW13

AY11

AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2

M1

G3 G2 G1

TABLE : Functional Strap

GPP_C5/SML0ALERT # (LPC or eSPI)

eSPI is selected

HIGH

LPC is selected (Default) LOGIC

LOW

TABLE : Functional Strap

GPP_C2/SMBALERT# (TLS Confidentiality)

Enable ME Crypto TLS with Confidentiality

HIGH

Disable ME Crypto TLS (Default)

LOW

U58E

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKYLAKE-U_BGA1356

TABLE : Functional Strap

SPI0_IO2 (Consent Strap)

HIGH Enabled (Default)

LOW

TABLE : Functional Strap

SPI0_IO3 (A0 Personality Strap)

HIGH

LOW

SKL_ULT

Disabled

Disabled (Default)

Enabled

LPC

5 OF 20

3

SMBUS, SMLINK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

2

LOGIC

VCC3_SUS VCC3B

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

R226 1K_0201_5%

1 2

LPCCLK_0 LPCCLK_1

R106 499_0201_1%

1 2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

1 2

R193 33_0201_5%EMC@

1 2

R220 0_0201_5%EMC@

LPCCLK_EC_24M LPCCLK_DEBUG_24M

2

C9091 22P_0201_25V8-J

RF@

1

R107 499_0201_1%

R394

4.7K_0201_5%

1 2

R397

4.7K_0201_5%

1 2

2

C9092 22P_0201_25V8-J

RF@

1

LPC_AD[3:0] <59,67>

-LPC_FRAME <59,67>

-SUS_STAT <59,67>

LPCCLK_EC_24M <59> LPCCLK_DEBUG_24M <67>

R28

8.2K_0201_5%

1 2

SMB_CLK SMB_DATA

SML0_CLK SML0_DATA

EC_SCL2 EC_SDA2

1

SMB_CLK <67> SMB_DATA <67>

SML0_CLK <36> SML0_DATA <36>

EC_SCL2 <60> EC_SDA2 <60>

-CLKRUN <59,67>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(5/16) : LPC/SPI/SMBUS/C-LINK

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

7 98

0.1

5

4

3

2

1

D D

R884

R2340

10K_0201_5%

1 2

NFC_DLREQ<63>

C C

-TBT_PLUG_EVENT<27> TBT_FORCE_PWR<27>

-EC_SCI<59>

-EC_WAKE<59>

I2C0_DATA<63> I2C0_CLK<63>

-WWAN_RESET<49>

-INT_MIC_DTCT<26>

WWAN_CFG0<49> WWAN_CFG1<49>

B B

-MIC_HW_EN

R961 0_0201_5%

1 2

VCC3_SUS

R65

1 2

@

1K_0201_5%

AN8 AP7 AP8 AR7

AM5 AN7 AP5 AN5

AB1 AB2

AB3

AD1 AD2 AD3 AD4

AH9

AH10

AH11 AH12

AF11 AF12

TABLE : Functional Strap

GPP_B22/GSPI1_MOSI (Boot BIOS Destination)

Boot BIOS from LPC

HIGH

Boot BIOS from SPI (Default) LOGIC

LOW

TABLE : Functional Strap

GPP_B18/GSPI0_MOSI (No Reboot)

Enable "No Reboot" Mode

HIGH

Disable "No Reboot" Mode (Default)

LOW

U58F

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

SKYLAKE-U_BGA1356

LPSS ISH

SKL_ULT

6 OF 20

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

Model

SWG

UMA

R10126

ASM

NO ASM

-DISCRETE_PRESENCE

DGFX_VRAM_ID0 DGFX_VRAM_ID1

TABLE : DGFX_VRAM_IDTABLE : -DISCRETE_PRESENCE

DFX_VRAM_ID[1..0]

00B

01B

10B

11B

VCC3_SUS

R10125

1 2

-DISCRETE_PRESENCE

DGFX_VRAM_ID0

DGFX_VRAM_ID1

1GB

2GB

4GB

N/A

10K_0201_5%

DGFX_PWRGD <12,91,92>

WWAN_CFG2 <49> WWAN_CFG3 <49>

SWG@

1 2

R10126 0_0201_5%

@

1 2

R10127 0_0201_5%

SWG@

1 2

R10128 0_0201_5%

LOGIC

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(6/16) : LPSS/ISH

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

8 98

0.1

5

D D

4

3

2

1

VCC3_SUS

1 2

R846 1K_0201_5%

VCC3_SUS

R1009 1K_0201_5%

C C

B B

HDA_SYNC<52> HDA_BCLK<52>

HDA_SDO<52>

HDA_SDIN0<52>

-HDA_RST<52>

2

1

DDI_PRIORITY1<30> -SC_DTCT <63> DDI_PRIORITY2<30>

PCH_SPKR<57>

PCH_SPKR

1 2

R423 33_0201_5%

1 2

R60 33_0201_5%EMC@

1 2

R74 33_0201_5%

1 2

R456 33_0201_5%

EMC@

C38 22P_0201_25V8-J

NFC_ACTIVE<63>

HDA_SYNC_CPU HDA_BCLK_CPU HDA_SDO_CPU

-HDA_RST_CPU

1 2

PLACE ON TOP SIDE

R566 0_0603_5%@

VCC3_SUS

TP901

@

Test_Point_40MIL

1

TEST PAD BOTTOM SIDE DO NOT MOVE AFTER FIX

1 2

R9133 0_0201_5%@

1 2

TP900

@

Test_Point_40MIL

1

NFC_ACTIVE_R

TABLE : Functional Strap

HDA_SDO/I2S0_TXD

Flash Descriptor Security Override

Disable Flash Descriptor Security (Override)

HIGH

Enable Flash Descriptor Security (Default)

LOW

U58G

AUDIO

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKYLAKE-U_BGA1356

TABLE : Functional Strap

GPP_B14/SPKR (Top Swap Override)

HIGH

Enable "Top Swap" Mode

LOW

Disable "Top Swap" Mode (Default) LOGIC

SKL_ULT

7 OF 20

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

SD_RCOMP

1 2

R2131 200_0201_1%

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(7/16) : AUDIO/SDXC

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

9 98

0.1

VCC3M

5

USB3 1

USB3 2

USB3 3 USB3P2

USB3 4

PCIE 1 (x4)

PCIE 2 (x4)

PCIE 3 (x4)

PCIE 4 (x4)

PCIE 5 (GbE)

PCIE 6

PCIE 7 (x2)

GPIO STRAP

PCIE 11 (x2)

GPIO STRAP

PCIE0_L0_RXN<40> PCIE0_L0_RXP<40> PCIE0_L0_TXN<40> PCIE0_L0_TXP<40>

PCIE0_L1_RXN<40> PCIE0_L1_RXP<40> PCIE0_L1_TXN<40> PCIE0_L1_TXP<40>

PCIE0_L2_RXN<40> PCIE0_L2_RXP<40> PCIE0_L2_TXN<40> PCIE0_L2_TXP<40>

PCIE0_L3_RXN<40> PCIE0_L3_RXP<40> PCIE0_L3_TXN<40> PCIE0_L3_TXP<40>

PCIE4_RXN<36> PCIE4_RXP<36> PCIE4_TXN<36> PCIE4_TXP<36>

PCIE5_RXN<48> PCIE5_RXP<48> PCIE5_TXN<48> PCIE5_TXP<48>

PCIE6_L1_RXN<49> PCIE6_L1_RXP<49> PCIE6_L1_TXN<49> PCIE6_L1_TXP<49>

PCIE8_L0_RXN<27> PCIE8_L0_RXP<27> PCIE8_L0_TXN<27> PCIE8_L0_TXP<27>

PCIE8_L1_RXN<27> PCIE8_L1_RXP<27> PCIE8_L1_TXN<27> PCIE8_L1_TXP<27>

-XDP_PRDY<19>

-XDP_PREQ<19>

-TPM_IRQ<66>

PCIE10_L0_RXN<32> PCIE10_L0_RXP<32>

PCIE10_L0_TXN<32> PCIE10_L0_TXP<32> PCIE10_L1_SATA2_RXN<32> PCIE10_L1_SATA2_RXP<32> PCIE10_L1_SATA2_TXN<32> PCIE10_L1_SATA2_TXP<32>

-DOCK_ATTACHED_3M

USB3P0_TXP USB3P0_TXN USB3P0_RXP USB3P0_RXN

C2751

C2752

2

1

0.1U_0201_6.3V6-K

5

PCIe Port Assignment

Discrete GPU

USB3P0

USB3P1

USB3P3

PCIE0

PCIE4

PCIE5

PCIE6_L1

PCIE6_L0_SATA1

PCIE8_L0

PCIE8_L1

PCIE10_L0

PCIE10_L1_SATA2

C2753

0.1U_0201_6.3V6-K

0 (x4)

4

GbE PHY

5

M.2 WLAN Slot Port 0

Optane x2 or

6 (x2)

M.2 WLAN Slot Port 1x 1

8 (x2)

Alpine Ridge-LP

10 (x2) Main Storage x 2

VCC3_SUS

PCIE6_L0_SATA1_RXN PCIE6_L0_SATA1_RXP PCIE6_L0_SATA1_TXN PCIE6_L0_SATA1_TXP

-XDP_PRDY

-XDP_PREQ

-TPM_IRQ

2 9

3 4 7 8

1 6

10

Vendor P/N LCFC P/N NXP PERICOM

R529 0_0201_5%@ R530 0_0201_5%@

U160

XSD SEL

A0_P A0_N A1_P A1_N

VDD1 VDD2 VDD3

CBTL02042ABQ_DHVQFN20_2P5X4P5

B0_P B0_N B1_P B1_N C0_P

C0_N

C1_P C1_N GND1 GND2 GND3

THERMAL_PAD

TABLE of USB3.0 SW (U160)

CBTL02042ABQ PI3PCIE3212ZBE

R2341 10K_0201_5%

1 2

1 2 1 2

I/O High Speed Signals Configuration Net Name

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

D D

Port 8

Port 9

Port 10

Port 11

Port 12

Port 13

Port 14

Port 15

Port 16

C C

B B

A A

Flexible I/O Configuration

USB3 1

USB3 2/SSIC

USB3 3

USB3 4

USB3 5/PCIE 1

USB3 6/PCIE 2

PCIE 3 (GbE)

PCIE 4 (GbE)

PCIE 5 (GbE)

PCIE 6

PCIE 7/SATA 0

PCIE 8/SATA 1A

PCIE 9 (GbE) PCIE 9 (x2)

PCIE 10 (GbE) PCIE 9 (x2)

PCIE 11/SATA 1B

PCIE 12/SATA 2

-DOCK_ATTACHED_3M<58,60,61>

19 18 17 16 15 14 13 12 5 11 20 21

R8964

100_0201_1%

1 2

4

0

1A

1B

2

PCIE_RCOMPN PCIE_RCOMPP

USB3P0_TXP_DOCK USB3P0_TXN_DOCK USB3P0_RXP_DOCK USB3P0_RXN_DOCK USB3P0_TXP_SYS USB3P0_TXN_SYS USB3P0_RXP_SYS USB3P0_RXN_SYS

SA00005R500 SA00005RJ00 SA000066600TOSHIBA TC7PCI3212MT

4

SATA Port Assignment

(PCIE 7)

SATA SSD on WWAN slot

(PCIE 11)

SATA SSD Main Storage

U58H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

USB3P0_TXP_DOCK <58> USB3P0_TXN_DOCK <58> USB3P0_RXP_DOCK <58> USB3P0_RXN_DOCK <58> USB3P0_TXP_SYS <34> USB3P0_TXN_SYS <34> USB3P0_RXP_SYS <34> USB3P0_RXN_SYS <34>

SKL_ULT

USBP0-

USBP0+

-DOCK_ATTACHED_3M

8 OF 20

3

WIGIG_DISABLE<6>

-WWAN_SSD_DTCT<49,61>

-WWAN_SSD_DTCT_3B<12>

SSIC / USB3

USB3_1_RXN USB3_1_RXP

USB3_1_TXN USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN USB3_4_RXP

USB3_4_TXN USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

U161

2

Y-

1

Y+

SEL

8

OE

3

USB2_COMP

VCC3M

9

VDD

GND

3

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10 USB2P_10

USB2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

10

PI3USB102ZMEX_UQFN10_1P4X1P8

2

VCC3B

12

PCIE6_L0_SATA1_TXP PCIE6_L0_SATA1_TXN

WIGIG_DISABLE

-WWAN_SSD_DTCT

-WWAN_SSD_DTCT_3B

C2592 0.22U_0201_6.3V6-K C2593 0.22U_0201_6.3V6-K

D728 RB521CM-30T2R_VMN2M

D727 RB521CM-30T2R_VMN2M D741 RB521CM-30T2R_VMN2M

1 2 1 2

VCC3B

VCC3_SUS

10K_0201_5%

1 2

1 2 1 2

PCIE6_L0_SATA1_TXP_C PCIE6_L0_SATA1_TXN_C PCIE6_L0_SATA1_RXN PCIE6_L0_SATA1_RXP

C9356

2

1

0.1U_0201_6.3V6-K

R10234

10K_0201_5%

C9357

2

1

0.1U_0201_6.3V6-K

R10317 10K_0201_5%

U189

2

XSD

9

SEL

3

A0_P

4

A0_N

7

A1_P

8

A1_N

1

VDD1

6

VDD2

10

C9358

2

1

0.1U_0201_6.3V6-K

VDD3

CBTL02042ABQ_DHVQFN20_2P5X4P5

WIGIG_DISABLE

-WWAN_SSD_DTCT

SEL(U189)

XSD(U189)

PCIE6_L0_SATA1

R503

R248

R648

1 2

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10

USB3P2_TXN_C

B15

USB3P2_TXP_C

A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3

USB2_ID

AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

2

C2754

0.1U_0201_6.3V6-K

1

4

M-

5

M+

6

D-

7

D+

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

C9424 0.1U_0201_6.3V6-K C9425 0.1U_0201_6.3V6-K

USBCOMP

1

TP938 Test_Point_12MIL

Vendor P/N LCFC P/N PERICOM NXP

USBP0-_DOCK

USBP0+_DOCK

USBP0-_SYS

USBP0+_SYS

USB3P0_RXN USB3P0_RXP USB3P0_TXN USB3P0_TXP

1 2 1 2

USBP0USBP0+

1 2

R564 113_0201_1%

1 2

R2573 0_0201_5%

1 2

R2580 1K_0201_5%

USB3P1_RXN_AOU <34> USB3P1_RXP_AOU <34> USB3P1_TXN_AOU <34> USB3P1_TXP_AOU <34>

USB3P2_RXN <50> USB3P2_RXP <50> USB3P2_TXN <50> USB3P2_TXP <50>

USB3P3_RXN <35> USB3P3_RXP <35> USB3P3_TXN <35> USB3P3_TXP <35>

USBP1-_AOU <34> USBP1+_AOU <34>

USBP2- <63> USBP2+ <63>

USBP3- <35> USBP3+ <35>

USBP4- <26> USBP4+ <26>

USBP5- <49> USBP5+ <49>

USBP6- <48> USBP6+ <48>

USBP7- <26> USBP7+ <26>

USBP8- <63> USBP8+ <63>

USBP9- <26> USBP9+ <26>

TABLE of USB2.0 SW (U161)

PI3USB102ZMEX NX3DV42GU

USBP0-_DOCK <58>

USBP0+_DOCK <58>

USBP0-_SYS <34>

USBP0+_SYS <34>

2015/11/02

SA00005RH00 SA00005RI00

LC Future Center Secret Data

Deciphered Date

2

-USB_PORT0_OC0 <34>

-USB_PORT1_OC1 <34>

-USB_PORT3_OC2 <35> NFC_INT <63>

TABLE of USB3.0 SW (U189) Vendor P/N LCFC P/N NXP

CBTL02042ABQ PI3PCIE3212ZBE

PERICOM

PCIE6_L0_SATA1_TXP_CACHE

19

B0_P

PCIE6_L0_SATA1_TXN_CACHE

18

B0_N

PCIE6_L0_SATA1_RXN_CACHE

17

B1_P

PCIE6_L0_SATA1_RXP_CACHE

16

B1_N

PCIE6_L0_SATA1_TXP_WIGIG

15

C0_P

PCIE6_L0_SATA1_TXN_WIGIG

14

C0_N

PCIE6_L0_SATA1_RXN_WIGIG

13

C1_P

PCIE6_L0_SATA1_RXP_WIGIG

12

C1_N

5

GND1

11

GND2

20

GND3

21

THERMAL_PAD

Optane SATA Cache WWAN Card None

H

2015/8/10

L

To M.2 Socket2

VCC3_SUS

R44

L

To M.2 Socket2

0

1

2

3

4

5

6

7

8

9

0

1

2

3

5

10K_0201_5%

R2745

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

H

LL

L

To M.2

Socket2

USB 2.0 Port Assignment

USB 3.0 System Port / Docking

USB 3.0 System Port (AOU)

Smart Cart Slot

USB 3.0 System Port (3rd Port)

IR Camera

M.2 WWAN Slot

NGFF WLAN Slot

USB Camera

Fingerprint Reader

Touch Panel

USB 3.0 Port Assignment

USB 3.0 System Port / Docking

USB 3.0 System Port (AOU)

Media Card Controller

USB 3.0 System Port (3rd Port)

(PCIE 1)4

(PCIE 2)

-WWAN_SATA_DTCT

-PE_DTCT

CPU(8/16) : PCIE/USB/SATA

C

Wednesday, November 02, 2016

1

SA00005R500 SA00005RJ00 SA000066600TOSHIBA TC7PCI3212MT

PCIE6_L0_SATA1_TXP_CACHE <49> PCIE6_L0_SATA1_TXN_CACHE <49> PCIE6_L0_SATA1_RXN_CACHE <49> PCIE6_L0_SATA1_RXP_CACHE <49> PCIE6_L0_SATA1_TXP_WIGIG <48> PCIE6_L0_SATA1_TXN_WIGIG <48> PCIE6_L0_SATA1_RXN_WIGIG <48> PCIE6_L0_SATA1_RXP_WIGIG <48>

WWAN Slot

L

H

HHH

H

L H

To M.2

Disconnect

Socket1

NFC_ON <63> SATA1_DEVSLP <49> SATA2_DEVSLP <33>

-WWAN_SATA_DTCT <49>

-PE_DTCT <33>

Windu-1

Windu-1Windu-1

1

L

HHH

L H

Socket1

of

10 98

H

DisconnectTo M.2

0.1

5

D D

C C

4

SKL_ULT

U58I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U_BGA1356

9 OF 20

3

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

2

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

PLANARID1 PLANARID2 PLANARID3

PLANARID0

-INTRUDER_PCH <13>

1

TABLE

LEVEL

1 NA

0

PLANARID3 PLANARID2 PLANARID1 PLANARID0

@

R43

B B

1 2

0_0201_5%

R47 0_0201_5%

1 2

R113 0_0201_5%

@

R48 0_0201_5%

1 2

TABLE

LEVEL

SDV 0000B

FVT 0001B

FVT-2 0010B

PLANAR ID

R43 R47 R113 R48

NA NA NA

ASM ASM ASM ASM

PLANARID[3..0]

0123

SIT 0011B

SIT-R 0100B

SVT 0101B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(9/16) : CSI-2/EMMC

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

11 98

0.1

5

4

3

2

1

VCC3B

2

C9359

0.1U_0201_6.3V6-K

D D

-PCIE6_CLK_100M

-PCIE0_CLK_100M<40> PCIE0_CLK_100M<40>

-CLKREQ_PCIE0<40>

-PCIE4_CLK_100M<36> PCIE4_CLK_100M<36>

-CLKREQ_PCIE4<36>

-PCIE5_CLK_100M<48> PCIE5_CLK_100M<48>

-CLKREQ_PCIE5<48>

-PCIE8_CLK_100M<27> PCIE8_CLK_100M<27>

-CLKREQ_PCIE8<27>

-PCIE10_CLK_100M<33> PCIE10_CLK_100M<33>

-CLKREQ_PCIE10<33>

12

100K_0201_5% R10146

PCIE6_CLK_100M

-CLKREQ_PCIE8

-WWAN_SSD_DTCT_3B<10>

C C

B B

DGFX_PWRGD<8,91,92>

D707

SWG@

1SS400CMT2R_VMN2M2

-PCIE6_CLK_100M PCIE6_CLK_100M

-CLKREQ_PCIE6

2

G

U190

2

1

10

8

VCC3_SUS

R10130

D

S

Y-

Y+

SEL

OE

12

13

1

9

4

M-

VDD

5

M+

6

D-

7

D+

GND

3

PI3USB102ZMEX_UQFN10_1P4X1P8

-CLKREQ_PCIE0_PCH

12

10K_0201_5%

SWG@

Q262 LSK3541G1ET2L_VMT3

-PCIE6_CLK_100M_CACHE

PCIE6_CLK_100M_CACHE

-PCIE6_CLK_100M_WIGIG

PCIE6_CLK_100M_WIGIG

TABLE of USB2.0 SW (U190) Vendor P/N LCFC P/N PERICOM

PI3USB102ZMEX NX3DV42GU

NXP

U58J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

-CLKREQ_PCIE0_PCH-DGFX_PWRGD

D706 1SS400CMT2R_VMN2M2

12

-PCIE6_CLK_100M_CACHE <49>

PCIE6_CLK_100M_CACHE <49>

-PCIE6_CLK_100M_WIGIG <48>

PCIE6_CLK_100M_WIGIG <48>

SKL_ULT

CLOCK SIGNALS

10 OF 20

12

SA00005RH00 SA00005RI00

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

SWG@

100K_0201_5% R10129

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

XTAL24_IN XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

-CLKREQ_PCIE6

VCC1R0_SUS

1 2

R609

2.71K_0402_0.5%

VCC3B

R10147 10K_0201_5%

1 2

SUSCLK_32K <48,59>

-SRTCRST <20>

-RTCRST <17,20>

12

D712 RB521CM-30T2R_VMN2M

12

D713 RB521CM-30T2R_VMN2M

1 2

R351 10M_0201_5%

1 2

Y6 CRYSTAL 32.768KHZ 9PF 20PPM

Vendor P/N

TXC

KDS

1 2

9H03280012 SJ10000J900

1TJF090DJ1A000B

-CLKREQ_PCIE6_CACHE

-CLKREQ_PCIE6_WIGIG

R308 1M_0201_5%

1 2

R133 0_0201_5%@

1 2

C348

6.8P_0201_25V8-C

Y6

32.768KHZ 9PF 20PPM 9H03280012

1 2

C326

6.8P_0201_25V8-C

LCFC P/N

SJ100069400

-CLKREQ_PCIE6_CACHE <49>

-CLKREQ_PCIE6_WIGIG <48>

XTAL24_OUT_R

2

C205

8.2P_0402_50V8-C

1

Vendor P/N

TXC

KDS

Y5 24MHZ_8PF_8Y24080002

1

Y5 CRYSTAL - 24MHZ 8PF +-30PPM

8Y24080002 SJ10000HI00

1ZZHAE24000CC0D

GND1

3

GND2

2

4

2

C206

8.2P_0402_50V8-C

1

3

LCFC P/N

SJ10000P200

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(10/16) : CLOCK SIGNALS

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

12 98

0.1

5

1 2

-PLTRST_NEAR<27>

-PLTRST_FAR<33,36,40,48,49,59,66,67,68>

D D

100P_0201_25V8-J

R991 33_0201_5%

2

C460

1

R993

1 2

33_0201_5%

2

C46 100P_0201_25V8-J

1

VCC3M

4

U73

5

VCC

4

OUT_Y

TC7SG17FE_SON5

3

1

NC

2

IN_A

GND

-PLTRST

3

2

1

Vendor P/N LCFC P/N TOSHIBA ON

C C

R19

4.7K_0201_5%

-XDP_DBR<17,19>

-RSMRST<19,60>

BPWRG<52,60,63,67,69>

CPUCORE_PWRGD<76>

MPWRG<60,69>

-PCIE_WAKE<27,48,68>

-LANWAKE<36> LANPHYPC<36>

B B

MPWRG

VCC3_SUS VCC1R0_SUS

TABLE of U73

TC7SG17FE NL17SZ17XV5T2G SN74LVC1G17DRLRTI SA00005MG00

VCC3M

R612 1K_0201_5%

1 2

-SUSWARN

TP160Test_Point_22MIL

SA00005T00J SA00005OU00

CPU_PWRGD

1

VCCST_PWRGD

1 2

R21 0_0201_5%@

1 2

R617 0_0201_5%@

1 2

R203 0_0201_5%@

1 2

R1884 0_0201_5%@

RTCVCC VCC3M

R646 1M_0201_5%

1 2

2

C7 1000P_0201_25V7-K

@

1

U58K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKYLAKE-U_BGA1356

-INTRUDER_PCH<11>

R10314 0_0201_5%

SKL_ULT

SYSTEM POWER MANAGEMENT

1 2

11 OF 20

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

S3

1

4

2

3

SPVR310100_4P

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

-INTRUDER

AM10 AM11

R10 0_0201_5%

R614 10K_0201_5%

@

1 2

D5

1 2

RB520CM-30T2R_VMN2M2

-PCH_SLP_S0 <17,83>

-PCH_SLP_S3 <17,27,60,68,96>

-PCH_SLP_S4 <17,60,68,84>

-PCH_SLP_S5 <17,68>

-PCH_SLP_SUS <60>

-PCH_SLP_LAN <61>

-PCH_SLP_WLAN <60>

-PCH_SLP_M <17,68>

-PWRSW_EC <60>

AC_PRESENT <60>

-BATLOW <27,61>

-EXT_PWR_GATE <16>

-INTRUDER_EC

-INTRUDER_EC <61>

D5:SCS00007M00(RB520CM)

R2324 10K_0201_5%

1 2

13

CPUCORE_ON<68,76>

A A

5

CPUCORE_ON

2

G

D

Q194 LSK3541G1ET2L_VMT3

S

4

2

G

R2325 10K_0201_5%

1 2

13

D

Q195 LSK3541G1ET2L_VMT3

S

VCCST_PWRGD

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(11/16) : SYSTEM PM

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

13 98

0.1

5

D D

4

3

R769

1 2

0.01_0603_LE_1%

@

2

VCCSTG_CPUVCCSTG

1

VCCCPUCORE

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40

AM32

C C

B B

AM33 AM35 AM37 AM38

AK32

AB62

AC63 AE63

AE62 AG62

G30

K32

P62

V62

H63

G61

AL63 AJ62

SKL_ULT

U58L

CPU POWER 1 OF 4

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO_AE62 VCCEOPIO_AG62

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKYLAKE-U_BGA1356

12 OF 20

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

VCCCPUCORE

VCCSTG_CPU

VCCCPUCORE

R9 100_0201_1%

1 2

R781 220_0201_5%

R70 100_0201_1%

1 2

VCCST

R2576

R782

56_0201_5%

@

1 2

R374

1 2

100_0201_5%

VCC_SENSE VSS_SENSE

-SVID_ALERT SVID_CLK SVID_DATA

VCC_SENSE <76> VSS_SENSE <76>

-SVID_ALERT <76> SVID_CLK <76> SVID_DATA <76>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(12/16) : CPU POWER (1/2)

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

14 98

0.1

5

4

3

2

1

VCCPLL

D D

VCCGFXCORE_I

U58M

A48

AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

A53 A58 A62 A66

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71 M62 N63 N64 N66 N67 N69

J70 J69

VCCGT_A48 VCCGT_A53 VCCGT_A58 VCCGT_A62 VCCGT_A66 VCCGT_AA63 VCCGT_AA64 VCCGT_AA66 VCCGT_AA67 VCCGT_AA69 VCCGT_AA70 VCCGT_AA71 VCCGT_AC64 VCCGT_AC65 VCCGT_AC66 VCCGT_AC67 VCCGT_AC68 VCCGT_AC69 VCCGT_AC70 VCCGT_AC71 VCCGT_J43 VCCGT_J45 VCCGT_J46 VCCGT_J48 VCCGT_J50 VCCGT_J52 VCCGT_J53 VCCGT_J55 VCCGT_J56 VCCGT_J58 VCCGT_J60 VCCGT_K48 VCCGT_K50 VCCGT_K52 VCCGT_K53 VCCGT_K55 VCCGT_K56 VCCGT_K58 VCCGT_K60 VCCGT_L62 VCCGT_L63 VCCGT_L64 VCCGT_L65 VCCGT_L66 VCCGT_L67 VCCGT_L68 VCCGT_L69 VCCGT_L70 VCCGT_L71 VCCGT_M62 VCCGT_N63 VCCGT_N64 VCCGT_N66 VCCGT_N67 VCCGT_N69

VCCGT_SENSE VSSGT_SENSE

SKYLAKE-U_BGA1356

C C

B B

VCCGT_SENSE<76> VSSGT_SENSE<76>

VCCGT_SENSE VSSGT_SENSE

VCCGFXCORE_I

R2152 100_0201_1%

1 2

R2153 100_0201_1%

1 2

SKL_ULT

CPU POWER 2 OF 4

13 OF 20

@

R10186

1 2

0.01_0603_LE_1%

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71

VCCGT_T62 VCCGT_U65 VCCGT_U68 VCCGT_U71 VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71

VCCGT_Y62

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

VCCGFXCORE_I

VCCST_CPU VCCSTG_CPU VCCST_CPU

2

1

2

C2422

1

1U_0402_6.3V6-K

2

C2423

1

1U_0402_6.3V6-K

VCCST_CPUVCCSTG_CPU

C2424

1U_0402_6.3V6-K

VCC1R2A

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKYLAKE-U_BGA1356

U58N

CPU POWER 3 OF 4

VCC1R2A VCC1R2AVCCST_CPUVCCST

SKL_ULT

2

10U_0402_6.3V6-M

VCCSA_J22 VCCSA_J23

VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

2

C1830

1

10U_0402_6.3V6-M

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

C1831

10U_0402_6.3V6-M

VCCCPUIO

2

1

VCCSA

C840

1 2

2

C1184

C1829

1

10U_0402_6.3V6-M

VCCIO_AK28 VCCIO_AK30

VCCIO_AL30

VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

VCCSA_AK23 VCCSA_AK25

VCCSA_G23

VCCSA_G25

VCCSA_G27

VCCSA_G28

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

14 OF 20

2

1

22U_0603_6.3V6-M

VCCCPUIO

1 2

R2291 100_0201_1%

C842

22U_0603_6.3V6-M

R2290 100_0201_1%

2

1

R2155 100_0201_1%

1 2

C844

22U_0603_6.3V6-M

VCCSA

VDDQC VCCPLL_OCVDDQ

VCC1R2A VCC1R2A

2

1

VCCCPUIO

2

C504

1

R2154 100_0201_1%

1 2

VSSSA_SENSE VCCSA_SENSE

2

C506

1

1U_0402_6.3V6-K

VSSSA_SENSE <76> VCCSA_SENSE <76>

2

C2427

1

1U_0402_6.3V6-K

C507

1U_0402_6.3V6-K

C2426

10U_0402_6.3V6-M

2

C505

1

1U_0402_6.3V6-K

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(13/16) : CPU POWER (2/2)

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

15 98

0.1

5

D D

-EXT_PWR_GATE<13>

R2564

@

1 2

0_0201_5%

4

VCC3_SUS

1 2

R2293 20K_0201_5%

@

R10187

1 2

0.01_0603_LE_1%

VCC3_SUS

U146

VDD1S1 ON7S2

2

D1

3

D2

SLG59M1470VTR_FC-TDFN9_1P5X2

3

VCCMPHY_GATEVCC1R0_SUS

@

4 5

6

GND

VCC3_SUS VCC1R8_SUS VCC1R0_SUS VCC1R0_SUS

2

C2428 47U_0805_6.3V6-M

1

2

C2429 47U_0805_6.3V6-M

1

2

C2430

47U_0805_6.3V6-M

1

2

C2431 47U_0805_6.3V6-M

1

VCC3M VCC3M_PCH

VCC1R0_SUS VCC1R0_SUS_PRIM

VCC1R0_SUS VCCPCHCORE

C C

VCCMPHY_GATE

@

R10188

1 2

0.01_0603_LE_1%

VCC1R0_SUS

@

R10189

1 2

0.01_0603_LE_1%

B B

@

R10220

1 2

0.01_0603_LE_1%

@

R10221

1 2

0.01_0603_LE_1%

@

R10222

1 2

0.01_0603_LE_1%

2

C2447 22U_0603_6.3V6-M

@

1

VCCMPHY_GATE_PLL

2

C2446 22U_0603_6.3V6-M

@

1

VCC1R0_SUS_PLL

2

C2655

0.1U_0201_6.3V6-K

1

NEAR V15

2

1

VCC3_SUS

C620 1U_0402_6.3V6-K

VCC3M_PCH

VCCPCHCORE

VCCMPHY_GATE

VCC1R0_SUS_PRIM

U58O

AB19

VCCPRIM_1P0_AB19

AB20

VCCPRIM_1P0_AB20

P18

VCCPRIM_1P0_P18

AF18

VCCPRIM_CORE_AF18

AF19

VCCPRIM_CORE_AF19

V20

VCCPRIM_CORE_V20

V21

VCCPRIM_CORE_V21

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0_K17

L1

VCCMPHYAON_1P0_L1

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0_K15

L15

VCCAMPHYPLL_1P0_L15

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0_AF20

AF21

VCCSRAM_1P0_AF21

T19

VCCSRAM_1P0_T19

T20

VCCSRAM_1P0_T20

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKYLAKE-U_BGA1356

SKL_ULT

CPU POWER 4 OF 4

15 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

A14

K19

L21

N20

L19

A10

AN11 AN13

VCC3_SUS

VCC1R8_SUS

VCC1R0_SUS_PRIM

VCC1R0_SUS

0.1U_0201_6.3V6-K

C795

1 2

2

C763

0.1U_0201_6.3V6-K

1

RTCVCC

2

C731 1U_0402_6.3V6-K

1

VCC3_SUS

2

1

2

1

C380 1U_0402_6.3V6-K

C503

0.1U_0201_6.3V6-K

VCC1R0_SUS_CLK2

2

C2450 22U_0603_6.3V6-M

@

1

VCC1R0_SUS_CLK4

2

C2452 22U_0603_6.3V6-M

@

1

VCC1R0_SUS_CLK5

2

C2454 22U_0603_6.3V6-M

@

1

2

C2451 22U_0603_6.3V6-M

@

1

2

C2453 22U_0603_6.3V6-M

@

1

2

C2455 22U_0603_6.3V6-M

@

1

@

R10190

1 2

0.01_0603_LE_1%

@

R10191

1 2

0.01_0603_LE_1%

@

R10192

1 2

0.01_0603_LE_1%

VCC1R0_SUS

VCC1R0_SUS VCCMPHY_GATE

2

C2433 1U_0402_6.3V6-K

1

NEAR K17 NEAR N15 NEAR N18 NEAR AA1

A A

5

4

2

C2435 1U_0402_6.3V6-K

1

VCCMPHY_GATE

2

1

3

C2439 1U_0402_6.3V6-K

VCC1R8_SUS

2

C2444 1U_0402_6.3V6-K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(14/16) : PCH POWER

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

16 98

0.1

5

4

3

2

1

APS/PETS Interface

D D

VCC3_SUS VCC3M

-PCH_SLP_S0<13,83>

-XDP_DBR<13,19>

-PWRSWITCH<26,58,67,68>

-RTCRST<12,20>

-PCH_SLP_M<13,68>

-PCH_SLP_S4<13,60,68,84>

-PCH_SLP_S5<13,68>

-PCH_SLP_S3<13,27,60,68,96>

SKL_ULT

U58P

AA65 AA68 AB15 AB16 AB18 AB21

AD13 AD16 AD19 AD20 AD21 AD62

AE64 AE65 AE66 AE67 AE68 AE69

AF10 AF15 AF17

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH63 AH64 AH67

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AL28 AL32 AL35 AL38

AL45 AL48 AL52 AL55 AL58 AL64

A5 A67 A70 AA2 AA4

AB8

AD8

AF1

AF2 AF4

AH6

AJ15 AJ18 AJ20

AJ4

AK8 AL2

AL4

GND 1 OF 3

VSS_A5 VSS_A67 VSS_A70 VSS_AA2 VSS_AA4 VSS_AA65 VSS_AA68 VSS_AB15 VSS_AB16 VSS_AB18 VSS_AB21 VSS_AB8 VSS_AD13 VSS_AD16 VSS_AD19 VSS_AD20 VSS_AD21 VSS_AD62 VSS_AD8 VSS_AE64 VSS_AE65 VSS_AE66 VSS_AE67 VSS_AE68 VSS_AE69 VSS_AF1 VSS_AF10 VSS_AF15 VSS_AF17 VSS_AF2 VSS_AF4 VSS_AF63 VSS_AG16 VSS_AG17 VSS_AG18 VSS_AG19 VSS_AG20 VSS_AG21 VSS_AG71 VSS_AH13 VSS_AH6 VSS_AH63 VSS_AH64 VSS_AH67 VSS_AJ15 VSS_AJ18 VSS_AJ20 VSS_AJ4 VSS_AK11 VSS_AK16 VSS_AK18 VSS_AK21 VSS_AK22 VSS_AK27 VSS_AK63 VSS_AK68 VSS_AK69 VSS_AK8 VSS_AL2 VSS_AL28 VSS_AL32 VSS_AL35 VSS_AL38 VSS_AL4 VSS_AL45 VSS_AL48 VSS_AL52 VSS_AL55 VSS_AL58 VSS_AL64

16 OF 20

SKYLAKE-U_BGA1356

VSS_AL65

VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71

VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63 VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68 VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48

VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63

VSS_AR8

VSS_AT2 VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35

VSS_AT4 VSS_AT42 VSS_AT56 VSS_AT58

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

AT63 AT68 AT71 AU10 AU15 AU20 AU32

1

TP929Test_Point_16MIL

1

TP926Test_Point_16MIL

1

TP934Test_Point_16MIL

1

TP927Test_Point_16MIL

1

TP928Test_Point_16MIL

AU38

AV68 AV69 AV70

AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW60 AW62 AW64 AW66

AY66

BA10

BA14

BA18

BA23

BA28

BA32

BA36

BA45

AV1

AW6

AW8

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1

BA2

F68

C C

B B

A A

1

TP931Test_Point_16MIL

1

TP932Test_Point_16MIL

1

TP933Test_Point_16MIL

U58Q

SKL_ULT

GND 2 OF 3

VSS_AT63 VSS_AT68 VSS_AT71 VSS_AU10 VSS_AU15 VSS_AU20 VSS_AU32 VSS_AU38 VSS_AV1 VSS_AV68 VSS_AV69 VSS_AV70 VSS_AV71 VSS_AW10 VSS_AW12 VSS_AW14 VSS_AW16 VSS_AW18 VSS_AW21 VSS_AW23 VSS_AW26 VSS_AW28 VSS_AW30 VSS_AW32 VSS_AW34 VSS_AW36 VSS_AW38 VSS_AW41 VSS_AW43 VSS_AW45 VSS_AW47 VSS_AW49 VSS_AW51 VSS_AW53 VSS_AW55 VSS_AW57 VSS_AW6 VSS_AW60 VSS_AW62 VSS_AW64 VSS_AW66 VSS_AW8 VSS_AY66 VSS_B10 VSS_B14 VSS_B18 VSS_B22 VSS_B30 VSS_B34 VSS_B39 VSS_B44 VSS_B48 VSS_B53 VSS_B58 VSS_B62 VSS_B66 VSS_B71 VSS_BA1 VSS_BA10 VSS_BA14 VSS_BA18 VSS_BA2 VSS_BA23 VSS_BA28 VSS_BA32 VSS_BA36 VSS_F68 VSS_BA45

17 OF 20

SKYLAKE-U_BGA1356

VSS_BA49 VSS_BA53 VSS_BA57

VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55

VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70

VSS_C1

VSS_C25

VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58

VSS_D6 VSS_D62 VSS_D66 VSS_D69 VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56

VSS_E6 VSS_E65 VSS_E71

VSS_F1

VSS_F13

VSS_F2

VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38

VSS_F4

VSS_F40 VSS_F42

VSS_BA41

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

1

TP925 Test_Point_16MIL

1

TP924 Test_Point_16MIL

1

TP923 Test_Point_16MIL

1

TP930 Test_Point_16MIL

1

TP935 Test_Point_16MIL

SKL_ULT

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

VSS_K63

K64

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

SKYLAKE-U_BGA1356

GND 3 OF 3

U58R

18 OF 20

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21

VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13

VSS_R6 VSS_T15 VSS_T17 VSS_T18

VSS_T2 VSS_T21

VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18

VSS_W13

VSS_W6 VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

J41 FCI_10051922-1810ELF

18

NC1

17

NC2

16

NC3

15

SLP_S0#

14

GND1

13

SYS_RESET#

12

GND2

11

PWRBTN#

10

GND3

9

RTCRST#

8

GND4

7

+V3.3DS

6

SLP_A#

5

SLP_S4#

4

SLP_S5#

3

VccDSW3_3

2

SLP_S3#

1

VccSus3_3

@

PEG2 PEG1

20 19

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(15/16) : GND

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

17 98

0.1

5

4

3

2

1

TABLE

CFG0 : Stall Reset Sequence after PCU PLL Lock until de-asserted 1 : No Stall

D D

0 : Stall

CFG3 : MSR Privacy Bit Feature 1 : MSR (C80h) bit[0] setting 0 : MSR (C80h) bit[0] overridden

CFG4 : eDP Enable 1 : Disabled 0 : Enabled

CFG9 : SVID Bus Communication 1 : Enabled 0 : Disabled

U58S

C C

1 2

CFG3<19>

ITP_PMODE<19>

B B

R527 0_0201_5%@

R528 0_0201_5%@

1 2

R1892 1K_0201_5%

@

1 2

R8965 1K_0201_5%

1 2

R1891 1K_0201_5%

@

1 2

R8898

1 2

49.9_0201_1%

AL25 AL27

BA70 BA68

E68

B67 D65 D67

E70 C68 D68 C67

F71 G69

F70 G68 H70 G71 H69 G70

E63

F63

E66

F66

E60

E8

AY2 AY1

D1 D3

K46

K45

C71

B70

F60

A52

J71

J68

F65 G65

F61

E61

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKYLAKE-U_BGA1356

SKL_ULT

RESERVED SIGNALS-1

19 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

AY71 AR56

AW71 AW70

AP56 C64

R2287 0_0201_5%

1 2

R2288 0_0201_5%

1 2

R2289

1 2

100K_0201_5%

VCCST

AW69 AW68

AU56

AW48

C7 U12 U11 H11

SKL_ULT

U58T

SPARE

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKYLAKE-U_BGA1356

20 OF 20

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

CPU(16/16) : CFG/RESERVED

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

18 98

0.1

5

D D

VCC1R0_SUS VCCSTG VCC1R0_SUSVCC3B

XDP_TCK1

R491 1K_0201_5%

1 2

R594 1K_0201_5%@

R588

@

1.5K_0201_1%

XDP_TCK0<6>

PCH_TCK<6>

XDP_TMS<6> XDP_TDI<6>

-XDP_TRST<6>

XDP_TDO<6>

-XDP_DBR<13,17>

ITP_PMODE<18>

-RSMRST<13,60>

C C

CFG3<18>

XDP_TCK0

XDP_TMS XDP_TDI

-XDP_TRST XDP_TDO

-XDP_DBR ITP_PMODE

-RSMRST

R2494 0_0201_5%@

R531 0_0201_5%@

-XDP_PRDY<10>

-XDP_PREQ<10>

1 2

12

-XDP_PRDY

-XDP_PREQ

1 2

4

R475 51_0201_5%

2

C8320

@

0.1U_0201_6.3V6-K

1

26 25

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

MOLEX_52435-2671

@

26 25 2424GND1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

J8

GND2

3

28 27

2

1

TABLE

Logic

Page 6 R2 ASM ASM

Page 7

B B

Page 19

Ref Des

R2559

R1892Page 18

J8

C8320

R475

R491

R588

R594

R2494

Merged

ASM

DCI 2.0

NO_ASM

ASM

NO_ASM

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/8/10

Title

XDP CONNECTOR

Size Document Number Rev

Custom

C

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

19 98

0.1

5

D D

4

3

2

1

VCC3SW

R2577

@

1.5K_0201_1%

1 2

R2578 47K_0201_5%

@

1 2

D3

C C

R4 1K_0201_5%

1 2

J12

1

2

3

GND1

4

GND2

HIGHS_WS33020-S0351-HF

@

B B

12

RB520CM-30T2R_VMN2M2

VCC3SW

D290 RB520CM-30T2R_VMN2M2

1 2

D6 RB520CM-30T2R_VMN2M2

1 2

RTCVCC

R620

1 2

20K_0201_5%

R250

1 2

20K_0201_5%

2

C287 1U_0402_6.3V6-K

@

1

2

C459 1U_0402_6.3V6-K

1

2

C285 1U_0402_6.3V6-K

1

-RTCRST

-SRTCRST

-RTCRST <12,17>

-SRTCRST <12>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

RTC BATTERY

Size Document Number Rev

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

20 98

0.1Custom

5

D D

4

VCC3_SUS

D12 RB520CM-30T2R_VMN2M2

1 2

VCC3_SUS_SPI

3

2

1

2

C429

0.1U_0201_6.3V6-K

1

C C

B B

SPI_IO3<7>

SPI_CLK<7,66>

SPI_MOSI_IO0<7,66>

SPI_CLK

R8981 33_0201_5%

R681 33_0201_5%EMC@

R674 33_0201_5%

1 2

12

2

C629

0.1U_0201_6.3V6-K

1

SPI_IO3_0_RSPI_IO3

SPI_CLK_0_R

SPI_MOSI_IO0_0_RSPI_MOSI_IO0

2

C575 33P_0201_25V8-J

EMC@

1

TABLE of SPI ROM (U49) Vendor P/N LCFC P/N WINBOND MXIC

U49

8

VCC

7

/HOLD/RESET(IO3)

6

CLK

5

DI(IO0)

W25Q128FVSIQ_SO8

2

C576 33P_0201_25V8-J

EMC@

1

TABLE

SF100 PIN HEADER INTERFACE (TOP VIEW)

VCC

1

CS#

3

MISO

5

(KEY)

7

W25Q128FVSIQ MX25L12873FM2I-10

DO(IO1)

/WP(IO2)

GND

D12.1

R681.2

R322.2

R674.2

R694.2

N/A

/CS

GND

SA00005LW00 SA00005VM00

-SPI_CS0_R -SPI_CS0

1

SPI_MISO_IO1_0_R SPI_MISO_IO1

2

3

4

GND CLK MOSI (RESET)

2

C577 33P_0201_25V8-J

EMC@

1

2 4 6 8

1 2

12

R32233_0201_5%

12

R69433_0201_5%

SPI_IO2SPI_IO2_0_R

R898033_0201_5%

-SPI_CS0 <7>

SPI_MISO_IO1 <7,66>

SPI_IO2 <7>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

SPI FLASH

Size Document Number Rev

Custom

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

21 98

0.1

5

4

3

2

1

M_A_DQ[63:0]<4>

-M_A_DQS[7:0]<4>

M_A_DQS[7:0]<4>

M_A_A[16:0]<4>

D D

VCC1R2A VCC1R2A

M_A_DQ5

M_A_DQ1 M_A_DQ4

-M_A_DQS0 M_A_DQS0

M_A_DQ2

M_A_DQ7

M_A_DQ9

M_A_DQ12

M_A_DQ10

M_A_DQ15

M_A_DQ16

M_A_DQ20

-M_A_DQS2

M_A_CKE0

M_A_BG1 M_A_BG0

M_A_A12 M_A_A9

M_A_A8 M_A_A6

M_A_DQS2

M_A_DQ23

M_A_DQ18

M_A_DQ25

M_A_DQ24

M_A_DQ30

M_A_DQ26

C C

M_A_CKE0<4>

M_A_BG1<4> M_A_BG0<4>

B B

J53A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4RB-7H

@

VSS_2

VSS_4

VSS_6

DM0_n/DBl0_n

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15 DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24 VSS_35 DQS3_c

DQS3_t

VSS_38

DQ31 VSS_40

DQ27 VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

DM8_n/DBl8_n/NC

VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

CKE1

VDD_2 ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

2 4

DQ4

6 8

DQ0

10 12 14 16

DQ6

18 20

DQ2

22 24 26 28

DQ8

30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130

M_A_DQ0

M_A_DQ6

M_A_DQ3

M_A_DQ8

M_A_DQ13

-M_A_DQS1 M_A_DQS1

M_A_DQ11

M_A_DQ14

M_A_DQ17

M_A_DQ21

M_A_DQ22

M_A_DQ19

M_A_DQ29

M_A_DQ28

-M_A_DQS3 M_A_DQS3

M_A_DQ31

M_A_DQ27

M_A_CKE1

-M_A_ACT

-M_A_ALERT

M_A_A11 M_A_A7

M_A_A5 M_A_A4

-DRAMRST

M_A_CKE1 <4>

-M_A_ACT <4>

-M_A_ALERT <4>

@

C27030.1U_0201_6.3V6-K

2

1

M_A_A1

M_A_DDRCLK0_1066M<4>

-M_A_DDRCLK0_1066M<4>

M_A_PARITY<4>

M_A_BS1<4>

-M_A_CS0<4>

M_A_ODT0<4>

-M_A_CS1<4>

M_A_ODT1<4>

-DRAMRST <5,24>

VCC3BVCC2R5A VCC0R6B

M_A_DDRCLK0_1066M

-M_A_DDRCLK0_1066M

M_A_PARITY

M_A_BS1

-M_A_CS0 M_A_A14

M_A_ODT0

-M_A_CS1

M_A_ODT1

SMB_CLK_3B<24,63,6 7> SMB_DATA_3B <24,63,67>

VCC1R2A VCC1R2A

J53B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

A14/WE_n

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

M_A_DQ37

M_A_DQ32

-M_A_DQS4 M_A_DQS4

M_A_DQ38

M_A_DQ39

M_A_DQ40

M_A_DQ44

M_A_DQ43

M_A_DQ46

M_A_DQ49

M_A_DQ52

-M_A_DQS6 M_A_DQS6

M_A_DQ50

M_A_DQ55

M_A_DQ56

M_A_DQ60

M_A_DQ59

M_A_DQ58

SMB_CLK_3B SMB_DATA_3B

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQS5

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4RB-7H

@

EVENT_n/NF

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41 VSS_67 DQS5_c

DQS5_t

VSS_70

DQ47 VSS_72

DQ43 VSS_74

DQ53 VSS_76

DQ48 VSS_78

DM6_n/DBl6_n

VSS_79

DQ54 VSS_81

DQ50 VSS_83

DQ60 VSS_85

DQ57 VSS_87 DQS7_c

DQS7_t

VSS_90

DQ63 VSS_92

DQ59 VSS_94

GND_2

132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

VTT

260

SA1

262

M_A_A2M_A_A3

M_A_DDRCLK1_1066M

-M_A_DDRCLK1_1066M

M_A_A0

M_A_A10

M_A_BS0 M_A_A16

M_A_A15 M_A_A13

M_A_DQ33

M_A_DQ36

M_A_DQ35

M_A_DQ34

M_A_DQ41

M_A_DQ45

-M_A_DQS5 M_A_DQS5

M_A_DQ42

M_A_DQ47

M_A_DQ48

M_A_DQ53

M_A_DQ54

M_A_DQ51

M_A_DQ57

M_A_DQ61

-M_A_DQS7 M_A_DQS7

M_A_DQ63

M_A_DQ62

SPD ADDRESS: 50H

M_A_DDRCLK1_1066M <4>

-M_A_DDRCLK1_1066M <4>

M_A_BS0 <4>

M_A_VREF_CA

VCC1R2A

2

C9093 47P_0201_25V8-J

RF@

1

VCC2R5A

2

C9094 47P_0201_25V8-J

RF@

1

VCC3B

2

C9095 47P_0201_25V8-J

RF@

1

2

C9104 100P_0201_50V8-J

RF@

1

2

C9105 100P_0201_50V8-J

RF@

1

2

C9106 100P_0201_50V8-J

RF@

1

VCC1R2A

R2583 1K_0201_1%

M_A_VREF_CA

1 2

R2582

M_A_VREF_CA_CPU<4>

A A

5

1 2

2_0201_1%

2

0.022U_0402_25V7-K C2659

1

R2581

24.9_0201_1%

1 2

R2584 1K_0201_1%

1 2

4

2.2U_0402_6.3V6-K

VCC3B M_A_VREF_CA

2

1

2

C2661

0.1U_0201_6.3V6-K

1

2.2U_0402_6.3V6-K

3

C2660

10U_0402_6.3V6-M

C2664

VCC2R5A

2

C2665 1U_0402_6.3V6-K

1

LC Future Center Secret Data

Deciphered Date

2

C2662

C2663

0.1U_0201_6.3V6-K

@

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

2015/08/10

Title

DDR4 SO DIMM CHANNEL-A (1/2)

Size Document Number Rev

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

22 98

0.1Custom

5

D D

VCC1R2A

4

3

2

1

2

C2671 1U_0402_6.3V6-K

1

C C

B B

VCC1R2A

2

1

VCC0R6B

2

1

VCC0R6B

2

1

C2684 10U_0402_6.3V6-M

C2697 1U_0402_6.3V6-K

C2701 10U_0402_6.3V6-M

2

C2672 1U_0402_6.3V6-K

1

2

C2685 10U_0402_6.3V6-M

1

2

C2698 1U_0402_6.3V6-K

1

2

C2702 10U_0402_6.3V6-M

1

2

C2673 1U_0402_6.3V6-K

1

2

C2686 10U_0402_6.3V6-M

1

2

C2674 1U_0402_6.3V6-K

1

2

C2687 10U_0402_6.3V6-M

1

2

C2675 1U_0402_6.3V6-K

1

2

C2688 10U_0402_6.3V6-M

1

2

C2676 1U_0402_6.3V6-K

1

2

C2689 10U_0402_6.3V6-M

1

2

C2677 1U_0402_6.3V6-K

1

2

C2690 10U_0402_6.3V6-M

1

2

C2678 1U_0402_6.3V6-K

1

2

C2691 10U_0402_6.3V6-M

1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

DDR4 SO DIMM CHANNEL-A (2/2)

Size Document Number Rev

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

23 98

0.1Custom

5

4

3

2

1

M_B_DQ[63:0]<5>

-M_B_DQS[7:0]<5>

M_B_DQS[7:0]<5>

M_B_A[16:0]<5>

D D

VCC1R2A VCC1R2A

M_B_DQ13

M_B_DQ12

-M_B_DQS1 M_B_DQS1

M_B_DQ10

M_B_DQ14

M_B_DQ4

M_B_DQ0

M_B_DQ6

M_B_DQ2

M_B_CKE0

M_B_BG1 M_B_BG0

M_B_A12 M_B_A9

M_B_A8 M_B_A6

M_B_DQ21

M_B_DQ16

-M_B_DQS2 M_B_DQS2

M_B_DQ18

M_B_DQ22

M_B_DQ29

M_B_DQ25

M_B_DQ30

M_B_DQ26

C C

M_B_CKE0<5>

M_B_BG1<5> M_B_BG0<5>

B B

J43A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4SB-7H

@

VSS_2

VSS_4

VSS_6

DM0_n/DBIO_n

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15 DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24 VSS_35 DQS3_c

DQS3_t

VSS_38

DQ31 VSS_40

DQ27 VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

DBI8_n VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

CKE1

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

2 4

DQ4

6 8

DQ0

10 12 14 16

DQ6

18 20

DQ2

22 24 26 28

DQ8

30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120

A11

122

A7

124 126

A5

128

A4

130

M_B_DQ8

M_B_DQ9

M_B_DQ15

M_B_DQ11

M_B_DQ1

M_B_DQ5

-M_B_DQS0 M_B_DQS0

M_B_DQ3

M_B_DQ7

M_B_DQ20

M_B_DQ17

M_B_DQ23

M_B_DQ19

M_B_DQ28

M_B_DQ24

-M_B_DQS3 M_B_DQS3

M_B_DQ31

M_B_DQ27

M_B_CKE1

-M_B_ACT

-M_B_ALERT

M_B_A11 M_B_A7

M_B_A5 M_B_A4

-DRAMRST

M_B_CKE1 <5>

-M_B_ACT <5>

-M_B_ALERT <5>

M_B_A1

M_B_DDRCLK0_1066M<5>

-M_B_DDRCLK0_1066M<5>

M_B_PARITY<5>

-DRAMRST <5,22>

VCC3BVCC2R5A VCC0R6B

SMB_CLK_3B<22,63,6 7> SMB_DATA_3B <22,63,67>

M_B_DDRCLK0_1066M

-M_B_DDRCLK0_1066M

M_B_PARITY

M_B_BS1

M_B_BS1<5>

-M_B_CS0

-M_B_CS0<5>

M_B_A14

M_B_ODT0

M_B_ODT0<5>

-M_B_CS1

-M_B_CS1<5>

M_B_ODT1

M_B_ODT1<5>

SMB_CLK_3B SMB_DATA_3B

VCC1R2A VCC1R2A

J43B

131

M_B_DQ37

M_B_DQ33

-M_B_DQS4 M_B_DQS4

M_B_DQ34

M_B_DQ38

M_B_DQ41

M_B_DQ40

M_B_DQ43

M_B_DQ47

M_B_DQ53

M_B_DQ48

-M_B_DQS6 M_B_DQS6

M_B_DQ50

M_B_DQ55

M_B_DQ60

M_B_DQ61

M_B_DQ59

M_B_DQ58

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4SB-7H

@

EVENT_n

VDD_10

CK1_t CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41 VSS_67 DQS5_c

DQS5_t

VSS_70

DQ47 VSS_72

DQ43 VSS_74

DQ53 VSS_76

DQ48 VSS_78

DM6_n/DBl6_n

VSS_79

DQ54 VSS_81

DQ50 VSS_83

DQ60 VSS_85

DQ57 VSS_87 DQS7_c

DQS7_t

VSS_90

DQ63 VSS_92

DQ59 VSS_94

GND_2

A2

A0

BA0

A13

RFU

SDA

SA0

Vtt

SA1

132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260

262

M_B_A2M_B_A3

M_B_DDRCLK1_1066M

-M_B_DDRCLK1_1066M

M_B_A0

M_B_A10

M_B_BS0 M_B_A16

M_B_A15 M_B_A13

M_B_DQ36

M_B_DQ32

M_B_DQ35

M_B_DQ39

M_B_DQ45

M_B_DQ44

-M_B_DQS5 M_B_DQS5

M_B_DQ42

M_B_DQ46

M_B_DQ52

M_B_DQ49

M_B_DQ51

M_B_DQ54

M_B_DQ56

M_B_DQ57

-M_B_DQS7 M_B_DQS7

M_B_DQ62

M_B_DQ63

M_B_DDRCLK1_1066M <5>

-M_B_DDRCLK1_1066M <5>

M_B_BS0 <5>

M_B_VREF_CA

SPD ADDRESS: 51H

VCC3B

1 2

R2066 10K_0201_5%

VCC1R2A

2

C9096 47P_0201_25V8-J

RF@

1

VCC2R5A

2

C9097 47P_0201_25V8-J

RF@

1

VCC3B

2

C9098 47P_0201_25V8-J

RF@

1

2

C9107 100P_0201_50V8-J

RF@

1

2

C9108 100P_0201_50V8-J

RF@

1

2

C9109 100P_0201_50V8-J

RF@

1

VCC1R2A

R2069 1K_0201_1%

M_B_VREF_CA

1 2

R2073

M_B_VREF_CA_CPU<4>

A A

5

1 2

2_0201_1%

2

0.022U_0402_25V7-K C2119

1

R2074

24.9_0201_1%

1 2

R2070 1K_0201_1%

1 2

4

2.2U_0402_6.3V6-K

VCC3B M_B_VREF_CA

2

1

2

C2118

0.1U_0201_6.3V6-K

1

2.2U_0402_6.3V6-K

3

C2117

C2120

VCC2R5A

2

C2121

0.1U_0201_6.3V6-K

@

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

10U_0402_6.3V6-M

2015/11/02

C2122

2

C2123 1U_0402_6.3V6-K

1

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

DDR4 SO DIMM CHANNEL-B (1/2)

Size Document Number Rev

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

24 98

0.1Custom

5

D D

VCC1R2A

4

3

2

1

2

C2124 1U_0402_6.3V6-K

1

VCC1R2A

2

C C

B B

1

VCC0R6B

2

1

VCC0R6B

2

1

C2132 10U_0402_6.3V6-M

C2140 1U_0402_6.3V6-K

C2144 10U_0402_6.3V6-M

2

C2125 1U_0402_6.3V6-K

1

2

C2133 10U_0402_6.3V6-M

1

2

C2141 1U_0402_6.3V6-K

1

2

C2145 10U_0402_6.3V6-M

1

2

C2126 1U_0402_6.3V6-K

1

2

C2134 10U_0402_6.3V6-M

1

2

C2127 1U_0402_6.3V6-K

1

2

C2135 10U_0402_6.3V6-M

1

2

C2128 1U_0402_6.3V6-K

1

2

C2136 10U_0402_6.3V6-M

1

2

C2129 1U_0402_6.3V6-K

1

2

C2137 10U_0402_6.3V6-M

1

2

C2130 1U_0402_6.3V6-K

1

2

C2138 10U_0402_6.3V6-M

1

2

C2131 1U_0402_6.3V6-K

1

2

C2139 10U_0402_6.3V6-M

1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

DDR4 SO DIMM CHANNEL-B (2/2)

Size Document Number Rev

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

25 98

0.1Custom

5

VCC3M VCC3P

5486

72

Q22 TPCF8004_2-3U1S

3

VCC3P_DRV

-LID_CLOSE USBP9USBP9+

1

R76 100_0201_5%

1 2

2

C603

0.1U_0402_25V6-K

1

1 2

D743 RB521CM-30T2R_VMN2M@

1 2

D742 RB521CM-30T2R_VMN2M

1 2

R2078 0_0201_5%@

1 2

R2079 0_0201_5%@

PANEL_BKLT_CTRL<3> BACKLIGHT_ON<59>

EDP_AUXN<3> EDP_AUXP<3>

EDP_TXP0<3> EDP_TXN0<3>

EDP_TXP1<3> EDP_TXN1<3>

EDP_HPD<3>

D D

VCC3P_DRV<69>

C C

TOUCH_EN<61>

USBP9-<10> USBP9+<10>

B B

A A

R361 47_0201_5%

1 2

D63 RB521CM-30T2R_VMN2M

1 2

R714 47K_0201_5%

1 2

100K_0201_5%

R10319

1 2

@

PANEL_BKLT_CTRL BACKLIGHT_ON

1 2

C8289 0.1U_0201_6.3V6-K

1 2

C8290 0.1U_0201_6.3V6-K

1 2

C8299 0.1U_0201_6.3V6-K

1 2

C8298 0.1U_0201_6.3V6-K

1 2

C8296 0.1U_0201_6.3V6-K

1 2

C8295 0.1U_0201_6.3V6-K

R38 100K_0201_5%

1 2

C9472 1000P_0201_25V7-KEMC_NS@

C9473 1000P_0201_25V7-KEMC_NS@

2

1

C724

0.01U_0402_25V7-K

2

R10319

R10319R10319

F44

F44F44

D743

D743D743

Q266

Q266Q266

R10321

R10321R10321

C9487

C9487C9487

R10320

R10320R10320

D744

D744D744

Page 61

R10322

R10322 ASM

R10322R10322

Page 61

R10323

R10323 ASM

R10323R10323

R38

R38R38

F39

F39F39

Page 61

R10307

R10307R10307

Page 61

R2412

R2412R2412

VCC3BVCC3PVCC3BVCC3TP

VCC3TP

21

1 2

R668 10K_0201_5%

F39 0.5A_32V_ERBRD0R50X

@

TOUCH_EN_R USBP9-_CONN USBP9+_CONN

EDP_AUXN_CONN EDP_AUXP_CONN

EDP_TXP0_CONN EDP_TXN0_CONN

EDP_TXP1_CONN EDP_TXN1_CONN

EMC@

C2610 1000P_0201_25V7-KEMC_NS@

D311 DF2S6.8UFS_1-1L1A2

D312 DF2S6.8UFS_1-1L1A2EMC@

12

2

1

F7

3A_32V_ERBRD3R00X

Touch Panel Sequence

Touch Panel SequenceTouch Panel Sequence

Support

Support Non-Support

SupportSupport

No ASM

No ASMNo ASM

No ASM

No ASMNo ASM

No ASM

No ASMNo ASM

No ASM

No ASMNo ASM

2

1

21

F44 0.5A_32V_ERBRD0R50X

4

VBL20VSYS

21

2

C9102 47P_0201_25V8-J

RF@

1

Non-Support

Non-SupportNon-Support

ASM

No ASM

ASMASM

No ASMNo ASM

ASM

No ASM

ASMASM

No ASMNo ASM

ASM

No ASM

ASMASM

No ASMNo ASM

ASM

No ASM

ASMASM

No ASMNo ASM

ASM

No ASM

ASMASM

No ASMNo ASM

ASM

No ASM

ASMASM

No ASMNo ASM

ASM

No ASM

ASMASM

No ASMNo ASM

ASM

No ASM

ASMASM

No ASMNo ASM

ASM No ASM

No ASM

ASMASM

No ASMNo ASM

ASM No ASM

No ASM

ASMASM

No ASMNo ASM

ASM

ASMASM

ASM

ASMASM

ASM

ASMASM

ASM

ASMASM

VCC3LCD

2

C315 1U_0402_6.3V6-K

C311

0.1U_0201_6.3V6-K

1

LCD CONNECTOR

J10

40

GND12

39

GND11

38

GND10

37

GND9

36

GND8

35

GND7

34

GND6

33

GND5

32

GND4

31

GND3

30

GND2

29

GND1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

I-PEX_20525-040E-02

@

2

C9118 100P_0201_50V8-J

RF@

1

2

C308

0.01U_0201_6.3V7-K

1

52 51 50 49 48 47 46 45 44 43 42 41

VCC3M VCC3TP

5486

72

3

Q266

@

TPCF8004_2-3U1S

2

1

RF

3

VCC3TP_ON<61>

2

C9101 47P_0201_25V8-J

RF@

1

USBP7-<10>

USBP7+<10>

2

C307

0.01U_0402_25V7-K

1

-INT_MIC_DTCT<8>

USBP7-

USBP7+

1

2

C9117 100P_0201_50V8-J

RF@

1

-LED_LOGO<59>

USBP4-<10> USBP4+<10>

MIC_DATA<52> MIC_CLK<52>

-LID_CLOSE<60>

1 2

2

1

0.9A

F3

3A_32V_ERBRD3R00X

2

C310

0.1U_0402_25V6-K

1

USBP4-

USBP4+

R10321

@

100_0201_5%

C9487

@

0.1U_0402_25V6-K

21

RF

-LED_LOGO

-INT_MIC_DTCT MIC_DATA MIC_CLK

12

R10320 33_0201_5%

D744 RB521CM-30T2R_VMN2M

1 2

VCC3P

VBL20

1.2A

2

C313 1U_0603_25V6-K

1

R102 3.9K_0402_5%

R9119 0_0402_5%@ R9120 0_0402_5%@

-LID_CLOSE

1 2

R786 0_0402_5%@

L10

EMC_NS@

1

4

DLW21SN900HQ2L_4P

SM070003100

1 2

R785 0_0402_5%@

L15

EMC_NS@

1

4

DLW21SN900HQ2L_4P

SM070003100

@

2

3

2

3

1 2

1 2 1 2

R513 33_0402_5%EMC@ R514 33_0402_5%EMC@

2

3

USBP4-_CONN

USBP4+_CONN

2

C9103 47P_0201_25V8-J

RF@

1

1 2 1 2

USBP7-_CONN

USBP7+_CONN

USBP4-_CONN USBP4+_CONN

2

1

EMC_NS@

C33 0.1U_0402_25V6-K

2

1

-PWRSWITCH<17,58,67,68>

-LED_PWR<59>

C9119 100P_0201_50V8-J

RF@

C815

EMC@

2

1

33P_0201_25V8-J

VCC3M

21

F31

0.5A_32V_ERBRD0R50X

-PWRSWITCH

-LED_PWR

1 2

R8954 100K_0201_5%

C817

EMC@

2

1

33P_0201_25V8-J

1 2

R13 33_0402_5%

21

F16

0.5A_32V_ERBRD0R50X

USBP7-_CONN USBP7+_CONN

-LID_CLOSE

2

C9127 10P_0201_25V8-J

EMC@

1

21

F26

3

VCC3BVCC3BVCC3SWVCC3SW VCC3MVCC3SW

21

F24

2

1

0.1U_0201_6.3V6-K

C2578

0.5A_32V_ERBRD0R50X

12

C2579

1A_32V_ERBRD1R00X

USBP7-_CONN USBP7+_CONN

D91 DF2S6.8UFS_1-1L1A2

EMC@

2

D93 AZ5125-02S.R7G_SOT23-3

EMC@

1

0.1U_0201_6.3V6-K

J11

30

29

28

27

26

25

24

23

22

21

2020GND1

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

I-PEX_20525-030E-02

@

12

D92 DF2S6.8UFS_1-1L1A2

EMC@

GND11 GND10

GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND23221

41 40 39 38 37 36 35 34 33

31

J52

1

2

3

4

5

6

7

GND1

8

GND2

HIGHS_FC1AF061-2201H

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2012/06/21

Title

LCD/LID/MIC/CAMERA/PWR SW

Size Document Number Rev

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

26 98

0.1Custom

5

1 2

PCIE8_L0_TXP<10> PCIE8_L0_TXN<10>

PCIE8_L1_TXP<10>

D D

C C

B B

TBT_I2C_SDA

TBT_I2C_SCL

TBTA_I2C_INT

A A

TBTB_I2C_INT

TBT_RTD3_CIO_PWR_EN

-TBT_PLUG_EVENT

TBT_SRC0_CFG1

1 2

R10168 2.2K_0201_5%

1 2

R10167 2.2K_0201_5%

1 2

R10164 10K_0201_5%

1 2

R10163 10K_0201_5%

1 2

R10169 10K_0201_5%

1 2

R10165 10K_0201_5%

1 2

R10166 1M_0201_5%

5

PCIE8_L1_TXN<10>

PCIE8_CLK_100M<12>

-PCIE8_CLK_100M<12>

-CLKREQ_PCIE8<12>

DDIP1_0P<3> DDIP1_0N<3>

DDIP1_1P<3> DDIP1_1N<3>

DDIP1_2P<3> DDIP1_2N<3>

DDIP1_3P<3> DDIP1_3N<3>

DDIP1_AUXP<3> DDIP1_AUXN<3>

DDIP1_HPD<3>

TBTA_RX2P<29> TBTA_RX2N<29>

TBTA_TX2P<29> TBTA_TX2N<29>

TBTA_TX1P<29> TBTA_TX1N<29>

TBTA_RX1P<29> TBTA_RX1N<29>

TBTA_AUXP<29> TBTA_AUXN<29>

TBTA_USB2P<29> TBTA_USB2N<29>

TBTA_LSTX<29> TBTA_LSRX<29> TBTA_HPD<29>

VCC3_TBT

TP920Test_Po int_40MIL

VCC3_TBT_LC

VCC3M

C9364 0.22U_0201_6.3V6-K

1 2

C9365 0.22U_0201_6.3V6-K

1 2

C9366 0.22U_0201_6.3V6-K

1 2

C9363 0.22U_0201_6.3V6-K

R10175 0_0201_5%@

1 2

C9369 0.1U_0201_6.3V6-K

1 2

C9370 0.1U_0201_6.3V6-K

1 2

C9371 0.1U_0201_6.3V6-K

1 2

C9372 0.1U_0201_6.3V6-K

1 2

C9373 0.1U_0201_6.3V6-K

1 2

C9374 0.1U_0201_6.3V6-K

1 2

C9375 0.1U_0201_6.3V6-K

1 2

C9376 0.1U_0201_6.3V6-K

1 2

C9377 0.1U_0201_6.3V6-K

1 2

C9378 0.1U_0201_6.3V6-K

1

1 2

R10162 1M_0201_5%

R10160 100K_0201_5%

R10161 1M_0201_5%

DPSRC_CTRLDATA

DPSRC_CTRLCLK

TBT_TMU_CLK_OUT

TBT_FORCE_PWR

TBT_RTD3_USB_PWR_EN

-BATLOW_TBT

-PCH_SLP_S3_TBT

4

1 2

R201 14K_0402_1%

1 2

R10154 10K_0402_5%

1 2

R10155 10K_0402_5%

1 2

R10156 10K_0402_5%

1 2

R10157 10K_0402_5%

1 2

R10158 4.75K_0402_0.5%

1 2

R10159 499_0201_1%

1 2

R10224 100K_0201_5%

1 2

R10225 100K_0201_5%

1 2

R10174 100K_0201_5%

1 2

R10173 10K_0402_5%

1 2

R10172 10K_0201_5%

1 2

R10171 10K_0201_5%

1 2

R10170 10K_0201_5%

4

VCC3_TBT

1 2

R10223 10K_0201_5%

PCIE8_L0_TXP_C PCIE8_L0_TXN_C

PCIE8_L1_TXP_C PCIE8_L1_TXN_C

DDIP1_0P_C DDIP1_0N_C

DDIP1_1P_C DDIP1_1N_C

DDIP1_2P_C DDIP1_2N_C

DDIP1_3P_C DDIP1_3N_C

DDIP1_AUXP_C DDIP1_AUXN_C

DPSINK_RBIAS

U186A

Y23

PCIE_RX0_P

Y22

PCIE_RX0_N

T23

PCIE_RX1_P

T22

PCIE_RX1_N

M23

NC_M23

M22

NC_M22

H23

NC_H23

H22

NC_H22

V19

PCIE_REFCLK_100_IN_P

T19

PCIE_REFCLK_100_IN_N

AC5

PCIE_CLKREQ_N

AB7

DPSNK0_ML0_P

AC7

DPSNK0_ML0_N

AB9

DPSNK0_ML1_P

AC9

DPSNK0_ML1_N

AB11

DPSNK0_ML2_P

AC11

DPSNK0_ML2_N

AB13

DPSNK0_ML3_P

AC13

DPSNK0_ML3_N

Y11

DPSNK0_AUX_P

W11

DPSNK0_AUX_N

AA2

DPSNK0_HPD

Y5

NC_Y5

R4

NC_R4

AB15

NC_AB15

AC15

NC_AC15

AB17

NC_AB17

AC17

NC_AC17

AB19

NC_AB19

AC19

NC_AC19

AB21

NC_AB21

AC21

NC_AC21

Y12

NC_Y12

W12

NC_W12

Y6

RSV_Y6

Y8

NC_Y8

N4

NC_N4

Y18

DPSNK_RBIAS

Y4

TDI

V4

TMS

T4

TCK

W4

TDO

H6

RBIAS

J6

RSENSE

A15

PA_RX1_P

B15

PA_RX1_N

A17

PA_TX1_P

B17

PA_TX1_N

A19

PA_TX0_P

B19

PA_TX0_N

B21

PA_RX0_P

A21

PA_RX0_N

Y15

PA_DPSRC_AUX_P

W15

PA_DPSRC_AUX_N

E20

PA_USB2_D_P

D20

PA_USB2_D_N

A5

PA_LSTX

A4

PA_LSRX

M4

PA_DPSRC_HPD

H19

PA_USB2_RBIAS

AC23

THERMDA_1

AB23

THERMDA_2

V18

PCIE_ATEST

AC1

TEST_EDM

L15

FUSE_VQPS

N15

NC_N15

C23

MONDC_CIO_0

C22

NC_C22

JHL6240_BGA337

PCIe GEN3

SINK PORT 0

SOURCE PORT 0

LC GPIOPOC GPIO

SINK PORT 1

TEST_PWR_GOOD

Misc

MISC

Port A

PORT B

POC

TBT PORTS

POC

MONDC_DPSNK_0

DEBUG

Y3 CRYSTAL 25MHZ 18PF 30PPM

Vendor P/N

TXC

8Y25000004 SJ10000H00J

KDS

1ZZHAE25000CC0F

3

PCIE_TX0_P PCIE_TX0_N

PCIE_TX1_P PCIE_TX1_N

NC_K23 NC_K22

NC_F23 NC_F22

PERST_N

PCIE_RBIAS

NC_R2 NC_R1

NC_N2 NC_N1

NC_L2 NC_L1

NC_J2 NC_J1

NC_W19

NC_Y19

NC_G1

NC_N6

GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7

GPIO_8 POC_GPIO_0 POC_GPIO_1 POC_GPIO_2 POC_GPIO_3 POC_GPIO_4 POC_GPIO_5 POC_GPIO_6

TEST_EN

RESET_N

XTAL_25_IN

XTAL_25_OUT

EE_DI

EE_DO

EE_CS_N

EE_CLK

PB_RX0_P PB_RX0_N

PB_TX0_P

PB_TX0_N

NC_A11 NC_B11

NC_A13 NC_B13

NC_Y16

NC_W16

NC_E19 NC_D19

NC_B4 NC_B5 NC_G2

NC_F19

MONDC_SVR

ATEST_P ATEST_N

USB2_ATEST

NC_W18

NC_AB2

R187 0_0402_5%

Y3 25MHZ_18PF_8Y25000004

1

C327

27P_0402_50V8-J

2

LCFC P/N

SJ10000P300

3

V23 V22

P23 P22

K23 K22

F23 F22

L4

N16

R2 R1

N2 N1

L2 L1

J2 J1

W19 Y19

G1

N6

U1 U2 V1 V2 W1 W2 Y1 Y2 AA1 J4 E2 D4 H4 F2 D2 F1

E1

AB5

F4

D22 D23

AB3 AC4 AC3 AB4

B7 A7

A9 B9

A11 B11

A13 B13

Y16 W16

E19 D19

B4 B5 G2

F19

D6

A23 B23

E18

W13

W18

AB2

1 2

GND1

2

PCIE8_L0_RXP_C PCIE8_L0_RXN_C

PCIE8_L1_RXP_C PCIE8_L1_RXN_C

PCIE_RBIAS

-TBT_EE_WP TBT_TMU_CLK_OUT

DPSRC_CTRLDATA DPSRC_CTRLCLK TBT_SRC0_CFG1

TBTB_I2C_INT TBT_RTD3_USB_PWR_EN

-BATLOW_TBT

-PCH_SLP_S3_TBT TBT_RTD3_CIO_PWR_EN

1 2

R10152 100_0201_5%

1 2

R10153 100_0201_5%

-TBT_RESET_R

TBT_XTAL_25_IN TBT_XTAL_25_OUT

TBT_EE_DI TBT_EE_DO

-TBT_EE_CS TBT_EE_CLK

TBT_XTAL_25_OUT

TBT_XTAL_25_IN

3

GND2

4

1

C329 27P_0402_50V8-J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

C312 0.22U_0201_6.3V6-K

1 2

C9361 0.22U_0201_6.3V6-K

1 2

C9362 0.22U_0201_6.3V6-K

1 2

C9360 0.22U_0201_6.3V6-K

1 2

R190 3.01K_0402_1%

1 2

D715 RB521CM-30T2R_VMN2M

1 2

D716 RB521CM-30T2R_VMN2M

1 2

R10292 0_0402_5%

TBT_EE_DI <29> TBT_EE_DO <29>

-TBT_EE_CS <29> TBT_EE_CLK <29>

-TBT_EE_CS

TBT_EE_DO

-TBT_EE_WP

LC Future Center Secret Data

2015/11/02

LC Future Center Secret Data

2

1

C9468

2

0.1U_0201_6.3V6-K

Deciphered Date

PCIE8_L0_RXP <10> PCIE8_L0_RXN <10>

PCIE8_L1_RXP <10> PCIE8_L1_RXN <10>

-PLTRST_NEAR <13>

TBT_I2C_SDA <29> TBT_I2C_SCL <29>

-PCIE_WAKE <13,48,68>

-TBT_PLUG_EVENT <8>

TBTA_I2C_INT <29>

TBT_FORCE_PWR <8>

-BATLOW <13,61>

-PCH_SLP_S3 <13,17,60,68,96>

-TBT_RESET <29>

R101493.3K_0201_5%

R101503.3K_0201_5%

R101483.3K_0201_5%

12

2015/08/10

1

2

3

U15

/CS

DO(IO1)

/WP(IO2)

1

VCC3_LDO_TBTA

D714 RB520CM-30T2R_VMN2M2

1 2

VCC3_LDO_TBTA_SPI

R101513.3K_0201_5%

12

8

VCC

/HOLD(IO3)

GND

W25Q80JVSSIQ_SO8

4

Title

ALPINE RIDGE (1/2)

Size Document Number Rev

Date: Sheet

DI(IO0)

5

6

CLK

7

TBT_EE_DI

TBT_EE_CLK

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

27 98

0.1Custom

5

4

3

2

1

IN from outside of Alpine Ridge

VCC3_TBT_LC

MAX

0.1A

Internal Use

D D

VCC0R9_TBT_CIO VCC0R9_TBT_USB VCC0R9_TBT_PCIE VCC0R9_TBT_DP

OUT

(TBD)

0.9A (TBD)

VCC3_TBT_S0VCC3_TBT

VCC3_TBT

VCC0R9_TBT_SVR

1

C370

C366

C367

1U_0402_6.3V6-K

VCC0R9_TBT_DP

C359

C355

1U_0402_6.3V6-K

VCC0R9_TBT_USB

C374

C C

B B

A A

1U_0402_6.3V6-K

VCC0R9_TBT_PCIE

C392

1U_0402_6.3V6-K

VCC0R9_TBT_CIO

C405

1U_0402_6.3V6-K

VCC3_TBT_S0

C368

C9355

1U_0402_6.3V6-K

47U_0603_6.3V6-M

C377

C393

C406

1U_0402_6.3V6-K

C394

C395

1U_0402_6.3V6-K

C407

1U_0402_6.3V6-K

1 2

C358

C356

C357

C361

C360

1U_0402_6.3V6-K

L51

1UH_PCFE20161T-1R0MDR_2.1A_20%

VCC3_TBT

C399

1U_0402_6.3V6-K

VCC3_TBT_ANA_PCIE VCC3_TBT_ANA_USB2

C400

1U_0402_6.3V6-K

0.1U_0402_16V7-K

U186B

L8

VCC0P9_DP_1

L11

NC_L11

L12

NC_L12

M8

VCC0P9_DP_2

T11

VCC0P9_DP_3

T12

VCC0P9_DP_4

L6

NC_L6

M6

NC_M6

V11

VCC0P9_ANA_DPSNK_1

V12

VCC0P9_ANA_DPSNK_2

V13

VCC0P9_ANA_DPSNK_3

M13

VCC0P9_PCIE_1

M15

VCC0P9_PCIE_2

M16

VCC0P9_PCIE_3

L19

NC_L19

N19

VCC0P9_ANA_PCIE_1

L18

VCC0P9_ANA_PCIE_2_1

M18

VCC0P9_ANA_PCIE_2_2

N18

VCC0P9_ANA_PCIE_2_3

R15

VCC0P9_USB_1

R16

VCC0P9_USB_2

R8

VCC0P9_CIO_1

R9

VCC0P9_CIO_2

R11

VCC0P9_CIO_3

R12

VCC0P9_CIO_4

L16

VCC3P3_ANA_PCIE

J16

VCC3P3_ANA_USB2

A6

VSS_ANA_1

A8

VSS_ANA_2

A10

VSS_ANA_3

A12

VSS_ANA_4

A14

VSS_ANA_5

A16

VSS_ANA_6

A18

VSS_ANA_7

A20

VSS_ANA_8

A22

VSS_ANA_9

B6

VSS_ANA_10

B8

VSS_ANA_11

B10

VSS_ANA_12

B12

VSS_ANA_13

B14

VSS_ANA_14

B16

VSS_ANA_15

B18

VSS_ANA_16

B20

VSS_ANA_17

B22

VSS_ANA_18

D8

VSS_ANA_19

D9

VSS_ANA_20

D11

VSS_ANA_21

D12

VSS_ANA_22

D13

VSS_ANA_23

D15

VSS_ANA_24

D16

VSS_ANA_25

D18

VSS_ANA_26

E8

VSS_ANA_27

E9

VSS_ANA_28

E11

VSS_ANA_29

E15

VSS_ANA_30

E16

VSS_ANA_31

E22

VSS_ANA_32

E23

VSS_ANA_33

F9

VSS_ANA_34

F16

VSS_ANA_35

F20

VSS_ANA_36

G22

VSS_ANA_37

G23

VSS_ANA_38

H1

VSS_ANA_39

H2

VSS_ANA_40

H12

VSS_ANA_41

H13

VSS_ANA_42

H15

VSS_ANA_43

H16

VSS_ANA_44

H20

VSS_ANA_45

J5

VSS_ANA_46

J18

VSS_ANA_47

J19

VSS_ANA_48

J20

VSS_ANA_49

J22

VSS_ANA_50

J23

VSS_ANA_51

K1

VSS_ANA_52

K2

VSS_ANA_53

L5

VSS_ANA_54

L20

VSS_ANA_55

L22

VSS_ANA_56

L23

VSS_ANA_57

M1

VSS_ANA_58

M2

VSS_ANA_59

M5

VSS_ANA_60

M19

VSS_ANA_61

M20

VSS_ANA_62

N5

VSS_ANA_63

N20

VSS_ANA_64

N22

VSS_ANA_65

N23

VSS_ANA_66

R6

VCC3P3_LC

VSS_ANA_67P1VSS_ANA_68P2VSS_ANA_69R5VSS_ANA_70

R18

R19

F8

VCC3P3_SX

VSS_ANA_71

VSS_ANA_72

VSS_ANA_73

R20

R22

R23

H9

R13

VCC3P3_SVR_1 VCC3P3_SVR_2 VCC3P3_SVR_3 VCC3P3A

VCC3P3_S0

VCC0P9_SVR_1

VCC0P9_SVR_2 VCC0P9_SVR_ANA_1 VCC0P9_SVR_ANA_2 VCC0P9_SVR_ANA_3 VCC0P9_SVR_ANA_4 VCC0P9_SVR_ANA_5 VCC0P9_SVR_ANA_6

VCC0P9_SVR_SENSE

SVR_VSS_1 SVR_VSS_2 SVR_VSS_3

VCC0P9_LVR_1

VCC0P9_LVR_2

VCC0P9_LVR_3 VCC0P9_LVR_SENSE

VSS_ANA_81 VSS_ANA_82 VSS_ANA_83 VSS_ANA_84 VSS_ANA_85 VSS_ANA_86 VSS_ANA_87 VSS_ANA_88 VSS_ANA_89 VSS_ANA_90 VSS_ANA_91 VSS_ANA_92 VSS_ANA_93 VSS_ANA_94 VSS_ANA_95 VSS_ANA_96 VSS_ANA_97 VSS_ANA_98

VSS_ANA_99 VSS_ANA_100 VSS_ANA_101 VSS_ANA_102 VSS_ANA_103 VSS_ANA_104 VSS_ANA_105 VSS_ANA_106 VSS_ANA_107 VSS_ANA_108 VSS_ANA_109

GND VCC

VSS_ANA_110 VSS_ANA_111 VSS_ANA_112 VSS_ANA_113 VSS_ANA_114 VSS_ANA_115 VSS_ANA_116 VSS_ANA_117

VSS_ANA_74

VSS_ANA_75T1VSS_ANA_76T2VSS_ANA_77T5VSS_ANA_78

VSS_ANA_80

VSS_ANA_79

T20

U23

U22

SVR_IND_1 SVR_IND_2 SVR_IND_3

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29

JHL6240_BGA337

A2 A3 B3

L9 M9 E12 E13 F11 F12 F13 F15 J9

TBT_SVR_IND

C1 C2 D1

0.6UH_CMME051B-R60MS_7A_20%

A1 B1 B2

VCC0R9_TBT_LVR

F18 H18 J11 H11

V5 V6 V8 V9 V15 V16 V20 W5 W6 W8 W9 W20 W22 W23 Y9 Y13 Y20 AA22 AA23 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 D5 E4 E5 E6 F5 F6 H5 H8 J8 J12 J13 J15 L13 M11 M12 N8 N9 N11 N12 N13 T6 T8 T9 T13 T15 T16 T18 AB1 AC2

VCC 0.9V from SVR (Step Voltage Regulator)

C9353

1U_0402_6.3V6-K

1 2

XFL4012-601MEC

C371

2

10U_0402_6.3V6-M

C383

C9354

1U_0402_6.3V6-K

L6

VCC 0.9V from LVR (Linear Voltage Regulator) Internal Use

1

C401

2

10U_0402_6.3V6-M

1

C373

C372

2

10U_0402_6.3V6-M

C385

C384

1U_0402_6.3V6-K

1

C390

C389

2

47U_0603_6.3V6-M

1

C403

C402

2

1U_0402_6.3V6-K

10U_0402_6.3V6-M

IN

C387

C386

1U_0402_6.3V6-K

VCC0R9_TBT_SVR

OUT

1

C391

2

47U_0603_6.3V6-M

C404

1U_0402_6.3V6-K

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

ALPINE RIDGE (2/2)

Size Document Number Rev

Custom

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

28 98

0.1

5

TBTA_VBUS_CONN

U16

B3

IN1

C2

IN2

C3

D D

2

C502

0.1U_0402_25V6-K

1

R508

1 2

1M_0201_5%

51.1K_0201_1%

R509

IN3

A1

EN#

C1

OVLO

1 2

R10087

10K_0201_5%

A2

OUT1

A3

OUT2

B2

OUT3

B1

ACOK#

GND_1A4GND_2B4GND_3

FPF2281BUCX-F130_WLCSP12

C4

VCC3M

1 2

1U_0603_25V6-K

C8333

1

2

Over Voltage Lock Out Trip Threshold = 1.20 * (1 + R508/R509)

VCC5MVCC3M

C9444

1

10U_0402_6.3V6-M

C C

TBTA_I2C_IRQ

R10299

TBTA_PRESET_CFG

1 2

1M_0201_1%

TBT_I2C_SDA<27> TBT_I2C_SCL<27> TBTA_I2C_INT<27>

I2C_DATA_TBT<61> I2C_CLK_TBT<61> TBTA_I2C_IRQ<60>

TBTA_HPD<27>

TBT_EE_CLK<27>

B B

TBT_EE_DI<27> TBT_EE_DO<27>

-TBT_EE_CS<27>

TBTA_USB2P<27> TBTA_USB2N<27>

-TBT_MRESET<61>

TBTA_LSTX<27> TBTA_LSRX<27>

TBTA_AUXP<27> TBTA_AUXN<27>

A A

1

TP936 Test_Point_20MIL

1

TP937 Test_Point_20MIL

C9441

1

22U_0603_6.3V6-M

1 2

R10250 10K_0201_5%

R10176 0_0201_5%

R10177 1M_0201_5%

R10305 1M_0201_5% R10178 1M_0201_5%

TBT_PD_THERMAL TBTA_PRESET_CFG

R10181 0_0201_5%

1 2

R10230 1M_0201_5%

1 2

R10231 1M_0201_5%

1 2

R10232 1M_0201_5%

1 2

R10233 1M_0201_5%

1 2

C9388 0.1U_0201_6.3V6-K

1 2

C9389 0.1U_0201_6.3V6-K

R10182 0_0201_5%

R10183 15K_0402_0.1%

TBTA_AUXN_C

TBTA_AUXP_C

TBT_I2C_SDA TBT_I2C_SCL

2

C9442

2

C9439

C9440

1

22U_0603_6.3V6-M

VCC3M

R10300

1 2

100K_0201_1%

1 2

1 2 1 2

1 2

1

TP921 Test_Point_12MIL

1

TP922 Test_Point_12MIL

TBTA_AUXP_C TBTA_AUXN_C

1 2

R10226 100K_0201_5%

1 2

R10227 100K_0201_5%

5

VCC3M

F1

I2C_ADDR

D1

I2C_SDA1

D2

I2C_SCL1

C1

I2C_IRQ1Z

A5

I2C_SDA2

B5

I2C_SCL2

B6

I2C_IRQ2Z

B2

GPIO0

C2

GPIO1

D10

GPIO2

G11

GPIO3

C10

GPIO4

E10

GPIO5

G10

GPIO6

D7

GPIO7

H6

GPIO8

A3

SPI_CLK

B4

SPI_MOSI

A4

SPI_MISO

B3

SPI_SSZ

L5

USB_RP_P

K5

USB_RP_N

E2

UART_TX

F2

UART_RX

F4

SWD_DATA

G4

SWD_CLK

E11

MRESET

L4

LSX_R2P

K4

LSX_P2R

L3

DEBUG3

K3

DEBUG4

L2

DEBUG1

K2

DEBUG2

J1

AUX_P

J2

AUX_N

F10

BUSPOWERZ

G2

R_OSC

U187 TPS65982DAZQZR_BGA96

VCC3_LDO_TBTA

H1

VIN_3V3

VCC3_LDO_TBTA

2

1

C9387 10U_0402_6.3V6-M

B1

VDDIO

2

1

C9385 2.2U_0402_10V6-K

C9384 2.2U_0402_10V6-K

C9386 1U_0201_6.3V6-M

C9383 2.2U_0402_10V6-K

G1

K1

E1

A2

H2

LDO_3V3

LDO_1V8A

LDO_1V8D

VOUT_3V3

GND_1

GND_2B8GND_3D6GND_4D8GND_5E5GND_6E6GND_7E7GND_8E8GND_9F5GND_10F6GND_11F7GND_12F8GND_13G5GND_14G6GND_15G7GND_16G8GND_17H4GND_18H5SSH7GND_19

A1

H10

LDO_BMC

PP_CABLE

4

TBTA_VBUS

VCC5M TBTA_VBUS

A11

B11

C11

D11

A8

B7

H11

J10

VBUS_1

GND_21A6GND_22A7GND_23

PP_5V0_1

GND_24

PP_5V0_2

PP_5V0_3

PP_5V0_4

3A

DEBUG_CTL1 DEBUG_CTL2

NC

GND_20

L1

H8

L11

1

C9470

0.22U_0201_6.3V6-K

2

4

J11

K11

VBUS_2

VBUS_3

VBUS_4

SENSEN

SENSEP

C_USB_TP C_USB_TN

HV_GATE2 HV_GATE1

C_USB_BP C_USB_BN

RPD_G1 RPD_G2

C_SBU1

C_SBU2

RESETZ

C_CC1 C_CC2

A10

B10

K6

L6

A9 B9

K7 L7

L9 L10

K9 K10

E4 D5

K8

L8

F11

TBTA_VBUS

1

2

C9471 1U_0402_25V6-K

TBTA_USB2TP TBTA_USB2TN

TBTA_USB2BP TBTA_USB2BN

TBTA_CC1 TBTA_CC2

TBTA_SBU1

TBTA_SBU2

TBTA_SBU1 TBTA_SBU2

TBTA_CC1 TBTA_CC2

1 2

C9463

0.1U_0603_50V7-K

TBTA_SBU1 TBTA_SBU2

TBTA_CC1 TBTA_CC2

Near U187

1 2

R10184 10K_0201_5%

1 2

R10185 10K_0201_5%

12

C9437 220P_0402_50V7-J

12

U193

15

SBU1

14

SBU2

12

CC1

11

CC2

20

D1

19

D2

17

D3

16

D4

3

VBIAS

THERMAL_PAD

TPD8S300_QFN20_3X3

1 2

R10243 0_0402_5%@

1 2

R10244 0_0402_5%@

1 2

R10245 0_0402_5%@

1 2

R10246 0_0402_5%@

2

C9469

0.01U_0201_6.3V7-K

1

TBTA_SENSEN_R <71>

TBTA_SENSEP_R <71>

TBTA_HV_GATE2 <71> TBTA_HV_GATE1 <71>

VCC3_LDO_TBTA

-TBT_RESET <27>

TBTA_CC1

TBTA_CC2

C9438 220P_0402_50V7-J

3

VCC3_LDO_TBTA

1

C9464

2

10

VPWR

C_SBU1 C_SBU2

C_CC1 C_CC2

RPD_G1

RPD_G2

FLT

GND1 GND2 GND3

12

R10297 21K_0201_1%

12

R10298 540_0402NEW_30%_PRF15BB541NB6RC

Put near PQ102

3

TBTA_SBU1_C

1

TBTA_SBU2_C

2

TBTA_CC1_C

4

TBTA_CC2_C

5

7

6

-FLT_REPORT

9

8 13 18 21

TBTA_SBU1_C TBTA_SBU2_C

TBTA_CC1_C TBTA_CC2_C

VCC3_LDO_TBTA

C

2

B

E

1U_0201_6.3V6-K

12

R10296 100K_0201_5%

TBT_PD_THERMAL

Q264 2SCR523MT2L_VMT3

3 1

TBTA_RX1P<27>

TBTA_RX1N<27>

TBTA_TX2N<27>

TBTA_TX2P<27>

2

D723

TBTA_RX1P

VCC3_LDO_TBTA

12

10K_0201_5%

R10242

EMC_NS@

1

D737

1

2

UCLAMP0571PPTNT_SGP1610N2-2

1 2

C9381 0.22U_0201_6.3V6-K

1 2

C9382 0.22U_0201_6.3V6-K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

TBTA_RX2P

TBTA_TX1P_C

TBTA_TX2P_C

TBTA_CC1_C

TBTA_CC2_C

TBTA_USB2BP

TBTA_USB2TP

TBTA_VBUS_CONN

TBTA_SBU2_C

TBTA_USB2BN

TBTA_USB2BP

TBTA_CC2_C

TBTA_TX2N_C

TBTA_TX2P_C

2015/11/02

PESD5V0H1BSF SOD962

EMC@

1

2

1

PESD5V0H1BSF SOD962

D724

EMC@

1

2

1

PESD5V0H1BSF SOD962

D717

EMC@

1

2

1

PESD5V0H1BSF SOD962

D718

EMC@

1

2

1

PESD5V0H1BSF SOD962

D733

EMC@

1

2

1

PESD5V0H1BSF SOD962

D734

EMC@

1

2

1

PESD5V0H1BSF SOD962

D67

EMC@

1

2

1

D68

EMC@

1

2

1

@

JTYC1

24

GND_B12

23

RX1+B11

22

RX1-_B10

21

VBUS_B9

20

SBU2_B8

19

D-_B7

18

D+_B6

17

CC2_B5

16

VBUS_B4

15

TX2-_B3

14

TX2+_B2

13

GND_B1

LC Future Center Secret Data

Deciphered Date

2

GND2525GND2626GND2727GND2828GND29

D726

EMC@

2

PESD5V0H1BSF SOD962

D725

EMC@

2

PESD5V0H1BSF SOD962

D79

EMC@

2

PESD5V0H1BSF SOD962

D719

EMC@

2

PESD5V0H1BSF SOD962

D736

EMC@

2

PESD5V0H1BSF SOD962

D735

EMC@

2

PESD5V0H1BSF SOD962

D721

EMC@

2

PESD5V0H1BSF SOD962 D722

EMC@

2

PESD5V0H1BSF SOD962

29

1

GND_A1

2

TX1+_A2

3

TX1-_A3

4

VBUS_A4

5

CC1_A5

6

D+_A6

7

D-_A7

8

SBU1_A8

9

VBUS_A9

10

RX2-_A10

11

RX2+_A11

12

GND_A12

GND30

30

JAE_DX07BL24JJ2

2015/08/10

1

TBTA_RX1N

TBTA_RX2N

TBTA_TX1N_C

TBTA_TX2N_C

TBTA_SBU1_C

TBTA_SBU2_C

TBTA_USB2BN

TBTA_USB2TN

TBTA_VBUS_CONN

C9433

C9434

C9435

C9436

10U_0603_25V6-M

2.2U_0402_25V6-K

TBTA_TX1P_C

TBTA_TX1N_C

TBTA_CC1_C

TBTA_USB2TP

TBTA_USB2TN

TBTA_SBU1_C

1 2

C9379 0.22U_0201_6.3V6-K

1 2

C9380 0.22U_0201_6.3V6-K

Title

USB-C/CONN

Size Document Number Rev

Custom

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

TBTA_TX1P <27>

TBTA_TX1N <27>

TBTA_RX2N <27>

TBTA_RX2P <27>

29 69

of

0.1

5

4

3

2

1

VCC3B

R2500

4.7K_0402_5%

1 2

2

C2544

0.01U_0201_6.3V7-K

1

DDIP2_0P_C DDIP2_0N_C DDIP2_1P_C DDIP2_1N_C DDIP2_2P_C DDIP2_2N_C DDIP2_3P_C DDIP2_3N_C

DDIP2_AUXP_C WIGIG_DP0P DDIP2_AUXN_C

PS8349B_DP_CFG0 PS8349B_DP_CFG1

PS8349B_MODE

PS8349B_PC1 PS8349B_PC2 PS8349B_PEQ

U147

1

VDD33_1

10

VDD33_2

34

VDD33_3

7

IN_HPD

8

IN_CA_DET

11

IN_D0p

12

IN_D0n

14

IN_D1p

15

IN_D1n

16

IN_D2p

17

IN_D2n

19

IN_D3p

20

IN_D3n

64

IN_AUXp

63

IN_AUXn

66

IN_DDC_SCL

65

IN_DDC_SDA

6

I2C_CTL_EN

2

DP_CFG0/SDA_CTL

3

DP_CFG1/SCL_CTL

56

CEXT

9

REXT

13

PD

5

SW0

4

SW1

21

MODE

22

PC1

45

PC2

18

PEQ

67

EPAD

PS8349BQFN66GTR-A0_QFN66_5X10

TMDS_CLKp TMDS_CLKn

TMDS_CH0p TMDS_CH0n TMDS_CH1p TMDS_CH1n TMDS_CH2p TMDS_CH2n

DP1_D0p DP1_D0n DP1_D1p DP1_D1n DP1_D2p DP1_D2n DP1_D3p DP1_D3n

DP2_D0p DP2_D0n DP2_D1p DP2_D1n DP2_D2p DP2_D2n DP2_D3p DP2_D3n

TMDS_SDA TMDS_SCL

DP1_AUXn_SDA DP1_AUXp_SCL

DP2_AUXn_SDA DP2_AUXp_SCL

TMDS_HPD

DP1_HPD DP2_HPD

DP1_CA_DET DP2_CA_DET

TMDS_PRE

TMDS_DDCBUF

25 24

28 27 30 29 33 32

55 54 52 51 50 49 47 46

44 43 41 40 39 38 36 35

57 58

61 62

59 60

31 53 42

48 37

26

23

PS8349B_TMDS_PRE

PS8349B_TMDS_DDCBUF

2

C2576

D D

DDIP2_CTRLCLK<3> DDIP2_CTRLDATA<3>

C C

1

R2378

2.2K_0201_5%

0.1U_0402_10V6-K

2

C2543

0.1U_0402_10V6-K

1

VCC3B

R2379

2.2K_0201_5%

1 2

2.2U_0402_6.3V6-K

2

C2545 .01U_0402_25V7-K

1

TP917 Test_Point_40MIL@

DDIP2_HPD<3>

DDIP2_0P<3> DDIP2_0N<3> DDIP2_1P<3> DDIP2_1N<3> DDIP2_2P<3> DDIP2_2N<3> DDIP2_3P<3> DDIP2_3N<3>

DDIP2_AUXP<3> DDIP2_AUXN<3>

2

R2515

C2587

4.99K_0201_1%

1

1 2

DDI_PRIORITY1<9>

DDI_PRIORITY2<9>

C2522 0.1U_0201_6.3V6-K C2523 0.1U_0201_6.3V6-K C2524 0.1U_0201_6.3V6-K C2525 0.1U_0201_6.3V6-K C2526 0.1U_0201_6.3V6-K C2527 0.1U_0201_6.3V6-K C2528 0.1U_0201_6.3V6-K C2529 0.1U_0201_6.3V6-K

DDIP2_AUXP

C2530 0.1U_0201_6.3V6-K

DDIP2_AUXN

C2531 0.1U_0201_6.3V6-K

R532

4.7K_0402_5%

2

C2546

0.1U_0402_10V6-K

1

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

1 2

TABLE:

SW1 SW0

LHLL

B B

LH

HH

MODE =

H : Automatic Switching mode,HDMI ID Enabled

L : Automatic Switching mode,HDMI ID Disabled

A A

Port Priority Sequence

DP1 Port > DP2 Port > TMDS Port

DP1 Port > TMDS Port > DP2 Port

TMDS Port > DP2 Port > DP1 Port

TMDS Port > DP1 Port > DP2 Port

DEFAULT

VCC3B

1 2

R2531 4.7K_0402_5%

1 2

R2523 4.7K_0402_5%

1 2

R2527 4.7K_0402_5%

1 2

R2529 4.7K_0402_5%

1 2

R146 4.7K_0402_5%

1 2

R2561 4.7K_0402_5%

1 2

R1875 4.7K_0402_5%@

1 2

R1877 4.7K_0402_5%

@

PS8349B_DP_CFG0

PS8349B_DP_CFG1

PS8349B_MODE

PS8349B_PC1

PS8349B_PC2

PS8349B_PEQ

PS8349B_TMDS_PRE

PS8349B_TMDS_DDCBUF

@

1 2

R2524 4.7K_0402_5%

@

1 2

R2528 4.7K_0402_5%

@

1 2

R2530 4.7K_0402_5%

@

1 2

R147 4.7K_0402_5%

@

1 2

R2562 4.7K_0402_5%

@

1 2

R1897 4.7K_0402_5%

@

1 2

R1899 4.7K_0402_5%

VCC3B

HDMI_CLKP HDMI_CLKN

HDMI_DATA0P HDMI_DATA0N HDMI_DATA1P HDMI_DATA1N HDMI_DATA2P HDMI_DATA2N

DOCK_DDIP2_0P DOCK_DDIP2_0N DOCK_DDIP2_1P DOCK_DDIP2_1N DOCK_DDIP2_2P DOCK_DDIP2_2N DOCK_DDIP2_3P DOCK_DDIP2_3N

WIGIG_DP0N WIGIG_DP1P WIGIG_DP1N WIGIG_DP2P WIGIG_DP2N WIGIG_DP3P WIGIG_DP3N

HDMI_DDC_DATA HDMI_DDC_CLK

DOCK_DDIP2_AUXN DOCK_DDIP2_AUXP

WIGIG_AUXN WIGIG_AUXP

HDMI_HPD_CONN DOCK_DDIP2_HPD WIGIG_HPD

12

R9129 1M_0201_5%

DDIP2_AUXN_C

R2516 1M_0402_5%

1 2

HDMI_CLKP <31> HDMI_CLKN <31>

HDMI_DATA0P <31> HDMI_DATA0N <31> HDMI_DATA1P <31> HDMI_DATA1N <31> HDMI_DATA2P <31> HDMI_DATA2N <31>

DOCK_DDIP2_0P <58> DOCK_DDIP2_0N <58> DOCK_DDIP2_1P <58> DOCK_DDIP2_1N <58> DOCK_DDIP2_2P <58> DOCK_DDIP2_2N <58> DOCK_DDIP2_3P <58> DOCK_DDIP2_3N <58>

WIGIG_DP0P <48> WIGIG_DP0N <48> WIGIG_DP1P <48> WIGIG_DP1N <48> WIGIG_DP2P <48> WIGIG_DP2N <48> WIGIG_DP3P <48> WIGIG_DP3N <48>

HDMI_DDC_DATA <31> HDMI_DDC_CLK <31>

DOCK_DDIP2_AUXN <58> DOCK_DDIP2_AUXP <58>

WIGIG_AUXN <48> WIGIG_AUXP <48>

HDMI_HPD_CONN <31> DOCK_DDIP2_HPD <58> WIGIG_HPD <48>

R2517 1M_0201_5%

1 2

DOCK_DDIP2_HPD

WIGIG_HPD

1

TP918 Test_Point_40MIL@

1

TP919 Test_Point_40MIL@

For PARADE Debug use.

HDMI_CLKN

HDMI_DATA0N

HDMI_DATA1N

HDMI_DATA2N

HDMI_DDC_DATA HDMI_DDC_CLK

HDMI_HPD_CONN

R9121 180_0402_1%@

R9123 180_0402_1%@

R9125 180_0402_1%@

R9127 180_0402_1%@

1 2

2

C2729 47P_0201_25V8-J

1

R2512 27K_0201_5%

2

C2730 47P_0201_25V8-J

1

HDMI_CLKP

HDMI_DATA0P

HDMI_DATA1P

HDMI_DATA2P

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/11/02

LC Future Center Secret Data

Deciphered Date

2

2015/08/10

Title

DDI DEMUX/HDMI LEVEL SHIFTE

Size Document Number Rev

Date: Sheet

Windu-1

Windu-1Windu-1

Wednesday, November 02, 2016

1

of

30 98

0.1Custom

Lenovo Thinkpad T470 Schematic

Specifications and Main Features

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