Lenovo Thinkpad P71 Schematics

5

LCD CONN
eDP 17.3"
FHD/QFHD

45

Thunderbolt

46-51

PCI Expre ss x4

USB2.0 CH2
USB3.0 CH2

USB2.0 CH1
USB3.0 CH1

USB2.0 CH3

USB2.0 CH4
USB3.0 CH4

USB2.0 CH5
USB3.0 CH5

USB2.0 CH6
USB3.0 CH6

USB2.0 CH14

USB2.0 CH8

USB2.0 CH10

USB2.0 CH11

USB2.0 CH12

SPI Flash TBT
4Mbits (U15)

HDMI Conn.

D D

TBT-PWR SW
/USB Type-C
(port 1)

TBT-PWR SW
/USB Type-C
(port 2)

C C

B B

52

53

USB3.0
CONN (USB2)

USB3.0
AOU (USB1)

USB2.0 M.2
WWAN Slot

USB3.0
Docking

USB3.0
CONN (USB3)

USB3.0
CONN (USB4)

USB2.0 M.2
WLAN Slot (BT)

USB2.0 2D
Camera

USB2.0
Touch Panel

USB2.0
Smart Card Slot

USB2.0
Express Slot

Right

54

Left

54

61

74

Right

54

Right

54

61

40

40

64

64

eDPx4

42

46

DPx4

DPx4

Mini DisplayPort

DisplayPort
(Docking)

HDD CONN
SSD

ODD CONN

M.2 SLOT
SSD

M.2 SLOT
SSD

Optane Memory

RTC Battery

FAN

G-Sensor

LED for Camera

LED for ThinkPad Logos

USB2.0

Port 9

A

Fingerprint
Reader

USB2.0

Port 13

Color
Sensor

54

5

SM Bus

ClickPad

40

eDP
Mux

eDPx4

dGPU MXM

NVIDIA

N17M-Q3

N17E­Q1/Q3//Q5

31

44

74

USB x 12 p orts

65

66

60

60

25

80

81

Thermal Sensor

PECI 3.0

SMB-MB/SB

CS15 Keyboard with
Numpad

41

eDPx4

PEG-16X
GEN3

DP Mux

SATA x4

CH2

CH3

CH0

CH4

Antenna

43

15

16

Embedded
Controller
MEC1653

4

Channel A

CPU

Intel

Kabylake_H

BGA1440

45W

3,4,5,6,7,8,9,10,11,12,13

DMI x4

DDR4 2400 MHz

SM Bus_B

Channel B

DDR4 2400 MHz

SM Bus_B

PCH

C-Link

Intel

Kabylake-H

vPro

14,15,16,17,18
19,20,21,22,23

LPC Bus 33MHz

75,76,77 84,85

Power Button
Subcard

7879

4

54

PCI Expre ss x7 ports

HDA

TPM 2.0

Lenovo
ASIC
ThinkEngine

USB Port 8

SM Bus

82

DDR4 / 1.2V

UNBUFFERED
DDR4
SO-DIMMA1

UNBUFFERED
DDR4
SO-DIMMB1

CPU XDP

SPI Flash
64Mbits
(SPI1)

Camera
Subcard

3

27 28

29

24

26

Stereo
Speaker

71

Microphone
Headphone

I/O SubCard Interface

USB 2.0 P8
SATA P3

LED for ThinkPad Logos

Security Cla ssification

Security Classi fication

Security Classi fication

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

40

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

DEPARTMENT EXCEP T AS AUTHORIZED BY LC FUTURE CENTE R NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEP T AS AUTHORIZED BY LC FUTURE CENTE R NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEP T AS AUTHORIZED BY LC FUTURE CENTE R NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

UNBUFFERED
DDR4
SO-DIMMA2

UNBUFFERED
DDR4
SO-DIMMB2

ALC3268 HDA
CODEC

Audio
(Docking)

67,68

68

Audio
Combo Jack

2

PY-Note Block Diagram

Project Code:
PCB(Raw Card):

Wireless LAN

30

Antenna

(M.2 WLAN Card)

Bluetooth

Type-A M.2 Card

USB

Port 14

Multi-Media
Controller
RTS5234s

67 62 64 56

I2S

74 40

AC-DC IN

Camera-(USB2)/LID SW
ODD Sub Card

LED for ThinkPad Logo
On A cover

2015/07/16

2015/07/16

2015/07/16

(UHS-II)

Internal
Mic

SD/MMC
Card Slot

DC/DC
Converter

40

40

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

I2C

DP710

1.0

61

Port 3
(X1)

M.2 SLOT
SSD

Port 13
(X1)

Express
Card Slot

63

Main

86

Battery

External Connector/Socket

Internal Connector/Socket

Internal Switch

2

SIM Card
Slot

60 60

Port 11
(X1)

Port 1
(X1)

Intel GbE PHY
JACKSONVILLE

88

2016/01/16

2016/01/16

2016/01/16

Type-B M.2 Card

1

PCB Layer Stackup

L1:TOP
L2:GND
L3:Signal
L4:PWR

Wireless WAN
Antenna

L5:Signal
L6:Signal
L7:GND
L8:Signal
L9:GND

(M.2 WWAN Ca rd)

61

USB

Port 3

M.2 SLOT
SSD

Port 19
(X1

Thunderbolt

Port 4
(X1)

61

L10:BOTTOM

Battery Charger

BQ24780SRUYR

DOCK_PWR20 M-BAT-PWR

System DC/DC

TPS51285BRUKR

VINT20

CPU DC/DC

M: NCP81205 MNTXG
S: NCP81382MNTXG

VINT20

VCCCPUIO

NB681GD-C623-Z

VCC5M

VCC1R0_SUS

TPS51362RVER

VCC5M

VCC1R2A /VCC0R6 B
+SMDDR_VREF_DIMM

LAN
MUX

57

MAGNETICS
RJ45

58,59

Docking

TPS51716RUKR

VINT20

VCC1R8B

BD9B300MUV-E2

VCC5M

VCC2R5A

BD91364AMUU-Z E2

VCC5M VCC2R5A

VCCOPC/VC CEOPIO (44e)

NB681GD-C623-Z
NB681GD-C623-Z

VCC5M VCCOPC
VCC5M VCCEOPIO

VCCGTX (44e)

NCP81210MNTXG

VINT20 VCCGTX

Title

Title

Title

TITLE PAGE

TITLE PAGE

TITLE PAGE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

1

88

OUTPUTSINPUTS

90

VCC5M
VCC3M

91

92,93,94

VCCCPUCORE
VCCGFXCORE_I
VCCSA

95

VCCCPUIO

96

VCC1R0_SUS

99

+SMDDR_VREF_DIMM

VCC0R6B
VCC1R2A

98

VCC1R8B

100

101
103

102

of

of

of

1111

1111

1111

0.1

0.1

0.1

A

5

4

3

2

1

TABLE: SYSTEM POWER STATE

Power state to be determined

D D

Schematics Mark Definition

BOM Structure 4+2 CPU

@
EMC@
RF@

C C

ME@
PRxxx,PCxxx,

PLxxx

42@
44e@

NO ASM

ASM
ASM
ASM

ASM

ASM

NO ASM

Any other mark like below is prohibited on Payton/Walter.
ESD@,EMI@,EMC_NS@,EMC_PX@,EMC_OPT@,CONN@,

4+4e CPU Note

NO ASM

ASM
ASM
ASM

ASM

NO ASM

EMC
RF
ME

Power

4+2 CPU

4+4e CPUASM

EC SMBus0 address

Device

Smart Battery

Addres s

0001 011X b

EC SMBus2 address

Device Address

Charge Controller

0001 0010

PCH SM Bus address

CH-A P

CH-A S

CH-B P

CH-B S

DDR DIMM0

DDR DIMM1

DDR DIMM2

DDR DIMM3

Addres sDevice

1001 0000b

1001 0001b

1001 0010b

1001 0011b

EC SMBus1 address

Device Address

G-Senor (LIS3DH)

G-Senor (KX023)

0011 000Xb

0011 110Xb

EC SMBus10 address

Device

Master VGA

Addres s

0x9E

PCH SM Bus0 address

Device

Intel Lan_I2 19

Addres s

0XC8

TABLE: SYSTEM COMPONENT PLACEMENT (AS OF 2014 Dec 8)

DCIN TBT-ATBT-BHDMIRJ45

CONN_NS@... RH,CH,LH(PCH related RLC)..

GPU FAN

Capacitor Naming Note

Ceramic Capacitors:

(FAN2)

DOCK

CPU

0.1U_0402_6.3VXX

Tolerance

B B

Temperature Characteristics
Rated Voltage
Package Size

Temperature Characteristics:

Symbol

Code Z5VZ5U Y5UZ5P Y5PY5V

01 32547698A

X5R NPOX7R X6SCOG

USBP1
(AOU)

DIMM

DIMM

SMARTCARD

CPU FAN
(FAN1)

M.2 SSD1

EXPRESSCARD

M.2 SSD2

mDP

USBP2

USBP5

SD CARD

USBP6

AUDIO

B

CFEDHGKJI

CJCHBJ SJSHCK UJ X5SSLUK

L

NOJ

Tolerance:

Symbol

A

Symbol P Q ZXV YS

AB DCGFJHMKN

+-0.05PF

5

+-0.25PF+-0.1PF +-1%+-0.5PF

+30,-10%+100,-0%Tolerance

+-2% +-3%Tolerance +-10%+-5% +-30%+-20%

+40,-20%+20,-10% +50,-20%+80,-20%

PCB_MB

XXX

PCB NM-B121

DAA00007D00

A

-30% ~ 10%

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

Blank

Blank

Blank

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

of

of

of

2111

2111

2111

0.1

0.1

0.1

5

4

3

2

1

D D

M_A_DQ[0..63]27,28

C C

B B

M_A_CB027,28

M_A_CB127,28
M_A_CB227,28
M_A_CB327,28
M_A_CB427,28
M_A_CB527,28

M_A_CB627,28

M_A_CB727,28

M_A_DQ0

M_A_DQ1
M_A_DQ2
M_A_DQ3

M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14

M_A_DQ15
M_A_DQ16

M_A_DQ17

M_A_DQ18
M_A_DQ19

M_A_DQ20
M_A_DQ21

M_A_DQ22
M_A_DQ23

M_A_DQ24

M_A_DQ25

M_A_DQ26
M_A_DQ27

M_A_DQ28

M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40

M_A_DQ41

M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45

M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50

M_A_DQ51
M_A_DQ52

M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61

M_A_DQ62
M_A_DQ63

M_A_CB0
M_A_CB1
M_A_CB2

M_A_CB3
M_A_CB4
M_A_CB5
M_A_CB6
M_A_CB7

U1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_CKP[0]

DDR0_CKN[0]
DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CLKP[2]

DDR0_CLKN[2]

DDR0_CLKP[3]

DDR0_CLKN[3]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_CS#[2]
DDR0_CS#[3]

DDR0_ODT[0]
DDR0_ODT[1]
DDR0_ODT[2]

DDR0_ODT[3]

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0]
DDR0_DQSN[1]

DDR0_DQSP[0]
DDR0_DQSP[1]

DDR0_DQSP[8]
DDR0_DQSN[8]

AG1

AG2
AK1

AK2

AL3

AK3

AL2

AL1

AT1
AT2
AT3

AT5

AD5
AE2
AD2
AE5

AD3

AE4

AE1

AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3
AP4
AN4
AP5

AP2
AP1
AP3
AN1

AN3

AT4
AH2

AN2
AU4
AE3
AU2
AU3

AG3

AU5

BR5
BL3
BG3

BD3

AB3
V3
R3
M3

BP5
BK3
BF3
BC3

AA3
U3
P3
L3

AY3
BA3

M_A_DDRCLK0_1066M

-M_A_DDRC LK0_1066M

-M_A_DDRC LK1_1066M
M_A_DDRCLK1_1066M
M_A_DDRCLK2_1066M

-M_A_DDRC LK2_1066M
M_A_DDRCLK3_1066M

-M_A_DDRC LK3_1066M

M_A_CKE0
M_A_CKE1
M_A_CKE2
M_A_CKE3

-M_A_CS0

-M_A_CS1

-M_A_CS2

-M_A_CS3

M_A_ODT0
M_A_ODT1

M_A_ODT2
M_A_ODT3

M_A_BA0

M_A_BA1

M_A_BG0

M_A_A16_RAS_N
M_A_A14_WE_N
M_A_A15_CAS_N

M_A_A0
M_A_A1

M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7

M_A_A8
M_A_A9
M_A_A10_AP
M_A_A11
M_A_A12
M_A_A13

M_A_BG1

-M_A_ACT

M_A_PARITY

-M_A_ALERT

-M_A_DQS0

-M_A_DQS1

-M_A_DQS2

-M_A_DQS3
M_A_DQS4

M_A_DQS5

M_A_DQS6
M_A_DQS7

M_A_DQS0
M_A_DQS1

M_A_DQS2
M_A_DQS3

-M_A_DQS4

-M_A_DQS5

-M_A_DQS6

-M_A_DQS7

M_A_DQS8

-M_A_DQS8

M_A_DDRCLK0_1066M 27

-M_A_DDRC LK0_1066M 27

-M_A_DDRC LK1_1066M 27
M_A_DDRCLK1_1066M 27
M_A_DDRCLK2_1066M 28

-M_A_DDRC LK2_1066M 28

M_A_DDRCLK3_1066M 28

-M_A_DDRC LK3_1066M 28

M_A_CKE0 27
M_A_CKE1 27
M_A_CKE2 28

M_A_CKE3 28

-M_A_CS0 27

-M_A_CS1 27

-M_A_CS2 28

-M_A_CS3 28

M_A_ODT0 27

M_A_ODT1 27

M_A_ODT2 28
M_A_ODT3 28

M_A_BA0 27,28
M_A_BA1 27,28
M_A_BG0 27,28

M_A_A16_RAS_N 27,28
M_A_A14_WE_N 27,28
M_A_A15_CAS_N 27,28

M_A_A10_AP 27,28
M_A_A11 27,28

M_A_A12 27,28
M_A_A13 27,28

M_A_BG1 27,28

-M_A_ACT 27,28

M_A_PARITY 27,28

-M_A_ALERT 27,28

M_A_DQS4 27,28
M_A_DQS5 27,28
M_A_DQS6 27,28
M_A_DQS7 27,28

-M_A_DQS4 2 7,28

-M_A_DQS5 2 7,28

-M_A_DQS6 2 7,28

-M_A_DQS7 2 7,28

M_A_DQS8 27,28

-M_A_DQS8 27,2 8

M_A_A[0..9] 27,28

-M_A_DQS[0..3] 27,28

M_A_DQS[0..3] 27,28

DDR CHANNEL
A

SKYLAKE-H-CPU_BGA1440

1 OF 14

DDR4 INTERLEAVE IMPLEMENTATION

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : DDR4 CH-A

CPU SKL-H : DDR4 CH-A

CPU SKL-H : DDR4 CH-A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

of

of

3111

3111

3111

A

0.1

0.1

0.1

5

4

3

2

1

D D

M_B_DQ[0..63]29,30

C C

B B

M_B_CB029,30

M_B_CB129,30
M_B_CB229,30
M_B_CB329,30

M_B_CB429,30
M_B_CB529,30
M_B_CB629,30
M_B_CB729,30

1

2

R543 121_0402_1%

2

R544 75_0402_1%

R545 100_0402_1%

1

1

2

M_B_DQ0

M_B_DQ1

M_B_DQ2
M_B_DQ3

M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15

M_B_DQ16
M_B_DQ17

M_B_DQ18
M_B_DQ19
M_B_DQ20

M_B_DQ21
M_B_DQ22

M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26

M_B_DQ27
M_B_DQ28

M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43

M_B_DQ44

M_B_DQ45
M_B_DQ46
M_B_DQ47

M_B_DQ48

M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52

M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57

M_B_DQ58

M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_CB0
M_B_CB1
M_B_CB2
M_B_CB3
M_B_CB4
M_B_CB5
M_B_CB6
M_B_CB7

DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2

PLACE CLOSE TO CPU

U1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKYLAKE-H-CPU_BGA1440

DDR CHANNEL B

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0]

DDR1_CKN[0]

DDR1_CKN[1]

DDR1_CKP[1]
DDR1_CLKP[2]
DDR1_CLKN[2]
DDR1_CLKP[3]
DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_CS#[2]

DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]
DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6]

DDR1_DQSN[7]

DDR1_DQSP[6]
DDR1_DQSP[7]

DDR1_DQSP[8]
DDR1_DQSN[8]

DDR_VREF_CA

DDR0_VREF_DQ

DDR1_VREF_DQ

AM9
AN9

AM8

AM7
AM11
AM10
AJ10
AJ11

AT8
AT10

AT7
AT11

AF11
AE7

AF10

AE10

AF7

AE8
AE9

AE11

AH10

AH11
AF8

AH8

AH9

AR9

AJ9

AK6
AK5

AL5
AL6

AM6

AN7
AN10

AN8

AR11

AH7

AN11

AR10

AF9

AR7

AT9

AJ7

AR8

BP9
BL9
BG9

BC9
AC9

W9
R9

M9

BR9

BJ9

BF9
BB9

AA9
V9

P9
L9

AW9
AY9

BN13
BP13

BR13

M_B_DDRCLK0_1066M

-M_B_DDRC LK0_1066M

-M_B_DDRC LK1_1066M
M_B_DDRCLK1_1066M
M_B_DDRCLK2_1066M

-M_B_DDRC LK2_1066M

M_B_DDRCLK3_1066M

-M_B_DDRC LK3_1066M

M_B_CKE0
M_B_CKE1
M_B_CKE2
M_B_CKE3

-M_B_CS0

-M_B_CS1

-M_B_CS2

-M_B_CS3

M_B_ODT0
M_B_ODT1

M_B_ODT2
M_B_ODT3

M_B_A16_RAS_N
M_B_A14_WE_N

M_B_A15_CAS_N

M_B_BA0
M_B_BA1
M_B_BG0

M_B_A0
M_B_A1

M_B_A2
M_B_A3

M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10_AP
M_B_A11
M_B_A12
M_B_A13
M_B_BG1

-M_B_ACT

M_B_PARITY

-M_B_ALERT

-M_B_DQS0

-M_B_DQS1

-M_B_DQS2

-M_B_DQS3

-M_B_DQS4

-M_B_DQS5

-M_B_DQS6

-M_B_DQS7

M_B_DQS0

M_B_DQS1

M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_DQS8

-M_B_DQS8

M_A_VREF_CA_CPU

M_B_VREF_DQ_CPU

M_B_DDRCLK0_1066M 29

-M_B_DDRC LK0_1066M 29

-M_B_DDRC LK1_1066M 29

M_B_DDRCLK1_1066M 29
M_B_DDRCLK2_1066M 30

-M_B_DDRC LK2_1066M 30
M_B_DDRCLK3_1066M 30

-M_B_DDRC LK3_1066M 30

M_B_CKE0 29
M_B_CKE1 29

M_B_CKE2 30

M_B_CKE3 30

-M_B_CS0 29

-M_B_CS1 29

-M_B_CS2 30

-M_B_CS3 30

M_B_ODT0 29
M_B_ODT1 29
M_B_ODT2 30
M_B_ODT3 30

M_B_A16_RAS_N 29,30

M_B_A14_WE_N 29,30
M_B_A15_CAS_N 29,30

M_B_BA0 29,30
M_B_BA1 29,30
M_B_BG0 29,30

M_B_A10_AP 29,30

M_B_A11 29,30
M_B_A12 29,30
M_B_A13 29,30

M_B_BG1 29,30

-M_B_ACT 29,30

M_B_PARITY 29,30

-M_B_ALERT 29,30

M_B_DQS8 29,30

-M_B_DQS8 29,3 0

M_A_VREF_CA_CPU 27

M_B_VREF_DQ_CPU 29

M_B_A[0..9] 29,30

-M_B_DQS[0..7] 29,30

M_B_DQS[0..7] 29,30

DDR_VREF_CA: Connected to VREF_CA on DIMM CH-A

DDR0_VREF_DQ: NC

A

DDR1_VREF_DQ: Connected to VREF_CA on DIMM CH-B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : DDR4 CH-B

CPU SKL-H : DDR4 CH-B

CPU SKL-H : DDR4 CH-B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

of

of

of

4111

4111

4111

0.1

0.1

0.1

5

D D

4

3

2

1

PEG_RXP[0]

PEG_RXN[0]

PEG_RXP[1]

PEG_RXN[1]

PEG_RXP[2]

PEG_RXN[2]

PEG_RXP[3]
PEG_RXN[3]

PEG_RXP[4]
PEG_RXN[4]

PEG_RXP[5]

PEG_RXN[5]

PEG_RXP[6]

PEG_RXN[6]

PEG_RXP[7]
PEG_RXN[7]

PEG_RXP[8]

PEG_RXN[8]

PEG_RXP[9]
PEG_RXN[9]

PEG_RXP[10]
PEG_RXN[10]

PEG_RXP[11]
PEG_RXN[11]

PEG_RXP[12]

PEG_RXN[12]

PEG_RXP[13]

PEG_RXN[13]

PEG_RXP[14]

PEG_RXN[14]

PEG_RXP[15]
PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0]
DMI_RXN[0]

DMI_RXP[1]
DMI_RXN[1]

DMI_RXP[2]

DMI_RXN[2]

DMI_RXP[3]
DMI_RXN[3]

SKYLAKE_HALO

BGA1440

3 OF 14

PEG_TXP[0]
PEG_TXN[0]

PEG_TXP[1]
PEG_TXN[1]

PEG_TXP[2]

PEG_TXN[2]

PEG_TXP[3]
PEG_TXN[3]

PEG_TXP[4]

PEG_TXN[4]

PEG_TXP[5]

PEG_TXN[5]

PEG_TXP[6]
PEG_TXN[6]

PEG_TXP[7]

PEG_TXN[7]

PEG_TXP[8]

PEG_TXN[8]

PEG_TXP[9]

PEG_TXN[9]

PEG_TXP[10]

PEG_TXN[10]

PEG_TXP[11]
PEG_TXN[11]

PEG_TXP[12]
PEG_TXN[12]

PEG_TXP[13]
PEG_TXN[13]

PEG_TXP[14]
PEG_TXN[14]

PEG_TXP[15]
PEG_TXN[15]

DMI_TXP[0]
DMI_TXN[0]

DMI_TXP[1]

DMI_TXN[1]

DMI_TXP[2]
DMI_TXN[2]

DMI_TXP[3]
DMI_TXN[3]

B25
A25

B24
C24

B23
A23

B22
C22

B21

A21

B20

C20

B19
A19

B18

C18

A17

B17

C16

B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10

B10

B8
A8

C6

B6

B5
A5

D4
B4

DMI_RXP0

DMI_RXN0

DMI_RXP1
DMI_RXN1

DMI_RXP2
DMI_RXN2

DMI_RXP3
DMI_RXN3

DMI_RXP0 15
DMI_RXN0 15

DMI_RXP1 15

DMI_RXN1 15

DMI_RXP2 15
DMI_RXN2 15

DMI_RXP3 15
DMI_RXN3 15

PEG_TXP0
PEG_TXN0

PEG_TXP1
PEG_TXN1

PEG_TXP2
PEG_TXN2

PEG_TXP3
PEG_TXN3

PEG_TXP4

PEG_TXN4

PEG_TXP5
PEG_TXN5

PEG_TXP6

PEG_TXN6

PEG_TXP7

PEG_TXN7

PEG_TXP8

PEG_TXN8

PEG_TXP9

PEG_TXN9

PEG_TXP10

PEG_TXN10

PEG_TXP11
PEG_TXN11

PEG_TXP12
PEG_TXN12

PEG_TXP13
PEG_TXN13

PEG_TXP14
PEG_TXN14

PEG_TXP15
PEG_TXN15

PEG_TXP0 31
PEG_TXN0 31

PEG_TXP1 31
PEG_TXN1 31

PEG_TXP2 31
PEG_TXN2 31

PEG_TXP3 31

PEG_TXN3 31

PEG_TXP4 31
PEG_TXN4 31

PEG_TXP5 31
PEG_TXN5 31

PEG_TXP6 31
PEG_TXN6 31

PEG_TXP7 31
PEG_TXN7 31

PEG_TXP8 31
PEG_TXN8 31

PEG_TXP9 31

PEG_TXN9 31

PEG_TXP10 31
PEG_TXN10 31

PEG_TXP11 31
PEG_TXN11 31

PEG_TXP12 31

PEG_TXN12 31

PEG_TXP13 31
PEG_TXN13 31

PEG_TXP14 31

PEG_TXN14 31

PEG_TXP15 31

PEG_TXN15 31

U1C

VCCCPUIO

DMI_TXP015

DMI_TXN015

DMI_TXP115

DMI_TXN115

DMI_TXP215
DMI_TXN215

DMI_TXP315
DMI_TXN315

PEG_RXP0
PEG_RXN0

PEG_RXP1

PEG_RXN1

PEG_RXP2
PEG_RXN2

PEG_RXP3
PEG_RXN3

PEG_RXP4
PEG_RXN4

PEG_RXP5

PEG_RXN5

PEG_RXP6

PEG_RXN6

PEG_RXP7
PEG_RXN7

PEG_RXP8
PEG_RXN8

PEG_RXP9
PEG_RXN9

PEG_RXP10
PEG_RXN10

PEG_RXP11
PEG_RXN11

PEG_RXP12
PEG_RXN12

PEG_RXP13
PEG_RXN13

PEG_RXP14
PEG_RXN14

PEG_RXP15
PEG_RXN15

R1

1

24.9_0402_1%

PEG_COMP_W12mil

2

DMI_TXP0
DMI_TXN0

DMI_TXP1
DMI_TXN1

DMI_TXP2

DMI_TXN2

DMI_TXP3
DMI_TXN3

PEG_RXP031
PEG_RXN031

PEG_RXP131

PEG_RXN131

PEG_RXP231

PEG_RXN231

PEG_RXP331
PEG_RXN331

PEG_RXP431
PEG_RXN431

PEG_RXP531

PEG_RXN531

PEG_RXP631

C C

B B

PEG_RXN631

PEG_RXP731
PEG_RXN731

PEG_RXP831
PEG_RXN831

PEG_RXP931
PEG_RXN931

PEG_RXP1031
PEG_RXN1031

PEG_RXP1131
PEG_RXN1131

PEG_RXP1231
PEG_RXN1231

PEG_RXP1331
PEG_RXN1331

PEG_RXP1431

PEG_RXN1431

PEG_RXP1531
PEG_RXN1531

E25

D25

E24

F24

E23

D23

E22
F22

E21

D21

E20

F20

E19

D19

E18
F18

D17

E17

F16
E16

D15

E15

F14
E14

D13

E13

F12

E12

D11

E11

F10
E10

G2

D8
E8

E6

F6

D5

E5

J8
J9

SKYLAKE-H-CPU_BGA1440

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : PEG/DMI

CPU SKL-H : PEG/DMI

CPU SKL-H : PEG/DMI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

of

of

5111

5111

5111

A

0.1

0.1

0.1

5

D D

4

3

2

1

U1D

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

C C

B B

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

SKYLAKE-H-CPU_BGA1440

SKYLAKE_HALO

BGA1440

4 OF 14

EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]

EDP_TXN[1]

EDP_TXN[2]
EDP_TXP[2]

EDP_TXN[3]
EDP_TXP[3]

EDP_AUXP
EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

EDP_TXP0_I

D29

EDP_TXN0_I

E29

EDP_TXP1_I

F28

EDP_TXN1_I

E28

EDP_TXN2_I

B29

EDP_TXP2_I

A29

EDP_TXN3_I

B28

EDP_TXP3_I

C28

EDP_AUXP_I

C26

EDP_AUXN_I

B26

A33

Leave EDP_DISP_UTIL NC

EDP_RCOMP_W20mil

D37

PROC_AUDIO_CLK_CPU

G27

PROC_AUDIO_SDO_CPU

G25

PROC_AUDIO_SDI_CPU_R

G29

2

1

C455

@

10P_0402_50V8-J

For EMC

EDP_TXP0_I 41
EDP_TXN0_I 41
EDP_TXP1_I 41
EDP_TXN1_I 41

EDP_TXN2_I 41

EDP_TXP2_I 41

EDP_TXN3_I 41
EDP_TXP3_I 41

EDP_AUXP_I 41
EDP_AUXN_I 41

1

2

R3 20_0402_1%

PLACE NEAR CPU

1 2

R638

@

33_0402_5%

PROC_AUDIO_CLK_CPU

VCCCPUIO

1

R2

24.9_0402_1%

2

PROC_AUDIO_CLK_CPU 17
PROC_AUDIO_SDO_CPU 17
PROC_AUDIO_SDI_CPU 17

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : DDI/EDP

CPU SKL-H : DDI/EDP

CPU SKL-H : DDI/EDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

of

of

6111

6111

6111

A

0.1

0.1

0.1

5

VCC3M

2

VCC1R2A

D D

C C

PROCPWRGD From PCH to CPU
RESET# From PCH to CPU

B B

CPUCORE_ON101,102,103,84,91

VCCST_PWRGD requirements (546884_SKL_H_PDG_Rev0_71)

1) Indication that the VCCST/VDDQ power supplies are stable and within specification.
(Table 41-1)

A

2) VCCST_PW RGD must go low during Sx pwr states, regardless of the voltage level of VCCST.
(Figure 41-1 Note 1)

3) VCCST_PW RGD should be equal or ealier than PCH_PW ROK.
(Table 41-5, tCPU16. See also 543016_SKL_PDG_UY_1_0)

4) VCCST_PW RGD is typically made from ALL_SYS_PWRGD
(CPUCORE_ON/VR_ON for CPU DCDC), not PCH_PWROK (CPUCORE_PWRGD).
(Figure 41-1)

1

1

2

3

2

1

5

VCC3B

R659
100K_0402_5%

@

Q55
DTC115TMT2L_VMT3

@

DDR_PG_CTRL

R77
10K_0402_5%

@

CPUCORE_ON

2

R774
100K_0402_5%

1

DDR_VTT_PG_CTRL

1

NC

2

A

2

G

VCC1R2A

1

5

U36

0.1U_0402_16V7-K

4

VCC3

Y

GND

SN74AUP1G07DCKR_SC-70

CPU_BCLK_100M20

-CPU_BCLK_ 100M20

CPU_PCI_BCLK_100M20

-CPU_PCI_BC LK_100M20

CPU_REFCLK_24M20

-CPU_REFCL K_24M20

-SVID_ALERT102,91

SVID_CLK102,91
SVID_DATA102,91

-PROCHOT102,76,91

PROCPWRGD_CPU17

-PCH_PLTRS T_PROC16

VCC3_SUS

2

R19
10K_0402_5%

1

1

D

Q1
LSK3541G1ET2L_VMT3

S

3

C709

2

VCCST_PWRGD VCCST_PWRGD_R

PM_SYNC16

PM_DOWN16

PECI16,76

-THERMTRIP16

Q1_Q2_R19

4

DDR_VTT_PG_CTRL 99

-SVID_ALERT

SVID_CLK
SVID_DATA

-PROCHOT

DDR_PG_CTRL

R14 220_0402_5%

R772 0_0402_5%

R773 0_0402_5%
R15 499_0402_1%

2

R586 60.4_0402_1%

1

R16 0_0402_5%

VCCST

R78

@

10K_0402_5%

VCC1R0_SUS

R20

@

10K_0402_5%

1 2

1

D

2

G

Q2
LSK3541G1ET2L_VMT3

S

3

4

1

1

1

1 2

1

2

12

VCCST

2

1

U36

TI

Supplier PN

SN74AUP1G07DCKR

NXP 74AUP1G07GW SA00007GU00

U1E

B31

BCLKP

A32

BCLKN

D35

PCI_BCLKP

C36

PCI_BCLKN

E31

CLK24P

D31

CLK24N

2

2

2

R1057
1K_0402_5%

-SVID_ALERT_ R

SVID_CLK_R

SVID_DATA_R

-PROCHOT_R

PROCPWRGD_CPU

-PCH_PLTRS T_PROC_R

Leave as NC

CPU_CATERR#

If VC CSTG is used inst ead of VCC1R0 _SUS,
VCCST_PWR GD will be off in sleep S0 bec ause
VCCSTG ma y be turned off when in sleep S0.
Currently, VCCSTG is still on in sleep S0,
but we may change logic to turn off VCCSTG in sleep S0.
(CT_20141216)

VCCST_PWRGD

BH31

VIDALERT#

BH32

VIDSCK

BH29

VIDSOUT

BR30

PROCHOT#

BT13

DDR_VTT_CNTL

H13

VCCST_PWRGD

BT31

PROCPWRGD

BP35

RESET#

BM34

PM_SYNC

BP31

PM_DOWN

BT34

PECI

J31

THERMTRIP#

BR33

SKTOCC#

BN1

PROC_SELECT#

BM30

CATERR#

SKYLAKE-H-CPU_BGA1440

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

SKYLAKE_HALO

BGA1440

3

5 OF 14

LCFC PN

SA00007F700

-SVID_ALERT

SVID_CLK

SVID_DATA

-PROCHOT

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]

CFG[7]
CFG[8]

CFG[9]

CFG[10]

CFG[11]

CFG[12]

CFG[13]
CFG[14]

CFG[15]

CFG[17]
CFG[16]

CFG[19]
CFG[18]

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

PROC_TDO

PROC_TDI

PROC_TMS
PROC_TCK

PROC_TRST#

PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

2015/07/16

2015/07/16

2015/07/16

2

R6
100_0402_5%

12

R9
1K_0402_1%

@

XDP_TDO 24
XDP_TDI 24
XDP_TMS 24

XDP_TCK 24

-XDP_TRST 24

-XDP_PREQ 24

-XDP_PRDY 24

VCCSTG

1 2

R7
1K_0402_1%

1

R10
1K_0402_1%

@

2

12

LOGIC

VCCST

2

DCI@

R18
51_0402_1%

1 2

LOGIC

LOGIC

R5
100_0402_5%

@

1

CFG3 24

2

R297
51_0402_1%

@

1

LOGIC

1 2

12

R8
1K_0402_1%

@

R4
56_0402_5%

1 2

BN25
BN27
BN26
BN28
BR20

BM20

BT20

BP20
BR23

BR22
BT23
BT22
BM19

BR19
BP19

BT19

BN23
BP23

BP22
BN22

BR27
BT27
BM31
BT30

BT28

BL32

BP28
BR28

BP30

BL30
BP27

BT25

CFG0

CPU_CFG1

CPU_CFG8
CPU_CFG9

CPU_CFG10
CPU_CFG11
CPU_CFG12
CPU_CFG13
CPU_CFG14
CPU_CFG15

CPU_CFG17

CPU_CFG16
CPU_CFG19
CPU_CFG18

CFG_RCOMP

TABLE

CFG[0] : Stall reset sequence after CPU PLL lock until de-asserted:
1 : No Stall
0 : Stall

CFG[2] : PEG Static Lane Reversal
1 : Normal Operation
0 : Lane Reversal

CFG[4] : eDP enable
1 : Disabled
0 : Enabled

CFG[6:5] : PEG Bifurcation, bus#:dev#:func#=0:1:0
11 : 1x16

CFG[7] : PEG Training
1 : PEG Train immediately following RESET# deassertion
0 : PEG Wait for BIOS for training

1

CFG2
CFG3
CFG4
CFG5

CFG6

CFG7

IST_TRIG
CPU_BPM1
CPU_BPM2
CPU_BPM3

TP53 Test_Point_32MIL

1

TP37 Test_Point_32MIL

1

TP38 Test_Point_32MIL

1

TP39 Test_Point_32MIL

1

TP40 Test_Point_32MIL

1

TP41 Test_Point_32MIL

1

TP42 Test_Point_32MIL

1

TP43 Test_Point_32MIL

1

TP44 Test_Point_32MIL

1

TP45 Test_Point_32MIL

1

TP46 Test_Point_32MIL

1

TP47 Test_Point_32MIL

1

TP48 Test_Point_32MIL

1

1

1

1

2

R17

49.9_0402_1%

1

TP49 Test_Point_32MIL

TP50 Test_Point_32MIL

TP51 Test_Point_32MIL

TP52 Test_Point_32MIL

CFG[19:0] pin has internal Pull up to VCCCPUIO with 5-8 k ohm.

LOGIC

CFG[19:8] : Reserved

Title

Title

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : MISC/CLK/JTAG/ CFG

CPU SKL-H : MISC/CLK/JTAG/ CFG

CPU SKL-H : MISC/CLK/JTAG/ CFG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

R11
1K_0402_1%

1

12

R12
1K_0402_1%

@

7111

7111

7111

1

R13
1K_0402_1%

@

2

of

of

0.1

0.1

0.1

A

5

4

3

2

1

SKYLAKE_HALO

D D

C C

B B

U1F

Y38

VSS_1

Y37

VSS_2

Y14

VSS_3

Y13

VSS_4

Y11

VSS_5

Y10

VSS_6

Y9

VSS_7

Y8

VSS_8

Y7

VSS_9

W34

VSS_10

W33

VSS_11

W12

VSS_12

W5

VSS_13

W4

VSS_14

W3

VSS_15

W2

VSS_16

W1

VSS_17

V30

VSS_18

V29

VSS_19

V12

VSS_20

V6

VSS_21

U38

VSS_153

U37

VSS_22

U6

VSS_23

T34

VSS_24

T33

VSS_25

T14

VSS_26

T13

VSS_27

T12

VSS_28

T11

VSS_29

T10

VSS_30

T9

VSS_31

T8

VSS_32

T7

VSS_33

T5

VSS_34

T4

VSS_35

T3

VSS_36

T2

VSS_37

T1

VSS_38

R30

VSS_39

R29

VSS_40

R12

VSS_41

P38

VSS_42

P37

VSS_43

P12

VSS_44

P6

VSS_45

N34

VSS_46

N33

VSS_47

N12

VSS_48

N11

VSS_49

N10

VSS_50

N9

VSS_51

N8

VSS_52

N7

VSS_53

N6

VSS_54

N5

VSS_55

N4

VSS_56

N3

VSS_57

N2

VSS_58

N1

VSS_59

M14

VSS_60

M13

VSS_61

M12

VSS_62

M6

VSS_63

L34

VSS_64

L33

VSS_65

L30

VSS_66

L29

VSS_67

K38

VSS_68

K11

VSS_69

K10

VSS_70

K9

VSS_71

K8

VSS_72

K7

VSS_73

K5

VSS_74

K4

VSS_75

K3

VSS_76

K2

VSS_77

SKYLAKE-H-CPU_BGA1440

BGA1440

6 OF 14

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112
VSS_113
VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135
VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

NCTFVSS_1

BT32
BT26
BT24

BT21

BT18
BT14
BT12

BR36
BR34
BR29
BR26

BR24
BR21
BR18
BR14
BR12

BP34
BP33
BP29
BP26
BP24
BP21

BP18
BP14
BP12

BN34
BN31
BN30

BN29
BN24
BN21
BN20

BN19

BN18
BN14

BN12

BM38

BM35
BM28
BM27

BM26
BM23
BM21
BM13
BM12

BM9
BM6

BM2

BL29

BK29
BK15

BK14
BJ32

BJ31

BJ25
BJ22

BH14

BH12

BH9
BH8
BH5
BH4
BH1

BG38
BG13
BG12

BF33

BF12
BE29

BD9

BC34
BC12

BB12

C17

C13

BT9

BT5

BR7

BP7

BN9
BN7

BN4
BN2

BE6

C9

K1

J36

J33

J32

J25

J22

J18

J10

J7

J4

H35

H32

H25

H22

H18

H12

H11

G28

G26

G24

G23

G22

G20

G18

G16

G14

G12

G10

G9

G8

G6

G5

G4

F36

F31
F29
F27

F25

F23

F21

F19

F17

F15

F13

F11

F9

F8

F5

F4

F3

F2

E38

E35

E34

E9

E4

D33

D30
D28

D26

D24

D22

D20

D18

D16

D14

D12

D10

D9

D6

D3

C37

C31

C29

C27

CPU_NCTF_1

D38

1

TP17 Test_Point_22MIL

SKYLAKE_HALO

U1L

SKYLAKE-H-CPU_BGA1440

VSS_154

VSS_155

VSS_156
VSS_157
VSS_158
VSS_159

VSS_160

VSS_161

VSS_162
VSS_163
VSS_164

VSS_165

VSS_166
VSS_167
VSS_168
VSS_169
VSS_170

VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182

VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188

VSS_189
VSS_190
VSS_191
VSS_192

VSS_193
VSS_194

VSS_195

VSS_196
VSS_197
VSS_198

VSS_199
VSS_200
VSS_201

VSS_202
VSS_203
VSS_204
VSS_205

VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211

VSS_212
VSS_213

VSS_214
VSS_215
VSS_216

VSS_217

VSS_218

VSS_219
VSS_220
VSS_221
VSS_222

VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228

VSS_229
VSS_230

VSS_231

VSS_232
VSS_233
VSS_234

VSS_235

VSS_236
VSS_237
VSS_238

BGA1440

12 OF 14

VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_244

VSS_245
VSS_246

VSS_247

VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

VSS_253

VSS_254
VSS_255

VSS_256

VSS_257
VSS_258
VSS_259
VSS_260

VSS_261

VSS_262

VSS_263
VSS_264

VSS_265
VSS_266

VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272

VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279

VSS_280
VSS_281
VSS_282
VSS_283
VSS_284

VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290

VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297

VSS_298
VSS_299

NCTFVSS_2

NCTFVSS_3

NCTFVSS_4

NCTFVSS_5

NCTFVSS_6
NCTFVSS_7

C25
C23
C21
C19
C15

C11

C8
C5

BM29

BM25
BM18
BM11
BM8
BM7
BM5

BM3
BL38

BL35

BL13
BL6
BK25
BK22

BK13

BK6

BJ30
BJ29

BJ15
BJ12

BH11
BH10
BH7
BH6
BH3
BH2

BG37
BG14
BG6
BF34
BF6
BE30

BE5
BE4
BE3
BE2
BE1
BD38

BD37
BD12
BD11
BD10
BD8

BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29

BB6

BB5

C2

BT36

BT35

BT4

BT3
BR38

CPU_NCTF_9
CPU_NCTF_10

CPU_NCTF_7

CPU_NCTF_8

1

TP18 Test_Point_22MIL

1

TP19 Test_Point_22MIL

1

TP23 Test_Point_22MIL

1

TP24 Test_Point_22MIL

U1M

BB4

VSS_300

BB3

VSS_301

BB2

VSS_302

BB1

VSS_303

BA38

VSS_304

BA37

VSS_305

BA12

VSS_306

BA11

VSS_307

BA10

VSS_308

BA9

VSS_309

BA8

VSS_310

BA7

VSS_311

BA6

VSS_312

B9

VSS_313

AY34

VSS_314

AY33

VSS_315

AY14

VSS_316

AY12

VSS_317

AW30

VSS_318

AW29

VSS_319

AW12

VSS_320

AW5

VSS_321

AW4

VSS_322

AW3

VSS_323

AW2

VSS_324

AW1

VSS_325

AV38

VSS_326

AV37

VSS_327

AU34

VSS_328

AU33

VSS_329

AU12

VSS_330

AU11

VSS_331

AU10

VSS_332

AU9

VSS_333

AU8

VSS_334

AU7

VSS_335

AU6

VSS_336

AT30

VSS_337

AT29

VSS_338

AT6

VSS_339

AR38

VSS_340

AR37

VSS_341

AR14

VSS_342

AR13

VSS_343

AR5

VSS_344

AR4

VSS_345

AR3

VSS_346

AR2

VSS_347

AR1

VSS_348

AP34

VSS_349

AP33

VSS_350

AP12

VSS_351

AP11

VSS_352

AP10

VSS_353

AP9

VSS_354

AP8

VSS_355

AN30

VSS_356

AN29

VSS_357

AN12

VSS_358

AN6

VSS_359

AN5

VSS_360

AM38

VSS_361

AM37

VSS_362

AM12

VSS_363

AM5

VSS_364

AM4

VSS_365

AM3

VSS_366

AM2

VSS_367

AM1

VSS_368

AL34

VSS_369

AL33

VSS_370

AL14

VSS_371

AL12

VSS_372

AL10

VSS_373

AL9

VSS_374

AL8

VSS_375

AL7

VSS_376

AL4

VSS_377

SKYLAKE-H-CPU_BGA1440

SKYLAKE_HALO

BGA1440

13 OF 14

VSS_378
VSS_379
VSS_380
VSS_381

VSS_382

VSS_383
VSS_384
VSS_385
VSS_386
VSS_387

VSS_388
VSS_389

VSS_390

VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398

VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408

VSS_409
VSS_410

VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423

VSS_424

VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431

VSS_432

VSS_433
VSS_434

VSS_435

VSS_436

VSS_437

VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446

NCTFVSS_8

NCTFVSS_9

NCTFVSS_10

NCTFVSS_11
NCTFVSS_12

AK30
AK29
AK4
AJ38

AJ37

AJ6
AJ5
AJ4

AJ3

AJ2

AJ1
AH34

AH33

AH12
AH6
AG30
AG29
AG11
AG10
AG8

AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33

AE6

AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6

AC5
AC4

AC3
AC2
AC1
AB34
AB33
AB6
AA30

AA29

AA12

A30
A28

A26

A24

A22
A20
A18
A16
A14
A12
A10
A9

A6

B37

B3

A34

A4
A3

CPU_NCTF_2

CPU_NCTF_3

CPU_NCTF_4

1

TP25 Test_Point_22MIL

1

TP26 Test_Point_22MIL

1

TP29 Test_Point_22MIL

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : GND

CPU SKL-H : GND

CPU SKL-H : GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

of

of

8111

8111

8111

A

0.1

0.1

0.1

5

4

3

2

1

D D

C C

B B

VCCCPUCORE

AA13
AA31
AA32
AA33
AA34

AA35

AA36

AA37
AA38
AB29
AB30

AB31
AB32

AB35
AB36

AB37
AB38

AC13

AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35

AC36
AD13

AD14
AD31

AD32

AD33

AD34

AD35

AD36
AD37
AD38
AE13
AE14
AE30

AE31

AE32

AE35
AE36

AE37
AE38
AF35
AF36
AF37
AF38

K13
K14

L13
N13
N14
N30

N31
N32
N35

N36
N37
N38

P13

SKYLAKE_HALO

U1G

BGA1440

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5

VCC_6

VCC_7

VCC_8
VCC_9
VCC_10
VCC_11

VCC_12
VCC_13

VCC_14

VCC_15

VCC_16
VCC_17

VCC_18

VCC_19
VCC_20

VCC_21

VCC_22
VCC_23
VCC_24
VCC_25
VCC_26

VCC_27

VCC_28

VCC_29
VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41

VCC_42

VCC_43
VCC_44

VCC_45
VCC_46
VCC_47
VCC_48
VCC_49

VCC_50

VCC_51
VCC_52

VCC_53
VCC_54
VCC_55
VCC_56

VCC_57
VCC_58
VCC_59

VCC_60
VCC_61
VCC_62

VCC_63

SKYLAKE-H-CPU_BGA1440

7 OF 14

VCC_64
VCC_65
VCC_66

VCC_67
VCC_68

VCC_69
VCC_70
VCC_71

VCC_72

VCC_73
VCC_74
VCC_75

VCC_76
VCC_77
VCC_78

VCC_79

VCC_80

VCC_81
VCC_82
VCC_83

VCC_84
VCC_85
VCC_86
VCC_87
VCC_88

VCC_89

VCC_90
VCC_91
VCC_92

VCC_93

VCC_94
VCC_95
VCC_96

VCC_97
VCC_98

VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105

VCC_106
VCC_107

VCC_108
VCC_109

VCC_110
VCC_111
VCC_112

VCC_113

VCC_114

VCC_115
VCC_116
VCC_117

VCC_118

VCC_119
VCC_120

VCC_121

VCC_122

VCC_123
VCC_124
VCC_125
VCC_126

VCC_SENSE
VSS_SENSE

VCCCPUCORE

V32
V33
V34

V35

V36

V37
V38

W13

W14

W29
W30
W31

W32
W35
W36

W37

W38

Y29
Y30
Y31

Y32
Y33
Y34
Y35
Y36

L14

P29

P30
P31

P32
P33
P34
P35

P36
R13
R31
R32
R33
R34
R35
R36
R37
R38

T29

T30
T31

T32
T35
T36

T37

T38

U29
U30
U31
U32
U33
U34

U35

U36

V13
V14
V31
P14

AG37
AG38

VCCCORE_SENSE_R
VSSCORE_SENSE_R

1 2

R750 0_0402_5%

1 2

R751 0_0402_5%

Near Processor pins

VCCCPUCORE

1

R21
100_0402_1%

2

1

R22
100_0402_1%

2

VCCCORE_SENSE 91

VSSCORE_SENSE 91

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : VCC

CPU SKL-H : VCC

CPU SKL-H : VCC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

of

of

of

9111

9111

9111

A

0.1

0.1

0.1

5

4

3

2

1

VCCGFXCORE_I

SKYLAKE_HALO

D D

C C

B B

U1H

BG34

VCCGT_1

BG35

VCCGT_2

BG36

VCCGT_3

BH33

VCCGT_4

BH34

VCCGT_5

BH35

VCCGT_6

BH36

VCCGT_7

BH37

VCCGT_8

BH38

VCCGT_9

BJ37

VCCGT_10

BJ38

VCCGT_11

BL36

VCCGT_12

BL37

VCCGT_13

BM36

VCCGT_14

BM37

VCCGT_15

BN36

VCCGT_16

BN37

VCCGT_17

BN38

VCCGT_18

BP37

VCCGT_19

BP38

VCCGT_20

BR37

VCCGT_21

BT37

VCCGT_22

BE38

VCCGT_23

BF13

VCCGT_24

BF14

VCCGT_25

BF29

VCCGT_26

BF30

VCCGT_27

BF31

VCCGT_28

BF32

VCCGT_29

BF35

VCCGT_30

BF36

VCCGT_31

BF37

VCCGT_32

BF38

VCCGT_33

BG29

VCCGT_34

BG30

VCCGT_35

BG31

VCCGT_36

BG32

VCCGT_37

BG33

VCCGT_38

BC36

VCCGT_39

BC37

VCCGT_40

BC38

VCCGT_41

BD13

VCCGT_42

BD14

VCCGT_43

BD29

VCCGT_44

BD30

VCCGT_45

BD31

VCCGT_46

BD32

VCCGT_47

BD33

VCCGT_48

BD34

VCCGT_49

BD35

VCCGT_50

BD36

VCCGT_51

BE31

VCCGT_52

BE32

VCCGT_53

BE37

VCCGT_54

SKYLAKE-H-CPU_BGA1440

BGA1440

8 OF 14

VCCGT_55
VCCGT_56

VCCGT_57
VCCGT_58
VCCGT_59
VCCGT_60
VCCGT_61

VCCGT_62
VCCGT_63
VCCGT_64
VCCGT_65
VCCGT_66
VCCGT_67
VCCGT_68

VCCGT_69
VCCGT_70
VCCGT_71

VCCGT_72
VCCGT_73
VCCGT_74

VCCGT_75

VCCGT_76

VCCGT_77

VCCGT_78

VCCGT_79
VCCGT_80

VCCGT_81
VCCGT_82
VCCGT_83
VCCGT_84

VCCGT_85

VCCGT_86

VCCGT_87

VCCGT_88
VCCGT_89
VCCGT_90

VCCGT_91

VCCGT_92

VCCGT_93

VCCGT_94

VCCGT_95
VCCGT_96

VCCGT_97

VCCGT_98

VCCGT_99
VCCGT_100
VCCGT_101

VCCGT_102

VCCGT_103
VCCGT_104

VCCGT_105

VCCGT_106

VCCGT_107
VCCGT_108

VCCGFXCORE_I

AV29

AV30

AV31
AV32
AV33
AV34
AV35

AV36
AW14
AW31
AW32
AW33
AW34

AW35
AW36
AW37
AW38

AY29
AY30
AY31

AY32

AY35

AY36

AY37

AY38
BA13

BA14
BA29
BA30
BA31

BA32

BA33

BA34

BA35
BA36
BB13

BB14

BB31

BB32

BB33

BB34
BB35

BB36

BB37

BB38
BC29
BC30

BC31

BC32
BC35

BE33
BE34
BE35
BE36

VCCGFXCORE_I

AJ29

AJ30

AJ31

AJ32
AJ33
AJ34

AJ35

AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38

AL13

AL29

AL30

AL31

AL32

AL35

AL36

AL37

AL38
AM13

AM14
AM29
AM30

AM31
AM32

AM33

AM34
AM35
AM36
AN13

AN14
AN31
AN32
AN33
AN34
AN35
AN36

AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38

AR29
AR30
AR31
AR32
AR33
AR34

AR35
AR36

AT14
AT31
AT32
AT33

AT34

AT35
AT36
AT37
AT38

AU14

AU29
AU30
AU31
AU32

AU35

AU36

AU37
AU38

U1N

VCCGT_109

VCCGT_110

VCCGT_111

VCCGT_112
VCCGT_113
VCCGT_114

VCCGT_115

VCCGT_116
VCCGT_117
VCCGT_118
VCCGT_119
VCCGT_120
VCCGT_121
VCCGT_122
VCCGT_123
VCCGT_124
VCCGT_125
VCCGT_126

VCCGT_127
VCCGT_128
VCCGT_129
VCCGT_130
VCCGT_131

VCCGT_132
VCCGT_133
VCCGT_134

VCCGT_135
VCCGT_136
VCCGT_137

VCCGT_138

VCCGT_139
VCCGT_140

VCCGT_141
VCCGT_142
VCCGT_143
VCCGT_144

VCCGT_145
VCCGT_146
VCCGT_147
VCCGT_148
VCCGT_149
VCCGT_150

VCCGT_151
VCCGT_152
VCCGT_153
VCCGT_154
VCCGT_155
VCCGT_156
VCCGT_157
VCCGT_158
VCCGT_159
VCCGT_160
VCCGT_161
VCCGT_162

VCCGT_163
VCCGT_164
VCCGT_165
VCCGT_166
VCCGT_167
VCCGT_168
VCCGT_169

VCCGT_170
VCCGT_171

VCCGT_172
VCCGT_173
VCCGT_174

VCCGT_175

VCCGT_176

VCCGT_177
VCCGT_178
VCCGT_179
VCCGT_180

VCCGT_181

VCCGT_182
VCCGT_183
VCCGT_184
VCCGT_185

VCCGT_186
VCCGT_187

VCCGT_188
VCCGT_189

SKYLAKE-H-CPU_BGA1440

SKYLAKE_HALO

BGA1440

14 OF 14

VCCGTX_1
VCCGTX_2
VCCGTX_3
VCCGTX_4
VCCGTX_5
VCCGTX_6
VCCGTX_7
VCCGTX_8

VCCGTX_9
VCCGTX_10
VCCGTX_11
VCCGTX_12
VCCGTX_13
VCCGTX_14

VCCGTX_15
VCCGTX_16
VCCGTX_17

VCCGTX_18
VCCGTX_19

VCCGTX_20

VCCGTX_21
VCCGTX_22

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31

AG32
AG33
AG34
AG35
AG36

AH13
AH14
AH29

AH30
AH31

AH32

AJ13
AJ14

AH38

AH35

AH37
AH36

42: NC (NC by DCDC side)
44e: VCCGTX

VCCGT_SENSE_R

VSSGT_SENSE_R

1 2

R752 0_0402_5%

1 2

R754 0_0402_5%

VCCGFXCORE_I

1

R23
100_0402_1%

2

12

R24
100_0402_1%

VCCGT_SENSE 91

VSSGT_SENSE 91

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : VCCGT/VCCGTX

CPU SKL-H : VCCGT/VCCGTX

CPU SKL-H : VCCGT/VCCGTX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

PAYTON

PAYTON

PAYTON

1

of

of

of

10 111

10 111

10 111

A

0.1

0.1

0.1

5

D D

C C

B B

4

VCCSA

VCCSA_1
VCCSA_2

VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6

VCCSA_7

VCCSA_8
VCCSA_9

VCCSA_10

VCCSA_11

VCCSA_12
VCCSA_13
VCCSA_14
VCCSA_15
VCCSA_16
VCCSA_17

VCCSA_18

VCCSA_19

VCCSA_20

VCCSA_21
VCCSA_22

VCCIO_1
VCCIO_2

VCCIO_3

VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13

VCCIO_14

VCCIO_15

VCCIO_16
VCCIO_17
VCCIO_18

VCCIO_19
VCCIO_20

VCCIO_21

SKYLAKE_HALO

BGA1440

U1I

J30

K29

K30
K31
K32
K33

K34

K35

L31
L32

L35

L36
L37

L38
M29
M30
M31

M32

M33

VCCCPUIO

1

1

1

C289

C379

2

2

10U_0603_6.3V6-M

C380

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

M34

M35
M36

AG12

G15

G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27

J15

J16

J17

J19

J20

J21

J26

J27

SKYLAKE-H-CPU_BGA1440

9 OF 14

3

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

VDDQ_13

VDDQ_14

VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21

VDDQ_22
VDDQ_23
VDDQ_24

VDDQC

VCCPLL_OC_1

VCCPLL_OC_2

VCCST

VCCSTG_1

VCCSTG_2

VCCPLL_1
VCCPLL_2

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE
VSSIO_SENSE

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7

AR12

AR6

AT12

AW6

AY6
J5
J6
K12
K6
L12

L6
R6
T6
W6

Y12

BH13

G11

H30

H29

G30

H28

J28

M38
M37

H14
J14

VCC1R2A

VCC1R2A

1

2

VCCSA_SENSE_R
VSSSA_SENSE_R

VCCST

VCC1R2A

C252

10U_0603_6.3V6-M

R756 0_0402_5%

R757 0_0402_5%

C4

1U_0402_6.3V6-K

C122

1U_0402_6.3V6-K

VCCST

C177

1U_0402_6.3V6-K

C1

1U_0402_6.3V6-K

1

1 2

2

VCC1R2A

1

1

1

C759

C760

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

@

@

1

C761

C762

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

@

@

C759~C766 close to CPU Side

VDDQC : Memory Control Clock Power

VCCPLL_OC : CPU digital PLL power rails

VCCSTG

R25
100_0402_1%

VCCSA

12

VCCCPUIO

C3

C2

@

1U_0402_6.3V6-K

2

1

1U_0402_6.3V6-K

2

12

R27
100_0402_1%

Resistors close to CPU pins

C763

1 2

@

1

R26
100_0402_1%

2

R28
100_0402_1%

1

2

C764

C765

1

10U_0402_6.3V

10U_0402_6.3V

@

C766

1 2

1 2

10U_0402_6.3V

10U_0402_6.3V

@

@

VCCSA_SENSE 91

VSSSA_SENSE 91

VCCCPUIO_SENSE 95
VSSCPUIO_SENSE 95

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : VCCSA/VCCIO/V DDQ

CPU SKL-H : VCCSA/VCCIO/V DDQ

CPU SKL-H : VCCSA/VCCIO/V DDQ

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet of

1

of

11 111

of

11 111

11 111

A

0.1

0.1

0.1

5

4

3

2

1

D D

C C

B B

U1J

BJ17
BJ19

BJ20
BK17
BK19

BK20

BL16

BL17

BL18

BL19

BL20

BL21
BM17

BN17

BJ23

BJ26

BJ27

BK23

BK26

BK27

BL23

BL24

BL25

BL26

BL27

BL28

BM24

BL15

BM16

BL22
BM22

BP15

BR15

BT15

BP16

BR16

BT16

BN15
BM15

BP17

BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13

AY13

BT29

BR25
BP25

SKYLAKE-H-CPU_BGA1440

SKYLAKE_HALO

VCCOPC_1
VCCOPC_2
VCCOPC_3
VCCOPC_4
VCCOPC_5

VCCOPC_6
VCCOPC_7
VCCOPC_8
VCCOPC_9
VCCOPC_10

VCCOPC_11

VCCOPC_12
VCCOPC_13

VCCOPC_14

RSVD_1
RSVD_2

RSVD_3
RSVD_4

RSVD_5

RSVD_6
RSVD_7

RSVD_8

RSVD_9

RSVD_10

RSVD_11

RSVD_12

RSVD_13

VCCOPC_SENSE

VSSOPC_SENSE

RSVD_14
RSVD_15

VCCEOPIO_1

VCCEOPIO_2

VCCEOPIO_3

RSVD_16

RSVD_17
RSVD_18

VCCEOPIO_SENSE
VSSEOPIO_SENSE

RSVD_19

RSVD_20

VCC_OPC_1P8_1

VCC_OPC_1P8_2

RSVD_21
RSVD_22

ZVM#
MSM#

ZVM2#
MSM2#

OPC_RCOMP

OPCE_RCOM P

OPCE_RCOM P2

BGA1440

10 OF 14

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : VCCOPC/RSVD

CPU SKL-H : VCCOPC/RSVD

CPU SKL-H : VCCOPC/RSVD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet

Date: Sheet

1

12 111

of

12 111

of

12 111

A

0.1

0.1

0.1

5

D D

4

3

2

1

U1K

D1

RSVD_TP_1

E1

RSVD_TP_2

E3

RSVD_TP_3

E2

RSVD_TP_4

BR1

RSVD_TP_5

BT2

RSVD_TP_6

BN35

RSVD_23

J24

RSVD_24

H24

C C

PCH_2_CPU_TRIGGER22
CPU_2_PCH_TRIGGER22

B B

R590

1

2

30_0402_1%

CPU_2_PCH_TRIGGER_R

RSVD_25

BN33

RSVD_26

BL34

RSVD_27

N29

RSVD_28

R14

RSVD_29

AE29

RSVD_30

AA14

RSVD_31

A36

RSVD_32

A37

RSVD_33

H23

PROC_TRIGIN

J23

PROC_TRIGOUT

F30

RSVD_34

E30

RSVD_35

B30

RSVD_36

C30

RSVD_37

G3

RSVD_38

J3

RSVD_39

BR35

RSVD_40

BR31

RSVD_41

BH30

RSVD_42

SKYLAKE-H-CPU_BGA1440

SKYLAKE_HALO

BGA1440

11 OF 14

RSVD_TP_7
RSVD_TP_8

RSVD_TP_9

RSVD_TP_10

RSVD_43

RSVD_44

VSS_447

RSVD_TP_11

RSVD_TP_12

RSVD_TP_13
RSVD_TP_14

RSVD_45

RSVD_46

RSVD_47
RSVD_48

VSS_448

RSVD_TP_15
RSVD_TP_16

RSVD_49

RSVD_50

RSVD_51

NCTF_1
NCTF_2
NCTF_3
NCTF_4

NCTF_5
NCTF_6

BM33
BL33

BJ14

BJ13

BK28

BJ28

BJ18

BJ16

BK16

BK24
BJ24

BK21
BJ21

BT17
BR17

BK18

BJ34
BJ33

G13

AJ8

BL31

B2
B38
BP1
BR2

C1
C38

CPU_NCTF_6

CPU_NCTF_5

1

TP30 Test_Point_22MIL

1

TP31 Test_Point_22MIL

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : RSVD

CPU SKL-H : RSVD

CPU SKL-H : RSVD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

13 111

of

13 111

of

13 111

A

0.1

0.1

0.1

5

4

3

2

1

NEAR--------------

12

TBT_SNK0_DPHPD32,46

D D

C C

SPI_MOSI_IO026,82
SPI_MISO_IO126,82

-SPI_CS026

SPI_CLK26,82

SPI_IO224,26
SPI_IO326

-SPI_CS282

from Docking Connector

DOCKID[3:0]74,77

CS0# for SPI ROM, CS2# for dTPM

DOCKID1
DOCKID0

DOCKID3

DOCKID2

TBT_SNK1_DPHPD32,46

EXT_DP_HPD32,43

BD17

AG15

AG14
AF17
AE17

AR19
AN17

BB29

BE30
BD31

BC31

AW31

BC29
BD30
AT31

AN36

AL39
AN41
AN38
AH43
AG44

D75 RB521CM-30

1

2

D76 RB521CM-30

12

D77 RB521CM-30

U3A

GPP_A11/PM E#

RSVD_1

RSVD_2
RSVD_3
RSVD_4

TP2
TP1

SPI0_MOSI

SPI0_MISO

SPI0_CS0#
SPI0_CLK

SPI0_CS1#

SPI0_IO2
SPI0_IO3
SPI0_CS2#

GPP_D1/SPI1 _CLK
GPP_D0/SPI1 _CS#
GPP_D3/SPI1 _MOSI
GPP_D2/SPI1 _MISO
GPP_D22/SP I1_IO3
GPP_D21/SP I1_IO2

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

1 OF 12

MUX_DP_HPD

1

R830
100K_0402_5%

2

GPP_B13/PLT RST#

GPP_G16/GSXC LK

GPP_G12/GSXD OUT

GPP_G13/GSXSL OAD

GPP_G14/GSXD IN

GPP_G15/GSXSR ESET#

GPP_E3/CPU _GP0
GPP_E7/CPU _GP1
GPP_B3/CPU _GP2
GPP_B4/CPU _GP3

GPP_H18/SM L4ALERT#

GPP_H17/SM L4DATA

GPP_H16/SM L4CLK

GPP_H15/SM L3ALERT#

GPP_H14/SM L3DATA

GPP_H13/SM L3CLK

GPP_H12/SM L2ALERT#

GPP_H11/SM L2DATA

GPP_H10/SM L2CLK

INTRUDER #

1

-PLTRST

BB27

P43
R39
R36
R42

R41

SYSTEM_DISPLAY_HPD MUX_DP_HPD

AF41
AE44
BC23
BD24

-TAMPER_DE T

BC36
BE34
BD39
BB36

BA35
BC35
BD35
AW35

Leave as NC

BD34

BE11

-INTRUDER

IN_A

3

GND

U2
TC7SG17FE_SON5

1

R838 0_0402_5%

1 2

R1001 0_0402_5%

1

R1000 0_0402_5%

1

R785 0_0402_5%

NC

2

VCC

OUT_Y

1

R105 0_0402_5%

2

2

2

U32: Think Engine 2

U27: Embedded Controller

U29: TPM

U24: Express PWR SW

J21: M.2 WLAN

J30: LPC

VCC3M

R29 33_0402_5%

5

4

2

-PLTRST_OUT

1

R30 33_0402_5%

1

-EXC_PWR _SHDN 54

-GPU_IS_3D_AC C_DEVICE 32

GC6_FB_EN 3 2

-GPU_EVENT 32

-DGFX_OUTPUT_ ENABLE 41

2

2

FAR--------------

U21: GbE

U14: Thunderbolt Controller

U23: SD Card Controller

J1: XDP

J17: M.2 SSD

J18: M.2 SSD

1

C6
100P_0402_50V8-J

2

1

C5
100P_0402_50V8-J

2

-PLTRST_FAR 24,46,52,53,56,60 ,62

-PLTRST_NEA R 54,6 1,75,82,83,84

to DP Bus Switch

B B

RTCVCC

3

1

R31
1M_0402_5%

2

2

C7
1000P_0402_50V7-K

1

2015/07/16

2015/07/16

2015/07/16

1

2

D1
RB520CM-30T2R_VMN2M2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

-INTRUDER_E C 77

2

2016/01/16

2016/01/16

2016/01/16

to EC

Title

Title

Title

PCH SKL-H : SPI

PCH SKL-H : SPI

PCH SKL-H : SPI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

14 111

14 111

14 111

0.1

0.1

0.1

-TAMPER_DE T

R1062
0_0402_5%

1 2

-TAMPER_DE T_SW1

4

OPEN

CLOSE

-INTRUDERSWITCH

HIGHCLOSE

DOOR

OPEN LOW (ACTIV E)

A

5

3

4

SW1
SPVR310100_4P

2

1

1

R32 0_0402_5%

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

A

5

4

3

2

1

Flexible I/O Configuration (v0.51)

PCIE 3

PCIE 5

PCIE 6

Net Name

PCIE1_EXP_SLOT

PCIE3_WLAN_SLOT

PCIE4_GBE

PCIE5_L0_TBT

PCIE5_L1_TBT

PCIE5_L2_TBT

PCIE5_L3_TBT

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN3
DMI_RXP3

DMI_TXN3

DMI_TXP3

C8 0.1U_0402_10V7-K
C9 0.1U_0402_10V7-K

C10

C11

C12

C13

C14 0.22U_0201_6.3V6-K

C15 0.22U_0201_6.3V6-K

C16 0.22U_0201_6.3V6-K

C17 0.22U_0201_6.3V6-K

C18 0.22U_0201_6.3V6-K

C19 0.22U_0201_6.3V6-K

C20 0.22U_0201_6.3V6-K

C21 0.22U_0201_6.3V6-K

I/O Hi gh Speed Signals Configuration

Port 1 - 6

D D

Port 7

Port 8

Port 9

Port 10

Port 11

Port 12

Port 13

Port 14

C C

USB3 7 / PCIE 1

USB3 8 / PCIE 2

USB3 9 / PCIE 3

USB3 10 / PCIE 4 (GBE)

PCIE 5 (GBE)

PCIE 6

PCIE 7 PCIE 7

PCIE 8 PCIE 8

Express Card

B B

WLAN Card

GbE

Thunderbolt
x 4

A

Please see Page 19

USB3 7 or PCIE 1

USB3 8

DMI_RXN05
DMI_RXP05
DMI_TXN05

DMI_TXP05
DMI_RXN15
DMI_RXP15

DMI_TXN15

DMI_TXP15
DMI_RXN25
DMI_RXP25
DMI_TXN25

DMI_TXP25
DMI_RXN35
DMI_RXP35
DMI_TXN35

DMI_TXP35

PCIE1_EXP_SLOT_RXN54
PCIE1_EXP_SLOT_RXP54

PCIE1_EXP_SLOT_TXN54
PCIE1_EXP_SLOT_TXP54

PCIE3_WLAN_SLOT_RXN61

PCIE3_WLAN_SLOT_RXP61

PCIE3_WLAN_SLOT_TXN61
PCIE3_WLAN_SLOT_TXP61
PCIE4_GBE_RXN56

PCIE4_GBE_RXP56

PCIE4_GBE_TXN56

PCIE4_GBE_TXP56

PCIE5_L0_TBT_RXN46
PCIE5_L0_TBT_RXP46

PCIE5_L0_TBT_TXN46
PCIE5_L0_TBT_TXP46

PCIE5_L1_TBT_RXN46

PCIE5_L1_TBT_RXP46

PCIE5_L1_TBT_TXN46
PCIE5_L1_TBT_TXP46
PCIE5_L2_TBT_RXN46

PCIE5_L2_TBT_RXP46
PCIE5_L2_TBT_TXN46
PCIE5_L2_TBT_TXP46
PCIE5_L3_TBT_RXN46

PCIE5_L3_TBT_RXP46
PCIE5_L3_TBT_TXN46

PCIE5_L3_TBT_TXP46

GBE

USB2.0 Configuration (v0.51)

USB2 # Assignment

USB2 1

USB2 2

USB2 3

USB2 4

USB2 5

USB2 6

USB2 7

USB2 8

USB2 9

USB2 10

USB2 11

USB2 12

USB2 13

USB2 14

R40

100_0402_1%

1

2

1 2

1

2

0.1U_0402_25V6-K

2

1

0.1U_0402_25V6-K

1

2

0.1U_0402_25V6-K

1

2

0.1U_0402_25V6-K

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

System Port 1 0

System Port 2 1

WWAN

DOCK

System Port 3 2

System Port 4 3

Reserved

Camera

Finger print

Touch panel

Smart Card

Express slot

Color Sensor

WLAN

PCIE_RCOMPN

12

PCIE Configuration (v0.51)

OCx #

PCIE # High Speed Signals

PCIE 1

PCIE 2

PCIE 3

PCIE 4

PCIE 5

PCIE 6

PCIE 7

PCIE 8

PCIE 9 - 20

PCIE_RCOMPP

PCIE1_EXP_SLOT_TXN_C
PCIE1_EXP_SLOT_TXP_C

PCIE3_WLAN_SLOT_TXN_C
PCIE3_WLAN_SLOT_TXP_C

PCIE4_GBE_TXN_C
PCIE4_GBE_TXP_C

PCIE5_L0_TBT_TXN_C
PCIE5_L0_TBT_TXP_C

PCIE5_L1_TBT_TXN_C
PCIE5_L1_TBT_TXP_C

PCIE5_L2_TBT_TXN_C
PCIE5_L2_TBT_TXP_C

PCIE5_L3_TBT_TXN_C

PCIE5_L3_TBT_TXP_C

Express slot 2

GEN

WLAN Card 2

GBE

Thunderbolt 1 3

Thunderbolt 2

Thunderbolt 3

Thunderbolt 4

Please see Page 16

U3B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKYLAKE-H-PCH_FCBGA837

USB3.0 Configuration (v0.51)

USB 3# High Speed Signals

USB3 1 - 6

Please see Page 19

USB3 7

USB3 8

USB3 9

USB3 10

SPT-H_PCH

DMI

USB 2.0

PCIe/USB 3

GPP_E9/USB 2_OC0#

GPP_E10/US B2_OC1#
GPP_E11/US B2_OC2#
GPP_E12/US B2_OC3#

GPP_F15/US B2_OCB_4

GPP_F16/US B2_OCB_5
GPP_F17/US B2_OCB_6
GPP_F18/US B2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

GPD7/RSVD

2 OF 12

USB2N_1
USB2P_1
USB2N_2

USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7

USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9

USB2N_10

USB2P_10

USB2N_11

USB2P_11

USB2N_12

USB2P_12

USB2N_13

USB2P_13

USB2N_14

USB2P_14

USB2_ID

VCC3_SUS

AF5
AG7

AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3

AB2

AL8

AL7
AA1
AA2
AJ8

AJ7

W2
W3
AD3
AD2

V2
V1

AJ11
AJ13

AD43

AD42
AD39
AC44
Y43

Y41

PLANARID2

W44
W43

USB2_COMP

AG3

AD10
AB13

Leave RSVD_AB13 NC

AG2

BD14

2

2

1

1 2

1

R34 10K_0402_5%

R35 10K_0402_5%

R33 10K_0402_5%

1 2

R36 10K_0402_5%

2

R845
1K_0402_1%

1

2

1

R38 10K_0402_5%

1 2

2

1

R39 10K_0402_5%

R41

1

113_0402_1%

R864
1K_0402_5%

USBP1-_SYSP1 54
USBP1+_SYSP1 54

USBP2-_SYSP2 54

USBP2+_SYSP2 54
USBP3-_WWAN 61
USBP3+_WWAN 61
USBP4-_DOCK 74

USBP4+_DOCK 74

USBP5-_SYSP3 54

USBP5+_SYSP3 54
USBP6-_SYSP4 54
USBP6+_SYSP4 54

USBP8-_CAMERA 40
USBP8+_CAMERA 40
USBP9-_FINGER_PRINT 54
USBP9+_FINGER_PRINT 54

USBP10-_TOUCH 42
USBP10+_TOUCH 42
USBP11-_SMART_CARD 64
USBP11+_SMART_CARD 64
USBP12-_EXP_SLOT 54
USBP12+_EXP_SLOT 54
USBP13-_COLOR_SENSOR 40

USBP13+_COLOR_SENSOR 40
USBP14-_WLAN 61
USBP14+_WLAN 61

-USB_PORT0_OC 0 54

-USB_PORT1_OC 1 54

-USB_PORT2_OC 2 54

-USB_PORT3_OC 3 54

PLANARID3 18

PLANARID2 18

2

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : DMI/PCIE/USB

PCH SKL-H : DMI/PCIE/USB

PCH SKL-H : DMI/PCIE/USB

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet of

1

15 111

15 111

15 111

of

of

0.1

0.1

0.1

5

D D

from / to WLAN

C C

PCIE9L2_MD2_SSD1_TXP60
PCIE9L2_MD2_SSD1_TXN60

M.2 SSD1 L2

Media Card

M.2 SSD1 L3

M.2 SSD2 L3

B B

M.2 SSD2 L2

PCIE9L2_MD2_SSD1_RXP60
PCIE9L2_MD2_SSD1_RXN60

PCIE13_MEDIACARD_TXN62
PCIE13_MEDIACARD_TXP62

PCIE13_MEDIACARD_RXN62
PCIE13_MEDIACARD_RXP62

PCIE9L3_MD2_SSD1_TXP60
PCIE9L3_MD2_SSD1_TXN60

PCIE9L3_MD2_SSD1_RXP60

PCIE9L3_MD2_SSD1_RXN60

PCIE17L3_MD2_SSD2_TXP60

PCIE17L3_MD2_SSD2_TXN60

PCIE17L3_MD2_SSD2_RXP60
PCIE17L3_MD2_SSD2_RXN60

PCIE17L2_MD2_SSD2_TXP60

PCIE17L2_MD2_SSD2_TXN60
PCIE17L2_MD2_SSD2_RXP60
PCIE17L2_MD2_SSD2_RXN60

CL_CLK_WLAN61
CL_DATA_WLAN61

-CL_RST_W LAN61

1 2

C28 0.22U_0201_6.3V6-K

1 2

C30 0.22U_0201_6.3V6-K

WWAN_CFG261

WWAN_CFG361
PLANARID118

PLANARID018

12

C37 0.1U_0402_10V7-K

12

C36 0.1U_0402_10V7-K

1

2

C38 0.22U_0201_6.3V6-K

1 2

C39 0.22U_0201_6.3V6-K

2

1

C40 0.22U_0201_6.3V6-K

1

2

C41 0.22U_0201_6.3V6-K

1

2

C42 0.22U_0201_6.3V6-K

2

1

C43 0.22U_0201_6.3V6-K

4

VCC3_SUS

1

R42
10K_0402_5%

@

2

PCIE9L2_MD2_SSD1_TXP_C
PCIE9L2_MD2_SSD1_TXN_C

PCIE13_MEDIACARD_TXN_C
PCIE13_MEDIACARD_TXP_C

PCIE9L3_MD2_SSD1_TXP_C
PCIE9L3_MD2_SSD1_TXN_C

PCIE17L3_MD2_SSD2_TXP_C
PCIE17L3_MD2_SSD2_TXN_C

PCIE17L2_MD2_SSD2_TXP_C

PCIE17L2_MD2_SSD2_TXN_C

3

PCIE / SATA Configuration (v0.51)

I / O High Speed Signals GEN

Port 15

SATA 0A / PCIE 9

Port 16

SATA 1A / PCIE 10
Port 17

Port 18

Port 19

Port 20

Port 21

Port 22

Port 23

Port 24

Port 25

Port 26

AV2
AV3

AW2

R44
R43
U39
N42

U43
U42
U41

M44

U36
P44
T45
T44

B33
C33
K31

L31

AB33
AB35
AA44
AA45

B38

C38
D39
E37

C36
B36

G35

E35

A35
B35
H33

G33

K44
N38
N39
H44
H43
L39
L37

/ PCIE 11

/ PCIE 12

SATA 0B / PCIE 13

SATA 1B / PCIE 14

SATA 2 / PCIE 15

SATA 3 / PCIE 16

SATA 4 / PCIE 17

SATA 5 / PCIE 18

/ PCIE 19

/ PCIE 20

U3C

CL_CLK
CL_DATA
CL_RST#

GPP_G8/FAN_ PWM_0
GPP_G9/FAN_ PWM_1
GPP_G10/FAN _PWM_2
GPP_G11/FAN _PWM_3

GPP_G0/FAN_ TACH_0
GPP_G1/FAN_ TACH_1
GPP_G2/FAN_ TACH_2
GPP_G3/FAN_ TACH_3
GPP_G4/FAN_ TACH_4

GPP_G5/FAN_ TACH_5
GPP_G6/FAN_ TACH_6
GPP_G7/FAN_ TACH_7

PCIE11_TXP
PCIE11_TXN
PCIE11_RXP

PCIE11_RXN

GPP_F10/SC LOCK
GPP_F11/SLOA D
GPP_F13/SD ATAOUT0
GPP_F12/SD ATAOUT1

PCIE14_TXN/SATA1B_TXN
PCIE14_TXP/SATA1B_TXP

PCIE14_RXN/SATA1B_RXN
PCIE14_RXP/SATA1B_RXP

PCIE13_TXN/SATA0B_TXN
PCIE13_TXP/SATA0B_TXP
PCIE13_RXN/SATA0B_RXN

PCIE13_RXP/SATA0B_RXP

PCIE12_TXP
PCIE12_TXN
PCIE12_RXP
PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP
PCIE20_TXN/SATA7_TXN

PCIE20_RXP/SATA7_RXP
PCIE20_RXN/SATA7_RXN
PCIE19_TXP/SATA6_TXP
PCIE19_TXN/SATA6_TXN
PCIE19_RXP/SATA6_RXP
PCIE19_RXN/SATA6_RXN

SKYLAKE-H-PCH_FCBGA837

CLINK

Configuration
M.2 SSD1 (L0) / SATA0A 3/3

M.2 SSD1 (L1)

M.2 SSD1 (L2)

M.2 SSD1 (L3)
Media Card 2
Reserved ---

SATA HDD BAY 3

SATA ODD BAY 3

M.2 SSD2 (L0) / SATA4 3
M.2 SSD2 (L1)

M.2 SSD2 (L2)

M.2 SSD2 (L3)

SPT-H_PCH

PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN
PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP

FAN

3 OF 12

PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E0/SAT AXPCIE0/SATAGP0
GPP_E1/SAT AXPCIE1/SATAGP1

GPP_E2/SAT AXPCIE2/SATAGP2

GPP_F0/SAT AXPCIE3/SATAGP3

GPP_F1/SAT AXPCIE4/SATAGP4

GPP_F2/SAT AXPCIE5/SATAGP5
GPP_F3/SAT AXPCIE6/SATAGP6

GPP_F4/SAT AXPCIE7/SATAGP7

GPP_F21/ED P_BKLTCTL

GPP_F20/ED P_BKLTEN

GPP_F19/ED P_VDDEN

HOST

GPP_E8/SAT ALED#

THERMTRIP#

PECI

PM_SYNC

PLTRST_PROC#

PM_DOWN

G31
H31

PCIE9L0_SATA0A_MD2_SSD1_TXN_C

C31

PCIE9L0_SATA0A_MD2_SSD1_TXP_C

B31

G29

E29

PCIE9L1_MD2_SSD1_TXN_C

C32

PCIE9L1_MD2_SSD1_TXP_C

B32

F41
E41

SATA2_TXN_C

B39

SATA2_TXP_C

A39

D43
E42

SATA3_TXN_C

A41

SATA3_TXP_C

A40

H42

H40

PCIE17L0_SATA4_MD2_SSD2_TXN_C

E45

PCIE17L0_SATA4_MD2_SSD2_TXP_C

F45

K37
G37

PCIE17L1_MD2_SSD2_TXN_C

G45

PCIE17L1_MD2_SSD2_TXP_C

G44

AD44

-PCIE_DETEC T_SSD1

AG36
AG35

AG39

AD35

-PCIE_DETEC T_SSD2

AD31
AD38

-MIC_HW_E N

AC43

AB44

W36
W35
W42

AJ3
AL3
AJ4
AK2
AH2

12

1

R51

R52

2

10K_0402_5%

@

@

10K_0402_5%

12

2

1

R53

0_0402_5%

2

R159

100K_0402_5%

1

2

1

1 2

1

1

1

1 2

2

R285

100K_0402_5%

1

1 2

1 2

1

1 2

1

R48

2

2

2

2

VCC3_SUS

2

C220.22U_0201_6.3V6-K

C230.22U_0201_6.3V6-K

C240.22U_0201_6.3V6-K
C250.22U_0201_6.3V6-K

C260.01U_0201_6.3V7-K

C270.01U_0201_6.3V7-K

C290.01U_0201_6.3V7-K

C310.01U_0201_6.3V7-K

C320.22U_0201_6.3V6-K

2

C330.22U_0201_6.3V6-K

C340.22U_0201_6.3V6-K

2

C350.22U_0201_6.3V6-K

1

604_0402_1%

VCCST

R45

R471K_0402_5%

R46

R43

12

12

1

2

2

10K_0402_5%

10K_0402_5%

10K_0402_5% 1

R49 30_0402_1%

R50 20_0402_1%

VCC3B

1

VCC3B

R768
10K_0402_5%

1 2

PCIE9L0_SATA0A_MD2_SSD1_RXN 60
PCIE9L0_SATA0A_MD2_SSD1_RXP 60

PCIE9L0_SATA0A_MD2_SSD1_TXN 60

PCIE9L0_SATA0A_MD2_SSD1_TXP 60

PCIE9L1_MD2_SSD1_RXN 60
PCIE9L1_MD2_SSD1_RXP 60
PCIE9L1_MD2_SSD1_TXN 60
PCIE9L1_MD2_SSD1_TXP 60

SATA2_HDDBAY_RXN 65

SATA2_HDDBAY_RXP 65

SATA2_HDDBAY_TXN 65

SATA2_HDDBAY_TXP 65

SATA3_ODDBAY_RXN 66

SATA3_ODDBAY_RXP 66

SATA3_ODDBAY_TXN 66

SATA3_ODDBAY_TXP 66

PCIE17L0_SATA4_MD2_SSD2_RXN 60
PCIE17L0_SATA4_MD2_SSD2_RXP 60

PCIE17L0_SATA4_MD2_SSD2_TXN 60
PCIE17L0_SATA4_MD2_SSD2_TXP 60

PCIE17L1_MD2_SSD2_RXN 60
PCIE17L1_MD2_SSD2_RXP 60
PCIE17L1_MD2_SSD2_TXN 60
PCIE17L1_MD2_SSD2_TXP 60

-SATALED

-PCIE_DETEC T_SSD1 60

BAY_ADAPTER_DTCT_ANALOG_PCH 60

-PCIE_DETEC T_SSD2 60

-WWAN _RESET 61

PANEL_BKLT_CTRL_I 41
VGA_BLON_I 41

PANEL_POWER_ON_I 41

12

12

-PCIE_DETEC T_SSD1

-PCIE_DETEC T_SSD2

R850 10K_0402_5%

R851 10K_0402_5%

To eDP

-THERMTRIP 7

PECI 7,76

PM_SYNC 7

-PCH_PLTRS T_PROC 7
PM_DOWN 7

2

1

1 2

M.2 SSD1
L0

M.2 SSD1
L1

HDDBAY

ODDBAY

M.2 SSD2
L0

M.2 SSD2
L1

VCC3_SUS

12

R818
100K_0402_5%

-SATALED_CON N 40

-SATALED60

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

-SATALED

G

2

S

2016/01/16

2016/01/16

2016/01/16

Q59
LSK3541G1ET2L_VMT3

3

Title

Title

Title

PCH SKL-H : SATA/PCIE

PCH SKL-H : SATA/PCIE

PCH SKL-H : SATA/PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1

D

2

1

D

2

G

Q60
LSK3541G1ET2L_VMT3

S

3

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

A

0.1

0.1

0.1

of

16 111

of

16 111

of

1

16 111

5

4

3

2

1

TABLE : Functional Strap

GPP_C5/SML0ALERT# (LPC or eSPI)

TABLE : Functional Strap

HDA_SDO

Flash Descriptor Security Override

HIGH

D D

HDA_SDO is used to update the Descriptor and/or the
ME regions of the SPI after MFG Done bit is set.

C C

PROC_AUDIO_SDO_CPU6

PROC_AUDIO_SDI_CPU6

PROC_AUDIO_CLK_CPU6

From RTC Reset circuits

From CPU DCDC

From ASIC

From/to DIMM and TP

From/to GBE

B B

A

From/to EC

2

R560

1

4.7K_0402_5%

Pullups on SMB are located in SMBUS Switch page.

Disable Flash Descriptor Security (Override)

LOW

Enable Flash Descriptor Security (Default)

EMC Part

1 2

C44

@

HDA_BCLK67

-HDA_RST67
HDA_SDIN067

HDA_SDO67
HDA_SYNC67

From ASIC

2

R559

4.7K_0402_5%

1

2

2.2K_0402_5%

1

5

47P_0402_50V8-J

VCC3_SUS

R67

2.2K_0402_5%

R57 33_0402_5%

R58 33_0402_5%

R59 33_0402_5%

R60 33_0402_5%

PROC_AUDIO_SDO_CPU PROC_AUDIO_SDO_PCH
PROC_AUDIO_SDI_CPU
PROC_AUDIO_CLK_CPU

-RTCRST25

-SRTCRST25

CPUCORE_PWRGD102,24,91

-RSMRST24,76

MPWRG76,85

SMB_CLK83
SMB_DATA83

SML0_CLK56
SML0_DATA56

EC_SCL276

EC_SDA276

2

2

R68

R69

1

1

2.2K_0402_5%

1 2

1 2

1

1

1

R70

499_0402_1%

2

2

2

VCC3_SUS

R61

R62

PLACE NEAR PCH

R65 0_0402_5%

R66 0_0402_5%

12

499_0402_1%

1

1

R71

2

12

1

2

2

SMB_CLK
SMB_DATA

SML0_CLK
SML0_DATA

EC_SCL2
EC_SDA2

VCC3_SUS

SML0_CLK

SML0_DATA

SMB_CLK

SMB_DATA

-SMB_ALERT

EC_SCL2

EC_SDA2

1

R56

2

Leave RSVD_BD1/BE2 NC

30_0402_1%

30_0402_1%

To enable DCI function

1K_0402_5%

HDA_BCLK_R

-HDA_RST_R
HDA_SDIN0

HDA_SDO_R
HDA_SYNC_R

PROC_AUDIO_CLK_PCH

-SMB_ALERT

PCHHOT#

DCI@

R819

2

150K_0402_5%

4

VCC3_SUS

1

PLACE ON BOTTOM SIDE

R54

1

2

1K_0402_5%

TP5

1

Test_Point_20MIL

TEST PAD
BOTTOM SIDE
DO NOT MOVE AF TER FIX

U3D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_ SCLK

AN42

GPP_D7/I2S0_ RXD

AM43

GPP_D6/I2S0_ TXD

AJ33

GPP_D5/I2S0_ SFRM

AH44

GPP_D20/DM IC_DATA0

AJ35

GPP_D19/DM IC_CLK0

AJ38

GPP_D18/DM IC_DATA1

AJ42

GPP_D17/DM IC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMB ALERT#

AW44

GPP_C0/SMB CLK

BB43

GPP_C1/SMB DATA

BA40

GPP_C5/SML 0ALERT#

AY44

GPP_C3/SML 0CLK

BB39

GPP_C4/SML 0DATA

AT27

GPP_B23/SM L1ALERT#/PCHH OT#

AW42

GPP_C6/SML 1CLK

AW45

GPP_C7/SML 1DATA

SKYLAKE-H-PCH_FCBGA837

PCHHOT#

R55

@

1

2

0_0402_5%

TP6

1

Test_Point_20MIL

TABLE : Functional Strap

SPT-H_PCH

GPP_A12/BM BUSY#/ISH_GP6/SX_EX IT_HOLDOFF#

AUDIO

GPP_A13/SU SWARN#/SUSP WRDNACK

SMBUS

JTAG

4 OF 12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

eSPI is selected

HIGH

LOW

LPC is selected(Default)

GPP_C2/SMBALERT# (TLS Confidentiality)

Enable ME Crypto TLS with Confidentiality

HIGH

LOW

Disable ME Crypto TLS (Default)

BB17

GPP_A8/CLK RUN#

GPD11/LANP HYPC

GPD9/SLP_W LAN#

DRAM_RESET#

GPP_B2/VRA LERT#

GPP_G17/ADR _COMPLETE

SYS_PWROK

GPD6/SLP_A #

GPP_B12/SLP _S0#

GPD4/SLP_S 3#
GPD5/SLP_S 4#

GPD10/SLP_S 5#

GPD8/SUSC LK

GPD0/BATLOW #

GPP_A15/SU SACK#

GPD2/LAN_W AKE#

GPD1/ACPR ESENT

GPD3/PWR BTN#

SYS_RESET#

GPP_B14/SPK R

PROCPWRGD

2015/07/16

2015/07/16

2015/07/16

AW22

AR15

AV13

BC14

BD23
AL27

GPP_B1

AR27

GPP_B0

N44

AN24

GPP_B11

AY1

BC13

WAKE#

BC15

AV15

SLP_LAN#

BC26
AW15
BD15
BA13

AN15
BD13
BB19

-SUSACK

BD19

-SUSWAR N

BD11
BB15
BB13

SLP_SUS#

AT13
AW1
BD26

PROCPWRGD_PCH

AM3

AT2

ITP_PMODE

AR3

JTAGX

AR2

JTAG_TMS

AP1

JTAG_TDO

AP2

JTAG_TDI

AN3

JTAG_TCK

R820

@

51_0402_1%

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1 2

1

1

R63 0_0402_5%

1

R64 0_0402_5%

R72 0_0402_5%

1

TP59 Test_Point_32MIL

2

R821

@

51_0402_1%

2

@

51_0402_1%

1

VCC1R2A

R822

1

R73

2

2016/01/16

2016/01/16

2016/01/16

<------LOGIC

<------LOGIC

-CLKRUN

-DRAMRST

2

-PCIE_WAK E

-PCH_SLP_LA N

2

-LANWAKE

1 2

VCC1R0_SUS

TABLE : Functional Strap

VCC3B

2

R74

1

8.2K_0402_5%

470_0402_5%

-CLKRUN 75,83

LANPHYPC 56

-PCH_SLP_W LAN 76

-DRAMRST 27,28,29,30

BPWRG 24,76,83,85

-PCIE_WAK E 46,54,61,84

-PCH_SLP_M 84

-PCH_SLP_LA N 77

-PCH_SLP_S0 104,95

-PCH_SLP_S3 46,76,84 ,95

-PCH_SLP_S4 76,84

-PCH_SLP_S5 84

SUSCLK_32K 61,75

-BATLOW 46,7 7

from LPC Device(EC)
to GBE

to M.2 WLAN

to DIMM/SMBU SW

SKL-H PCH doesn't
require CORE VID

to PHY PLL power FET
from ASIC

from M.2 WLAN Slot

to ASIC
to ASIC

to EC/FPR/ASIC/DebugPort
to EC/ASIC/DebugPort
to ASIC

to EC/ASIC/WLAN
from ASIC

Pull-up on –LANWAKE is placed on GbE page

-LANWAKE 56
AC_PRESENT 76

-PCH_SLP_SU S 76

-PWRSW _EC 76

-XDP_DBR 24

PCH_SPKR 72

PROCPWRGD_CPU 7

JTAGX 24

PCH_TMS 24

PCH_TDO 24

PCH_TDI 24

PCH_TCK 24

from GBE
from ASIC
to EC
from EC
from XDP port
to Audio Mixer

to/from debug port

GPP_B14/SPKR (Top Swap Override)

Enable "Top Swap" Mode

HIGH

LOW

Disable "Top S wap" Mode (Default by intern al PD)

VCC3M

1

R75

@

2

12

R76

10K_0402_5%

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

10K_0402_5%

-PCIE_WAK E

-PCH_SLP_LA N

-CLKRUN

-DRAMRST

Title

Title

Title

PCH SKL-H : AUDIO/SMBUS/JTAG

PCH SKL-H : AUDIO/SMBUS/JTAG

PCH SKL-H : AUDIO/SMBUS/JTAG

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

17 111

17 111

1

17 111

0.1

0.1

0.1

of

A

5

D D

DDP[B:D]_HPD[0:2]
PAYTON: NC
WALTER:
N16P QUADRO = NC
N16S GEFORCE = CONNECT FROM DISPLAYS

C C

EDP_HPD_I41

4

U3E

AW4

GPP_I0/DDPB _HPD0

AY2

GPP_I1/DDPC _HPD1

AV4

GPP_I2/DDPD _HPD2

BA4

GPP_I3/DDPE _HPD3

BD7

GPP_I4/EDP_ HPD

SKYLAKE-H-PCH_FCBGA837

3

SPT-H_PCH

5 OF 12

GPP_I7/DDPC _CTRLCLK

GPP_I8/DDPC _CTRLDATA

GPP_I5/DDPB _CTRLCLK

GPP_I6/DDPB _CTRLDATA

GPP_I9/DDPD _CTRLCLK

GPP_I10/DDP D_CTRLDATA

GPP_F14
GPP_F23
GPP_F22

GPP_G23
GPP_G22
GPP_G21
GPP_G20

GPP_H23

GPP_H23
PAYTON: NC
WALTER: -DGFX_WITH_DISPLAYOUT(INPUT)
N16P QUADRO = LOW
N16S GEFORCE = HIGH

2

DDP[B:C]_CTRLCLK/DATA
PAYTON: NC
WALTER:
N16P QUADRO = NC
N16S GEFORCE = CONNECT FROM DISPLAYS

VCC3B

BB3
BD6
BA5
BC4

BE5
BE6

Y44
V44
W39

L43
L44
U35

R35
BD36

-SC_DTCT

-GPU_RST_PCH _U

12

@

R1016
10K_0402_5%

-SC_DTCT 64

SmartCard

MXM_ON_PCH 32

-PLTRST_FAR14,24,46,52,53,60,62

VCC3B

1

@

R1017
10K_0402_5%

2

1

2

U38
74LVC1G08GW_SOT353-1-5

B

VCC

A

GND3Y

5

4

1

VCC3B

-GPU_RST_PCH 31

TABLE

PLANAR ID

3210

R81R37R79

1

B B

TABLE

PLANARID3

12

R79
0_0402_5%

PLANARID2

1

@

R37
0_0402_5%

2

PLANARID1

1

R81
0_0402_5%

2

PLANARID0

1

R82
0_0402_5%

2

PLANARID0 16
PLANARID1 16

PLANARID2 15
PLANARID3 15

NA

0ASMASM

LEVEL PLANARID[3..0]

4+2 SDV

0001b

0010b4+2 FVT

4+2 SIT

4+2 SVT

0011b

0100b

4+2 SOVP

Reserved

Reserved

A

Reserved 1010b

1000b

1001b

R82

NANANA

ASMASM

CPU PCH

ES () ES ()

ES () ES ()

QS () QS ()

QS () QS ()

Prod

Prod0101b

Reserved 1011b

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : DDI CONTROL

PCH SKL-H : DDI CONTROL

PCH SKL-H : DDI CONTROL

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet

1

18 111

18 111

18 111

of

0.1

0.1

0.1

A

5

4

3

2

1

Flexible I/O Configuration (v0.51)

USB3P1_SYSP1_TXN54

USB3P1_SYSP1_TXP54
USB3P1_SYSP1_RXN54
USB3P1_SYSP1_RXP54

USB3P2_SYSP2_TXN54

USB3P2_SYSP2_TXP54

USB3P2_SYSP2_RXN54
USB3P2_SYSP2_RXP54

USB3P6_SYSP4_TXN54

USB3P6_SYSP4_TXP54
USB3P6_SYSP4_RXN54
USB3P6_SYSP4_RXP54

USB3P5_SYSP3_TXN54

USB3P5_SYSP3_TXP54
USB3P5_SYSP3_RXN54

USB3P5_SYSP3_RXP54

USB3P4_DOCK_TXP74

USB3P4_DOCK_TXN74

USB3P4_DOCK_RXP74

USB3P4_DOCK_RXN74

Net Name

USB3P1_SYSP1

USB3P2_SYSP2

USB3P3_WWAN

USB3P4_DOCK

USB3P5_SYSP3

USB3P6_SYSP4

U3F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKYLAKE-H-PCH_FCBGA837

VCC3_SUS

R83

1 2

10K_0402_5%

SPT-H_PCH

LPC/eSPI

USB

SATA

6 OF 12

GPP_A1/LAD 0/ESPI_IO0
GPP_A2/LAD 1/ESPI_IO1
GPP_A3/LAD 2/ESPI_IO2
GPP_A4/LAD 3/ESPI_IO3

GPP_A5/LFR AME#/ESPI_CS0#

GPP_A6/SER IRQ/ESPI_CS1#

GPP_A7/PIRQA #/ESPI_ALERT0#

GPP_A0/RCIN #/ESPI_ALERT1#

GPP_A14/SU S_STAT#/ESPI_RE SET#

GPP_A9/CLK OUT_LPC0/ESPI_CL K

GPP_A10/CLK OUT_LPC1

GPP_G19/SMI#

GPP_G18/NMI#

GPP_E6/DEV SLP2
GPP_E5/DEV SLP1
GPP_E4/DEV SLP0
GPP_F9/DEV SLP7
GPP_F8/DEV SLP6
GPP_F7/DEV SLP5

GPP_F6/DEV SLP4

GPP_F5/DEV SLP3

AT22
AV22
AT19
BD16

BE16
BA17
AW17

AT17
BC18

BC17

AV19

M45

N43

AE45
AG43
AG42
AB39
AB36

AB43

AB42

AB41

LPC_AD0

LPC_AD1
LPC_AD2
LPC_AD3

1 2

R84 22_0402_5%

1

R85 22_0402_5%

VCC3B

2

R562

8.2K_0402_5%

1

LPC_AD0 75,83
LPC_AD1 75,83
LPC_AD2 75,83

LPC_AD3 75,83

-LPC_FRAME 75,83
IRQSER 75,8 3

-TPM_IRQ 82

-KBRC 75

-SUS_STAT 75,83

2

LPCCLK_EC_24M 75
LPCCLK_DEBUG_24M 83

-BAY_MEDIA_EJEC T_PCH 66

DEVSLP0_MD2_SSD1 60

WWAN_CFG1 61

WWAN_CFG0 61

-INT_MIC_DTC T 40
DEVSLP4_MD2_SSD2 60

SSD in M.2 Slot 1

SSD in M.2 Slot 2

I/O Hi gh Speed Signals Configuration

Port 1

D D

USB3 1 Capable o f OTG USB3

USB2 3 / SSIC 1

Port 2

Port 3

USB3 3 / SSIC 2

Port 4

USB3 4

Port 5

USB3 5

Port 6

USB3 6

USB3

USB3 or SSIC

USB3

USB3

USB3

System Port 1

C C

System Port 2

System Port 4

System Port 3

DOCK

B B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : USB3/LPC

PCH SKL-H : USB3/LPC

PCH SKL-H : USB3/LPC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

19 111

of

19 111

of

19 111

0.1Custom

0.1Custom

0.1Custom

A

5

D D

4

3

2

1

R86 Need change to 2.71K_0.5%

U3G

AR17

GPP_A16/CLK OUT_48

CPU_REFCLK_24M7

-CPU_REFCL K_24M7

CPU_BCLK_100M7

-CPU_BCLK_ 100M7

-CLKREQ_PCIE0 _UHS262

-CLKREQ_PCIE2 _WLAN61

C C

B B

-CLKREQ_PCIE3 _GBE56

-CLKREQ_PCIE4 _MD2_SSD160

-CLKREQ_PEG31

-CLKREQ_PCIE6 _EXPCARD54

-CLKREQ_PCIE7 _MD2_SSD260

-CLKREQ_PCIE8 _TBT46

R867 100K_0402_5%

External Pull on CLKREQ# should be placed in device page,
as power railis may be different from PCH-H..

1

2

C46 6.8P_0402_50V8-D

32.768KHZ_9PF_9H03280012

2

1

C47 6.8P_0402_50V8-D

VCC1R0_SUS

1 2

Y1

TXC

9H03280012

KDS

1TJF090DJ1A000B

XTAL24_OUT

R86

1

2

2.7K_0402_0.5%

RTCX1

1

R87
10M_0402_5%

1 2

2

RTCX2

XTAL24_IN

XCLK_BIASREF

RTCX1
RTCX2

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRC CLKREQ0#

AW24

GPP_B6/SRC CLKREQ1#

AT24

GPP_B7/SRC CLKREQ2#

BD25

GPP_B8/SRC CLKREQ3#

BB24

GPP_B9/SRC CLKREQ4#

BE25

GPP_B10/SR CCLKREQ5#

AT33

GPP_H0/SRC CLKREQ6#

AR31

GPP_H1/SRC CLKREQ7#

BD32

GPP_H2/SRC CLKREQ8#

BC32

GPP_H3/SRC CLKREQ9#

BB31

GPP_H4/SRC CLKREQ10#

BC33

GPP_H5/SRC CLKREQ11#

BA33

GPP_H6/SRC CLKREQ12#

AW33

GPP_H7/SRC CLKREQ13#

BB33

GPP_H8/SRC CLKREQ14#

BD33

GPP_H9/SRC CLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKYLAKE-H-PCH_FCBGA837

PCIE Clock Assignment
Clock 0 : UHS II
Clock 1 : NA

SPT-H_PCH

7 OF 12

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3

CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6

CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9

CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

L1
L2

J1

J2

N7
N8

L7
L5

D3
F2

E5

G4

D5
E6

D8
D7

R8

R7

U5
U7

W10
W11

N3
N2

P3
P2

R3
R4

-CPU_PCI_BC LK_100M 7

CPU_PCI_BCLK_100M 7

-PCIE0_CLK_10 0M_UHS2 62

PCIE0_CLK_100M_UHS2 62

-PCIE2_CLK_10 0M_WLAN 61

PCIE2_CLK_100M_WLAN 61

-PCIE3_CLK_10 0M_GBE 56

PCIE3_CLK_100M_GBE 56

-PCIE4_CLK_10 0M_MD2_SSD1 60

PCIE4_CLK_100M_MD2_SSD1 60

-PEG_CLK_100M 31

PEG_CLK_100M 31

-PCIE6_CLK_10 0M_EXPCARD 54

PCIE6_CLK_100M_EXPCARD 54

-PCIE7_CLK_10 0M_MD2_SSD2 60

PCIE7_CLK_100M_MD2_SSD2 60

-PCIE8_CLK_10 0M_TBT 46

PCIE8_CLK_100M_TBT 46

Clock 2 : Wireless LAN M.2 Slot

1 2

C48 22P_0402_50V8-J

24MHZ_18PF_8Y24000033

1 2

C49 27P_0402_50V8-J

TXC
KDS

A

XTAL24_OUT_R

Y2

3

4

2

1

XTAL24_IN_R

8Y24000033
1ZZHAE24000CC0F

1

R1067 0_0201_5%

2

R88
1M_0402_5%

1

R1066 0_0201_5%

2

1

2

XTAL24_OUT

XTAL24_IN

Clock 3 : Giga Bit Ethernet
Clock 4 : PCIe SSD on M.2 Slot
Clock 5 : Discrete GFX(MXM or Onboard)
Clock 6 : Express Slot
Clock 7 : PCIe SSD on M.2 Slot
Clock 8 : Thunderbolt
Clock 9 - 15 : NA

A

Title

Title

Title

Title

Title

Security Classification

Security Classification

Security Classification

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : CLK

PCH SKL-H : CLK

PCH SKL-H : CLK

PCH SKL-H : CLK

PCH SKL-H : CLK

PCH SKL-H : CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet of

Date: Sheet of

Date: Sheet of

Date: Sheet

Date: Sheet

1

of

20 111

20 111

20 111

20

of

20

of

20

0.1

0.1

0.1

0.1

0.1

0.1

5

D D

4

3

2

1

1

C658

0.1U_0402_16V7-K

2

NEAR
BA31

0.1U_0402_25V6-K

NEAR
BA26

VCCHDAPLL_1P0

2

@

1

C69

2

22U_0805_6.3V6-M

NEAR PCH PKG

1

C62

2

0.1U_0402_25V6-K

0.033A

VCC1R0_SUS

@

1

C723

2

VCC1R0_SUS

0.195A

VCC3M

0.029A

VCC3_SUS

R92

1

0_0603_5%

3.137A

1.0V

VCC1R0_SUS

@

@

1

22U_0805_6.3V6-M

VCCMPHYPLL_1P0

VCCAPLLEBB_1P0

VCCUSB2PLL_1P0

VCCHDAPLL_1P0

VCC3_SUS

@

1

C65

2

22U_0805_6.3V6-M

2

VCC3M

22U_0805_6.3V6-M

C50

4.110A

1.0V

C C

B B

VCC1R0_SUS

1

1

1

C61

C60

C758

2

22U_0603_6.3V6M

2

2

1U_0402_6.3V6-K

10U_0603_6.3V6-M

NEAR PCH PKG

0.11A 0.012A

1.0V

VCC1R0_SUS

R89

1

2

0_0603_5%

NEAR PCH PIN

@

1

2

22U_0805_6.3V6-M

@

1

2

1U_0402_6.3V6-K

VCCMPHYPLL_1P0

@

1

C66

2

1U_0402_6.3V6-K

1

C52

C51

C64

1

2

NEAR

2

K2

1U_0402_6.3V6-K

1

C59

2

1U_0402_6.3V6-K

NEAR
BA29

NEAR
W15

0.03A

1.0V

VCC1R0_SUS

1

0_0603_5%

C67

AA23
AA26
AA28
AC23
AC26

AC28
AE23

AE26

Y23

Y25

BA29

N17
R19

U20
V17
R17

K2

K3

U21
U23
U25
U26
V26
A43

B43

C44

C45

V28

AC17

AJ5
AL5

AN19
BA15

W15

R90

2

U3H

VCCPRIM_1P0_1
VCCPRIM_1P0_2
VCCPRIM_1P0_3
VCCPRIM_1P0_4
VCCPRIM_1P0_5

VCCPRIM_1P0_6
VCCPRIM_1P0_7
VCCPRIM_1P0_8

VCCPRIM_1P0_9

VCCPRIM_1P0_10

DCPDSW_1P0

VCCCLK1_1
VCCCLK3_2

VCCCLK4_3
VCCCLK2_4
VCCCLK2_5

VCCCLK5_6

VCCCLK5_7

VCCMPHY_1P0_1
VCCMPHY_1P0_2
VCCMPHY_1P0_3
VCCMPHY_1P0_4
VCCMPHY_1P0_5
VCCMPHYPLL_1P0_1

VCCMPHYPLL_1P0_2

VCCPCIE3PLL_1P0_1

VCCPCIE3PLL_1P0_2

VCCAPLLEBB_1P0
VCCPRIM_1P0_16
VCCUSB2PLL_1P0_1
VCCUSB2PLL_1P0_2

VCCHDAPLL_1P0
VCCHDA

VCCDSW_3P3_1

SKYLAKE-H-PCH_FCBGA837

VCCAPLLEBB_1P0

SPT-H_PCH

CORE

MPHY

USB

VCC1R0_SUS

8 OF 12

1 2

VCCGPIO

R91

0_0603_5%

VCCPRIM_1P0_17

VCCDSW_3P3_2

VCCPGPPA

VCCPGPPBCH_1
VCCPGPPBCH_2

VCCPGPPEF_1

VCCPGPPEF_2

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0_15

VCCATS

VCCRTCPRIM_3P3

VCCRTC

DCPRTC

VCCPRIM_1P0_11
VCCPRIM_1P0_12

VCCPRIM_1P0_13

VCCPRIM_1P0_14

VCCSPI_1

VCCSPI_2
VCCSPI_3

VCCPGPPD_1

VCCPGPPD_2
VCCPGPPD_3
VCCPGPPD_4

VCCPRIM_3P3_1

VCCPRIM_3P3_2
VCCPRIM_3P3_3

VCCUSB2PLL_1P0

1

2

22U_0805_6.3V6-M

AL22

BA24

BA31

BC42
BD40
AJ41

AL41

AD41
AN5

AD15
AD13
BA20
BA22

BA26

AJ20
AJ21

AJ23

AJ25

BE41

BE43
BE42

BC44

BA45
BC45
BB45

BD3

BE3
BE4

@

C68

NEAR PCH PKG

Note 1: Ampere in this page means Iccmax current described in SKL PCH H EDS r0.91 page 57.

A

Note 2: Decoupling capacitors refers SKL H PDG r0.71 page 526.
SKL H RVP11 schematics r0.7 also referred.

RTCVCC

0.1U_0402_25V6-K

1

2

0.1U_0402_25V6-K

1

C659

0.1U_0402_16V7-K

2

0.007A

1

C63

2

NEAR
BA22

@

C724

NEAR
BA31

VCC3B

1U_0402_6.3V6-K

0.746A

VCC3_SUS

@

@

@

1

1

C53

2

0.1U_0402_25V6-K

0.1U_0402_25V6-K

NEAR

NEAR

BC42

AJ41

1

2

1

C288

C514

2

1U_0402_6.3V6-K

NEAR
AD13

1

C54

2

2

0.1U_0402_25V6-K

NEAR
AD41

@

1

C55

C56

2

0.1U_0402_25V6-K

0.1U_0402_25V6-K

NEAR
AN5

NEAR
BA20

1

1

2

C58

C57

2

1U_0402_6.3V6-K

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : POWER

PCH SKL-H : POWER

PCH SKL-H : POWER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

PAYTON

PAYTON

PAYTON

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet

1

21 111

21 111

of

21 111

0.1Custom

0.1Custom

0.1Custom

5

D D

4

3

2

1

SPT-H_PCH

U3I

AC18

VSS_1

AN4

VSS_2

AN10

VSS_3

BE14

VSS_4

BE18

VSS_5

BE23

VSS_6

BE28

VSS_7

BE32

VSS_8

BE37

VSS_9

BE40

VSS_10

BE9

VSS_11

C10

VSS_12

C2

VSS_13

C28

VSS_14

C37

VSS_15

J7

VSS_16

K10

VSS_17

K27

VSS_18

K33

VSS_19

K36

VSS_20

K4

VSS_21

K42

VSS_22

K43

VSS_23

L12

C C

B B

VSS_24

L13

VSS_25

L15

VSS_26

L4

VSS_27

L41

VSS_28

L8

VSS_29

M35

VSS_30

M42

VSS_31

N10

VSS_32

N15

VSS_33

N19

VSS_34

N22

VSS_35

N24

VSS_36

N35

VSS_37

N36

VSS_38

N4

VSS_39

N41

VSS_40

N5

VSS_41

P17

VSS_42

P19

VSS_43

P22

VSS_44

P45

VSS_45

R10

VSS_46

R14

VSS_47

R22

VSS_48

R29

VSS_49

R33

VSS_50

R38

VSS_51

R5

VSS_52

T1

VSS_53

T2

VSS_54

T4

VSS_55

Y18

VSS_56

Y20

VSS_57

Y21

VSS_58

Y26

VSS_59

Y28

VSS_60

Y29

VSS_61

A18

VSS_62

A25

VSS_63

A32

VSS_64

A37

VSS_65

AA17

VSS_66

AA18

VSS_67

AA20

VSS_68

AA21

VSS_69

AA25

VSS_70

AA29

VSS_71

AA4

VSS_72

AA42

VSS_73

AB10

VSS_74

9 OF 12

SKYLAKE-H-PCH_FCBGA837

VSS_75
VSS_76
VSS_77
VSS_78

VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88

VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94

VSS_95
VSS_96
VSS_97

VSS_98
VSS_99

VSS_100

VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112

VSS_113
VSS_114
VSS_115
VSS_116

VSS_117
VSS_118

VSS_119
VSS_120

VSS_121
VSS_122

VSS_123
VSS_124

VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136

VSS_137

VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148

AR5
AR7
U15
AL4

AE29
AE4
AE42
AF18
AF20
AF21
AF23
AF25
AF26

AF28
AF29
AG11
AG13
AG31
AG32
AG33

AG38
AG4
AH1

AH17
AH18

AH20

AH21
AH23
AH25
AH26
AH28
AH29
AH45
AJ10
AJ14
AJ15
AJ17

AJ18
AJ26
AJ28
AJ29
AJ31

AJ32
AJ36

AK4
AK42

AU7
AV17

AV24

AV27
AV31
AV33
AV6
AW13
AW19
AW29
AW37
AW9
AY38
AY45
B25

B3
B37

B40
B6
BA1
BB11
BB16
BB21
BB25
BB30
BB34
BC2

BD43

W14
W31
W32
W33
W38

SPT-H_PCH

U3L

C42

VSS_149

D10

VSS_150

D12

VSS_151

D15

VSS_152

D16

VSS_153

D17

VSS_154

D19

VSS_155

D21

VSS_156

D24

VSS_157

D25

VSS_158

D27

VSS_159

D29

VSS_160

D30

VSS_161

D31

VSS_162

D33

VSS_163

D35

VSS_164

D36

VSS_165

E13

VSS_166

E15

VSS_167

E31

VSS_168

E33

VSS_169

F44

VSS_170

F8

VSS_171

G42

VSS_172

G9

VSS_173

H17

VSS_174

H19

VSS_175

H22

VSS_176

H24

VSS_177

H27

VSS_178

H29

VSS_179

H3

VSS_180

H35

VSS_181

J10

VSS_182

J11

VSS_183

J3

VSS_184

J39

VSS_185

J5

VSS_186

T42

VSS_187

U10

VSS_188

U11

VSS_189

U14

VSS_190

U17

VSS_191

U18

VSS_192

U28

VSS_193

U29

VSS_194

U31

VSS_195

U32

VSS_196

U33

VSS_197

U38

VSS_198

U4

VSS_199

U8

VSS_200

V18

VSS_201

V20

VSS_202

V21

VSS_203

V23

VSS_204

V25

VSS_205

V29

VSS_206

V3

VSS_207

V45

VSS_208

VSS_209
VSS_210
VSS_211
VSS_212
VSS_213

W4

VSS_214

W8

VSS_215

Y17

VSS_216

12 OF 12

SKYLAKE-H-PCH_FCBGA837

VSS_217
VSS_218

VSS_219
VSS_220

VSS_221
VSS_222
VSS_223
VSS_224

VSS_225

VSS_226
VSS_227
VSS_228
VSS_229

VSS_230

VSS_231

VSS_232
VSS_233
VSS_234

VSS_235
VSS_236

VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255

VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261

VSS_262
VSS_263
VSS_264
VSS_265

VSS_266
VSS_267

VSS_268

VSS_269
VSS_270
VSS_271

VSS_272
VSS_273
VSS_274

VSS_275
VSS_276
VSS_277
VSS_278
VSS_279

VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285

AB11
AB7

AB14

AB31

AB32
AB38
AB4
AB5

AC1

AC20
AC21
AC25
AC29

AC45

AB8
AD11
AD14
AB15

AD32
AD33

AD36
AD4
AD8
AE18
AE20
AE21

AE25
AE28
AL10
AL11
AL13
AL17
AL19
AL24
AL29
AL32
AL33
AL38

AM15
AM17
AM19
AM22
AM24
AM27
AM29

AM45
AN11
AN22
AN27

AN31

AN39
AN7

AN8
AP11
AP4

AR33
AR34
AR42

AR9
AT10
AT15
AT36

AT9
AU1
AU35
AU36
AU39
AU45
C4

U3J

PCH_NCTF_1

1

TP86Test_Point_22MIL

PCH_NCTF_3

1

TP84Test_Point_22MIL

PCH_NCTF_4

1

TP85Test_Point_22MIL

PCH_NCTF_5

1

TP80Test_Point_22MIL

PCH_NCTF_7

1

TP82Test_Point_22MIL

PCH_NCTF_8

1

TP83Test_Point_22MIL

PCH_NCTF_2

1

TP87Test_Point_22MIL

PCH_NCTF_6

1

TP81Test_Point_22MIL

BD2

VSS_286

BD45

VSS_287

BD44

VSS_288

BE44

VSS_289

D45

VSS_290

A42

VSS_291

B45

VSS_292

B44

VSS_293

A4

VSS_294

A3

VSS_295

B2

VSS_296

A2

VSS_297

B1

VSS_298

BB1

VSS_299

BC1

VSS_300

A44

VSS_301

C1

RSVD_5

D1

RSVD_6

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

10 OF 12

RSVD_7
RSVD_8
RSVD_9

RSVD_10

RSVD_11

RSVD_12

RSVD_13
RSVD_14
RSVD_15

RSVD_16

RSVD_17

RSVD_18

PREQ#
PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

AR22
W13
U13

P31

N31

Leave as NC

P27

R27
N29
P29

AN29

R24
P24

AT3
AT4

AY5

PCH_2_CPU_TRIGGER_R

AL2
AK1

R656

12

30_0402_1%

-PCH_PREQ 2 4

-PCH_PRDY 24

-CPU_TRST 24
PCH_2_CPU_TRIGGER 13

CPU_2_PCH_TRIGGER 13

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : GND/RSVD

PCH SKL-H : GND/RSVD

PCH SKL-H : GND/RSVD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

22 111

of

22 111

of

22 111

A

0.1

0.1

0.1

5

D D

4

3

2

1

PAYTON WALTER

GPP_D9 -MXM_PRESENCE -DISCRETE_PRESENCE

U3K

AT29

GPP_B22/GSPI1 _MOSI

AR29

GPP_B21/GSPI1 _MISO

AV29

GPP_B20/GSPI1 _CLK

BC27

GPP_B19/GSPI1 _CS#

BD28

GPP_B18/GSPI0 _MOSI

BD27

GPP_B17/GSPI0 _MISO

AW27

GPP_B16/GSPI0 _CLK

AR24

GPP_B15/GSPI0 _CS#

AV44

GPP_C9/UAR T0_TXD

BA41

GPP_C8/UAR T0_RXD

AU44

GPP_C11/UA RT0_CTS#

AV43

GPP_C10/UA RT0_RTS#

AU41

GPP_C15/UA RT1_CTS#/ISH_U ART1_CTS#

AT44

GPP_C14/UA RT1_RTS#/ISH_U ART1_RTS#

AT43

GPP_C13/UA RT1_TXD/ISH_UA RT1_TXD

AU43

GPP_C12/UA RT1_RXD/ISH_UA RT1_RXD

AN43

GPP_C23/UA RT2_CTS#

AN44

GPP_C22/UA RT2_RTS#

AR39

GPP_C21/UA RT2_TXD

AR45

GPP_C20/UA RT2_RXD

AR41

GPP_C19/I2C 1_SCL

AR44

GPP_C18/I2C 1_SDA

AR38

GPP_C17/I2C 0_SCL

AT42

GPP_C16/I2C 0_SDA

AM44

GPP_D4/ISH_ I2C2_SDA/ISH_I2C3 _SDA

AJ44

GPP_D23/ISH _I2C2_SCL/ISH_I2C 3_SCL

SKYLAKE-H-PCH_FCBGA837

R1063 0_0201_5%@

TP88Test_Point_22MIL
TP89Test_Point_22MIL

GPP_B18_NO_ REBOOT

1 2

1

1

Leave as NC Leave as NC

ISH_UART1 _TXD
ISH_UART1 _RXD

GPP_B18_NO_ REBOOT24

VCC3B

C C

From EC

-EC_WAKE75

-EC_SCI75

Leave as NC Leave as NC

B B

SPT-H_PCH

GPP_D9
GPP_D10
GPP_D11

GPP_D16/ISH _UART0_CTS#

GPP_D14/ISH _UART0_TXD/SM L0BCLK/I2C2_SCL

GPP_D13/ISH _UART0_RXD/SM L0BDATA/I2C2_S DA

GPP_D15/ISH _UART0_RTS#

11 OF 12

GPP_D12

GPP_H20/ISH _I2C0_SCL
GPP_H19/ISH _I2C0_SDA

GPP_H22/ISH _I2C1_SCL
GPP_H21/ISH _I2C1_SDA

GPP_A23/ISH _GP5
GPP_A22/ISH _GP4

GPP_A21/ISH _GP3
GPP_A20/ISH _GP2
GPP_A19/ISH _GP1
GPP_A18/ISH _GP0

GPP_A17/ISH _GP7

AL44
AL36
AL35
AJ39

AJ43
AL43
AK44

AK45

BC38
BB38

BD38
BE39

BC22
BD18

BE21
BD22
BD21
BB22

BC19

-MXM_PRES ENCE 31
DGFX_PWRGD 23,32,46

TBT_FORCE_ON 46

-CIO_PLUG_EVEN T 46

From MXM

TBT

From / to TBTTBT

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : GSPI/UART/I2C

PCH SKL-H : GSPI/UART/I2C

PCH SKL-H : GSPI/UART/I2C

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet of

1

of

23 111

of

23 111

23 111

A

0.1

0.1

0.1

5

Enalbe DCI Mode - Short Pad

JDCI1 SHORT PADS@

JTAGX17

PCH_TMS17

PCH_TDI17

D D

-CPU_TRST22

PCH_TDO17

-PCH_PRDY22

-PCH_PREQ22

JTAGX

PCH_TMS

PCH_TDI

-CPU_TRST

PCH_TDO

-PCH_PRDY

-PCH_PREQ

1 2

JDCI2 SHORT PADS@

1

2

JDCI3 SHORT PADS@

1 2

JDCI4 SHORT PADS@

1

2

JDCI5 SHORT PADS@

1

2

JDCI6 SHORT PADS

@

1 2

JDCI7 SHORT PADS@

1

2

4

XDP_TCK

XDP_TMS

XDP_TDI

-XDP_TRST

XDP_TDO

-XDP_PRDY

-XDP_PREQ

3

SPI_IO214,26

1

R597

@

1K_0402_1%

2

2

VCC1R0_SUS

VCC1R0_SUS

1

VCC3B VCC1R0_SUS

R96
for Debug use 2.2KΩ
without debug use 10KΩ

XDP_TCK7

C C

B B

XDP_TMS7

XDP_TDI7

-XDP_TRST7

XDP_TDO7

-XDP_DBR17

-PLTRST_FAR14,46,52,53,56,60,62

BPWRG17,76,83,85

-RSMRST17,24,76

CFG37

R591
R593
R594
R595
R596
R657 NO ASM

R102
R597

A

SHEET 7

R297

XDP_TCK

XDP_TMS
XDP_TDI

-XDP_TRST
XDP_TDO

-XDP_DBR

-PLTRST_FAR

BPWRG

-RSMRST

-XDP_PRDY7

-XDP_PREQ7

No use

NO ASM
NO ASM
NO ASM
NO ASM
NO ASM
NO ASM
NO ASMR658

NO ASM

NO ASM
NO ASM

-XDP_PRDY

-XDP_PREQ

Individual
Port

NO ASM
NO ASM
NO ASM
NO ASM
NO ASM

NO ASM

ASM
ASMNO ASM

ASM
ASM

DCI 2.0
w/o connector

R820 NO ASMASMNO ASM

SHEET 17

5

R821
R822

NO ASM
NO ASM

ASM
ASM

VCCST

1

R96

2.2K_0402_5%

2

2

R99 1K_0402_5%

2

R101 1K_0402_5%

1

R102

@

1K_0402_1%

2

DCI@

R97
51_0402_1%

1 2

1

@

1

@

ASM
ASM
ASM
ASM
ASM
ASM
ASM

NO ASM
NO ASM

ASMR18
NO ASM

LOGIC

NO ASM
NO ASM

4

@

2

C70

0.1U_0402_25V6-K

1

26
25

23

22

21

20
19
18

17
16
15
14
13
12
11
10

9
8
7
6
5

4
3
2
1

JXDP1

26

GND_2

25
2424GND_1
23

22

21

20
19
18

17

16
15
14
13
12
11
10
9
8
7
6

5
4
3
2
1

MOLEX_52435-2671

@

R97

J1
C70
R96
R101

R93
J2
R98
R100

2

R93

@

51_0402_1%

1

PCH_TCK17

28
27

CPUCORE_PWRGD102,17,91

-RSMRST17,24,76

No use

NO ASM
NO ASM
NO ASM
ASM
NO ASM

NO ASM
NO ASM
NO ASM
NO ASM

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

Individual
Port

ASM
ASM
ASM
ASM
ASM

ASM
ASM
ASM
ASM

2015/07/16

2015/07/16

2015/07/16

PCH_TCK

PCH_TMS
PCH_TDI

PCH_TDO

-XDP_DBR

-RSMRST

DCI 2.0
w/o connector

ASM
NO ASM
NO ASM
ASM
NO ASM

NO ASM
NO ASM
NO ASM
NO ASM

LOGIC

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

@

R98 1K_0402_5%

1

2

@

R100 1K_0402_5%

TABLE : Functional Strap

GPP_B18/GSPI0_MOSI (No Reboot)

Enable "No Reboot" Mode

HIGH

LOW Disable "No Reboot" Mode (Default )

VCC3_SUS

1

R563

@

1K_0402_5%

2

GPP_B18_NO_ REBOOT

2016/01/16

2016/01/16

2016/01/16

2

VCC1R0_SUS

JXDP2

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

MOLEX_52435-2671

@

GND_2

GND_1

28

27

R563

ASM

NO ASM

LOGIC

Place near PCH

GPP_B18_NO_ REBOOT 23

Title

Title

Title

XDP CONNECTOR

XDP CONNECTOR

XDP CONNECTOR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

PAYTON

PAYTON

PAYTON

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

24 111

of

of

24 111

24 111

0.1Custom

0.1Custom

0.1Custom

A

5

D D

C C

JRTC1

1

1

2

2

3

GND1

4

GND2

HIGHS_WS32021-S0471-HF

ME@

4

VCC3SW

1

R827

2.2K_0402_5%

2

12

1 2

R828
33K_0402_5%

RDRD

R107
1K_0402_5%

RTCVCC_Must_Less_than_3p2V

RB520CM-30T2R_VMN2M2

D3

12

RB520CM-30T2R_VMN2M2

3

RTCVCC

2

D2

1

1

2

20K_0402_5%

RTCVCC must be less than 3.2V from SKL.

C71
1U_0402_6.3V6-K

R108

1

2

-RTCRST

1

C72
1U_0402_6.3V6-K

2

1 2

JCMOS
SHORT PADS

@

2

-RTCRST 17

1

R109

1 2

20K_0402_5%

B B

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

-SRTCRST

1

C73
1U_0402_6.3V6-K

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

JME
SHORT PADS

1

@

-SRTCRST 17

2016/01/16

2016/01/16

2016/01/16

2

Title

Title

Title

RTC BATTERY

RTC BATTERY

RTC BATTERY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

25 111

of

25 111

of

25 111

0.1

0.1

0.1

A

5

4

3

2

1

R110 R598 U5

D D

PRE ES1
ES1/ ES2

AFTER QS

C C

B B

NO ASM

ASM

SPI_IO314

SPI_CLK14,82

SPI_MOSI_IO014,82

ASM

NO ASM

SPI_IO3

SPI_CLK

SPI_MOSI_IO0

QE="1"

QE=Don't
Care

1

R592
1K_0402_1%

@

2

R592

ASM

NO ASM

2

C74

0.1U_0201_6.3V6-K

1

1

R113 15_0402_5%

1

R115 15_0402_5%

1

R117 15_0402_5%

1

R598
1K_0402_1%

@

2

2

2

2

R358

ASM

NO ASM

2

C75

0.1U_0201_6.3V6-K

1

SPI_IO3_R

SPI_CLK_R

SPI_MOSI_IO0_R

LOGIC

VCC3_SUS VCC3_SUS_SPI

D4
RB520CM-30T2R_VMN2M2

1 2

VCC3_SUS_SPI

12

R110
1K_0402_1%

U5

8

VCC

7

HOLD#

6

CLK

5

DI

W25Q128FVSIQ_SO8

TABLE

SF100 PIN HEADER INTERFACE (TOP VIEW)

1

VCC

3

CS#

5

MISO

7

(KEY)

D12.1
R322.2
R694.2
N/A

WP#

GND

CS#

1

2

DO

3

4

GND
R681.2
R674.2
N/A

-SPI_CS0_R

SPI_MISO_IO1_R

SPI_IO2_R

GND

CLK

MOSI

(RESET)

1

R111
1K_0402_1%

2

R112 0_0402_5%

R114 15_0402_5%

R116 15_0402_5%

1

1 2

1

2

2

-SPI_CS0

SPI_MISO_IO1

SPI_IO2

1

R358
1K_0402_1%

@

2

-SPI_CS0 14

SPI_MISO_IO1 14,82

SPI_IO2 14,24

Note : Pull-down on SPI_IO2 is
placed on page-24

2
4
6
8

2

1

C586

@

10P_0402_50V8-J

A

5

For EMC

1 2

@

4

R646
33_0402_5%

SPI_CLK_R

U5 SPI ROM

vPRO model(16MB)

WINBOND W25Q128FVSIQ
MACRON IX MX25L12 873FM2I-10 G
MICRON N25Q 128A13ESE DFF

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

Title

Title

SPI FLASH

SPI FLASH

SPI FLASH

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet of

1

of

26 111

of

26 111

26 111

A

0.1

0.1

0.1

5

VCC1R2A VCC2R5A

M_A_DQ[0..63] 28,3

M_A_A[0..9] 28,3

-M_A_DQS[0..7] 28,3

M_A_DQS[0..7] 28,3

D D

M_A_VREF_CA_CPU4

2

0.022U_0402_25V7-K

C C

B B

A

C688

1

2

R553

24.9_0402_1%

1

M_A_CB528,3

M_A_CB028,3

-M_A_DQS828,3
M_A_DQS828,3

M_A_CB328,3

M_A_CB228,3

M_A_CKE03

M_A_BG128,3
M_A_BG028,3

M_A_A1228,3

5

VCC1R2A

2

R542
1K_0402_1%

1

R546

1

2_0402_1%

M_A_DQ4

M_A_DQ0

-M_A_DQS0
M_A_DQS0

M_A_DQ7

M_A_DQ3

M_A_DQ13

M_A_DQ12

M_A_DQ15

M_A_DQ14

M_A_DQ21

M_A_DQ20

-M_A_DQS2
M_A_DQS2

M_A_DQ22

M_A_DQ18

M_A_DQ29

M_A_DQ28

M_A_DQ27

M_A_DQ30

M_A_CB0

-M_A_DQS8
M_A_DQS8

M_A_CB3

M_A_CB2

M_A_CKE0

M_A_BG1

M_A_BG0

M_A_A12
M_A_A9

M_A_A8

M_A_A6

M_A_VREF_CA_CHA_DIMM

2

R548
1K_0402_1%

1 2

VCC1R2A

VCC1R2A VCC1R2A

2

C685

1

JDIMM1A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4RB-7H

ME@

0.1U_0402_10V7-K

1

C76

2

C91

DM0_n/DBl0_n

VSS_11

VSS_13

VSS_15

DQS1_c

DQS1_t
VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

DM2_n/DBl2_n

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35

DQS3_c

DQS3_t
VSS_38

VSS_40

VSS_42
CB4/NC

VSS_44

CB0/NC

VSS_46

DM8_n/DBl8_n/NC

VSS_47

CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

10U_0603_6.3V6-M

1U_0402_6.3V6-K

VSS_2

DQ4

VSS_4

DQ0

VSS_6

VSS_7

DQ6

VSS_9

DQ2

DQ12

DQ8

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1

A11

4

1

1

C77

2

10U_0603_6.3V6-M

C92

1U_0402_6.3V6-K

2
4
6
8
10
12
14
16
18
20
22

24
26

28
30

32
34
36
38

40
42

44
46

48

50

52
54
56
58

60

62
64
66
68
70

72

74
76
78
80
82

84
86
88

90

92

94
96
98
100
102
104
106
108
110

112

114

116
118

120

122

A7

124
126

A5

128

A4

130

4

2

VCC1R2A

C78

C93

10U_0603_6.3V6-M

1U_0402_6.3V6-K

1

C79

2

10U_0603_6.3V6-M

C94

1U_0402_6.3V6-K

M_A_DQ1

M_A_DQ5

M_A_DQ6

M_A_DQ2

M_A_DQ9

M_A_DQ8

-M_A_DQS1

M_A_DQS1

M_A_DQ10

M_A_DQ11

M_A_DQ16

M_A_DQ17

M_A_DQ19

M_A_DQ23

M_A_DQ24

M_A_DQ25

-M_A_DQS3
M_A_DQS3

M_A_DQ26

M_A_DQ31

M_A_CB4M_A_CB5

M_A_CB1

M_A_CB7

M_A_CB6

-DRAMRST

M_A_CKE1

-M_A_ACT

-M_A_ALERT

M_A_A11

M_A_A7

M_A_A5
M_A_A4

1

1

C81

C80

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

C96

C95

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_A_CB4 28,3

M_A_CB1 28,3

M_A_CB7 28,3

M_A_CB6 28,3

-DRAMRST 17,28,29,30
M_A_CKE1 3

-M_A_ACT 28,3

-M_A_ALERT 28,3

M_A_A11 28,3

2

@

C689

1

0.1U_0402_10V7-K

1

1

C83

C82

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

C97

C98

1U_0402_6.3V6-K

1U_0402_6.3V6-K

3

VCC0R6B

1

1

C85

C84

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

+

C99

@

2

330U_D2_2VM_R9M

M_A_DDRCLK0_1066M3

-M_A_DDRC LK0_1066M3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

VCC3B

3

M_A_PARITY28,3

M_A_BA128,3

-M_A_CS03

M_A_A14_WE_N28,3

M_A_ODT03

-M_A_CS13

M_A_ODT13

SMB_CLK_3B28,29,30,79,83

R124

1

0_0402_5%

2

C87

C86

1U_0402_6.3V6-K

1U_0402_6.3V6-K

VCC1R2A

M_A_A3
M_A_A1

M_A_DDRCLK0_1066M

-M_A_DDRC LK0_1066M

M_A_PARITY

M_A_BA1

-M_A_CS0

M_A_A14_WE_N M_A_A16_RAS_N

M_A_ODT0

-M_A_CS1

M_A_ODT1

M_A_DQ33

M_A_DQ37

-M_A_DQS4
M_A_DQS4

M_A_DQ38

M_A_DQ39

M_A_DQ44

M_A_DQ41

M_A_DQ43

M_A_DQ46

M_A_DQ50

M_A_DQ52

-M_A_DQS6
M_A_DQS6

M_A_DQ54

M_A_DQ51

M_A_DQ57

M_A_DQ61

M_A_DQ62

M_A_DQ58

1

1

C100

2

2015/07/16

2015/07/16

2015/07/16

C101

2

0.1U_0402_10V7-K

1

C88

2

VCC1R2A

VCC2R5A

2.2U_0402_6.3V6-M

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

C89

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

JDIMM1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

A14/WE_n

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQS5

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4RB-7H

ME@

2

2

C90

1U_0402_6.3V6-K

EVENT_n/NF

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

VSS_56

VSS_58

DM4_n/DBl4_n

VSS_59

VSS_61

VSS_63

VSS_65

VSS_67

DQS5_c

DQS5_t

VSS_70

VSS_72

VSS_74

VSS_76

VSS_78

DM6_n/DBl6_n

VSS_79

VSS_81

VSS_83

VSS_85

VSS_87

DQS7_c

DQS7_t

VSS_90

VSS_92

VSS_94

GND_2

2016/01/16

2016/01/16

2016/01/16

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

BA0

A13

SA2

SDA

SA0
VTT
SA1

VCC1R2A

VCC0R6B

132

A2

134
136
138

140
142
144

A0

146
148
150
152
154
156
158
160

162

164

166
168
170
172

174

176
178
180
182

184
186

188
190

192

194
196
198
200

202
204

206

208

210
212
214
216

218
220
222
224
226
228
230
232

234

236

238
240
242

244

246
248
250

252
254

256

258

260

262

1

VCC3B

12

12

R118
0_0402_5%

@

SA0_CHA_P

R121
0_0402_5%

VCC3B

12

1

2

R119
0_0402_5%

@

SA1_CHA_P

R122
0_0402_5%

VCC3B

1

2

12

R120
0_0402_5%

@

SA2_CHA_P

R123
0_0402_5%

SPD Address = 0H

VCC1R2A

2

R555

M_A_A2

M_A_DDRCLK1_1066M

-M_A_DDRC LK1_1066M

M_A_A0

M_A_A10_AP

M_A_BA0

M_A_A15_CAS_N

M_A_A13

M_A_VREF_CA_CHA_DIMM

SA2_CHA_P

M_A_DQ36

M_A_DQ32

M_A_DQ35

M_A_DQ34

M_A_DQ40

M_A_DQ45

-M_A_DQS5
M_A_DQS5

M_A_DQ47

M_A_DQ42

M_A_DQ48

M_A_DQ49

M_A_DQ53

M_A_DQ55

M_A_DQ56

M_A_DQ60

-M_A_DQS7
M_A_DQS7

M_A_DQ59

M_A_DQ63

SMB_DATA_3BSMB_CLK_3B

SA0_CHA_P

SA1_CHA_P

Title

Title

Title

DDR4 CH-A PRIMARY

DDR4 CH-A PRIMARY

DDR4 CH-A PRIMARY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet of

Date: Sheet

240_0402_1%

1

M_A_DDRCLK1_1066M 3

-M_A_DDRC LK1_1066M 3

M_A_A10_AP 28,3

M_A_BA0 28,3

M_A_A16_RAS_N 28,3

M_A_A15_CAS_N 28,3

M_A_A13 28,3

M_A_VREF_CA_CHA_DIMM 28

VCC1R2A

2

1

@

C692

1

2

2.2U_0402_6.3V6-M

VCC1R2A

SMB_DATA_3B 28,29,30,79,83

1

C691

0.1U_0402_10V7-K

of

27 111

of

27 111

27 111

0.1Custom

0.1Custom

0.1Custom

A

5

M_A_DQ[0..63] 27,3

M_A_A[0..9] 27,3

-M_A_DQS[0..7] 27,3

M_A_DQS[0..7] 27,3

D D

VCC1R2A

1

2

C102

10U_0603_6.3V6-M

4

1

1

1

1

1

C105

C104

C103

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

C106

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

1

C107

C108

2

10U_0603_6.3V6-M

C109

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

VCC2R5A

1

2

3

1

C113

C110

10U_0603_6.3V6-M

C112

C111

2

10U_0603_6.3V6-M

1U_0402_6.3V6-K

1U_0402_6.3V6-K

VCC0R6B

1

2

C114

10U_0603_6.3V6-M

2

VCC3B

1

C116

C115

2

1U_0402_6.3V6-K

10U_0603_6.3V6-M

12

R125
0_0402_5%

SA0_CHA_S

1

R128
0_0402_5%

@

2

1

VCC3B VCC3B

12

R126
0_0402_5%

@

SA1_CHA_S

12

R129
0_0402_5%

1

2

1

2

R127
0_0402_5%

@

SA2_CHA_S

R130
0_0402_5%

DQ4

DQ0

DQ6

DQ2

DQ8

C119

C118

1U_0402_6.3V6-K

2

4
6
8
10
12
14
16

18

20
22
24
26
28

30
32
34
36
38
40

42
44
46
48
50
52

54
56
58
60
62
64
66
68
70
72
74

76

78

80
82

84
86
88
90
92
94
96
98
100

102
104
106
108
110
112
114

116
118
120

A11

122

A7

124

126

A5

128

A4

130

C123

1U_0402_6.3V6-K

1U_0402_6.3V6-K

VCC1R2A

M_A_DQ1

M_A_DQ5

M_A_DQ6

M_A_DQ2

M_A_DQ9

M_A_DQ8

-M_A_DQS1
M_A_DQS1

M_A_DQ10

M_A_DQ11

M_A_DQ16

M_A_DQ17

M_A_DQ19

M_A_DQ23

M_A_DQ24

M_A_DQ25

-M_A_DQS3

M_A_DQS3

M_A_DQ26

M_A_DQ31

M_A_CB4

M_A_CB1

M_A_CB7

M_A_CB6

-DRAMRST

M_A_CKE3

-M_A_ACT

-M_A_ALERT

M_A_A11

M_A_A7

M_A_A5
M_A_A4

C124

C120

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_A_CB4 27,3

M_A_CB1 27,3

M_A_CB7 27,3

M_A_CB6 27,3

-DRAMRST 17,27,29,30

M_A_CKE3 3

-M_A_ACT 27,3

-M_A_ALERT 27,3

M_A_A11 27,3

C125

C121

1U_0402_6.3V6-K

1U_0402_6.3V6-K

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

VDD_16

VDD_18

VREFCA

RFU

VSS_54

DQ36

VSS_56

DQ32

VSS_58

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t

VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t

VSS_90

DQ63

VSS_92

DQ59

VSS_94

SDA

GND_2

VCC1R2A

132

A2

134
136
138
140
142
144

A0

146

148

150

BA0

152
154
156
158

A13

160
162
164
166
168

170

172

174
176

178

180

182
184

186
188

190

192
194
196

198
200

202

204

206
208
210
212
214
216
218

220

222
224
226
228

230
232
234
236
238
240
242
244
246
248
250

252
254
256

SA0

258

Vtt

260

SA1

262

VCC1R2A

VCC2R5A VCC0R6B

VCC1R2A

M_A_A3
M_A_A1

M_A_DDRCLK2_1066M3

-M_A_DDRC LK2_1066M3

VCC3B

M_A_PARITY27,3

M_A_BA127,3

-M_A_CS23

M_A_A14_WE_N27,3

M_A_ODT23

-M_A_CS33

M_A_ODT33

SMB_CLK_3B27,29,30,79,83

R131

1

0_0402_5%

M_A_DDRCLK2_1066M

-M_A_DDRC LK2_1066M

M_A_PARITY

M_A_BA1

-M_A_CS2

M_A_A14_WE_N M_A_A16_RAS_N

M_A_ODT2

-M_A_CS3

M_A_ODT3

M_A_DQ33

M_A_DQ37

-M_A_DQS4

M_A_DQS4

M_A_DQ38

M_A_DQ39

M_A_DQ44

M_A_DQ41

M_A_DQ43

M_A_DQ46

M_A_DQ50

M_A_DQ52

-M_A_DQS6

M_A_DQS6

M_A_DQ54

M_A_DQ51

M_A_DQ57

M_A_DQ61

M_A_DQ62

M_A_DQ58

SMB_CLK_3B

1

2

1

C126

2

C127

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

JDIMM2B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4SB-7H

ME@

RAS_n/A16

CAS_n/A15

C0/CS2_n/NC

DM4_n/DBl4_n

DM6_n/DBl6_n

SPD Address = 1H

VCC1R2A

2

R556

M_A_A2

M_A_DDRCLK3_1066M

-M_A_DDRC LK3_1066M

M_A_A0

M_A_A10_AP

M_A_BA0

M_A_A15_CAS_N

M_A_A13

M_A_VREF_CA_CHA_DIMM

SA2_CHA_S

M_A_DQ36

M_A_DQ32

M_A_DQ35

M_A_DQ34

M_A_DQ40

M_A_DQ45

-M_A_DQS5

M_A_DQS5

M_A_DQ47

M_A_DQ42

M_A_DQ48

M_A_DQ49

M_A_DQ53

M_A_DQ55

M_A_DQ56

M_A_DQ60

-M_A_DQS7
M_A_DQS7

M_A_DQ59

M_A_DQ63

SMB_DATA_3B
SA0_CHA_S

SA1_CHA_S

240_0402_1%

1

M_A_A10_AP 27,3

M_A_BA0 27,3
M_A_A16_RAS_N 27,3

M_A_A15_CAS_N 27,3

M_A_A13 27,3

VCC1R2A

VCC1R2A

SMB_DATA_3B 27,29,30,79,83

M_A_DDRCLK3_1066M 3

-M_A_DDRC LK3_1066M 3

M_A_VREF_CA_CHA_DIMM 27

2

1

@

C693

C694

1

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

C117

1U_0402_6.3V6-K

VCC1R2A VCC1R2A

VCC1R2A

M_A_DQ4

C C

B B

M_A_CB527,3

M_A_CB027,3

-M_A_DQS827,3

M_A_DQS827,3

M_A_CB327,3

M_A_CB227,3

M_A_CKE23

M_A_BG127,3

M_A_BG027,3

M_A_A1227,3

A

M_A_DQ0

-M_A_DQS0
M_A_DQS0

M_A_DQ7

M_A_DQ3

M_A_DQ13

M_A_DQ12

M_A_DQ15

M_A_DQ14

M_A_DQ21

M_A_DQ20

-M_A_DQS2
M_A_DQS2

M_A_DQ22

M_A_DQ18

M_A_DQ29

M_A_DQ28

M_A_DQ27

M_A_DQ30

M_A_CB5

M_A_CB0

-M_A_DQS8

M_A_DQS8

M_A_CB3

M_A_CB2

M_A_CKE2

M_A_BG1

M_A_BG0

M_A_A12
M_A_A9

M_A_A8
M_A_A6

JDIMM2A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4SB-7H

ME@

VSS_2

VSS_4

VSS_6

DM0_n/DBIO_n

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15

DQS1_c

DQS1_t
VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24

VSS_35

DQS3_c

DQS3_t
VSS_38

DQ31

VSS_40

DQ27
VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

DBI8_n
VSS_47
CB6/NC
VSS_49

CB7/NC
VSS_51

RESET_n

CKE1
VDD_2
ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

DDR4 CH-A SECONDARY

DDR4 CH-A SECONDARY

DDR4 CH-A SECONDARY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

28 111

of

28 111

of

28 111

0.1Custom

0.1Custom

0.1Custom

5

M_B_DQ[0..63] 30,4

M_B_A[0..9] 30,4

-M_B_DQS[0..7] 30,4

M_B_DQS[0..7] 30,4

VCC1R2A

R550

2

M_B_DQ2

M_B_DQ5

-M_B_DQS0
M_B_DQS0

M_B_DQ6

M_B_DQ3

M_B_DQ10

M_B_DQ14

M_B_DQ12

M_B_DQ13

M_B_DQ22

M_B_DQ18

-M_B_DQS2

M_B_DQS2

M_B_DQ20

M_B_DQ19

M_B_DQ27

M_B_DQ31

M_B_DQ30

M_B_DQ24

M_B_CB2

M_B_CB6

-M_B_DQS8
M_B_DQS8

M_B_CB7

M_B_CB1

M_B_CKE0

M_B_BG1

M_B_BG0

M_B_A12
M_B_A9

M_B_A8
M_B_A6

VCC1R2A

2

R549
1K_0402_1%

1

M_B_VREF_CA_CHB_DIMM

R551
1K_0402_1%

1 2

VCC1R2A

2

1

D D

C C

B B

A

M_B_VREF_DQ_CPU4

0.022U_0402_25V7-K

C687

M_B_CB230,4

M_B_CB630,4

-M_B_DQS830,4
M_B_DQS830,4

M_B_CB730,4

M_B_CB130,4

M_B_CKE04

M_B_BG130,4
M_B_BG030,4

M_B_A1230,4

2

1

2

R552

24.9_0402_1%

1

1

2_0402_1%

VCC1R2A VCC2R5A

1

C128

2

C143

C686

0.1U_0402_10V7-K

JDIMM3A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13
15
17
19
21
23
25
27
29
31
33

35

37

39
41
43
45

47

49
51
53
55

57
59

61
63

65

67
69
71
73

75
77
79

81

83

85
87

89
91

93
95

97

99
101
103
105
107
109
111
113
115
117
119
121

123
125

127
129

DM0_n/DBI0_n

DQS0_t

VSS_8
DQ7
VSS_10
DQ3
VSS_12
DQ13
VSS_14
DQ9
VSS_16
DM1_n/DBl1_n

VSS_17
DQ15
VSS_19
DQ10
VSS_21
DQ21

VSS_23

DQ17
VSS_25
DQS2_c

DM2_n/DBl2_n

DQS2_t

VSS_28
DQ23
VSS_30

DQ19

VSS_32

DQ29
VSS_34
DQ25
VSS_36

DM3_n/DBl3_n
VSS_37
DQ30

VSS_39

DQ26

VSS_41
CB5/NC

VSS_43
CB1/NC

VSS_45
DQS8_c

DBI8_n/DBI_n/NC

DQS8_t
VSS_48

CB2/NC
VSS_50
CB3/NC
VSS_52
CKE0
VDD_1
BG1
BG0
VDD_3
A12
A9
VDD_5

A8

A6
VDD_7

FOX_AS0A827-H8RB-7H

ME@

RESET_n

ALERT_n

10U_0603_6.3V6-M

1U_0402_6.3V6-K

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15

DQS1_c

DQS1_t
VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24

VSS_35

DQS3_c

DQS3_t

VSS_38

DQ31

VSS_40

DQ27
VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

VSS_47
CB6/NC

VSS_49
CB7/NC
VSS_51

CKE1

VDD_2

ACT_n

VDD_4

VDD_6

VDD_8

DQ4

DQ0

DQ6

DQ2

DQ8

4

1

1

1

C131

2

10U_0603_6.3V6-M

C146

1U_0402_6.3V6-K

VCC1R2A

M_B_DQ4

M_B_DQ0

M_B_DQ1

M_B_DQ7

M_B_DQ8

M_B_DQ9

-M_B_DQS1

M_B_DQS1

M_B_DQ11

M_B_DQ15

M_B_DQ17

M_B_DQ16

M_B_DQ23

M_B_DQ21

M_B_DQ28

M_B_DQ25

-M_B_DQS3

M_B_DQS3

M_B_DQ26

M_B_DQ29

M_B_CB4

M_B_CB3

M_B_CB5

M_B_CB0

-DRAMRST

M_B_CKE1

-M_B_ACT

-M_B_ALERT

M_B_A11

M_B_A7

M_B_A5
M_B_A4

1

C132

2

10U_0603_6.3V6-M

C147

1U_0402_6.3V6-K

2

@

1

1

C130

C129

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

C145

C144

1U_0402_6.3V6-K

1U_0402_6.3V6-K

VCC1R2A

2
4
6
8

10
12
14
16
18
20
22
24
26

28
30
32
34
36
38
40

42
44
46

48
50

52

54
56
58
60
62
64
66
68
70
72
74

76
78
80
82

84
86
88
90
92
94
96
98

100
102
104
106
108
110
112

114

116
118
120

A11

122

A7

124

126

A5

128

A4

130

1

C133

2

2

10U_0603_6.3V6-M

C148

1U_0402_6.3V6-K

M_B_CB4 30,4

M_B_CB3 30,4

M_B_CB5 30,4

M_B_CB0 30,4

-DRAMRST 17,27,28,30

M_B_CKE1 4

-M_B_ACT 30,4

-M_B_ALERT 30,4

M_B_A11 30,4

C690

0.1U_0402_10V7-K

1

C134

C135

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

C150

C149

1U_0402_6.3V6-K

1U_0402_6.3V6-K

3

1

1

C136

C137

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

+

C151

@

2

330U_D2_2VM_R9M

M_B_DDRCLK0_1066M4

-M_B_DDRC LK0_1066M4

VCC3B

M_B_PARITY30,4

M_B_BA130,4

-M_B_CS04

M_B_A14_WE_N30,4

M_B_ODT04

-M_B_CS14

M_B_ODT14

SMB_CLK_3B27,28,30,79,83

R138

1

0_0402_5%

2

C139

C138

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_B_DDRCLK0_1066M

-M_B_DDRC LK0_1066M

M_B_PARITY

M_B_A14_WE_N

SMB_CLK_3B

1

C152

2

0.1U_0402_10V7-K

VCC1R2A

M_B_A3

M_B_A1

M_B_BA1

-M_B_CS0

M_B_ODT0

-M_B_CS1

M_B_ODT1

M_B_DQ38

M_B_DQ35

-M_B_DQS4
M_B_DQS4

M_B_DQ33

M_B_DQ32

M_B_DQ40

M_B_DQ41

M_B_DQ42

M_B_DQ46

M_B_DQ52

M_B_DQ48

-M_B_DQS6
M_B_DQS6

M_B_DQ50

M_B_DQ51

M_B_DQ57

M_B_DQ61

M_B_DQ56

M_B_DQ60

1

C153

2

2.2U_0402_6.3V6-M

VCC0R6B

1

2

C140

VCC1R2AVCC2R5A

1

2

10U_0603_6.3V6-M

131
133
135
137

139
141

143

145

147

149

151
153
155
157

159

161
163
165
167
169

171

173
175
177
179
181
183
185
187
189
191
193
195

197
199
201
203
205
207
209
211

213

215
217

219

221
223
225
227
229
231
233
235

237

239

241
243
245
247
249
251
253
255
257

259

261

2

C141

C142

1U_0402_6.3V6-K

10U_0603_6.3V6-M

JDIMM3B

A3
A1
VDD_9
CK0_t

CK0_c
VDD_11

Parity

BA1
VDD_13
CS0_n

WE_n/A14
VDD_15
ODT0
CS1_n

VDD_17

ODT1
VDD_19
C1/CS3_n/NC
VSS_53
DQ37

VSS_55
DQ33

VSS_57
DQS4_c
DQS4_t
VSS_60
DQ38
VSS_62
DQ34
VSS_64
DQ44
VSS_66
DQ40
VSS_68

DM5_n/DBl5_n
VSS_69
DQ46
VSS_71
DQ42
VSS_73
DQ52

VSS_75

DQ49
VSS_77

DQS6_c

DQS6_t

VSS_80
DQ55
VSS_82
DQ51
VSS_84
DQ61
VSS_86

DQ56

VSS_88

DM7_n/DBl7_n
VSS_89

DQ62

VSS_91
DQ58
VSS_93
SCL
VDDSPD
VPP_1

VPP_2

GND_1

FOX_AS0A827-H8RB-7H

ME@

EVENT_n/NF

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

BA0

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

SA2

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t
VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

DM6_n/DBl6_n

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t
VSS_90

DQ63

VSS_92

DQ59

VSS_94

SDA

GND_2

1

VCC3B

1

2

1

2

R132
0_0402_5%

@

SA0_CHB_P

R135
0_0402_5%

VCC3B

12

1

2

R136
0_0402_5%

SA1_CHB_P

R133
0_0402_5%

@

VCC3B

12

1

2

R134
0_0402_5%

@

SA2_CHB_P

R137
0_0402_5%

SPD Address = 2H

VCC1R2A

VCC0R6B

132

A2

134
136

138

140

142
144

A0

146
148

150

152
154
156

158

A13

160
162

164
166
168
170
172
174
176
178
180
182
184
186

188
190
192
194
196
198
200
202
204
206
208
210

212
214
216
218
220
222
224
226
228
230
232

234

236

238
240
242
244
246
248

250
252

254
256

SA0

258

Vtt

260

SA1

262

M_B_A2

M_B_DDRCLK1_1066M

-M_B_DDRC LK1_1066M

M_B_A0

M_B_A10_AP

M_B_BA0
M_B_A16_RAS_N

M_B_A15_CAS_N

M_B_A13

M_B_VREF_CA_CHB_DIMM

SA2_CHB_P

M_B_DQ34

M_B_DQ39

M_B_DQ36

M_B_DQ37

M_B_DQ44

M_B_DQ45

-M_B_DQS5
M_B_DQS5

M_B_DQ47

M_B_DQ43

M_B_DQ54

M_B_DQ55

M_B_DQ53

M_B_DQ49

M_B_DQ59

M_B_DQ62

-M_B_DQS7

M_B_DQS7

M_B_DQ63

M_B_DQ58

SMB_DATA_3B

SA0_CHB_P

SA1_CHB_P

VCC1R2A

2

R557
240_0402_1%

1

M_B_DDRCLK1_1066M 4

-M_B_DDRC LK1_1066M 4

M_B_A10_AP 30,4

M_B_BA0 30,4
M_B_A16_RAS_N 30,4

M_B_A15_CAS_N 30,4

M_B_A13 30,4

M_B_VREF_CA_CHB_DIMM 30

VCC1R2A

2

1

@

C696

1

2

2.2U_0402_6.3V6-M

VCC1R2A

SMB_DATA_3B 27,28,30,79,83

C695

0.1U_0402_10V7-K

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

DDR4 CH-B PRIMARY

DDR4 CH-B PRIMARY

DDR4 CH-B PRIMARY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet of

Date: Sheet

1

of

29 111

of

29 111

29 111

0.1Custom

0.1Custom

0.1Custom

5

M_B_DQ[0..63] 29,4

M_B_A[0..9] 29,4

-M_B_DQS[0..7] 29,4

M_B_DQS[0..7] 29,4

D D

VCC1R2A VCC1R2A

VCC1R2A VCC1R2A

M_B_DQ2

C C

B B

M_B_CB229,4

M_B_CB629,4

-M_B_DQS829,4

M_B_DQS829,4

M_B_CB729,4

M_B_CB129,4

M_B_CKE24

M_B_BG129,4

M_B_A1229,4

A

M_B_DQ5

-M_B_DQS0
M_B_DQS0

M_B_DQ6

M_B_DQ3

M_B_DQ10

M_B_DQ14

M_B_DQ12

M_B_DQ13

M_B_DQ22

M_B_DQ18

-M_B_DQS2
M_B_DQS2

M_B_DQ20

M_B_DQ19

M_B_DQ27

M_B_DQ31

M_B_DQ30

M_B_DQ24

M_B_CB2

M_B_CB6

-M_B_DQS8

M_B_DQS8

M_B_CB7

M_B_CB1

M_B_CKE2

M_B_BG1

M_B_BG0

M_B_A12
M_B_A9

M_B_A8
M_B_A6

VCC1R2A

JDIMM4A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4RB-7H

ME@

1

C154

2

10U_0603_6.3V6-M

C169

1U_0402_6.3V6-K

VSS_2

VSS_4

VSS_6

DM0_n/DBl0_n

VSS_7

VSS_9

VSS_11

VSS_13

VSS_15

DQS1_c

DQS1_t
VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

DM2_n/DBl2_n

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35

DQS3_c

DQS3_t

VSS_38

VSS_40

VSS_42

CB4/NC
VSS_44
CB0/NC
VSS_46

DM8_n/DBl8_n/NC

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

VDD_2
ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

1

2

DQ12

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1

DQ4

DQ0

DQ6

DQ2

DQ8

4

1

1

1

C156

C155

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

C170

C171

1U_0402_6.3V6-K

1U_0402_6.3V6-K

2
4
6
8
10

12

14
16
18
20
22
24
26
28
30
32
34
36

38
40
42
44
46
48
50
52

54

56
58

60

62
64
66
68
70
72
74
76

78

80

82

84

86
88
90
92
94
96
98
100
102
104
106
108

110
112
114
116
118
120

A11

122

A7

124
126

A5

128

A4

130

1

1

C158

C157

2

2

10U_0603_6.3V6-M

C172

1U_0402_6.3V6-K

M_B_DQ4

M_B_DQ0

M_B_DQ1

M_B_DQ7

M_B_DQ8

M_B_DQ9

-M_B_DQS1
M_B_DQS1

M_B_DQ11

M_B_DQ15

M_B_DQ17

M_B_DQ16

M_B_DQ23

M_B_DQ21

M_B_DQ28

M_B_DQ25

-M_B_DQS3
M_B_DQS3

M_B_DQ26

M_B_DQ29 M_B_DQS6

M_B_CB4

M_B_CB3

M_B_CB5

M_B_CB0

-DRAMRST

M_B_CKE3

-M_B_ACT

-M_B_ALERT

M_B_A11

M_B_A7

M_B_A5
M_B_A4

C159

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

C173

C174

1U_0402_6.3V6-K

1U_0402_6.3V6-K

1

C160

C161

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

C175

C176

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_B_CB4 29,4

M_B_CB3 29,4

M_B_CB5 29,4

M_B_CB0 29,4

-DRAMRST 17,27,28,29
M_B_CKE3 4

-M_B_ACT 29,4

-M_B_ALERT 29,4

M_B_A11 29,4

VCC2R5A

1

2

M_B_DDRCLK2_1066M4

-M_B_DDRC LK2_1066M4

C162

3

10U_0603_6.3V6-M

VCC3B

1

C163

2

M_B_A14_WE_N29,4

1 2

10U_0603_6.3V6-M

M_B_PARITY29,4

M_B_BA129,4

-M_B_CS24

M_B_ODT24

-M_B_CS34

M_B_ODT34

SMB_CLK_3B27,28,29,79,83

R145

0_0402_5%

C164

1U_0402_6.3V6-K

M_B_DDRCLK2_1066M

-M_B_DDRC LK2_1066M

C165

1U_0402_6.3V6-K

M_B_PARITY

M_B_A14_WE_N

SMB_CLK_3B

1

C178

2

0.1U_0402_10V7-K

1

C167

2

10U_0603_6.3V6-M

131
133
135
137

139
141
143

145
147
149
151
153
155
157
159
161
163

165
167
169

171

173

175
177
179
181
183
185

187

189

191
193

195
197
199

201
203
205
207
209

211
213
215
217
219
221
223
225
227
229
231
233

235
237
239
241
243
245
247

249

251
253
255
257
259

261

2

C168

1U_0402_6.3V6-K

JDIMM4B

A3
A1

EVENT_n/NF

VDD_9
CK0_t
CK0_c

VDD_11
Parity

BA1
VDD_13
CS0_n
A14/WE_n
VDD_15
ODT0
CS1_n
VDD_17
ODT1

VDD_19

C1/CS3_n/NC
VSS_53
DQ37

VSS_55

DQ33

VSS_57
DQS4_c
DQS4_t
VSS_60
DQ38
VSS_62
DQ34

VSS_64

DQ44
VSS_66

DQ40
VSS_68
DM5_n/DBl5_n

VSS_69
DQ46
VSS_71
DQ42
VSS_73
DQ52

VSS_75
DQ49
VSS_77
DQS6_c
DQS6_t
VSS_80
DQS5
VSS_82
DQ51
VSS_84
DQ61
VSS_86

DQ56
VSS_88
DM7_n/DBl7_n
VSS_89
DQ62
VSS_91

DQ58

VSS_93
SCL
VDDSPD
VPP_1
VPP_2

GND_1

FOX_AS0A826-H4RB-7H

ME@

CK1_c/NF

A16/RAS_n

A15/CAS_n

C0/CS2_n/NC

DM4_n/DBl4_n

DM6_n/DBl6_n

VDD_10

CK1_t/NF

VDD_12

A10/AP

VDD_14

BA0

VDD_16

VDD_18

VREFCA

SA2

VSS_54

DQ36

VSS_56

DQ32

VSS_58

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t
VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t
VSS_90

DQ63

VSS_92

DQ59

VSS_94

SDA
SA0
VTT
SA1

GND_2

A2

A0

A13

VCC0R6B

1

C166

2

10U_0603_6.3V6-M

VCC1R2A

VCC2R5A VCC0R6B

VCC1R2A

M_B_A3
M_B_A1

M_B_BA1

-M_B_CS2

M_B_ODT2

-M_B_CS3

M_B_ODT3

M_B_DQ38

M_B_DQ35

-M_B_DQS4

M_B_DQS4

M_B_DQ33

M_B_DQ32

M_B_DQ40

M_B_DQ41

M_B_DQ42

M_B_DQ46

M_B_DQ52

M_B_DQ48

-M_B_DQS6

M_B_DQ50

M_B_DQ51

M_B_DQ57

M_B_DQ61

M_B_DQ56

M_B_DQ60

1

C179

2

2.2U_0402_6.3V6-M

VCC1R2A

132
134
136
138
140
142

144

146
148
150
152
154

156
158
160
162
164
166
168
170
172
174
176

178

180

182
184
186
188

190

192
194
196
198

200

202

204

206

208
210
212
214
216

218

220

222
224

226

228

230
232

234

236

238
240
242
244
246
248
250

252
254
256
258
260

262

VCC3B

12

12

R139
0_0402_5%

SA0_CHB_S

R142
0_0402_5%

@

VCC3B VCC3B

1

R140
0_0402_5%

2

SA1_CHB_S

1

R143
0_0402_5%

@

2

SPD Address = 3H

VCC1R2A

R558

M_B_A2

M_B_DDRCLK3_1066M

-M_B_DDRC LK3_1066M

M_B_A0

M_B_A10_AP

M_B_BA0
M_B_A16_RAS_N

M_B_A15_CAS_N

M_B_A13

M_B_VREF_CA_CHB_DIMM

SA2_CHB_S

M_B_DQ34

M_B_DQ39

M_B_DQ36

M_B_DQ37

M_B_DQ44

M_B_DQ45

-M_B_DQS5
M_B_DQS5

M_B_DQ47

M_B_DQ43

M_B_DQ54

M_B_DQ55

M_B_DQ53

M_B_DQ49

M_B_DQ59

M_B_DQ62

-M_B_DQS7

M_B_DQS7

M_B_DQ63

M_B_DQ58

SMB_DATA_3B

SA0_CHB_S

SA1_CHB_S

240_0402_1%

1 2

M_B_A10_AP 29,4

M_B_BA0 29,4
M_B_A16_RAS_N 29,4

M_B_A15_CAS_N 29,4

M_B_A13 29,4

VCC1R2A

VCC1R2A

SMB_DATA_3B 27,28,29,79,83M_B_BG029,4

1

1

R141
0_0402_5%

@

2

SA2_CHB_S

12

R144
0_0402_5%

M_B_DDRCLK3_1066M 4

-M_B_DDRC LK3_1066M 4

M_B_VREF_CA_CHB_DIMM 29

2

1

@

2

C697

C698

1

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTA INS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CEN TER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

DDR4 CH-B SECONDARY

DDR4 CH-B SECONDARY

DDR4 CH-B SECONDARY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Wednesday, December 07, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

30 111

of

30 111

of

30 111

0.1Custom

0.1Custom

0.1Custom