LENOVO ThinkPad P51X Schematics

D

TBT-PWR SW
/USB Type-C
(port 1)

C

B

A

HDMI Conn.

52

USB3.0
CONN (USB1)

USB3.0
AOU (USB2)

USB2.0 M.2
WWAN Slot

USB3.0
Docking

USB3.0
CONN (USB3)

USB3.0
CONN (USB4)

USB2.0 M.2
WLAN Slot (BT)

USB3.0 2D/3D
Camera

USB2.0
Touch Panel

USB2.0
Smart Card Slot

USB2.0
Express Slot

USB2.0

Port 09

Fingerprint
Reader
Conn

5

LCD CONN
eDP 15.6"
FHD/UHD

SPI Flash TBT

45

8Mbits

Thunderbolt

46-51

Port 5~8ports from PCH
PCI Express x4

Back

USB2.0 CH02
USB3.0 CH02

54

Back

USB2.0 CH01
USB3.0 CH01

54

USB2.0 CH03
USB3.0 CH03

61

USB2.0 CH04
USB3.0 CH04

74

Right

USB2.0 CH05
USB3.0 CH05

55

Right

USB2.0 CH06
USB3.0 CH06

55

USB2.0 CH14

61

USB2.0 CH08
USB3.0 CH08

40

USB2.0 CH10

78

USB2.0 CH11

64

USB2.0 CH12

64

USB2.0

Port 13

Color
Sensor
Conn

79

5

eDPx1

42

46

eDPx1

dGPU

NVIDIA

DPx2

N17P-Q1
N17P-Q3

31-39

Mini DisplayPort

DisplayPort
(Docking)

LED for ThinkPad Logos

SM Bus

ClickPad

40

44

71

USB x 11 ports

HDD CONN
SSD

HDD CONN
SSD

M.2 SLOT
SSD

M.2 SLOT
SSD

RTC Battery

CPU FAN
GPU GAN

G-Sensor

Thermal Sensor

PECI 3.0

SMB-MB/SB

LED for Camera

eDP
Mux

eDPx1

41

PEGx16
GEN3

DP Mux

43

16

SATA x4

CH2

65

66

60

60

25

80

81

11

CH3

CH0

CH4

Embedded
Controller
MEC1653L

CS13 Keyboard with
Numpad

4

Channel A

CPU

Intel

Kabylake_H

BGA1440

45W

3,4,5,6,7,8,9,
10,11,12,13

DMI x1

DDR4 2400MHz

Channel B

DDR4 2400MHz

PECI3.0

PCH

Intel

Kabylake-H

vPro

14,15,16,17,18
19,20,21,22,23

LPC Bus 33MHz

TPM 1.2

Lenovo
ASIC
ThinkEngine

75,76,77 84,85

Power Button
Subcard

7879

4

40

USB Port 8

DDR4 / 1.2V

SM Bus_B

SM Bus_B

CPU XDP

SM Bus

C-Link

PCI Express x11 ports

HDA

SPI Flash
128 Mbits
(SPI 0)

82

Camera
Subcard

3

UNBUFFERED
DDR4
SO-DIMMA1

UNBUFFERED
DDR4
SO-DIMMB1

26

USB 2.0 P?/P?
USB 3.0 P?
SATA P?/P?
MDI

27 28

29

24

Stereo
Speaker

69

Microphone
Headphone

Audio
Combo Jack

I/O SubCard Interface

LED for ThinkPad Logos

40

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

UNBUFFERED
DDR4
SO-DIMMA2

Walter2-Note Block Diagram

Project Code:

PCB(Raw Card):

UNBUFFERED
DDR4
SO-DIMMB2

ALC3268 HDA
CODEC

68,69 71 42

66

Issued Date

Issued Date

Issued Date

30

I2C

Audio
(Docking)

Internal
Mic

AC-DC IN

Camera-(USB3)/LID SW
LAN Sub Card

LED for ThinkPad Logo
On A cover

2015/07/16

2015/07/16

2015/07/16

67,68 62 64 56

2

Wireless LAN
Antenna

(M.2 WLAN Card)

Bluetooth

Type-A M.2 Card

USB

Port 14

Port 13
(X1)

Multi-Media
Controller
RTS5250s

SD/MMC
Card Slot

63

DC/DC
Converter

86

I2C

40

40

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

External Connector/Socket

Internal Connector/Socket

Internal Switch

2

61

SIM Card

Port 3
(X1)

M.2 SLOT
Optane Memory
SSD

Express
Card Slot

Main
Battery

Slot

60 60

Port 9~12
(X4)

Port 1
(X1)

Intel GbE PHY
JACKSONVILLE

88

2016/01/16

2016/01/16

2016/01/16

2016 Mar ' 10

Wireless WAN
Antenna

(M.2 WWAN Card/
Optane Memory)

Type-B M.2 Card

61

USB

Port 3

M.2 SLOT
Optane Memory
SSD

Port 17~20
(X4)

Thunderbolt

Port 4
(X1)

LAN
MUX

MAGNETICS
RJ45

58,59

Docking

57

Title

Title

Title

TITLE PAGE

TITLE PAGE

TITLE PAGE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

PCB Layer Stackup

L1:TOP
L2:GND1
L3:Signal 1
L4:GND 2
L5:Signal 2
L6:GND3
L7:VCC1
L8:Signal 3
L9:VCC2
L10:Signal 4
L11:GND4
L12:BOTTOM

61

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

BQ24780SRUYR

INPUTS

TPS51285BRUKR

VINT20

M: NCP81205MNTXG
S: NCP81382MNTXG

VINT20

NB681AGD-Z

SN1409027RVER

VCC5M

VCC1R2A/VCC0R6B
+SMDDR_VREF_DIMM

TPS51716RUKR

VINT20

BD9139MUV-E2

BD91364BMUU-ZE2

NCP81172MNTWG

TPS51219RTER

NB681AGD-Z

VCC5M

!"#$%&'

!"#$%&'

!"#$%&'

1

Battery Charger

OUTPUTS

M-BAT-PWRDOCK_PWR20_F

System DC/DC

VCC5M
VCC3M

CPU DC/DC

VCCCPUIO

91

92,93,94

VCCCPUCORE
VCCGFXCORE_I
VCCSA

VCCCPUIOVINT20

VCC1R0_SUS

VCC1R0_SUS

+SMDDR_VREF_DIMM

VCC0R6B
VCC1R2A

VCC1R8B

VCC1R8BVCC5M

VCC2R5A

VCC2R5AVCC5M

GFXCORE_D

VCCGFXCORE_DVINT20

VCC1R35VIDEO

VCC1R35VIDEOVCC5M

VCC1R05VIDEO

VCC1R05VIDEO
VCC1R05VIDEO_PLL

1 116

1 116

1

1 116

D

88

90

C

95

96

99

B

98

100

110

111

A

112

0.1

0.1

0.1

of

of

of

5

4

3

2

1

TABLE: SYSTEM POWER STATE

Gx State
(System State)

D

G0 S0 M0

G1

G2

G3 --- --- OFF OFF OFF OFF OFF OFF

Sx State
(System State)

Mx State
(System State)SWPowerMPower

SUS

AMT

Power

PowerAPowerBPower

ON ON ON ON ON ON

S3

M3
M-OFF

ON ON ON ON ON OFF
ON ON ON OFF ON OFF

Deep S3 M-OFF ON ON OFF OFF ON OFF
S4 M3 ON ON ON ON OFFOFF
Deep S4 M-OFF ON ON ONOFF OFF OFF
S5
Deep S5
S5 EC OFF

M3
M-OFF
M-OFF

ONONON ON

ON

OFF OFF OFF OFF OFF

OFF

OFF OFFON
ON

User Observation Chipset

System Operating

Standby

Standby
with USB wake enabled

Standby

Hibernation
with RTC wakeup

Hibernation or
Shutdown

OFFOFFOFF

No Power

Full On

Suspend-to-RAM
(STR)

Suspend-to-Disk
(STD)

Soft Off

Mechanical Off

Schematics Mark Definition

BOM Structure BTO Item

@
EMC@ Assembled. EMC related parts.

C

RF@
ME@
PRxxx,PCxxx,

PLxxx

N16PQ1@
N16SQ3@
VP@
NVP@

Not assembled.

Assembled. RF related parts.
Assembled. ME related parts.
PWR related parts.

If @, not assembled.

Assembled. for N16PQ1 GPU SKU
Assembled. for N16PQ3 GPU SKU
Assembled. for support vPro
Assembled. Not support vPro

EC SMBus0 address

Device

Smart Battery

Address

0001 011X b

EC SMBus2 address

Device Address

Charge Controller

0001 0010

PCH SM Bus address

CH-A P

CH-A S

CH-B P

CH-B S

DDR DIMM0

DDR DIMM1

DDR DIMM2

DDR DIMM3

AddressDevice

1001 0000b

1001 0001b

1001 0010b

1001 0011b

EC SMBus1 address

Device Address

G-Senor (LIS3DH)

G-Senor (KX023)

0011 000Xb

0011 110Xb

EC SMBus10 address

Device

Master VGA

Address

0x9E

PCH SM Bus0 address

Device

Intel Lan_I219

Address

0XC8

D

C

!"#$%&'()$*+),$-.,($/(-%0$.1$2)%'./.&(3$%"$4+#&%"56+-&()7
89:;<8=>;<8=?@A9;<8=?@4B;<8=?@C4D;<?CAA;<$
?CAA@A9;777$EF<?F<GFH4?F$)(-+&(3$EG?I77

VRAM

VRAM LAN

ZZZ

ZZZ1

LAN

U21

!"#"$%&'()*"+%,-)*'&.

B

/$%&*1(./&+&(1,"%2)

X7614001001

S4GQ1@

ZZZ2

3456738397:4;<==

D%-()+"J(
D(*2()+&M)($?'+)+J&().1&.J1
E+&(3$K%-&+L(
4+J,+L($9.N(

GPU

GPU

X7614001002

M4GQ1@

UV1

X7614001003

S4GQ3@

ZZZ3

X7614001004

M4GQ3@

UV1

WGI219LM SLKJ5 A0

SA000073020 VPRO@

U21

WGI219V SLKJ5 A0

SA000072Z10 NVPRO@

B

!$*+$%&,-%$./0&%&(,$%12,1(2)

+,-."/

!"#$ %&'%&( )&(%&* )&*)&'

A

A

!"#$%&'($)

78 9:&;45<=>

0&1 2*3041 05+!36

!DEF@6B?G

!?!@A? +?+@!B (? 0&++C(B

+,-."/

>A F!6D?@QB2

HI7J7&*D

HI7J:&*DHI7J8*D HI8KHI7J&*D

C

23?

HI:K HI9KL"/$MNOP$ HI87KHI&K HI97KHI:7K

+,-."/ * S %0' )+

H97RI87KH877RI7KL"/$MNOP$

5

H;7RI:7KH:7RI87K H&7RI:7KH=7RI:7K

4

I97KTUT87K

CPU PCB

CPU PCB

U1

i7-7820HQ vPro

SA000086P10

CPU1@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

N17P-Q1-A2 FCBGA 908P

SA000084H00

N17PQ1@

U1

i7-7700HQ N-VP

SA000086Q20

CPU2@

2

2016/01/16

2016/01/16

2016/01/16

U1

E3-1505MV6

SA000086Y10

CPU3@

N17P-Q3-A2 FCBGA 908P

SA000084G00

N17PQ3@

U1

E3-1535MV6

SA000086R10

CPU4@

Title

Title

Title

Blank

Blank

Blank

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

!"#$%&'

!"#$%&'

!"#$%&'

1

ZZZ4

PCB NM-B041

DAZ12W00100

of

of

of

2 116

2 116

2 116

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

D

M_A_DQ[0..63]<27,28>

C

B

M_A_CB0<27,28>

M_A_CB1<27,28>

M_A_CB2<27,28>

M_A_CB3<27,28>

M_A_CB4<27,28>

M_A_CB5<27,28>

M_A_CB6<27,28>

M_A_CB7<27,28>

M_A_DQ0
M_A_DQ1

M_A_DQ2

M_A_DQ3
M_A_DQ4
M_A_DQ5

M_A_DQ6
M_A_DQ7

M_A_DQ8

M_A_DQ9

M_A_DQ10

M_A_DQ11
M_A_DQ12
M_A_DQ13

M_A_DQ14

M_A_DQ15

M_A_DQ16

M_A_DQ17

M_A_DQ18
M_A_DQ19

M_A_DQ20

M_A_DQ21

M_A_DQ22
M_A_DQ23

M_A_DQ24

M_A_DQ25

M_A_DQ26

M_A_DQ27

M_A_DQ28

M_A_DQ29

M_A_DQ30

M_A_DQ31

M_A_DQ32

M_A_DQ33

M_A_DQ34

M_A_DQ35
M_A_DQ36

M_A_DQ37

M_A_DQ38
M_A_DQ39

M_A_DQ40

M_A_DQ41

M_A_DQ42
M_A_DQ43
M_A_DQ44

M_A_DQ45

M_A_DQ46

M_A_DQ47

M_A_DQ48

M_A_DQ49
M_A_DQ50

M_A_DQ51
M_A_DQ52

M_A_DQ53

M_A_DQ54

M_A_DQ55

M_A_DQ56

M_A_DQ57

M_A_DQ58

M_A_DQ59

M_A_DQ60
M_A_DQ61

M_A_DQ62

M_A_DQ63

M_A_CB0

M_A_CB1

M_A_CB2

M_A_CB3

M_A_CB4

M_A_CB5

M_A_CB6

M_A_CB7

U1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_CKP[0]

DDR0_CKN[0]

DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CLKP[2]

DDR0_CLKN[2]
DDR0_CLKP[3]

DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]
DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_ODT[2]

DDR0_ODT[3]

DDR0_MA[3]

DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0]

DDR0_DQSN[1]

DDR0_DQSP[0]

DDR0_DQSP[1]

DDR0_DQSP[8]

DDR0_DQSN[8]

AG1

AG2

AK1

AK2

AL3

AK3
AL2

AL1

AT1

AT2
AT3

AT5

AD5

AE2

AD2

AE5

AD3

AE4

AE1

AD4

AH5

AH1

AU1

AH4

AG4

AD1

AH3
AP4

AN4

AP5

AP2

AP1

AP3
AN1

AN3

AT4

AH2

AN2

AU4

AE3

AU2

AU3

AG3

AU5

BR5

BL3

BG3

BD3
AB3

V3

R3

M3

BP5

BK3

BF3

BC3
AA3

U3

P3

L3

AY3

BA3

M_A_DDRCLK0_2400M

-M_A_DDRCLK0_2400M

-M_A_DDRCLK1_2400M

M_A_DDRCLK1_2400M

M_A_DDRCLK2_2400M

-M_A_DDRCLK2_2400M

M_A_DDRCLK3_2400M

-M_A_DDRCLK3_2400M

M_A_CKE0

M_A_CKE1

M_A_CKE2

M_A_CKE3

-M_A_CS0

-M_A_CS1

-M_A_CS2

-M_A_CS3

M_A_ODT0

M_A_ODT1

M_A_ODT2

M_A_ODT3

M_A_BA0

M_A_BA1
M_A_BG0

M_A_A16_RAS_N

M_A_A14_WE_N
M_A_A15_CAS_N

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6
M_A_A7

M_A_A8

M_A_A9

M_A_A10_AP

M_A_A11

M_A_A12

M_A_A13

M_A_BG1

-M_A_ACT

M_A_PARITY

-M_A_ALERT

-M_A_DQS0

-M_A_DQS1

-M_A_DQS2

-M_A_DQS3

M_A_DQS4

M_A_DQS5

M_A_DQS6

M_A_DQS7

M_A_DQS0

M_A_DQS1

M_A_DQS2

M_A_DQS3

-M_A_DQS4

-M_A_DQS5

-M_A_DQS6

-M_A_DQS7

M_A_DQS8

-M_A_DQS8

M_A_DDRCLK0_2400M <27>

-M_A_DDRCLK0_2400M <27>

-M_A_DDRCLK1_2400M <27>

M_A_DDRCLK1_2400M <27>

M_A_DDRCLK2_2400M <28>

-M_A_DDRCLK2_2400M <28>

M_A_DDRCLK3_2400M <28>

-M_A_DDRCLK3_2400M <28>

M_A_CKE0 <27>

M_A_CKE1 <27>

M_A_CKE2 <28>
M_A_CKE3 <28>

-M_A_CS0 <27>

-M_A_CS1 <27>

-M_A_CS2 <28>

-M_A_CS3 <28>

M_A_ODT0 <27>

M_A_ODT1 <27>

M_A_ODT2 <28>

M_A_ODT3 <28>

M_A_BA0 <27,28>

M_A_BA1 <27,28>

M_A_BG0 <27,28>

M_A_A16_RAS_N <27,28>

M_A_A14_WE_N <27,28>

M_A_A15_CAS_N <27,28>

M_A_A10_AP <27,28>

M_A_A11 <27,28>

M_A_A12 <27,28>

M_A_A13 <27,28>
M_A_BG1 <27,28>

-M_A_ACT <27,28>

M_A_PARITY <27,28>

-M_A_ALERT <27,28>

-M_A_DQS[0..7] <27,28>

M_A_DQS[0..7] <27,28>

M_A_DQS8 <27,28>

-M_A_DQS8 <27,28>

M_A_A[0..9] <27,28>

D

C

B

DDR CHANNEL
A

SKYLAKE-H-CPU_BGA1440

@

A

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Issued Date

Issued Date

1 OF 14

DDR4 INTERLEAVE IMPLEMENTATION

Title

Title

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

2015/07/16

2015/07/16

2015/07/16

3

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : DDR4 CH-A

CPU SKL-H : DDR4 CH-A

CPU SKL-H : DDR4 CH-A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

!"#$%&'

!"#$%&'

!"#$%&'

1

of

of

of

3 116

3 116

3 116

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

D

M_B_DQ[0..63]<29,30>

C

B

M_B_CB0<29,30>

M_B_CB1<29,30>

M_B_CB2<29,30>

M_B_CB3<29,30>

M_B_CB4<29,30>

M_B_CB5<29,30>

M_B_CB6<29,30>

M_B_CB7<29,30>

1

2

R543 121_0402_1%

2

R544 75_0402_1%

R545 100_0402_1%

1

2

1

PLACE CLOSE TO CPU

M_B_DQ0

M_B_DQ1

M_B_DQ2

M_B_DQ3

M_B_DQ4
M_B_DQ5
M_B_DQ6

M_B_DQ7

M_B_DQ8
M_B_DQ9

M_B_DQ10
M_B_DQ11

M_B_DQ12

M_B_DQ13
M_B_DQ14

M_B_DQ15

M_B_DQ16

M_B_DQ17

M_B_DQ18

M_B_DQ19

M_B_DQ20

M_B_DQ21
M_B_DQ22

M_B_DQ23

M_B_DQ24
M_B_DQ25

M_B_DQ26

M_B_DQ27

M_B_DQ28

M_B_DQ29

M_B_DQ30

M_B_DQ31

M_B_DQ32

M_B_DQ33

M_B_DQ34

M_B_DQ35

M_B_DQ36

M_B_DQ37
M_B_DQ38

M_B_DQ39

M_B_DQ40

M_B_DQ41
M_B_DQ42

M_B_DQ43

M_B_DQ44

M_B_DQ45

M_B_DQ46

M_B_DQ47

M_B_DQ48

M_B_DQ49

M_B_DQ50

M_B_DQ51

M_B_DQ52

M_B_DQ53

M_B_DQ54

M_B_DQ55

M_B_DQ56

M_B_DQ57

M_B_DQ58
M_B_DQ59

M_B_DQ60

M_B_DQ61

M_B_DQ62

M_B_DQ63

M_B_CB0

M_B_CB1

M_B_CB2

M_B_CB3

M_B_CB4

M_B_CB5

M_B_CB6
M_B_CB7

DDR_RCOMP0

DDR_RCOMP1

DDR_RCOMP2

U1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKYLAKE-H-CPU_BGA1440

@

DDR CHANNEL B

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0]

DDR1_CKN[0]

DDR1_CKN[1]

DDR1_CKP[1]

DDR1_CLKP[2]
DDR1_CLKN[2]

DDR1_CLKP[3]

DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1]

DDR1_CS#[2]

DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]
DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3]

DDR1_MA[4]

DDR1_ALERT#

DDR1_DQSN[6]

DDR1_DQSN[7]

DDR1_DQSP[6]

DDR1_DQSP[7]

DDR1_DQSP[8]

DDR1_DQSN[8]

DDR_VREF_CA

DDR0_VREF_DQ

DDR1_VREF_DQ

DDR1_PAR

AM9

AN9

AM8

AM7

AM11
AM10

AJ10

AJ11

AT8

AT10

AT7

AT11

AF11

AE7

AF10

AE10

AF7

AE8
AE9

AE11

AH10

AH11

AF8

AH8

AH9

AR9

AJ9

AK6

AK5

AL5

AL6

AM6

AN7

AN10

AN8
AR11

AH7

AN11

AR10

AF9

AR7

AT9

AJ7

AR8

BP9

BL9

BG9
BC9

AC9

W9

R9

M9

BR9

BJ9

BF9

BB9

AA9

V9

P9

L9

AW9

AY9

BN13

BP13

BR13

M_B_DDRCLK0_2400M

-M_B_DDRCLK0_2400M

-M_B_DDRCLK1_2400M

M_B_DDRCLK1_2400M

M_B_DDRCLK2_2400M

-M_B_DDRCLK2_2400M

M_B_DDRCLK3_2400M

-M_B_DDRCLK3_2400M

M_B_CKE0

M_B_CKE1

M_B_CKE2

M_B_CKE3

-M_B_CS0

-M_B_CS1

-M_B_CS2

-M_B_CS3

M_B_ODT0

M_B_ODT1

M_B_ODT2

M_B_ODT3

M_B_A16_RAS_N

M_B_A14_WE_N

M_B_A15_CAS_N

M_B_BA0

M_B_BA1
M_B_BG0

M_B_A0

M_B_A1

M_B_A2

M_B_A3
M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8
M_B_A9

M_B_A10_AP

M_B_A11

M_B_A12
M_B_A13

M_B_BG1

-M_B_ACT

M_B_PARITY

-M_B_ALERT

-M_B_DQS0

-M_B_DQS1

-M_B_DQS2

-M_B_DQS3

-M_B_DQS4

-M_B_DQS5

-M_B_DQS6

-M_B_DQS7

M_B_DQS0

M_B_DQS1

M_B_DQS2

M_B_DQS3

M_B_DQS4

M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_DQS8

-M_B_DQS8

M_A_VREF_CA_CPU

M_B_VREF_DQ_CPU

DDR_VREF_CA : Connected to VREF_CA on DIMM CH-A
DDR0_VREF_DQ : NC
DDR1_VREF_DQ : Connected to VREF_CA on DIMM CH-B

M_B_DDRCLK0_2400M <29>

-M_B_DDRCLK0_2400M <29>

-M_B_DDRCLK1_2400M <29>

M_B_DDRCLK1_2400M <29>

M_B_DDRCLK2_2400M <30>

-M_B_DDRCLK2_2400M <30>

M_B_DDRCLK3_2400M <30>

-M_B_DDRCLK3_2400M <30>

M_B_CKE0 <29>

M_B_CKE1 <29>

M_B_CKE2 <30>

M_B_CKE3 <30>

-M_B_CS0 <29>

-M_B_CS1 <29>

-M_B_CS2 <30>

-M_B_CS3 <30>

M_B_ODT0 <29>

M_B_ODT1 <29>

M_B_ODT2 <30>

M_B_ODT3 <30>

M_B_A16_RAS_N <29,30>

M_B_A14_WE_N <29,30>

M_B_A15_CAS_N <29,30>

M_B_BA0 <29,30>

M_B_BA1 <29,30>

M_B_BG0 <29,30>

M_B_A10_AP <29,30>

M_B_A11 <29,30>

M_B_A12 <29,30>

M_B_A13 <29,30>

M_B_BG1 <29,30>

-M_B_ACT <29,30>

M_B_PARITY <29,30>

-M_B_ALERT <29,30>

M_B_DQS8 <29,30>

-M_B_DQS8 <29,30>

M_A_VREF_CA_CPU <27>

M_B_VREF_DQ_CPU <29>

M_B_A[0..9] <29,30>

-M_B_DQS[0..7] <29,30>

M_B_DQS[0..7] <29,30>

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : DDR4 CH-B

CPU SKL-H : DDR4 CH-B

CPU SKL-H : DDR4 CH-B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

!"#$%&'

!"#$%&'

!"#$%&'

1

of

of

4 116

4 116

4 116

A

0.1

0.1

0.1

5

Walter Unique

4

3

2

1

D

PEG_RXP[15:0]<31>

PEG_RXN[15:0]<31>

PEG_RXP15

PEG_RXN15

PEG_RXP14

PEG_RXN14

PEG_RXP13

PEG_RXN13

PEG_RXP12

PEG_RXN12

PEG_RXP11

PEG_RXN11

PEG_RXP10

PEG_RXN10

PEG_RXP9

C

VCCCPUIO

B

PEG_RXP8

PEG_RXP7

PEG_RXP6

PEG_RXP5

PEG_RXP4

PEG_RXP3

PEG_RXP2

PEG_RXP1

PEG_RXP0

DMI_TXP0<15>

DMI_TXN0<15>

DMI_TXP1<15>

DMI_TXN1<15>

DMI_TXP2<15>

DMI_TXN2<15>

DMI_TXP3<15>

DMI_TXN3<15>

PEG_RXN9

PEG_RXN8

PEG_RXN7

PEG_RXN6

PEG_RXN5

PEG_RXN4

PEG_RXN3

PEG_RXN2

PEG_RXN1

PEG_RXN0

R1

1

24.9_0402_1%

2

PEG_COMP_W12mil

DMI_TXP0
DMI_TXN0

DMI_TXP1

DMI_TXN1

DMI_TXP2

DMI_TXN2

DMI_TXP3
DMI_TXN3

U1C

E25

D25

E24

F24

E23

D23

E22

F22

E21

D21

E20

F20

E19

D19

E18

F18

D17

E17

F16

E16

D15

E15

F14

E14

D13

E13

F12

E12

D11

E11

F10

E10

G2

D8

E8

E6

F6

D5

E5

J8

J9

SKYLAKE-H-CPU_BGA1440

@

PEG_RXP[0]

PEG_RXN[0]

PEG_RXP[1]

PEG_RXN[1]

PEG_RXP[2]

PEG_RXN[2]

PEG_RXP[3]

PEG_RXN[3]

PEG_RXP[4]

PEG_RXN[4]

PEG_RXP[5]

PEG_RXN[5]

PEG_RXP[6]

PEG_RXN[6]

PEG_RXP[7]

PEG_RXN[7]

PEG_RXP[8]

PEG_RXN[8]

PEG_RXP[9]

PEG_RXN[9]

PEG_RXP[10]
PEG_RXN[10]

PEG_RXP[11]

PEG_RXN[11]

PEG_RXP[12]

PEG_RXN[12]

PEG_RXP[13]

PEG_RXN[13]

PEG_RXP[14]

PEG_RXN[14]

PEG_RXP[15]

PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0]

DMI_RXN[0]

DMI_RXP[1]

DMI_RXN[1]

DMI_RXP[2]

DMI_RXN[2]

DMI_RXP[3]

DMI_RXN[3]

SKYLAKE_HALO

BGA1440

3 OF 14

PEG_TXP[0]

PEG_TXN[0]

PEG_TXP[1]

PEG_TXN[1]

PEG_TXP[2]

PEG_TXN[2]

PEG_TXP[3]

PEG_TXN[3]

PEG_TXP[4]

PEG_TXN[4]

PEG_TXP[5]

PEG_TXN[5]

PEG_TXP[6]

PEG_TXN[6]

PEG_TXP[7]

PEG_TXN[7]

PEG_TXP[8]

PEG_TXN[8]

PEG_TXP[9]

PEG_TXN[9]

PEG_TXP[10]

PEG_TXN[10]

PEG_TXP[11]

PEG_TXN[11]

PEG_TXP[12]

PEG_TXN[12]

PEG_TXP[13]

PEG_TXN[13]

PEG_TXP[14]

PEG_TXN[14]

PEG_TXP[15]

PEG_TXN[15]

DMI_TXP[0]

DMI_TXN[0]

DMI_TXP[1]

DMI_TXN[1]

DMI_TXP[2]

DMI_TXN[2]

DMI_TXP[3]

DMI_TXN[3]

1

2

B25

PEG_TXP15_C

A25

PEG_TXN15_C

B24

PEG_TXP14_C

C24

B23

PEG_TXP13_C

A23

PEG_TXN13_C

B22

PEG_TXP12_C

C22

PEG_TXN12_C

B21

PEG_TXP11_C

A21

PEG_TXN11_C

B20

PEG_TXP10_C

C20

PEG_TXN10_C

B19

PEG_TXP9_C

A19

PEG_TXN9_C PEG_TXN9

B18

PEG_TXP8_C

C18

PEG_TXN8_C

A17

PEG_TXP7_C

B17

PEG_TXN7_C

C16

PEG_TXP6_C

B16

A15

PEG_TXP5_C

B15

PEG_TXN5_C

C14

PEG_TXP4_C

B14

PEG_TXN4_C

A13

PEG_TXP3_C

B13

PEG_TXN3_C

C12

PEG_TXP2_C

B12

PEG_TXN2_C

A11

PEG_TXP1_C

B11

PEG_TXN1_C

C10

PEG_TXP0_C

B10

PEG_TXN0_C

B8

A8

C6

B6

B5

A5

D4

B4

C2004 0.22U_0201_6.3V6-K

1

C9071 0.22U_0201_6.3V6-K

1

C2003 0.22U_0201_6.3V6-K

1

C9070 0.22U_0201_6.3V6-K

1

C9044 0.22U_0201_6.3V6-K

1

C9069 0.22U_0201_6.3V6-K

C9045 0.22U_0201_6.3V6-K

C9068 0.22U_0201_6.3V6-K

1

C9046 0.22U_0201_6.3V6-K

C9104 0.22U_0201_6.3V6-K

1

C9047 0.22U_0201_6.3V6-K

1

C9066 0.22U_0201_6.3V6-K

1

C9048 0.22U_0201_6.3V6-K

1

C9065 0.22U_0201_6.3V6-K

1

C9049 0.22U_0201_6.3V6-K

1

C9064 0.22U_0201_6.3V6-K

1 2

C9050 0.22U_0201_6.3V6-K

C9063 0.22U_0201_6.3V6-K

1

C9051 0.22U_0201_6.3V6-K

1

C9062 0.22U_0201_6.3V6-K

1

C9052 0.22U_0201_6.3V6-K

1

C9061 0.22U_0201_6.3V6-K

1

C9053 0.22U_0201_6.3V6-K

1

C9060 0.22U_0201_6.3V6-K

1

C9054 0.22U_0201_6.3V6-K

C9059 0.22U_0201_6.3V6-K

1 2

C9055 0.22U_0201_6.3V6-K

1

C9058 0.22U_0201_6.3V6-K

1

C9042 0.22U_0201_6.3V6-K

1

C9057 0.22U_0201_6.3V6-K

1

C9043 0.22U_0201_6.3V6-K

1

C9056 0.22U_0201_6.3V6-K

DMI_RXP0

DMI_RXN0

DMI_RXP1
DMI_RXN1

DMI_RXP2

DMI_RXN2

DMI_RXP3

DMI_RXN3

1

1

1 2

1

1 2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2
2

2

2

2

2

2

2

2

2

2
2

PEG_TXP[15:0] <31>

PEG_TXN[15:0] <31>

DMI_RXP0 <15>

DMI_RXN0 <15>

DMI_RXP1 <15>

DMI_RXN1 <15>

DMI_RXP2 <15>

DMI_RXN2 <15>

DMI_RXP3 <15>

DMI_RXN3 <15>

PEG_TXP15

PEG_TXN15

PEG_TXP14

PEG_TXN14PEG_TXN14_C

PEG_TXP13

PEG_TXN13

PEG_TXP12

PEG_TXN12

PEG_TXP11

PEG_TXN11

PEG_TXP10

PEG_TXN10

PEG_TXP9

PEG_TXP8

PEG_TXN8

PEG_TXP7

PEG_TXN7

PEG_TXP6

PEG_TXN6PEG_TXN6_C

PEG_TXP5

PEG_TXN5

PEG_TXP4

PEG_TXN4

PEG_TXP3

PEG_TXN3

PEG_TXP2

PEG_TXN2

PEG_TXP1

PEG_TXN1

PEG_TXP0

PEG_TXN0

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : PEG/DMI

CPU SKL-H : PEG/DMI

CPU SKL-H : PEG/DMI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

!"#$%&'

!"#$%&'

!"#$%&'

1

of

of

of

5 116

5 116

5 116

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

D

U1D

K36

DDI1_TXP[0]

K37

DDI1_TXN[0]

J35

DDI1_TXP[1]

J34

DDI1_TXN[1]

DP

C

3/1 Remove IGPU DP ports

TBT

B

H37

DDI1_TXP[2]

H36

DDI1_TXN[2]

J37

DDI1_TXP[3]

J38

DDI1_TXN[3]

D27

DDI1_AUXP

E27

DDI1_AUXN

H34

DDI2_TXP[0]

H33

DDI2_TXN[0]

F37

DDI2_TXP[1]

G38

DDI2_TXN[1]

F34

DDI2_TXP[2]

F35

DDI2_TXN[2]

E37

DDI2_TXP[3]

E36

DDI2_TXN[3]

F26

DDI2_AUXP

E26

DDI2_AUXN

C34

DDI3_TXP[0]

D34

DDI3_TXN[0]

B36

DDI3_TXP[1]

B34

DDI3_TXN[1]

F33

DDI3_TXP[2]

E33

DDI3_TXN[2]

C33

DDI3_TXP[3]

B33

DDI3_TXN[3]

A27

DDI3_AUXP

B27

DDI3_AUXN

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

BGA1440

4 OF 14

EDP_TXP[0]

EDP_TXN[0]

EDP_TXP[1]

EDP_TXN[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXP

EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

D29

EDP_TXP0_I

E29

EDP_TXN0_I

F28

EDP_TXP1_I

E28

EDP_TXN1_I

B29

EDP_TXN2_I

A29

EDP_TXP2_I

B28

EDP_TXN3_I

C28

EDP_TXP3_I

C26

EDP_AUXP_I

B26

EDP_AUXN_I

A33

Leave EDP_DISP_UTIL NC

D37

EDP_RCOMP_W12mil

Need to confirm
we required these signals for PY/WLT

G27

PROC_AUDIO_CLK_CPU

G25

PROC_AUDIO_SDO_CPU

G29

PROC_AUDIO_SDI_CPU_R

EDP_TXP0_I <41>

EDP_TXN0_I <41>

EDP_TXP1_I <41>

EDP_TXN1_I <41>

EDP_TXN2_I <41>
EDP_TXP2_I <41>

EDP_TXN3_I <41>

EDP_TXP3_I <41>

EDP_AUXP_I <41>

EDP_AUXN_I <41>

1

Place near CPU.

Need create 5% P/N

2

R320_0402_5%

VCCCPUIO

1

2

PROC_AUDIO_CLK_CPU <17>

PROC_AUDIO_SDO_CPU <17>

PROC_AUDIO_SDI_CPU <17>

2

R9989

@

0_0402_5%

1

1

2

EMI

C9355

@

0.1U_0402_10V6-K

R2

24.9_0402_1%

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : DDI/EDP

CPU SKL-H : DDI/EDP

CPU SKL-H : DDI/EDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

!"#$%&'

!"#$%&'

!"#$%&'

1

of

of

of

6 116

6 116

6 116

A

0.1

0.1

0.1

5

Payton Common

4

3

2

VCCST

1

VCCSTG

R8
1K_0402_1%

@

1

R4
56_0402_1%

2

CFG3 <24>

2

51_0402_1%
R297

1

VCC3M

2

D

VCC1R2A

C

1

1

2

3

2

1

@

PROCPWRGD From PCH to CPU
RESET# From PCH to CPU

VCC3B

@

DDR_PG_CTRL

2

R774
100K_0402_5%

@

1

DDR_VTT_PG_CTRL

1

2

VCC1R2A

5

0.1U_0402_16V7-K

U36

P

NC

4

Y

A

G

SN74AUP1G07DCKR SC70

3

C709

1 2

R659
100K_0402_5%

Q55
DTC115TMT2L_VMT3

R77
10K_0402_5%

6/29 Follow windu schematic

-SVID_ALERT<91>

SVID_CLK<91>

SVID_DATA<91>

-PROCHOT<76,91>

PROCPWRGD_CPU<17>

-PCH_PLTRST_PROC<16>

PM_SYNC<16>

PM_DOWN<16>

PECI<16,76>

-THERMTRIP<16>

DDR_VTT_PG_CTRL <99>

CPU_BCLK_100M<20>

-CPU_BCLK_100M<20>

CPU_PCI_BCLK_100M<20>

-CPU_PCI_BCLK_100M<20>

CPU_REFCLK_24M<20>

-CPU_REFCLK_24M<20>

-SVID_ALERT

SVID_CLK

SVID_DATA

-PROCHOT

DDR_PG_CTRL

VCCST_PWRGD

PROCPWRGD_CPU

VCCST

2

R78 10K_0402_5%

NEED TO CONFIRM

1

R14 220_0402_1%

R772 0_0402_5%

R773 0_0402_5%

R15 499_0402_1%

Follow CRB schematic 2016/3/9

R586 60.4_0402_1%

R16 0_0402_5%

1

2

1

2

1

2

1

2

1

2

1

2

U1E

B31

BCLKP

A32

BCLKN

D35

PCI_BCLKP

C36

PCI_BCLKN

E31

CLK24P

D31

CLK24N

BH31

VIDALERT#

BH32

VIDSCK

BH29

VIDSOUT

BR30

PROCHOT#

BT13

DDR_VTT_CNTL

H13

VCCST_PWRGD

BT31

PROCPWRGD

BP35

RESET#

BM34

PM_SYNC

BP31

PM_DOWN

BT34

PECI

J31

THERMTRIP#

BR33

SKTOCC#

BN1

PROC_SELECT#

BM30

CATERR#

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

BGA1440

5 OF 14

CFG[0]

CFG[1]

CFG[2]

CFG[3]
CFG[4]

CFG[5]
CFG[6]

CFG[7]

CFG[8]

CFG[9]

CFG[10]

CFG[11]

CFG[12]

CFG[13]

CFG[14]

CFG[15]

CFG[17]

CFG[16]

CFG[19]

CFG[18]

BPM#[0]

BPM#[1]

BPM#[2]

BPM#[3]

PROC_TDO

PROC_TDI

PROC_TMS

PROC_TCK

PROC_TRST#

PROC_PREQ#

PROC_PRDY#

CFG_RCOMP

BN25

BN27

BN26

BN28
BR20

BM20

BT20

BP20

BR23

BR22

BT23

BT22

BM19

BR19

BP19

BT19

BN23

BP23

BP22

BN22

BR27

BT27

BM31

BT30

BT28

BL32

BP28

BR28

BP30

BL30

BP27

BT25

CFG0

CFG2

CFG3

CFG4

CFG7

IST_TRIG

CFG_RCOMP

49.9_0402_1%

-SVID_ALERT

SVID_CLK

SVID_DATA

-PROCHOT

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

R17

Follow DCI Schematic 6/23

1

TP53Test_Point_32MIL

TP993Test_Point_32MIL

TP994Test_Point_32MIL

TP37Test_Point_32MIL

TP38Test_Point_32MIL

TP39Test_Point_32MIL

TP40Test_Point_32MIL

1

TP41Test_Point_32MIL

TP42Test_Point_32MIL

TP43Test_Point_32MIL

TP44Test_Point_32MIL

2

TP45Test_Point_32MIL

TP46Test_Point_32MIL

TP47Test_Point_32MIL

TP48Test_Point_32MIL

TP49 Test_Point_32MIL

TP50 Test_Point_32MIL

TP51 Test_Point_32MIL
TP52 Test_Point_32MIL

2

R18
51_0402_1%

1

XDP_TDO <24>

XDP_TDI <24>

XDP_TMS <24>

XDP_TCK <24>

-XDP_TRST <24>

-XDP_PREQ <24>

-XDP_PRDY <24>

@

1

R5

@

100_0402_1%

2

1

1K_0402_5%
R11

2

Walter Only

1

R6
100_0402_1%

2

1

R12
1K_0402_1%

2

2

R7
1K_0402_1%

1

1

R13
1K_0402_1%

@

2

D

C

6/27 VCC1R0_SUS change to VCCST and change to 10ohm

VCC3_SUS

B

CPUCORE_ON<84,91>

VCCST_PWRGD requirements (546884_SKL_H_PDG_Rev0_71)

1) Indication that the VCCST/VDDQ power supplies are stable and within specification.
(Table 41-1)

2) VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST.

A

(Figure 41-1 Note 1)

3) VCCST_PWRGD should be equal or ealier than PCH_PWROK.
(Table 41-5, tCPU16. See also 543016_SKL_PDG_UY_1_0)

4) VCCST_PWRGD is typically made from ALL_SYS_PWRGD
(CPUCORE_ON/VR_ON for CPU DCDC), not PCH_PWROK (CPUCORE_PWRGD).
(Figure 41-1)

CPUCORE_ON

5

2

R19
10K_0402_5%

1

1

D

2

G

Q1
LSK3541G1ET2L_VMT3

S

3

VCC1R0_SUS

1

2

@

VCCST

1

R10095

1K_0402_5%

2

1

D

2

G

S

3

4

If VCCSTG is used instead of VCC1R0_SYS,
VCCST_PWRGD will be off in Sleep S0 because
VCCSTG may be turned off when in Sleep S0.
Currently, VCCSTG is still on in Sleep S0
but we may change logic to turn off VCCSTG in sleep S0.

R20

(CT_20141216)

1K_0402_5%

Q2
LSK3541G1ET2L_VMT3

VCCST_PWRGD

TABLE

CFG[19:0] pin has internal Pull up to VCCCPUIO with 5-8 k ohm.

CFG[0] : Stall reset sequence after CPU PLL lock until de-asserted:
1 : No Stall
0 : Stall

CFG[2] : PEG Static Lane Reversal
1 : Normal Operation
0 : Lane Reversal

CFG[4] : eDP enable
1 : Disabled
0 : Enabled

CFG[6:5] : PEG Bifurcation, bus#:dev#:func#=0:1:0
11 : 1x16

CFG[7] : PEG Training
1 : PEG Train immediately following RESET# deassertion
0 : PEG Wait for BIOS for training

<----------- LOGIC

<----------- LOGIC

<----------- LOGIC

<----------- LOGIC

CFG[19:8] : Reserved

For x16 Reversal Lanes - CFG[6/5/2] setting is 110
For x4 Reversal Lanes - CFG[6/5/2] setting is 000

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

<----------- LOGIC

Title

Title

Title

CPU SKL-H : MISC/CLK/JTAG/CFG

CPU SKL-H : MISC/CLK/JTAG/CFG

CPU SKL-H : MISC/CLK/JTAG/CFG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

!"#$%&'

!"#$%&'

!"#$%&'

1

of

of

of

7 116

7 116

7 116

B

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

SKYLAKE_HALO

D

C

B

U1F

Y38

VSS_1

Y37

VSS_2

Y14

VSS_3

Y13

VSS_4

Y11

VSS_5

Y10

VSS_6

Y9

VSS_7

Y8

VSS_8

Y7

VSS_9

W34

VSS_10

W33

VSS_11

W12

VSS_12

W5

VSS_13

W4

VSS_14

W3

VSS_15

W2

VSS_16

W1

VSS_17

V30

VSS_18

V29

VSS_19

V12

VSS_20

V6

VSS_21

U38

VSS_153

U37

VSS_22

U6

VSS_23

T34

VSS_24

T33

VSS_25

T14

VSS_26

T13

VSS_27

T12

VSS_28

T11

VSS_29

T10

VSS_30

T9

VSS_31

T8

VSS_32

T7

VSS_33

T5

VSS_34

T4

VSS_35

T3

VSS_36

T2

VSS_37

T1

VSS_38

R30

VSS_39

R29

VSS_40

R12

VSS_41

P38

VSS_42

P37

VSS_43

P12

VSS_44

P6

VSS_45

N34

VSS_46

N33

VSS_47

N12

VSS_48

N11

VSS_49

N10

VSS_50

N9

VSS_51

N8

VSS_52

N7

VSS_53

N6

VSS_54

N5

VSS_55

N4

VSS_56

N3

VSS_57

N2

VSS_58

N1

VSS_59

M14

VSS_60

M13

VSS_61

M12

VSS_62

M6

VSS_63

L34

VSS_64

L33

VSS_65

L30

VSS_66

L29

VSS_67

K38

VSS_68

K11

VSS_69

K10

VSS_70

K9

VSS_71

K8

VSS_72

K7

VSS_73

K5

VSS_74

K4

VSS_75

K3

VSS_76

K2

VSS_77

SKYLAKE-H-CPU_BGA1440

@

BGA1440

6 OF 14

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

NCTFVSS_1

K1

J36

J33

J32

J25

J22

J18

J10

J7

J4

H35

H32

H25

H22

H18

H12

H11

G28

G26

G24

G23

G22

G20

G18

G16

G14

G12

G10

G9

G8

G6

G5

G4

F36

F31

F29

F27

F25

F23

F21

F19

F17

F15

F13

F11

F9

F8

F5

F4

F3

F2

E38

E35

E34

E9

E4

D33

D30

D28

D26

D24

D22

D20

D18

D16

D14

D12

D10

D9

D6

D3

C37

C31

C29

C27

D38

1

TP958

Test_Point_20MIL

C17

C13

BT32

BT26

BT24

BT21

BT18

BT14

BT12

BT9

BT5

BR36

BR34
BR29

BR26

BR24

BR21

BR18

BR14

BR12

BR7

BP34

BP33

BP29

BP26

BP24

BP21

BP18

BP14

BP12

BP7

BN34

BN31
BN30

BN29

BN24

BN21
BN20

BN19

BN18

BN14

BN12

BN9

BN7

BN4

BN2

BM38

BM35

BM28

BM27

BM26

BM23
BM21

BM13

BM12

BM9

BM6

BM2

BL29

BK29

BK15

BK14

BJ32

BJ31

BJ25

BJ22

BH14

BH12

BH9

BH8

BH5

BH4

BH1

BG38

BG13

BG12

BF33

BF12

BE29

BE6

BD9

BC34

BC12

BB12

C9

SKYLAKE_HALO

U1L

SKYLAKE-H-CPU_BGA1440

@

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167
VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175
VSS_176
VSS_177

VSS_178

VSS_179

VSS_180

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185
VSS_186

VSS_187
VSS_188

VSS_189

VSS_190

VSS_191
VSS_192

VSS_193

VSS_194

VSS_195

VSS_196

VSS_197

VSS_198

VSS_199

VSS_200

VSS_201

VSS_202

VSS_203

VSS_204

VSS_205

VSS_206
VSS_207

VSS_208

VSS_209

VSS_210

VSS_211

VSS_212

VSS_213

VSS_214

VSS_215

VSS_216
VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236

VSS_237

VSS_238

BGA1440

12 OF 14

VSS_239

VSS_240

VSS_241

VSS_242

VSS_243

VSS_244

VSS_245

VSS_246

VSS_247

VSS_248

VSS_249

VSS_250

VSS_251

VSS_252

VSS_253
VSS_254
VSS_255

VSS_256

VSS_257

VSS_258

VSS_259

VSS_260

VSS_261

VSS_262

VSS_263

VSS_264

VSS_265

VSS_266

VSS_267

VSS_268
VSS_269

VSS_270

VSS_271

VSS_272

VSS_273

VSS_274
VSS_275

VSS_276

VSS_277

VSS_278

VSS_279

VSS_280
VSS_281

VSS_282

VSS_283

VSS_284

VSS_285

VSS_286
VSS_287

VSS_288

VSS_289
VSS_290
VSS_291

VSS_292

VSS_293

VSS_294

VSS_295

VSS_296

VSS_297

VSS_298

VSS_299

NCTFVSS_2

NCTFVSS_3

NCTFVSS_4

NCTFVSS_5

NCTFVSS_6
NCTFVSS_7

C25

C23

C21

C19

C15

C11

C8

C5

BM29

BM25

BM18

BM11

BM8

BM7

BM5

BM3
BL38

BL35

BL13

BL6

BK25

BK22

BK13

BK6

BJ30

BJ29

BJ15

BJ12

BH11

BH10
BH7

BH6

BH3

BH2

BG37

BG14
BG6

BF34

BF6

BE30

BE5

BE4
BE3

BE2

BE1

BD38

BD37

BD12
BD11

BD10

BD8

BD7

BD6

BC33

BC14

BC13

BC6

BB30

BB29

BB6

BB5

C2

BT36

BT35

BT4

BT3
BR38

1

TP959 Test_Point_20MIL

1

TP960 Test_Point_20MIL

1

TP961 Test_Point_20MIL

1

TP962 Test_Point_20MIL

U1M

BB4

VSS_300

BB3

VSS_301

BB2

VSS_302

BB1

VSS_303

BA38

VSS_304

BA37

VSS_305

BA12

VSS_306

BA11

VSS_307

BA10

VSS_308

BA9

VSS_309

BA8

VSS_310

BA7

VSS_311

BA6

VSS_312

B9

VSS_313

AY34

VSS_314

AY33

VSS_315

AY14

VSS_316

AY12

VSS_317

AW30

VSS_318

AW29

VSS_319

AW12

VSS_320

AW5

VSS_321

AW4

VSS_322

AW3

VSS_323

AW2

VSS_324

AW1

VSS_325

AV38

VSS_326

AV37

VSS_327

AU34

VSS_328

AU33

VSS_329

AU12

VSS_330

AU11

VSS_331

AU10

VSS_332

AU9

VSS_333

AU8

VSS_334

AU7

VSS_335

AU6

VSS_336

AT30

VSS_337

AT29

VSS_338

AT6

VSS_339

AR38

VSS_340

AR37

VSS_341

AR14

VSS_342

AR13

VSS_343

AR5

VSS_344

AR4

VSS_345

AR3

VSS_346

AR2

VSS_347

AR1

VSS_348

AP34

VSS_349

AP33

VSS_350

AP12

VSS_351

AP11

VSS_352

AP10

VSS_353

AP9

VSS_354

AP8

VSS_355

AN30

VSS_356

AN29

VSS_357

AN12

VSS_358

AN6

VSS_359

AN5

VSS_360

AM38

VSS_361

AM37

VSS_362

AM12

VSS_363

AM5

VSS_364

AM4

VSS_365

AM3

VSS_366

AM2

VSS_367

AM1

VSS_368

AL34

VSS_369

AL33

VSS_370

AL14

VSS_371

AL12

VSS_372

AL10

VSS_373

AL9

VSS_374

AL8

VSS_375

AL7

VSS_376

AL4

VSS_377

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

BGA1440

13 OF 14

VSS_378
VSS_379

VSS_380

VSS_381

VSS_382

VSS_383

VSS_384

VSS_385

VSS_386

VSS_387

VSS_388

VSS_389

VSS_390

VSS_391

VSS_392

VSS_393

VSS_394

VSS_395
VSS_396

VSS_397
VSS_398

VSS_399
VSS_400

VSS_401

VSS_402

VSS_403

VSS_404

VSS_405

VSS_406

VSS_407

VSS_408

VSS_409

VSS_410

VSS_411

VSS_412

VSS_413

VSS_414

VSS_415

VSS_416

VSS_417

VSS_418

VSS_419

VSS_420

VSS_421
VSS_422

VSS_423
VSS_424

VSS_425

VSS_426

VSS_427

VSS_428

VSS_429

VSS_430

VSS_431

VSS_432

VSS_433

VSS_434

VSS_435

VSS_436

VSS_437
VSS_438

VSS_439

VSS_440

VSS_441

VSS_442

VSS_443

VSS_444

VSS_445

VSS_446

NCTFVSS_8

NCTFVSS_9

NCTFVSS_10

NCTFVSS_11

NCTFVSS_12

AK30
AK29

AK4

AJ38

AJ37

AJ6

AJ5

AJ4

AJ3

AJ2

AJ1

AH34

AH33

AH12

AH6

AG30

AG29

AG11
AG10

AG8
AG7

AG6
AF14

AF13

AF12

AF4

AF3

AF2

AF1

AE34

AE33

AE6

AD30

AD29

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AC38

AC37

AC12
AC6

AC5
AC4

AC3

AC2

AC1

AB34

AB33

AB6

AA30

AA29

AA12

A30

A28

A26

A24
A22

A20

A18

A16

A14

A12

A10

A9

A6

B37

B3

A34

A4

TP965 Test_Point_20MIL

A3

1

TP963 Test_Point_20MIL

1

TP964 Test_Point_20MIL

1

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : GND

CPU SKL-H : GND

CPU SKL-H : GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

!"#$%&'

!"#$%&'

!"#$%&'

1

of

of

of

8 116

8 116

8 116

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

D

C

B

VCCCPUCORE

AA13

AA31

AA32

AA33
AA34

AA35

AA36

AA37

AA38

AB29

AB30

AB31

AB32

AB35

AB36

AB37

AB38

AC13

AC14

AC29

AC30

AC31

AC32

AC33

AC34

AC35

AC36

AD13

AD14

AD31

AD32

AD33

AD34

AD35

AD36

AD37

AD38

AE13

AE14

AE30
AE31

AE32

AE35

AE36

AE37

AE38
AF35

AF36

AF37

AF38

N13

N14

N30
N31

N32

N35

N36

N37

N38

SKYLAKE_HALO

U1G

VCC_1

VCC_2

VCC_3

VCC_4
VCC_5

VCC_6

VCC_7

VCC_8

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27
VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40
VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46
VCC_47

VCC_48

VCC_49

VCC_50

K13

VCC_51

K14

VCC_52

L13

VCC_53

VCC_54

VCC_55

VCC_56
VCC_57

VCC_58

VCC_59

VCC_60

VCC_61

VCC_62

P13

VCC_63

SKYLAKE-H-CPU_BGA1440

@

BGA1440

7 OF 14

VCC_64

VCC_65

VCC_66

VCC_67

VCC_68

VCC_69

VCC_70

VCC_71

VCC_72

VCC_73

VCC_74

VCC_75

VCC_76

VCC_77
VCC_78

VCC_79

VCC_80

VCC_81

VCC_82

VCC_83

VCC_84
VCC_85

VCC_86

VCC_87

VCC_88

VCC_89

VCC_90

VCC_91

VCC_92

VCC_93

VCC_94

VCC_95

VCC_96

VCC_97

VCC_98

VCC_99

VCC_100

VCC_101

VCC_102

VCC_103

VCC_104

VCC_105

VCC_106

VCC_107

VCC_108

VCC_109

VCC_110

VCC_111

VCC_112
VCC_113

VCC_114

VCC_115

VCC_116

VCC_117

VCC_118

VCC_119

VCC_120

VCC_121

VCC_122

VCC_123

VCC_124

VCC_125

VCC_126

VCC_SENSE

VSS_SENSE

VCCCPUCORE

V32

V33

V34

V35

V36

V37

V38

W13

W14

W29

W30

W31

W32

W35
W36

W37

W38

Y29

Y30

Y31

Y32

Y33

Y34

Y35

Y36

L14

P29

P30

P31

P32

P33

P34

P35

P36

R13

R31

R32

R33

R34

R35

R36

R37

R38

T29

T30

T31

T32

T35

T36
T37

T38

U29

U30

U31

U32

U33

U34

U35

U36

V13

V14

V31

P14

1

R750 0_0402_5%

AG37

AG38

1

R751 0_0402_5%

VCCCPUCORE

1

100_0402_1%
R21

2

2
2

1

100_0402_1%
R22

2

VCCCORE_SENSE <91>

VSSCORE_SENSE <91>

D

C

B

NEAR PROCESSOR PINS

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : VCC

CPU SKL-H : VCC

CPU SKL-H : VCC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

!"#$%&'

!"#$%&'

!"#$%&'

1

of

of

of

9 116

9 116

9 116

A

0.1

0.1

0.1

5

Walter Unique

VCCGFXCORE_I

4

VCCGFXCORE_I

VCCGFXCORE_I

3

2

1

SKYLAKE_HALO

U1H

D

C

B

BG34

BG35

BG36

BH33
BH34

BH35

BH36

BH37

BH38

BJ37

BJ38

BL36
BL37

BM36

BM37

BN36

BN37

BN38

BP37

BP38
BR37

BT37

BE38

BF13

BF14
BF29

BF30

BF31

BF32

BF35

BF36

BF37

BF38

BG29

BG30

BG31

BG32

BG33

BC36
BC37

BC38

BD13

BD14
BD29

BD30

BD31

BD32

BD33

BD34

BD35

BD36

BE31

BE32

BE37

BGA1440

VCCGT_1

VCCGT_2

VCCGT_3

VCCGT_4
VCCGT_5

VCCGT_6

VCCGT_7

VCCGT_8
VCCGT_9

VCCGT_10

VCCGT_11

VCCGT_12
VCCGT_13

VCCGT_14

VCCGT_15

VCCGT_16

VCCGT_17

VCCGT_18

VCCGT_19

VCCGT_20
VCCGT_21

VCCGT_22

VCCGT_23

VCCGT_24

VCCGT_25
VCCGT_26

VCCGT_27

VCCGT_28

VCCGT_29

VCCGT_30

VCCGT_31

VCCGT_32

VCCGT_33

VCCGT_34

VCCGT_35

VCCGT_36

VCCGT_37

VCCGT_38

VCCGT_39
VCCGT_40

VCCGT_41

VCCGT_42

VCCGT_43
VCCGT_44

VCCGT_45

VCCGT_46

VCCGT_47

VCCGT_48

VCCGT_49

VCCGT_50

VCCGT_51

VCCGT_52

VCCGT_53

VCCGT_54

SKYLAKE-H-CPU_BGA1440

@

8 OF 14

VCCGT_55

VCCGT_56

VCCGT_57

VCCGT_58

VCCGT_59

VCCGT_60

VCCGT_61

VCCGT_62

VCCGT_63

VCCGT_64

VCCGT_65
VCCGT_66

VCCGT_67

VCCGT_68
VCCGT_69

VCCGT_70

VCCGT_71

VCCGT_72

VCCGT_73

VCCGT_74

VCCGT_75

VCCGT_76

VCCGT_77

VCCGT_78

VCCGT_79

VCCGT_80

VCCGT_81

VCCGT_82

VCCGT_83

VCCGT_84

VCCGT_85

VCCGT_86

VCCGT_87

VCCGT_88

VCCGT_89
VCCGT_90

VCCGT_91

VCCGT_92

VCCGT_93

VCCGT_94

VCCGT_95

VCCGT_96

VCCGT_97

VCCGT_98

VCCGT_99

VCCGT_100

VCCGT_101

VCCGT_102

VCCGT_103
VCCGT_104

VCCGT_105
VCCGT_106

VCCGT_107

VCCGT_108

AV29

AV30

AV31

AV32

AV33

AV34

AV35

AV36

AW14

AW31

AW32
AW33

AW34

AW35
AW36

AW37

AW38

AY29

AY30

AY31

AY32

AY35

AY36

AY37

AY38

BA13

BA14

BA29

BA30

BA31

BA32

BA33

BA34

BA35

BA36
BB13

BB14

BB31

BB32

BB33

BB34

BB35

BB36

BB37

BB38

BC29

BC30

BC31

BC32
BC35

BE33
BE34

BE35

BE36

U1N

AJ29

VCCGT_109

AJ30

VCCGT_110

AJ31

VCCGT_111

AJ32

VCCGT_112

AJ33

VCCGT_113

AJ34

VCCGT_114

AJ35

VCCGT_115

AJ36

VCCGT_116

AK31

VCCGT_117

AK32

VCCGT_118

AK33

VCCGT_119

AK34

VCCGT_120

AK35

VCCGT_121

AK36

VCCGT_122

AK37

VCCGT_123

AK38

VCCGT_124

AL13

VCCGT_125

AL29

VCCGT_126

AL30

VCCGT_127

AL31

VCCGT_128

AL32

VCCGT_129

AL35

VCCGT_130

AL36

VCCGT_131

AL37

VCCGT_132

AL38

VCCGT_133

AM13

VCCGT_134

AM14

VCCGT_135

AM29

VCCGT_136

AM30

VCCGT_137

AM31

VCCGT_138

AM32

VCCGT_139

AM33

VCCGT_140

AM34

VCCGT_141

AM35

VCCGT_142

AM36

VCCGT_143

AN13

VCCGT_144

AN14

VCCGT_145

AN31

VCCGT_146

AN32

VCCGT_147

AN33

VCCGT_148

AN34

VCCGT_149

AN35

VCCGT_150

AN36

VCCGT_151

AN37

VCCGT_152

AN38

VCCGT_153

AP13

VCCGT_154

AP14

VCCGT_155

AP29

VCCGT_156

AP30

VCCGT_157

AP31

VCCGT_158

AP32

VCCGT_159

AP35

VCCGT_160

AP36

VCCGT_161

AP37

VCCGT_162

AP38

VCCGT_163

AR29

VCCGT_164

AR30

VCCGT_165

AR31

VCCGT_166

AR32

VCCGT_167

AR33

VCCGT_168

AR34

VCCGT_169

AR35

VCCGT_170

AR36

VCCGT_171

AT14

VCCGT_172

AT31

VCCGT_173

AT32

VCCGT_174

AT33

VCCGT_175

AT34

VCCGT_176

AT35

VCCGT_177

AT36

VCCGT_178

AT37

VCCGT_179

AT38

VCCGT_180

AU14

VCCGT_181

AU29

VCCGT_182

AU30

VCCGT_183

AU31

VCCGT_184

AU32

VCCGT_185

AU35

VCCGT_186

AU36

VCCGT_187

AU37

VCCGT_188

AU38

VCCGT_189

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

BGA1440

14 OF 14

VCCGTX_1

VCCGTX_2

VCCGTX_3
VCCGTX_4

VCCGTX_5

VCCGTX_6

VCCGTX_7

VCCGTX_8

VCCGTX_9

VCCGTX_10
VCCGTX_11

VCCGTX_12

VCCGTX_13

VCCGTX_14

VCCGTX_15

VCCGTX_16
VCCGTX_17

VCCGTX_18

VCCGTX_19

VCCGTX_20

VCCGTX_21
VCCGTX_22

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29

AF30

AF31
AF32

AF33

AF34

AG13

AG14

AG31

AG32

AG33

AG34

AG35

AG36

AH13

AH14
AH29

AH30

AH31

AH32

AJ13
AJ14

AH38

AH35

AH37

AH36

1

R752 0_0402_5%

1

R754 0_0402_5%

2

2

VCCGFXCORE_I

1

100_0402_1%
R23

2

1

100_0402_1%
R24

2

D

C

VCCGT_SENSE <91>

VSSGT_SENSE <91>

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : VCCGT/VCCGTX

CPU SKL-H : VCCGT/VCCGTX

CPU SKL-H : VCCGT/VCCGTX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

!"#$%&'

!"#$%&'

!"#$%&'

1

of

of

of

10 116

10 116

10 116

A

0.1

0.1

0.1

5

Payton Common

4

3

2

VCC1R2A

1

D

1

C759

VCCST

2

22U_0603_6.3V6M

C2

C1

1U_0201_6.3V6-K

RESISTORS CLOSE TO CPU PINS

AA6

AE12
AF5

AF6

AG5

AG9

AJ12

AL11

AP6
AP7

AR12
AR6

AT12

AW6

AY6

J5

J6

K12

K6

L12

L6

R6

T6
W6

Y12

BH13

G11

H30

H29

G30

H28
J28

M38

M37

H14

J14

VCC1R2A

VDDQC : Memory Control Clock Power

VCCPLL_OC : CPU digital PLL power rails

VCC1R2A

1

2

10U_0402_6.3V6-M

VCC1R2A

C252

C122

C177

1U_0201_6.3V6-K

1U_0201_6.3V6-K

2

1

R756 0_0402_5%

1

R757 0_0402_5%

VCCST

2

C4

1U_0201_6.3V6-K

VCCSA

VCCSA_1

VCCSA_2

VCCSA_3
VCCSA_4

VCCSA_5

VCCSA_6

VCCSA_7

VCCSA_8

VCCSA_9

VCCSA_10
VCCSA_11

VCCSA_12

VCCSA_13

VCCSA_14
VCCSA_15

VCCSA_16
VCCSA_17

VCCSA_18

VCCSA_19

VCCSA_20

VCCSA_21

VCCSA_22

VCCIO_1

VCCIO_2

VCCIO_3

VCCIO_4

VCCIO_5

VCCIO_6
VCCIO_7

VCCIO_8

VCCIO_9

VCCIO_10

VCCIO_11

VCCIO_12

VCCIO_13

VCCIO_14
VCCIO_15

VCCIO_16

VCCIO_17

VCCIO_18

VCCIO_19

VCCIO_20

VCCIO_21

SKYLAKE_HALO

BGA1440

9 OF 14

VDDQ_1

VDDQ_2
VDDQ_3

VDDQ_4

VDDQ_5

VDDQ_6

VDDQ_7

VDDQ_8

VDDQ_9

VDDQ_10

VDDQ_11
VDDQ_12

VDDQ_13

VDDQ_14

VDDQ_15

VDDQ_16

VDDQ_17

VDDQ_18

VDDQ_19

VDDQ_20

VDDQ_21

VDDQ_22

VDDQ_23
VDDQ_24

VDDQC

VCCPLL_OC_1

VCCPLL_OC_2

VCCST

VCCSTG_1

VCCSTG_2

VCCPLL_1
VCCPLL_2

VCCSA_SENSE

VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

U1I

J30

K29

K30

K31

K32

K33

K34

K35

L31

L32
L35

L36

L37

L38

M29

M30
M31

M32

C

B

VCCCPUIO

1

2

10U_0402_6.3V6-M

1

1

C289

C379

C380

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

M33

M34

M35

M36

AG12

G15

G17

G19

G21

H15
H16

H17

H19

H20

H21

H26

H27

J15

J16

J17

J19

J20

J21

J26

J27

SKYLAKE-H-CPU_BGA1440

@

1

1

C760

2

22U_0603_6.3V6M

1

2

C761

C762

2

22U_0603_6.3V6M

1

2

22U_0603_6.3V6M

6/20 C759~C766 close to PCU Side

VCCSTG

@

C3

1U_0201_6.3V6-K

1U_0201_6.3V6-K

VCCSA

VCCCPUIO

1

1

R25

2

100_0402_1%

1

R27

2

100_0402_1%

R26

2

100_0402_1%

VCCSA_SENSE <91>

VSSSA_SENSE <91>

VCCCPUIO_SENSE <95>

VSSCPUIO_SENSE <95>

1

R28

2

100_0402_1%

2

C763

C764

1

10U_0402_6.3V

10U_0402_6.3V

C766

C765

1

1

10U_0402_6.3V

10U_0402_6.3V

2

2

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : VCCSA/VCCIO/VDDQ

CPU SKL-H : VCCSA/VCCIO/VDDQ

CPU SKL-H : VCCSA/VCCIO/VDDQ

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

1

of

11 116

of

11 116

of

11 116

A

0.1

0.1

0.1

5

Walter Unique

4

3

2

1

D

C

B

Follow PAYTON schematic 6/27

2

R155 49.9_0402_1%

R156 49.9_0402_1%

R281 49.9_0402_1%

1

1

2

2

1

OPC_RCOMP

OPCE_RCOMP
OPCE_RCOMP2

U1J

BJ17

BJ19

BJ20

BK17

BK19

BK20

BL16

BL17

BL18

BL19

BL20

BL21

BM17

BN17

BJ23

BJ26

BJ27

BK23

BK26

BK27

BL23

BL24

BL25

BL26

BL27

BL28

BM24

BL15

BM16

BL22

BM22

BP15

BR15

BT15

BP16

BR16

BT16

BN15

BM15

BP17

BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13

AY13

BT29

BR25
BP25

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

VCCOPC_1

VCCOPC_2

VCCOPC_3

VCCOPC_4

VCCOPC_5

VCCOPC_6

VCCOPC_7

VCCOPC_8

VCCOPC_9

VCCOPC_10

VCCOPC_11

VCCOPC_12

VCCOPC_13

VCCOPC_14

RSVD_1

RSVD_2

RSVD_3

RSVD_4

RSVD_5

RSVD_6

RSVD_7

RSVD_8

RSVD_9

RSVD_10

RSVD_11

RSVD_12

RSVD_13

VCCOPC_SENSE

VSSOPC_SENSE

RSVD_14

RSVD_15

VCCEOPIO_1

VCCEOPIO_2

VCCEOPIO_3

RSVD_16

RSVD_17

RSVD_18

VCCEOPIO_SENSE
VSSEOPIO_SENSE

RSVD_19

RSVD_20

VCC_OPC_1P8_1

VCC_OPC_1P8_2

RSVD_21

RSVD_22

ZVM#

MSM#

ZVM2#

MSM2#

OPC_RCOMP

OPCE_RCOMP
OPCE_RCOMP2

BGA1440

10 OF 14

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : VCCOPC/RSVD

CPU SKL-H : VCCOPC/RSVD

CPU SKL-H : VCCOPC/RSVD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

of

of

12 116

12 116

of

1

12 116

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

D

U1K

D1

RSVD_TP_1

E1

RSVD_TP_2

E3

RSVD_TP_3

E2

RSVD_TP_4

BR1

RSVD_TP_5

BT2

RSVD_TP_6

BN35

RSVD_23

J24

RSVD_24

H24

C

PCH_2_CPU_TRIGGER<22>

CPU_2_PCH_TRIGGER<22>

B

R590

1

2

30_0402_1%

RSVD_25

BN33

RSVD_26

BL34

RSVD_27

N29

RSVD_28

R14

RSVD_29

AE29

RSVD_30

AA14

RSVD_31

A36

RSVD_32

A37

RSVD_33

H23

PROC_TRIGIN

J23

PROC_TRIGOUT

F30

RSVD_34

E30

RSVD_35

B30

RSVD_36

C30

RSVD_37

G3

RSVD_38

J3

RSVD_39

BR35

RSVD_40

BR31

RSVD_41

BH30

RSVD_42

SKYLAKE-H-CPU_BGA1440

@

SKYLAKE_HALO

BGA1440

11 OF 14

RSVD_TP_7

RSVD_TP_8

RSVD_TP_9

RSVD_TP_10

RSVD_43

RSVD_44

VSS_447

RSVD_TP_11

RSVD_TP_12

RSVD_TP_13

RSVD_TP_14

RSVD_45

RSVD_46

RSVD_47

RSVD_48

VSS_448

RSVD_TP_15
RSVD_TP_16

RSVD_49

RSVD_50

RSVD_51

NCTF_1

NCTF_2

NCTF_3

NCTF_4

NCTF_5
NCTF_6

BM33

BL33

BJ14

BJ13

BK28

BJ28

BJ18

BJ16

BK16

BK24

BJ24

BK21

BJ21

BT17

BR17

BK18

BJ34
BJ33

G13

AJ8

BL31

B2

B38

BP1

TP967 Test_Point_20MIL

BR2

C1

TP966 Test_Point_20MIL

C38

1

1

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

CPU SKL-H : RSVD

CPU SKL-H : RSVD

CPU SKL-H : RSVD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

13 116

of

of

13 116

of

1

13 116

A

0.1

0.1

0.1

5

Payton Common

D

C

SPI_MOSI_IO0<26,82>

SPI_MISO_IO1<26,82>

-SPI_CS0<26>

SPI_CLK<26,82>

SPI_IO2<24,26>

SPI_IO3<26>

-SPI_CS2<82>

DOCKID[3:0]<74>

from Docking Connector

DOOR SWITCH -INTRUDER

B

CLOSE

OPEN

TBT_SNK0_DPHPD<32,46>

TBT_SNK1_DPHPD<32,46>

EXT_DP_HPD<32,43>

VCC3_SUS

2

R10097

@

10K_0402_5%

1

CS0# for SPI ROM, CS2# for dTPM

DOCKID1

DOCKID0

DOCKID3

DOCKID2

OPEN

CLOSE

HIGH

LOW (ACTIVE)

4

D75

2

RB521CS-30GT2RA_VMN2-2

RB521CS-30GT2RA_VMN2-2

RB521CS-30GT2RA_VMN2-2

U3A

BD17

GPP_A11/PME#

AG15

RSVD_1

AG14

RSVD_2

AF17

RSVD_3

AE17

RSVD_4

AR19

TP2

AN17

TP1

BB29

SPI0_MOSI

BE30

SPI0_MISO

BD31

SPI0_CS0#

BC31

SPI0_CLK

AW31

SPI0_CS1#

BC29

SPI0_IO2

BD30

SPI0_IO3

AT31

SPI0_CS2#

AN36

GPP_D1/SPI1_CLK

AL39

GPP_D0/SPI1_CS#

AN41

GPP_D3/SPI1_MOSI

AN38

GPP_D2/SPI1_MISO

AH43

GPP_D22/SPI1_IO3

AG44

GPP_D21/SPI1_IO2

SKYLAKE-H-PCH_FCBGA837

6/27 Tamper switch GPI define on GPP_H18

D76

2

D77

2

TAMPER_SWITCH

2

1

1

1

1

SPT-H_PCH

R10096
0_0402_5%

1 OF 12

SPVR310100_4P

3

1

R830

2

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0

GPP_E7/CPU_GP1

GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

SW1

2

1

3

4

MUX_DP_HPD

100K_0402_5%

-PLTRST

BB27

P43

R39

R36

R42

R41

AF41

SYSTEM_DISPLAY_HPD

AE44

BC23

BD24

BC36

TAMPER_SWITCH

BE34

BD39
BB36

BA35

-GPU_EVENT

R785 0_0402_5%

BC35

BD35

Leave as NC

AW35

BD34

BE11

1

R32 0_0402_5%

1

-INTRUDER

1M_0402_5%

2

U2

1

NC

2

IN_A

3

GND

2

RTCVCC

R31

OUT_Y

TC7SG17FE_SON5

R10158

1

2

@

0_0201_5%

R10045

2

0_0201_5%

1

2

2

C7

1

1000P_0402_25V7-K

2

VCC3M

5

VCC

4

@

100K_0201_5%

1

-EXC_PWR_SHDN <64>

-VGA_DISABLE <34>

GC6_FB_EN <34,111>

-GPU_EVENT <34>

-DGFX_OUTPUT_ENABLE <41>

Need to check target device
position to assign

R29 33_0402_5%

1

2

R30 33_0402_5%

1

1

R10159

2

MUX_DP_HPD

2

VCC3B

1

R10049 10K_0402_5%

1

2

D1
RB520CM-30T2R_VMN2M2

1

1

C5

2

100P_0402_50V8-J

C6

2

100P_0402_50V8-J

to DP Bus Switch

2

to EC

-INTRUDER_EC <77>

1

D

-PLTRST_FAR <24,46,52,56,60,62>

-PLTRST_NEAR <34,61,64,75,82,83,84>

C

-DGFX_OUTPUT_ENABLE

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : SPI

PCH SKL-H : SPI

PCH SKL-H : SPI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

of

14 116

of

14 116

14 116

1

of

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

I/O High Speed Signals Configuration

Port 1 - 6

D

Port 7

Port 8

Port 9

Port 10

Port 11

Port 12

Port 13

Port 14

C

Express Card

B

WLAN Card

GbE

Thunderbolt
x 4

Flexible I/O Configuration (v0.51)

USB3 7 / PCIE 1

USB3 8 / PCIE 2

USB3 9 / PCIE 3

USB3 10 / PCIE 4 (GBE)

PCIE 5 (GBE)

PCIE 6

PCIE 7 PCIE 7

PCIE 8 PCIE 8

PCIE1_EXP_SLOT_RXN<64>

PCIE1_EXP_SLOT_RXP<64>

PCIE1_EXP_SLOT_TXN<64>

PCIE1_EXP_SLOT_TXP<64>

PCIE3_WLAN_SLOT_RXN<61>

PCIE3_WLAN_SLOT_RXP<61>

PCIE3_WLAN_SLOT_TXN<61>

PCIE3_WLAN_SLOT_TXP<61>

PCIE4_GBE_RXN<56>
PCIE4_GBE_RXP<56>
PCIE4_GBE_TXN<56>

PCIE4_GBE_TXP<56>

PCIE5_L0_TBT_RXN<46>

PCIE5_L0_TBT_RXP<46>

PCIE5_L0_TBT_TXN<46>

PCIE5_L0_TBT_TXP<46>

PCIE5_L1_TBT_RXN<46>

PCIE5_L1_TBT_RXP<46>

PCIE5_L1_TBT_TXN<46>
PCIE5_L1_TBT_TXP<46>

PCIE5_L2_TBT_RXN<46>
PCIE5_L2_TBT_RXP<46>

PCIE5_L2_TBT_TXN<46>

PCIE5_L2_TBT_TXP<46>

PCIE5_L3_TBT_RXN<46>
PCIE5_L3_TBT_RXP<46>

PCIE5_L3_TBT_TXN<46>

PCIE5_L3_TBT_TXP<46>

Please see Page 19

USB3 7 or PCIE 1

USB3 8

PCIE 3

GBE

PCIE 5

PCIE 6

USB2.0 Configuration (v0.51)

Net Name

PCIE1_EXP_SLOT

PCIE3_WLAN_SLOT

PCIE4_GBE

PCIE5_L0_TBT

PCIE5_L1_TBT

PCIE5_L2_TBT

PCIE5_L3_TBT

USB2 # Assignment

USB2 1

USB2 2

USB2 3

USB2 4

USB2 5

USB2 6

USB2 7

USB2 8

USB2 9

USB2 10

USB2 11

USB2 12

USB2 13

USB2 14

DMI_RXN0<5>

DMI_RXP0<5>

DMI_TXN0<5>

DMI_TXP0<5>

DMI_RXN1<5>

DMI_RXP1<5>

DMI_TXN1<5>

DMI_TXP1<5>
DMI_RXN2<5>

DMI_RXP2<5>

DMI_TXN2<5>

DMI_TXP2<5>

DMI_RXN3<5>
DMI_RXP3<5>

DMI_TXN3<5>

DMI_TXP3<5>

1

2

C8 0.1U_0201_6.3V6-K

1

2

C9 0.1U_0201_6.3V6-K

2

1

C10

1

2

C11

2

1

C12

1

2

C13

2

1

C14 0.22U_0201_6.3V6-K

1

2

C15 0.22U_0201_6.3V6-K

1

2

C16 0.22U_0201_6.3V6-K

1

2

C17 0.22U_0201_6.3V6-K

12

C18 0.22U_0201_6.3V6-K

1

2

C19 0.22U_0201_6.3V6-K

2

1

C20 0.22U_0201_6.3V6-K

2

1

C21 0.22U_0201_6.3V6-K

DMI_RXN0

DMI_RXP0

DMI_TXN0

DMI_TXP0

DMI_RXN1

DMI_RXP1

DMI_TXN1

DMI_TXP1
DMI_RXN2

DMI_RXP2
DMI_TXN2

DMI_TXP2

DMI_RXN3

DMI_RXP3

DMI_TXN3

DMI_TXP3

2

100_0402_1%

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

System Port 1 0

System Port 2 1

WWAN

DOCK

System Port 3 2

System Port 4 3

Reserved

Camera

Finger print

Touch panel

Smart Card

Reserved

Color Sensor

WLAN

R40

1

PCIE1_EXP_SLOT_TXN_C

PCIE1_EXP_SLOT_TXP_C

PCIE3_WLAN_SLOT_TXN_C

PCIE3_WLAN_SLOT_TXP_C

PCIE4_GBE_TXN_C
PCIE4_GBE_TXP_C

PCIE5_L0_TBT_TXN_C

PCIE5_L0_TBT_TXP_C

PCIE5_L1_TBT_TXN_C

PCIE5_L1_TBT_TXP_C

PCIE5_L2_TBT_TXN_C

PCIE5_L2_TBT_TXP_C

PCIE5_L3_TBT_TXN_C

PCIE5_L3_TBT_TXP_C

PCIE_RCOMPN

PCIE_RCOMPP

PCIE Configuration (v0.51)

OCx #

PCIE # High Speed Signals

PCIE 1

PCIE 2

PCIE 3

PCIE 4

PCIE 5

PCIE 6

PCIE 7

PCIE 8

PCIE 9 - 20

L27

N27

C27

B27

E24

G24

B28

A28

G27

E26

B29

C29

L29

K29

B30

A30

B18
C17

H15
G15

A16

B16

B19

C19

E17

G17

L17
K17
B20
C20

E20

G19
B21
A21

K19

L19

D22

C22

G22

E22

B22
A23

L22

K22

C23

B23

K24

L24

C24

B24

WLAN Card 2

GBE

Thunderbolt 1 3

Thunderbolt 2

Thunderbolt 3

Thunderbolt 4

Please see Page 16

U3B

DMI_RXN0

DMI_RXP0

DMI_TXN0

DMI_TXP0

DMI_RXN1

DMI_RXP1

DMI_TXN1

DMI_TXP1

DMI_RXN2

DMI_RXP2

DMI_TXN2

DMI_TXP2

DMI_RXN3

DMI_RXP3

DMI_TXN3

DMI_TXP3

PCIE_RCOMPN
PCIE_RCOMPP

PCIE1_RXN/USB3_7_RXN

PCIE1_RXP/USB3_7_RXP

PCIE1_TXN/USB3_7_TXN

PCIE1_TXP/USB3_7_TXP

PCIE2_TXN/USB3_8_TXN

PCIE2_TXP/USB3_8_TXP

PCIE2_RXN/USB3_8_RXN
PCIE2_RXP/USB3_8_RXP

PCIE3_RXN/USB3_9_RXN
PCIE3_RXP/USB3_9_RXP
PCIE3_TXN/USB3_9_TXN
PCIE3_TXP/USB3_9_TXP

PCIE4_RXN/USB3_10_RXN

PCIE4_RXP/USB3_10_RXP
PCIE4_TXN/USB3_10_TXN
PCIE4_TXP/USB3_10_TXP

PCIE5_RXN
PCIE5_RXP

PCIE5_TXN

PCIE5_TXP

PCIE6_RXN

PCIE6_RXP

PCIE6_TXN
PCIE6_TXP
PCIE7_RXN

PCIE7_RXP

PCIE7_TXN

PCIE7_TXP

PCIE8_RXN
PCIE8_RXP

PCIE8_TXN

PCIE8_TXP

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

DMI

GEN

PCIe/USB 3

2 OF 12

USB3.0 Configuration (v0.51)

USB 3# High Speed Signals

USB3 1 - 6

Please see Page 19

USB3 7

USB3 8

USB3 9

USB3 10

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5
USB2P_5

USB2N_6

USB2P_6

USB 2.0

USB2N_7

USB2P_7

USB2N_8
USB2P_8

USB2N_9

USB2P_9

USB2N_10
USB2P_10
USB2N_11

USB2P_11

USB2N_12

USB2P_12

USB2N_13

USB2P_13

USB2N_14

USB2P_14

GPP_E9/USB2_OC0#

GPP_E10/USB2_OC1#

GPP_E11/USB2_OC2#

GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4

GPP_F16/USB2_OCB_5

GPP_F17/USB2_OCB_6

GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

AF5

AG7

AD5

AD7

AG8

AG10

AE1

AE2

AC2
AC3

AF2

AF3

AB3

AB2

AL8
AL7

AA1

AA2

AJ8

AJ7

W2

W3

AD3

AD2

V2

V1

AJ11

AJ13

AD43

AD42

AD39

AC44
Y43

Y41

W44

W43

AG3

USB2_COMP

AD10

AB13

Leave RSVD_AB13 NC

AG2

Follow CRB schematic 3/9

BD14

VCC3_SUS

R3410K_0201_5%

R3510K_0201_5%

R3310K_0201_5%

1

1

12

2

2

1

R41 113_0402_1%

1

2

R3610K_0201_5%

1

@

2

2

R845
1K_0402_1%

R3710K_0201_5%

1

2

R3910K_0201_5%

R3810K_0201_5%

1

1

2

2

USBP1-_SYSP1 <54>

USBP1+_SYSP1 <54>

USBP2-_SYSP2 <54>

USBP2+_SYSP2 <54>

USBP3-_WWAN <61>

USBP3+_WWAN <61>

USBP4-_DOCK <74>

USBP4+_DOCK <74>

USBP5-_SYSP3 <55>

USBP5+_SYSP3 <55>
USBP6-_SYSP4 <55>

USBP6+_SYSP4 <55>

USBP8-_CAMERA <40>

USBP8+_CAMERA <40>

USBP9-_FINGER_PRINT <79>

USBP9+_FINGER_PRINT <79>

USBP10-_TOUCH <40>

USBP10+_TOUCH <40>

USBP11-_SMART_CARD <64>

USBP11+_SMART_CARD <64>

USBP12-_EXP_SLOT <64>

USBP12+_EXP_SLOT <64>

USBP13-_COLOR_SENSOR <40>

USBP13+_COLOR_SENSOR <40>

USBP14-_WLAN <61>

USBP14+_WLAN <61>

-USB_PORT0_OC0 <54>

-USB_PORT1_OC1 <54>

-USB_PORT2_OC2 <55>

-USB_PORT3_OC3 <55>

PLANARID3 <18>

PLANARID2 <18>

6/27 PLANARID2 from GPP_F14 change to GPP_F16

1

R10066
1K_0402_1%

2

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : DMI/PCIE/USB

PCH SKL-H : DMI/PCIE/USB

PCH SKL-H : DMI/PCIE/USB

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

of

15 116

of

15 116

15 116

1

of

A

0.1

0.1

0.1

5

Payton Common

D

CL_CLK_WLAN<61>

from / to WLAN

C

M.2 SSD1 L2

Media Card

M.2 SSD1 L3

M.2 SSD2 L3

B

M.2 SSD2 L2

PCIE9L2_MD2_SSD1_TXP<60>

PCIE9L2_MD2_SSD1_TXN<60>

PCIE9L2_MD2_SSD1_RXP<60>

PCIE9L2_MD2_SSD1_RXN<60>

WWAN_CFG2<61>

WWAN_CFG3<61>
PLANARID1<18>

PLANARID0<18>

PCIE13_MEDIACARD_TXN<62>

PCIE13_MEDIACARD_TXP<62>
PCIE13_MEDIACARD_RXN<62>

PCIE13_MEDIACARD_RXP<62>

PCIE9L3_MD2_SSD1_TXP<60>

PCIE9L3_MD2_SSD1_TXN<60>

PCIE9L3_MD2_SSD1_RXP<60>

PCIE9L3_MD2_SSD1_RXN<60>

PCIE17L3_MD2_SSD2_TXP<60>

PCIE17L3_MD2_SSD2_TXN<60>

PCIE17L3_MD2_SSD2_RXP<60>

PCIE17L3_MD2_SSD2_RXN<60>

PCIE17L2_MD2_SSD2_TXP<60>

PCIE17L2_MD2_SSD2_TXN<60>

PCIE17L2_MD2_SSD2_RXP<60>

PCIE17L2_MD2_SSD2_RXN<60>

CL_DATA_WLAN<61>

-CL_RST_WLAN<61>

1

2

C28 0.22U_0201_6.3V6-K

1

2

C30 0.22U_0201_6.3V6-K

1

2

C37 0.1U_0201_10V6-K

2

1

C36 0.1U_0201_10V6-K

1

2

C38 0.22U_0201_6.3V6-K

1 2

C39 0.22U_0201_6.3V6-K

1

2

C40 0.22U_0201_6.3V6-K

2

1

C41 0.22U_0201_6.3V6-K

1

2

C42 0.22U_0201_6.3V6-K

1

2

C43 0.22U_0201_6.3V6-K

4

VCC3_SUS

1

R42

@

10K_0402_5%

2

PCIE9L2_MD2_SSD1_TXP_C

PCIE9L2_MD2_SSD1_TXN_C

PCIE13_MEDIACARD_TXN_C

PCIE13_MEDIACARD_TXP_C

PCIE9L3_MD2_SSD1_TXP_C

PCIE9L3_MD2_SSD1_TXN_C

PCIE17L3_MD2_SSD2_TXP_C

PCIE17L3_MD2_SSD2_TXN_C

PCIE17L2_MD2_SSD2_TXP_C

PCIE17L2_MD2_SSD2_TXN_C

3

PCIE / SATA Configuration (v0.51)

I / O High Speed Signals GEN

Port 15

SATA 0A / PCIE 9

Port 16

SATA 1A / PCIE 10
Port 17

Port 18

Port 19

Port 20

Port 21

Port 22

Port 23

Port 24

Port 25

Port 26

AW2

AB33

AB35

AA44

AA45

/ PCIE 11

/ PCIE 12

SATA 0B / PCIE 13

SATA 1B / PCIE 14

SATA 2 / PCIE 15

SATA 3 / PCIE 16

SATA 4 / PCIE 17

SATA 5 / PCIE 18

/ PCIE 19

/ PCIE 20

U3C

AV2

CL_CLK

AV3

CL_DATA

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

GPP_F10/SCLOCK

GPP_F11/SLOAD

GPP_F13/SDATAOUT0

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKYLAKE-H-PCH_FCBGA837

CLINK

Configuration

M.2 SSD1 (L0) / SATA0A 3/3

M.2 SSD1 (L1)

M.2 SSD1 (L2)

M.2 SSD1 (L3)
Media Card 2

Reserved ---

SATA2 for HDD1 3

SATA3 for HDD2 3

M.2 SSD2 (L0) / SATA4 3
M.2 SSD2 (L1)

M.2 SSD2 (L2)

M.2 SSD2 (L3)

SPT-H_PCH

PCIE9_RXN/SATA0A_RXN

PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP

FAN

3 OF 12

PCIE10_TXN/SATA1A_TXN

PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E0/SATAXPCIE0/SATAGP0

GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP3

GPP_F1/SATAXPCIE4/SATAGP4

GPP_F2/SATAXPCIE5/SATAGP5

GPP_F3/SATAXPCIE6/SATAGP6

GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

HOST

GPP_E8/SATALED#

THERMTRIP#

PM_SYNC

PLTRST_PROC#

PM_DOWN

G31

H31

C31

PCIE9L0_SATA0A_MD2_SSD1_TXN_C

B31

PCIE9L0_SATA0A_MD2_SSD1_TXP_C

G29

E29
C32

PCIE9L1_MD2_SSD1_TXN_C

B32

PCIE9L1_MD2_SSD1_TXP_C

F41

E41
B39

SATA2_TXN_C

A39

SATA2_TXP_C

D43

E42

A41

SATA3_TXN_C

A40

SATA3_TXP_C

H42

H40

E45

PCIE17L0_SATA4_MD2_SSD2_TXN_C

F45

PCIE17L0_SATA4_MD2_SSD2_TXP_C

K37

G37

G45

PCIE17L1_MD2_SSD2_TXN_C

G44

PCIE17L1_MD2_SSD2_TXP_C

AD44

-SATALED

AG36

AG35
AG39

AD35

AD31

AD38

AC43

-MIC_HW_EN

AB44

W36

W35

W42

AJ3

AL3

PECI

AJ4
AK2
AH2

10K_0402_5%

12

@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

R51

10K_0402_5%

2

VCC3_SUS VCCST

R4310K_0402_5%

R4410K_0402_5%

1

1

2

2

2

1

C22

1

2

C23

2

1

C24

1

2

C25

1

2

C260.01U_0201_6.3V7-K

2

1

C270.01U_0201_6.3V7-K

1

2

C290.01U_0201_6.3V7-K

1

2

C310.01U_0201_6.3V7-K

1

2

C32

2

1

C33

1

2

C34

1

2

C35

1

R52

@

2

1

2

R53

0_0201_5%

1

R159

2

100K_0402_5%

VCC3B

R4610K_0402_5%

R4510K_0402_5%

1

1

2

2

1

1

2

100K_0201_5%

R471K_0402_5%

R10055

R10056

R76810K_0201_5%

1

1

1

1

2

2

2

2

10K_0402_5%

10K_0402_5%

2

R48604_0402_1%

2

R10098 0_0402_5%

1 2

30_0402_1%

1

R285

VCC3B

PCIE9L0_SATA0A_MD2_SSD1_RXN <60>

PCIE9L0_SATA0A_MD2_SSD1_RXP <60>

PCIE9L0_SATA0A_MD2_SSD1_TXN <60>

PCIE9L0_SATA0A_MD2_SSD1_TXP <60>

PCIE9L1_MD2_SSD1_RXN <60>

PCIE9L1_MD2_SSD1_RXP <60>

PCIE9L1_MD2_SSD1_TXN <60>

PCIE9L1_MD2_SSD1_TXP <60>

SATA2_HDDBAY1_RXN <65>

SATA2_HDDBAY1_RXP <65>

SATA2_HDDBAY1_TXN <65>

SATA2_HDDBAY1_TXP <65>

SATA3_HDDBAY2_RXN <66>

SATA3_HDDBAY2_RXP <66>

SATA3_HDDBAY2_TXN <66>
SATA3_HDDBAY2_TXP <66>

PCIE17L0_SATA4_MD2_SSD2_RXN <60>

PCIE17L0_SATA4_MD2_SSD2_RXP <60>

PCIE17L0_SATA4_MD2_SSD2_TXN <60>

PCIE17L0_SATA4_MD2_SSD2_TXP <60>

PCIE17L1_MD2_SSD2_RXN <60>

PCIE17L1_MD2_SSD2_RXP <60>

PCIE17L1_MD2_SSD2_TXN <60>
PCIE17L1_MD2_SSD2_TXP <60>

-PCIE_DETECT_SSD1 <60>

-PCIE_DETECT_SSD2 <60>

-WWAN_RESET <61>

PANEL_BKLT_CTRL_I <41>

VGA_BLON_I <41>
PANEL_POWER_ON_I <41>

1

R49

2

R5020_0402_1%

1

R10028
100K_0402_5%

2

1

M.2 SSD1 L0

M.2 SSD1 L1

SATA2 HDD1

SATA3 HDD2

Walter Only

M.2 SSD2 L0

M.2 SSD2 L1

To eDP

-THERMTRIP <7>

PECI <7,76>

PM_SYNC <7>

-PCH_PLTRST_PROC <7>

PM_DOWN <7>

Follow INTEL schematic 6/27

D

C

B

-SATALED_CONN <40>

1

D

-SATALED<60>

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

-SATALED

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

Deciphered Date

Deciphered Date

Deciphered Date

G

Q59
LSK3541G1ET2L_VMT3

S

3

2

2016/01/16

2016/01/16

2016/01/16

Title

Title

Title

PCH SKL-H : SATA/PCIE

PCH SKL-H : SATA/PCIE

PCH SKL-H : SATA/PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet of

1

D

2

G

S

3

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Q60
LSK3541G1ET2L_VMT3

1

of

16 116

of

16 116

16 116

A

0.1

0.1

0.1

5

4

3

2

1

Payton Common

TABLE : Functional Strap

HDA_SDO

D

C

From RTC Reset circuits

From CPU DCDC

From ASIC

From ASIC

From/to DIMM
and TP

From/to GBE

From/to EC

B

Flash Descriptor Security Override

HIGH

Disable Flash Descriptor Security (Override)

LOW

Enable Flash Descriptor Security (Default)

HDA_SDO is used to update the Descriptor and/or the
ME regions of the SPI after MFG Done bit is set.

@

C44

1

2

47P_0402_50V8-J

HDA_BCLK<67>

-HDA_RST<67>

HDA_SDIN0<67>

HDA_SDO<67>
HDA_SYNC<67>

20140730: As of now, we cannot get information about these pins
from SKL-H RVP and other documents. We need to confirm about them later.

PROC_AUDIO_SDO_CPU<6>

PROC_AUDIO_SDI_CPU<6>

PROC_AUDIO_CLK_CPU<6>

DDI_PRIORITY2 IS DESIGN HOOK FOR WALTER.
THIS WILL BE REMOVED FORM PAYTON FVT.
PAYTON HAS HDMI PORT ON DOCK ALWAYS THEN DON'T NEED THIS FUNCTION

PROC_AUDIO_SDO_CPU

PROC_AUDIO_SDI_CPU

PROC_AUDIO_CLK_CPU

DDI_PRIORITY2<43>

-RTCRST<25>

-SRTCRST<25>

CPUCORE_PWRGD<24,91>

-RSMRST<24,76>

MPWRG<76,85>

SMB_CLK<83>

SMB_DATA<83>

SML0_CLK<56>

SML0_DATA<56>

EC_SCL2<76>

EC_SDA2<76>

R57 33_0402_5%

R58 33_0402_5%

R59 33_0402_5%
R60 33_0402_5%

1 2

2

1

2

1

1

2

R61

R62

R65 0_0402_5%

R66 0_0402_5%

2

2

PLACE NEAR PCH

DDI_PRIORITY2

1

2

1

2

1

30_0402_1%

1

30_0402_1%

-SMB_ALERT
SMB_CLK

SMB_DATA

-SML0_ALERT

SML0_CLK

SML0_DATA

PCHHOT#

EC_SCL2

EC_SDA2

VCC3_SUS

VCC3_SUS

R54

1

1K_0402_5%

1K_0402_5%

Test_Point_20MIL

TEST PAD
BOTTOM SIDE
DO NOT MOVE AFTER FIX

HDA_BCLK_R

-HDA_RST_R

HDA_SDIN0

HDA_SDO_R

HDA_SYNC_R

1

PCHHOT#

VCC3_SUS

1

R56

2

Leave RSVD_BD1/BE2 NC

PROC_AUDIO_SDO_PCH

PROC_AUDIO_CLK_PCH

R819

2

150K_0402_5%

To enable DCI function

PLACE ON BOTTOM SIDE

R55

2

1

0_0402_5%

TP5

1

TP6

Test_Point_20MIL

U3D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKYLAKE-H-PCH_FCBGA837

1

TP987 Test_Point_12MIL

1

TP988 Test_Point_12MIL

1

TP989 Test_Point_12MIL

1

TP990 Test_Point_12MIL

TABLE : Functional Strap

GPP_C5/SML0ALERT#(LPC or SPI)

HIGH

eSPI is selected

LOW

LPC is selected(Default)

TABLE : Functional Strap

@

2

1

AUDIO

GPP_C5/SML0ALERT#(TLS Confidentiality)

HIGH

Enable ME Crypto TLS with Confldentlality

LOW

Disable ME Crypto TLS(Default)

SPT-H_PCH

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

SMBUS

JTAG

4 OF 12

-PCH_SLP_S4

-PCH_SLP_S5

-PWRSW_EC

-PCH_SLP_M

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B1

GPP_G17/ADR_COMPLETE

GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#

GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAGX

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

51_0402_1%

BB17

AW22

AR15

AV13

BC14
BD23
AL27

AR27

N44

AN24

AY1

BC13

BC15

AV15

BC26
AW15

BD15

BA13

AN15

BD13

BB19

BD19

BD11

BB15

BB13

AT13

AW1

BD26
AM3

AT2

AR3

AR2

AP1

AP2

AN3

R820

@

-CLKRUN

-DRAMRST

1

R63 0_0402_5%

-PCIE_WAKE

-PCH_SLP_LAN

-SUSACK

-SUSWARN

-LANWAKE

PROCPWRGD_PCH

2

R821
51_0402_1%

@

1 2

1

2

1

R72

TP59Test_Point_32MIL

2

R822
51_0402_1%

@

1

2

1

VCC1R0_SUS

2

R64 0_0402_5%

1

-CLKRUN <75,83>

LANPHYPC <56>

-PCH_SLP_WLAN <76>

-DRAMRST <27,28,29,30>

BPWRG <24,76,83,85>

-PCIE_WAKE <46,61,64,84>

-PCH_SLP_M <84>

-PCH_SLP_LAN <77>

-PCH_SLP_S0 <95,104>

-PCH_SLP_S3 <46,76,84,95>

-PCH_SLP_S4 <76,84>

-PCH_SLP_S5 <84>

SUSCLK_32K <61,75>

-BATLOW <46,77>

-LANWAKE <56>

AC_PRESENT <76>

-PCH_SLP_SUS <76>

-PWRSW_EC <76>

-XDP_DBR <24>

0_0402_5%

TABLE : Functional Strap

GPP_B14/SPKR(Top Swap Owerride)

HIGH

Enable "TOP Swap" Mode

LOW

Disable "TOP Swap" Mode (Default by Internal PD)

PCH_SPKR <72>

PROCPWRGD_CPU <7>

JTAGX <24>

PCH_TMS <24>

PCH_TDO <24>

PCH_TDI <24>

PCH_TCK <24>

from LPC Device(EC)
to GBE

to M.2 WLAN

to DIMM/SMBU SW

SKL-H PCH doenn't
require CORE VDD

to PHY PLL power FET
from ASIC

from M.2 WLAN Slot
to ASIC
to ASIC

to EC/FPR/ASIC/DebugPort
to EC/ASIC/DebugPort
to ASIC

to EC/ASIC/WLAN
from ASIC

from GBE
from ASIC
to EC
from EC
from XDP port
to Audio Mixer

to/from debug port

D

C

B

2

R74

1

8.2K_0402_5%

2016/01/16

2016/01/16

2016/01/16

VCC3MVCC1R2A VCC3B

1

R75

@

2

1

R76

2

10K_0402_5%

10K_0402_5%

-PCIE_WAKE

-PCH_SLP_LAN

-CLKRUN

-DRAMRST

Title

Title

Title

PCH SKL-H : AUDIO/SMBUS/JTAG

PCH SKL-H : AUDIO/SMBUS/JTAG

PCH SKL-H : AUDIO/SMBUS/JTAG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

1

of

17 116

of

17 116

17 116

of

A

0.1

0.1

0.1

VCC3_SUS

1

1

1

R559

R560

2

2

4.7K_0402_5%

4.7K_0402_5%

A

1

R68

R67

2

2

499_0402_1%

2.2K_0402_5%

Pullups on SMB are located in SMBUS Switch page.

5

1

1

R69

2

499_0402_1%

1

1

R70

R71

@

2

2

2.2K_0402_5%

2.2K_0402_5%

R10099

-SML0_ALERT

2

2.2K_0402_5%

SMB_CLK

SMB_DATA

SML0_CLK

SML0_DATA

-SMB_ALERT

EC_SCL2

EC_SDA2

4

-SML0_ALERT

1

R10100

2

1K_0402_5%

@

-DRAMRST

1

C9360
330P_0402_50V7-K

2

1

R73

2

470_0402_5%

EMI

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

5

Walter Unique

4

3

2

1

D

VCC3M

1

R456

@

2

10K_0201_5%

U3E

AW4

GPP_I0/DDPB_HPD0

3/9 Remove IGPU DP ports

C

EDP_HPD_I<41>

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

GPP_I10/DDPD_CTRLDATA

5 OF 12

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_F14

GPP_F23

GPP_F22

GPP_G23

GPP_G22

GPP_G21
GPP_G20

GPP_H23

BB3

BD6

BA5

BC4

BE5

BE6

Y44

V44

W39

L43

L44

U35
R35

BD36

3/9 Remove IGPU DP ports

-SC_DTCT <64>

GPU_PWR_EN <114,115>

SmartCard

Add GPU_PWR_EN 3/3

-DGFX_WITH_DISPLAYOUT

TABLE

PLANAR ID

3/29 close to PCH

1

GPP_H23
PAYTON: NC
WALTER: -DGFX_WITH_DISPLAYOUT (INPUT)
N16P QUADRO = LOW

R10022

N16S GEFORCE= HIGH

2

10K_0402_5%

-GPU_RST <34>

D

C

3210

R81R80R79

1

NA

0 ASMASM

PLANARID3

B

PLANARID2

PLANARID1
PLANARID0

PLANARID3 <15>

PLANARID2 <15>

PLANARID1 <16>

PLANARID0 <16>

6/27 PLANARID2 from GPP_F14 change to GPP_F16

R82

NANANA

ASMASM

Configuration

N16S

N16S / (Invalid)

N16P

N16P

-DGFX_WITH
_DISPLAYOUT

H

H

L

L

-DGFX_OUTPUT
_DISPLAYOUT

H

L

H

L

dGFX_output

---

mDP,TBT

eDP,mDP,TBT

iGFX_output

eDP,mDP,TBT

mDP,TBT

eDP

B

(P.14)

2

1

R79
0_0201_5%

@

2

1

R80
0_0201_5%

2

1

R81
0_0201_5%

2

1

R82
0_0201_5%

TABLE

LEVEL PLANARID[3..0]

--------PDV

SDV 0001b

FVT 0010b

SIT 0011b

CPU PCH

-------- --------

ES(Q0)

ES2(C0)

ES(Q0)

ES2(C0)

QS(R0) QS(D1)

SIT-4G 0011b QS(R0) QS(D1)

0011b QS(R0) QS(D1)SIT-2

SVT 0100b Prod Prod

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : DDI CONTROL

PCH SKL-H : DDI CONTROL

PCH SKL-H : DDI CONTROL

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

18 116

of

18 116

of

18 116

A

0.1

0.1

0.1

5

Payton Common

D

USB3P1_SYSP1_TXN<54>

System Port 1

System Port 2

System Port 4

System Port 3

DOCK

VCC3M

C

1

2

C9276

B

VCC3M

@

4.7K_0201_5%

@

4.7K_0201_5%

A

1

2

0.1U_0402_16V7-K

1

R10129

2

1

R10130

2

1

C616

2

0.1U_0402_16V7-K

10U_0603_6.3V6-M

EQ3

DE3

OS3

OS4

DE4

EQ4

EQ3 EQ4

USB3P1_SYSP1_TXP<54>

USB3P1_SYSP1_RXN<54>

USB3P1_SYSP1_RXP<54>

USB3P2_SYSP2_TXN<54>

USB3P2_SYSP2_TXP<54>

USB3P2_SYSP2_RXN<54>

USB3P2_SYSP2_RXP<54>

<Walter Only>

<Walter Only>

USB3P4_DOCK_TXP<74>

USB3P4_DOCK_TXN<74>

USB3P4_DOCK_RXP<74>

USB3P4_DOCK_RXN<74>

C9348

VCC3M

@

4.7K_0201_5%

@

4.7K_0201_5%

1

U3403

VCC33

2

EQ1

3

DE1

4

OS1

5

EN

14

RSV

15

OS2

16

DE2

17

EQ2

GND

GND2

6

10

1

R10131

2

12

R10132

13

VCC33_1

GND3

GND4

GND5

18

21

25

VCC3M

@

4.7K_0201_5%

@

4.7K_0201_5%

USB3P6_SYSP4_TXN_I

USB3P6_SYSP4_TXP_I

USB3P6_SYSP4_RXN_I

USB3P6_SYSP4_RXP_I

USB3P5_SYSP3_TXN_I
USB3P5_SYSP3_TXP_I

USB3P5_SYSP3_RXN_I

USB3P5_SYSP3_RXP_I

TUSB502_QFN24_4X4

1

R10133

2

DE3

1

R10139

2

TX1N

TX1P

RX2N

RX2P

TX2P

TX2N

RX1P

RX1N

NC1

23

22

20

19

12

11

9

8

7

NC

24

4

U3F

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKYLAKE-H-PCH_FCBGA837

USB3.0 Redriver
Port-4

USB3P6_SYSP4_TXN <55>

USB3P6_SYSP4_TXP <55>

USB3P6_SYSP4_RXN <55>

USB3P6_SYSP4_RXP <55>

USB3P6_SYSP4_RXP_C

USB3P6_SYSP4_RXN_C

USB3P6_SYSP4_TXP_C

USB3P6_SYSP4_TXN_C

VCC3M

@

4.7K_0201_5%

4.7K_0201_5%

@

VCC3M

1

R10134

2

DE4

1

R10140

2

1

2

2

2

2

2

C617

10U_0603_6.3V6-M

VCC3M

@

4.7K_0201_5%

@

4.7K_0201_5%

USB

1

C9287

1

C9288

1

C9284

1

C9283

close to U3404

12

R10135

OS3

1

R10136

2

SPT-H_PCH

LPC/eSPI

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

SATA

6 OF 12

0.1U_0402_16V7-K

USB3P6_SYSP4_RXP_I

0.1U_0402_16V7-K

USB3P6_SYSP4_RXN_I

0.1U_0402_16V7-K

0.1U_0402_16V7-K

1

C609

2

0.1U_0402_16V7-K

USB3P6_SYSP4_TXP_I

USB3P6_SYSP4_TXN_I

VCC3M

4.7K_0201_5%

@

4.7K_0201_5%

GPP_A1/LAD0/ESPI_IO0

GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2

GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI#

GPP_G18/NMI#

GPP_E6/DEVSLP2

GPP_E5/DEVSLP1

GPP_E4/DEVSLP0

GPP_F9/DEVSLP7

GPP_F8/DEVSLP6

GPP_F7/DEVSLP5

GPP_F6/DEVSLP4

GPP_F5/DEVSLP3

USB3.0 Redriver
Port-3

1

C610

2

0.1U_0402_16V7-K

1

@

R10137

2

OS4

1

R10138

2

3

VCC3_SUS

1

R83

10K_0402_5%

2

AT22

AV22
AT19

BD16

BE16

BA17

AW17

AT17

BC18

BC17
AV19

M45

N43

AE45

AG43

AG42

AB39

AB36

AB43

AB42

AB41

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

1

R84 22_0402_5%

1

R85 22_0402_5%

Follow Schematic Checklist 2016/3/9

2

EQ5

3

DE5

4

OS5

5

14

15

OS6

16

DE6

17

EQ6

U3404

EQ1

DE1

OS1

EN

RSV

OS2

DE2

EQ2

2

VCC3B

1

2

R562

8.2K_0402_5%

I/O High Speed Signals Configuration

Port 1

Port 2

Port 3

Port 4

Port 5

LPC_AD0 <75,83>

LPC_AD1 <75,83>

LPC_AD2 <75,83>
LPC_AD3 <75,83>

-LPC_FRAME <75,83>

IRQSER <75,83>

-TPM_IRQ <82>

-KBRC <75>

-SUS_STAT <75,83>

2

2

1

@

R10141

2

EQ5

4.7K_0201_5%

1

@

R10142

2

4.7K_0201_5%

13

1

VCC33

VCC33_1

GND

GND4

GND3

GND2

GND5

6

21

18

10

25

LPCCLK_EC_24M <75>

LPCCLK_DEBUG_24M <83>

DEVSLP0_MD2_SSD1 <60>

WWAN_CFG1 <61>

WWAN_CFG0 <61>

-INT_MIC_DTCT <40>

DEVSLP4_MD2_SSD2 <60>

VCC3MVCC3M

1

@

R10143

2

EQ6

4.7K_0201_5%

1

@

R10144

2

4.7K_0201_5%

23

TX1N

22

TX1P

20

RX2N

19

RX2P

12

USB3P5_SYSP3_RXP_C

TX2P

11

USB3P5_SYSP3_RXN_C

TX2N

9

USB3P5_SYSP3_TXP_C

RX1P

8

USB3P5_SYSP3_TXN_C

RX1N

7

NC

24

NC1

TUSB502_QFN24_4X4

Port 6

to SSD in M.2 Slot

to SSD in M.2 Slot

VCC3M

12

@

R10145

DE5

4.7K_0201_5%

1

@

R10151

2

4.7K_0201_5%

USB3P5_SYSP3_TXN <55>

USB3P5_SYSP3_TXP <55>

USB3P5_SYSP3_RXN <55>

USB3P5_SYSP3_RXP <55>

2

2

2

2

Flexible I/O Configuration (v0.51)

USB3 1 Capable of OTG USB3

USB2 3 / SSIC 1

USB3 3 / SSIC 2

USB3 4

USB3 5

USB3 6

VCC3M

1

@

R10146

2

DE6

4.7K_0201_5%

1

@

R10152

2

4.7K_0201_5%

1

C92950.1U_0402_16V7-K

1

C92960.1U_0402_16V7-K

1

C92940.1U_0402_16V7-K

1

C92930.1U_0402_16V7-K

USB3P5_SYSP3_RXP_I

USB3P5_SYSP3_RXN_I

USB3P5_SYSP3_TXP_I

USB3P5_SYSP3_TXN_I

1

USB3

USB3 or SSIC

USB3

USB3

USB3

VCC3M

12

@

R10147

OS5

4.7K_0201_5%

1

@

R10149

2

4.7K_0201_5%

Net Name

USB3P1_SYSP1

USB3P2_SYSP2

USB3P3_WWAN

USB3P4_DOCK

USB3P5_SYSP3

USB3P6_SYSP4

VCC3M

1

@

R10148

2

4.7K_0201_5%

1

@

R10150

2

4.7K_0201_5%

D

C

OS6

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : USB3/LPC

PCH SKL-H : USB3/LPC

PCH SKL-H : USB3/LPC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

1

of

19 116

of

19 116

of

19 116

0.1Custom

0.1Custom

0.1Custom

5

Payton Common

4

3

2

1

D

U3G

AR17

GPP_A16/CLKOUT_48

CPU_REFCLK_24M<7>

-CPU_REFCLK_24M<7>

CPU_BCLK_100M<7>

-CPU_BCLK_100M<7>

C

1

R10068
100K_0402_5%

2

B

-CLKREQ_PCIE0_UHS2<62>

-CLKREQ_PCIE2_WLAN<61>

-CLKREQ_PCIE3_GBE<56>

-CLKREQ_PCIE4_MD2_SSD1<60>

-CLKREQ_PCIE5_PEG<31>

-CLKREQ_PCIE6_EXPCARD<64>

-CLKREQ_PCIE7_MD2_SSD2<60>

-CLKREQ_PCIE8_TBT<46>

VCC3B

C46 10P_0402_50V8-J

32.768KHZ_9PF_1TJH090DR1A0001

C47 10P_0402_50V8-J

External Pull on CLKREQ# should be placed in device page,
as power railis may be different from PCH-H..

R10046 10K_0402_5%

1

2

1

2

VCC1R0_SUS

12

1

1

Y1

Y1 ->
KDS 1TJH090DR1A0001

2

2

1

R86 2.7K_0402_0.5%

-CLKREQ_PCIE5_PEG

R87
10M_0402_5%

2

RTCX1

RTCX2

XTAL24_OUT

XTAL24_IN

XCLK_BIASREF

RTCX1
RTCX2

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKYLAKE-H-PCH_FCBGA837

PCIE Clock Assignment

SPT-H_PCH

7 OF 12

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0

CLKOUT_PCIE_P0

CLKOUT_PCIE_N1

CLKOUT_PCIE_P1

CLKOUT_PCIE_N2

CLKOUT_PCIE_P2

CLKOUT_PCIE_N3

CLKOUT_PCIE_P3

CLKOUT_PCIE_N4

CLKOUT_PCIE_P4

CLKOUT_PCIE_N5

CLKOUT_PCIE_P5

CLKOUT_PCIE_N6

CLKOUT_PCIE_P6

CLKOUT_PCIE_N7

CLKOUT_PCIE_P7

CLKOUT_PCIE_N8

CLKOUT_PCIE_P8

CLKOUT_PCIE_N9

CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

L1

L2

J1

J2

N7

N8

L7

L5

D3

F2

E5

G4

D5

E6

D8

D7

R8

R7

U5

U7

W10

W11

N3

N2

P3

P2

R3

R4

-CPU_PCI_BCLK_100M <7>

CPU_PCI_BCLK_100M <7>

-PCIE0_CLK_100M_UHS2 <62>

PCIE0_CLK_100M_UHS2 <62>

-PCIE2_CLK_100M_WLAN <61>

PCIE2_CLK_100M_WLAN <61>

-PCIE3_CLK_100M_GBE <56>

PCIE3_CLK_100M_GBE <56>

-PCIE4_CLK_100M_MD2_SSD1 <60>

PCIE4_CLK_100M_MD2_SSD1 <60>

-PCIE5_CLK_100M_PEG <31>

PCIE5_CLK_100M_PEG <31>

-PCIE6_CLK_100M_EXPCARD <64>

PCIE6_CLK_100M_EXPCARD <64>

-PCIE7_CLK_100M_MD2_SSD2 <60>

PCIE7_CLK_100M_MD2_SSD2 <60>

-PCIE8_CLK_100M_TBT <46>

PCIE8_CLK_100M_TBT <46>

D

C

B

Clock 0 : UHS II
Clock 1 : NA

C48

1

2

3.9P_0201_25V9-C

24MHZ_6PF_1ZZHAE24000CC0B

C49

1

2

3.9P_0201_25V9-C

SJ10000P000, S CRYSTAL 24MHZ 6PF 1ZZHAE24000CC0B,

R10169

1

2

1

4

3

Y2

0_0201_5%

1

2

R88
1M_0201_5%

R10170

2

1

0_0201_5%

XTAL24_OUT

2

XTAL24_IN

Clock 2 : Wireless LAN M.2 Slot
Clock 3 : Giga Bit Ethernet
Clock 4 : PCIe SSD on M.2 Slot
Clock 5 : Discrete GFX(MXM or Onboard)
Clock 6 : Express Slot
Clock 7 : PCIe SSD on M.2 Slot
Clock 8 : Thunderbolt
Clock 9 - 15 : NA

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : CLK

PCH SKL-H : CLK

PCH SKL-H : CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

1

of

20 116

20 116

of

20 116

of

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

To use eSPI, VCCPGPPA should have 1.8V

D

0.029A

VCC3_SUS

VCCUSB2PLL_1P0

1

C68

2

0.195A

VCC3M

0.033A1.0V

VCC1R0_SUS

3.137A

1.0V

VCC1R0_SUS

C50

@

22U_0805_6.3V6-M

C64

@

1

C65

2

@

22U_0805_6.3V6-M

NEAR PCH PIN

1

C51

@

2

1

2

0.1U_0402_25V6-K

NEAR
W15

VCCMPHYPLL_1P0

C66

@

NEAR

1

K2

C52

@

2

1U_0402_10V6-K

1

C59

2

1U_0402_10V6-K

NEAR
BA29

0.03A

1.0V

VCC1R0_SUS

1

C67

2

1U_0402_10V6-K

1

4.110A

1.0V

C

B

VCC1R0_SUS

1

C60

2

22U_0805_6.3V6-M

NEAR PCH PKG

1

C61

2

1U_0402_10V6-K

2

22U_0805_6.3V6-M

VCCMPHYPLL_1P0

VCCAPLLEBB_1P0

VCCUSB2PLL_1P0

VCCHDAPLL_1P0

VCC3_SUS

VCC3M

0.11A 0.012A

VCC1R0_SUS

R89

2

1

0_0603_5%

1

2

22U_0805_6.3V6-M

U3H

AA23

VCCPRIM_1P0_1

AA26

VCCPRIM_1P0_2

AA28

VCCPRIM_1P0_3

AC23

VCCPRIM_1P0_4

AC26

VCCPRIM_1P0_5

AC28

VCCPRIM_1P0_6

AE23

VCCPRIM_1P0_7

AE26

VCCPRIM_1P0_8

Y23

VCCPRIM_1P0_9

Y25

VCCPRIM_1P0_10

BA29

DCPDSW_1P0

N17

VCCCLK1_1

R19

VCCCLK3_2

U20

VCCCLK4_3

V17

VCCCLK2_4

R17

VCCCLK2_5

K2

VCCCLK5_6

K3

VCCCLK5_7

U21

VCCMPHY_1P0_1

U23

VCCMPHY_1P0_2

U25

VCCMPHY_1P0_3

U26

VCCMPHY_1P0_4

V26

VCCMPHY_1P0_5

A43

VCCMPHYPLL_1P0_1

B43

VCCMPHYPLL_1P0_2

C44

VCCPCIE3PLL_1P0_1

C45

VCCPCIE3PLL_1P0_2

V28

VCCAPLLEBB_1P0

AC17

VCCPRIM_1P0_16

AJ5

VCCUSB2PLL_1P0_1

AL5

VCCUSB2PLL_1P0_2

AN19

VCCHDAPLL_1P0

BA15

VCCHDA

W15

VCCDSW_3P3_1

SKYLAKE-H-PCH_FCBGA837

R90

1

0_0603_5%

2

SPT-H_PCH

CORE

MPHY

USB

VCCAPLLEBB_1P0

8 OF 12

VCCGPIO

VCCPRIM_1P0_17

VCCDSW_3P3_2

VCCPGPPA

VCCPGPPBCH_1

VCCPGPPBCH_2

VCCPGPPEF_1

VCCPGPPEF_2

VCCPGPPG

VCCPRIM_3P3

VCCPRIM_1P0_15

VCCATS

VCCRTCPRIM_3P3

VCCRTC

DCPRTC

VCCPRIM_1P0_11

VCCPRIM_1P0_12

VCCPRIM_1P0_13

VCCPRIM_1P0_14

VCCSPI_1

VCCSPI_2

VCCSPI_3

VCCPGPPD_1

VCCPGPPD_2

VCCPGPPD_3

VCCPGPPD_4

VCCPRIM_3P3_1

VCCPRIM_3P3_2

VCCPRIM_3P3_3

VCC1R0_SUS

AL22

BA24
BA31

BC42

BD40

AJ41

AL41

AD41

AN5

AD15

AD13

BA20

BA22

BA26

AJ20

AJ21

AJ23

AJ25

BE41

BE43

BE42

BC44

BA45

BC45

BB45

BD3

BE3

BE4

R91

1

0_0603_5%

VCC1R0_SUS

VCC3B

2

1U_0402_10V6-K

NEAR PCH PKG(follow CRB)

Note 1: Ampere in this page means Iccmax current described in SKL PCH H EDS r0.91 page 57.

A

Note 2: Decoupling capacitors refers SKL H PDG r0.7 page 507.
SKL H RVP11 schematics r0.5 also referred.

0.1U_0402_25V6-K

NEAR
BA26

1

C658

0.1U_0402_16V7-K

NEAR

2

BA31

RTCVCC

1

1

C62

2

2

0.1U_0402_25V6-K

NEAR
BA22

R92

1

2

0_0603_5%

NEAR PCH PKG(follow CRB)

C63

1U_0402_6.3V6-K

1

2

1U_0402_10V6-K

1

C659

0.1U_0402_16V7-K

NEAR

2

BA31

@

1

C53

2

NEAR

0.1U_0402_25V6-K

BC42

1

C288

2

VCC3B

VCCHDAPLL_1P0

C69

0.1U_0402_25V6-K

@

1

2

NEAR
AJ41

0.746A

VCC3_SUS

@

@

1

2

NEAR
AN5

1

C57

C56

2

NEAR

0.1U_0402_25V6-K

BA20

0.1U_0402_25V6-K

1

C54

C55

2

NEAR

0.1U_0402_25V6-K

0.1U_0402_25V6-K

AD41

0.007A

VCC3B

1

C514

2

1U_0402_6.3V6-K

NEAR
AD13

1

2

NEAR
AD13

D

C58

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : POWER

PCH SKL-H : POWER

PCH SKL-H : POWER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

WALTER

WALTER

WALTER

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

of

21 116

of

21 116

21 116

0.1Custom

0.1Custom

0.1Custom

5

Payton Common

4

3

2

1

D

SPT-H_PCH

U3I

AC18

VSS_1

AN4

VSS_2

AN10

VSS_3

BE14

VSS_4

BE18

VSS_5

BE23

VSS_6

BE28

VSS_7

BE32

VSS_8

BE37

VSS_9

BE40

VSS_10

BE9

VSS_11

C10

VSS_12

C2

VSS_13

C28

VSS_14

C37

VSS_15

J7

VSS_16

K10

VSS_17

K27

VSS_18

K33

VSS_19

K36

VSS_20

K4

VSS_21

K42

VSS_22

K43

C

B

VSS_23

L12

VSS_24

L13

VSS_25

L15

VSS_26

L4

VSS_27

L41

VSS_28

L8

VSS_29

M35

VSS_30

M42

VSS_31

N10

VSS_32

N15

VSS_33

N19

VSS_34

N22

VSS_35

N24

VSS_36

N35

VSS_37

N36

VSS_38

N4

VSS_39

N41

VSS_40

N5

VSS_41

P17

VSS_42

P19

VSS_43

P22

VSS_44

P45

VSS_45

R10

VSS_46

R14

VSS_47

R22

VSS_48

R29

VSS_49

R33

VSS_50

R38

VSS_51

R5

VSS_52

T1

VSS_53

T2

VSS_54

T4

VSS_55

Y18

VSS_56

Y20

VSS_57

Y21

VSS_58

Y26

VSS_59

Y28

VSS_60

Y29

VSS_61

A18

VSS_62

A25

VSS_63

A32

VSS_64

A37

VSS_65

AA17

VSS_66

AA18

VSS_67

AA20

VSS_68

AA21

VSS_69

AA25

VSS_70

AA29

VSS_71

AA4

VSS_72

AA42

VSS_73

AB10

VSS_74

9 OF 12

SKYLAKE-H-PCH_FCBGA837

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85
VSS_86

VSS_87
VSS_88
VSS_89
VSS_90

VSS_91

VSS_92
VSS_93
VSS_94

VSS_95
VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101
VSS_102
VSS_103

VSS_104

VSS_105

VSS_106

VSS_107
VSS_108

VSS_109

VSS_110

VSS_111
VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117
VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124
VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133
VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139
VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

AR5

AR7

U15

AL4

AE29
AE4

AE42

AF18

AF20

AF21

AF23

AF25

AF26
AF28
AF29
AG11

AG13

AG31
AG32
AG33

AG38
AG4

AH1

AH17

AH18

AH20

AH21
AH23
AH25

AH26

AH28

AH29

AH45
AJ10

AJ14

AJ15

AJ17
AJ18

AJ26

AJ28

AJ29

AJ31

AJ32

AJ36

AK4

AK42

AU7

AV17

AV24

AV27
AV31

AV33

AV6

AW13

AW19

AW29

AW37

AW9

AY38
AY45

B25

B3

B37
B40

B6
BA1

BB11

BB16

BB21

BB25

BB30

BB34

BC2

BD43

SPT-H_PCH

U3L

C42

VSS_149

D10

VSS_150

D12

VSS_151

D15

VSS_152

D16

VSS_153

D17

VSS_154

D19

VSS_155

D21

VSS_156

D24

VSS_157

D25

VSS_158

D27

VSS_159

D29

VSS_160

D30

VSS_161

D31

VSS_162

D33

VSS_163

D35

VSS_164

D36

VSS_165

E13

VSS_166

E15

VSS_167

E31

VSS_168

E33

VSS_169

F44

VSS_170

F8

VSS_171

G42

VSS_172

G9

VSS_173

H17

VSS_174

H19

VSS_175

H22

VSS_176

H24

VSS_177

H27

VSS_178

H29

VSS_179

H3

VSS_180

H35

VSS_181

J10

VSS_182

J11

VSS_183

J3

VSS_184

J39

VSS_185

J5

VSS_186

T42

VSS_187

U10

VSS_188

U11

VSS_189

U14

VSS_190

U17

VSS_191

U18

VSS_192

U28

VSS_193

U29

VSS_194

U31

VSS_195

U32

VSS_196

U33

VSS_197

U38

VSS_198

U4

VSS_199

U8

VSS_200

V18

VSS_201

V20

VSS_202

V21

VSS_203

V23

VSS_204

V25

VSS_205

V29

VSS_206

V3

VSS_207

V45

VSS_208

W14

VSS_209

W31

VSS_210

W32

VSS_211

W33

VSS_212

W38

VSS_213

W4

VSS_214

W8

VSS_215

Y17

VSS_216

12 OF 12

SKYLAKE-H-PCH_FCBGA837

VSS_217

VSS_218

VSS_219

VSS_220

VSS_221

VSS_222

VSS_223

VSS_224

VSS_225

VSS_226

VSS_227

VSS_228

VSS_229

VSS_230

VSS_231

VSS_232

VSS_233

VSS_234

VSS_235

VSS_236
VSS_237

VSS_238

VSS_239
VSS_240

VSS_241

VSS_242

VSS_243

VSS_244

VSS_245

VSS_246

VSS_247
VSS_248
VSS_249

VSS_250

VSS_251

VSS_252

VSS_253

VSS_254

VSS_255

VSS_256

VSS_257
VSS_258

VSS_259
VSS_260

VSS_261

VSS_262

VSS_263
VSS_264

VSS_265

VSS_266

VSS_267

VSS_268

VSS_269

VSS_270

VSS_271

VSS_272

VSS_273

VSS_274
VSS_275

VSS_276

VSS_277

VSS_278

VSS_279

VSS_280
VSS_281

VSS_282

VSS_283

VSS_284
VSS_285

AB11

AB7

AB14

AB31

AB32

AB38

AB4

AB5

AC1

AC20

AC21

AC25

AC29

AC45

AB8

AD11

AD14

AB15

AD32

AD33
AD36

AD4

AD8
AE18

AE20

AE21

AE25

AE28

AL10

AL11

AL13
AL17

AL19

AL24

AL29

AL32

AL33

AL38

AM15

AM17

AM19
AM22

AM24
AM27

AM29

AM45

AN11
AN22

AN27

AN31

AN39

AN7

AN8

AP11

AP4

AR33

AR34

AR42
AR9

AT10

AT15

AT36

AT9

AU1
AU35

AU36

AU39

AU45
C4

U3J

BD2

VSS_286

BD45

VSS_287

BD44

VSS_288

BE44

VSS_289

D45

VSS_290

A42

VSS_291

B45

VSS_292

B44

VSS_293

A4

VSS_294

A3

VSS_295

B2

VSS_296

A2

VSS_297

B1

VSS_298

BB1

VSS_299

BC1

VSS_300

A44

VSS_301

C1

RSVD_5

D1

RSVD_6

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

10 OF 12

RSVD_7

RSVD_8

RSVD_9

RSVD_10

RSVD_11

RSVD_12

RSVD_13

RSVD_14

RSVD_15

RSVD_16

RSVD_17

RSVD_18

PREQ#

PRDY#

CPU_TRST#

PCH_TRIGOUT

PCH_TRIGIN

AR22

W13

U13

P31

N31

P27

R27

N29

P29

AN29

R24

P24

AT3

AT4

AY5

AL2

AK1

Leave as NC

R656

1

2

30_0402_1%

-PCH_PREQ <24>

-PCH_PRDY <24>

-CPU_TRST <24>

PCH_2_CPU_TRIGGER <13>

CPU_2_PCH_TRIGGER <13>

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : GND/RSVD

PCH SKL-H : GND/RSVD

PCH SKL-H : GND/RSVD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

22 116

of

22 116

of

22 116

A

0.1

0.1

0.1

5

Walter Unique

D

GPP_B18_NO_REBOOT<24>

VCC3B

C

From EC

-EC_WAKE<75>

-EC_SCI<75>

R10103

1

@

0_0201_5%

4

3

2

1

PAYTON WALTER

GPP_D9 -MXM_PRESENCE -DISCRETE_PRESENCE

: Always Low

N16P N16S

GPP_D11

VCC3_SUS

1

R9881

U3K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B18_NO_REBOOT

2

Leave as NC

TP998Test_Point_20MIL

1

UART1_TXD

1

UART1_RXD

TP999Test_Point_20MIL

Leave as NC

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SKYLAKE-H-PCH_FCBGA837

SPT-H_PCH

GPP_D9

GPP_D10

GPP_D11

GPP_D16/ISH_UART0_CTS#

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

GPP_D15/ISH_UART0_RTS#

11 OF 12

GPP_D12

GPP_H20/ISH_I2C0_SCL

GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL

GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5

GPP_A22/ISH_GP4
GPP_A21/ISH_GP3

GPP_A20/ISH_GP2

GPP_A19/ISH_GP1

GPP_A18/ISH_GP0

GPP_A17/ISH_GP7

AL44

AL36

AL35
AJ39

AJ43

AL43

AK44

AK45

BC38

BB38

BD38

BE39

BC22

BD18
BE21

BD22

BD21

BB22

BC19

10K_0402_5%

2

-DISCRETE_PRESENCE

WALTER_P_T

Leave as NC

Leave as NC

1

R9928
10K_0402_5%

2

1

2

R9882
0_0402_5%

HIGH LOW

DGFX_PWRGD <110,112,115>

TBT_FORCE_ON <46>

-CIO_PLUG_EVENT <46>

D

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

PCH SKL-H : GSPI/UART/I2C

PCH SKL-H : GSPI/UART/I2C

PCH SKL-H : GSPI/UART/I2C

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

23 116

of

of

23 116

23 116

B

A

0.1

0.1

0.1

5

Walter Unique

TABLE : CPU ITP DEBUG REPORT

No use

D

R591
R593
R594
R595
R596
R657 NO ASM

NO ASM
NO ASM
NO ASM
NO ASM
NO ASM
NO ASM
NO ASMR658

R102
R597
R9907

JXDP1
C70
R96
R101 ASM
R9909

C

R9910
R9916
R99

NO ASM

NO ASM
NO ASM
NO ASM
ASM
NO ASM
NO ASM
NO ASM
NO ASM

NO ASM
R9912 ASMASMNO ASM
R9934
R9930
R9931
R9932
R9933

NO ASM

NO ASM

NO ASM

NO ASM

NO ASM

LOGIC

TABLE : PCH ITP DEBUG REPORT

No use DCI 2.0

B

R93
JXDP1
R9917
R101
R9908
R9911
R9913
R9915

NO ASM

NO ASM

NO ASM

NO ASM

NO ASM

NO ASM

NO ASM

NO ASM ASM

LOGIC

R820 NO ASMASMNO ASM
R821

NO ASM

NO ASM

TABLE : Functional Strap

A

GPP_B18/GSPI0_MOSI (No Reboot)

Enable "No Reboot" Mode

HIGH

LOW Disable "No Reboot" Mode (Default )

5

Individual
Port

NO ASM
NO ASM
NO ASM
NO ASM
NO ASM

NO ASM

ASM
ASMNO ASM
ASM
ASM
ASM
ASM

ASM
ASM
ASM
ASM

ASM
ASM
ASM
ASM
ASM

Individual
Port

ASM
ASM
ASM
ASM
ASM
ASM
ASM

ASM
ASMR822

DCI 2.0
w/o connector

w/o connector

ASM
ASM
ASM
ASM
ASM
ASM
ASM

NO ASM
NO ASM
ASM
NO ASM
NO ASM
ASM
NO ASM
ASM
ASM
ASM
ASM

ASM
ASM
ASM
ASM
ASM

NO ASM
NO ASM
NO ASM
NO ASM
NO ASM
NO ASM
NO ASM
NO ASM

NO ASM
NO ASM

R563

ASM

NO ASM

SHEET 17

LOGIC

4

VCC3_SUS

1

2

4

R563
1K_0402_5%

@

Place near PCH

GPP_B18_NO_REBOOT

JTAGX<17>

PCH_TMS<17>

PCH_TDI<17>

-CPU_TRST<22>

PCH_TDO<17>

-PCH_PRDY<22>

-PCH_PREQ<22>

VCC1R0_SUS

2

R93
51_0402_1%

@

1

R9913 0_0402_5%

PCH_TDI

R9915 0_0402_5%

PCH_TDO

GPP_B18_NO_REBOOT <23>

1 2

@

1

@

JTAGX

PCH_TMS

PCH_TDI

-CPU_TRST

PCH_TDO

-PCH_PRDY

-PCH_PREQ

2

3

Follow DCI Schematic 6/23

1

R591 0_0402_5%

R593 0_0402_5%

R594 0_0402_5%

R595 0_0402_5%

R596 0_0402_5%

R657 0_0402_5%

R658 0_0402_5%

TDI

TDO

Follow DCI Schematic 7/4

PCH_TCK<17>

XDP_TCK<7>

XDP_TMS<7>
XDP_TDI<7>

-XDP_TRST<7>

XDP_TDO<7>

-XDP_DBR<17>

-PLTRST_FAR<14,46,52,56,60,62>

CPUCORE_PWRGD<17,91>

BPWRG<17,76,83,85>

-RSMRST<17,76>

CFG3<7>

-XDP_PRDY<7>

-XDP_PREQ<7>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2

1

2

1

2

1

2

1

2

1

2

1

2

VCCST

PCH_TMS

-RSMRST

XDP_TCK

XDP_TMS

XDP_TDI

-XDP_TRST

XDP_TDO

-XDP_PRDY

-XDP_PREQ

1

R9907
100_0402_1%

2

1

R9908 0_0402_5%

R9909 0_0402_5%

R9911 0_0402_5%

R9910 0_0402_5%

R9912 0_0402_5%

R9934 0_0402_5%

R9916 0_0402_5%

R99 1K_0402_5%

R9917 1K_0402_5%

R9930 0_0201_5%

R101 1K_0402_5%

R9931 0_0402_5%

R9932 0_0402_5%

R9933 0_0402_5%

2015/07/16

2015/07/16

2015/07/16

2

@

1

2

@

2

1

@

2

1

@

1

2

@

1

2

@

1

2

@

@

1 2

@

2

1

1

2

@

@

2

1

1 2

@

1

2

@

2

1

@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

TDI

TDO

2

1

R102
1K_0402_1%

@

2

2

VCC3B

10K_0402_5%

1

2

SPI_IO2<14,26>

R96

2016/01/16

2016/01/16

2016/01/16

VCC1R0_SUS

1

1

R597
1K_0402_1%

@

2

2

C70

0.1U_0402_25V6-K

@

1

JXDP1

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

MOLEX_52435-2671

@

Title

Title

Title

XDP CONNECTOR

XDP CONNECTOR

XDP CONNECTOR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

28

GND_2

27

GND_1

WALTER

WALTER

WALTER

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

24 116

24 116

1

24 116

D

C

B

A

0.1Custom

0.1Custom

0.1Custom

of

of

of

5

4

3

2

1

Payton Common

D

C

JRTC1

1

1

2

2

3

GND1

4

GND2

HIGHS_WS33021-S0351-HF

@

6/29 Change diode and Res.

VCC3SW

VCC3SW

1

2

1

2

R10043

3.01K_0402_1%

R10044
43K_0402_1%

2

R107
1K_0402_5%

1

D3

2

RB520CS-30GT2RA_VMN2-2

1

D290
RB520CM-30T2R_VMN2M2

1 2

@

2

D2
RB520CM-30T2R_VMN2M2

1

RTCVCC

1

20K_0402_5%

RTCVCC must be less than 3.2V from SKL.

1

C71
1U_0402_10V6K

2

R108

2

1

C72
1U_0402_10V6K

2

-RTCRST

2

1

JCMOS
SHORT PADS

@

D

C

-RTCRST <17>

R109

2

1

20K_0402_5%

2015/07/16

2015/07/16

2015/07/16

1

C73
1U_0402_10V6K

2

B

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

-SRTCRST

JME
SHORT PADS

@

1 2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

-SRTCRST <17>

2016/01/16

2016/01/16

2016/01/16

2

Title

Title

Title

RTC BATTERY

RTC BATTERY

RTC BATTERY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

25 116

of

25 116

of

25 116

B

A

0.1

0.1

0.1

5

Payton Common

4

3

2

1

D

C

B

PRE ES1
ES1/ES2

AFTER QS

R110 R598 U5

NO ASM

ASM

ASM

NO ASM

SPI_MOSI_IO0<14,82>

QE="1"

QE= Don't
Care

SPI_IO3<14>

SPI_CLK<14,82>

R592

ASM

NO ASM

SPI_CLK

SPI_MOSI_IO0

R358

ASM

NO ASM

1

R592

@

1K_0402_1%

2

1

R113 15_0402_5%

1

R115 15_0402_5%

1

R117 15_0402_5%

1

R598

@

1K_0402_1%

2

D

LOGIC

VCC3_SUS

2

D4
RB520CS-30GT2RA_VMN2-2

1

VCC3_SUS_SPI

1

1

2

0.1U_0402_25V6-K

2

2

2

C74

C75

2

0.1U_0402_25V6-K

SPI_IO3_RSPI_IO3

SPI_CLK_R

SPI_MOSI_IO0_R

1

R110
1K_0402_1%

2

2

R9990
0_0402_5%

1

1

C9356

0.1U_0402_10V6-K

2

U5

8

VCC

7

HOLD#

6

CLK

5

DI

W25Q128FVSIQ_SO8

@

EMI

@

1

CS#

2

DO

3

WP#

4

GND

TABLE

SF100 PIN HEADER INTERFACE (TOP VIEW)

1

VCC
CS#
MISO
(KEY)

D12.1
R322.2
R694.2
N/A

3
5
7

VCC3_SUS_SPI

-SPI_CS0_R

SPI_MISO_IO1_R

SPI_IO2_R

GND
R681.2
R674.2
N/A

1

R111
1K_0402_1%

2

1

R112 0_0402_5%

R114 15_0402_5%

R116 15_0402_5%

NOTE:

Pull-down on SPI_IO2 is placed on page-24

GND

2

CLK

4

MOSI

6

(RESET)

8

2

1

2

1

2

-SPI_CS0

SPI_MISO_IO1

SPI_IO2

1

R358
1K_0402_1%

2

@

C

-SPI_CS0 <14>

SPI_MISO_IO1 <14,82>

SPI_IO2 <14,24>

B

U5 SPI ROM

vPRO model(16MB)

WINBOND W25Q128FVSIQ
MACRONIX MX25L12873FM2I-10G
MICRON N25Q128A13ESEDFF

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

SPI FLASH

SPI FLASH

SPI FLASH

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

1

of

26 116

of

26 116

of

26 116

A

0.1

0.1

0.1

5

M_A_DQ[0..63] <3,28>

M_A_A[0..9] <3,28>

-M_A_DQS[0..7] <3,28>

M_A_DQS[0..7] <3,28>

VCC1R2A

D

M_A_VREF_CA_CPU

C

B

A

R546

1

2_0402_1%

1

C688

0.022U_0402_25V7-K

2

1

R553

24.9_0402_1%

2

M_A_CB5<3,28>

M_A_CB0<3,28>

-M_A_DQS8<3,28>

M_A_DQS8<3,28>

M_A_CB3<3,28>

M_A_CB2<3,28>

M_A_CKE0<3>

M_A_BG1<3,28>

M_A_BG0<3,28>

M_A_A12<3,28>

2

1

R542
1K_0402_1%

2

M_A_VREF_CA_CHA_DIMM

1

R548
1K_0402_1%

2

M_A_DQ4

M_A_DQ0

-M_A_DQS0

M_A_DQS0

M_A_DQ7

M_A_DQ3

M_A_DQ13

M_A_DQ12

M_A_DQ15

M_A_DQ14

M_A_DQ21

M_A_DQ20

-M_A_DQS2

M_A_DQS2

M_A_DQ22

M_A_DQ18

M_A_DQ29

M_A_DQ28

M_A_DQ27

M_A_DQ30

M_A_CB5 M_A_CB4

M_A_CB0

-M_A_DQS8

M_A_DQS8

M_A_CB3

M_A_CB2

M_A_CKE0

M_A_BG1

M_A_BG0

M_A_A12

M_A_A9

M_A_A8

M_A_A6

12

C885

0.1U_0402_16V7-K

VCC1R2A

VCC1R2A VCC1R2A

Payton Common

5

JDIMM1A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4RB-7H

@

VCC1R2A

1

C76

2

10U_0402_6.3V6-M

1

C91

2

1U_0402_6.3V6-K

VSS_2

VSS_4

VSS_6

DM0_n/DBI0_n

VSS_7

VSS_9

VSS_11

VSS_13

VSS_15

DQS1_c

DQS1_t

VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

DM2_n/DBl2_n

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35

DQS3_c

DQS3_t

VSS_38

VSS_40

VSS_42
CB4/NC

VSS_44

CB0/NC

VSS_46

DBI8_n/DBI_n/NC

VSS_47
CB6/NC

VSS_49

CB7/NC

VSS_51

RESET_n

VDD_2
ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

DQ4

DQ0

DQ6

DQ2

DQ12

DQ8

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1

4

1

1

1

1

C80

C81

C82

2

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C95

C96

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_A_CB4 <3,28>

M_A_CB1 <3,28>

M_A_CB7 <3,28>

M_A_CB6 <3,28>

-DRAMRST <17,28,29,30>

M_A_CKE1 <3>

-M_A_ACT <3,28>

-M_A_ALERT <3,28>

M_A_A11 <3,28>

@

1

C689

2

0.1U_0402_10V7-K

C83

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C98

C97

1U_0402_6.3V6-K

1U_0402_6.3V6-K

4

1

C78

2

C93

VCC1R2A

10U_0402_6.3V6-M

1U_0402_6.3V6-K

1

C79

2

10U_0402_6.3V6-M

C94

1U_0402_6.3V6-K

M_A_DQ1

M_A_DQ5

M_A_DQ6

M_A_DQ2

M_A_DQ9

M_A_DQ8

-M_A_DQS1

M_A_DQS1

M_A_DQ10

M_A_DQ11

M_A_DQ16

M_A_DQ17

M_A_DQ19

M_A_DQ23

M_A_DQ24

M_A_DQ25

-M_A_DQS3

M_A_DQS3

M_A_DQ26

M_A_DQ31

M_A_CB1

M_A_CB7

M_A_CB6

-DRAMRST

M_A_CKE1

-M_A_ACT

-M_A_ALERT

M_A_A11

M_A_A7

M_A_A5

M_A_A4

1

C77

2

10U_0402_6.3V6-M

C92

1U_0402_6.3V6-K

2

4

6

8

10

12

14
16

18

20

22
24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66
68

70
72

74

76

78

80

82

84

86
88

90

92

94

96

98

100

102

104

106

108

110

112
114

116

118

120

A11

122

A7

124

126

A5

128

A4

130

3

VCC2R5A

1

1

C84

3

10U_0402_6.3V6-M

VCC3B

C85

2

M_A_PARITY<3,28>

M_A_BA1<3,28>

-M_A_CS0<3>

M_A_A14_WE_N<3,28>

M_A_ODT0<3>

-M_A_CS1<3>

M_A_ODT1<3>

SMB_CLK_3B<28,29,30,79,83>

1 2

0_0402_5%

10U_0402_6.3V6-M

R124

2

1

+

C99

@

2

330U_D2_2VM_R9M

M_A_DDRCLK0_2400M<3>

-M_A_DDRCLK0_2400M<3>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C87

C86

1U_0402_6.3V6-K

M_A_DDRCLK0_2400M

-M_A_DDRCLK0_2400M

1

2

2015/07/16

2015/07/16

2015/07/16

1U_0402_6.3V6-K

M_A_A14_WE_N

C100

VCC0R6B

1

C88

2

VCC2R5A

VCC1R2A

M_A_A3

M_A_A1

M_A_PARITY

M_A_BA1

-M_A_CS0

M_A_ODT0

-M_A_CS1

M_A_ODT1

M_A_DQ33

M_A_DQ37

-M_A_DQS4

M_A_DQS4

M_A_DQ38

M_A_DQ39

M_A_DQ44

M_A_DQ41

M_A_DQ43

M_A_DQ46

M_A_DQ50

M_A_DQ52

-M_A_DQS6

M_A_DQS6

M_A_DQ54

M_A_DQ51

M_A_DQ57

M_A_DQ61

M_A_DQ62

M_A_DQ58

SMB_CLK_3B

1

C101

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

2

10U_0402_6.3V6-M

VCC1R2A

2

C89

C90

10U_0402_6.3V6-M

JDIMM1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4RB-7H

@

2

1U_0402_6.3V6-K

EVENT_n/NF

C0/CS2_n/NC

DM4_n/DBl4_n

DM6_n/DBl6_n

2016/01/16

2016/01/16

2016/01/16

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

VREFCA

VSS_54

VSS_56

VSS_58

VSS_59

VSS_61

VSS_63

VSS_65

VSS_67

DQS5_c

DQS5_t

VSS_70

VSS_72

VSS_74

VSS_76

VSS_78

VSS_79

VSS_81

VSS_83

VSS_85

VSS_87

DQS7_c

DQS7_t

VSS_90

VSS_92

VSS_94

GND_2

DQ36

DQ32

DQ39

DQ35

DQ45

DQ41

DQ47

DQ43

DQ53

DQ48

DQ54

DQ50

DQ60

DQ57

DQ63

DQ59

BA0

A13

SA2

SDA

SA0

SA1

A2

A0

Vtt

1

VCC3B

1

2

12

R118
0_0402_5%

@

SA0_CHA_P

R121
0_0402_5%

VCC3B

1

R119
0_0402_5%

@

2

SA1_CHA_P SA2_CHA_P

1

R122
0_0402_5%

2

SPD Address = 0H

VCC1R2A VCC0R6B

132

134

136

138

140

142

144

146
148

150

152

154

156

158

160

162

164
166

168
170

172
174

176

178

180

182
184

186

188

190

192

194

196

198

200

202

204

206

208

210

212

214

216

218

220

222

224

226

228

230

232

234

236
238

240
242

244

246

248
250

252

254

256

258

260

262

M_A_A2

M_A_DDRCLK1_2400M

-M_A_DDRCLK1_2400M

M_A_A0

M_A_A10_AP

M_A_BA0

M_A_A16_RAS_N

M_A_A15_CAS_N

M_A_A13

M_A_VREF_CA_CHA_DIMM

SA2_CHA_P

M_A_DQ36

M_A_DQ32

M_A_DQ35

M_A_DQ34

M_A_DQ40

M_A_DQ45

-M_A_DQS5
M_A_DQS5

M_A_DQ47

M_A_DQ42

M_A_DQ48

M_A_DQ49

M_A_DQ53

M_A_DQ55

M_A_DQ56

M_A_DQ60

-M_A_DQS7

M_A_DQS7

M_A_DQ59

M_A_DQ63

SMB_DATA_3B

SA0_CHA_P

SA1_CHA_P

Title

Title

Title

DDR4 CH-A PRIMARY

DDR4 CH-A PRIMARY

DDR4 CH-A PRIMARY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

VCC1R2A

2

R555
240_0402_1%

1

M_A_DDRCLK1_2400M <3>

-M_A_DDRCLK1_2400M <3>

M_A_A10_AP <3,28>

M_A_BA0 <3,28>

M_A_A16_RAS_N <3,28>

M_A_A15_CAS_N <3,28>

M_A_A13 <3,28>

M_A_VREF_CA_CHA_DIMM <28>

VCC1R2A

@

VCC1R2A

SMB_DATA_3B <28,29,30,79,83>

1

VCC3B

1

R120
0_0402_5%

@

2

1

R123
0_0402_5%

2

1

C692

2

2.2U_0402_6.3V6-M

of

27 116

of

27 116

of

27 116

D

C

2

C691

1

0.1U_0402_10V7-K

B

A

0.1Custom

0.1Custom

0.1Custom

5

M_A_DQ[0..63] <3,27>

M_A_A[0..9] <3,27>

-M_A_DQS[0..7] <3,27>

M_A_DQS[0..7] <3,27>

D

VCC1R2A VCC1R2A

VCC1R2A

M_A_DQ4

C

B

M_A_CB5<3,27>

M_A_CB0<3,27>

-M_A_DQS8<3,27>

M_A_DQS8<3,27>

M_A_CB3<3,27>

M_A_CB2<3,27>

M_A_CKE2<3>

M_A_BG1<3,27>

M_A_BG0<3,27>

M_A_A12<3,27>

A

M_A_DQ0

-M_A_DQS0

M_A_DQS0

M_A_DQ7

M_A_DQ3

M_A_DQ13

M_A_DQ12

M_A_DQ15

M_A_DQ14

M_A_DQ21

M_A_DQ20

-M_A_DQS2

M_A_DQS2

M_A_DQ22

M_A_DQ18

M_A_DQ29

M_A_DQ28

M_A_DQ27

M_A_DQ30

M_A_CB5

M_A_CB0

-M_A_DQS8

M_A_DQS8

M_A_CB3

M_A_CB2

M_A_CKE2

M_A_BG1

M_A_BG0

M_A_A12

M_A_A9

M_A_A8

M_A_A6

VCC1R2A

JDIMM2A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4SB-7H

@

1

C102

2

10U_0402_6.3V6-M

C117

1U_0402_6.3V6-K

DM0_n/DBIO_n

DM2_n/DBl2_n

RESET_n

ALERT_n

VSS_11

VSS_13

VSS_15

DQS1_c

DQS1_t

VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35

DQS3_c

DQS3_t

VSS_38

VSS_40

VSS_42

CB4/NC

VSS_44
CB0/NC

VSS_46

VSS_47

CB6/NC

VSS_49

CB7/NC

VSS_51

1

2

VSS_2

DQ4

VSS_4

DQ0

VSS_6

VSS_7

DQ6

VSS_9

DQ2

DQ12

DQ8

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

DBI8_n

CKE1

VDD_2

ACT_n

VDD_4

VDD_6

VDD_8

4

1

1

1

1

C103

C104

C105

C106

2

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C123

C119

C118

1U_0402_6.3V6-K

1U_0402_6.3V6-K

1U_0402_6.3V6-K

VCC1R2A

2

4

6
8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40
42

44

46

48

50

52

54

56
58

60

62

64

66
68

70

72

74

76

78

80

82

84

86

88

90
92

94

96

98

100

102

104

106

108
110

112
114

116
118

120

A11

122

A7

124

126

A5

128

A4

130

M_A_DQ1

M_A_DQ5

M_A_DQ6

M_A_DQ2

M_A_DQ9

M_A_DQ8

-M_A_DQS1

M_A_DQS1

M_A_DQ10

M_A_DQ11

M_A_DQ16

M_A_DQ17

M_A_DQ19

M_A_DQ23

M_A_DQ24

M_A_DQ25

-M_A_DQS3

M_A_DQS3

M_A_DQ26

M_A_DQ31

M_A_CB4

M_A_CB1

M_A_CB7

M_A_CB6

-DRAMRST

M_A_CKE3

-M_A_ACT

-M_A_ALERT

M_A_A11

M_A_A7

M_A_A5

M_A_A4

C107

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C124

C120

1U_0402_6.3V6-K

1U_0402_6.3V6-K

1

1

C109

C108

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C125

C121

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_A_CB4 <3,27>

M_A_CB1 <3,27>

M_A_CB7 <3,27>

M_A_CB6 <3,27>

-DRAMRST <17,27,29,30>

M_A_CKE3 <3>

-M_A_ACT <3,27>

-M_A_ALERT <3,27>

M_A_A11 <3,27>

VCC2R5A

1

2

M_A_DDRCLK2_2400M<3>

-M_A_DDRCLK2_2400M<3>

M_A_PARITY<3,27>

M_A_BA1<3,27>

-M_A_CS2<3>

M_A_A14_WE_N<3,27>

M_A_ODT2<3>

-M_A_CS3<3>

M_A_ODT3<3>

3

1

C110

C111

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

SMB_CLK_3B<27,29,30,79,83>

VCC3B

R131

1

0_0402_5%

C113

C112

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_A_A3

M_A_A1

M_A_DDRCLK2_2400M

-M_A_DDRCLK2_2400M

M_A_PARITY

M_A_BA1

-M_A_CS2

M_A_A14_WE_N M_A_A16_RAS_N

M_A_ODT2

-M_A_CS3

M_A_ODT3

1

2

2

C126

0.1U_0402_10V7-K

VCC0R6B

VCC1R2A

M_A_DQ33

M_A_DQ37

-M_A_DQS4

M_A_DQS4

M_A_DQ38

M_A_DQ39

M_A_DQ44

M_A_DQ41

M_A_DQ43

M_A_DQ46

M_A_DQ50

M_A_DQ52

-M_A_DQS6

M_A_DQS6

M_A_DQ54

M_A_DQ51

M_A_DQ57

M_A_DQ61

M_A_DQ62

M_A_DQ58

SMB_CLK_3B

1

C127

2

2.2U_0402_6.3V6-M

1

C114

2

VCC2R5A

10U_0402_6.3V6-M

1

C115

2

VCC1R2A

2

C116

1U_0402_6.3V6-K

10U_0402_6.3V6-M

JDIMM2B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4SB-7H

@

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t

VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

DM6_n/DBl6_n

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t

VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

VCC3B

SPD ADDRESS = 1H

VCC1R2A

VCC0R6B

132

A2

134

136

138

140
142

144

A0

146

148
150

BA0

152

154

156

158

A13

160

162

164

166

RFU

168

170

172

174

176

178

180

182

184

186

188

190

192
194

196
198

200

202

204

206

208

210

212
214
216
218

220

222

224

226
228

230
232

234

236

238

240

242

244

246

248
250

252
254

SDA

256

SA0

258

Vtt

260

SA1

262

1

R125
0_0402_5%

2

SA0_CHA_S

1

R128
0_0402_5%

@

2

M_A_A2

M_A_DDRCLK3_2400M

-M_A_DDRCLK3_2400M

M_A_A0

M_A_A10_AP

M_A_BA0

M_A_A15_CAS_N

M_A_A13

M_A_VREF_CA_CHA_DIMM

SA2_CHA_S

M_A_DQ36

M_A_DQ32

M_A_DQ35

M_A_DQ34

M_A_DQ40

M_A_DQ45

-M_A_DQS5

M_A_DQS5

M_A_DQ47

M_A_DQ42

M_A_DQ48

M_A_DQ49

M_A_DQ53

M_A_DQ55

M_A_DQ56

M_A_DQ60

-M_A_DQS7

M_A_DQS7

M_A_DQ59

M_A_DQ63

SMB_DATA_3B

SA0_CHA_S

SA1_CHA_S

1

VCC3B

1

R126
0_0402_5%

@

2

SA1_CHA_S

1

R129
0_0402_5%

2

VCC1R2A

1

R556
240_0402_1%

2

M_A_A10_AP <3,27>

M_A_BA0 <3,27>

M_A_A16_RAS_N <3,27>

M_A_A15_CAS_N <3,27>

M_A_A13 <3,27>

VCC1R2A

VCC1R2A

SMB_DATA_3B <27,29,30,79,83>

VCC3B

M_A_DDRCLK3_2400M <3>

-M_A_DDRCLK3_2400M <3>

M_A_VREF_CA_CHA_DIMM <27>

1

@

C694

2

2.2U_0402_6.3V6-M

1

R127
0_0402_5%

@

2

1

R130
0_0402_5%

2

2

C693

1

SA2_CHA_S

D

C

0.1U_0402_10V7-K

B

A

Payton Common

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

DDR4 CH-A SECONDARY

DDR4 CH-A SECONDARY

DDR4 CH-A SECONDARY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet

Tuesday, December 13, 2016

1

28 116

28 116

of

28 116

0.1Custom

0.1Custom

0.1Custom

D

M_B_VREF_DQ_CPU <4>

12

C

B

A

R550

1

2_0402_1%

1

C687

0.022U_0402_25V7-K

2

R552

24.9_0402_1%

M_B_CB2<4,30>

M_B_CB6<4,30>

-M_B_DQS8<4,30>

M_B_DQS8<4,30>

M_B_CB7<4,30>

M_B_CB1<4,30>

M_B_CKE0<4>

M_B_BG1<4,30>
M_B_BG0<4,30>

M_B_A12<4,30>

5

2

M_B_DQ[0..63] <4,30>

M_B_A[0..9] <4,30>

-M_B_DQS[0..7] <4,30>

M_B_DQS[0..7] <4,30>

VCC1R2A

1

R549
1K_0402_1%

2

M_B_VREF_CA_CHB_DIMM

1

R551
1K_0402_1%

2

M_B_DQ2

M_B_DQ5

-M_B_DQS0

M_B_DQS0

M_B_DQ6

M_B_DQ3

M_B_DQ10

M_B_DQ14

M_B_DQ12

M_B_DQ13

M_B_DQ22

M_B_DQ18

-M_B_DQS2
M_B_DQS2

M_B_DQ20

M_B_DQ19

M_B_DQ27

M_B_DQ31

M_B_DQ30

M_B_DQ24

M_B_CB2

M_B_CB6

-M_B_DQS8

M_B_DQS8

M_B_CB7

M_B_CB1

M_B_CKE0

M_B_BG1

M_B_BG0

M_B_A12

M_B_A9

M_B_A8

M_B_A6

1

C686

0.1U_0402_16V7-K

2

VCC1R2A

VCC1R2A VCC1R2A

VCC1R2A

JDIMM3A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A827-H8RB-7H

@

1

C128

2

10U_0402_6.3V6-M

C143

1U_0402_6.3V6-K

DM0_n/DBIO_n

DM2_n/DBl2_n

RESET_n

ALERT_n

1

2

VSS_2

DQ4

VSS_4

DQ0

VSS_6

VSS_7

DQ6

VSS_9

DQ2

VSS_11

DQ12

VSS_13

DQ8

VSS_15

DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24

VSS_35

DQS3_c

DQS3_t

VSS_38

DQ31

VSS_40

DQ27

VSS_42

CB4/NC

VSS_44

CB0/NC

VSS_46

DBI8_n

VSS_47

CB6/NC

VSS_49
CB7/NC

VSS_51

CKE1

VDD_2

ACT_n

VDD_4

VDD_6

VDD_8

C129

10U_0402_6.3V6-M

C144

1U_0402_6.3V6-K

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34
36

38

40

42

44

46

48

50
52

54

56

58

60
62

64

66

68

70

72

74

76

78

80

82

84
86

88

90

92

94

96

98

100

102
104

106
108

110
112

114

116

118

120

A11

122

A7

124

126

A5

128

A4

130

4

1

1

C130

2

10U_0402_6.3V6-M

C145

1U_0402_6.3V6-K

VCC1R2A

C131

2

C146

M_B_DQ4

M_B_DQ0

M_B_DQ1

M_B_DQ7

M_B_DQ8

M_B_DQ9

-M_B_DQS1

M_B_DQS1

M_B_DQ11

M_B_DQ15

M_B_DQ17

M_B_DQ16

M_B_DQ23

M_B_DQ21

M_B_DQ28

M_B_DQ25

-M_B_DQS3

M_B_DQS3

M_B_DQ26

M_B_DQ29

M_B_CB4

M_B_CB3

M_B_CB5

M_B_CB0

-DRAMRST

M_B_CKE1

-M_B_ACT

-M_B_ALERT

M_B_A11

M_B_A7

M_B_A5

M_B_A4

1

1

1

1

C132

C133

C134

2

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C148

C147

1U_0402_6.3V6-K

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_B_CB4 <4,30>

M_B_CB3 <4,30>

M_B_CB5 <4,30>

M_B_CB0 <4,30>

-DRAMRST <17,27,28,30>

M_B_CKE1 <4>

-M_B_ACT <4,30>

-M_B_ALERT <4,30>

M_B_A11 <4,30>

@

1

C690

2

0.1U_0402_10V7-K

C135

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C150

C149

1U_0402_6.3V6-K

1U_0402_6.3V6-K

VCC2R5A

1

+

@

2

3

1

1

C138

1U_0402_6.3V6-K

2

C139

1U_0402_6.3V6-K

M_B_DDRCLK0_2400M

-M_B_DDRCLK0_2400M

1

2

C137

C136

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C151

330U_D2_2VM_R9M

M_B_DDRCLK0_2400M<4>

-M_B_DDRCLK0_2400M<4>

VCC3B

M_B_PARITY<4,30>

M_B_BA1<4,30>

-M_B_CS0<4>

M_B_A14_WE_N<4,30>

M_B_ODT0<4>

-M_B_CS1<4>

M_B_ODT1<4>

SMB_CLK_3B<27,28,30,79,83>

1

0_0402_5%

R138

M_B_A3

M_B_A1

M_B_PARITY

M_B_BA1

-M_B_CS0

M_B_A14_WE_N

M_B_ODT0

-M_B_CS1

M_B_ODT1

M_B_DQ38

M_B_DQ35

-M_B_DQS4

M_B_DQS4

M_B_DQ33

M_B_DQ32

M_B_DQ40

M_B_DQ41

M_B_DQ42

M_B_DQ46

M_B_DQ52

M_B_DQ48

-M_B_DQS6

M_B_DQS6

M_B_DQ50

M_B_DQ51

M_B_DQ57

M_B_DQ61

M_B_DQ56

M_B_DQ60

SMB_CLK_3B

1

C152

2

0.1U_0402_10V7-K

VCC0R6B

VCC2R5A

VCC1R2A

C153

2.2U_0402_6.3V6-M

1

1

C140

2

2

10U_0402_6.3V6-M

VCC1R2A

C141

10U_0402_6.3V6-M

JDIMM3B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A827-H8RB-7H

@

2

VCC3B

1

R132
0_0402_5%

C142

1U_0402_6.3V6-K

2

1

2

@

SA0_CHB_P

R135
0_0402_5%

VCC3B

1

2

R136
0_0402_5%

1

R133
0_0402_5%

@

2

1

SA1_CHB_P

VCC3B

1

2

1

2

R134
0_0402_5%

@

SA2_CHB_P

R137
0_0402_5%

D

SPD Address = 2H

VCC1R2A

1

R557
240_0402_1%

2

M_B_DDRCLK1_2400M <4>

-M_B_DDRCLK1_2400M <4>

M_B_A10_AP <4,30>

M_B_BA0 <4,30>

M_B_A16_RAS_N <4,30>

M_B_A15_CAS_N <4,30>

M_B_A13 <4,30>

M_B_VREF_CA_CHB_DIMM <30>

VCC1R2A

1

@

2

VCC1R2A

SMB_DATA_3B <27,28,30,79,83>

C

1

C695

C696

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

B

A

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t

VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

DM6_n/DBl6_n

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c
DQS7_t

VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

BA0

RFU

SDA

VCC1R2A

VCC0R6B

132

A2

134

136
138

140

142

144

A0

146

148

150

152

154

156

158

A13

160

162

164

166

168

170
172

174

176

178
180

182

184

186

188

190

192

194

196

198

200

202

204

206

208

210

212

214

216

218

220

222

224

226

228

230

232

234

236

238

240
242

244

246

248
250

252
254
256

SA0

258

Vtt

260

SA1

262

M_B_A2

M_B_DDRCLK1_2400M

-M_B_DDRCLK1_2400M

M_B_A0

M_B_A10_AP

M_B_BA0

M_B_A16_RAS_N

M_B_A15_CAS_N

M_B_A13

M_B_VREF_CA_CHB_DIMM

SA2_CHB_P

M_B_DQ34

M_B_DQ39

M_B_DQ36

M_B_DQ37

M_B_DQ44

M_B_DQ45

-M_B_DQS5

M_B_DQS5

M_B_DQ47

M_B_DQ43

M_B_DQ54

M_B_DQ55

M_B_DQ53

M_B_DQ49

M_B_DQ59

M_B_DQ62

-M_B_DQS7

M_B_DQS7

M_B_DQ63

M_B_DQ58

SMB_DATA_3B

SA0_CHB_P

SA1_CHB_P

Payton Common

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

DDR4 CH-B PRIMARY

DDR4 CH-B PRIMARY

DDR4 CH-B PRIMARY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet

Date: Sheet

Date: Sheet

Tuesday, December 13, 2016

of

29 116

of

29 116

of

1

29 116

0.1Custom

0.1Custom

0.1Custom

5

M_B_DQ[0..63] <4,29>

M_B_A[0..9] <4,29>

-M_B_DQS[0..7] <4,29>

M_B_DQS[0..7] <4,29>

D

VCC1R2A VCC1R2A

VCC1R2A

M_B_DQ2

C

B

M_B_CB2<4,29>

M_B_CB6<4,29>

-M_B_DQS8<4,29>

M_B_DQS8<4,29>

M_B_CB7<4,29>

M_B_CB1<4,29>

M_B_CKE2<4>

M_B_BG1<4,29>

M_B_BG0<4,29>

M_B_A12<4,29>

A

M_B_DQ5

-M_B_DQS0

M_B_DQS0

M_B_DQ6

M_B_DQ3

M_B_DQ10

M_B_DQ14

M_B_DQ12

M_B_DQ13

M_B_DQ22

M_B_DQ18

-M_B_DQS2

M_B_DQS2

M_B_DQ20

M_B_DQ19

M_B_DQ27

M_B_DQ31

M_B_DQ30

M_B_DQ24

M_B_CB2

M_B_CB6

-M_B_DQS8

M_B_DQS8

M_B_CB7

M_B_CB1

M_B_CKE2

M_B_BG1

M_B_BG0

M_B_A12

M_B_A9

M_B_A8

M_B_A6

VCC1R2A

1

2

JDIMM4A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4RB-7H

@

C154

10U_0402_6.3V6-M

C169

1U_0402_6.3V6-K

DM0_n/DBl0_n

DM2_n/DBl2_n

DM8_n/DBl8_n/NC

1

C155

2

C170

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15

DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24

VSS_35

DQS3_c

DQS3_t

VSS_38

DQ31

VSS_40

DQ27

VSS_42

CB4/NC

VSS_44

CB0/NC

VSS_46

VSS_47
CB6/NC

VSS_49
CB7/NC

VSS_51

RESET_n

CKE1

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

DQ4

DQ0

DQ6

DQ2

DQ8

4

1

1

C156

C157

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

1U_0402_6.3V6-K

2

4

6

8

10

12

14

16

18

20

22

24

26
28

30

32

34

36

38

40

42
44

46

48

50

52
54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94
96

98
100

102
104

106

108

110

112
114

116

118

120

A11

122

A7

124

126

A5

128

A4

130

10U_0402_6.3V6-M

C172

C171

1U_0402_6.3V6-K

1U_0402_6.3V6-K

1

C158

2

C173

VCC1R2A

M_B_DQ4

M_B_DQ0

M_B_DQ1

M_B_DQ7

M_B_DQ8

M_B_DQ9

-M_B_DQS1

M_B_DQS1

M_B_DQ11

M_B_DQ15

M_B_DQ17

M_B_DQ16

M_B_DQ23

M_B_DQ21

M_B_DQ28

M_B_DQ25

-M_B_DQS3

M_B_DQS3

M_B_DQ26

M_B_DQ29

M_B_CB4

M_B_CB3

M_B_CB5

M_B_CB0

-DRAMRST
M_B_CKE3

-M_B_ACT

-M_B_ALERT

M_B_A11
M_B_A7

M_B_A5

M_B_A4

1

C159

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C174

1U_0402_6.3V6-K

1U_0402_6.3V6-K

1

1

C161

C160

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

C175

C176

1U_0402_6.3V6-K

1U_0402_6.3V6-K

M_B_CB4 <4,29>

M_B_CB3 <4,29>

M_B_CB5 <4,29>

M_B_CB0 <4,29>

-DRAMRST <17,27,28,29>

M_B_CKE3 <4>

-M_B_ACT <4,29>

-M_B_ALERT <4,29>

M_B_A11 <4,29>

VCC2R5A

M_B_DDRCLK2_2400M<4>

-M_B_DDRCLK2_2400M<4>

M_B_PARITY<4,29>

M_B_BA1<4,29>

-M_B_CS2<4>

M_B_A14_WE_N<4,29>

M_B_ODT2<4>

-M_B_CS3<4>

M_B_ODT3<4>

3

1

1

C162

C163

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

SMB_CLK_3B<27,28,29,79,83>

VCC3B

R145

1

0_0402_5%

C165

C164

1U_0402_6.3V6-K

1U_0402_6.3V6-K

1

2

2

VCC0R6B

VCC2R5A

VCC1R2A

M_B_A3

M_B_A1

M_B_DDRCLK2_2400M

-M_B_DDRCLK2_2400M

M_B_PARITY

M_B_BA1

-M_B_CS2

M_B_A14_WE_N

M_B_ODT2

-M_B_CS3

M_B_ODT3

M_B_DQ38

M_B_DQ35

-M_B_DQS4

M_B_DQS4

M_B_DQ33

M_B_DQ32

M_B_DQ40

M_B_DQ41

M_B_DQ42

M_B_DQ46

M_B_DQ52

M_B_DQ48

-M_B_DQS6

M_B_DQS6

M_B_DQ50

M_B_DQ51

M_B_DQ57

M_B_DQ61

M_B_DQ56

M_B_DQ60

SMB_CLK_3B

1

C178

C179

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

1

C166

2

10U_0402_6.3V6-M

1

C167

2

VCC1R2A

2

C168

1U_0402_6.3V6-K

10U_0402_6.3V6-M

JDIMM4B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

A14/WE_n

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQS5

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4RB-7H

@

EVENT_n/NF

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t

VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

DM6_n/DBl6_n

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c
DQS7_t

VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

SPD ADDRESS = 3H

VCC1R2A

VCC0R6B

132

A2

134

136

138

140

142

144

A0

146

148

150

BA0

152

154

156

158

A13

160

162
164

166

SA2

168

170
172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

202

204

206

208

210

212

214
216

218

220

222

224

226

228

230

232

234

236

238

240
242

244

246

248

250

252

254

SDA

256

SA0

258

VTT

260

SA1

262

VCC3B

1

R139
0_0402_5%

2

SA0_CHB_S

1

R142
0_0402_5%

@

2

M_B_A2

M_B_DDRCLK3_2400M

-M_B_DDRCLK3_2400M

M_B_A0

M_B_A10_AP

M_B_BA0

M_B_A16_RAS_N

M_B_A15_CAS_N

M_B_A13

M_B_VREF_CA_CHB_DIMM

SA2_CHB_S

M_B_DQ34

M_B_DQ39

M_B_DQ36

M_B_DQ37

M_B_DQ44

M_B_DQ45

-M_B_DQS5
M_B_DQS5

M_B_DQ47

M_B_DQ43

M_B_DQ54

M_B_DQ55

M_B_DQ53

M_B_DQ49

M_B_DQ59

M_B_DQ62

-M_B_DQS7
M_B_DQS7

M_B_DQ63

M_B_DQ58

SMB_DATA_3B

SA0_CHB_S

SA1_CHB_S

1

VCC3B

1

R140
0_0402_5%

2

SA1_CHB_S

1

R143
0_0402_5%

@

2

VCC1R2A

1

R558
240_0402_1%

2

VCC1R2A

VCC1R2A

SMB_DATA_3B <27,28,29,79,83>

VCC3B

M_B_DDRCLK3_2400M <4>

-M_B_DDRCLK3_2400M <4>

M_B_A10_AP <4,29>

M_B_BA0 <4,29>

M_B_A16_RAS_N <4,29>

M_B_A15_CAS_N <4,29>

M_B_A13 <4,29>

M_B_VREF_CA_CHB_DIMM <29>

@

1

R141
0_0402_5%

@

2

1

2

1

2

SA2_CHB_S

R144
0_0402_5%

C698

2.2U_0402_6.3V6-M

D

C

2

C697

1

0.1U_0402_10V7-K

B

A

Payton Common

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

2015/07/16

2015/07/16

2015/07/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/01/16

2016/01/16

2016/01/16

Title

DDR4 CH-B SECONDARY

DDR4 CH-B SECONDARY

DDR4 CH-B SECONDARY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Tuesday, December 13, 2016

Tuesday, December 13, 2016

Date: Sheet of

Date: Sheet of

Date: Sheet

Tuesday, December 13, 2016

1

30 116

30 116

of

30 116

0.1Custom

0.1Custom

0.1Custom