Lenovo ThinkPad Edge E550 Schematics

A

1 1

B

C

D

E

LCFC Confidential

2 2

NM-A221 Rev1.0 Schematic

Intel Crescent Bay Processor with DDRIIIL + Wild Cat Point PCH

3 3

4 4

A

AMD Opal-XT/ Jet-XT

2013-09-07 Rev1.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/09/07

2014/09/07

2014/09/07

Title

Title

Title

COVER PAGE

COVER PAGE

COVER PAGE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet

Date: Sheet

Date: Sheet

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

E

of

of

of

1 81

1 81

1 81

1.0

1.0

1.0

A

B

C

D

E

eDP Conn.

USB Port 7

DP Port 0

Page 38

1 1

5V 480MHzUSB 2.0 Port 2 & 3

USB 2.0 Port 7

DP Port0

OneLink board

Page 34

DP Repeater

On OneLink board

HDMI Conn.

Page 46

VGA Conn

2 2

RJ45 Conn.

Page 48

5V 5GT/sUSB 3.0 Port 4

DDI1 HDMI

DDI2 DP

Traslater to
CRT

Intel
WGI218V-QQJZ Non Vpro
WGI218LM QQJY Vpro
QFN48_6X6

MUX

Page 42

Page 43Page 44

PCIe port 4

Page 47

DDI1

DDI1

DDI2 DP

PCIe Gen1 Port 4

Broad Well

Intel

Crescent Bay

Processor

BGA1168

40mm*24mm

+

Intel WPT Point

Memory BUS (DDRIII)
1DPC (Interleaved)

1.35V DDRIIIL 1333/1600 MT/s

PCIE Port 5

USB 2.0 Port 0,1
5V 480MHz

USB 3.0 Port1,2

5V 5GT/s

PCIe Gen1 Port 3

SATA Gen3 Port 1

USB 2.0 port 4&6

JUSB1

USB 3.0 Port 2
USB 2.0 Port 1

NGFF Card WLAN

USB Left

Page 41

NGFF Card

PCIe Port 3

USB 2.0 port6

page 52

DDR3L-SO-DIMM X2

BANK 0, 1, 2, 3

UP TO 16G

Jet-XT M2 (AMD Radeon R5 M240)
Topaz-XT M2(AMD Radeon R5 M240)

VRAM 128M*16 *8
VRAM 256M*16 *8

JUSB2

USB 3.0 Port 1
USB 2.0 Port 0

Page 40

NGFF Card
mSATA/WWAN(option)

SATA Port 1

USB 2.0 port4

page 52

Page 18~19

PCIe port 5

Page 20~29

Realtek
RTS5227E
SD/MMC/XD Conn

Page 32

3 3

Power Circuit DC/DC

Page 65~70

SPI ROM
(8MB for NVpro)

One-Link Docking Board
&

(12MB for Vpro)

Page 9

PCIe Gen1 Port 6

SPI BUS

3.3V 33MHz

LPC BUS

3.3V 33MHz

PCH

USB3.0 Port3

Mirror function

Combon Jack Board

EC
ITE IT8586E/FX

Page 62

USB 2.0 Port 5

SATA Gen3 Port 0 SATA HDD

HD Audio

3.3V 24MHz

USB 2.0 Port 4

Finger printer

Page 50

SATA Port 0

page 37

SATA ODDSATA Gen2 Port 1

SATA Port 1

page 37

Codec
ALC3232-CG

Page 35, 36

HP_R/L_JACK
Ext Mic

SP_OUTR/L

SPK Conn.

Page 36

Combon Jack

4 4

Power Board

https://t.me/schematicslaptop
https://t.me/biosarchive

A

Thermal Sensor
Fintek F75303M

Page 55

B

Int.KBD

Page 51

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Touch Pad Conn

USB Port 4

Page 51

2013/09/07

2013/09/07

2013/09/07

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/09/07

2014/09/07

2014/09/07

Page 54

Title

Title

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet

Date: Sheet

Date: Sheet

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

2 81

2 81

2 81

E

1.0

1.0

1.0

of

of

of

A

Voltage Rails

( O --> Means ON , X --> Means OFF )

Power Plane

1 1

+3VALW

B+

+5VALW

State

S0

S3

2 2

S5 S4/AC Only

S5 S4
Battery only

O

O O O

O

O

O

O

X X

S5 S4
AC & Battery
don't exist

X X

SMBUS Control Table

3 3

PCH_SML0_CLK
PCH_SML0_DAT

PCH_SML1CLK
PCH_SML1DATA

EC_SMB_CK1
EC_SMB_DA1

PCH_SMBCLK
PCH_SMBDATA

4 4

SOURCE

PCH

+3V_PCH

PCH

+3V_PCH

IT8586E

+3VL

PCH

+3V_PCH

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Main
VGA

+3VS +3VS

LAN BATT SODIMM

V

+3V_PCH

V

X X X X X X

XX X X X X X X

V

+3VL

IT8586E

V

+3VS

X X X X X

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

A

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

HIGH

B

+5VS

+3VS

+1.5VS

+VCCSA

+V1.5S_VCCP

+CPU_CORE

+1.5V

OO

X

+VGA_CORE

+GFX_CORE

+1.8VS

+1.05VS

+0.75VS

+3.3VS_VGA

+1.5VS_VGA

+1.05VS_VGA

X

X

X

X

WLAN
WiMAX

V V

+3VS

ON

ON

ON

ON

ON

ON

ON

OFF

ON

OFF

B

X

Thermal
Sensor

V

ON ON

ON

OFF

OFF

OFF

PCH

+3V_PCH

LOW

OFF

OFF

OFF

C

High Speed I/O port

I/O High Speed Signal

1

USB3 1

2

USB3 2

3

PCIE 1 / USB3 3

4

PCIE 2 / USB3 4

5

PCIE 3

6

PCIE 4

7

PCIE 5 L0

8

PCIE 5 L1

9

PCIE 5 L2

10

PCIE 5 L3

11

PCIE 6 L0 / SATA 3

12

PCIE 6 L1 / SATA 2

13

PCIE 6 L2 / SATA 1

14

PCIE 6 L3 / SATA 0

Configuration

USB3 1

USB3 2

NC

USB3 4

PCIE 3

PCIE 4

PCIE 5 L0

PCIE 5 L1

PCIE 5 L2

PCIE 5 L3

PCIE 6

SATA 2

SATA 1

SATA 0

Port assignment

On MB USB

On MB USB

NC

Docking USB

WLAN

LAN

GPU

GPU

GPU

GPU

Cardreader

mSATA

ODD

HDD

BOM Structure Table

NOTEBOM Structure

PCB@ For PCB load BOM

3G@

TPM@

NM14@

NM15@

UMA@

CP
Module

Charger

DIS@

X76@

M2G@

X

M1G@

S2G@

X

XXXXXXXX

V

+3VL

S1G@

ME@

TS@ Touch screen function

DEBUG@ For debug

VX X

+3VS

NVPRO@ For Non-VPRO function

VPRO@ For VPRO function
X76_S2G@
S2G@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2013/09/07

2013/09/07

2013/09/07

3G function(Option with TS@)

Trusted Platform Module (TPM)

14" SKU ID

15" SKU ID

UMA SKU ID

Optimus SKU ID

GPU VRAM Setting

Micron 256Mx16 VRAM

Micron 128Mx16 VRAM

Samsung 256Mx16 VRAM

Samsung 128Mx16 VRAM

ME Connector

For bypassBYPASS@

For mirror functionMIRROR@

For Samsung 2G VRAM

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

D

2014/09/07

2014/09/07

2014/09/07

E

UC1

Haswell-ULT-CL8064701478202_SR16Q

SR16Q@
SA00005VY10

UC1

Broadwell-ULT-CL8065801674128_QG21

QG21@
SA000067H00

UC1

Broadwell-ULT-CL8065801675027_QG22

QG22@
SA000067I00

UC1

Haswell-ULT-CL8064701477400_SR1ED

SR1ED@
SA00005YW10

UV1

JET M2 XT

JET@
SA000066500

ZZZ7

X76_S2G@

K4W4G1646D-BC1A

X7603901003

ZZZ10

X76_S1G@

K4W2G1646Q-BC1A

X7603901004

UL1

VPRO@

WGI218LM-QQJY-B1_QFN48_6X6

SA00005TP10

UC1

BDW-3205U-1.5G

QGZ6@
SA000072M00

UC1

BDW-i3-2G

QH18@
SA000072H00

UC1

HSW I3 4030U

SR1EN@
SA000810100

Title

Title

Title

NOTE LIST

NOTE LIST

NOTE LIST

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Broadwell-1.6GHz ULV 15W 2+2U 1600 DDR ES2

Broadwell-1.6GHz 15W 2+2U 1333 DDR ES2

Haswell-CL8064701478404 QEAR D0

Haswell-CL8064701477600 QEAH D0 2.0G

ZZZ8

H5TC4G63AFR-11C

X7603901001

ZZZ11

H5TC2G63FFR-11C

X7603901005

UC1

BDW-3755U-1.7G

QGZ5@
SA000072J00

UC1

BDW-i3-2G

QGZ3@
SA000072P00

UC1

HSW I5 4210U

SR1EF@
SA000066Y20

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

UC1

Broadwell-1.8GHz 15W 2+2U 1600 DDR ES2

QGH9@
SA000810900

UC1

QGHB@
SA000811100

UC1

QGHA@
SA000811000

UC1

QEAR@
SA00005YZ00

UC1

QEAH@
SA000066W00

ZZZ9

X76_H2G@

X76_H1G@

UC1

BDW-i5-2G

QH17@
SA000072K00

UC1

HSW I3 4005U

SR1EK@
SA00005YZ20

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

E

X76_M2G@

MT41J256M16HA-093G:E

X7603901002

ZZZ12

X76_M1G@

MT41J128M16JT-093G:K

X7603901006

UC1

BDW-i7-2.2G

QH15@
SA000072L00

UC1

BDW-3805U-1.9G

QGZ4@
SA000072N00

ZZZ1

NM-A221

PCB@
DAZ0TS00100

3 81

3 81

3 81

1.0

1.0

1.0

5

4

3

2

1

Hot plug detect for IFP link E

VGA and GDDR5 Voltage Rails (N13Px GPIO)

GPIO I/O ACTIVE Function Description

GPIO0

D D

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

C C

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

B B

+1.05VS_VGA

OUT GPU VID4-

OUT

OUT

OUT

OUT

OUT

OUT

I/O

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

-

GPU VID3OUT

VGA_BL_PWM

-

-

VGA_ENVDD

- VGA_ENBKL

GPU VID1

-

GPU VID2

-

DPRSLPVR_VGA

-

Thermal Catastrophic Over Temperature

-

GPIO9

-

Memory VREF Control

-

GPU VID0-OUT

AC Power Detect Input

GPU VID5-

FB_CLAMP_TOGGLE_REQ#

-

N/A (100K pull low)

FRMLCK#

-

N/A

-

dGPU_HDMI_HPD

HPD_IRQ

-

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us

(10K pull High)

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)

GPU Mem NVCLK

Products

N13X
128bit
1GB
GDDR5

Physical
Strapping pin

ROM_SCLK

(4) (1,5) (6)

(W) (W) (MHz)

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

/MCLK NVVDD

(V) (A) (W) (A) (W)

TBD TBDTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Power Rail

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

+3VS_VGA

Logical
Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

Device ID

N13P-GT
(28nm)

0x0FDB

SMB_ALT_ADDR

(ROM_SO Bit 1)

FBVDD

Logical
Strapping Bit2

SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

setting

0

1

ROM_SO ROM_SCLK

GPU

N13P-GT1
28nm

GPU

FB Memory (GDDR5)

Samsung
2500MHz

Hynix
2500MHz

Samsung
2500MHz

2500MHz

PU 25K

PU 45KPU 10K PD 10K

PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K

K4G10325FG-HC04

32Mx32

H5GQ1H24BFR-T2C

32Mx32 PD 35K

K4G20325FD-FC04

64Mx32

H5GQ2H24MFR-T2CHynix

64Mx32

PD 35K

N13P-GT

ROM_SI

PD 45K

PD 30K

PD 25K

FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

I2C Slave addrees ID

0x9E

0x9C

STRAP2STRAP1STRAP0

STRAP3

PU 5K PD 10K

(1.05V)

Logical
Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

PLLVDD

I/O and
PLLVDD

Logical
Strapping Bit0

PEX_PLL_EN_TERM

RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

PCIE_MAX_SPEED DP_PLL_VDD33V

SOR0_EXPOSED

STRAP4

Master

Slave

Other

(3.3V)(1.05V)(1.8V)

https://t.me/schematicslaptop

https://t.me/biosarchive

Other Power rail

A A

+3VS_VGA

Tpower-off <10ms

1.all GPU power rails should be turned off within 10ms

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

VGA NOTE

VGA NOTE

VGA NOTE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet

Date: Sheet

Date: Sheet

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

of

of

of

4 81

4 81

4 81

1.0

1.0

1.0

5

D D

4

3

2

1

MISC

THERMAL

PWR

DDR3L

HSW_ULT_DDR3L

1 OF 19

HSW_ULT_DDR3L

2 OF 19

QFSY@

C45

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2

EDPDDI

EDP_TXN3
EDP_TXP3

EDP_AUXN
EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

CPU_EDP_TX0-

B46

CPU_EDP_TX0+

A47

CPU_EDP_TX1-

B47

CPU_EDP_TX1+

C47
C46
A49
B49

A45

CPU_EDP_AUX#

B45

CPU_EDP_AUX

D20

EDP_COMP

A43






CPU_EDP_TX0- <38>
CPU_EDP_TX0+ <38>
CPU_EDP_TX1- <38>
CPU_EDP_TX1+ <38>

CPU_EDP_AUX# <38>
CPU_EDP_AUX <38>

1 2

RC1 24.9_0402_1%

+VCCIOA_OUT



+1.05VS_VCCST

1 2

RC164 51_0402_1%XDP@

1 2

RC3 51_0402_1%XDP@

1 2

RC4 51_0402_1%

1 2

RC6 51_0402_1%@

JTAG

PRDY

PREQ
PROC_TCK
PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

J62
K62
E60
E61
E59
F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO

1
1

1

1

XDP_TDI

T1

XDP_TDO

T2

XDP_TCLK

T3

XDP_TRST#

T4

XDP PU/PD portion need to check agian.

UC1A

DDI1_MUX_TX0-<42>
DDI1_MUX_TX0+<42>







C C

+1.05VS_VCCST

12

RC2
62_0402_5%

VR_HOT#<62,67,73>

B B

VR_HOT#






DDI1_MUX_TX1-<42>
DDI1_MUX_TX1+<42>
DDI1_MUX_TX2-<42>
DDI1_MUX_TX2+<42>
DDI1_MUX_TX3-<42>
DDI1_MUX_TX3+<42>

DDI2_VGA_TX0-<43>
DDI2_VGA_TX0+<43>
DDI2_VGA_TX1-<43>
DDI2_VGA_TX1+<43>

H_PECI<62>

1 2

RC5 56_0402_5%

1 2

RC7 10K_0402_5%

1 2

RC8 200_0402_1%

1 2

RC9 120_0402_1%

1 2

RC10 100_0402_1%

DDR3_DRAMRST#<18,19>

DDR_PG_CTRL<18>

DDI1_MUX_TX0­DDI1_MUX_TX0+
DDI1_MUX_TX1­DDI1_MUX_TX1+
DDI1_MUX_TX2­DDI1_MUX_TX2+
DDI1_MUX_TX3­DDI1_MUX_TX3+

DDI2_VGA_TX0­DDI2_VGA_TX0+
DDI2_VGA_TX1­DDI2_VGA_TX1+

H_PECI

VR_HOT#_R

H_CPUPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR3_DRAMRST#
DDR_PG_CTRL

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

Broadwell-ULT_CL8064701614813_QFSY

SA000064600

UC1B

D61

PROC_DETECT

K61

CATERR

N62

PECI

K63

PROCHOT

C61

PROCPWRGD

AU60

SM_RCOMP0

AV60

SM_RCOMP1

AU61

SM_RCOMP2

AV15

SM_DRAMRST

AV61

SM_PG_CNTL1

Broadwell-ULT_CL8064701614813_QFSY

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

BDW_DDI/EDP/XDP

BDW_DDI/EDP/XDP

BDW_DDI/EDP/XDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

5 81

5 81

5 81

1.0

1.0

1.0

5

4

3

2

1

Interleaved (Butterfly Topology)
Broadwell Platform System Memory Interface
Document Number: 528378
BDW U DDR3L/DDR3L-RS SO-DIMM Interleaved Recommendations

D D

Channel A Byte 0 & 1

Channel B Byte 0 & 1

Channel A Byte 2 & 3

MCP

Channel A

Channel B Byte 2 & 3

DDR_A_D[0..63]<18> DDR_B_D[0..63]<19>
DDR_A_DQS#[0..7]<18>
DDR_A_DQS[0..7]<18>
DDR_A_MA[0..15]<18> DDR_B_MA[0..15]<19>

UC1C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5

C C

B B

DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31

AH63
AH62
AK63
AK62
AH61
AH60
AK61

AK60
AM63
AM62

AP63

AP62
AM61
AM60

AP61

AP60

AP58

AR58
AM57

AK57

AL58
AK58
AR57
AN57
AP55
AR55

AM54

AK54

AL55
AK55
AR54
AN54
AY58

AW58

AY56

AW56

AV58
AU58
AV56
AU56
AY54

AW54

AY52

AW52

AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

HSW_ULT_DDR3L

DDR CHANNEL A

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3

SA_CS#0
SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0
SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

AU43
AW43
AY42
AY43

AP33
AR32

AP32

AY34
AW34
AU34

AU35
AV35
AY41

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

AP49
AR51
AP51

SA_CLK_DDR#0
SA_CLK_DDR0
SA_CLK_DDR#1
SA_CLK_DDR1

DDRA_CKE0_DIMMA
DDRA_CKE1_DIMMA

DDRA_CS0_DIMMA#
DDRA_CS1_DIMMA#

DDRA_ODT0

DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_B_DQS#0
DDR_B_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_B_DQS#2
DDR_B_DQS#3

DDR_A_DQS0
DDR_A_DQS1
DDR_B_DQS0
DDR_B_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_B_DQS2
DDR_B_DQS3

SM_DIMM_VREFCA
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

SA_CLK_DDR#0 <18>
SA_CLK_DDR0 <18>
SA_CLK_DDR#1 <18> SB_CLK_DDR0 <19>
SA_CLK_DDR1 <18>

DDRA_CKE0_DIMMA <18>
DDRA_CKE1_DIMMA <18>

DDRA_CS0_DIMMA# <18>
DDRA_CS1_DIMMA# <18>

1

T5

DDR_A_RAS# <18>
DDR_A_WE# <18>
DDR_A_CAS# <18>

DDR_A_BS0 <18>
DDR_A_BS1 <18>
DDR_A_BS2 <18>

SM_DIMM_VREFCA <18>
SA_DIMM_VREFDQ <18>
SB_DIMM_VREFDQ <19>

DDR_B_DQS#[0..7]<19>
DDR_B_DQS[0..7]<19>

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AY31

AW31

AY29

AW29

AV31
AU31
AV29
AU29
AY27

AW27

AY25

AW25

AV27
AU27
AV25
AU25

AM29

AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26

AM26

AK25
AL25
AY23

AW23

AY21

AW21

AV23
AU23
AV21
AU21
AY19

AW19

AY17

AW17

AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

UC1D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

HSW_ULT_DDR3L

DDR CHANNEL B

Channel A Byte 4 & 5

Channel B Byte 4 & 5

Channel A Byte 6 & 7

Channel B Byte 6 & 7

AM38

SB_CK#0

AN38

SB_CK0

AK38

SB_CK#1

AL38

SB_CK1

AY49

SB_CKE0

AU50

SB_CKE1

AW49

SB_CKE2

AV50

SB_CKE3

AM32

SB_CS#0

AK32

SB_CS#1

AL32

SB_ODT0

AM35

SB_RAS

AK35

SB_WE

AM33

SB_CAS

AL35

SB_BA0

AM36

SB_BA1

AU49

SB_BA2

AP40

SB_MA0

AR40

SB_MA1

AP42

SB_MA2

AR42

SB_MA3

AR45

SB_MA4

AP45

SB_MA5

AW46

SB_MA6

AY46

SB_MA7

AY47

SB_MA8

AU46

SB_MA9

AK36

SB_MA10

AV47

SB_MA11

AU47

SB_MA12

AK33

SB_MA13

AR46

SB_MA14

AP46

SB_MA15

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

DDR_A_DQS#4
DDR_A_DQS#5
DDR_B_DQS#4
DDR_B_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

SB_CLK_DDR#0
SB_CLK_DDR0
SB_CLK_DDR#1
SB_CLK_DDR1

DDRB_CKE0_DIMMB
DDRB_CKE1_DIMMB

DDRB_CS0_DIMMB#
DDRB_CS1_DIMMB#

DDRB_ODT0

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_A_DQS4
DDR_A_DQS5
DDR_B_DQS4
DDR_B_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_B_DQS6
DDR_B_DQS7

MCP

Channel B

SB_CLK_DDR#0 <19>

SB_CLK_DDR#1 <19>
SB_CLK_DDR1 <19>

DDRB_CKE0_DIMMB <19>
DDRB_CKE1_DIMMB <19>

DDRB_CS0_DIMMB# <19>
DDRB_CS1_DIMMB# <19>

1

T6

DDR_B_RAS# <19>
DDR_B_WE# <19>
DDR_B_CAS# <19>

DDR_B_BS0 <19>
DDR_B_BS1 <19>
DDR_B_BS2 <19>

A A

Broadwell-ULT_CL8064701614813_QFSY

5

3 OF 19

Broadwell-ULT_CL8064701614813_QFSY

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4 OF 19

2

2014/09/07

2014/09/07

2014/09/07

Title

Title

Title

BDW_DDR3L INT

BDW_DDR3L INT

BDW_DDR3L INT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

6 81

6 81

6 81

1.0

1.0

1.0

5

4

3

2

1

RTC External Circuit

D D




C C

B B

1 2

RC11 0_0402_5%

PCH_HDA_SDIN0<35>

PCH_HDA_RST#<35>
PCH_HDA_BCLK<35>
PCH_HDA_SDOUT<35>
PCH_HDA_SYNC<35>

ME_FLASH<62>

+RTCVCC+RTCBATT

1

CC2

@

1U_0402_10V6-K

2

+RTCVCC

1 2

RC16 1M_0402_5%

1 2

RC15 330K_0402_5%

RPC25

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

SD30000370T

1 2

RC44 0_0402_5%

JCMOS, JME Setting, Need Under DDR Door

T8
T9
T10
T11
T12

T13

+RTCVCC

1
1
1
1
1

1

HDA_RST#
HDA_BCLK
HDA_SDOUT
HDA_SYNC

1 2

20K_0402_5%

1 2

20K_0402_5%

PCH_RTCX1
PCH_RTCX2
PCH_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

HDA_BCLK
HDA_SYNC
HDA_RST#
PCH_HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_JTAGX

RC12

PCH_RTCRST#

RC14

PCH_SRTCRST#

UC1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD1

AC4

RSVD2

AE63

JTAGX

AV2

RSVD0

Broadwell-ULT_CL8064701614813_QFSY

JCMOS1 @

1 2

1 2

CC1 1U_0402_10V6-K

JME1 @

1 2

1 2

CC5 1U_0402_10V6-K

HSW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

5 OF 19

RTC Crystal

1

2

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

RC13

1 2

10M_0402_5%

YC1

1 2

32.768KHZ_12.5PF_9H03200042
CC3
12P_0402_50V8-J

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA_IREF

RSVD3
RSVD4

SATA_RCOMP

SATALED

PCH_RTCX1
PCH_RTCX2





1



CC4
12P_0402_50V8-J

2

J5

SATA_PRX_DTX_N0

H5

SATA_PRX_DTX_P0

B15

SATA_PTX_DRX_N0

A15

SATA_PTX_DRX_P0

J8

SATA_PRX_DTX_N1

H8

SATA_PRX_DTX_P1

A17

SATA_PTX_DRX_N1

B17

SATA_PTX_DRX_P1

J6

SATA_PRX_DTX_N2

H6

SATA_PRX_DTX_P2

B14

SATA_PTX_DRX_N2

C15

SATA_PTX_DRX_P2

F5

PCIE6_CRX_DTX_N

E5

PCIE6_CRX_DTX_P

C17
D17

V1
U1
V6
AC1

A12
L11
K10
C12
U3

PCIE6_CTX_DRX_N

PCIE6_CTX_DRX_P

PCH_GPIO34

ODD_DETEC#

PCH_GPIO36

EC_SCI#

+1.05VS_PSATA3PLL

SATACOMP

RC22 3.01K_0402_1%

1 2

CC23 0.1U_0402_10V7-K

1 2

CC24 0.1U_0402_10V7-K

1 2

SATACOMP





SATA_PRX_DTX_N0 <37>
SATA_PRX_DTX_P0 <37>
SATA_PTX_DRX_N0 <37>
SATA_PTX_DRX_P0 <37>

SATA_PRX_DTX_N1 <37>
SATA_PRX_DTX_P1 <37>
SATA_PTX_DRX_N1 <37>
SATA_PTX_DRX_P1 <37>

SATA_PRX_DTX_N2 <52>
SATA_PRX_DTX_P2 <52>
SATA_PTX_DRX_N2 <52>
SATA_PTX_DRX_P2 <52>

ODD_DETEC# <37>

EC_SCI# <62>

HDD

ODD, only for 15"

SSD(NGFF)

PCIE6_CTX_C_DRX_N
PCIE6_CTX_C_DRX_P

Only for 15"

+1.05VS_PSATA3PLL

https://t.me/schematicslaptop

https://t.me/biosarchive

PCIE6_CRX_DTX_N <32>
PCIE6_CRX_DTX_P <32>
PCIE6_CTX_C_DRX_N <32>
PCIE6_CTX_C_DRX_P <32>

PCH_GPIO34
PCH_GPIO36
ODD_DETEC#
EC_SCI#

RPC1

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

Card Reader

+3VS

A A

INTVRMEN





 

*

 






5

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

Title

Title

RTC/HDA/SATA/PCIe/JTAG

RTC/HDA/SATA/PCIe/JTAG

RTC/HDA/SATA/PCIe/JTAG

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet

Date: Sheet

Date: Sheet

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

of

of

of

7 81

7 81

7 81

1.0

1.0

1.0

5

D D

4

3

2

1

UC1F

+3VS

WLAN

C C

LAN

VGA

CR

B B

1 2

RC29 10K_0402_5%DIS@

1 2

RC32 10K_0402_5%UMA@

CLK_PCIE_WLAN#<52>
CLK_PCIE_WLAN<52>
CLKREQ_PCIE2_WLAN#<52>

CLK_PCIE_LAN#<47>
CLK_PCIE_LAN<47>
CLKREQ_PCIE3_LAN#<47>

CLK_PCIE_VGA#<20>
CLK_PCIE_VGA<20>
CLKREQ_PCIE4_VGA#<20>

CLK_PCIE_CR#<32>
CLK_PCIE_CR<32>
CLKREQ_PCIE5_CR#<32>

+3VS

RPC2

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

+3VS

1 2

RC165 10K_0402_5%

1 2

RC166 10K_0402_5%

UMA@

DIS@

PCH_GPIO19

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
CLKREQ_PCIE2_WLAN#

CLK_PCIE_LAN#
CLK_PCIE_LAN
CLKREQ_PCIE3_LAN#

CLK_PCIE_VGA#
CLK_PCIE_VGA
CLKREQ_PCIE4_VGA#

CLK_PCIE_CR#
CLK_PCIE_CR
CLKREQ_PCIE5_CR#

CLKREQ_PCIE2_WLAN#
CLKREQ_PCIE3_LAN#
PCH_GPIO19
CLKREQ_PCIE5_CR#

CLKREQ_PCIE4_VGA#CLKREQ_PCIE4_VGA#

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

Broadwell-ULT_CL8064701614813_QFSY

HSW_ULT_DDR3L

CLOCK

SIGNALS

6 OF 19

XTAL24_IN

XTAL24_OUT

RSVD5
RSVD6

DIFFCLK_BIASREF

TESTLOW_C35

TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

A25
B25

K21
M21
C26

C35
C34
AK8
AL8

AN15
AP15

B35
A35

PCH_XTAL24_IN
PCH_XTAL24_OUT

DIFFCLK_BIASREF

MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4

PCH_PCI_CLK_R
CLK_PCI_TPM_R

MCP_TESTLOW3
MCP_TESTLOW4
MCP_TESTLOW1
MCP_TESTLOW2

1 2

RC23 3.01K_0402_1%




1 2

RC24 22_0402_5%

1 2

RC25 22_0402_5%TPM@

RPC4

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

+1.05VS_PLPTCLKPLL

CLK_PCI_EC <62>
CLK_PCI_TPM <56>

PCH_XTAL24_IN

PCH_XTAL24_OUTDISCRETE_PRESENCE

12P_0402_50V8-J

CC6

1

1

2

RC30

1 2

1M_0402_5%

YC2

1

GND1

24MHZ_10PF_8Y24000011

3

GND2

2

4

3

1

CC7
12P_0402_50V8-J

2

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

BDW_CLOCK/PM

BDW_CLOCK/PM

BDW_CLOCK/PM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

8 81

8 81

8 81

1.0

1.0

1.0

5

4

3

2

1

D D

RPC23

1 8

SPI_IO3_8MB SPI_IO3

2 7

SPI_CLK_8MB
SPI_SI_8MB
SPI_IO2_8MB

33_0804_8P4R_5%

SPI_IO3_4MB SPI_IO3
SPI_CLK_4MB
SPI_SI_4MB
SPI_IO2_4MB

33_0804_8P4R_5%

3 6
4 5

SD30000370T

RPC24

1 8
2 7
3 6
4 5

SD30000370T

VPRO@

SPI_CLK
SPI_SI
SPI_IO2

SPI_CLK
SPI_SI
SPI_IO2

+3V_SPI



SPI_SO_8MB
SPI_SO_4MB

LPC_AD[3:0]<56,62>

LPC_FRAME#<56,62>

1 2

RC100 33_0402_5%

1 2

RC101 33_0402_5%

VPRO@

1 2

RC117 1K_0402_5%

1 2

RC118 1K_0402_5%

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

SPI_CLK

SPI_CS0#_8MB
SPI_CS1#_4MB

SPI_SI
SPI_SO

SPI_IO2
SPI_IO3

UC1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

Broadwell-ULT_CL8064701614813_QFSY

HSW_ULT_DDR3L

LPC

SMBUS

SML1ALERT/PCHHOT/GPIO73

C-LINKSPI

7 OF 19

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

AF2
AD2
AF4

PCH_GPIO11
PCH_SMB_CLK
PCH_SMB_DATA
PCH_GPIO60
PCH_SML0_CLK
PCH_SML0_DAT
PCH_GPIO73
PCH_SML1CLK
PCH_SML1DATA

CL_CLK_WLAN
CL_DATA_WLAN
CL_RST_WLAN#

PCH_SML0_CLK <47>
PCH_SML0_DAT <47>

CL_CLK_WLAN <52>
CL_DATA_WLAN <52>
CL_RST_WLAN# <52>







PCH_SML0_CLK
PCH_SML0_DAT

PCH_SMB_CLK
PCH_SMB_DATA
PCH_SML1CLK
PCH_SML1DATA

PCH_GPIO11
PCH_GPIO60
PCH_GPIO73

1 2

RC92 499_0402_1%

1 2

RC93 499_0402_1%

RPC14

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

RPC15

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

SD300002P0T

+3V_PCH

+3V_PCH

Near UC4M1 and UC8M1

C C

Security ROM

USROM1

1

NC_1

2

NC_2

PLTRST#_NEAR<10,32,47>

PLTRST#_NEAR

3

PROT#

4

GND

PCA24S08AD_SO8

SA00004MK00/SA00004ML00

VCC

SCL
SDA

WP

8
7
6

PM_SMB_CLK

5

PM_SMB_DAT

M3 Support + Intel LAN PHY / Wireless LAN Solution

B B

+3VS

RC112 0_0402_5%

+3VM

SPI_CS0#_8MB

SPI_SO_8MB

SPI_IO2_8MB

1 2

1

2

3

4

UC8M1

VCC

CS#

DO

HOLD#

CLK

WP#

GND

W25Q64FVSSIQ_SO8

8

7

6

5

DI

1 2

RC110 0_0402_5%@



1 2

FSCE#<62>
SPI_FMOSI#<62>
SPI_FMISO<62>

A A

SPI_FSCK<62>

RE19 0_0402_5%

1 2

RE21 0_0402_5%

1 2

RE22 0_0402_5%

1 2

RE24 0_0402_5%

+3V_SPI

0.085 A

+3V_SPI

SPI_IO3_8MB

SPI_CLK_8MB

SPI_SI_8MB

+3V_SPI

+3V_SPI

1

CC25

0.1U_0402_10V7-K

2

SPI_CS0#_8MB
SPI_SI_8MB
SPI_SO_8MB
SPI_CLK_8MB

+3VS

1

CC22

0.1U_0402_10V6-K

2

SPI_CS1#_4MB
SPI_SO_4MB
SPI_IO2_4MB

UC4M1

1

CS#

2

DO

HOLD#

3

WP#

4

GND

W25Q32FVSSIQ_SO8

VPRO@

VCC

SM Bus

+3VS

PCH_SMB_CLK

PCH_SMB_DATA

8

+3V_SPI

7

SPI_IO3_4MB

6

SPI_CLK_4MB

CLK

5

SPI_SI_4MB

DI

+3V_SPI

1

CC26

VPRO@

0.1U_0402_10V7-K

2

PCH_SML1CLK EC_SMB_CK3

PCH_SML1DATA EC_SMB_DA3

6 1

D

5

QC1A

G

2N7002KDWH_SOT363-6

3 4

S

D

QC1B
2N7002KDWH_SOT363-6

+3VS

6 1

5

G

3 4

S

D

QC2B
2N7002KDWH_SOT363-6

DIMM1, DIMM2,
WLAN(@), CP, Security ROM
Touch Panel

2

G

S

RC106 4.7K_0402_5%

RC107 4.7K_0402_5%

PM_SMB_CLK

PM_SMB_DAT

GPU, EC, Thermal Sensor

2N7002KDWH

2

G

Vth= min 1V, max 2.5V
ESD 2KV

S

D

QC2A
2N7002KDWH_SOT363-6

1 2

+3VS

1 2

PM_SMB_CLK <18,19,49>

PM_SMB_DAT <18,19,49>

EC_SMB_CK3 <21,34,55,62>

EC_SMB_DA3 <21,34,55,62>

Close to SPI ROM (UC8M1).

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

BDW_LPC/SPI/SM BUS

BDW_LPC/SPI/SM BUS

BDW_LPC/SPI/SM BUS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

9 81

9 81

9 81

1.0

1.0

1.0

5

4

3

2

1

D D

UC1H

1 2

SUSACK#<62>

PCH_SYSPWROK<62>

PCH_PWROK<62>
PCH_APWROK<78>

PLTRST#<20>

EC_RSMRST#<62>

SUSWARN#<62>

PBTN_OUT#<62>

AC_PRESENT<62>

C C

+3VALW +3V_PCH

B B

RPC18

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

SD300002P0T

RC37 0_0402_5%@

1 2

RC41 0_0402_5%

1 2

RC42 0_0402_5%

VPRO@

1 2

RC39 0_0402_5%@

AC_PRESENT
BATLOW#
PCIE_WAKE#

PCH_APWROK

SUSACK#_R
SYS_RESET#
PCH_SYSPWROK
PWROK
APWROK
PLTRST#

EC_RSMRST#
SUSWARN#_R
PBTN_OUT#
AC_PRESENT
BATLOW#

1

PCH_SLP_WLAN#

T17

+3VS

1 2

RC108 10K_0402_5%

1 2

RC51 8.2K_0402_5%

1 2

RC27 10K_0402_5%

1 2

RC28 100K_0402_1%@

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5
AG7

AW6

AV4

AL7

AJ8
AN4
AF3

AM5

Broadwell-ULT_CL8064701614813_QFSY



APWROK
PLTRST

RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29

SYS_RESET#

CLKRUN#

EC_RSMRST#

EC_DPWROK_R

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

8 OF 19








1.05VS_PGOOD<14,62,70>

SUS_STAT/GPIO61

1 2

RC49 10K_0402_5%@

DSWVRMEN

DPWROK



WAKE

CLKRUN/GPIO32

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4
SLP_S3

SLP_A
SLP_SUS
SLP_LAN

AW7

DSWODVREN

AV5

EC_DPWROK_R

AJ5

PCIE_WAKE#

V5

CLKRUN#

AG4

SUS_STAT#

AE6

SUSCLK_32K

AP5

PM_SLP_S5#

AJ6

PM_SLP_S4#

AT4

PM_SLP_S3#

AL5

PM_SLP_A#

AP4

PCH_SLP_SUS#

AJ7

PCH_SLP_LAN#





1 2

RC125

@

10K_0402_5%

SUSWARN#_R

1

2

1

PCH_APWROK

CC40

@

.01U_0402_16V7-K

1 2

RC45 330K_0402_5%

CLKRUN# <56>

1 2

RC47 0_0402_5%@

SUSCLK_32K <52>
PM_SLP_S5# <62>

PM_SLP_S4# <62>
PM_SLP_S3# <62>
PM_SLP_A# <62>
PCH_SLP_SUS# <62>

T18

1

PLTRST#

RC26

100K_0402_5%

2

3

12

+RTCVCC

UC3

NC

IN_A

GND

TC7SG17FE_SON5

VCC

OUT_Y

LPC_PD# <56>

5

4

RC48 33_0402_5%

RC50 33_0402_5%

RC43 0_0402_5%

RC52 0_0402_5%@

RC33 100K_0402_5%@

1

CC8

@

1U_0402_10V6-K

2

+3VALW

1 2

1 2

https://t.me/biosarchive

12

1 2

1 2

1

CC9

100P_0402_50V8-J

2

1

CC82

100P_0402_50V8-J

2

EC_RSMRST#

EC_DPWROK <62>

+3VALW

PLTRST#_NEAR <32,47,9>

PLTRST#_FAR <52,56,62>

https://t.me/schematicslaptop

RC109

A A

1 2

0_0402_5%

RC111

1 2

0_0402_5%

SUSACK#_RSUSWARN#_R

PWROKAPWROK

5









4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

Title

Title

BDW_SYS PM

BDW_SYS PM

BDW_SYS PM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet

Date: Sheet

Date: Sheet

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

of

of

of

10 81

10 81

10 81

1.0

1.0

1.0

5

D D

4

3

2

1

eDP SIDEBAND

PCIE

HSW_ULT_DDR3L

9 OF 19

DISPLAY

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD

EDP_HPD

B9
C9
D9
D11

C5
B6
B5
A6

C8
A8
D6

PCH_MUX_CLK
PCH_MUX_DAT
PCH_VGA_CLK
PCH_VGA_DAT

PCH_MUX_AUX#
PCH_VGA_AUX#
PCH_MUX_AUX
PCH_VGA_AUX

PCH_MUX_HPD
PCH_VGA_HPD
CPU_EDP_HPD

PCH_MUX_CLK <42>
PCH_MUX_DAT <42>

PCH_MUX_AUX# <42>
PCH_VGA_AUX# <43>
PCH_MUX_AUX <42>
PCH_VGA_AUX <43>

PCH_MUX_HPD <42>
PCH_VGA_HPD <43>
CPU_EDP_HPD <38>

After testing, check if can un-stuff.

1.

籔籔籔籔

VENDOR

絋絋絋絋絋絋絋絋

PU

Τmeet SPEC value.

2. Vender fine tune recommend value.(Pass
Through Mode)

3. Vendor recommend use PU 4.7K ohm. (10/1)
Intel Spec is PU 2.2K ohm

PCH_MUX_CLK
PCH_MUX_DAT

PCH_VGA_CLK
PCH_VGA_DAT

PCH_MUX_HPD

PCH_VGA_HPD

CPU_EDP_HPD

ENBKL

, 絋絋絋絋絋絋絋絋

1 2

RC115 4.7K_0402_5%

1 2

RC116 4.7K_0402_5%

1 2

RC31 2.2K_0402_5%

1 2

RC40 2.2K_0402_5%

1 2

RC157 100K_0402_5%@

1 2

RC158 100K_0402_5%

1 2

RC159 100K_0402_5%

1 2

RC156 100K_0402_5%

Vih anf Vil

+3VS

UC1I

PCH_EDP_PWM<38>

ENBKL<62>

PCH_ENVDD<38>



C C

+3VS

1 8
2 7
3 6
4 5

B B

1 8
2 7
3 6
4 5

1 2

RC85 10K_0402_5%



RPC16

VGA_ON
DGPU_HOLD_RST#
BT_ON
CP_BYPASS

10K_0804_8P4R_5%

RPC17

PCH_TSOFF#
F4_LED#
F1_LED#
FN_LED#

10K_0804_8P4R_5%

DGPU_PWROK

UMA@

DGPU_PWROK<29,76>

VGA_ON<20,29,72,76,77>

DGPU_HOLD_RST#<20>

BT_ON<52>

PCH_TSOFF#<51>

FN_LED#<51>
F4_LED#<51>

PLANARID3<12>

F1_LED#<51>

CP_BYPASS <12,49>

PCH_EDP_PWM
ENBKL
PCH_ENVDD

DGPU_PWROK
VGA_ON
DGPU_HOLD_RST#
BT_ON

PCH_TSOFF#
FN_LED#
F4_LED#
PLANARID3
F1_LED#

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

Broadwell-ULT_CL8064701614813_QFSY






*

A A





Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

BDW_eDP SBAND/DDPx

BDW_eDP SBAND/DDPx

BDW_eDP SBAND/DDPx

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

11 81

11 81

11 81

1.0

1.0

1.0

5

4

3

2

1

UC1J

D D

Only for 15"

EC_WAKE#

RC167 0_0402_5%@

PCH_LAN_WAKE#<47>

EC_WAKE#<62>

C C

RC168 0_0402_5%@

RC169 0_0402_5%

1 2

1 2

1 2

ONEDOCK_DET#<34>

RF_OFF#<52>
LANPHYPC<47>

ODD_EN<37>
ODD_DA#<37>

DEVSLP0<37>

DEVSLP1<52>

PCH_BEEP<36>

PCH_GPIO76
RF_OFF#
LANPHYPC
PCH_GPIO15
ODD_EN
ODD_DA#
PCH_GPIO24
DS_WAKE#
PCH_GPIO28
PCH_GPIO26

PCH_GPIO56
PCH_GPIO57
PCH_GPIO58

PCH_GPIO44
PCH_GPIO47
PLANARID0
PLANARID1
PLANARID2

EC_WAKE_R#
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46

ONEDOCK_DET#
PCH_GPIO10
DEVSLP0
PCH_GPIO70
DEVSLP1
PCH_GPIO39
PCH_BEEP

SATA Port
DEVSLP0
DEVSLP1

1 2

RC90 10K_0402_5%

1 2

B B

A A

RC91 10K_0402_5%

DS_WAKE#

SATA Port 0

SATA Port 1

RPC5

18

PCH_GPIO59PCH_GPIO25

27

PCH_GPIO56

36

PCH_GPIO47

45

18
27
36
45

18
27
36
45

18
27
36
45

PCH_GPIO44

PCH_GPIO58
PCH_GPIO57

ONEDOCK_DET#

RF_OFF#
PCH_GPIO46
EC_WAKE_R#
PCH_GPIO26

PCH_GPIO24
PCH_GPIO28
PCH_GPIO14
PCH_GPIO45

10K_0804_8P4R_5%
RPC6

10K_0804_8P4R_5%

RPC7

10K_0804_8P4R_5%

RPC19

10K_0804_8P4R_5%

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

Broadwell-ULT_CL8064701614813_QFSY

+3VS+3V_PCH+3VALW +3VS

HSW_ULT_DDR3L

GPIO

RPC8

18
27
36
45

10K_0804_8P4R_5%

RPC9

18
27
36
45

10K_0804_8P4R_5%

RPC10

18
27
36
45

10K_0804_8P4R_5%

RPC11

18
27
36
45

4.7K_0804_8P4R_5%

RPC12

18
27
36
45

10K_0804_8P4R_5%

10 OF 19

ODD_DA#
PCH_GPIO83
PCH_GPIO69
PCH_GPIO89

PCH_GPIO76
ODD_ENPCH_GPIO10
PCH_GPIO6
WWAN_DISABLE#

FW_GPIO
PCH_GPIO70
PCH_GPIO90
PCH_CMOS_ON

PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
PCH_GPIO0

PCH_GPIO64
PCH_GPIO65
PCH_GPIO67
PCH_GPIO85

CPU/
MISC

SERIAL IO

THRMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD7
RSVD8

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3

I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

RPC20

10K_0804_8P4R_5%

RPC21

10K_0804_8P4R_5%

1 2

RC83 10K_0402_5%

1 2

RC84 10K_0402_5%

Intel recommend OPI_RCOMP PD 50 ohm 1%

D60

THRMTRIP#

V4

KBRST#

T4

SERIRQ

AW15
AF20

OPI_RCOMP

AB21




R6

PCH_GPIO83

L6

PCH_GPIO84

N6

PCH_GPIO85

L8

PCH_GPIO86

R7

PCH_GPIO87PCH_GPIO59

L5

PCH_GPIO88

N7

PCH_GPIO89

K2

PCH_GPIO90

J1

PCH_GPIO91

K3

CP_RESET#

J2

CP_BYPASS

G1

TP_REST

K4

PCH_GPIO0

G2

PCH_GPIO1

J3

PCH_GPIO2

J4

PCH_GPIO3

F2

WWAN_DET#

F3

WWAN_DISABLE#

G4

PCH_GPIO6

F1

FW_GPIO

E3

PCH_GPIO64

F4

PCH_GPIO65

D3

PCH_GPIO66

E4

PCH_GPIO67

C3

PCH_CMOS_ON

E2

PCH_GPIO69

18

PCH_GPIO91

27

PCH_GPIO84

36

PCH_GPIO87

45

PCH_GPIO88

18

SERIRQ

27

KBRST#

36

WWAN_DET#

45

PCH_GPIO39

DEVSLP0

DEVSLP1

KBRST# <62>
SERIRQ <56,62>

1 2

RC55 49.9_0402_1%

CP_RESET# <49>
CP_BYPASS <11,49>
TP_REST <49>

WWAN_DET# <52>

WWAN_DISABLE# <52>

FW_GPIO <38>

PCH_CMOS_ON <38>

THRMTRIP#

Only for 15"

1 2

RC53 1K_0402_1%

1 2

RC54
0_0402_5%

@

Planar ID

PLANARID0
(GPIO48)

0

14"

1

15"

*

PLANARID0

PLANARID1

PLANARID2

PLANARID3<11>

GPIO15, Internal PD

1: INTEL ME TLS W Confidentiality
0: INTEL ME TLS WO Confidentiality

PCH_GPIO15

GPIO66, Internal 20K PD

1: Top-Block Swap Override EN
*0: Disable

PCH_GPIO66

GPIO81, No Reboot, Internal PD

1: Enabled No Reboot Mode
*0: Disable No Reboot Mode

PCH_BEEP

GPIO86, Internal PD

1: Enabled
*0: SPI ROM

PCH_GPIO86

+1.05VS_VCCST

H_THERMTRIP# <21>

GPIO18 PLANARID2

(GPIO50)

HSW

UMA

BDW

OPT

12

12

10K_0402_5%

10K_0402_5%

10K_0402_5%

RC68

RC67

BDW@

12

12

10K_0402_5%

RC71

RC72

@

HSW@

RC75 1K_0402_5%

@

RC76 1K_0402_5%

@

RC77 1K_0402_5%

12

@

RC80 1K_0402_5%

RC82 1K_0402_5%

12

12

12

PLANARID3
(GPIO51)

NA

PU

12

10K_0402_5%

RC69

12

10K_0402_5%

RC73

@

12

+3VS

*

10K_0402_5%

10K_0402_5%

+3V_PCH

+3VS

+3VS

+3VS

12

RC70

15NM@

12

RC74

14NM@

2013/08/29 Set Nactive and Pull Down

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

BDW_GPIO/SIO

BDW_GPIO/SIO

BDW_GPIO/SIO

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

12 81

12 81

12 81

1.0

1.0

1.0

5

D D

4

3

2

1

UC1K

USB20_N4
USB20_P4

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD9

E13

RSVD10

A27

PCIE_RCOMP

B27

PCIE_IREF

Broadwell-ULT_CL8064701614813_QFSY

RC34 0_0402_5%
RC35 0_0402_5%

RC36 0_0402_5%3G@
RC38 0_0402_5%3G@

PCIE_CRX_GTX_N0<20>
PCIE_CRX_GTX_P0<20>

PCIE_CTX_C_GRX_N0<20>

C C







B B

PCIE_CTX_C_GRX_P0<20>

PCIE_CTX_C_GRX_N1<20>
PCIE_CTX_C_GRX_P1<20>

PCIE_CTX_C_GRX_N2<20>
PCIE_CTX_C_GRX_P2<20>

PCIE_CTX_C_GRX_N3<20>
PCIE_CTX_C_GRX_P3<20>

PCIE3_CTX_C_DRX_N<52>
PCIE3_CTX_C_DRX_P<52>

PCIE4_CTX_C_DRX_N<47>
PCIE4_CTX_C_DRX_P<47>

CC10 0.1U_0402_10V7-KDIS@
CC11 0.1U_0402_10V7-KDIS@

CC12 0.1U_0402_10V7-KDIS@
CC13 0.1U_0402_10V7-KDIS@

CC14 0.1U_0402_10V7-KDIS@
CC15 0.1U_0402_10V7-KDIS@

CC16 0.1U_0402_10V7-KDIS@
CC17 0.1U_0402_10V7-KDIS@

CC18 0.1U_0402_10V7-K
CC19 0.1U_0402_10V7-K

CC20 0.1U_0402_10V7-K
CC21 0.1U_0402_10V7-K





+1.05VS_PUSB3PLL

A A

RC87 3K_0402_1%

1 2
1 2

PCIE_CRX_GTX_N1<20>
PCIE_CRX_GTX_P1<20>

1 2
1 2

PCIE_CRX_GTX_N2<20>
PCIE_CRX_GTX_P2<20>

1 2
1 2

PCIE_CRX_GTX_N3<20>
PCIE_CRX_GTX_P3<20>

1 2
1 2

PCIE3_CRX_DTX_N<52>
PCIE3_CRX_DTX_P<52>

1 2
1 2

PCIE4_CRX_DTX_N<47>
PCIE4_CRX_DTX_P<47>

1 2
1 2

USB3P3_RXN<38>
USB3P3_RXP<38>

USB3P3_TXN<38>
USB3P3_TXP<38>

USB3P4_RXN<34>
USB3P4_RXP<34>

USB3P4_TXN<34>
USB3P4_TXP<34>

1 2

PCIE_RCOMP&PCIE_IREF (Shared with DMI)
Width 20Mil, Space 15Mil, Length 500Mil

PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P0

PCIE5_PTX_DRX_N0
PCIE5_PTX_DRX_P0

PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1

PCIE5_PTX_DRX_N1
PCIE5_PTX_DRX_P1

PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P2

PCIE5_PTX_DRX_N2
PCIE5_PTX_DRX_P2

PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3

PCIE5_PTX_DRX_N3
PCIE5_PTX_DRX_P3

PCIE3_CRX_DTX_N
PCIE3_CRX_DTX_P

PCIE3_CTX_DRX_N
PCIE3_CTX_DRX_P

PCIE4_CRX_DTX_N
PCIE4_CRX_DTX_P

PCIE4_CTX_DRX_N
PCIE4_CTX_DRX_P

USB3P3_RXN
USB3P3_RXP

USB3P3_TXN
USB3P3_TXP

USB3P4_RXN
USB3P4_RXP

USB3P4_TXN
USB3P4_TXP

PCIE_RCOMP

HSW_ULT_DDR3L

PCIE USB

11 OF 19

1 2
1 2

1 2
1 2

AN8

USB2N0

AM8

USB2P0

AR7

USB2N1

AT7

USB2P1

AR8

USB2N2

AP8

USB2P2

AR10

USB2N3

AT10

USB2P3

AM15

USB2N4

AL15

USB2P4

AM13

USB2N5

AN13

USB2P5

AP11

USB2N6

AN11

USB2P6

AR13

USB2N7

AP13

USB2P7

G20

USB3RN1

H20

USB3RP1

C33

USB3TN1

B34

USB3TP1

E18

USB3RN2

F18

USB3RP2

B33

USB3TN2

A33

USB3TP2

AJ10

USBRBIAS

AJ11

USBRBIAS

AN10

RSVD11

AM10

RSVD12

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

AL3
AT1
AH2
AV3

USB20_N4_TPANEL <51>
USB20_P4_TPANEL <51>

USB20_N4_WWAN <52>
USB20_P4_WWAN <52>

USB20_N0
USB20_P0

USB20_N1
USB20_P1

USB20_N2
USB20_P2

USB20_N3
USB20_P3

USB20_N4
USB20_P4

USB20_N5
USB20_P5

USB20_N6
USB20_P6

USB20_N7
USB20_P7

USB3P1_RXN
USB3P1_RXP

USB3P1_TXN
USB3P1_TXP

USB3P2_RXN
USB3P2_RXP

USB3P2_TXN
USB3P2_TXP

USBRBIAS



USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

RC81

1 2

22.6_0402_1%









USB20_N0 <40>
USB20_P0 <40>

USB20_N1 <41>
USB20_P1 <41>

USB20_N2 <34>
USB20_P2 <34>

USB20_N3 <34>
USB20_P3 <34>

USB20_N5 <50>
USB20_P5 <50>

USB20_N6 <52>
USB20_P6 <52>

USB20_N7 <38>
USB20_P7 <38>

USB3P1_RXN <40>
USB3P1_RXP <40>

USB3P1_TXN <40>
USB3P1_TXP <40>

USB3P2_RXN <41>
USB3P2_RXP <41>

USB3P2_TXN <41>
USB3P2_TXP <41>

USB_OC0# <41>
USB_OC1# <40>
USB_OC2# <34>







 











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USBRBIAS/USBRBIAS#

1. trace length and no longer than 450 mils to resistor.

2. Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils (0.381 mm).


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



USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

RPC13

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

+3V_PCH



Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

BDW_PCIE/USB BUS

BDW_PCIE/USB BUS

BDW_PCIE/USB BUS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

13 81

13 81

13 81

1.0

1.0

1.0

5

Haswell MCP (Power)

4

3

2

1

+1.05VS

D D

VCCSENSE<73>

+VCCIO_OUT

+VCCIOA_OUT

+1.05VS_VCCST

C C

+1.05VS_VCCST

RC119

1 2

0_0603_5%

TP28

1 2

RC122 150_0402_1%

1

VR_SVID_CLK<73>

VR_ON<73>

+1.05VS_VCCST

+VCC_CORE

12

RC120

100_0402_1%

RC121 0_0402_5%

VR_SVID_ALRT#_R
VR_SVID_CLK
VR_SVID_DAT
VCCST_PWRGD
VR_ON

VGATE<73>

22U_0603_6.3V6-M

VGATE

PWR_DEBUG

1U_0402_6.3VA-K

@

1

2

@

1

CC37

2

+VCC_CORE

12

CC38

0.5A

+VCC_CORE

+1.35V

TP6
TP7
TP8
TP9

1.4A

0.1A

3A

UC1L

L59

RSVD13

J58

RSVD14

AH26

VDDQ1

AJ31

VDDQ2

AJ33

VDDQ3

AJ37

VDDQ4

AN33

VDDQ5

AP43

VDDQ6

AR48

VDDQ7

AY35

VDDQ8

AY40

VDDQ9

AY44

VDDQ10

AY50

VDDQ11

F59

VCC1

N58

RSVD15

AC58

RSVD16

E63

VCC_SENSE

AB23

RSVD17

A59

VCCIO_OUT

E20

VCCIOA_OUT

AD23

RSVD18

AA23

RSVD19

AE59

RSVD20

L62

VIDALERT

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS344

H59

PWR_DEBUG

P62

VSS345

P60

1

RSVD_TP1

P61

1

RSVD_TP2

N59

1

RSVD_TP3

N61

1

RSVD_TP4

T59

RSVD21

AD60

RSVD22

AD59

RSVD23

AA59

RSVD24

AE60

RSVD25

AC59

RSVD26

AG58

RSVD27

U59

RSVD28

V59

RSVD29

AC22

VCCST1

AE22

VCCST2

AE23

VCCST3

AB57

VCC2

AD57

VCC3

AG57

VCC4

C24

VCC5

C28

VCC6

C32

VCC7

Broadwell-ULT_CL8064701614813_QFSY




HSW_ULT_DDR3L

HSW ULT POWER

12 OF 19

VCC8

VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

30.5A

+VCC_CORE

+1.35V

330U_D2_2V_Y

@

2.2U_0402_6.3V6-K

1

CC83

1

+

2

2

@

2.2U_0402_6.3V6-K
CC28

CC27

1

2

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K
CC30

CC29

1

1

2

2

HW 4PCS 2.2UF CAP Mounted
HW 6PCS 10UF CAP Mounted
PWR 2PCS 470U Near VR Output

VCC_SENSE

Length Match: No More Than 25Mil
Space: More Than 25Mil
GND Reference

10U_0603_6.3V6-M

10U_0603_6.3V6-M

@

1

CC31

2

10U_0603_6.3V6-M

@

1

1

CC32

CC33

2

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

CC34

2

10U_0603_6.3V6-M

1

1

CC35

CC36

2

2

SVID

1, Stripline Line, No More Than 6000Mil
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil

+VCC_CORE[1..68]

32A

+1.05VS_VCCST[1..3] 0.1A

1.4AVDDQ[1..11]

B B

+1.05VS_VCCST

RC124

0_0402_5%

VCCST_PG_EC<62>

1.05VS_PGOOD<10,62,70>

1 2

1 2

RC126 0_0402_5%@

DC1

RB521CS-30GT2RA_VMN2-2

1 2

12

RC123
10K_0402_5%

VCCST_PWRGD

VR_SVID_ALRT#<73>

SVID ALERT

RC161

75_0402_1%

+1.05VS_VCCST

Place the PU
resistors close to CPU

1 2

RC162

1 2

43_0402_1%

VR_SVID_ALRT#_RVR_SVID_ALRT#

SVID DATA

+1.05VS_VCCST

12

RC163
130_0402_1%

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

VR_SVID_DAT<73>

2014/09/07

2014/09/07

2014/09/07

2

Place the PU
resistors close to CPU

VR_SVID_DAT

Title

Title

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

14 81

14 81

14 81

1.0

1.0

1.0

5

4

3

2

1

Haswell MCP (Power2)

+1.05VS

1 2

2.2UH_LQM21PN2R2MC0D

1 2

2.2UH_LQM21PN2R2MC0D

D D

1 2

2.2UH_LQM21PN2R2MC0D

+1.05VS

1U_0402_10V6-K

10U_0603_6.3V6-M

1

CC39

2

1

CC46

2

+1.05VS_PLPTVCC1P05

LC1

+1.05VS_PLPTCLKPLL

LC2

+1.05VS_POPIPLL

LC3

1U_0402_10V6-K

1

CC47

2

+1.05VS_POPIPLL 57mA

Close J11 H11 H15

C C

+1.05VS

1U_0402_10V6-K

1

CC51

2

Close AG16

+3V_PCH

1U_0402_10V6-K

CC63

1

2

Close AH14

B B

+3VS

0.1U_0402_10V6-K

1

CC70

2

+1.05VS_PLPTCLKPLL 31mA

+1.05VS_PLPTCLKPLL +1.05VS_PLPTVCC1P05

CRB 100uF x1+1uF x1
PDG 1uF x2

+3V_PCH

22U_0603_6.3V6-M

1

2

Close AC9

VCC3_3[1:4] 41mA

+1.05VS

+1.05VS_POPIPLL

100U_1206_6.3V6-M

@

1

CC41

2

CRB 100uF x1+1uF x1
PDG 1uF x1

Close AA21

100U_1206_6.3V6-M

1

CC53

2

Close A20

CC64

Close AH11

+3VS

22U_0603_6.3V6-M

1

CC71

2

1 2

2.2UH_LQM21PN2R2MC0D

1 2

2.2UH_LQM21PN2R2MC0D

1U_0402_10V6-K

1

CC42

2

1U_0402_10V6-K

1

CC54

2

+3V_PCH

1U_0402_10V6-K

1

CC65

2

VCCSDIO 17mA

+3VS

1U_0402_10V6-K

+1.05VS_PUSB3PLL

LC4

+1.05VS_PSATA3PLL

LC5

VCCHSIO 1.838A +1.05VS_PUSB3PLL 41mA

+1.05VS

1U_0402_10V6-K

1

2

Close K9 ,L10 ,M9

+1.05VS

1U_0402_10V6-K

1

CC55

2

Close J17 R21

1

CC72

2

CC48

+RTCVCC

1U_0402_10V6-K

1U_0402_10V6-K

CC43

1

2

1U_0402_10V6-K

1

CC56

2

1

CC73

2

1U_0402_10V6-K

@

CC84

1

2

CRB 100uF x1+1uF x1
PDG 1uF x2

+1.05VS_PLPTVCC1P05 185mA

CRB 100uF x1+1uF x1
PDG 1uF x3

0.1U_0402_10V6-K

0.1U_0402_10V6-K

@

1

1

CC74

CC75

2

2

Close B18 and B11

Close J18,J17

VCCDSW 114mA

VCCDSW3_3

1U_0402_10V6-K

1

@

CC76

2

+3VL

+3VALW

+1.05VS_PUSB3PLL

100U_1206_6.3V6-M

1

2

100U_1206_6.3V6-M

1U_0402_10V6-K

1

CC57

2

1 2

RC127 0_0402_5%@

1 2

RC132 0_0402_5%

1U_0402_10V6-K

1

CC44

CC45

2

+1.05VS_PSATA3PLL 42mA

+1.05VS_PSATA3PLL

1

CC59

2

100U_1206_6.3V6-M

Close B11

1

2

CC60

VCCDSW3_3

2.2U_0402_6.3V6-K

1

CC62

2

1 2

RC130 0_0402_5%@

+3VS

1 2

RC133 0_0402_5%

+3VM

+1.05VS_PUSB3PLL

+1.05VS_PSATA3PLL

+1.05VS_POPIPLL

+1.05VS_PLPTVCC1P05

+1.05VS_PLPTCLKPLL

VCCSUS3_3[1:5] 65mA

+1.05VS

+3V_PCH

+3V_PCH

+3VS

+1.05VS

+3V_PCH

TP10

VCCHDA 11mA

+1.05VS_DCPSUS3

+1.05VS_DCPSUS2

VCCDSW3_3

TP11
TP12
TP13

+3VM_VCCSPI

B18
B11

1

Y20

AA21

W21

AH14

AH13

AC9

AA9

AH10

W9

J18
K19
A20
J17
R21
T21
K18

1

M20

1
1

V21
AE20
AE21

L10
M9

J13

UC1M

K9

VCCHSIO[1]
VCCHSIO[2]
VCCHSIO[3]

N8

VCC1_05[1]

P9

VCC1_05[2]
VCCUSB3PLL
VCCSATA3PLL

RSVD30
VCCAPLL[1]
VCCAPLL[2]

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCDSW3_3

V8

VCC3_3[1]
VCC3_3[2]

VCCCLK[1]
VCCCLK[2]
VCCACLKPLL
VCCCLK[3]
VCCCLK[4]
VCCCLK[5]
RSVD31
RSVD32
RSVD33
VCCSUS3_3[3]
VCCSUS3_3[4]

Broadwell-ULT_CL8064701614813_QFSY

RC131 0_0402_5%

+1.05VS

RC134 0_0603_5%@

+1.05VM

HSW_ULT_DDR3L

HSIO

OPI

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

1U_0402_10V6-K

Close AB8

1 2

1 2

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

13 OF 19

+1.05VS_DCPSUS4

1

@

CC66

2

+1.05VM_PCH_VCCASW

0.67 A

RTC

VCCSUS3_3[5]

VCCRTC
DCPRTC

SPI

CORE

USB2

VCCSPI

VCCASW[1]
VCCASW[2]

VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]

VCC1_05[7]
DCPSUSBYP[1]
DCPSUSBYP[2]

VCCASW[3]
VCCASW[4]

VCCASW[5]
DCPSUS1[1]
DCPSUS1[2]

VCCTS1_5

VCC3_3[3]
VCC3_3[4]

VCCSDIO[1]

VCCSDIO[2]

DCPSUS4

RSVD34
VCC1_05[8]
VCC1_05[9]

DCPSUS[4:1]

+1.05VS_DCPSUS3

1U_0402_10V6-K

1

@

CC67

2

Close J13 Close AH13

AH11
AG10
AE7

Y8

AG14
AG13

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8

J15
K14
K16

U8
T9

AB8

AC20
AG16
AG17

+1.05VS_DCPSUS4

1

+1.05VS_DCPSUS2

1U_0402_10V6-K

1

2

+3V_PCH
+RTCVCC

+DCPRTC

+3VM_VCCSPI

VCCASW[1:5] 658mA

+PCH_DCPSUSBYP

+PCH_DCPSUSBYP

+1.05VS_DCPSUS1

VCCTS1_5 3mA

@

CC68

T14

+1.05VM_PCH_VCCASW

+1.05VS

+1.05VM_PCH_VCCASW

+1.5VS
+3VS

+3VS

+1.05VS

1U_0402_10V6-K

Close AD10,AD8

+1.05VS_DCPSUS1

1

@

CC69

2

4

Close AH10

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

Title

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

15 81

15 81

15 81

1.0

1.0

1.0

Close K14,K16

VCCSPI 18mA

0.1U_0402_10V6-K

1

@

CC78

2

A A

Close Y8 Close AG19Close AE9 AF9 AG8

Close V8,W9

+1.05VM_PCH_VCCASW

22U_0603_6.3V6-M

1U_0402_10V6-K

CC77

1

2

5

1

2

CC79

Close U8,T9

+DCPRTC+3VM_VCCSPI

0.1U_0402_10V6-K

1

CC80

2

Close AE7

Close AG10

+PCH_DCPSUSBYP

1U_0402_10V6-K

1

CC81

2

5

4

3

2

1

Haswell MCP (VSS)

D D

HSW_ULT_DDR3L

A11

VSS1

A14

VSS2

A18

VSS3

A24

VSS4

A28

VSS5

A32

VSS6

A36

VSS7

A40

VSS8

A44

VSS9

A48

VSS10

A52

VSS11

A56

VSS12

AA1

VSS13

AA58

VSS14

AB10

VSS15

AB20

VSS16

AB22

VSS17

AB7

C C

B B

VSS18

AC61

VSS19

AD21

VSS20

AD3

VSS21

AD63

VSS22

AE10

VSS23

AE5

VSS24

AE58

VSS25

AF11

VSS26

AF12

VSS27

AF14

VSS28

AF15

VSS29

AF17

VSS30

AF18

VSS31

AG1

VSS32

AG11

VSS33

AG21

VSS34

AG23

VSS35

AG60

VSS36

AG61

VSS37

AG62

VSS38

AG63

VSS39

AH17

VSS40

AH19

VSS41

AH20

VSS42

AH22

VSS43

AH24

VSS44

AH28

VSS45

AH30

VSS46

AH32

VSS47

AH34

VSS48

AH36

VSS49

AH38

VSS50

AH40

VSS51

AH42

VSS52

AH44

VSS53

AH49

VSS54

AH51

VSS55

AH53

VSS56

AH55

VSS57

AH57

VSS58

AJ13

VSS59

AJ14

VSS60

AJ23

VSS61

AJ25

VSS62

AJ27

VSS63

AJ29

VSS64

Broadwell-ULT_CL8064701614813_QFSY

14 OF 19

VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

HSW_ULT_DDR3L

UC1N

UC1O

AP22

VSS129

AP23

VSS130

AP26

VSS131

AP29

VSS132

AP3

VSS133

AP31

VSS134

AP38

VSS135

AP39

VSS136

AP48

VSS137

AP52

VSS138

AP54

VSS139

AP57

VSS140

AR11

VSS141

AR15

VSS142

AR17

VSS143

AR23

VSS144

AR31

VSS145

AR33

VSS146

AR39

VSS147

AR43

VSS148

AR49

VSS149

AR5

VSS150

AR52

VSS151

AT13

VSS152

AT35

VSS153

AT37

VSS154

AT40

VSS155

AT42

VSS156

AT43

VSS157

AT46

VSS158

AT49

VSS159

AT61

VSS160

AT62

VSS161

AT63

VSS162

AU1

VSS163

AU16

VSS164

AU18

VSS165

AU20

VSS166

AU22

VSS167

AU24

VSS168

AU26

VSS169

AU28

VSS170

AU30

VSS171

AU33

VSS172

AU51

VSS173

AU53

VSS174

AU55

VSS175

AU57

VSS176

AU59

VSS177

AV14

VSS178

AV16

VSS179

AV20

VSS180

AV24

VSS181

AV28

VSS182

AV33

VSS183

AV34

VSS184

AV36

VSS185

AV39

VSS186

AV41

VSS187

AV43

VSS188

AV46

VSS189

AV49

VSS190

AV51

VSS191

AV55

VSS192

Broadwell-ULT_CL8064701614813_QFSY

15 OF 19

VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49

D5
D50
D51
D53
D54
D55
D57
D59
D62

D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22

G3

G5

G6

G8
H13

HSW_ULT_DDR3L

UC1P

VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299

Broadwell-ULT_CL8064701614813_QFSY

QFSY@

16 OF 19

VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337

VSS338
VSS339
VSS340

VSS_SENSE

VSS341

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62

1 2

RC142 0_0402_5%

AH16

12

RC143
100_0402_1%

VSSSENSE <73>

VSS_SENSE

Length Match: No More Than 25Mil
Space: More Than 25Mil
GND Reference

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

2013/09/07

2013/09/07

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

16 81

16 81

16 81

1.0

1.0

1.0

5

Haswell MCP (OTHER)

4

3

2

1

D D

UC1Q

DC_TEST_AY2_AW2

TP14

DC_TEST_AY3_AW3

1

TP_DC_TEST_AY60

@

DC_TEST_AY61_AW61
DC_TEST_AY62_AW62

1

TP_DC_TEST_B2

TP17

DC_TEST_A3_B3

@

DC_TEST_A61_B61
DC_TEST_A62_B63

DC_TEST_C1_C2

C C

1

TP24

1

@

TP28 remove for layout routing

TP26

TP30

TP32@

@

1

@

1

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

Broadwell-ULT_CL8064701614813_QFSY

UC1R

AT2

RSVD35

AU44

RSVD36

AV44

RSVD37

D15

RSVD38

F22

RSVD39

H22

RSVD40

J21

RSVD41

Broadwell-ULT_CL8064701614813_QFSY

UC1S

HSW_ULT_DDR3L

17 OF 19

HSW_ULT_DDR3L

18 OF 19

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60

DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1

DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2

DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

A3

DC_TEST_A3_B3

A4

TP_DC_TEST_A4

A60

TP_DC_TEST_A60

A61

DC_TEST_A61_B61

A62

TP_DC_TEST_A62

AV1

TP_DC_TEST_AV1

AW1

TP_DC_TEST_AW1

AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

TP_DC_TEST_AW63

N23
R23
T23
U10

AL1
AM11
AP7
AU10
AU15
AW14
AY14

1

TP15

@

1

TP16

@

1

TP18@

1

TP19@

1

TP20

@

1

TP21

@

1

TP22

1

TP23

@

1

@

TP25

1

TP27

@
@

1

TP29

@

1

TP31

@

1

TP33

1

TP34

@

1

@

TP35

@

CFG4

*L: Embedded DisplayPort Enabled
H: Embedded DisplayPort Disabled

CFG3

1: Disable
0: Enable, Set DFX Enabled BIT
In Debug Interface MSR

CFG4

CFG0

CFG1

CFG8

CFG9

CFG10

CFG3

1 2

RC144 1K_0402_1%

12

@

RC145 1K_0402_1%

RC146 1K_0402_1%

RC147 1K_0402_1%

RC148 1K_0402_1%

RC149 1K_0402_1%

RC150 1K_0402_1%

12

@

12

@

12

@

12

@

12

@

B B

CFG4

RC152 49.9_0402_1%

CFG_RCOMP&TD_IREF

Width 20Mil
Space 15Mil
Length 500Mil

A A

RC153 8.2K_0402_1%

5

TP36
TP38
TP40
TP41

TP44
TP46
TP47
TP48
TP50
TP52
TP53
TP55
TP56
TP57
TP58

TP61
TP62
TP63
TP65

1

CFG0

1

CFG1

@

1

CFG2

@

1

CFG3

@
@

1

CFG5

1

CFG6

@

1

CFG7

@

1

CFG8

@

1

CFG9

@

1

CFG10

@

1

CFG11

@

1

CFG12

@

1

CFG13

@

1

CFG14

@

1

CFG15

@
@

1

CFG16

1

CFG18

@

1

CFG17

@

1

CFG19

@
@

12

12

CFG_RCOMP

TD_IREF

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD53

E1

RSVD54

D1

RSVD55

J20

RSVD56

H18

RSVD57

B12

TD_IREF

Broadwell-ULT_CL8064701614813_QFSY

RESERVED

PROC_OPI_RCOMP

19 OF 19

4

RSVD_TP5
RSVD_TP6

RSVD_TP7
RSVD_TP8

RSVD58

RSVD_TP9

RSVD_TP10

RSVD_TP11

RSVD59

RSVD60
RSVD61

RSVD62
RSVD63

VSS342
VSS343

RSVD64
RSVD65

AV63
AU63

C63
C62
B43

A51
B51

L60

N60

W23
Y22
AY15

PROC_OPI_COMP

AV62
D58

P22
N21

P20
R20

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

TP37

1

@

TP39

@

1

TP43

1

@

TP45

@

1

TP49

1

TP51

@
@

1

TP54

@

1

TP59

1

TP60

@
@

1

TP64

1

TP66

@
@

1

TP67

1

TP68

@
@

3

RC151 49.9_0402_1%

2013/09/07

2013/09/07

2013/09/07

12

OPI_RCOMP

Width 20Mil
Space 15Mil
Length 500Mil

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/09/07

2014/09/07

2014/09/07

Title

Title

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

17 81

17 81

17 81

1.0

1.0

1.0

5

DIMM1@

RD2

2_0402_1%

DIMM1@

+1.35V

1.8K_0402_1%

12

12

RD1

DIMM1@

1.8K_0402_1%

RD3

2.2U_0402_6.3V6-K

0.1U_0402_10V7-K

DIMM1@

1

1

CD3

CD1

@

2

2

SA_DIMM_VREFDQ<6>

1 2

D D

1

CD2

DIMM1@

0.022U_0402_25V7-K

2

12

RD4

DIMM1@

24.9_0402_1%

Close to JDIMM1

C C

B B

A A

DDRA_CKE0_DIMMA<6>

DDR_A_BS2<6>

SA_CLK_DDR0<6>
SA_CLK_DDR#0<6>

DDR_A_BS0<6>

DDR_A_WE#<6>
DDR_A_CAS#<6>

DDRA_CS1_DIMMA#<6>

+3VS

+0.675VS +0.675VS

2.2U_0402_6.3V6-K

@

1

CD29

2

5

0.1U_0402_10V6-K

DIMM1@

DDRA_CKE0_DIMMA

DDR_A_BS2

DDRA_CS1_DIMMA#

0_0402_5%

CD30

1

2

12

+1.35V +1.35V

+V_DDR_REFA

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

SA_CLK_DDR0
SA_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

0_0402_5%

12

RD13

RD14

4

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

DQS#0

VSS10

VSS12

VSS14

VSS16

VSS17

VSS19

VSS21

VSS24

VSS26

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

EVENT#

Channel A

4

DQ4
DQ5

VSS3

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1

CK1#

BA1

RAS#

ODT0

ODT1

NC2

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5

DQ46
DQ47

DQ52
DQ53

DM6

DQ54
DQ55

DQ60
DQ61

DQS7

DQ62
DQ63

SDA

SCL

VTT2

ME@

A15
A14

A11

S0#

3

DDR_A_DQS#[0..7] <6>

RD9

1.8K_0402_1%

RD11

1.8K_0402_1%

+VREF_CA <19>

2013/09/07

2013/09/07

2013/09/07

DDR_A_DQS[0..7] <6>

DDR_A_D[0..63] <6>

DDR_A_MA[0..15] <6>

All VREF traces should
have 10 mil trace width

RD10

1 2

2_0402_1%

1

2

12

DDR_PG_CTRL<5>

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

CD12

0.022U_0402_25V7-K

RD12

24.9_0402_1%

SM_PG_CTRL

Deciphered Date

Deciphered Date

Deciphered Date

2
4

DDR_A_D4

6

DDR_A_D5

8
10

DDR_A_DQS#0

12

DDR_A_DQS0

14
16

DDR_A_D6

18

DDR_A_D7

20
22

DDR_A_D12

24

DDR_A_D13

26
28
30

DDR3_DRAMRST#

32
34

DDR_A_D14

36

DDR_A_D15

38
40

DDR_A_D20

42

DDR_A_D21

44
46
48
50

DDR_A_D22

52

DDR_A_D23

54
56

DDR_A_D28

58

DDR_A_D29

60
62

DDR_A_DQS#3

64

DDR_A_DQS3

66
68

DDR_A_D30

70

DDR_A_D31

72

74

DDRA_CKE1_DIMMA

76
78

DDR_A_MA15

80

DDR_A_MA14

82
84

DDR_A_MA11

86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_MA7

DDR_A_MA6

DDR_A_MA4

DDR_A_MA2

DDR_A_MA0

SA_CLK_DDR1

SA_CLK_DDR#1

DDR_A_BS1

DDR_A_RAS#

DDRA_CS0_DIMMA#

SA_ODT0

SA_ODT1

+VREF_CA

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D44

DDR_A_D45

DDR_A_DQS#5

DDR_A_DQS5

DDR_A_D46

DDR_A_D47

DDR_A_D52

DDR_A_D53

DDR_A_D54

DDR_A_D55

DDR_A_D60

DDR_A_D61

DDR_A_DQS#7

DDR_A_DQS7

DDR_A_D62

DDR_A_D63

A7

A6
A4

A2
A0

G2

+1.35V

12

RD21

470_0402_5%

1

CD18

2

DDR3_DRAMRST# <19,5>

+1.35V

12

12

1

@

2

DDRA_CKE1_DIMMA <6>

SA_CLK_DDR1 <6>
SA_CLK_DDR#1 <6>

DDR_A_BS1 <6>
DDR_A_RAS# <6>

DDRA_CS0_DIMMA# <6>

0.1U_0402_10V7-K

2.2U_0402_6.3V6-K

DIMM1@

1

CD17

2

CD59

0.1U_0402_10V7-K

@

close to JDDR3L.126

PM_SMB_DAT <19,49,9>
PM_SMB_CLK <19,49,9>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2

SM_DIMM_VREFCA <6>

DDR_PG_CTRL

12

RD23

220K_0402_5%

12

RD24

@

2M_0402_5%

2

Layout Note:
Place near JDIMM1

DIMM1@

DIMM1@

CD13

CD14

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

1

2

2

DIMM1@

CD8

CD9

1U_0402_6.3VA-K

1U_0402_6.3VA-K

@

1

1

2

2

DIMM1@

CD23

1U_0402_6.3VA-K

1

2

UD1

NC11Vcc

2

A

3

GND

74AUP1G07GF_SOT891-6_1X1

2

G

2014/09/07

2014/09/07

2014/09/07

6

5

NC2

4

Y

+1.35V+5V_DDR

QD1

13

D

LBSS138LT1G_1N_SOT23-3

S

1

DIMM1@

DIMM1@

CD15

10U_0603_6.3V6-M

DIMM1@

CD16

10U_0603_6.3V6-M

1

1

2

2

DIMM1@

CD19

10U_0603_6.3V6-M

DIMM1@

CD21

CD20

10U_0603_6.3V6-M

1

1

2

2

CD22

10U_0603_6.3V6-M

330U_D2_2V_Y

1

1

+

2

2

For RF solution.

DIMM1@

CD11

CD10

1U_0402_6.3VA-K

1U_0402_6.3VA-K

@

1

2

Layout Note:
Place near JDIMM1.203,204

DIMM1@

CD24

1U_0402_6.3VA-K

1

2

+1.35V

1 2

RD5 66.5_0402_1%DIMM1@

1 2

RD6 66.5_0402_1%DIMM1@

1 2

RD7 66.5_0402_1%DIMM2@

1 2

RD8 66.5_0402_1%DIMM2@

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

2

CD25

1U_0402_6.3VA-K

@

1

2

1

CD61

0.1U_0402_10V7-K

2

XXXX

XXXX

XXXX

Custom

Custom

Custom

2200P_0402_50V7-K

1U_0402_6.3VA-K

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

CRF1

RF_NS@

CD26

@

1

2

1

2

SM_PG_CTRL

CRF2

47P_0402_50V8-J

RF_NS@

1

2

+0.675VS

SM_PG_CTRL <69>

SA_ODT0
SA_ODT1

SB_ODT0
SB_ODT1

SB_ODT0 <19>
SB_ODT1 <19>

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

18 81

18 81

18 81

+1.35V

1.0

1.0

1.0

5

+1.35V

12

RD15

DIMM2@

RD17

SB_DIMM_VREFDQ<6>

D D

DIMM2@

DIMM2@

1 2

1

2_0402_1%

CD310.022U_0402_25V7-K

DIMM2@

2

12

RD1824.9_0402_1%

1.8K_0402_1%

12

RD16

DIMM2@

1.8K_0402_1%

2.2U_0402_6.3V6-K

CD32

0.1U_0402_10V7-K

1

1

CD33

DIMM2@

@

2

2

Close to JDIMM2

DDRB_CKE0_DIMMB<6>

+3VS

+0.675VS

DDR_B_BS2<6>

SB_CLK_DDR0<6>
SB_CLK_DDR#0<6>

DDR_B_BS0<6>

DDR_B_WE#<6>
DDR_B_CAS#<6>

DDRB_CS1_DIMMB#<6>

+3VS

12

RD19

DIMM2@

10K_0402_5%

2.2U_0402_6.3V6-K

CD58

0.1U_0402_10V6-K

@

1

1

DIMM2@

CD57

2

2

C C

B B

A A

5

4

+1.35V +1.35V

JDIMM2

+V_DDR_REFB

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D24
DDR_B_D25

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_B_D16
DDR_B_D17

DDR_B_D18
DDR_B_D19

DDRB_CKE0_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

SB_CLK_DDR0
SB_CLK_DDR#0

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13

DDRB_CS1_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

0_0402_5%

12

RD20

1

VREF_DQ

3

VSS_1

5

DQ0

7

DQ1

9

VSS_3

11

DM0

13

VSS_5

15

DQ2

17

DQ3

19

VSS_7

21

DQ8

23

DQ9

25

VSS_9

27

DQS1#

29

DQS1

31

VSS_11

33

DQ10

35

DQ11

37

VSS_13

39

DQ16

41

DQ17

43

VSS_15

45

DQS2#

47

DQS2

49

VSS_17

51

DQ18

53

DQ19

55

VSS_19

57

DQ24

59

DQ25

61

VSS_21

63

DM3

65

VSS_23

67

DQ26

69

DQ27

71

VSS_25

73

CKE0

75

VDD_1

77

NC_1

79

BA2

81

VDD_3

83

A12/BC#

85

A9

87

VDD_5

89

A8

91

A5

93

VDD_7

95

A3

97

A1

99

VDD_9

101

CK0

103

CK0#

105

VDD_11

107

A10/AP

109

BA0

111

VDD_13

113

WE#

115

CAS#

117

VDD_15

119

A13

121

S1#

123

VDD_17

125

TEST

127

VSS_27

129

DQ32

131

DQ33

133

VSS_29

135

DQS4#

137

DQS4

139

VSS_31

141

DQ34

143

DQ35

145

VSS_33

147

DQ40

149

DQ41

151

VSS_36

153

DM5

155

VSS_37

157

DQ42

159

DQ43

161

VSS_39

163

DQ48

165

DQ49

167

VSS_41

169

DQS6#

171

DQS6

173

VSS_43

175

DQ50

177

DQ51

179

VSS_45

181

DQ56

183

DQ57

185

VSS_47

187

DM7

189

VSS_49

191

DQ58

193

DQ59

195

VSS_51

197

SA0

199

VDDSPD

201

SA1

203

VTT_1

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

Channel B

<Address: SA1:SA0=10>

DIMM_2 STD H:4mm

4

VSS_2

DQ4
DQ5

VSS_4

DQS0#

DQS0

VSS_6

DQ6
DQ7

VSS_8

DQ12
DQ13

VSS_10

DM1

RESET#

VSS_12

DQ14
DQ15

VSS_14

DQ20
DQ21

VSS_16

DM2

VSS_18

DQ22
DQ23

VSS_20

DQ28
DQ29

VSS_22

DQS3#

DQS3

VSS_24

DQ30
DQ31

VSS_26

CKE1

VDD_2

VDD_4

VDD_6

VDD_8

VDD_10

CK1#

VDD_12

RAS#

VDD_14

ODT0

VDD_16

ODT1

NC_2

VDD_18

VREF_CA

VSS_28

DQ36
DQ37

VSS_30

DM4

VSS_32

DQ38
DQ39

VSS_34

DQ44
DQ45

VSS_35

DQS5#

DQS5

VSS_38

DQ46
DQ47

VSS_40

DQ52
DQ53

VSS_42

DM6

VSS_44

DQ54
DQ55

VSS_46

DQ60
DQ61

VSS_48

DQS7#

DQS7

VSS_50

DQ62
DQ63

VSS_52

EVENT#

SDA

VTT_2

GND2

BOSS2

ME@

A15
A14

A11

CK1

BA1

S0#

SCL

3

2013/09/07

2013/09/07

2013/09/07

DDR_B_DQS#[0..7] <6>

DDR_B_DQS[0..7] <6>

DDR_B_D[0..63] <6>

DDR_B_MA[0..15] <6>

+VREF_CA <18>

All VREF traces should
have 10 mil trace width

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2
4

DDR_B_D4

6

DDR_B_D5

8
10

DDR_B_DQS#0

12

DDR_B_DQS0

14
16

DDR_B_D6

18

DDR_B_D7

20
22

DDR_B_D12

24

DDR_B_D13

26
28
30

DDR3_DRAMRST#

32
34

DDR_B_D14

36

DDR_B_D15

38
40

DDR_B_D28

42

DDR_B_D29

44
46
48
50

DDR_B_D30

52

DDR_B_D31

54
56

DDR_B_D20

58

DDR_B_D21

60
62

DDR_B_DQS#2

64

DDR_B_DQS2

66
68

DDR_B_D22

70

DDR_B_D23

72

74

DDRB_CKE1_DIMMB

76
78

DDR_B_MA15

80

DDR_B_MA14

82
84

DDR_B_MA11

86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_B_MA7

DDR_B_MA6

DDR_B_MA4

DDR_B_MA2

DDR_B_MA0

SB_CLK_DDR1

SB_CLK_DDR#1

DDR_B_BS1

DDR_B_RAS#

DDRB_CS0_DIMMB#

SB_ODT0

SB_ODT1

+VREF_CA

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39

DDR_B_D44

DDR_B_D45

DDR_B_DQS#5

DDR_B_DQS5

DDR_B_D46

DDR_B_D47

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55

DDR_B_D60

DDR_B_D61

DDR_B_DQS#7

DDR_B_DQS7

DDR_B_D62

DDR_B_D63

+0.675VS

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A7

A6
A4

A2
A0

@

PM_SMB_DAT <18,49,9>
PM_SMB_CLK <18,49,9>

Issued Date

Issued Date

Issued Date

3

1

2

DDR3_DRAMRST# <18,5>

CD60

0.1U_0402_10V7-K

DDRB_CKE1_DIMMB <6>

SB_CLK_DDR1 <6>
SB_CLK_DDR#1 <6>

DDR_B_BS1 <6>
DDR_B_RAS# <6>

DDRB_CS0_DIMMB# <6>
SB_ODT0 <18>

SB_ODT1 <18>

1

CD49

DIMM2@

0.1U_0402_10V7-K

2

2

2

DIMM2@

CD42

10U_0603_6.3V6-M

CD38

1U_0402_6.3VA-K

2014/09/07

2014/09/07

2014/09/07

1

Layout Note:
Place near JDIMM2

+0.675VS

10U_0603_6.3V6-M

19 81

19 81

19 81

+1.35V

1.0

1.0

1.0

DIMM2@

DIMM2@

CD43

10U_0603_6.3V6-M

1

1

2

2

DIMM2@

CD39

1U_0402_6.3VA-K

@

1

1

2

2

DIMM2@

CD51

1U_0402_6.3VA-K

1

2

DIMM2@

CD44

CD45

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

1

2

2

DIMM2@

CD40

CD41

1U_0402_6.3VA-K

1U_0402_6.3VA-K

@

1

1

2

2

Layout Note:
Place near JDIMM2.203,204

DIMM2@

DIMM2@

CD53

CD52

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1U_0402_6.3VA-K

1

2

Custom

Custom

Custom

XXXX

XXXX

XXXX

1U_0402_6.3VA-K

1

2

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

DIMM2@

DIMM2@

CD47

CD46

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

1

2

2

For RF solution.

CRF3

CRF4

2200P_0402_50V7-K

47P_0402_50V8-J

RF_NS@

RF_NS@

1

1

2

2

DIMM2@

DIMM2@

CD55

CD54

1

2

10U_0603_6.3V6-M

1U_0402_6.3VA-K

1

2

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

DIMM2@

CD48

10U_0603_6.3V6-M

1

2

DIMM2@

CD56

1

2

1

2

UV1A

OPAL@

PART 1 0F 9

3

4

5

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

+3VS_VGA

12

RV9
10K_0402_5%

@

PLT_RST_VGA# <21,76>

12

RV167
100K_0402_5%

DIS@

1 2

RV4 0_0402_5%

1 2

RV5 0_0402_5%

1 2

RV7 1K_0402_5%DIS@

+3VS_VGA

@

12

CV19

0.1U_0402_10V7-K

1

@

2

0.1U_0402_10V7-K

2N7002WT1G_1N_SC-70-3

1 3

D

SB00000YY00

1 2

RV16 0_0402_5%

CV20

1

@

2

PLT_RST_VGA#

12

RV11

@

10K_0402_5%

2

G

@

1 2

RC114 0_0402_5%@



1

IN1

2

IN2

DIS@

VGA_ON<11,29,72,76,77>

PCIE_CTX_C_GRX_P0<13>
PCIE_CTX_C_GRX_N0<13>

PCIE_CTX_C_GRX_P1<13>
PCIE_CTX_C_GRX_N1<13>

PCIE_CTX_C_GRX_P2<13>
PCIE_CTX_C_GRX_N2<13>

PCIE_CTX_C_GRX_P3<13>
PCIE_CTX_C_GRX_N3<13>

+3VS

5

VCC

OUT

GND

3

CLK_PCIE_VGA
CLK_PCIE_VGA#

4

RV13

10K_0402_5%

A A

CTX0

CTX1

CTX2

CTX3

B B

PLTRST#<10>

DGPU_HOLD_RST#<11>

C C

D D

PLTRST#

DGPU_HOLD_RST#

MC74VHC1G08DFT2G_SC70-5

UV15

CLK_PCIE_VGA<8>
CLK_PCIE_VGA#<8>

CLKREQ_PCIE4_VGA#<8>

1

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AH16

TEST_PG

AA30

PERSTB

216-0855000_A0_FCBGA962

+3VS_VGA

12

RV14

@

2

10K_0402_5%

CLK_REQ_GPU#

RV15
10K_0402_5%

@

1 2

QV1

@

S

PCI EXPRESS INTERFACE

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

CLK_REQ_GPU# <21>

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

PCIE_TX8P

PCIE_TX8N

PCIE_TX9P

PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

Y33

PCIE_CRX_C_GTX_P0

Y32

PCIE_CRX_C_GTX_N0

W33

PCIE_CRX_C_GTX_P1

W32

PCIE_CRX_C_GTX_N1

U33

PCIE_CRX_C_GTX_P2

U32

PCIE_CRX_C_GTX_N2

U30

PCIE_CRX_C_GTX_P3

U29

PCIE_CRX_C_GTX_N3

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

Y30

RV6 1.69K_0402_1%DIS@

Y29

RV8 1K_0402_5%DIS@

1 2

1 2

CV1 0.1U_0402_10V7-KDIS@
CV2 0.1U_0402_10V7-KDIS@

CV3 0.1U_0402_10V7-KDIS@
CV4 0.1U_0402_10V7-KDIS@

CV5 0.1U_0402_10V7-KDIS@
CV6 0.1U_0402_10V7-KDIS@

CV7 0.1U_0402_10V7-KDIS@
CV8 0.1U_0402_10V7-KDIS@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P0 <13>
PCIE_CRX_GTX_N0 <13>

PCIE_CRX_GTX_P1 <13>
PCIE_CRX_GTX_N1 <13>

PCIE_CRX_GTX_P2 <13>
PCIE_CRX_GTX_N2 <13>

PCIE_CRX_GTX_P3 <13>
PCIE_CRX_GTX_N3 <13>

160mA

+1.8VS_VGA MPLL_PVDD

LV3

DIS@

1 2

BLM18PG221SN1D_2P

CV220

DIS@

10U_0603_6.3V6-M

1

2

75mA

+0.95VS_VGA

+1.8VS_VGA SPLL_PVDD

LV4

DIS@

1 2

BLM18PG121SN1D_2P

CV222

DIS@

10U_0603_6.3V6-M

1

2

0.1U_0402_10V7-K

1U_0402_10V6-K

1

1

DIS@

DIS@

2

2

CV225

CV221

100mA

+0.95VS_VGA

LV5

DIS@

1 2

BLM18PG121SN1D_2P

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

CV223

CV226

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

10U_0603_6.3V6-M

1

DIS@

2

1U_0402_10V6-K

1

DIS@

2

Deciphered Date

Deciphered Date

Deciphered Date

CV224

4

SPLL_VDDC

0.1U_0402_10V7-K

1

DIS@

2

CV219

1U_0402_10V6-K

1

DIS@

2

2014/07/01

2014/07/01

2014/07/01

CV218

DIS@

CRX0

CRX1

CRX2

CRX3

1

2

UV1C

PART 3 0F 9

AV33

AU34

AW34

AW35

AK10
AL10

XTALOUT

1

CV18

DIS@

22P_0402_50V8-J

2

20 81

20 81

20 81

XTALIN

XTALOUT

1.0

1.0

1.0

XTALIN

XTALOUT

H7

MPLL_PVDD_1

0.1U_0402_10V7-K

H8

MPLL_PVDD_2

AM10

SPLL_PVDD

AN9

SPLL_VDDC

AN10

SPLL_PVSS

AF30

NC_XTAL_PVDD

AF31

NC_XTAL_PVSS

216-0855000_A0_FCBGA962

XTALIN

1

CV17

DIS@

22P_0402_50V8-J

2

Title

Title

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

PLLS/XTAL

RV10

1 2

1M_0402_5%

YV1

4

NC2

1

OSC1

27MHZ_16PF_7V27000011

XO_IN

XO_IN2

CLKTESTA
CLKTESTB

DIS@

DIS@

3

OSC2

2

NC1

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

5

5

4

3

2

1

VREFG

FDO

UV1B

MUTI GFX

AD29

GENLK_CLK

AC29

GENLK_VSYNC

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AJ23

SMBCLK

AH23

SMBDATA

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21

AK13

GPIO_22_ROMCSB

AN13

CLKREQB

AG32

GPIO_29

AG33

GPIO_30

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AC30

CEC_1

AK24

HPD1

AH13

VREFG

AL21

PX_EN

AD28

TESTEN

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

THERMAL

AF29

DPLUS

AG29

DMINUS

AK32

GPIO_28_FDO

AL31

TS_A

AJ32

TSVDD

AJ33

TSVSS

216-0855000_A0_FCBGA962

PART 2 0F 9

DPA

DPB

DPC

DPD

SMBus

I2C

DAC1

MLPS

BACO

DDC/AUX

DEBUG

TXCAP_DPA3P

TXCAM_DPA3N

TX0P_DPA2P
TX0M_DPA2N

TX1P_DPA1P
TX1M_DPA1N

TX2P_DPA0P
TX2M_DPA0N

TXCBP_DPB3P

TXCBM_DPB3N

TX3P_DPB2P
TX3M_DPB2N

TX4P_DPB1P
TX4M_DPB1N

TX5P_DPB0P
TX5M_DPB0N

TXCCP_DPC3P

TXCCM_DPC3N

TX0P_DPC2P

TX0M_DPC2N

TX1P_DPC1P

TX1M_DPC1N

TX2P_DPC0P

TX2M_DPC0N

TXCDP_DPD3P

TXCDM_DPD3N

TX3P_DPD2P

TX3M_DPD2N

TX4P_DPD1P

TX4M_DPD1N

TX5P_DPD0P

TX5M_DPD0N

AVSSN_1

AVSSN_2

AVSSN_3

HSYNC

VSYNC

AVSSQ

VDD1DI
VSS1DI

NC_TSVSSQ

DDC1CLK

DDC1DATA

AUX1P
AUX1N

DDC2CLK

DDC2DATA

AUX2P
AUX2N

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDCCLK_AUX6P

DDCDATA_AUX6N

DDCVGACLK

DDCVGADATA

AU24
AV23

AT25
AR24

AU26
AV25

AT27
AR26

AR30
AT29

AV31
AU30

VID CODES

AR32
AT31

AT33
AU32

AU14
AV13

AT15
AR14

AU16
AV15

AT17
AR16

AU20
AT19

AT21
AR20

AU22
AV21

AT23
AR22

AD39

R

AD37

AE36

G

AD35

AF37

B

AE38

AC36
AC38

AB34

RSET

AD34

AVDD

AE34

AC33
AC34

V13

NC_1

U13

NC_2

AF33
AF32

NC_7

AA29

NC_8

AG21

NC_9

AC32

NC_5

AC31

NC_3

AD30

NC_4

AD32

NC_6

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26
AN26

AM27
AL27

AM19
AL19

AN20
AM20

AL30
AM30

AL29
AM29

AN21
AM21

AK30
AK29

AJ30
AJ31

PS_0

PS_1

PS_2

PS_3

0

110

PLT_RST_VGA#<20,76>

SVDSVC

00

11

SVD

GPIO15_PWRCNTL_0

SVC

Keep voltage level.

+1.8VS_VGA

12

RV148

DIS@

499_0402_1%

8.45K_0402_1%

8.45K_0402_1%

4.75K_0402_1%

+3VS_VGA

2

D D

EC_SMB_CK3<34,55,62,9>

EC_SMB_DA3<34,55,62,9>

PU AT EC SIDE, +3VS AND 4.7K

C C

B B

+3VS_VGA

A A

6 1

D

DIS@

2N7002KDWH_SOT363-6

0_0402_5%

12

RV131
10K_0402_5%

@

G

S

QV5A

12

RV144

@

DIS@

2N7002KDWH_SOT363-6

VGA_AC_DC#<62>

GPU_VR_HOT#<62,76>

12

RV132
10K_0402_5%

@

5

3 4

D

QV5B

12

RV135
10K_0402_5%

@

SMBCLK

G

SMBDAT

S

12

RV1420_0402_5% @

1 2

VGA_AC_DC# GPIO5_AC_BATT

RB751V-40_SOD323-2

SCS00006S00

DIS@

1 2

RV149 0_0402_5%@

+1.8VS_VGA

RV128
499_0402_1%

DIS@

1 2

CV214

0.1U_0402_10V7-K

1

@

2

RV160
249_0402_1%

DIS@

1 2

12

RV136
10K_0402_5%

@

JTAG_TRSTB
JTAG_TMS
JTAG_TDI
JTAG_TDO

+3VS_VGA

+3VS_VGA

12

RV117

DIS@

2.2K_0402_5%

DV5

NC but reserved PU resistor

CLK_REQ_GPU#<20>

1 2

RV99 45.3K_0402_1%DIS@

1 2

RV98 45.3K_0402_1%DIS@

SMBCLK
SMBDAT

+3VS_VGA

RV129 0_0402_5%
RV130 100_0402_5%

1

TPV13Test_Point_20MIL

1

TPV14Test_Point_20MIL

RV138
RV139
RV140

1

TPV3Test_Point_20MIL

1

TPV4Test_Point_20MIL

1

TPV5Test_Point_20MIL

1

TPV6Test_Point_20MIL

1 2

@

1 2

@

I2CS_SCL
I2CS_SDA

@

1 2
1 2

@

1 2

GPIO5_AC_BATT

GPIO8_ROMSO
GPIO9_ROMSI
GPIO10_ROMSCK

GPIO15_PWRCNTL_0

GPIO17_THERMAL_INT

GPIO19_CTF
GPIO20_PWRCNTL_1

GPIO22_ROMCSB

10K_0402_5%
10K_0402_5%
10K_0402_5%@

PX5.0 doesn't need this function. Leave as NC.

1 2

1

RV101 0_0402_5%@

CV215

TPV12Test_Point_20MIL

12

RV137
10K_0402_5%

@

0.1U_0402_10V7-K

1

DIS@

2

RV147

DIS@

1 2

10K_0402_5%

+3VS_VGA

13mA

+1.8VS_VGA

@

1 2

RV93 5.11K_0402_1%

1 2

RV94 1K_0402_5%DIS@

LV6

1 2

BLM15PX121SN1D_2P

E450 unused.

CV216

DIS@

DIS@

1

JTAG_TRSTB

TPV7Test_Point_20MIL

1

JTAG_TDI

TPV8Test_Point_20MIL

1

JTAG_TCK

TPV9Test_Point_20MIL

1

JTAG_TMS

TPV10Test_Point_20MIL

1

JTAG_TDO

TPV11Test_Point_20MIL

CV217

10U_0603_6.3V6-M

1U_0402_10V6-K

1

1

DIS@

2

2

After check with AE, can leave NC for GPIO17.

GPIO17_THERMAL_INT

GPIO19_CTF

RV118 10K_0402_5%@

2K_0402_1%

DIS@

RV104 47K_0402_5%

RV102 47K_0402_5%@

12

PLT_RST_VGA#

Boot Voltage

1.1V

1.0V

0.9V(Default)

0.8V

1 2

RV89 0_0402_5%

1 2

RV90 0_0402_5%

RV145
10K_0402_5%

DIS@

+1.8VS_VGA

12

RV112

DIS@

RV113

DIS@

+1.8VS_VGA

RV106

@

RV109

PS_0

CV213

0.1U_0402_10V7-K

12

1

@

2

12

PS_1

CV212

0.1U_0402_10V7-K

12

1

@

2

1 2

1 2

RV91
10K_0402_5%

@

RV127
10K_0402_5%

DIS@

12

12

@

+3VS_VGA

12

12

RV146
10K_0402_5%

DIS@

DV4

@

1 2

RB751V-40_SOD323-2

SCS00006S00

12

RV92
10K_0402_5%

DIS@

12

RV133
10K_0402_5%

@

CV206

@

+1.8VS_VGA

RV108

@

4.99K_0402_1%

RV111

DIS@

4.75K_0402_1%

+1.8VS_VGA

RV114

S2G@

3.4K_0402_1%

RV107

S2G@

10K_0402_1%

RV105

@

1 2

2.2K_0402_5%

12

RV103

@

10K_0402_5%

+3VS_VGA

CV205

1

@

2

RV134

1 2

10U_0603_6.3V6-M

0.1U_0402_10V7-K
10K_0402_5%

CV208

1

2

@

1

@

2

CV209

1

@

2

Add Optional Bypass resistor

RV115 0_0402_5%

RV116 0_0402_5%

0.1U_0402_10V7-K

UV14

1

VCC(A)

2

1A

3

2A

5

DIR

74AVCH2T45GD_XSON8_3X2

+3VS_VGA

0.1U_0402_25V6-K

1 2

1 2

@

MLPS Recommend setting Value

PS_0 PS0[5..1] = 11001

PS_2

12

PS_2

CV210

0.082U_0402_50V7-K

12

1

@

2

12

PS_3

CV211

0.1U_0402_10V7-K

12

1

@

2

PS_3

Memory (GDDR3)

Samsung

Hynix

Micron

RV110

1 2

0_0402_5%

C

2

QV4

B

S TR TTC4116FU NPN SC-70-3

E

SB000010U00

3 1

@

+1.8VS_VGA

8

VCC(B)

7

RV96 33_0402_5%@

1B

6

RV97 33_0402_5%@

2B

4

GND

PS1[5..1] = 11000PS_1

PS2[5..1] = 11000

PS3[5..1] = 11xxx

RV114

PU 8.45K

1G

2G

PU 3.4K

1G

2G

PU 4.75K

1G

2G

PU 3.24K

@

CV207

@

0.1U_0402_10V7-K

1

2

1 2

1 2

H_THERMTRIP# <12>

RV112 = 8.45K ohm
RV113 = 2K ohm
CV213 = NC

RV106 = NC
RV109 = 4.75K ohm
CV212 = NC

RV108 = NC
RV111 = 4.75K ohm
CV210 = NC

RV114 =
RV107 =
CV211 = NC

RV107

PD 2K

PD 10K

PD 2KPU 4.53K

NC

PD 4.75KNC

PD 5.62K

SVI2_SVD

SVI2_SVD <76>

SVI2_SVCGPIO20_PWRCNTL_1

SVI2_SVC <76>

Strap PS_3[3..1]

001

110

010

111

000

101

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/07/01

2014/07/01

2014/07/01

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

1

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

21 81

21 81

21 81

1.0

1.0

1.0

1

1.5A

+1.5VS_VGA

A A

B B

C C

D D

CV22

1

DIS@

2

13mA

+1.8VS_VGA

25mA

+3VS_VGA

30mA

+1.8VS_VGA

.01U_0402_16V7-K

CV26

CV27

CV28

2.2U_0402_6.3V6-K

0.1U_0402_10V7-K

1

DIS@

2

2.2U_0402_6.3V6-K

1

1

DIS@

DIS@

2

2

CV53

DIS@

CV62

@

CV63

DIS@

CV29

CV23

2.2U_0402_6.3V6-K

1

DIS@

2

1U_0402_10V6-K

1

2

1U_0402_10V6-K

1

2

1U_0402_10V6-K

1

2

CV30

2.2U_0402_6.3V6-K

1

DIS@

DIS@

2

VDDC_SEN<76>

VDDC_RTN<76>

2.2U_0402_6.3V6-K

1

2

+1.8VS_VGA

+3VS_VGA

CV31

2

UV1E

PART 5 0F 9

MEM I/O

AC7

VDDR1_1

10U_0603_6.3V6-M

1

DIS@

2

AD11

VDDR1_2

AF7

VDDR1_3

AG10

VDDR1_4

AJ7

VDDR1_5

AK8

VDDR1_6

AL9

VDDR1_7

G11

VDDR1_8

G14

VDDR1_9

G17

VDDR1_10

G20

VDDR1_11

G23

VDDR1_12

G26

VDDR1_13

G29

VDDR1_14

H10

VDDR1_15

J7

VDDR1_16

J9

VDDR1_17

K11

VDDR1_18

K13

VDDR1_19

K8

VDDR1_20

L12

VDDR1_21

L16

VDDR1_22

L21

VDDR1_23

L23

VDDR1_24

L26

VDDR1_25

L7

VDDR1_26

M11

VDDR1_27

N11

VDDR1_28

P7

VDDR1_29

R11

VDDR1_30

U11

VDDR1_31

U7

VDDR1_32

Y11

VDDR1_33

Y7

VDDR1_34

LEVEL

TRANSLATION

AF26

VDD_CT_1

AF27

VDD_CT_2

AG26

VDD_CT_3

AG27

VDD_CT_4

I/O

AF23

VDDR3_1

AF24

VDDR3_2

AG23

VDDR3_3

AG24

VDDR3_4

DVP

AD12

VDDR4_1

AF11

VDDR4_2

AF12

VDDR4_3

AF13

VDDR4_4

AF15

VDDR4_5

AG11

VDDR4_6

AG13

VDDR4_7

AG15

VDDR4_8

VOLTAGE
SENESE

AF28

FB_VDDC

AG28

FB_VDDCI

AH29

FB_GND

216-0855000_A0_FCBGA962

NC_PCIE_VDDR_1
NC_PCIE_VDDR_2
NC_PCIE_VDDR_3
NC_PCIE_VDDR_4
NC_PCIE_VDDR_5
NC_PCIE_VDDR_6

NC_BIF_VDDC_1
NC_BIF_VDDC_2

PCIE_PVDD

PCIE

PCIE_VDDC_1
PCIE_VDDC_2
PCIE_VDDC_3
PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8

PCIE_VDDC_9
PCIE_VDDC_10
PCIE_VDDC_11
PCIE_VDDC_12

BIF_VDDC_1

BACO

BIF_VDDC_2

VDDC_1

CORE

VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26

VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37
VDDC_38
VDDC_39
VDDC_40
VDDC_41
VDDC_42
VDDC_43
VDDC_44
VDDC_45
VDDC_46
VDDC_47
VDDC_48
VDDC_49
VDDC_50
VDDC_51
VDDC_52
VDDC_53
VDDC_54
VDDC_55
VDDC_56

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4
VDDCI_5
VDDCI_6
VDDCI_7
VDDCI_8

VDDCI_9
VDDCI_10
VDDCI_11
VDDCI_12
VDDCI_13

CORE I/O

ISOLATED

VDDCI_14
VDDCI_15
VDDCI_16
VDDCI_17
VDDCI_18
VDDCI_19
VDDCI_20
VDDCI_21
VDDCI_22

AA31
AA32
AA33
AA34
W30
Y31
V28
W29
AB37

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

N27
T27

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18

AH22
AH27
AH28
M26
N24
R18
R21
R23
R26
T17
T20
T22
T24
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

3

TPV1
Test_Point_32MIL

1

CV32

CV39

CV54

CV33

10U_0603_6.3V6-M

1U_0402_10V6-K

1

1

DIS@

DIS@

2

2

CV41

CV40

2.2U_0402_6.3V6-K

1

DIS@

2

CV55

2.2U_0402_6.3V6-K

1

DIS@

2

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

1

1

DIS@

DIS@

2

2

CV56

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

1

1

DIS@

DIS@

2

2

CV34

DIS@

CV42

DIS@

CV57

DIS@

CV35

1U_0402_10V6-K

1

1

DIS@

2

2

CV43

2.2U_0402_6.3V6-K

1

1

DIS@

2

2

CV58

2.2U_0402_6.3V6-K

1

1

DIS@

2

2

4

100mA

+1.8VS_VGA

CV21

10U_0603_6.3V6-M

1

DIS@

2

CV36

1U_0402_10V6-K

1

DIS@

2

CV44

2.2U_0402_6.3V6-K

1

DIS@

2

CV59

2.2U_0402_6.3V6-K

1

@

2

CV25

CV24

1U_0402_10V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1

1

DIS@

DIS@

2

2

CV37

CV45

CV60

1U_0402_10V6-K

1

DIS@

2

2.2U_0402_6.3V6-K

1

DIS@

2

2.2U_0402_6.3V6-K

1

@

2

CV38

CV46

CV61

1A

+0.95VS_VGA

0.8A

CV47

+0.95VS_VGA

CV227

1

DIS@

2

CV50

CV49

CV48

10U_0603_6.3V6-M

1

DIS@

2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

1

DIS@

DIS@

2

2

CV51

10U_0603_6.3V6-M

1

DIS@

2

1U_0402_10V6-K

1

DIS@

2

2.2U_0402_6.3V6-K

1

DIS@

2

2.2U_0402_6.3V6-K

1

@

2

5

1U_0402_10V6-K

37A

+VGA_CORE

CV52

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

1

DIS@

@

2

2

37A

+VGA_CORE

CV64

CV65

CV66

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

DIS@

2

1U_0402_10V6-K

1

1

DIS@

DIS@

2

2

CV67

DIS@

CV68

CV69

CV70

0.1U_0402_10V7-K

1U_0402_10V6-K

1U_0402_10V6-K

1

1

DIS@

2

2

0.1U_0402_10V7-K

1

1

DIS@

DIS@

2

2

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

5

22 81

22 81

22 81

1.0

1.0

1.0

5

UV1G

AB39

E39
F34
F39
G33
G34
H31

D D

C C

B B

A A

H34
H39

J31

J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39

W31
W34

Y34
Y39

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33

F7
F9
G2
G6
H9
J2

J27

J6
J8

K14

K7
L11
L17

L2
L22
L24

L6
M17
M22
M24
N16
N18

N2
N21
N23
N26

N6
R15
R17

R2
R20
R22
R24
R27

R6
T11
T13
T16
T18
T21
T23
T26
U15
U17

U2
U20
U22
U24
U27

U6
V11
V16
V18
V21
V23
V26

W2

W6
Y15
Y17
Y20
Y22
Y24
Y27

5

PART 7 0F 9

GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210

GND

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175

216-0855000_A0_FCBGA962

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8

GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43

GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60

GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97

GND_44

VSS_MECH_1
VSS_MECH_2
VSS_MECH_3

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20

AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20

AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

AG22

A39
AW1
AW39

4

237mA

+1.8VS_VGA

4

CV71

10U_0603_6.3V6-M

1

@

2

RV17 150_0402_1%

CV72

1U_0402_10V6-K

1

@

2

DIS@

1 2

3

UV1F

PART 6 0F 9

DP_VDDR DP_VDDC

AN24

NC_DP_VDDR_1

AP24

NC_DP_VDDR_6

AP25

NC_DP_VDDR_7

AP26

NC_DP_VDDR_8

AU28

NC_DP_VDDR_10

AV29

NC_DP_VDDR_12

AP20

NC_DP_VDDR_2

AP21

NC_DP_VDDR_3

AP22

NC_DP_VDDR_4

AP23

NC_DP_VDDR_5

AU18

NC_DP_VDDR_9

AV19

NC_DP_VDDR_11

AH34

DP_VDDR_13

AJ34

DP_VDDR_14

AF34

DP_VDDR_15

AG34

DP_VDDR_16

AM37

DP_VDDR_17

AL38

DP_VDDR_18

AM32

DP_VDDR_19

CALIBRATION

AW28

DPAB_CALR

AW18

DPCD_CALR

AM39

DPEF_CALR

216-0855000_A0_FCBGA962

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

DP_VDDC_1
DP_VDDC_2
DP_VDDC_3
DP_VDDC_4
DP_VDDC_5
DP_VDDC_6
DP_VDDC_7
DP_VDDC_8
DP_VDDC_9

NC_DP_VDDC_1
NC_DP_VDDC_4
NC_DP_VDDC_2
NC_DP_VDDC_3

DP GND

DP_VSSR_1
DP_VSSR_2
DP_VSSR_3
DP_VSSR_4
DP_VSSR_5
DP_VSSR_6
DP_VSSR_7
DP_VSSR_8

DP_VSSR_9
DP_VSSR_10
DP_VSSR_11
DP_VSSR_12
DP_VSSR_13
DP_VSSR_14
DP_VSSR_15
DP_VSSR_16
DP_VSSR_17
DP_VSSR_18
DP_VSSR_19
DP_VSSR_20
DP_VSSR_21
DP_VSSR_22
DP_VSSR_23
DP_VSSR_24
DP_VSSR_25
DP_VSSR_26
DP_VSSR_27
DP_VSSR_28
DP_VSSR_29
DP_VSSR_30
DP_VSSR_31
DP_VSSR_32
DP_VSSR_33
DP_VSSR_34
DP_VSSR_35

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

AP31
AP32
AN33
AP33
AL33
AM33
AK33
AK34
AN31

AP13
AT13
AP14
AP15

AN27
AP27
AP28
AW24
AW26
AN29
AP29
AP30
AW30
AW32
AN17
AP16
AP17
AW14
AW16
AN19
AP18
AP19
AW20
AW22
AN34
AP39
AR39
AU37
AF39
AH39
AK39
AL34
AV27
AR28
AV17
AR18
AN38
AM35
AN32

Deciphered Date

Deciphered Date

Deciphered Date

2

280mA

+0.95VS_VGA

2014/07/01

2014/07/01

2014/07/01

1

UV1D

PART 4 0F 9

LVDS CONTROL

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

LVTMDP

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

216-0855000_A0_FCBGA962

Title

Title

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

AK27

VARY_BL

AJ27

DIGON

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35

TXOUT_U3P

AG36

TXOUT_U3N

AP34
AR34

AW37
AU35

AR37
AU39

AP35
AR35

AN36

TXOUT_L3P

AP37

TXOUT_L3N

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

1

23 81

23 81

23 81

1.0

1.0

1.0

1

2

3

4

5

FBA_MA[15..0] <25,26>

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9

MAA1_5/MAA_0
MAA1_6/MAA_1
MAA1_7/MAA_2

ADBIA0/ODTA0
ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B

MAA1_9/NC

FBA_BA[2..0] <25,26>

G24

FBA_MA0

J23

FBA_MA1

H24

FBA_MA2

J24

FBA_MA3

H26

FBA_MA4

J26

FBA_MA5

H21

FBA_MA6

G21

FBA_MA7

H19

FBA_MA8

H20

FBA_MA9

L13

FBA_MA10

G16

FBA_MA11

J16

FBA_MA12

H16

FBA_BA2

J17

FBA_BA0

H17

FBA_BA1

A32

FBA_DQM0

C32

FBA_DQM1

D23

FBA_DQM2

E22

FBA_DQM3

C14

FBA_DQM4

A14

FBA_DQM5

E10

FBA_DQM6

D9

FBA_DQM7

C34

FBA_DQS0

D29

FBA_DQS1

D25

FBA_DQS2

E20

FBA_DQS3

E16

FBA_DQS4

E12

FBA_DQS5

J10

FBA_DQS6

D7

FBA_DQS7

A34

FBA_DQS#0

E30

FBA_DQS#1

E26

FBA_DQS#2

C20

FBA_DQS#3

C16

FBA_DQS#4

C12

FBA_DQS#5

J11

FBA_DQS#6

F8

FBA_DQS#7

J21

FBA_ODTA0

G19

FBA_ODTA1

H27

FBA_CLKA0

G27

FBA_CLKA0#

J14

FBA_CLKA1

H14

FBA_CLKA1#

K23

FBA_RASA0#

K19

FBA_RASA1#

K20

FBA_CASA0#

K17

FBA_CASA1#

K24

FBA_CSA0#

K27

M13

FBA_CSA1#

K16

K21

FBA_CKEA0

J20

FBA_CKEA1

K26

FBA_WEA0#

L15

FBA_WEA1#

H23

FBA_MA13

J19

FBA_MA14

M21

FBA_MA15

M20

FBA_ODTA0 <25>
FBA_ODTA1 <26>

FBA_CLKA0 <25>
FBA_CLKA0# <25>

FBA_CLKA1 <26>
FBA_CLKA1# <26>

FBA_RASA0# <25>
FBA_RASA1# <26>

FBA_CASA0# <25>
FBA_CASA1# <26>

FBA_CSA0# <25>

FBA_CSA1# <26>

FBA_CKEA0 <25>
FBA_CKEA1 <26>

FBA_WEA0# <25>
FBA_WEA1# <26>

+1.5VS_VGA

12

12

+1.5VS_VGA

12

12

RV19

40.2_0402_1%

CHB@

RV21
100_0402_5%

CHB@

RV23

40.2_0402_1%

CHB@

RV25
100_0402_5%

CHB@

CV74

CV76

FBB_DQS[7..0]<27,28>

FBB_DQM[7..0]<27,28>

FBB_DQS#[7..0]<27,28>

FBB_D[0..63]<27,28>

UV1I

AA12

C5

DQB0_0

C3

DQB0_1

E3

DQB0_2

E1

DQB0_3

F1

DQB0_4

F3

DQB0_5

F5

DQB0_6

G4

DQB0_7

H5

DQB0_8

H6

DQB0_9

J4

DQB0_10

K6

DQB0_11

K5

DQB0_12

L4

DQB0_13

M6

DQB0_14

M1

DQB0_15

M3

DQB0_16

M5

DQB0_17

N4

DQB0_18

P6

DQB0_19

P5

DQB0_20

R4

DQB0_21

T6

DQB0_22

T1

DQB0_23

U4

DQB0_24

V6

DQB0_25

V1

DQB0_26

V3

DQB0_27

Y6

DQB0_28

Y1

DQB0_29

Y3

DQB0_30

Y5

DQB0_31

AA4

DQB1_0

AB6

DQB1_1

AB1

DQB1_2

AB3

DQB1_3

AD6

DQB1_4

AD1

DQB1_5

AD3

DQB1_6

AD5

DQB1_7

AF1

DQB1_8

AF3

DQB1_9

AF6

DQB1_10

AG4

DQB1_11

AH5

DQB1_12

AH6

DQB1_13

AJ4

DQB1_14

AK3

DQB1_15

AF8

DQB1_16

AF9

DQB1_17

AG8

DQB1_18

AG7

DQB1_19

AK9

DQB1_20

AL7

DQB1_21

AM8

DQB1_22

AM7

DQB1_23

AK1

DQB1_24

AL4

DQB1_25

AM6

DQB1_26

AM1

DQB1_27

AN4

DQB1_28

AP3

DQB1_29

AP1

DQB1_30

AP5

DQB1_31

Y12

MVREFDB
MVREFSB

FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34

1U_0402_10V6-K

1

CHB@

2

1U_0402_10V6-K

1

CHB@

2

FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

MVREFDB
MVREFSB

PART 9 0F 9

GDDR5/DDR3

MEMORY INTERFACE B

FBB_D[0..63]

WCKB0B_0

WCKB0B_1

WCKB1B_0

WCKB1B_1

DRAM_RST

FBA_DQS[7..0]<25,26>

FBA_DQM[7..0]<25,26>

FBA_DQS#[7..0]<25,26>

FBA_D[0..63]<25,26>

A A

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20

+1.5VS_VGA

12

12

+1.5VS_VGA

12

12

RV18

40.2_0402_1%

CHA@

RV20
100_0402_5%

CHA@

RV22

40.2_0402_1%

CHA@

RV24
100_0402_5%

CHA@

CV73

1U_0402_10V6-K

1

CHA@

2

CV75

1U_0402_10V6-K

1

CHA@

2

RV26 120_0402_1%CHA@

1 2

B B

C C

FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

MVREFDA
MVREFSA

AG12

AH12

C37
C35

A35

E34
G32
D33

F32

E32
D31

F30
C30

A30

F28
C28

A28

E28
D27

F26
C26

A26

F24
C24

A24

E24
C22

A22

F22
D21

A20

F20
D19

E18
C18

A18

F18
D17

A16

F16
D15

E14

F14
D13

F12

A12
D11

F10

A10
C10
G13
H13

J13
H11
G10

G8

K9

K10

G9

A8

C8

E8
A6

C6

E6
A5

L18

L20

L27
N12

M27

M12

UV1H

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MVREFDA
MVREFSA

NC_MEM_CALRN0
NC_MEM_CALRN1
NC_MEM_CALRN2

MEM_CALRP0

NC_MEM_CALRP1
NC_MEM_CALRP2

FBA_D[0..63]

PART 8 0F 9

GDDR5/DDR3

MEMORY INTERFACE A

MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12

WCKA0_0/DQMA0_0

WCKA0B_0/DQMA0_1

WCKA0_1/DQMA0_2

WCKA0B_1/DQMA0_3

WCKA1_0/DQMA1_0

WCKA1B_0/DQMA1_1

WCKA1_1/DQMA1_2

WCKA1B_1/DQMA1_3

EDCA0_0/QSA0_0
EDCA0_1/QSA0_1
EDCA0_2/QSA0_2
EDCA0_3/QSA0_3
EDCA1_0/QSA1_0
EDCA1_1/QSA1_1
EDCA1_2/QSA1_2
EDCA1_3/QSA1_3

DDBIA0_0/QSA0_0B
DDBIA0_1/QSA0_1B
DDBIA0_2/QSA0_2B
DDBIA0_3/QSA0_3B
DDBIA1_0/QSA1_0B
DDBIA1_1/QSA1_1B
DDBIA1_2/QSA1_2B
DDBIA1_3/QSA1_3B

MAA0_8/MAA_13
MAA1_8/MAA_14
MAA0_9/MAA_15

MAB0_0
MAB0_1
MAB0_2
MAB0_3
MAB0_4
MAB0_5
MAB0_6
MAB0_7
MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MAB1_7

WCKB0_0

WCKB0_1

WCKB1_0

WCKB1_1

EDCB0_0
EDCB0_1
EDCB0_2
EDCB0_3
EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DDBIB0_0
DDBIB0_1
DDBIB0_2
DDBIB0_3
DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3

ADBIB0
ADBIB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B
RASB1B

CASB0B
CASB1B

CSB0B_0
CSB0B_1

CSB1B_0
CSB1B_1

CKEB0
CKEB1

WEB0B
WEB1B

MAB0_8
MAB1_8
MAB0_9
MAB1_9

FBB_MA[15..0] <27,28>

FBB_BA[2..0] <27,28>

P8

FBB_MA0

T9

FBB_MA1

P9

FBB_MA2

N7

FBB_MA3

N8

FBB_MA4

N9

FBB_MA5

U9

FBB_MA6

U8

FBB_MA7

Y9

FBB_MA8

W9

FBB_MA9

AC8

FBB_MA10

AC9

FBB_MA11

AA7

FBB_MA12

AA8

FBB_BA2

Y8

FBB_BA0

AA9

FBB_BA1

H3

FBB_DQM0

H1

FBB_DQM1

T3

FBB_DQM2

T5

FBB_DQM3

AE4

FBB_DQM4

AF5

FBB_DQM5

AK6

FBB_DQM6

AK5

FBB_DQM7

F6

FBB_DQS0

K3

FBB_DQS1

P3

FBB_DQS2

V5

FBB_DQS3

AB5

FBB_DQS4

AH1

FBB_DQS5

AJ9

FBB_DQS6

AM5

FBB_DQS7

G7

FBB_DQS#0

K1

FBB_DQS#1

P1

FBB_DQS#2

W4

FBB_DQS#3

AC4

FBB_DQS#4

AH3

FBB_DQS#5

AJ8

FBB_DQS#6

AM3

FBB_DQS#7

T7

FBB_ODTA0

W7

FBB_ODTA1

L9

FBB_CLKA0

L8

FBB_CLKA0#

AD8

FBB_CLKA1

AD7

FBB_CLKA1#

T10

FBB_RASA0#

Y10

FBB_RASA1#

W10

FBB_CASA0#

AA10

FBB_CASA1#

P10

FBB_CSA0#

L10

AD10

FBB_CSA1#

AC10

U10

FBB_CKEA0

AA11

FBB_CKEA1

N10

FBB_WEA0#

AB11

FBB_WEA1#

T8

FBB_MA13

W8

FBB_MA14

U12

FBB_MA15

V12

AH11

DRAM_RST

FBB_ODTA0 <27>
FBB_ODTA1 <28>

FBB_CLKA0 <27>
FBB_CLKA0# <27>

FBB_CLKA1 <28>
FBB_CLKA1# <28>

FBB_RASA0# <27>
FBB_RASA1# <28>

FBB_CASA0# <27>
FBB_CASA1# <28>

FBB_CSA0# <27>

FBB_CSA1# <28>

FBB_CKEA0 <27>
FBB_CKEA1 <28>

FBB_WEA0# <27>
FBB_WEA1# <28>

216-0855000_A0_FCBGA962

D D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

216-0855000_A0_FCBGA962

FBA_RST#<25,26,27,28>

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

FBA_RST#

RV28

RV27

CHB@

1 2

49.9_0402_1%

CV77
120P_0402_50V8-J

CHB@

Title

Title

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

CHB@

1 2

10_0402_5%

1

RV29

5.1K_0402_5%

CHB@

2

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

DRAM_RST

12

1

CV78
68P_0402_50V8-J

@

2

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

5

24 81

24 81

24 81

1.0

1.0

1.0

1

2

3

4

5

Memory Partition A - Lower 32 bits

UV3

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14

FBA_BA0
FBA_BA1
FBA_BA2

FBA_CLKA0
FBA_CLKA0#
FBA_CKEA0

FBA_ODTA0
FBA_CSA0#
FBA_RASA0#
FBA_CASA0#
FBA_WEA0#

FBA_DQS3
FBA_DQS0

FBA_DQM3
FBA_DQM0

FBA_DQS#3
FBA_DQS#0

FBA_MA15

CV87

1U_0402_10V6-K

1

CHA@

2

CV99

0.1U_0402_10V7-K

1

CHA@

2

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC1

L1

NC2

J9

NC3

L9

NC4

M7

NC5

K4W4G1646D-BC1A_FBGA96

CV88

1U_0402_10V6-K

1U_0402_10V6-K

1

CHA@

2

CV100

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1

CHA@

2

+FBA_VREFC0

A A

B B

+FBA_VREFD0

FBA_CLKA0<24>
FBA_CLKA0#<24>
FBA_CKEA0<24>

FBA_ODTA0<24>
FBA_CSA0#<24>
FBA_RASA0#<24>
FBA_CASA0#<24>
FBA_WEA0#<24>

Vram Swap

1

2

10U_0603_6.3V6-M

FBA_RST#

12

12

RV37
243_0402_1%

CHA@

UV6 SIDE UV7 SIDE

CV84

CHA@

CV96

CHA@

CV86

CV85

1U_0402_10V6-K

1U_0402_10V6-K

1

2

1

2

1

1

CHA@

CHA@

2

2

UV6 SIDE UV7 SIDE

CV97

CV98

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1

1

CHA@

CHA@

2

2

FBA_RST#<24,26,27,28>

RV36
10K_0402_5%

@

C C

+1.5VS_VGA +1.5VS_VGA

CV83

CHA@

+1.5VS_VGA +1.5VS_VGA

96-BALL
SDRAM DDR3

S2G@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9



FBA_D29
FBA_D24
FBA_D28
FBA_D27
FBA_D25
FBA_D26
FBA_D31
FBA_D30

FBA_D3
FBA_D6
FBA_D1
FBA_D4
FBA_D2
FBA_D7
FBA_D0
FBA_D5

+1.5VS_VGA





CV89

CV90

10U_0603_6.3V6-M

1

CHA@

2

CV101

CV91

CV92

1U_0402_10V6-K

1U_0402_10V6-K

CHA@

CV102

CHA@

1U_0402_10V6-K

1

1

CHA@

2

2

CV103

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1

1

CHA@

2

2

1

CHA@

2

0.1U_0402_10V7-K

1

CHA@

2

Change all VRAM footprint to MT41K256M16HA107_FBGA_96P-A39P

CV93

CHA@

CV104

CHA@

UV4

+FBA_VREFD0
+FBA_VREFC0

FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA8
FBA_MA9
FBA_MA10
FBA_MA11
FBA_MA12
FBA_MA13
FBA_MA14

FBA_BA0
FBA_BA1
FBA_BA2

FBA_CLKA0
FBA_CLKA0#
FBA_CKEA0

FBA_ODTA0
FBA_CSA0#
FBA_RASA0#
FBA_CASA0#
FBA_WEA0#

FBA_DQS2
FBA_DQS1

FBA_DQM2
FBA_DQM1

FBA_DQS#2
FBA_DQS#1

FBA_RST#

12

RV38
243_0402_1%

CHA@

CV94

1U_0402_10V6-K

1U_0402_10V6-K

1

1

CHA@

2

2

CV105

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1

1

CHA@

2

2

FBA_MA15

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC1

L1

NC2

J9

NC3

L9

NC4

M7

NC5

K4W4G1646D-BC1A_FBGA96

96-BALL
SDRAM DDR3

S2G@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

E3
F7
F2
F8
H3
H8
G2
H7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9



FBA_D18
FBA_D23
FBA_D17
FBA_D22
FBA_D16
FBA_D21
FBA_D19
FBA_D20

FBA_D13
FBA_D10
FBA_D15
FBA_D9
FBA_D14
FBA_D8
FBA_D12
FBA_D11

+1.5VS_VGA





FBA_MA[15..0] <24,26>

FBA_BA[2..0] <24,26>

FBA_DQS[7..0] <24,26>

FBA_DQM[7..0] <24,26>

FBA_DQS#[7..0] <24,26>

FBA_D[0..63] <24,26>

+1.5VS_VGA

12

RV30

4.99K_0402_1%

CHA@

12

RV32

4.99K_0402_1%

CHA@

FBA_CLKA0

FBA_CLKA0#

CV79

1

CHA@

2

RV41

40.2_0402_1%

CHA@

RV42

40.2_0402_1%

CHA@

+FBA_VREFC0

0.1U_0402_10V7-K

RV31

4.99K_0402_1%

CHA@

RV33

4.99K_0402_1%

CHA@

12

CV95

1 2

.01U_0402_16V7-K

12

+1.5VS_VGA

12

12

CHA@

CV80

CHA@

1

2

+FBA_VREFD0

0.1U_0402_10V7-K

D D

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

XXXX

XXXX

XXXX

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Thursday, November 06, 2014

Thursday, November 06, 2014

Thursday, November 06, 2014

Date: Sheet of

Date: Sheet of

Date: Sheet of

AITE1_NM-A221

AITE1_NM-A221

AITE1_NM-A221

5

25 81

25 81

25 81

1.0

1.0

1.0