Lenovo ThinkPad E470 Schematic

A

1 1

B

C

D

E

LCFC Confidential

2 2

KENOBI NM-A821 Rev2.0 Schematic

Intel KabyLake Processor with DDR4 + PCH-LP

NVIDA N16V-GMR GDDR3 2GB

3 3

2016-08-24 Rev2.0

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

C

2015/10/5

LC Future Center Secret Data

Deciphered Date

D

2016/12/31

Title

COVER PAGE

Size Document Number Rev

Custom

Thursday, August 25, 2016

Date: Sheet of

Thursday, August 25, 2016

KENOBI

E

1 82

2.0

A

www.vinaﬁx.com

B

C

D

E

Kenobi KBL U Block Diagram

GPU

VRAM

1 1

GDDR3

Page 31~32

DDR5

DIS only (SWG)

DDR4 2133/2400 Mhz SODIMM A

DDR4 2133/2400 Mhz SODIMM B

Page 25~30

NVIDIA

N16V-GMR1-S-A2 N16S-GTR-S-A2

Page22

Page23

DDR4 2133/2400MHz Channel A

DDR4 2133/2400MHz Channel B

PCIE x 4

(PCIE Lane 1~4)

Intel CPU

Kabylake U 15W (UM A& DIS) Kabylake PCH-LP

10 USB 2.0/1.1 Ports

6 USB 3.0 Ports

3 SATA Ports 12 PCIE Ports HD Audio

LPC I/F

ACPI 3.0

Touch Panel (Optional)

15" LCD FHD/HD

2 2

DMIC_DATA DMIC_CLK

2D Camera (Digital MIC)

IR Camera (Optional)

Page37

EDP x 2

USB 2.0 x 1

(Port 5)

USB 2.0 x 1

(Port 7)

USB 2.0 x 1

(Port 8)

PCIe x 1

(PCIE Lane 9)

USB 2.0 x 1

(Port 6)

SATA x 1

USB 2.0 x 1

(Port 9)

PCIe x 2

(PCIE Lane11/12)

NGFF Card WLAN

Page 48

802.11 a/b/g/n BT V4.0 combo

HDD

Page42

Finger Print

Page61

WORLD FAIR

VAL1167

M2 Slot for SSD

Page42

Card Reader

Page49

Bayhub

OZ621FJ1LN

Right- Fr ont

JUSB4 (USB3.0)

Page44

Right - Back

3 3

JUSB3 (USB3.0)

Page44

Reserve

PCIe x 1

(PCIE Lane 5)

USB 3.0 x 1

(Port 4)

USB 2.0 x 1

(Port 4)

USB 3.0 x 1

(Port 3)

USB 2.0 x 1

(Port 3)

AOU

JUSB2 (USB2.0)

Page45

RJ45 Conn.

Page47

Combol Jack

Page53

4 4

Stereo Speaker

Page52

MIC IN/GND

HP R/L

(2CH 2W/4ohm)

USB charger (AOU)

Page44

TI

TPS2546RTER

LAN 10/100/1000

Page46

Realtek

R8111GUS

HDA Codec

Page51

CONEXANT

CX11852-11Z

USB 3.0 x 1

(Port 2)

USB 2.0 x 1

(Port 2)

PCIe x 1

(PCIE Lane 10)

HDA

BGA1356

40mm*24mm

Page 5~20

DDI1

DDI2

USB 3.0 x 1

(Port 1)

USB 2.0 x 1

(Port 1)

LPC BUS

SPI BUS

ITE

IT8586EX

Mirror function

Flash ROM 4M/8M

Page21

Infineon

SLB9670VQ1.2

HDMI v1.4

Switch MUX

Parade

PS8743

SPI BUS

TPM 1.2

Page58

Page36

USB Type-C PD

I2C

Page54

I2C

Fintek

LIS3DSHTR

Cypress

CYPD3125

Page55

EC

Page57

FAN

Page61 Page60 Page59

Int. KB

I2CInt. K/B Matrix

G-sensor

Power Control

Type C Conn.

Page55

SMBus

PS2

Thermal Sensor

Page62

Fintek

F75303M

Click Pad Track Point

Page63 Page63

A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

D

2015/09/01

LC Future Center Secret Data

Deciphered Date

2016/12/31

Title

BLOCK DIAGRAM

Size

Document Number Rev

A1

Thursday, August 25, 2016

Date: Sheet of

E

KENOBI

2 82

2.0

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

S5 S4/AC Only

( O --> Means ON , X --> Means OFF )

+3VALW

B+

+3VL

O

+5VALW

+1VALW

+1.8VALW

+2.5V

+1.2V

+VCC_STG

OOO

OOOO

O

X

+5VS

+3VS

+VCC_CORE

+VCC_IO

+VCC_SA

+VCC_ST

+VGA_CORE

+3VS_VGA

+1.5VS_VGA

+3VS_AON

+1VS_VGA

+0.6VS

X

SMBUS Control Table

SOURCE

IT8580FEC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK3

EC_SMB_DA3

PCH_SMB_DATA

PCH_SML1CLK PCH_SML1DAT

+3VL

IT8580F

+3VL

IT8580F

+3VS

PCHPCH_SMB_CLK

+3V_PCH

PCH

+3V_PCH

+3VS_VGA

Main

BATT

VGA

(Charger)

X

+3VALW

X XX X

V

X

XX X

SODIMM

V

XXXXX

X

V

+3VS

XXXXXXX

WLAN WiMAX

X

Thermal Sensor

V

+3VS

XX

PCH

V

+3V_PCH

CP Module

X

V

+5VS

LAN PHY

X

X V

X

G sensor

+3VS_GS

BOM Structure Table

BOM Structure

NOTE

X

USB Type-C

X

V

+3VPD_VDD

X

PCB@ For PCB load BOM

S5 S4 Battery only

O

XX

X

XDP@ Debug port

UMA@

UMA SKU ID

S5 S4 AC & Battery don't exist

XX

X

DIS@

SSD@ SSD setting

Optimus SKU ID

Finger printer settingFRP@

For USB Type-C functionTYPEC@

STATE

Full ON

S1(Power On Suspend)

3 3

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_A# SLP_S3# SLP_S4# SLP_S5# EC_ON2 EC_ON SUSP#

HIGH HIGH HIGH HIGH

HIGH

LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

OFF

OFFLOW LOW LOW LOW

SYSON

HIGH

LOW

ME@

EMC_2D@ For EMC function

EMC_NS@ For EMC function

RF_NS@ For RF function

S2G@ For VRAM Strap

CHA@ For VRAMA function

ME Connector

For EMC functionEMC@

CHB@ For VRAMB function

USB2 Port

DevicePort

USB3 Port

PCIE Port

DevicePort

Port Device

SATA Port

RANKA@ GPU DDR5 Setting

DevicePort

X76@ GPU VRAM Setting

3DCCD@ 3D Camera Setting 1 2 3 4 5

JUSB2 JUSB3 JUSB4 JUSB4 Touch Panel

TYPE-C

1 TYPE-CJUSB1 2 3

JUSB1 JUSB2 JUSB3

4

6 BT 7

4 4

8 9

CMOS IR CAMERA FP/Smart

1 2 3 4 5 6 7 8 9 10 11 12

A

B

GPU GPU GPU GPU

CardReader

X X

X

WLAN LAN

M.2 SSD M.2 SSD

1 2 3 4

HDD

X X X

VGA@ VGA Setting

MUX@ MUX Setting

ODD@ ODD Setting

TPM@

Trusted Platform Module (TPM)

MIRROR@ For mirror function

NGC6@

For VGA Non GC6 function

GC6@ For VGA GC6 function

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2015/10/5

LC Future Center Secret Data

Deciphered Date

D

2016/12/31

Title

NOTE LIST

Size Document Number Rev

Custom

Thursday, August 25, 2016

Date: Sheet of

Thursday, August 25, 2016

KENOBI

E

3 82

2.0

5

[KENOBI PWR Sequence_SKL-U_DDR4_Non-Deep Sx]

4

3

2

1

D D

C C

AC_IN

B+

+3VLP/+VL

MAINPWON_EC

EC_ON

+3VALW

3V5V_ON

+5VALW

EC_ON2

+1VALW/+1.8VALW

ON/OFFBTN#

PBTN_OUT#

EC_RSMRST#

SUSPWRDNACK

AC_PRESENT

170mS

9mS

200uS

PM_SLP_S5#

moniter AC_IN (51_ON)

Min:50nS

15mS

Min:60nS

20mS

415mS

95~100mS

Moniter ON/OFFBTN# rising edge

20ms

Montier PBTN_OUT# falling edge.

[AC Mode]

[DC Mode]

BATT+

AC_PRESENT

B+

+3VLP/+VL

ON/OFFBTN#

EN_5V/EN_3V

+5VALW/+3VALW

+1VALW/+1.8VALW

EC_RSMRST#

SUSPWRDNACK

PBTN_OUT#

T=10ms

moniter EN_3VPCH_PWR_EN

Moniter ON/OFFBTN#

T=10ms

Moniter ON/OFFBTN# and EN_3/5V both of risgin edge

T=110ms

20ms

Moniter ON/OFFBTN# rising edge

PM_SLP_S4#

PM_SLP_S3#

SYSON

+1.2V

DDR_PG_CTRL

immediately, After PM_SLP_S4# falling edge

+0.6VS

SUSP# After PM_SLP_S3# moniter SYSON ri sing edge.

T=20ms

immediately, After PM_SLP_S3# falling edge

+5VS

+3VS

+1.5VS

B B

VCCST_PG_EC (ALL_SYS_PWRGD,non CPU code VR)

VR_ON

+VCC_CORE

T=20ms

After SUSP# risign edge

immediately, VCCST_PG_PWR & VCCST_PG_EC risign edge

Vboot

immediately, After SUSP# falling edge

VGATE

T=10ms

After VCCST_PG_EC risi ng edgePCH_PWROK

immediately, After SUSP# falling edge

H_CPUPWRGD_R

SYS_PWROK

After VCCST_PG_EC assertion

immediately, After SUSP# falling edge

T=99ms

PLT_RST#

After CPUPWRGD/PCH_PWRGD/SYS_PWROK assertion

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND C ONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE C ENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE C ENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE C ENTER.

2

2015/10/5

LC Future Center Secret Data

Deciphered Date

2016/12/31

Title

Power Sequence

Size

Document Number Rev

D

Thursday, August 25, 2016

Date: Sheet of

1

KENOBI

4 82

2.0

5

4

3

2

1

D D

UC1A

PCH_HDMI_TX2-[36] PCH_HDMI_TX2+[36]

HDMI

USB TYPE C

+VCC_IO

C C

[SKL PDG]EDP_RCOM P Pull up to VCCIO via 24.9 ohm resistor

[SKL PDG]EDP_RCOM P

1. Trace width=20 mils, Spacing=25mil, Max length=100mils

2. RC1 close to MCP

PCH_HDMI_TX1-[36] PCH_HDMI_TX1+[36] PCH_HDMI_TX0-[36] PCH_HDMI_TX0+[36] PCH_HDMI_TXC-[36] PCH_HDMI_TXC+[36]

DDI2_MUX_TX0-[55] DDI2_MUX_TX0+[55] DDI2_MUX_TX1-[55] DDI2_MUX_TX1+[55] DDI2_MUX_TX2-[55] DDI2_MUX_TX2+[55] DDI2_MUX_TX3-[55] DDI2_MUX_TX3+[55]

HDMI_CLK[36] HDMI_DAT[36]

1 2

RC1 24.9_0402_1%

PCH_HDMI_TX2PCH_HDMI_TX2+ PCH_HDMI_TX1PCH_HDMI_TX1+ PCH_HDMI_TX0PCH_HDMI_TX0+ PCH_HDMI_TXCPCH_HDMI_TXC+

DDI2_MUX_TX0DDI2_MUX_TX0+ DDI2_MUX_TX1DDI2_MUX_TX1+ DDI2_MUX_TX2DDI2_MUX_TX2+ DDI2_MUX_TX3DDI2_MUX_TX3+

HDMI_CLK HDMI_DAT

PCH_MUX_CLK PCH_MUX_DAT

EDP_COMP

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

REV = 1

@

SKL_U LT

DDI

DISPLAY SIDEBANDS

EDP

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

??1 OF 20

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+

CPU_EDP_AUX# CPU_EDP_AUX

DDI2_MUX_AUX# DDI2_MUX_AUX

HDMI_HPD PCH_MUX_HPD

CPU_EDP_HPD

ENBKL PCH_EDP_PWM

PCH_ENVDD

CPU_EDP_TX0- [37] CPU_EDP_TX0+ [37] CPU_EDP_TX1- [37] CPU_EDP_TX1+ [37]

CPU_EDP_AUX# [37] CPU_EDP_AUX [37]

DDI2_MUX_AUX# [55] DDI2_MUX_AUX [55]

HDMI_HPD [36] PCH_MUX_HPD [54,55]

CPU_EDP_HPD [37]

ENBKL [57] PCH_EDP_PWM [37] PCH_ENVDD [37]

EDP

DDPB_CTRLDATA, DDPC_CTRLDATA Internal PD 20K

1 2

RC2 100K_0402_5%

RC3 100K_0402_5%

1 2

RC5 100K_0402_5%

1 2

TYPEC_NS@

+3VS

1 2

RC4 2.2K_0402_5%@

1 2

RC6 2.2K_0402_5%

1 2

RC7 3.3K_0402_5%

RC8 3.3K_0402_5%

1 2

PCH_MUX_CLK

PCH_MUX_DAT

HDMI_CLK

HDMI_DAT

ENBKL

CPU_EDP_HPD

[SKL PDG]EDP_HPD Pull down to ground via 100k ohm resistor

PCH_MUX_HPD

B B

A A

5

20160218 Staff RC7/RC8 for HDMI detect issue

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

20160824 Change RC5 from @ to TYPEC_NS@ (Only for Non Type-C SKU)

LC Future Center Secret Data

Deciphered Date

2015/09/01

Deciphered Date

2

2016/12/31

Title

KBL(1/16):DDI/EDP

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

5 82

1

5 82

2.0

5

4

3

2

1

D D

H_PECI[57] VR_HOT#[57,67,70]

TC30

[SKL PDG]If THERMTRIP# goes active, the CPU is indicating an overheat condition, and the PCH will immediately transition to an S5 state. CPU_GP can be used from external sensors for the thermal management.

EC_WAKE#[57]

C C

[SKL PDG]PROC_OPI_RCOMP: Signal should be pulled down to ground wit h a resistance of 50 ohm

∮

1 %.

[SKL PDG]PCH_ OPI_RCOMP: Signal should be pulled down t o ground with a resistance of 50 ohm

∮

1 %.

[SKL PDG]On Package Interface Compensation (OPI) Guidelines

Should be referenced to VSS plane only. VSS reference planes must be continuous Require low DC resistance routing <0.2 ohm Avoid routing next to clock pins or noisy signals.

+VCC_STG

12

RC11 1K_0402_5%

H_PECI VR_HOT#

H_THERMTRIP#

1

EC_WAKE# EC_WAKE#_L

1 2

RC13 499_0402_1% RC12 0_0402_5%@

1 2

RC18 0_0402_5%

@

RC21 49.9_0402_1%

1 2 1 2

RC23 49.9_0402_1% RC24 49.9_0402_1%

1 2 1 2

RC25 49.9_0402_1%

TC1

TC2 TC3 TC4 TC5

+VCC_ST

12

1

1 1 1 1

PROC_POPIRCO MP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

RC213 1K_0402_5%

@

VR_HOT#_R THRMTRIP#

XDP_BPM#1 XDP_BPM#2 XDP_BPM#3

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U_BGA1356

REV = 1

@

SKL_U LT

CPU MISC

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

?? 4 OF 20

XDP_TCLK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TR ST# PCH_JTAGX

THRMTRIP#

XDP_TDI

XDP_TMSXDP_BPM#0

PCH_JTAG_TDI

PCH_JTAG_TMS

PCH_JTAG_TDO

XDP_TDO

PCH_JTAGX

20160525 Change RC19/RC20 to100 ohm for PROC_TDO termination

XDP_TCLK

XDP_TRST#

PCH_JTAG_TCK

RC10 1K_0402_1%

RC14 51_0402_5%@

RC15 51_0402_5%@

RC16 51_0402_5%@

RC17 51_0402_5%@

RC19 100_0402_5%

RC20 100_0402_5%@

RC22 1K_0402_5%@

20160119 Unmount RC16,RC17,RC20

RC26 51_0402_5%

RC27 51_0402_5%@

RC28 51_0402_5%@

12

1 2

+VCC_ST

+VCC_STG

[SKL PDG]1 K pull- up to VCCST

Termination option

XDP_TCLK

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TRST#

B B

A A

1 2

RC29 0_0402_5%DCI@

RC30 0_0402_5%DCI@

1 2

RC31 0_0402_5%DCI@

1 2

RC32 0_0402_5%DCI@

1 2

RC33 0_0402_5%DCI@

Close to UC1

PCH_JTAGX

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TR ST#

XDP_TCLK

PROC_TCK Termination:

51 ohm +/- 5% pull down to GNG (Ground) Placed to within 200ps (1100 mil) or PROC_TCK pin

PCH_JTAG_TDO

PCH_JTAG_TDO Termination:

51ohm +/- 5% pull up to VccSTG or equivalent. Placed to within 200ps (1100 mil) or PCH_JTAG_TDO pin

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(2/16):MISC/JTAG

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

6 82

1

6 82

2.0

5

D D

4

3

2

1

DDR_A_MA0

DDR_A_D[63..0][22]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21

C C

B B

DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

REV = 1 @

SKL_U LT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

?

2 OF 20

DDR_A_DDRCLK0_1866M#

AU53

DDR_A_DDRCLK0_1866M

AT53

DDR_A_DDRCLK1_1866M#

AU55

DDR_A_DDRCLK1_1866M

AT55

DDR_A_CKE0

BA56

DDR_A_CKE1

BB56 AW56 AY56

DDR_A_CS0#

AU45

DDR_A_CS1#

AU43

DDR_A_ODT0

AT45

DDR_A_ODT1

AT43

DDR_A_MA5

BA51

DDR_A_MA9

BB54

DDR_A_MA6

BA52

DDR_A_MA8

AY52

DDR_A_MA7

AW52

DDR_A_BG0

AY55

DDR_A_MA12

AW54

DDR_A_MA11

BA54

DDR_A_ACT_N

BA55

DDR_A_BG1

AY54

DDR_A_MA13

AU46

DDR_A_MA15

AU48

DDR_A_MA14

AT46

DDR_A_MA16

AU50

DDR_A_BA0

AU52

DDR_A_MA2

AY51

DDR_A_BA1

AT48

?

DDR_A_MA10

AT50

DDR_A_MA1

BB50

DDR_A_MA0

AY50

DDR_A_MA3

BA50

DDR_A_MA4

BB52

DDR_A_DQS#0

AM70

DDR_A_DQS0

AM69

DDR_A_DQS#1

AT69

DDR_A_DQS1

AT70

DDR_A_DQS#2

BA64

DDR_A_DQS2

AY64

DDR_A_DQS#3

AY60

DDR_A_DQS3

BA60

DDR_A_DQS#4

BA38

DDR_A_DQS4

AY38

DDR_A_DQS#5

AY34

DDR_A_DQS5

BA34

DDR_A_DQS#6

BA30

DDR_A_DQS6

AY30

DDR_A_DQS#7

AY26

DDR_A_DQS7

BA26

DDR_A_ALERT_N

AW50

DDR_A_PARITY

AT52

DDR4_VREF_CA_CPU _A

AY67

DDR4_VREF_DQ_CP U_A

AY68

DDR4_VREF_DQ_CP U_B

BA67

DDR_PG_CTRL

AW67

DDR_A_DDRCLK0_1866M# [22] DDR_A_DDRCLK0_1866M [22] DDR_A_DDRCLK1_1866M# [22] DDR_A_DDRCLK1_1866M [22]

DDR_A_CKE0 [22] DDR_A_CKE1 [22]

DDR_A_CS0# [22] DDR_A_CS1# [22] DDR_A_ODT0 [22] DDR_A_ODT1 [22]

DDR_A_BG0 [22]

DDR_A_ACT_N [22] DDR_A_BG1 [22]

DDR_A_BA0 [22]

DDR_A_BA1 [22]

DDR_A_ALERT_N [22] DDR_A_PARITY [22]

DDR4_VREF_CA_CPU _A [22]

TC31

1

DDR4_VREF_DQ_CP U_B [23]

DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA16

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

+1.2V

+3VALW

+3VS

DDR_A_MA[0..16] [22]

DDR_A_DQS#[0..7] [22]

DDR_A_DQS[0..7] [22]

UC2

1

DDR_PG_CTRL

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

NC1

2

A

3

GND

74AUP1G07GF_ SOT891-6_1X1

Vcc

NC2

Y

2016/12/31

6

5

4

RC34 100K_0402_5%

1 2

1

CC1

0.1U_0402_10V7-K

2

Title

KBL(3/16):DDR4 CH.A

Size Document Number Rev

Custom

Date: Sheet of

RC214 100K_0402_5%

@

1 2

SM_PG_CTRL [69]

20160118 Reserve RC214 for leakage issue

KENOBI

Thursday, August 25, 2016

1

7 82

2.0

5

D D

4

3

2

1

DDR_B_D[0..63][23]

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18

C C

B B

DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U_BGA1356

REV = 1 @

SKL_U LT

DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0]

DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

3 OF 20

DDR_B_MA0 DDR_B_MA1

DDR_B_DDRCLK0_1866M#

AN45

DDR_B_DDRCLK1_1866M#

AN46

DDR_B_DDRCLK0_1866M

AP45

DDR_B_DDRCLK1_1866M

AP46

DDR_B_CKE0

AN56

DDR_B_CKE1

AP55 AN55 AP53

DDR_B_CS0#

BB42

DDR_B_CS1#

AY42

DDR_B_ODT0

BA42

DDR_B_ODT1

AW42

DDR_B_MA5

AY48

DDR_B_MA9

AP50

DDR_B_MA6

BA48

DDR_B_MA8

BB48

DDR_B_MA7

AP48

DDR_B_BG0

AP52

DDR_B_MA12

AN50

DDR_B_MA11

AN48

DDR_B_ACT_N

AN53

DDR_B_BG1

AN52

DDR_B_MA13

BA43

DDR_B_MA15

AY43

DDR_B_MA14

AY44

DDR_B_MA16

AW44

DDR_B_BA0

BB44

?

DDR_B_MA2

AY47

DDR_B_BA1

BA44

DDR_B_MA10

AW46

DDR_B_MA1

AY46

DDR_B_MA0

BA46

DDR_B_MA3

BB46

DDR_B_MA4

BA47

DDR_B_DQS#0

AH66

DDR_B_DQS0

AH65

DDR_B_DQS#1

AG69

DDR_B_DQS1

AG70

DDR_B_DQS#2

AR66

DDR_B_DQS2

AR65

DDR_B_DQS#3

AR61

DDR_B_DQS3

AR60

DDR_B_DQS#4

AT38

DDR_B_DQS4

AR38

DDR_B_DQS#5

AT32

DDR_B_DQS5

AR32

DDR_B_DQS#6

AR25

DDR_B_DQS6

AR27

DDR_B_DQS#7

AR22

DDR_B_DQS7

AR21

DDR_B_ALERT_N

AN43

DDR_B_PARITY

AP43

DDR4_DRAMRST_N DDR4_DRAMRST_N

AT13

SM_RCOMP0

AR18

SM_RCOMP1

AT18

SM_RCOMP2

AU18

[KBL PD G] for DDR4 COM PENSATION DDR_RCOM P[0] Pull down 121 ohm resistor DDR_RCOM P[1] Pull down 80.6 ohm resistor DDR_RCOM P[2] Pull down 100 ohm resistor

DDR_B_DDRCLK0_1866M# [23] DDR_B_DDRCLK1_1866M# [23] DDR_B_DDRCLK0_1866M [23] DDR_B_DDRCLK1_1866M [23]

DDR_B_CKE0 [23] DDR_B_CKE1 [23]

DDR_B_CS0# [23] DDR_B_CS1# [23] DDR_B_ODT0 [23] DDR_B_ODT1 [23]

DDR_B_BG0 [23]

DDR_B_ACT_N [23] DDR_B_BG1 [23]

DDR_B_BA0 [23]

DDR_B_BA1 [23]

DDR_B_ALERT_N [23] DDR_B_PARITY [23]

RC36 121_0402_1%

1 2 1 2

RC38 80.6_0402_1% RC39 100_0402_1%

1 2

DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA16

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

+1.2V

RC35 470_0402_5%

1 2

RC37 0_0402_5%

@

DDR_B_MA[0..16] [ 23]

DDR_B_DQS#[0..7] [23]

DDR_B_DQS[0..7] [23]

DDR4_DRAMRST# [22,23]

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(4/16):DDR4 CH.B

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

8 82

1

8 82

2.0

5

D D

[KBL PDG]Manufacturing Mode Jumper

1. If strap is sampled low, the security measures defined in the Flash Descriptor will be in effect (default)

2. If sampled high, the Flash Descriptor Security will be overridden.

4

3

20160408

1.Unstaff RC188 and Staff RC211 with 100K resistor

2

1

PCH_HDA_RST#[51] PCH_HDA_BCLK[51] PCH_HDA_SDOUT[51] PCH_HDA_SYNC[51]

10P_0402_50V8-J EMC _NS@

PCH_HDA_RST# HDA_RST#

PCH_HDA_SDOUT PCH_HDA_SYNC HDA_SYNC

1

CC185

ME_FLASH[57]

2

Place RC183.184.185.186 close together

Note:

C C

SPKR (PC_BEEP) has an integrated weak pull-down resistor (20 K ohm nominal) to disable Top-Block Sway by default.

To enable Top-Block Swap, this signal should be pulled up to V3.3S through a 1k to 2.2 Kohm ∮5% resistor.

PCH_BEEP

Note: Internal PD 20K

PCH_HDA_SDIN0

RC198 33_0402_5%

1 2 1 2

RC199 33_0402_5%

1 2

RC200 33_0402_5% RC201 33_0402_5%

1 2

RC41 2.2K_0402_5%@

1 2

RC44 1K_0402_5%@

HDA_BCLK HDA_SDOUT

RC40 0_0402_5%

+VCC_IO

+3VS

@

SKL_U LT

DGPU_HOLD _RST# PCH_HDA_BCLK

VGA_APWR_ON

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

[SKL PDG] internal SD Card

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

??7 OF 20

+3VS

@

12

DGPU_HOLD _RST#

VGA_APWR_ON

HDA_SYNC HDA_BCLK HDA_SDOUT PCH_HDA_SDIN0

HDA_RST#

VGA_APWR_ON _R

DGPU_HOLD _RST#

PCH_BEEP

UC1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKYLAKE-U_BGA1356

REV = 1 @

Reserve PD by NV suggestion

AUDIO

1 2

RC188 10K_0402_5%

1 2

RC187 10K_0402_5%

PCH_HDA_SDIN0[51]

GC6_FB_EN_G PIO[28]

VGA_APWR_ON[33,75]

VGA_APWR_ON

RC208 0_0402_5%

DGPU_HOLD _RST# [28]

PCH_BEEP[52]

1 2

RC211 100K_0402_5%

1 2

RC210 10K_0402_5%

Not support internal SD card. Remove SD_RCOMP

Note:

B B

A A

HDA_SDO should only be asserted high via external pull-up to 3.3A rail in manufacturing/debug environments ONLY.

Note: Internal PD 20K

5

HDA_SDOUT

HDA_SYNC

1 2

RC46 1K_0402_5%@

1 2

RC48 20K_0402_5%@

+VCC_HDA

+3VALW_PCH

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(5/16):HDA/SDIO

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

9 82

1

9 82

2.0

5

4

3

2

1

RTC External Circuit

+RTCBATT, +RTCVCC Trace width = 20mils

JCMOS, JME Setting, Need Under DDR Door

+RTCVCC+RTCVCC+RTCBATT

D D

+3VS

RC53 10K_0402_5%

1 2

@

C C

+3VS

1 2

RC55 10K_0402_5%

RC176 10K_0402_5%

1 2

RC177 10K_0402_5%

1 2

RC178 10K_0402_5%

1 2

RC209 10K_0402_5%

1 2

CLKREQ_PCIE 4_VGA#

CLKREQ_PCIE 2_WLAN#

CLKREQ_PCIE 3_LAN#

CLKREQ_PCIE 5_CR#

CLKREQ#_PCIE1_SSD

1 2

RC49 0_0402_5%

@

1

CC4 1U_0402_10V6-K

2

M.2 SSD

WLAN

LAN

VGA

CR

[SKL PDG]External pull-up resistor required if used for CLKREQ# functionality.

1

CC5

0.1U_0402_10V6-K

2

CLK_PCIE_SSD#[42] CLK_PCIE_SSD[42] CLKREQ#_PCIE1_SSD[42]

CLK_PCIE_WL AN#[48] CLK_PCIE_WL AN[48] CLKREQ_PCIE 2_WLAN#[48]

CLK_PCIE_LAN#[46] CLK_PCIE_LAN[46] CLKREQ_PCIE 3_LAN#[46]

CLK_PCIE_VG A#[25] CLK_PCIE_VGA[25] CLKREQ_PCIE 4_VGA#[25]

CLK_PCIE_CR#[49] CLK_PCIE_CR[49] CLKREQ_PCIE 5_CR#[49]

CLK_PCIE_SSD# CLK_PCIE_SSD CLKREQ#_PCIE1_SSD

CLK_PCIE_WL AN# SUSCLK_32K CLK_PCIE_WL AN CLKREQ_PCIE 2_WLAN#

CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_PCIE 3_LAN#

CLK_PCIE_VG A# CLK_PCIE_VGA CLKREQ_PCIE 4_VGA#

CLK_PCIE_CR# CLK_PCIE_CR CLKREQ_PCIE 5_CR#

1 2

RC50 20K_0402_5%

1 2

RC51 20K_0402_5%

D42 C42

AR10

B42 A42

AT7

D41 C41 AT8

D40 C40

AT10

B40 A40

AU8

E40 E38

AU7

PCH_RTCRST#

PCH_SRTCRST#

UC1J

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

REV = 1

@

JCMOS1 @

1 2

CC3 1U_0402_10V6K

1 2

JME1 @

1 2

CC6 1U_0402_10V6K

1 2

SKL_U LT

CLOCK SIGNALS

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

??10 OF 20

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

PCH_XTAL24_IN PCH_XTAL24_OUT

DIFFCLK_BIASREF

PCH_RTCX1 PCH_RTCX2

PCH_SRTCRST# PCH_RTCRST#

SUSCLK_32K [48]

1 2

RC56

2.7K_0402_1%

+1VALW

Place RC176,177,178,209 close together

[SKL PDG]

B B

A A

5

1.Sp ace > 15mils

2.No trace under crystal

3.Place on oppsosit si de of MCP for temp inf l uence

4.The exact capacitor values forC1 and C2 must be based on the crystal maker recommendat i ons. Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF.

PCH_RTCX1

RTC Cryst al

1 2

RC57 10M_0402_5%

1 2

YC1

32.768KHZ_12.5PF_9H03200042

1

CC7

6.8P_0402_50V8-D

2

20160127 Change CC7/CC8 to 6.8p by vender suggestion

4

PCH_RTCX2

[SKL PDG]Max Cr ystal ESR = 50k Ohm.

1

CC8

6.8P_0402_50V8-D

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

[SKL PDG]

1.A 24 MHz crystal with crystal frequency tolerance and stabili ty of +/-30 ppm

2.Two External Load Capacitors (Ce1 and Ce2)

3.A 1-Mohm bi as resistor (Rf)

PCH_XTAL24_IN

Issued Date

PCH_XTAL24_OUT

CC9

12P_0402_50V8-J

1

2

2015/09/01

1 2

RC58 1M_0402_5%

1

GND1

2

LC Future Center Secret Data

3

GND2

YC2

4

24MHZ_10PF_8Y24000011

Deciphered Date

2

1

CC10 12P_0402_50V8-J

2

2016/12/31

Title

KBL(6/16):CLOCK SIGNALS

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

10 82

1

10 82

2.0

5

4

3

2

1

Functional Strap Definitions

L:Disable Intel ME Crypto TLS cipher suite (no confidentiality).

D D

C C

*H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality).Support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

+3VALW_PCH

SMBALERT#

1 2

RC59 1K_0402_5%

GPP_C2, Internal PD 20K

JTAG ODT

+3VALW_PCH

SPI0_MOSI

SPI_SI

SPI_SO

1 2

@

RC62 8.2K_0402_5%

1 2

@

RC65 8.2K_0402_5%

+3VALW_PCH

close to CPU

All_GPU_PWRGD[25]

KBRST#[57]

10P_0402_50V8-J EMC_ NS@

KBRST#

1

2

CC183

SPI_CLK[21,58] SPI_SO[21,58] SPI_SI[21,58] SPI_IO2[21] SPI_IO3[21]

SPI_CS0#_8MB[21] SPI_CS1#_4MB[21] SPI_CS2#_TPM[58]

RC107 0_0402_5%

1 2

GPU_EVENT#[28]

EC_SCI#[57]

CL_CLK_WLAN[48]

CL_DATA_WLAN[48] CL_RST_WLAN#[48]

SERIRQ[57,58]

SPI_CLK SPI_SO SPI_SI SPI_IO2 SPI_IO3 SPI_CS0#_8MB SPI_CS1#_4MB SPI_CS2#_TPM

All_GPU_PWRG D_R GPU_EVENT# EC_SCI#

SERIRQ

UC1E

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

SKYLAKE-U_BGA1356

REV = 1

@

SPI - FLASH

SPI - TOUCH

C LINK

SKL_U LT

LPC

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

??5 OF 20

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

PCH_SMB_CLK PCH_SMB_DATA

SMBALERT#

SML0ALERT#

PCH_SML1CLK PCH_SML1DATA

SML1ALERT#

SUS_STAT#

PCH_PCI_CLK_R

CLKRUN#

LPC_AD0 [57] LPC_AD1 [57] LPC_AD2 [57] LPC_AD3 [57]

LPC_FRAME# [57]

RC66

8.2K_0402_5%

1 2

+3VS

DIMM1, DIMM2, Secur ity EEPROM, Cl i ck Pad

EC,dGPU,Thermal Sensor

RC63 0_0402_5%

@

1 2

EMC@

1 2

RC64 22_0402_5%

10P_0402_50V8-J EMC_ NS@

1

TC7

CLK_PCI_EC [57]

1

CC184

2

Close to UC1

GPP_C5, Internal PD 20K

*L: LPC H: eSPI

@

SML0ALERT#

B B

1 2

RC67 1K_0402_5%

Place RC179,180,181 close together

1 2

RC179 10K_0402_5% RC180 10K_0402_5%

1 2 1 2

RC181 10K_0402_5%

RC72 4.7K_0402_5%

1 2 1 2

RC76 4.7K_0402_5%

1 2

RC212 10K_0402_5%

SERIRQ EC_SCI#

KBRST#

CP_SMB_CLK CP_SMB_DAT

GPU_EVENT#

PCH_SMB_CLK PCH_SMB_DATA PCH_SML1CLK PCH_SML1DATA

+3VALW_PCH

RC71 2.2K_0402_1%

1 2 1 2

RC73 2.2K_0402_1% RC74 2.2K_0402_1%

1 2 1 2

RC75 2.2K_0402_1%

SB00000YS00

2N7002KDWH_SOT 363-6

+3VALW_PCH+3VS

PCH_SMB_CLK

+3VS

QC1A

6 1

D

G

2

PCH_SML1CLK

S

CP_SMB_CLK [22,23,63]

+3VS

SB00000YS00

2N7002KDWH_SOT 363-6 QC2A

6 1

D

S

G

2

EC_SMB_CK3 [28,57,59,62]

Plan to remove QC1 after SDV

5

G

5

G

Add RC212 PU by NV suggestion

SML1ALERT#

A A

1 2

RC77 1K_0402_5%@

PCH_SMB_DATA PCH_SML1DATA

3 4

S

D

QC1B 2N7002KDWH_SOT 363-6

SB00000YS00

CP_SMB_DAT [22,23,63]

3 4

S

D

QC2B 2N7002KDWH_SOT 363-6

SB00000YS00

EC_SMB_DA3 [28,57,59,62]

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(7/16):LPC/SPI/SMBUS/CL

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

11 82

1

11 82

2.0

5

4

3

2

1

D D

VCCST_PG_EC[57]

C C

+VCC_ST

12

RC85 1K_0402_5%

EC_RSMRST#[57]

PCH_SYSPWROK[57]

PCH_PWROK[57]

+3VALW

+3VS

Place RC183.184.185.186 close together

1 2

RC183 10K_0402_5%

1 2

RC184 10K_0402_5%

1 2

RC185 10K_0402_5%

1 2

RC186 10K_0402_5%

1 2

@

RC87 10K_0402_5%

1 2

RC218

20160408

1.Add RC218 for PME# by BIOS request

+3VALW_PCH

AC_PRESENT

BATLOW#

PCIE_WAKE#

PCH_SLP_LAN#

PBTN_OUT#

PME#

20K_0402_5%

1 2

RC78 10K_0402_5%

RC89 60.4_0402_1%

1 2

RC81 0_0402_5%

1 2

RC82 0_0402_5%

TC10

TC12

PLTRST# SYS_RESET#

EC_RSMRST#

H_CPUPWRGD

1

VCCST_PWRGD

PCH_SYSPWROK PCH_PWROK EC_DPWROK_REC_RSMRST#

SUSPWRDNACK SUSACK#

PCIE_WAKE#

1

RC93 10K_0402_5%

1 2

PCH_PWROK

UC1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKYLAKE-U_BGA1356

REV = 1 @

SYSTEM POWER MANAGEMENT

EC_RSMRST#

RC94 10K_0402_5%

1 2

SKL_U LT

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

PLTRST#

RC88

100K_0402_5%

??11 OF 20

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

12

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

PCH_SLP_SUS# PCH_SLP_LAN#

PM_SLP_A#

PBTN_OUT# AC_PRESENT

BATLOW#

PME# PCH_INTRUDER#

EXT_PWR_GATE# VRALERT#

UC3

1

NC

2

IN_A

3

GND

TC7SG17FE_ SON5

1

TC8

1

TC9

1

TC28

1

TC11

RC83 1M_0402_5%

1

TC13

1

TC14

5

VCC

4

OUT_Y

PM_SLP_S3# [57] PM_SLP_S4# [57] PM_SLP_S5# [57]

PCH_SLP_LAN# [46]

PBTN_OUT# [57] AC_PRESENT [57]

12

Connect to Power

+3VALW

+RTCVCC

PLT_RST# [28,42,46,48,49,57,58]

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(8/16):SYSTEM PM

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

12 82

1

12 82

2.0

5

4

3

2

1

D D

C C

Place decoupling cap on TOP side

[KBL PDG]VCC

[KBL PDG] EE 10uF x7, 10uF x8, 1uF x35 Power 22uF x9, 47uF x8

CC13

1

2

CC27

1

2

CC53

1

2

CC63

1

2

1U_0201_6.3V6-M

CC15

1

2

1U_0201_6.3V6-M

CC29

CC28

1

2

1U_0201_6.3V6-M

CC54

CC55

1

2

1U_0201_6.3V6-M

CC64

CC66

1

2

10U_0402_6.3V6-M

CC14

10U_0402_6.3V6-M

CC16

CC17

1

2

1U_0201_6.3V6-M

CC31

CC30

1

2

1U_0201_6.3V6-M

CC56

CC57

1

2

1U_0201_6.3V6-M

CC68

CC65

1

2

10U_0402_6.3V6-M

CC18

CC171

1

2

1U_0201_6.3V6-M

CC33

CC32

1

2

1U_0201_6.3V6-M

CC59

CC58

1

2

1U_0201_6.3V6-M

CC70

CC67

1

2

10U_0402_6.3V6-M

CC19

1

2

1U_0201_6.3V6-M

CC34

1

2

1U_0201_6.3V6-M

CC60

1

2

1U_0201_6.3V6-M

CC69

1

2

1U_0201_6.3V6-M

CC20

CC21

1

2

1U_0201_6.3V6-M

CC35

1U_0201_6.3V6-M

CC36

1

2

1U_0201_6.3V6-M

CC62

CC61

1

2

1U_0201_6.3V6-M

CC71

CC170

1

2

1

2

1

2

1

2

1U_0201_6.3V6-M

CC22

1

2

1U_0201_6.3V6-M

1

2

1U_0201_6.3V6-M

1

2

1U_0201_6.3V6-M

CC72

1

2

Place decoupling cap on TOP side

+VCC_GT+VCC_CORE

[KBL PDG]VCCGT

[KBL PDG] EE 10uF x12,1uF x14, Power 47uF x8,22uFx12

10U_0603_6.3V6-M

CC23

CC24

12

1U_0402_10V6-K

CC37

CC38

1

2

10U_0603_6.3V6-M

CC25

12

1U_0402_10V6-K

CC39

1

2

10U_0603_6.3V6-M

CC173

CC26

12

1U_0402_10V6-K

CC40

1

2

CC41

1

2

10U_0603_6.3V6-M

CC174

CC175

CC176

CC177

CC178

1U_0402_10V6-K

CC179

12

1U_0402_10V6-K

CC47

CC46

1

2

12

1U_0402_10V6-K

CC42

1

2

CC43

1

2

1U_0402_10V6-K

CC44

1

2

CC45

1

2

10U_0603_6.3V6-M

CC180

12

1U_0402_10V6-K

CC48

1

2

CC49

1

2

1U_0402_10V6-K

CC50

1

2

10U_0402_6.3V6-M

CC75

10U_0402_6.3V6-M

CC77

CC76

1

2

10U_0402_6.3V6-M

CC73

CC74

1

2

B B

A A

Place decoupling cap on bottom side

10U_0402_6.3V6-M

CC78

CC79

1

2

10U_0402_6.3V6-M

CC172

1

2

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(9/16):Decoupling

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

13 82

1

13 82

2.0

5

4

3

2

1

D D

GPP_B22, Internal PD 20K

*L: SPI H: LPC

GSPI1_MOSI

To enable boot to LPC, this signal should be pulled up to V3.3S through a 1k to

2.2 K ∮5 % resistor

@

RC95 1K_0402_5%

12

+3VS

GPP_B18, Internal PD 20K

*L: Disable ¨ No Reboot〃 mode H: Enable ¨ No Reboot〃 mode

GSPI0_MOSI

To enable no reboot on TCO Timer expiration

C C

UC1F

RF_OFF#[48]

BT_ON[48]

UART2_RX[48]

B B

UART2_TX[48] F4_LED#[60] PCH_TSOFF#[37]

RF_OFF#

BT_ON

UART2_RX UART2_TX F4_LED# PCH_TSOFF#

@

1 2

GSPI0_MOSI

GSPI1_MOSI

PLANARID0 PLANARID1 PLANARID2

MIC_HW_EN

RC108 0_0402_5%

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

SKYLAKE-U_BGA1356

AH11

REV = 1

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

LPSS ISH

, this signal should be pulled-up to V3.3S through a 1k to 2.2 K ∮5 % resistor

?

SKL_U LT

6 OF 20

RC102 1K_0402_5%

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

12

@

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

?

GPP_A12/BM_BUSY#/ISH_GP6

+3VS

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

DCI_CLK DCI_DATA

F1_LED#

F1_LED# [60]

1

TC17

Project ID

PLANARID0 (GPP_C8)

L

14"

H

15"

PLANARID0

PLANARID1

PLANARID2

DCI_CLK [55] DCI_DATA [55]

PLANARID1 (GPP_C9)

UMA

DIS

12

RC96 10K_0402_5%

KBL@

12

RC101 10K_0402_5%

SKL@

PLANARID2 (GPP_C10)

Skylake

Kabylake

12

RC52 10K_0402_5%

DIS@

RC54 10K_0402_5%

UMA@

1 2

+3VS

12

RC99 10K_0402_5%@

RC104 10K_0402_5%

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(10/16):GPIO/CPU/MISC

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

14 82

1

14 82

2.0

5

D D

4

3

2

1

USB Port Number

UC1H

PCIE/ USB3/S ATA

1 1

PCIE_CRX_GTX _N1 PCIE_CRX_GTX _P1 PCIE_CTX_G RX_N1 PCIE_CTX_G RX_P1

PCIE_CRX_GTX _N2 PCIE_CRX_GTX _P2 PCIE_CTX_G RX_N2 PCIE_CTX_G RX_P2

PCIE_CRX_GTX _N3 PCIE_CRX_GTX _P3 PCIE_CTX_G RX_N3 PCIE_CTX_G RX_P3

PCIE_CRX_GTX _N4 PCIE_CRX_GTX _P4 PCIE_CTX_G RX_N4 PCIE_CTX_G RX_P4

PCIE_PRX_DTX _N5 PCIE_PRX_DTX _P5 PCIE_PTX_DRX_ N5 PCIE_PTX_DRX_ P5

SATA_PRX_DTX _N0 SATA_PRX_DTX _P0 SATA_PTX_DRX_ N0 SATA_PTX_DRX_ P0

PCIE_PRX_DTX _N9 PCIE_PRX_DTX _P9 PCIE_PTX_DRX_ N9 PCIE_PTX_DRX_ P9

PCIE_PRX_DTX _N10 PCIE_PRX_DTX _P10 PCIE_PTX_DRX_ N10 PCIE_PTX_DRX_ P10

PCIE_RCOMP

XDP_PRDY_N XDP_PREQ_N

PIRQA#

PCIE_PRX_DTX _N11 PCIE_PRX_DTX _P11 PCIE_PTX_DRX_ N11 PCIE_PTX_DRX_ P11 PCIE_PRX_DTX _N12 PCIE_PRX_DTX _P12 PCIE_PTX_DRX_ N12 PCIE_PTX_DRX_ P12

PCIE_CRX_GTX _N1[25]

PCIE_CRX_GTX _P1[25] PCIE_CTX_C_ GRX_N1[25] PCIE_CTX_C_ GRX_P1[25]

PCIE_CRX_GTX _N2[25]

PCIE_CRX_GTX _P2[25] PCIE_CTX_C_ GRX_N2[25] PCIE_CTX_C_ GRX_P2[25]

GPU

C C

Card Reader

HDD

WLAN

LAN

B B

M.2 SSD

PCIE_CRX_GTX _N3[25]

PCIE_CRX_GTX _P3[25] PCIE_CTX_C_ GRX_N3[25] PCIE_CTX_C_ GRX_P3[25]

PCIE_CRX_GTX _N4[25]

PCIE_CRX_GTX _P4[25] PCIE_CTX_C_ GRX_N4[25] PCIE_CTX_C_ GRX_P4[25]

PCIE_PRX_DTX _N5[49]

PCIE_PRX_DTX _P5[49] PCIE_PTX_C_ DRX_N5[49] PCIE_PTX_C_ DRX_P5[49]

SATA_PRX_DTX _N0[42]

SATA_PRX_DTX _P0[42] SATA_PTX_DRX_ N0[42] SATA_PTX_DRX_ P0[42]

PCIE_PRX_DTX _N9[48]

PCIE_PRX_DTX _P9[48] PCIE_PTX_C_ DRX_N9[48] PCIE_PTX_C_ DRX_P9[48]

PCIE_PRX_DTX _N10[46]

PCIE_PRX_DTX _P10[46] PCIE_PTX_C_ DRX_N10[46] PCIE_PTX_C_ DRX_P10[46]

PCIE_PRX_DTX _N11[42]

PCIE_PRX_DTX _P11[42] PCIE_PTX_DRX_ N11[42] PCIE_PTX_DRX_ P11[42]

PCIE_PRX_DTX _N12[42]

PCIE_PRX_DTX _P12[42] PCIE_PTX_DRX_ N12[42] PCIE_PTX_DRX_ P12[42]

1 2

CC86 0.22U_0402_10V6-K

DIS@

CC87 0.22U_0402_10V6-K

1 2

DIS@

1 2

CC88 0.22U_0402_10V6-K

DIS@

CC89 0.22U_0402_10V6-K

1 2

DIS@

1 2

CC90 0.22U_0402_10V6-K

DIS@

CC91 0.22U_0402_10V6-K

1 2

DIS@

1 2

CC92 0.22U_0402_10V6-K

DIS@

CC93 0.22U_0402_10V6-K

1 2

DIS@

1 2 1 2

CC84 0.1U_0402_10V7-K CC85 0.1U_0402_10V7-K

1 2 1 2

CC82 0.1U_0402_10V7-K CC83 0.1U_0402_10V7-K

1 2 1 2

CC80 0.1U_0402_10V7-K CC81 0.1U_0402_10V7-K

1 2

RC115 100_0402_1%

TC18 TC19

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

REV = 1 @

SKL_U LT

SSIC / USB3

USB3_1_RXN USB3_1_RXP USB3_1_TXN

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_TXP

USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

??8 OF 20

USB3P1_RXN USB3P1_RXP USB3P1_TXN USB3P1_TXP

USB3P2_RXN USB3P2_RXP USB3P2_TXN USB3P2_TXP

USB3P4_RXN USB3P4_RXP USB3P4_TXN USB3P4_TXP

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N4 USB20_P4

USB20_N5 USB20_P5

USB20_N6 USB20_P6

USB20_N7 USB20_P7

USB20_N8 USB20_P8

USB20_N9 USB20_P9

USBCOMP USB2_ID

USB2_VBUSSENSE

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

HDD_DEVSLP0

SSD_DEVSLP1

SSD_DET#

USB3P1_RXN [55] USB3P1_RXP [55]

USB3P1_TXN [55] USB3P1_TXP [55]

USB3P2_RXN [44] USB3P2_RXP [44]

USB3P2_TXN [44] USB3P2_TXP [44]

USB3P4_RXN [44] USB3P4_RXP [44]

USB3P4_TXN [44] USB3P4_TXP [44]

USB20_N1 [55] USB20_P1 [55]

USB20_N2 [44] USB20_P2 [44]

USB20_N3 [45] USB20_P3 [45]

USB20_N4 [44] USB20_P4 [44]

USB20_N5 [37] USB20_P5 [37]

USB20_N6 [48] USB20_P6 [48]

USB20_N7 [37] USB20_P7 [37]

USB20_N8 [37] USB20_P8 [37]

USB20_N9 [61] USB20_P9 [61]

1 2

RC114 113_0402_1%

USB_OC1# [44] USB_OC2# [44] USB_OC3# [44]

HDD_DEVSLP0 [42]

SSD_DEVSLP1 [42]

SSD_DET# [42]

TYPE C

On Board (Lef t)

On Bo ard (Ri ght-Front)

TYPE C

On Board (AOU)

On Bo ard (Ri ght-Back)

On Bo ard (Ri ght-Front)

Touch Panel

BT

CAM ERA

IR CAMERA

FPR

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

20160308

1. Add RC215,RC217 for SSD detect

SSD_DEVSLP1

SSD_DET#

HDD_DEVSLP0

PIRQA#

SSD_DEVSLP1

USB2_ID

USB2_VBUSSENSE

1K_0402_5%

Reserve

Port2

Port3

Port4

+3VALW_PCH

RC190 10K_0402_5%

1 2 1 2

RC191 10K_0402_5%

1 2

RC192 10K_0402_5% RC193 10K_0402_5%

1 2

RC216 10K_0402_5%@

RC215 10K_0402_5%

RC110 10K_0402_5%

RC113 10K_0402_5%

RC217 10K_0402_5%

RC116

12

RC117

1K_0402_5%

1 2

+3VS

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(11/16):PCIE/USB/SATA

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

15 82

1

15 82

2.0

5

4

3

2

1

SKL_U LT

CPU POWER 1 OF 4

VCC_SENSE VSS_SENSE

VCCSTG_G20

+VCC_GT

+VCC_SFR+VCC_ST

RC127

1 2

0_0402_5%

Place CC110 on bottom side

[SKL PDG]VCCPLL

[SKL PDG]1uF x1

+VCC_SFROC should be sourced from the VDDQ VR

+VCC_GT

12

RC136 0_0402_5%@ RC137 0_0402_5%@

12

CC110

1

2

1 2 1 2

1U_0402_10V6K

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VIDALERT#

VIDSCK

VIDSOUT

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

??12 OF 20

UC1M

A48

VCCGT_A48

A53

VCCGT_A53

A58

VCCGT_A58

A62

VCCGT_A62

A66

VCCGT_A66

AA63

VCCGT_AA63

AA64

VCCGT_AA64

AA66

VCCGT_AA66

AA67

VCCGT_AA67

AA69

VCCGT_AA69

AA70

VCCGT_AA70

AA71

VCCGT_AA71

AC64

VCCGT_AC64

AC65

VCCGT_AC65

AC66

VCCGT_AC66

AC67

VCCGT_AC67

AC68

VCCGT_AC68

AC69

VCCGT_AC69

AC70

VCCGT_AC70

AC71

VCCGT_AC71

J43

VCCGT_J43

J45

VCCGT_J45

J46

VCCGT_J46

J48

VCCGT_J48

J50

VCCGT_J50

J52

VCCGT_J52

J53

VCCGT_J53

J55

VCCGT_J55

J56

VCCGT_J56

J58

VCCGT_J58

J60

VCCGT_J60

K48

VCCGT_K48

K50

VCCGT_K50

K52

VCCGT_K52

K53

VCCGT_K53

K55

VCCGT_K55

K56

VCCGT_K56

K58

VCCGT_K58

K60

VCCGT_K60

L62

VCCGT_L62

L63

VCCGT_L63

L64

VCCGT_L64

L65

VCCGT_L65

L66

VCCGT_L66

L67

VCCGT_L67

L68

VCCGT_L68

L69

VCCGT_L69

L70

VCCGT_L70

L71

VCCGT_L71

M62

VCCGT_M62

N63

VCCGT_N63

N64

VCCGT_N64

N66

VCCGT_N66

N67

VCCGT_N67

N69

VCCGT_N69

J70

VCCGT_SENSE

J69

VSSGT_SENSE

SKYLAKE-U_BGA1356

REV = 1 @

VCC_SENSE_R VSS_SENSE_R

VR_SVID_ALRT#_R VR_SVID_CLK VR_SVID_DAT

1 2 1 2

SKL_U LT

CPU POWER 2 OF 4

+VCC_STG

VCCGTX_SENSE VSSGTX_SENSE

RC121 0_0402_5%@ RC122 0_0402_5%@

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71 VCCGT_T62 VCCGT_U65 VCCGT_U68

VCCGT_U71 VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71

VCCGT_Y62

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

+VCC_ST

12

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

[KBL PDG]VIDSOUT

VR_SVID_DAT [70]

[KBL PDG]VIDSCK

VR_SVID_CLK [70]

Rpu1

RC125 56_0402_1%

VR_SVID_ALRT#VR_SVID_ALRT#_R

+VCC_IO

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE_R VCCSA_SENSE_R

[KBL PDG]VIDALERT#

VR_SVID_ALRT# [70]

[KBL PDG]VCCIO

[KBL PDG]1uF x4

1U_0402_10V6-K

CC102

+VCC_SA

CC114

CC120

RC131

1 2 1 2

@

RC1320_0402_5%

12

1U_0402_10V6-K

CC104

1

2

[KBL PDG]VCCSA

[KBL PDG]10uF x13, 1uF x7

10U_0603_6.3V6-M

CC115

12

10U_0603_6.3V6-M

1U_0402_10V6-K

CC121

1

2

RC129 100_0402_1%

1 2 1 2

RC130 100_0402_1%

0_0402_5%@

CC103

CC116

CC122

1U_0402_10V6-K

1

2

10U_0603_6.3V6-M

12

1U_0402_10V6-K

1

2

12

RC135 100_0402_1%

Place decoupling cap

1U_0402_10V6-K

on TOP side

CC105

1

2

10U_0603_6.3V6-M

CC117

12

CC124

+VCC_SA

1

2

1U_0402_10V6-K

CC118

CC123

12

CC119

12

1U_0402_10V6-K

CC126

1

2

+VCC_IO

RC133 100_0402_1%

10U_0603_6.3V6-M

Place decoupling cap

12

on TOP side

1U_0402_10V6-K

CC127

CC125

1

2

1

2

VSSSA_SENSE [70]

VCCSA_SENSE [70]

+VCC_ST

Rpu2

+VCC_CORE

12

RC120 100_0402_1%

RC123 100_0402_1%

VCC_SENSE [70]

VSS_SENSE [70]

VR_SVID_DAT

VR_SVID_CLK

12

+VCC_ST

12

RC119 100_0402_1%

Rpu1

RC124 100_0402_1%@

Rs1

1 2

RC126 220_0402_1%

+VCC_GT

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

??13 OF 20

Place CC109 on bottom side

10U_0603_6.3V6-M

CC97

CC98

12

+VCC_STG

+VCC_SFROC

+VCC_SFR

10U_0603_6.3V6-M

CC99

+1.2V

+VCC_ST

+1.2V

10U_0603_6.3V6-M

CC100

12

[KBL PDG]VDDQ

[KBL PDG]10uF x4

UC1N

AU23 AU28 AU35 AU42

BB23 BB32 BB41 BB47 BB51

AM40

A18

A22

AL23

K20 K21

CPU POWER 3 OF 4

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20 VCCPLL_K21

SKYLAKE-U_BGA1356

REV = 1 @

SKL_U LT

VCCIO_AK28 VCCIO_AK30 VCCIO_AL30

VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

VCCSA_AK23 VCCSA_AK25

VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28

VCCSA_J22 VCCSA_J23

VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

??14 OF 20

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40

AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

G30

K32

AK32

AB62

P62 V62

H63

G61

AC63 AE63

AE62 AG62

AL63

AJ62

CC109

+VCC_SFROC+1.2V

CC130

100_0402_1%

1

2

1

2

UC1L

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO_AE62 VCCEOPIO_AG62

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKYLAKE-U_BGA1356

REV = 1

@

1U_0402_10V6K

RC134

RC138

+VCC_CORE +VCC_CORE

D D

C C

+VCC_STG +VCC_ST

1U_0402_10V6K

CC108

1

2

Place CC109 on bottom side

[SKL PDG]VCCSTG

B B

A A

[SKL PDG]1uF x1

+1.2V

CC129

Place CC129 on bottom side

[SKL PDG]VDDQC

[SKL PDG]10uF x1

Preferred to place the 10uF cap on the secondary under the package shadow near VDDQC pin and short to VDDQ rail under with a shape

10U_0603_6.3V6-M

12

[SKL PDG]VCCST

[SKL PDG]1uF x1

RC128

1 2

0_0402_5%

Place CC130 on bottom side

[SKL PDG]VCCPLL

[SKL PDG]1uF x1

VCCGT_SENSE[70]

VSSGT_SENSE[70]

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(12/16):POWER

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

16 82

1

16 82

2.0

5

4

3

+1VALW_PCH

2

1

D D

Reserve for Sense Resistor

+1.8VALW +1.8VALW_PCH

RC139 0_0603_5%

+3VALW +3VALW_PCH

+1VALW +1VALW_PCH

+1VALW +VCC_MPHYGT

1 2

RC140 0_0805_5%

1 2

RC141 0_0805_5%

1 2

RC202 0_0805_5%

1 2

CC132 please close to N18

[SKL PDG]VccAPLLEBB

[SKL PDG]1uF x1 [SKL PDG]Close N18, Placement type:Edge<3mm(118mil)

SRAM Primary Well 1.0 V. Dedicated SRAM rail and can have on board power down gate control.

CC136 please close to AF20

[SKL PDG]VccSRAM

[SKL PDG]1uF x1 [SKL PDG]Close AF20, Placement type:Edge<10mm(394mil)

C C

+VCC_MPHYGT

+1VALW_PCH

1 2

RC145 0_0402_5%

1 2

RC146 0_0402_5%

+VCC_AMPHYPLL

+1VALW_PLL

+3VALW_PCH

please close to AG15 , Y16 & T16

1U_0402_10V6K

1

CC140

CC141

2

+VCC_MPHYGT

1U_0402_10V6K

1

CC142

2

1U_0402_10V6K

VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.)

+VCC_MPHYGT

1

CC132

[SKL PDG]VccMPHYGT

2

[SKL PDG]1uF x1 [SKL PDG]Close N15, Placement type:Edge<3mm(118mil) [SKL PDG]47uF x1 [SKL PDG]Close N15, Placement type:Edge<10mm(394mil)

Mod PHY Always On Primary 1.0 V: Always on primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic

1

@

CC136

2

[SKL PDG]VccMPHYAON

[SKL PDG]1uF x1 [SKL PDG]Close K17, Placement type:Edge<3mm(118mil)

Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM power, USB AFE Digital Logic, JTAG, Thermal Sensor and MIPI DPHY.

CC133 & CC134 please close to N15

1U_0402_10V6K

1

2

+1VALW_PCH

CC137 please close to K17

1U_0402_10V6K

1

2

+1VALW_PCH

CC143 please close to AB19

1U_0402_10V6K

1

[SKL PDG]VCCPRIM

[SKL PDG]1uF x1 [SKL PDG]Close AB19, Placement type:Edge<10mm(394mil)

2

CC133

CC137

CC143

1

CC134 47U_0805_6.3V6-M

2

CC181

22U_0603_6.3V6-M

CC182

22U_0603_6.3V6-M

1

2

1

2

+VCC_HDA

1

CC131 22U_0603_6.3V6-M

2

1

CC135 22U_0603_6.3V6-M

2

+1VALW_PLL

+VCC_MPHYGT

+VCC_AMPHYPLL

+VCC_DSW3P3

+3V_SPI

+3VALW_PRIM

+PCH_CORE

+DCPDSW

UC1O

AB19

VCCPRIM_1P0_AB19

AB20

VCCPRIM_1P0_AB20

P18

VCCPRIM_1P0_P18

AF18

VCCPRIM_CORE_AF18

AF19

VCCPRIM_CORE_AF19

V20

VCCPRIM_CORE_V20

V21

VCCPRIM_CORE_V21

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0_K17

L1

VCCMPHYAON_1P0_L1

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0_K15

L15

VCCAMPHYPLL_1P0_L15

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0_AF20

AF21

VCCSRAM_1P0_AF21

T19

VCCSRAM_1P0_T19

T20

VCCSRAM_1P0_T20

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKYLAKE-U_BGA1356

REV = 1 @

SKL_ULT

CPU POWER 4 OF 4

1100mA

600mA

22mA

1500mA

88mA

26mA

118mA

68mA

565mA

75mA

33mA

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE

VCCPGPPF VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

85mA

+3VALW_PCH

161mA

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19

T1

AA1

AK17

AK19 BB14

BB10

+DCPRTC

A14

K19

L21

N20

L19

A10

AN11 AN13

??15 OF 20

+1.8VALW_PCH

1

T1

1

T2

+3VALW_PRIM

135mA

+1VALW_PCH

+1.8VALW_PCH

+3VALW_RTCPRIM

+RTCVCC

Primary Well 3.3 V

B B

A A

5

+3VALW_PCH

1 2

RC147 0_0402_5%

[SKL PDG]VCCPRIM [SKL PDG]VccHDA

[SKL PDG]1uF x1 [SKL PDG]Close V19, Placement type:Edge<3mm(118mil)

+VCC_AMPHYPLL

+3VALW_PRIM +VCC_HDA

@

1U_0402_10V6K

1

@

CC149

2

HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Definition Audio.

+3VALW_PCH

1 2

1

CC145

2

[SKL PDG]1uF x1 [SKL PDG]Close AJ19, Placement type:Edge<10mm(394mil)

Core Logic Primary Well: This rail scales from 0.85 V to 1.0 V.

[SKL PDG]VccPRIM_Core

[SKL PDG]1uF x1 [SKL PDG]Close AF18, Placement type:Edge<10mm(394mil)

4

RC148 0_0402_5%

+1VALW

1 2

RC151 0_0805_5%

Thermal Sensor Primary Well 1.8 V

@

1U_0402_10V6K

+PCH_CORE

1U_0402_10V6K

1

2

1

2

[SKL PDG]VccATS [SKL PDG]DcpDSW [SKL PDG]DcpRTC

CC147

[SKL PDG]1uF x1 [SKL PDG]Close AA1, Placement type:Edge<10mm(394mil)

Deep Sx Well for GPD GPIOs and USB2

+3VALW_PCH +VCC_DSW3P3

CC150

[SKL PDG]VccDSW

1 2

RC152 0_0402_5%

@

3

+1.8VALW_PCH

1U_0402_10V6K

1

2

Deep Sx Well 1.0 V: This rail is generated by on die DSW low dropout (LDO) linear voltage regulator to supply DSW GPIOs, DSW core logic and DSW USB2 logic. Board needs to connect 1 uF capacitor to this rail and power should NOT be driven from the board. When primary well power is up, this rail is bypassed from VCCPRIM_1p0.

CC144

[SKL PDG]1uF x1 [SKL PDG]Close AL1, Placement type:Edge<3mm(118mil)

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

+3VALW_PCH

1 2

RC150 0_0402_5%

@

[SKL PDG]VccRTCPRIM

[SKL PDG]1uF x1,0.1uF x2 [SKL PDG]Close AK17, Placement type:Edge<3mm(118mil)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+DCPDSW

1U_0402_10V6K

1

CC148

2

+3VALW_RTCPRIM

1U_0402_10V6K

1

CC151

2

2015/09/01

0.1U_0402_10V6-K

1

2

RTC de-coupling capacitor only. This rail should NOT be driven.

[SKL PDG]0.1uF x1 [SKL PDG]Close BB10, Placement type:Edge<3mm(118mil)

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

0.1U_0402_10V6-K

1

CC153

CC152

[SKL PDG]VccRTC

[SKL PDG]1uF x1

2

[SKL PDG]Close AK19, Placement type:Edge<3mm(118mil)

LC Future Center Secret Data

Deciphered Date

2016/12/31

+DCPRTC

1

CC146

0.1U_0402_10V6-K

2

+RTCVCC

1U_0402_10V6K

1

CC154

2

Title

KBL(13/16):POWER

Size Document Number Rev

A2

Date: Sheet of

KENOBI

Thursday, August 25, 2016

1

17 82

2.0

5

D D

4

3

2

1

UC1R

SKL_U LT

GND 3 OF 3

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

VSS_K63

K64

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

SKYLAKE-U_BGA1356

REV = 1

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21

VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13

VSS_R6 VSS_T15 VSS_T17 VSS_T18

VSS_T2

VSS_T21

VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18

VSS_W13

VSS_W6

VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

18 OF 20

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

??

AT63 AT68

AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68 BA45

UC1Q

SKL_U LT

GND 2 OF 3

VSS_AT63 VSS_AT68 VSS_AT71 VSS_AU10 VSS_AU15 VSS_AU20 VSS_AU32 VSS_AU38 VSS_AV1 VSS_AV68 VSS_AV69 VSS_AV70 VSS_AV71 VSS_AW10 VSS_AW12 VSS_AW14 VSS_AW16 VSS_AW18 VSS_AW21 VSS_AW23 VSS_AW26 VSS_AW28 VSS_AW30 VSS_AW32 VSS_AW34 VSS_AW36 VSS_AW38 VSS_AW41 VSS_AW43 VSS_AW45 VSS_AW47 VSS_AW49 VSS_AW51 VSS_AW53 VSS_AW55 VSS_AW57 VSS_AW6 VSS_AW60 VSS_AW62 VSS_AW64 VSS_AW66 VSS_AW8 VSS_AY66 VSS_B10 VSS_B14 VSS_B18 VSS_B22 VSS_B30 VSS_B34 VSS_B39 VSS_B44 VSS_B48 VSS_B53 VSS_B58 VSS_B62 VSS_B66 VSS_B71 VSS_BA1 VSS_BA10 VSS_BA14 VSS_BA18 VSS_BA2 VSS_BA23 VSS_BA28 VSS_BA32 VSS_BA36 VSS_F68 VSS_BA45

VSS_BA49 VSS_BA53 VSS_BA57

VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55

VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70

VSS_C1

VSS_C25

VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58

VSS_D6 VSS_D62 VSS_D66 VSS_D69

VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56

VSS_E6

VSS_E65 VSS_E71

VSS_F1

VSS_F13

VSS_F2

VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38

VSS_F4

VSS_F40 VSS_F42

VSS_BA41

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

UC1P

SKL_U LT

GND 1 OF 3

A5

VSS_A5

A67

VSS_A67

A70

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD13

AD16

VSS_AD16

AD19

VSS_AD19

C C

B B

AD20 AD21 AD62

AD8 AE64 AE65 AE66 AE67 AE68 AE69

AF1

AF10 AF15 AF17

AF2

AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6 AH63 AH64 AH67

AJ15 AJ18 AJ20

AJ4 AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2 AL28 AL32 AL35 AL38

AL4 AL45 AL48 AL52 AL55 AL58 AL64

VSS_AD20 VSS_AD21 VSS_AD62 VSS_AD8 VSS_AE64 VSS_AE65 VSS_AE66 VSS_AE67 VSS_AE68 VSS_AE69 VSS_AF1 VSS_AF10 VSS_AF15 VSS_AF17 VSS_AF2 VSS_AF4 VSS_AF63 VSS_AG16 VSS_AG17 VSS_AG18 VSS_AG19 VSS_AG20 VSS_AG21 VSS_AG71 VSS_AH13 VSS_AH6 VSS_AH63 VSS_AH64 VSS_AH67 VSS_AJ15 VSS_AJ18 VSS_AJ20 VSS_AJ4 VSS_AK11 VSS_AK16 VSS_AK18 VSS_AK21 VSS_AK22 VSS_AK27 VSS_AK63 VSS_AK68 VSS_AK69 VSS_AK8 VSS_AL2 VSS_AL28 VSS_AL32 VSS_AL35 VSS_AL38 VSS_AL4 VSS_AL45 VSS_AL48 VSS_AL52 VSS_AL55 VSS_AL58 VSS_AL64

VSS_AL65

VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71

VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63 VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68 VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48

VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63

VSS_AR8

VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35

VSS_AT42 VSS_AT56 VSS_AT58

VSS_AT2

VSS_AT4

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

SKYLAKE-U_BGA1356

REV = 1

A A

5

16 OF 20

4

??

SKYLAKE-U_BGA1356

REV = 1

17 OF 20

??

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(14/16):GND

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

18 82

1

18 82

2.0

5

D D

4

3

2

1

UC1I

C C

B B

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U_BGA1356

REV = 1 @

SKL_U LT

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

??9 OF 20

1 2

@

RC153 200_0402_1%

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(15/16):CSI-2/EMMC

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

19 82

1

19 82

2.0

5

4

3

2

1

D D

UC1S

CFG0

CFG3 CFG4

RC158 49.9_0402_1%

C C

+1VALW_PCH

RC160 1.5K_0402_5%

12

CFG_RCOMP

ITP_PMODE

E68 B67 D65 D67 E70 C68 D68 C67

F71

G69

F70

G68 H70 G71 H69 G70

E63

F63

E66

F66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

F60

A52

BA70 BA68

J71 J68

F65

G65

F61

E61

E8

D1 D3

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKL_U LT

RESERVED SIGNALS-1

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

TP5 TP6

RSVD_D5 RSVD_D4

RSVD_B2

RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4

RSVD_C4

TP4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

TP1 TP2

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

A69 B69

AY3

D71 C70

C54 D54

AY4 BB3

AY71 AR56

AW71 AW70

AP56 C64

RSVD_AY3

VSS_AY71 ZVM#

MSM# PROC_SELECT

RC161

1 2

@

RC162

1 2

1

0_0402_5%

0_0402_5%@ TC21

TC22

+VCC_ST

12

@

RC163 100K_0402_1%

[SKL EDS]

CFG0

L:Stall. *H:(Default) Normal Operation; No stall.

RC154 1K_0402_5%@

RC155 1K_0402_1%@

CFG4

*L: Embedded DisplayPort Enabled H: Embedded DisplayPort Disabled

RC156 1K_0402_5%@

RC157 1K_0402_1%

CFG3

CFG3 require >= 0.5"

CPU Debug Consent Strap

1 2

RC159 1K_0402_5%@

TABLE

CFG0 : Stall Reset Sequence

after PCU PLL Lock until de-asserted

1 : No Stall

0 : Stall

CFG4 : eDP Enable

1 : Disabled 0 : Enabled

+VCC_IO

12

+VCC_IO

12

B B

A A

5

SKYLAKE-U_BGA1356

REV = 1 @

UC1T

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

SKYLAKE-U_BGA1356

REV = 1 @

4

SKL_U LT

SPARE

RSVD_F6 RSVD_E3

RSVD_C11

RSVD_B11

RSVD_A11 RSVD_D12 RSVD_C12

RSVD_F52

F6 E3 C11 B11 A11 D12 C12 F52

??20 OF 20

??19 OF 20

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

KBL(16/16):CFG/RESERVED

Size Document Number Rev

Custom

Date: Sheet of

KENOBI

Thursday, August 25, 2016

20 82

1

20 82

2.0

5

D D

4

3

2

1

+3VALW

1 2

RC164 0_0603_5%

+3V_SPI

0.085 A

4MB(32Mb) Reserve 8MB(64Mb)

UC8M1

SPI_CS0#_8MB[11] SPI_CS1#_4MB[11]

C C

SPI_SO_8MB

SPI_IO2_8MB

1

CS#

2

DO

3

WP#

4

GND

W25Q64FVSSIQ_SO8

VCC

HOLD#

CLK

DI

8

7

6

5

+3V_SPISPI_CS0#_8MB

SPI_IO3_8MB

SPI_CLK_8MB

SPI_SI_8MB

+3V_SPI

1

CC156

0.1U_0402_10V7-K

2

SPI_CS1#_4MB SPI_SO_4MB SPI_IO2_4MB

[SKL] SP I 0_CS0#: SPI FLASH SPI 0_CS1#: SPI FLASH SPI 0_CS2#: SPI TPM

UC4M1

1

CS#

2

DO

3

WP#

4

GND

W25Q32FVSSIQ_SO8

4M@

VCC

HOLD#

CLK

8 7 6 5

DI

+3V_SPI SPI_IO3_4MB SPI_CLK_4MB SPI_SI_4MB

+3V_SPI

1

CC157

0.1U_0402_10V7-K

4M@

2

Place RC194,195,196,197 close together Place RC203,204,205,206 close together

SPI_IO3_8MB SPI_IO3 SPI_CLK_8MB SPI_SI_8MB SPI_IO2_8MB

RC194 33_0402_5%

1 2 1 2

RC195 33_0402_5% RC196 33_0402_5%

1 2 1 2

RC197 33_0402_5%

SPI_CLK SPI_SI SPI_IO2

SPI_IO3 [11]

SPI_CLK [11,58]

SPI_SI [11,58] SPI_IO2 [11]

SPI_IO3_4MB SPI_ IO3 SPI_CLK_4MB SPI_SI_4MB SPI_IO2_4MB

RC203 33_0402_5%4M@

1 2 1 2

RC204 33_0402_5%4M@ RC205 33_0402_5%4M@

1 2 1 2

RC206 33_0402_5%4M@

SPI_CLK SPI_SI SPI_IO2

Near SPI ROM

SPI_SO_8MB SPI_SO SPI_SO_4MB SPI_SO

B B

1 2

RC165 33_0402_5%

SPI_SO [11,58]

1 2

4M@

RC166 33_0402_5%

+3V_SPI

Mirror Code

RC167 0_0402_5%

FSCE#[57]

SPI_FMOSI#[57]

SPI_FMISO[57]

SPI_FSCK[57]

1 2

RC169 0_0402_5%

1 2

RC171 0_0402_5%

1 2

RC172 0_0402_5%

SPI_CS0#_8MB

SPI_SI_8MB

SPI_SO_8MB

SPI_CLK_8MB

SPI_IO2

SPI_IO3

RC168 1K_0402_5%

RC170 1K_0402_5%

RC173 1K_0402_5%@

12

1 2

Close to SPI ROM (UC8M1).

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

SPI ROM

Size Document Number Rev

Custom

Thursday, August 25, 2016

Date: Sheet of

Thursday, August 25, 2016

KENOBI

1

21 82

2.0

5

4

3

2

1

Place 10uF/1uF decoupling cap, 4 near each side of the DIMM connector close to VDD pins. 330uF placeholder

[KBL PDG]VDDQ

[KBL PDG] EE 10uF x16, 1uF x16. 330uF x1

+1.2V +2.5V

12

CD6 10U_0603_6.3V6-M

CD19 1U_0402_6.3V6-K

DDR4_DRAMRST# [8, 23] DDR_A_CKE1 [7]

DDR_A_ACT_N [7] DDR_A_ALERT_N [7]

CD18 1U_0402_6.3V6-K

DDR_A_D0

DDR_A_D4

DDR_A_D6

DDR_A_D3

DDR_A_D8

DDR_A_D13

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D11

DDR_A_D14

DDR_A_D17

DDR_A_D21

DDR_A_D22

DDR_A_D19

DDR_A_D29

DDR_A_D28

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D31

DDR_A_D27

DDR_A_ACT_N DDR_A_ALERT_N

DDR_A_MA11 DDR_A_MA7

DDR_A_MA5 DDR_A_MA4

12

CD5 10U_0603_6.3V6-M

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

12

CD4 10U_0603_6.3V6-M

CD17 1U_0402_6.3V6-K

12

CD1 10U_0603_6.3V6-M

D D

C C

B B

DDR_A_CKE0[7]

DDR_A_BG1[7] DDR_A_BG0[7]

+1.2V

DDR_A_D5

DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2

DDR_A_D7

DDR_A_D9

DDR_A_D12

DDR_A_D10

DDR_A_D15

DDR_A_D16

DDR_A_D20

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D23

DDR_A_D18

DDR_A_D25

DDR_A_D24

DDR_A_D30

DDR_A_D26

DDR_A_DQS#8 DDR_A_DQS8

DDR_A_CKE0

DDR_A_BG1 DDR_A_BG0

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA6

CD14 1U_0402_6.3V6-K

+1.2V +1.2V

12

CD2 10U_0603_6.3V6-M

CD15 1U_0402_6.3V6-K

JDIMM1A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4RB-7H

12

CD3 10U_0603_6.3V6-M

CD16 1U_0402_6.3V6-K

ME@

VSS_2

VSS_4

VSS_6

DM0_n/DBl0_n

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15 DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24 VSS_35 DQS3_c

DQS3_t

VSS_38

DQ31 VSS_40

DQ27 VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

DM8_n/DBl8_n/NC

VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

CKE1

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

DQ4

DQ0

DQ6

DQ2

DQ8

A11

A7

A5 A4

12

CD7 10U_0603_6.3V6-M

CD20 1U_0402_6.3V6-K

+3VS +3VS +3VS

12

RD6 10K_0402_5%

@

SA0_CHA_P SA1_CHA_P SA2_CHA_P

12

RD9 0_0402_5%

CD21 1U_0402_6.3V6-K

12

RD7 10K_0402_5%

@

12

RD10 0_0402_5%

12

CD8 10U_0603_6.3V6-M

1

+

@

CD26 330U_D2_2VM_R9M

2

DDR_A_D[0..63] [7]

DDR_A_MA[0..16] [7]

DDR_A_DQS#[0..7] [7]

DDR_A_DQS[0..7] [7]

DDR_A_DDRCLK0_1866M[7] DDR_A_DDRCLK0_1866M#[7]

SPD Address = 0H

+3VS

RD12

@

0_0402_5%

1 2

[KBL PDG]VDDSPD

[KBL PDG] EE 0.1uF x1, 2.2uF x1.

12

RD8 10K_0402_5%

@

12

RD11 0_0402_5%

DDR_A_DDRCLK0_1866M DDR_A_DDRCLK0_1866M#

DDR_A_PARITY[7]

DDR_A_BA1[7]

DDR_A_CS0#[7]

DDR_A_ODT0[7] DDR_A_CS1#[7]

DDR_A_ODT1[7]

CP_SMB_CLK[11,23,63]

1

CD29

0.1U_0402_10V7-K

2

Place decoupling cap on DRAM side.

[KBL PDG]VPP

[KBL PDG] EE 10uF x2, 1uF x2.

12

CD9 10U_0603_6.3V6-M

12

CD10 10U_0603_6.3V6-M

CD11 1U_0402_6.3V6-K

Place decoupling on the VTT plane close to SODIMM

[KBL PDG]VTT

+0.6VS

[KBL PDG] EE 10uF x2, 1uF x4.

12

CD22 10U_0603_6.3V6-M

DDR_A_MA3 DDR_A_MA1

DDR_A_PARITY

DDR_A_BA1

DDR_A_CS0# DDR_A_MA14

DDR_A_ODT0 DDR_A_CS1#

DDR_A_ODT1

DDR_A_D37

DDR_A_D32

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D38

DDR_A_D39

DDR_A_D40

DDR_A_D44

DDR_A_D43

DDR_A_D46

DDR_A_D49

DDR_A_D52

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50

DDR_A_D55

DDR_A_D56

DDR_A_D60

DDR_A_D59

DDR_A_D58

CP_SMB_CLK VDDSPD_1

1

2

+1.2V

CD30

2.2U_0402_6.3V6-M

12

CD23 10U_0603_6.3V6-M

+1.2V+2.5V

131 133 135 137 139 141 143

145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259

261

CD24 1U_0402_6.3V6-K

JDIMM1B

A3 A1

EVENT_n/NF VDD_9 CK0_t CK0_c VDD_11 Parity

BA1 VDD_13 CS0_n A14/WE_n VDD_15 ODT0 CS1_n VDD_17 ODT1

C0/CS2_n/NC VDD_19 C1/CS3_n/NC VSS_53 DQ37 VSS_55 DQ33 VSS_57 DQS4_c

DM4_n/DBl4_n DQS4_t VSS_60 DQ38 VSS_62 DQ34 VSS_64 DQ44 VSS_66 DQ40 VSS_68 DM5_n/DBl5_n VSS_69 DQ46 VSS_71 DQ42 VSS_73 DQ52 VSS_75 DQ49 VSS_77 DQS6_c

DM6_n/DBl6_n DQS6_t VSS_80 DQS5 VSS_82 DQ51 VSS_84 DQ61 VSS_86 DQ56 VSS_88 DM7_n/DBl7_n VSS_89 DQ62 VSS_91 DQ58 VSS_93 SCL VDDSPD VPP_1 VPP_2

GND_1

FOX_AS0A826-H4RB-7H

ME@

VDD_10

CK1_t/NF

CK1_c/NF

VDD_12

A10/AP

VDD_14

A16/RAS_n

VDD_16

A15/CAS_n

VDD_18

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t VSS_90

DQ63

VSS_92

DQ59

VSS_94

SDA

VTT

GND_2

A2

A0

BA0

A13

SA2

SA0

SA1

CD12 1U_0402_6.3V6-K

CD63 1U_0402_6.3V6-K

+1.2V +0.6VS

132 134 136 138 140 142 144

146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260

262

CD64 1U_0402_6.3V6-K

DDR_A_MA2 EVENT_n_1

DDR_A_DDRCLK1_1866M DDR_A_DDRCLK1_1866M#

DDR_A_MA0

DDR_A_MA10

DDR_A_BA0 DDR_A_MA16

DDR_A_MA15 DDR_A_MA13

M_VREF_CA_DIMMA SA2_CHA_P

DDR_A_D33

DDR_A_D36

DDR_A_D35

DDR_A_D34

DDR_A_D41

DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D42

DDR_A_D47

DDR_A_D48

DDR_A_D53

DDR_A_D54

DDR_A_D51

DDR_A_D57

DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D63

DDR_A_D62

CP_SMB_DAT SA0_CHA_P

SA1_CHA_P

RF

CD65 1U_0402_6.3V6-K

+1.2V

RD5 240_0402_1%

1 2

DDR_A_DDRCLK1_1866M [7] DDR_A_DDRCLK1_1866M# [7]

DDR_A_BA0 [7]

+1.2V

2.2U_0402_6.3V6-M

1

CD27

2

@

+1.2V

CP_SMB_DAT [11,23,63]

0.1U_0402_10V7-K

2

CD28

1

@

Place decoupling cap close to DIMM

+1.2V

12

RD1

1K_0402_1%

A A

DDR4_VREF_CA_CPU_A[7]

5

1 2

1

CD13

0.022U_0402_25V7-K

2

12

RD4

24.9_0402_1%

RD2 2_0402_1%

12

RD3

1K_0402_1%

M_VREF_CA_DIMMA

12

CD25

0.1U_0402_16V7-K

@

4

+1.2V

RD13

240_0402_1%

12

RD14 240_0402_1%

DDR_A_DQS#8

DDR_A_DQS8

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

DDR4 CH-A PRIMARY

Size Document Number Rev

Thursday, August 25, 2016

Date: Sheet of

Thursday, August 25, 2016

1

KENOBI

22 82

2.0Custom

5

4

3

2

1

Place 10uF/1uF decoupling cap, 4 near each side of the DIMM connector close to VDD pins. 330uF placeholder

[KBL PDG]VDDQ

+1.2V

[KBL PDG] EE 10uF x16, 1uF x16. 330uF x1

12

CD34 10U_0603_6.3V6-M

D D

+1.2V

CD49 1U_0402_6.3V6-K

12

CD35 10U_0603_6.3V6-M

CD50 1U_0402_6.3V6-K

12

CD36 10U_0603_6.3V6-M

CD51 1U_0402_6.3V6-K

12

CD37 10U_0603_6.3V6-M

CD52 1U_0402_6.3V6-K

12

CD38 10U_0603_6.3V6-M

CD53 1U_0402_6.3V6-K

12

CD39 10U_0603_6.3V6-M

CD54 1U_0402_6.3V6-K

12

CD55 1U_0402_6.3V6-K

CD40 10U_0603_6.3V6-M

Layout Node:

Place Close DIMMs

+1.2V +1.2V

JDIMM2A

1

DDR_B_D13

C C

B B

DDR_B_CKE0[8]

DDR_B_BG1[8] DDR_B_BG0[8]

DDR_B_D12

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10

DDR_B_D14

DDR_B_D4

DDR_B_D0

DDR_B_D6

DDR_B_D2

DDR_B_D21

DDR_B_D16

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18

DDR_B_D22

DDR_B_D29

DDR_B_D25

DDR_B_D30

DDR_B_D26

DDR_B_DQS#8 DDR_B_DQS8

DDR_B_CKE0

DDR_B_BG1 DDR_B_BG0

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA6

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

FOX_AS0A826-H4SB-7H

SP071407011

VSS_2

VSS_4

VSS_6

DM0_n/DBIO_n

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15 DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

DM2_n/DBl2_n

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24 VSS_35 DQS3_c

DQS3_t

VSS_38

DQ31 VSS_40

DQ27 VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

DBI8_n VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

CKE1

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

DQ4

DQ0

DQ6

DQ2

DQ8

ME@

A11

A7

A5 A4

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

DDR_B_D8

DDR_B_D9

DDR_B_D15

DDR_B_D11

DDR_B_D1

DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D3

DDR_B_D7

DDR_B_D20

DDR_B_D17

DDR_B_D23

DDR_B_D19

DDR_B_D28

DDR_B_D24

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D31

DDR_B_D27

DDR_B_MA11 DDR_B_MA7

DDR_B_MA5 DDR_B_MA4

+3VS

12

SPD Address = 2H

DDR4_DRAMRST# [8, 22] DDR_B_CKE1 [8]

DDR_B_ACT_N [8] DDR_B_ALERT_N [8]

RD20 10K_0402_5%

@

SA0_CHB_P SA1_CHB_P SA2_CHB_P

RD23 0_0402_5%

12

CD41 10U_0603_6.3V6-M

CD56 1U_0402_6.3V6-K

+3VS +3VS

12

RD21 10K_0402_5%

12

RD24 0_0402_5%

@

[KBL PDG]VDDSPD

[KBL PDG] EE 0.1uF x1, 2.2uF x1.

1

+

CD57 330U_D2_2VM_R9M

2

DDR_B_D[0..63] [8]

DDR_B_MA[0..16] [ 8]

DDR_B_DQS#[0..7] [8]

DDR_B_DQS[0..7] [8]

DDR_B_DDRCLK0_1866M[8] DDR_B_DDRCLK0_1866M#[8]

DDR_B_PARITY[8]

DDR_B_BA1[8]

DDR_B_CS0#[8]

DDR_B_ODT0[8] DDR_B_CS1#[8]

DDR_B_ODT1[8]

12

+3VS

@

1 2

RD22 10K_0402_5%

@

RD25 0_0402_5%

RD26 0_0402_5%

CP_SMB_CLK[11,22,63]

DDR_B_DDRCLK0_1866M DDR_B_DDRCLK0_1866M#

1

CD60

0.1U_0402_10V7-K

2

Place decoupling cap on DRAM side.

[KBL PDG]VPP

[KBL PDG] EE 10uF x2, 1uF x2.

+0.6VS

12

CD32 10U_0603_6.3V6-M

12

CD33 10U_0603_6.3V6-M

CD42 1U_0402_6.3V6-K

Place decoupling on the VTT plane close to SODIMM

+2.5V

[KBL PDG]VTT

[KBL PDG] EE 10uF x2, 1uF x4.

12

CD45 10U_0603_6.3V6-M

DDR_B_MA3 DDR_B_MA1

DDR_B_PARITY

DDR_B_BA1

DDR_B_CS0# DDR_B_MA14

DDR_B_ODT0 DDR_B_CS1#

DDR_B_ODT1

DDR_B_D37

DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34

DDR_B_D38

DDR_B_D41

DDR_B_D40

DDR_B_D43

DDR_B_D47

DDR_B_D53

DDR_B_D48

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50

DDR_B_D55

DDR_B_D60

DDR_B_D61

DDR_B_D59

DDR_B_D58

CP_SMB_CLK VDDSPD_2

+1.2V

1

CD61

2.2U_0402_6.3V6-M

2

12

CD46 10U_0603_6.3V6-M

+1.2V+2.5V

CD47 1U_0402_6.3V6-K

JDIMM2B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

FOX_AS0A826-H4SB-7H

SP071407011

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

DM6_n/DBl6_n

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

CD48 1U_0402_6.3V6-K

+1.2V +0.6VS

ME@

132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

RFU

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

Vtt

260

SA1

262

CD68 1U_0402_6.3V6-K

DDR_B_MA2 EVENT_n_2

DDR_B_DDRCLK1_1866M DDR_B_DDRCLK1_1866M#

DDR_B_MA0

DDR_B_MA10

DDR_B_BA0 DDR_B_MA16

DDR_B_MA15 DDR_B_MA13

M_VREF_CA_DIMMB SA2_CHB_P

DDR_B_D36

DDR_B_D32

DDR_B_D35

DDR_B_D39

DDR_B_D45

DDR_B_D44

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D42

DDR_B_D46

DDR_B_D52

DDR_B_D49

DDR_B_D51

DDR_B_D54

DDR_B_D56

DDR_B_D57

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62

DDR_B_D63

CP_SMB_DAT SA0_CHB_P

SA1_CHB_P

CD66 1U_0402_6.3V6-K

+1.2V

12

RD19 240_0402_1%

+1.2V

CP_SMB_DAT [11,22,63]

CD67 1U_0402_6.3V6-K

DDR_B_DDRCLK1_1866M [8] DDR_B_DDRCLK1_1866M# [8]

DDR_B_BA0 [8]

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

1

CD58

2

@

CD59

2

@

Place decoupling cap close to DIMM

+1.2V

12

RD15 1K_0402_1%

RD16 2_0402_1%

DDR4_VREF_DQ_CPU_B[7]

A A

5

1 2

1

CD43

0.022U_0402_25V7-K

2

12

RD18

24.9_0402_1%

12

RD17 1K_0402_1%

M_VREF_CA_DIMMB

12

CD44

0.1U_0402_16V7-K

@

4

+1.2V

RD27

240_0402_1%

12

RD28 240_0402_1%

DDR_B_DQS#8

DDR_B_DQS8

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE CO MPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/09/01

LC Future Center Secret Data

Deciphered Date

2

2016/12/31

Title

DDR4 CH-B PRIMARY

Size Document Number Rev

Thursday, August 25, 2016

Date: Sheet of

Thursday, August 25, 2016

1

KENOBI

23 82

2.0Custom

5

4

3

2

1

Resistor Values

4.99K

10K

D D

15K

20K

24.9K

30.1K

34.8K

45.3K

Physical Strapping pin

ROM_SCLK

ROM_SI

ROM_SO PCIE_CFG

C C

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

Power Rail

+3VS_AON

Pull-up to

+3VGS

1000

1001

1010

10 11

1100

1101

1110

1111

Logical Strapping Bit3

SOR3_EXPOSED

Pull-down to Gnd

0000

0001

0010

00 11

0100

0101

0110

0111

Logical Strapping Bit2

SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

DEVID_SEL

Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)

Reserved(keep pull-up and pull-down footprint and not stuff by default)

DEVID_SEL

0

1

(Default)

PCIE_CFG

0

1

Logical Strapping Bit1

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

(Default) 3D Device (Class Code 302h)

Logical Strapping Bit0

RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

SMBUS_ALT_ADDR

0

1

0x9E (Default)

0x9C (Multi-GPU usage)

VGA_DEVICE

0

1

VGA Device (Default)

X76

GPU STRAP4ROM_SOROM_SI

Samsung

B B

N16S-GTR

Hynix

N16V-GMR

A A

5

K4W4G1646E-BC1A(E-Die)256MX16 PD 24.9K

H5TC4G63CFR-N0C(C-Die)256Mx16 PD 30.1K

MT41J256M16LY-091G:N PD 20KMicron

4

SD03424928T

SD03430128T

SD02820028T

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PD 5K NCPU 50KPD 5K NCNC

Issued Date

2015/10/5

3

STRAP1STRAP0ROM_SCLK STRAP3

NC

LC Future Center Secret Data

STRAP2FB Memory (GDDR3)

Deciphered Date

2016/12/31

Title

VGA NOTE

Size

Document Number Rev

B

Thursday, August 25, 2016

Dat e: Sheet of

2

Dat e: Sheet of

Thursday, August 25, 2016

KENOBI

1

24 82

2.0

1

PCIE_CTX_C_GRX_N[1..4][15] PCIE_CTX_C_GRX_P[1..4][15]

PCIE_CRX_GTX_N[1..4][15] PCIE_CRX_GTX_P[1..4][15]

A A

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4

B B

DGFX_PWRGD[28,75]

VDDQPWRGD[79]

C C

CLKREQ_PCIE4_VGA#[10]

D D

DGFX_PWRGD

VDDQPWRGD

+3VS

RV922 10K_0402_5%DIS@

1

PCIE_CTX_C_GRX_N[1..4] PCIE_CTX_C_GRX_P[1..4]

PCIE_CRX_GTX_N[1..4] PCIE_CRX_GTX_P[1..4]

VGA_PEX_RST#[28]

CV8 0.22U_0402_10V6-KDIS@ CV9 0.22U_0402_10V6-KDIS@

CV10 0.22U_0402_10V6-KDIS@ CV11 0.22U_0402_10V6-KDIS@

CV12 0.22U_0402_10V6-KDIS@ CV13 0.22U_0402_10V6-KDIS@

CV21 0.22U_0402_10V6-KDIS@ CV22 0.22U_0402_10V6-KDIS@

DV1

2

3

BAT54AW_SOT323-3

DIS@

12

VDDQPWRGD

VGA_PEX_RST#

CLK_PCIE_VGA[10]

1

2

G

RV139

CLK_PCIE_VGA#[10]

+3VS_AON

1 2

DIS@

S

@

1 2 1 2

NV Suggest

+3VS_AON

1 3

D

QV1 2N7002KW_SOT323-3

1 2

RV21 10K_0402_5%

DIS@

All_GPU_PWRGD

0_0402_5%

DIS@

1 2

+3VS_AON

RV5 10K_0402_5%

DIS@

1 2

CLKREQ_VGA#

RV9 10K_0402_5%

1 2

2

RV11 0_0402_5%

CLKREQ_VGA#

CLK_PCIE_VGA CLK_PCIE_VGA#

PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1

PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1

PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2

PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2

PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3

PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

PCIE_CRX_C_GTX_P4 PCIE_CRX_C_GTX_N4

PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4

All_GPU_PWRGD [11]

@

2

+3VS_AON

12

RV19

@

10K_0402_5%

N15S-GM-A1_FCBGA595

AB6

AC7

AC6

AE8 AD8

AC9 AB9

AG6 AG7

AB10 AC10

AF7

AE7

AD11 AC11

AE9

AF9

AC12 AB12

AG9

AG10

AB13 AC13

AF10 AE10

AD14 AC14

AE12 AF12

AC15 AB15

AG12 AG13

AB16 AC16

AF13 AE13

AD17 AC17

AE15 AF15

AC18 AB18

AG15 AG16

AB19 AC19

AF16 AE16

AD20 AC20

AE18 AF18

AC21 AB21

AG18 AG19

AD23 AE23

AF19 AE19

AF24 AE24

AE21 AF21

AG24 AG25

AG21 AG22

DIS@

UV1A

COMMON

1/14 PCI_EXPRESS

PEX_WAKE*_NC

PEX_RST*

PEX_CLKREQ*

PEX_REFCLK PEX_REFCLK*

PEX_TX0 PEX_TX0*

PEX_RX0 PEX_RX0*

PEX_TX1 PEX_TX1*

PEX_RX1 PEX_RX1*

PEX_TX2 PEX_TX2*

PEX_RX2 PEX_RX2*

PEX_TX3 PEX_TX3*

PEX_RX3 PEX_RX3*

NC_AB13 NC_AC13

NC_AF10 NC_AE10

NC_AD14 NC_AC14

NC_AE12 NC_AF12

NC_AC15 NC_AB15

NC_AG12 NC_AG13

NC_AB16 NC_AC16

NC_AF13 NC_AE13

NC_AD17 NC_AC17

NC_AE15 NC_AF15

NC_AC18 NC_AB18

NC_AG15 NC_AG16

NC_AB19 NC_AC19

NC_AF16 NC_AE16

NC_AD20 NC_AC20

NC_AE18 NC_AF18

NC_AC21 NC_AB21

NC_AG18 NC_AG19

NC_AD23 NC_AE23

NC_AF19 NC_AE19

NC_AF24 NC_AE24

NC_AE21 NC_AF21

NC_AG24 NC_AG25

NC_AG21 NC_AG22

3

Under GPU

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14

NC FOR GF119

PEX_PLL_HVDD_1 PEX_PLL_HVDD_2

PEX_SVDD_3V3

NC FOR GM108NC FO R G F117/GK208/GM 108

VDD_SENSE

GND_SENSE

PEX_TSTCLK

PEX_TSTCLK*

PEX_PLLVDD_1 PEX_PLLVDD_2

TESTMODE

PEX_TERMP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

AA22 AB23 AC24 AD25 AE26 AE27

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27

AA8 AA9

AB8

F2

F1

AF22 AE22

AA14 AA15

AD9

AF25

2015/08/28

1U_0402_6.3VA-K

PEX_TSTCLK PEX_TSTCLK#

GPU_TESTMODE

GPU_PEX_TERMP

LC Future Center Secret Data

12

10K_0402_5%

1 2

RV10

Near GPU

1

CV1

2

DIS@

1

CV14

2

DIS@

4.7U_0603_6.3VA-K

Place near GPU

1

CV23

2

0.1U_0402_16V7-K

DIS@

+VGA_CORE

12

RV2

DIS@

100_0402_1%

12

RV3

DIS@

100_0402_1%

RV6

1 2

Under GPU

1

2

0.1U_0402_16V7-K

RV8

DIS@

2.49K_0402_1%

DIS@

Deciphered Date

4

Midway between GPU and power supply

1

CV3

2

DIS@

1

CV16

2

DIS@

@

CV26

DIS@

1

CV4

2

10U_0603_6.3V6-M

DIS@

1

CV18

2

10U_0603_6.3V6-M

DIS@

1

CV24

2

4.7U_0603_6.3VA-K

DIS@

GFXCORE_VDD_SENSE_D [75]

GFXCORE_GND_SENSE_D [75]

200_0402_5%

Near GPU

1

CV27

2

1U_0402_6.3VA-K

DIS@

2016/08/27

4

22U_0603_6.3V6-M

4.7U_0603_6.3VA-K

1

CV28

2

4.7U_0603_6.3VA-K

DIS@

1

CV6

2

DIS@

1

CV19

2

DIS@

+3VS_AON

1

CV25

2

DIS@

to VGA CORE Power IC sense pin

+1VS_VGA

Title

Size

Custom

Date: Sheet of

5

+1VS_VGA

NVVDD Decoupling

Capactior Type

4.7uF_0603 1uF_0402 22uF_0805 10uF_0805

N16S-GT PCIE

Document Number Rev

Thursday, August 25, 2016

GB2B-64

NV DG

Actual

1

11

KENOBI

25 82

5

25 82

2.0

Lenovo ThinkPad E470 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual