Lenovo S10-3c Schematics
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Board name: Mother Board Schematic
Project name: BM5999
Version: REV:1.3
initial Date: 2010-04-21
Bitland Electronics Co.,LTD
1. System Block Diagram & Schematic page description;
2. Power Block Diagram & Discription;
3. Annotations & information;
4. Schematic modify Item and history;
New update: 5. Power on & off Sequence;
6. ACPI Mode Switch Timings;
7. Power On Sequence Map;
8. CLOCK Distribution;
C C
9. Power Distribution;
Bitland Confidential
Hardware drawing by: Hardware check by: EMI Check by:
Power drawing by:
Power check by:
B B
Manager Sign by:
A A
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
5
4
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was obtained with the expressed written consent of Bitland
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Title
Title
Title
BM5999
BM5999
BM5999
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CONTENT
1 Title
2 System Block & Index
Bitland Confidential
3 PWR Block & description
4 NOTE
5 Sch Modify and history
Bitland Electronics Co.,LTD
D D
6 CK-505
SYSTEM BLOCK Ver:C
CK505M
Clocking
ICS365
+V3.3S
C C
10' TFT
+V3.3S;+V5S
VGA
+V5S
PCIE mini Card
WIFI
LVDS
RGB
PCIE 1X
USB1.1/2.0
B B
SIM CARD
PCIE mini Card
3G
USB PORT1
+V5AL
USB PORT2
+V5AL
BIOS
16Mbit
+V3.3AL
SPI
Pineview M
BGA559
+V3.3S,+V1.5S,
+V1.05S,+V1.8S
+0.89S
DMI
x2
Tiger Point
BGA360
+V1.05S,+V3.3S
+V3.3AL,+V5AL
+V1.5S,+V5S
+V3.3A_RTC
LPC
KB Controller/EC
ITE8512
EC_RTC
DDR3
667
PCIE X1
SATA
HDA
Thermal Sensor
G780
+V3.3S
DDR3 SODIMM1 667
+V0.75S,+V1.5,+V3.3S
10/100M
LAN
+V5S,+V3.3S
S-ATA
2.5" HHD
+V5S,+V3.3S
AZALIA
ALC662
+V5S,+V3.3S
AMP
TPA6017A
+V5S
Speaker
RJ45
MiC
Audio Jack
+V5S,+3.3S
L
R
USB PORT3
+V5AL
A A
Card Reader
RTL5159
+V3.3AL
TouchPAD
SD/MMC/MS CARD
5
4
SPI
EC ROM
512Kbit
EC_V3.3AL
KB Matrix
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
3
2
was obtained with the expressed written consent of Bitland
SYS BLOCK & SCH PAGE
SYS BLOCK & SCH PAGE
SYS BLOCK & SCH PAGE
BM5999
BM5999
BM5999
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S18 POWER BLOCK Ver:A
Charger
D D
ISL6251
Adapter
20V
+V1.8S/+V1.05S PWR
TPS51117
6A 4A
+V1.5
1A
C C
VIN
V_5
B B
V_3
2A
Battery
Power
Switch
4.5A
4.5A
Always_On
Power
TPS51125
5A
1.5A
+VDC
1.5A
4A
1.5A
3A
1.5A 1.5A
+V3.3AL+V5AL
+V1.05S
1A
+V0.75S+V1.5S
APL5331
Platform
Logic
IMVP-6
CLK_ENABLE#
IMVP6_PWRGD
Tiger point
CLK
CHIP
VR_ON
DPRSLPVR
TPS51117 TPS51117
Vss_sense
Vcc_sense
VR_TT#
Vcc_core
VID[6...0]
PSI#
DPRSTP#
DPRSTP#
CPU_PWRGD
4A
3A
+V5S
PSI#
PROCHOT#
+V3.3S
0.4A
CPU
VCC_CORE
ISL6261
+V1.8S
uP7710
4
4A
+0.89S
TPS51117
6A/6.5W
+VCC_CORE
3
POWER Distribution
Battery
AC
System
VREG
9-20V
CPU Core Regulator
IMVP-6 Compliant
VCCP,GMCH_CORE,
ICH_CORE
1.05V
DDR VCC Regulator
V1.5
DDR VTT Regulator
V0.75S
GFX CORE
+0.89S
1.5V Interface Regulator
V1.5S
5.0V Interface Regulator
V5A
3.3V Interface Regulator
V3.3A
2
4A
CPU
3A
0V-1.4625V VCC
1.05V FSB VCCP
0.25A
1.5V VCCA
4A
DDR2 SO-DIMM
0.75A
0.75V SM VTT
1.8V VDD/VDDQ
CPU
1.7A
1.5V DDR I/O
0.5A
3.3V TVDAC
1.05V FSB VTT
1.05V Core(Int)
1.05V VCC_PEG
7A
1.8V LVDS
2.5A
1.05V DMI
1.05V HSIO
PCH
1.05V VCC_CPU
1.05V Core
1.5A
1.05V DMI
1.5V PCI Express
1.5V SATA
1.5V LAN
1.5V USB
V5S
4A
V5AL
LDO
4A
V3.3S
V3.3AL
EC_RTC
3A
1A
0.1A
0.1A
0.5A
0.1A
0.5A
0.5A
0.5A
1.5A
1A
0.5A
0.5A
0.5A
0.5A
0.3A
0.25A
0.25A
1A
1A
0.5A
1.5V AZALIA
1.5V AL
5VRef
5VrefSus
3.3VBG
RTC
3.3V IDE/PCI
3.3V VccSus
1.5VSUS(IntVR)
1.05VSUS(Int/ExtVR)
USB(Each port)
V5A
SATA
V3.3S&V5S
BLUETOOTH
V3.3S
Camera
V5AL
LVDS
V3.3S,VDC or V5S
CK505-M
V3.3S
EC&SPI
EC_RTC
Azalia
V5,V3.3S
Mini-PCI Express
Each slot
+1.5V&+V3.3AL&+V3.3S
0.5A
VDC
1
0.25A
CRT
0.5A
A A
5
4
3
2
0.4A
0.25A
0.8A
V5S,V3.3S
LAN
V3.3AL
FAN
V5S
CardReader
V3.3AL
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
D
D
D
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
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Bitland Information Technology Co.,Ltd
PWR Block & description
PWR Block & description
PWR Block & description
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Voltage Rails
+VDC
D D
+VBATTERY
+VCC_CORE
+V1.05S
+V1.5
+V0.75S
+V3.3AL
+V5AL
+V3.3S
+V5S
+V0.89S 0.89V for GFX
Primary DC system power supply (9V-20V)
Battery Power supply (9-20V)
Core Voltage for CPU
1.05V for Pineview & Tiger point core / FSB VTT
1.5V power rail for DDR3
0.75V DDR3 Termination voltage
3.3V always on power rail
5V for ICH7-M's VCC5 Refsus
3.3V main power rail
5V main power rail
C C
Board stack up description
PCB Layers
Top(Signal1)
Power
Ground
Bottom(Signal4)
Trace Impedence:55ohm +/-15%
I2C SMB Address
Device
Clock Generator
SO-DIMM0
CPU Thermal Sensor
Smart Battery
PCIE Slot
Power States
Signal
S0(Full On)
S3(STM)
S4(STD)
S5(SoftOff)
SLP_S3#
HIGH
LOW
LOW OFF
Wake up Events
LID switch from EC
Power switch from EC
Address Hex
1101 001x
1010 000x
1001 100x
0001 011x
TBD
SLP_S4#
D2
A0
98
16
TBD
HIGH
HIGH ON OFF
LOW
LOW
SLP_S5#
HIGH
HIGH
HIGH
LOW
Master
ICH7-M
ICH7-M
KBC
KBC
ICH7-M
+V*ALW
ON
ON
ON
+V*
ON ON
ON
OFFLOW
+V*S
OFF
OFF
OFF
Clock
ON
OFF
OFF
B B
USB Table
USB Port#
0
Function Description
PCB Footprints
3
SOT23
12
54
SOT23_5
3
21
1
2
3
ns: Component marked "ns" is not stuff
4
5
Bitland Information Technology Co.,Ltd
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Page Name
Page Name
7
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
Bitland Information Technology Co.,Ltd
Notes & Anotation
Notes & Anotation
Notes & Anotation
BM5999
BM5999
BM5999
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Schematic modify Item and history:
D D
C C
B B
A A
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
5
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was obtained with the expressed written consent of Bitland
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Sch Modify and history
Sch Modify and history
Sch Modify and history
BM5999
BM5999
BM5999
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+V3.3S7,8,9,10,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+V3.3S
D D
C C
+V3.3S
12
FB39
FB39
NC_100ohm@100MHz,3A
NC_100ohm@100MHz,3A
FB0603
FB0603
C3101
C3101
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
+V1.05S
12
FB40
FB40
100ohm@100MHz,3A
100ohm@100MHz,3A
FB0603
FB0603
C3098
C3098
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C3102
C3102
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C3104
C3104
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C3099
C3099
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3103
C3103
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3105
C3105
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3108
C3108
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
FB38
FB38
FB0603
FB0603
100ohm@100MHz,3A
100ohm@100MHz,3A
1 2
+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK
+V3.3S
C3091
C3091
4.7UF/10V,Y5V
4.7UF/10V,Y5V
C0805
C0805
C3106
C3106
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
4
C3095
C3095
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3107
C3107
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3096
C3096
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3100
C3100
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
C3094
PCI_CLK_DEBUG22
PCI_CLK_EC25
PCI_CLK_ICH10
C3094
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3097
C3097
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
R3761 22 R0402R3761 22 R0402
R3762 22 R0402R3762 22 R0402
R3763 22 R0402R3763 22 R0402
R3764 10K R0402R3764 10K R0402
R3765 33,5% R0402R3765 33,5% R0402
R3766 33,5% R0402R3766 33,5% R0402
R3767 2.2KR0402R3767 2.2K R0402
R3768 1K,5% R0402R3768 1K,5% R0402
R3769 10K R0402R3769 10K R0402
R3770 33 R0402R3770 33 R0402
C3093
C3093
4.7UF/10V,Y5V
4.7UF/10V,Y5V
C0805
C0805
CLK_USB48_CR17
CLK_USB48_ICH10
CLK_ICH1411
0610 add 1k resistor
3
+V3.3S_CK_VDD
C3092
C3092
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
+V3.3S_CK_VDD
+V3.3S_CK_VDD
+V3.3S_CK_VDD
+V3.3S_CK_VDD
+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK
+VDDIO_CLK
TME
27M_SEL
PCIF_ITP_EN
CLK_XTAL_IN
CLK_XTAL_OUT
No more than 500 mil
+V3.3S
U509
U509
ICS365
ICS365
TSSOP64-0_5-17X8_1X1_2MM
TSSOP64-0_5-17X8_1X1_2MM
2
VDD_PCI
9
VDD_48
16
VDD_PLL3
61
VDD_REF
39
VDD_SRC
55
VDD_CPU
12
VDD_IO
20
VDD_PLL3_IO
26
VDD_SRC_IO_1
36
VDD_SRC_IO_2
45
VDD_SRC_IO_3
49
VDD_CPU_IO
1
PCI0/OE#_0/2_A
3
PCI1/OE#_1/4_A
4
PCI2/TME
5
PCI3/FSD
6
PCI4/SRC5_SEL
7
PCIF5/ITP_EN
60
XTAL_IN
59
XTAL_OUT
10
USB_48/FSA
57
FSB/TEST_MODE
62
REF0/FSC/TEST_SEL
8
VSS_PCI
11
VSS_48
15
VSS_IO
19
VSS_PLL3
52
VSS_CPU
23
VSS_SRC_1
29
VSS_SRC_2
58
VSS_REF
42
VSS_SRC3
SRC5/PCI_STOP#
SRC5#/CPU_STOP#
SRC8#/CPU2#_ITP
SRC3#/OE#_1/4_B
CK_PWRGD/PWRDWN#
2
+V3.3S 7,8,9,10,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+V1.05S 8,9,10,11,12,29,34
Remove serial resistor
swap pins for layout
48
IO_VOUT
SMB_DATA
SMB_CLK
CPU0
CPU0#
CPU1
CPU1#
SRC8/CPU2_ITP
SRC10
SRC10#
SRC11/OE#_10
SRC11#/OE#_9
SRC9
SRC9#
SRC7/OE#_8
SRC7#/OE#_6
SRC6
SRC6#
SRC4
SRC4#
SRC3/OE#_0/2_B
SRC2/SATA
SRC2#/SATA#
SRC1/SE1
SRC1#/SE2
SRC0/DOT96
SRC0#/DOT96#
SMBUS ADD:1101 001X
63
64
38
37
54
53
51
50
47
46
34
35
33
32
30
31
44
43
41
40
27
28
24
25
21
22
17
18
13
14
56
1
SMB_DATA_S 11,13
SMB_CLK_S 11,13
PM_STPPCI# 11
PM_STPCPU# 11
CLK_CPU_BCLK 8
CLK_CPU_BCLK# 8
CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_LAN 19
CLK_PCIE_LAN# 19
CLK_DMI_ICH 10
CLK_DMI_ICH# 10
CLK_PCIE_EXPCARD 22
CLK_PCIE_EXPCARD# 22
CLK_SATA_ICH 10
CLK_SATA_ICH# 10
DPL_REFSSCLKIN_DP 7
DPL_REFSSCLKIN_DN 7
CK_96M_DREF_DP 7
CK_96M_DREF_DN 7
VR_PWRGD_CLK_EN 11
B B
+V1.05S
CPU_BSEL08
CPU_BSEL18
CPU_BSEL28
A A
R3781 0 R0402R3781 0 R0402 C3112 NC_10PF/50V,NPO ns
R3783 0,5%R0402R3783 0,5%R0402
R3785 0 R0402R3785 0 R0402
5
BUS FREQUENCE SELECT
C3110
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
C3110
0.1UF/25V,Y5V
0.1UF/25V,Y5V
C0402
C0402
R3776
R3776
NC_1K,5%
NC_1K,5%
R0402
R0402
R3787
R3787
NC_1K
NC_1K
R0402
R0402
ns
ns
R3777
R3777
NC_1K
NC_1K
R0402
R0402
R3788
R3788
NC_1K
NC_1K
R0402
R0402
ns
ns
R3778
R3778
NC_1K
NC_1K
R0402
R0402
R3789
R3789
NC_1K
NC_1K
R0402
R0402
ns
ns
C3114
C3114
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
C3115
C3115
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
4
13
Y8
Y8
CLK_XTAL_IN
24
14.318180MHz
14.318180MHz
Y_5938
Y_5938
CLK_XTAL_OUT
27M_SEL
R3775
R3775
NC_10K
NC_10K
R0402
R0402
ns
ns
R3779
R3779
10K
10K
R0402
R0402
R3791
R3791
1K
1K
R0402
R0402
CK505_CLK_EN#36
3
1
R3790
R3790
10K
10K
R0402
R0402
+V3.3S
3
2
TME
Q32
Q32
2N7002
2N7002
SOT23
SOT23
R3780 10K R0402R3780 10K R0402
0:Normal mode
1:No Overclocking
VR_PWRGD_CLK_EN 11
C3116
C3116
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
2
+V3.3S
CLK_ICH14
CLK_USB48_ICH
PCI_CLK_EC
PCI_CLK_ICH
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
C3109 NC_10PF/50V,NPO ns
C3109 NC_10PF/50V,NPO ns
C0402
C0402
C3111 NC_10PF/50V,NPO ns
C3111 NC_10PF/50V,NPO ns
C0402
C0402
C3112 NC_10PF/50V,NPO ns
C0402
C0402
C3113 NC_10PF/50V,NPO ns
C3113 NC_10PF/50V,NPO ns
C0402
C0402
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
CK505M
CK505M
CK505M
BM5999
BM5999
BM5999
1
642
642
642
of
of
of
1.3
1.3
1.3
5
hexainf@hotmail.com
GRATIS - FOR FREE
4
3
2
1
+V3.3S 6,8,9,10,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+V3.3S
+V3.3S6,8,9,10,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
MA_DQS[7:0] 13
D D
PINEVIEW_M
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
EXP_CLKINN
EXP_CLKINP
RSVD_R10
RSVD_R9
RSVD_N10
RSVD_N9
RSVD_K2
RSVD_J1
RSVD_M4
RSVD_L3
XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17
RSVD_L11
RSVD_TP_AA7
RSVD_TP_AA6
RSVD_TP_R5
RSVD_TP_R6
RSVD_TP_AA21
RSVD_TP_W21
RSVD_TP_T21
RSVD_TP_V21
PINEVIEW_M
DMI
DMI
1 OF 6
1 OF 6
PINEVIEW_M
PINEVIEW_M
VGA
VGA
3 OF 6
3 OF 6
PM_EXTTS#_1/DPRSLPVR
MISC
MISC
CRT_DDC_DATA
CRT_DDC_CLK
DPL_REFCLKINP
DPL_REFCLKINN
DPL_REFSSCLKINP
DPL_REFSSCLKINN
PM_EXTTS#_0
CRT_DDC_DATA
CRT_DDC_CLK
PM_EXTTS#1
PM_EXTTS#0
DDR3_DRAM_PWROK#25
4
G2
DMI_TXP_0
G1
DMI_TXN_0
H3
DMI_TXP_1
J2
DMI_TXN_1
L10
EXP_RCOMPO
L9
EXP_ICOMPI
L8
EXP_RBIAS
N11
RSVD_TP_N11
P11
RSVD_TP_P11
K3
RSVD_K3
L2
RSVD_L2
M2
RSVD_M2
N2
RSVD_N2
M30
CRT_HSYNC
M29
CRT_VSYNC
N31
CRT_RED
P30
CRT_GREEN
P29
CRT_BLUE
N30
CRT_IRTN
L31
L30
P28
DAC_IREF
Y30
Y29
AA30
AA31
R3805 0,5% R0402R3805 0,5% R0402
K29
J30
L5
PWROK
AA3
RSTINB
W8
HPL_CLKINN
W9
HPL_CLKINP
R3810 2.2K,5% R0402R3810 2.2K,5% R0402
R3812 2.2K,5% R0402R3812 2.2K,5% R0402
R3814 NC_10K,5% R0402 nsR3814 NC_10K,5% R0402 ns
R3817 10K,5% R0402R3817 10K,5% R0402
DMI_ICH_MT_IR_0_DP
DMI_ICH_MT_IR_0_DN
DMI_ICH_MT_IR_1_DP
DMI_ICH_MT_IR_1_DN
MCH COMP0/1 SIGNALS:TIE TOGETHER AT PINS.
R3796 49.9,1%
R3796 49.9,1%
GIRCOMP
GRBIAS
R3797
R3797
Checklist is 10 ohm
CRT_HSYNC_R
CRT_VSYNC_R
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_DDC_DATA
CRT_DDC_CLK
DACREFSET
CK_96M_DREF_DP
CK_96M_DREF_DN
DPL_REFSSCLKIN_DP
DPL_REFSSCLKIN_DN
PM_EXTTS#1
PM_EXTTS#0
BUF_PLT_RST#
CLK_MCH_BCLK#
CLK_MCH_BCLK
R0402
R0402
750,1% R0402
750,1% R0402
R3798
R3798
10,5% R0402
10,5% R0402
10,5% R0402
10,5% R0402
R3799
R3799
665,1%R0402
665,1%R0402
R3803
R3803
CK_96M_DREF_DP 6
CK_96M_DREF_DN 6
DPL_REFSSCLKIN_DP 6
DPL_REFSSCLKIN_DN 6
PM_DPRSLPVR 11,36
PM_EXTTS#0 13
BUF_PLT_RST# 10,11,19,22,25
CLK_MCH_BCLK# 6
CLK_MCH_BCLK 6
+V3.3S
+V3.3AL10,11,12,14,19,20,22,23,24,25,27,30,31,33,34
R441
R441
100K,5%
100K,5%
R0402
R0402
C305
C305
0.1,X7R
0.1,X7R
C0402
C0402
placed within
500 mils from
Pineview-M pins
CRT_HSYNC 15
CRT_VSYNC 15
CRT_RED 15
CRT_GREEN 15
CRT_BLUE 15
CRT_DDC_DATA 15
CRT_DDC_CLK 15
+V1.59,13,29,30,31
R430
R430
10K,5%
10K,5%
R0402
R0402
3
1
2
DMI_ICH_MT_IR_0_DP 10
DMI_ICH_MT_IR_0_DN 10
DMI_ICH_MT_IR_1_DP 10
DMI_ICH_MT_IR_1_DN 10
Add C2 C3 for ESD
2010-4-22
IMVP_PWRGD 11,25,36
C3
C3
C2
C2
NC_0.1/10V,X7R
NC_0.1/10V,X7R
NC_0.1/10V,X7R
NC_0.1/10V,X7R
C0402
C0402
C0402
C0402
DDR3_DRAM_PWROK
Q26
Q26
2N7002
2N7002
SOT23
SOT23
C302
C302
0.1,X7R
0.1,X7R
C0402
C0402
3
U510B
MA_A_A[14:0]13
M_CLK_DDR013
M_CLK_DDR#013
M_CLK_DDR113
M_CLK_DDR#113
MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6
MA_A_A7
MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14
MA_A_WE#
MA_A_WE#13
MA_A_CAS#
MA_A_CAS#13
MA_A_RAS#
MA_A_RAS#13
MA_A_BS#0
MA_A_BS#013
MA_A_BS#1
MA_A_BS#113
MA_A_BS#2
MA_A_BS#213
M_CS#0
M_CS#013
M_CS#1
M_CS#113
M_CKE0
M_CKE013
M_CKE1
M_CKE113
M_ODT0
M_ODT013
M_ODT1
M_ODT113
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
AH19
AK18
AK16
AH14
AK14
AH13
AK12
AK20
AH12
AK22
AK21
AH20
AK11
AH22
AK25
AH10
AK10
AK24
AH26
AH24
AK27
AG15
AF15
AD13
AC13
AC15
AD15
AF13
AG13
AD17
AC17
AB15
AB17
AJ18
AJ14
AJ12
AJ11
AJ24
AJ10
AJ22
AJ20
AJ21
AJ25
AH9
AJ8
U510B
DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14
DDR_A_WEB
DDR_A_CASB
DDR_A_RASB
DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2
DDR_A_CSB_0
DDR_A_CSB_1
DDR_A_CSB_2
DDR_A_CSB_3
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3
DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3
DDR_A_CK_0
DDR_A_CKB_0
DDR_A_CK_1
DDR_A_CKB_1
DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CK_4
DDR_A_CKB_4
RSVD_AD17
RSVD_AC17
RSVD_AB15
RSVD_AB17
R431 NC_0,5% R0402R431 NC_0,5% R0402
MCH_VREF
AB11
AB13
AK28
AK29
AL28
AJ26
AB4
AK8
VSS_AB4
RSVD_AK8
RSVD_TP_AB11
RSVD_TP_AB13
DDR_VREF
DDR_RPD
DDR_RPU
RSVD_AK29
DDR3_DRAM_PWROK
+V1.59,13,29,30,31
R419 10K,5% R0402R419 10K,5% R0402
+V1.59,13,29,30,31
R418 0,5% R0402R418 0,5% R0402
R3808 80.6,1% R0402R3808 80.6,1% R0402
R3809 80.6,1% R0402R3809 80.6,1% R0402
C3121
C3121
0.1/10V,X7R
0.1/10V,X7R
C0402
C0402
MCH_DDR_RPD
MCH_DDR_RPU
DDR3_DRAMRST#13
+V1.59,13,29,30,31
R3816
R3816
1K,1%
1K,1%
R0603
R0603
MCH_VREF
R3818
R3818
1K,1%
1K,1%
R0603
R0603
C3124
C3124
0.1,X7R
0.1,X7R
C0402
C0402
PNV_22MM_REV1P10_0
PNV_22MM_REV1P10_0
U510A
U510A
1
MCH_BSEL0
1
MCH_BSEL1
1
MCH_BSEL2
XDP_RSVD_05
XDP_RSVD_09
XDP_RSVD_11
XDP_RSVD_17
F3
F2
H4
G3
N7
N6
R10
R9
N10
N9
K2
J1
M4
L3
PNV_22MM_REV1P10_0
PNV_22MM_REV1P10_0
U510C
U510C
D12
A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8
C10
D10
B11
B10
B12
C11
T60ICTP T60ICTP
T61ICTP T61ICTP
T62ICTP T62ICTP
ns
ns
NC_1K,5%
NC_1K,5%
ns
ns
NC_1K,5%
NC_1K,5%
ns
ns
DMI_MCH_IT_MR_0_DP
DMI_MCH_IT_MR_0_DN
DMI_MCH_IT_MR_1_DP
DMI_MCH_IT_MR_1_DN
R0402
R0402
R0402
R0402
DMI_ICH_IT_MR_0_DP10
DMI_ICH_IT_MR_0_DN10
DMI_ICH_IT_MR_1_DP10
DMI_ICH_IT_MR_1_DN10
CLK_MCH_3GPLL#6
CLK_MCH_3GPLL6
C C
C3118 0.1/10V,X7RC0402C3118 0.1/10V,X7RC0402
C3117 0.1/10V,X7RC0402C3117 0.1/10V,X7RC0402
C3119 0.1/10V,X7RC0402C3119 0.1/10V,X7RC0402
C3120 0.1/10V,X7RC0402C3120 0.1/10V,X7RC0402
R3800 NC_1K,5%R0402
R3800 NC_1K,5%R0402
R3801 1K,5% R0402R3801 1K,5% R0402
R3802
R3802
R3804
R3804
L11
B B
AA7
AA6
R5
R6
AA21
W21
T21
V21
PNV_22MM_REV1P10_0
PNV_22MM_REV1P10_0
CRT_RED
R3811 150,1% R0402R3811 150,1%R0402
CRT_GREEN
R3813 150,1% R0402R3813 150,1%R0402
CRT_BLUE
R3815 150,1% R0402R3815 150,1%R0402
A A
5
PINEVIEW_M
PINEVIEW_M
DDR_A_DQS_0
DDR_A_DQSB_0
DDR_A_DQS_1
DDR_A_DQSB_1
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
2 OF 6
2 OF 6
DDR_A
DDR_A
2
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQS_2
DDR_A_DQSB_2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
DDR_A_DQS_3
DDR_A_DQSB_3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQS_4
DDR_A_DQSB_4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQS_5
DDR_A_DQSB_5
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
DDR_A_DQS_6
DDR_A_DQSB_6
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
DDR_A_DQS_7
DDR_A_DQSB_7
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
MA_DQS#[7:0] 13
MA_DM[7:0] 13
MA_DATA[63:0] 13
AD3
MA_DQS0
AD2
MA_DQS#0
AD4
DDR_A_DM_0
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
DDR_A_DM_1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DM_2
DDR_A_DM_3
DDR_A_DM_4
DDR_A_DM_5
DDR_A_DM_6
DDR_A_DM_7
MA_DM0
AC4
MA_DATA0
AC1
MA_DATA1
AF4
MA_DATA2
AG2
MA_DATA3
AB2
MA_DATA4
AB3
MA_DATA5
AE2
MA_DATA6
AE3
MA_DATA7
AB8
MA_DQS1
AD7
MA_DQS#1
AA9
MA_DM1
AB6
MA_DATA8
AB7
MA_DATA9
AE5
MA_DATA10
AG5
MA_DATA11
AA5
MA_DATA12
AB5
MA_DATA13
AB9
MA_DATA14
AD6
MA_DATA15
AD8
MA_DQS2
AD10
MA_DQS#2
AE8
MA_DM2
AG8
MA_DATA16
AG7
MA_DATA17
AF10
MA_DATA18
AG11
MA_DATA19
AF7
MA_DATA20
AF8
MA_DATA21
AD11
MA_DATA22
AE10
MA_DATA23
AK5
MA_DQS3
AK3
MA_DQS#3
AJ3
MA_DM3
AH1
MA_DATA24
AJ2
MA_DATA25
AK6
MA_DATA26
AJ7
MA_DATA27
AF3
MA_DATA28
AH2
MA_DATA29
AL5
MA_DATA30
AJ6
MA_DATA31
AG22
MA_DQS4
AG21
MA_DQS#4
AD19
MA_DM4
AE19
MA_DATA32
AG19
MA_DATA33
AF22
MA_DATA34
AD22
MA_DATA35
AG17
MA_DATA36
AF19
MA_DATA37
AE21
MA_DATA38
AD21
MA_DATA39
AE26
MA_DQS5
AG27
MA_DQS#5
AJ27
MA_DM5
AE24
MA_DATA40
AG25
MA_DATA41
AD25
MA_DATA42
AD24
MA_DATA43
AC22
MA_DATA44
AG24
MA_DATA45
AD27
MA_DATA46
AE27
MA_DATA47
AE30
MA_DQS6
AF29
MA_DQS#6
AF30
MA_DM6
AG31
MA_DATA48
AG30
MA_DATA49
AD30
MA_DATA50
AD29
MA_DATA51
AJ30
MA_DATA52
AJ29
MA_DATA53
AE29
MA_DATA54
AD28
MA_DATA55
AB27
MA_DQS7
AA27
MA_DQS#7
AB26
MA_DM7
AA24
MA_DATA56
AB25
MA_DATA57
W24
MA_DATA58
W22
MA_DATA59
AB24
MA_DATA60
AB23
MA_DATA61
AA23
MA_DATA62
W27
MA_DATA63
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
Pineview-M DMI DDR VGA
Pineview-M DMI DDR VGA
Pineview-M DMI DDR VGA
BM5999
BM5999
BM5999
1
1.3
1.3
742
742
742
1.3
of
of
of
5
D D
+V3.3S 6,7,9,10,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+V1.05S 6,9,10,11,12,29,34
+V3.3S
+V3.3S6,7,9,10,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+V3.3S
R3820
R3820
R3821
R3821
2.2K,5%
2.2K,5%
2.2K,5%
2.2K,5%
R0402
R0402
R0402
R0402
L_DDC_CLK
L_DDC_DATA
C C
B B
+V1.05S
4
MCH_LVDS_CLKAN14
MCH_LVDS_CLKAP14
MCH_LVDS_YAN014
MCH_LVDS_YAP014
MCH_LVDS_YAN114
MCH_LVDS_YAP114
MCH_LVDS_YAN214
MCH_LVDS_YAP214
R0402
R0402
R3819 2.37K,1%
R3819 2.37K,1%
LVDS_BKLTEN14
L_DDC_CLK14
L_DDC_DATA14
LVDS_VDDEN14
R3843 62,5% R0402R3843 62,5% R0402
R3844 51,5% R0402R3844 51,5% R0402
R3845 51,5% R0402R3845 51,5% R0402
R3846 51,5% R0402R3846 51,5% R0402
R3847 51,5% R0402R3847 51,5% R0402
+V1.05S
MCH_LVDS_CLKAN
MCH_LVDS_CLKAP
MCH_LVDS_YAN0
MCH_LVDS_YAP0
MCH_LVDS_YAN1
MCH_LVDS_YAP1
MCH_LVDS_YAN2
MCH_LVDS_YAP2
LVD_IBG
LVDS_BKLTEN
L_DDC_CLK
L_DDC_DATA
LVDS_VDDEN
CPU_RSVD_0
H_TDI
H_TCK
H_TMS
H_TRST_N
H_THERMDA
H_THERMDC
R3854
R3854
1K,5%
1K,5%
R0402
R0402
U510D
U510D
U25
LVD_A_CLKM
U26
LVD_A_CLKP
R23
LVD_A_DATAM_0
R24
LVD_A_DATAP_0
N26
LVD_A_DATAM_1
N27
LVD_A_DATAP_1
R26
LVD_A_DATAM_2
R27
LVD_A_DATAP_2
R22
LVD_IBG
J28
LVD_VBG
N22
LVD_VREFH
N23
LVD_VREFL
L27
LBKLT_EN
L26
LBKLT_CTL
L23
LCTLA_CLK
K25
LCTLB_CLK
K23
LDDC_CLK
K24
LDDC_DATA
H26
LVDD_EN
G11
BPM_1B_0
E15
BPM_1B_1
G13
BPM_1B_2
F13
BPM_1B_3
B18
BPM_2_0#/RSVD
B20
BPM_2_1#/RSVD
C20
BPM_2_2#/RSVD
B21
BPM_2_3#/RSVD
G5
RSVD_G5
D14
TDI
D13
TDO
B14
TCK
C14
TMS
C16
TRST_B
D30
THRMDA_1
E30
THRMDC_1
C30
RSVD_C30
D31
RSVD_D31
PNV_22MM_REV1P10_0
PNV_22MM_REV1P10_0
+V3.3S
1
2 3
R3851
R3851
10K,5%
10K,5%
R0402
R0402
Q33
Q33
MMBT3904-F
MMBT3904-F
SOT23
SOT23
PINEVIEW_M
PINEVIEW_M
LVDS
LVDS
4 OF 6
4 OF 6
+V1.05S
R3855
R3855
1K,5%
1K,5%
R0402
R0402
3
E7
H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#
H_DPRSTP#
H_DPSLP#
H_INIT#
PM_THRMTRIP#
H_PWRGD
CPU_GTLREF
CLK_CPU_BCLK#
CLK_CPU_BCLK
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
EXTBGREF
C3129
C3129
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
H_SMI# 10
H_A20M# 10
H_FERR# 10
H_INTR 10
H_NMI 10
H_IGNNE# 10
H_STPCLK# 10
H_DPRSTP# 11,36
H_DPSLP# 11
H_INIT# 10
PM_THRMTRIP# 10
VR_PROCHOT#
H_PWRGD 11
CLK_CPU_BCLK# 6
CLK_CPU_BCLK 6
CPU_BSEL0 6
CPU_BSEL1 6
CPU_BSEL2 6
CPU_VID0 36
CPU_VID1 36
CPU_VID2 36
CPU_VID3 36
CPU_VID4 36
CPU_VID5 36
CPU_VID6 36
+V1.05S
R3848
R3848
976,1%
976,1%
R0402
R0402
R3849
R3849
3.32K,1%
3.32K,1%
R0402
R0402
C3126
C3126
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C3128
C3128
0.1,X7R
0.1,X7R
C0402
C0402
Voltage divider
should be
placed within
0.5” of
processor pin.
R3831
R3831
2K,1%
2K,1%
R0402
R0402
R3830
R3830
1K,1%
1K,1%
R0603
R0603
SMI_B
H7
A20M_B
H6
FERR_B
F10
LINT00
ICH
ICH
CPUPWRGOOD
CPU
CPU
LINT10
IGNNE_B
STPCLK_B
DPRSTP_B
DPSLP_B
INIT_B
PRDY_B
PREQ_B
THERMTRIP_B
PROCHOT_B
GTLREF
VSS_H27
RSVD_L6
RSVD_E17
BCLKN
BCLKP
BSEL_0
BSEL_1
BSEL_2
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
RSVD_L7
RSVD_D20
RSVD_H13
RSVD_D18
RSVD_TP_K9
RSVD_TP_D19
EXTBGREF
F11
E5
F8
G6
G10
G8
E11
F15
E13
C18
W1
A13
H27
L6
E17
H10
J10
K5
H5
K6
H30
H29
H28
G30
G29
F29
E29
L7
D20
H13
D18
K9
D19
K7
EC_PROCHOT# 25
Q34
Q34
R3856
R3856
MMBT3904-F
MMBT3904-F
1K
1K
23
SOT23
SOT23
R0402
R0402
1
+V1.05S
VR_PROCHOT#
2
H_DPRSTP#
This Daisy-Chain CMOS
topology should be routed
from Tiger Point to Intel
MVP-6, then to Pineview-M
processor (in this order
exactly).
+V1.05S
Voltage divider
should be
C3127
C3127
placed within
0.5” of
0.1,X7R
0.1,X7R
processor pin.
C0402
C0402
H_THERMDA
H_THERMDC
NOTE
1.H_THERMDA/C线宽10 MILS,
然后再包地处理
2.H_THERMDA/C
C3131
C3131
2200pF/50V,X7R
2200pF/50V,X7R
C0402
C0402
.
走线远离
R3858
R3858
10K
10K
R0402
R0402
+V3.3S
R3850
R3850
220
220
R0402
R0402
C3130
C3130
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
U511
U511
1
VDD
2
D+
3
DTHERM#4GND
TMP411,TI
TMP411,TI
并配对走线
19V及VGA
+V3.3S
0622 change to TI,TMP411
EC SMBUS ADD:1001 100X
8
SCL
7
SDA
6
ALERT#
5
R3853
R3853
10K
10K
R0402
R0402
+V3.3S
,
或高速线走线
C3132
C3132
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
1
C3133
C3133
27pF/50V,NPO
27pF/50V,NPO
C0402
C0402
I2C_CLK 25
I2C_DATA 25
A A
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
5
4
3
2
was obtained with the expressed written consent of Bitland
Pineview-M HOST LVDS
Pineview-M HOST LVDS
Pineview-M HOST LVDS
BM5999
BM5999
BM5999
1
1.3
1.3
1.3
of
of
of
842
842
842
5
hexainf@hotmail.com
GRATIS - FOR FREE
+V3.3S 6,7,8,10,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+VCC_CORE 36
+V1.05S 6,8,10,11,12,29,34
+V1.5S 12,22,29,30
+V0.89S 29,32
+V1.8S 34
D D
+V0.89S
C3135
C3135
10UF/6.3V,X5R
10UF/6.3V,X5R
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
+V1.57,13,29,30,31
10UF/6.3V,X5R
10UF/6.3V,X5R
C C
+V1.05S
C3168
C3168
10UF/6.3V,X5R
10UF/6.3V,X5R
B B
C0603
C0603
1UF/10V,X7R
1UF/10V,X7R
C3183
C3183
180mA
C3184
C3184
+V1.8S
C0603
C0603
FB 600 ohm@100MHz
1 2
+V1.05S
+V1.05S
+V1.8S
R38660,5%R0603 R38660,5%R0603
1UF/10V,X7R
1UF/10V,X7R
+V3.3S6,7,8,10,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
1.38A
C0805
C0805
C3146
C3146
C3136
C3136
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C3151
C3151
C3139
C3139
1UF/10V,X7R
1UF/10V,X7R
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C0603
C0603
2.27A
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
C3156
C3156
C3155
C3155
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
2.2UF/10V,X7R
2.2UF/10V,X7R
10UF/6.3V,X5R
10UF/6.3V,X5R
C3165
C3165
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
1.32A
C3169
C3169
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C0805
C0805
1UF/10V,X7R
1UF/10V,X7R
+V1.05S
FB42
FB42
FB0603
FB0603
154mA
600ohm@100MHz,500mA
600ohm@100MHz,500mA
C3185
C3185
C0603
C0603
1UF/10V,X7R
1UF/10V,X7R
330mA
1UF/10V,X7R
1UF/10V,X7R
C3188
C3188
C0603
C0603
1UF/10V,X7R
1UF/10V,X7R
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C0805
C0805
C0805
C0805
C0805
C0805
+VCCA_VCCD
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C0603
C0603
C31740.1uF/10V,X7R
C31740.1uF/10V,X7R
C0402
C0402
R0603
R0603
+VCCSFR_AB_DPL
+VCCACRTDAC_M
+V3.3S
+V1.05S
+VCC_RING
+VCC_LGI_VID
C3189
C3189
C0603
C0603
C3147
C3147
C3152
C3152
C3157
C3157
C3159
C3159
C3166
C3166
C3170
C3170
C3172
C3172
R38640,5%
R38640,5%
+V3.3S
C3148
C3148
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C3140
C3140
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
+VCC_DDR
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
C3158
C3158
C0805
C0805
C3160
C3160
2.2UF/10V,X7R
2.2UF/10V,X7R
+VCCCK_DDR
C3167
C3167
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C0805
C0805
C3171
C3171
2.2UF/10V,X7R
2.2UF/10V,X7R
C3173
C3173
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C3176
C3176
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3178
C3178
VCCD_HMPL
6mA
1UF/10V,X7R
1UF/10V,X7R
C3190
C3190
C0603
C0603
4
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C0603
C0603
1UF/10V,X7R
1UF/10V,X7R
U510E
U510E
T13
VCCGFX_T13
T14
VCCGFX_T14
T16
VCCGFX_T16
T18
VCCGFX_T18
T19
VCCGFX_T19
V13
VCCGFX_V13
V19
VCCGFX_V19
W14
VCCGFX_W14
W16
VCCGFX_W16
W18
VCCGFX_W18
W19
VCCGFX_W19
AK13
VCCSM_AK13
AK19
VCCSM_AK19
AK9
VCCSM_AK9
AL11
VCCSM_AL11
AL16
VCCSM_AL16
AL21
VCCSM_AL21
AL25
VCCSM_AL25
AK7
VCCCK_DDR_AK7
AL7
VCCCK_DDR_AL7
U10
VCCA_DDR_U10
U5
VCCA_DDR_U5
U6
VCCA_DDR_U6
U7
VCCA_DDR_U7
U8
VCCA_DDR_U8
U9
VCCA_DDR_U9
V2
VCCA_DDR_V2
V3
VCCA_DDR_V3
V4
VCCA_DDR_V4
W10
VCCA_DDR_W10
W11
VCCA_DDR_W11
AA10
VCCACK_DDR_AA10
AA11
VCCACK_DDR_AA11
AA19
VCCD_AB_DPL
V11
VCCD_HMPLL
AC31
VCCSFR_AB_DPL
T30
VCCACRTDAC
T31
VCC_GIO
J31
VCCRING_EAST
C3
VCCRING_WEST_C3
B2
VCCRING_WEST_B2
C2
VCCRING_WEST_C2
A21
VCC_LGI_VID
C3191
C3191
PNV_22MM_REV1P10_0
PNV_22MM_REV1P10_0
GFX/MCH
GFX/MCH
DDR
DDR
PINEVIEW_M
PINEVIEW_M
EXP\CRT\PLL
EXP\CRT\PLL
5 OF 6
5 OF 6
POWER
POWER
DMI
DMI
VCC_A23
VCC_A25
VCC_A27
VCC_B23
VCC_B24
VCC_B25
VCC_B26
VCC_B27
VCC_C24
VCC_C26
VCC_D23
VCC_D24
VCC_D26
VCC_D28
CPU
CPU
VCC_E22
VCC_E24
VCC_E27
VCC_F21
VCC_F22
VCC_F25
VCC_G19
VCC_G21
VCC_G24
VCC_H17
VCC_H19
VCC_H22
VCC_H24
VCC_J17
VCC_J19
VCC_J21
VCC_J22
VCC_K15
VCC_K17
VCC_K21
VCC_L14
VCC_L16
VCC_L19
VCC_L21
VCC_N14
VCC_N16
VCC_N19
VCC_N21
VCCSENSE
VSSSENSE
VCCA
VCCP_D4
VCCP_B4
VCCP_B3
VCCALVD
VCCDLVD
LVDS
LVDS
VCCA_DMI_T1
VCCA_DMI_T2
VCCA_DMI_T3
RSVD_P2
VCCSFR_DMIHMPLL
VCCP_E2
3
+VCC_CORE
A23
3.5A
A25
A27
1UF/10V,X7R
1UF/10V,X7R
B23
B24
C0603
C0603
B25
B26
B27
C24
C26
D23
D24
D26
D28
C0805
C0805
E22
10UF/6.3V,X5R
10UF/6.3V,X5R
E24
E27
F21
F22
F25
G19
G21
G24
C0805
C0805
H17
10UF/6.3V,X5R
10UF/6.3V,X5R
H19
H22
H24
J17
J19
J21
J22
K15
C0805
C0805
K17
10UF/6.3V,X5R
10UF/6.3V,X5R
K21
L14
ns
ns
L16
L19
L21
N14
N16
N19
N21
Layout Note: VCCSENSE
and VSSSENSE lines
should be of equal
length
Route VCCSENSE and VSSSENSE
traces at 27.4 Ohms with 50
mil spacing
C29
B29
Y2
D4
B4
B3
0610 add
0.1UF/50V,X7R
0.1UF/50V,X7R
V30
W31
T1
T2
T3
P2
AA1
E2
C3179
C3179
C3180
C3180
10UF/6.3V,X5R
10UF/6.3V,X5R
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
0.1UF/50V,X7R
0.1UF/50V,X7R
C3177
C3177
0.1/10V,X7R
0.1/10V,X7R
C0402
C0402
1 2
C0402
C0402
C0805
C0805
+VCCA_DMI
C3186
C3186
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
+VCCSFR_DMIHMPLL
C3192
C3192
C0603
C0603
C3144
C3144
C3143
C3143
C0603
C0603
1UF/10V,X7R
1UF/10V,X7R
10UF/6.3V,X5R
10UF/6.3V,X5R
C3149
C3149
C3150
C3150
C0805
C0805
10UF/6.3V,X5R
10UF/6.3V,X5R
C3141
C3141
C3153
C3153
C0805
C0805
10UF/6.3V,X5R
10UF/6.3V,X5R
C3161
C3161
C3162
C3162
C0805
C0805
ns
ns
600ohm@100MHz,500mA
600ohm@100MHz,500mA
FB41
FB41
FB0603
FB0603
C3182
C3182
C3187
C3187
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C0603
C0603
C3193
C3193
2.2UF/10V,Y5V
2.2UF/10V,Y5V
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C0805
C0805
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
10UF/6.3V,X5R
10UF/6.3V,X5R
ns
ns
80mA
0.01UF/50V,X7R
0.01UF/50V,X7R
C0402
C0402
+V1.05S
+V1.05S
60mA
C3181
C3181
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
480mA
104mA
+V1.05S
ns
ns
C3145
C3145
C0603
C0603
1UF/10V,X7R
1UF/10V,X7R
10UF/6.3V,X5R
10UF/6.3V,X5R
C3137
C3137
C0805
C0805
10UF/6.3V,X5R
10UF/6.3V,X5R
C3154
C3154
C0805
C0805
10UF/6.3V,X5R
10UF/6.3V,X5R
C3163
C3163
C0805
C0805
ns
ns
R3861
R3861
0,5%
0,5%
C3175
C3175
R3865
R3865
0,5%
0,5%
R3868
0,5%
0,5%
R3871 0,5%R0603R3871 0,5%R0603
C3194
C3194
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C3134
C3134
C3138
C3138
C3142
C3142
C3164
C3164
R0402
R0402
R0603
R0603
R0603R3868
R0603
Layout Note: Route VCCSENSE &
VSSSENSE traces at 27.4 Ohms
with 25 mil spacing to other
signals. Place PU and PD within
2 inch of CPU.
Outer width=13 mil spacing=7 mil
Inner width=13 mil spacing=7 mil
Length match < 25 mil
+VCC_CORE
R3860
R3860
100,5%
100,5%
R0402
R0402
VCCSENSE 36
R3862
R3862
100,5%
100,5%
R0402
R0402
VSSSENSE 36
+V1.5S
+V1.8S
+V1.05S
+V1.8S
2
PINEVIEW_M
PINEVIEW_M
U510F
U510F
A11
VSS_A11
A16
VSS_A16
A19
VSS_A19
A29
RSVD_NCTF_A29
A3
RSVD_NCTF_A3
A30
RSVD_NCTF_A30
A4
RSVD_NCTF_A4
AA13
VSS_AA13
AA14
VSS_AA14
AA16
VSS_AA16
AA18
VSS_AA18
AA2
VSS_AA2
AA22
VSS_AA22
AA25
VSS_AA25
AA26
VSS_AA26
AA29
VSS_AA29
AA8
VSS_AA8
AB19
VSS_AB19
AB21
VSS_AB21
AB28
VSS_AB28
AB29
VSS_AB29
AB30
VSS_AB30
AC10
VSS_AC10
GND
AC11
AC19
AC21
AC28
AC30
AD26
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10
AH18
AH23
AH28
AJ16
AJ31
AK23
AK30
AK31
AL13
AL19
AL23
AL29
AL30
AC2
AD5
AE1
AG3
AH4
AH6
AH8
AJ1
AK1
AK2
AL2
AL3
AL9
B13
B16
B19
B22
B30
B31
B5
B9
C1
C12
C21
C22
C25
C31
D22
E1
E10
E19
E21
E25
E8
F17
F19
GND
VSS_AC11
6 OF 6
6 OF 6
VSS_AC19
VSS_AC2
VSS_AC21
VSS_AC28
VSS_AC30
VSS_AD26
VSS_AD5
VSS_AE1
VSS_AE11
VSS_AE13
VSS_AE15
VSS_AE17
VSS_AE22
VSS_AE31
VSS_AF11
VSS_AF17
VSS_AF21
VSS_AF24
VSS_AF28
VSS_AG10
VSS_AG3
VSS_AH18
VSS_AH23
VSS_AH28
VSS_AH4
VSS_AH6
VSS_AH8
RSVD_NCTF_AJ1
VSS_AJ16
VSS_AJ31
RSVD_NCTF_AK1
RSVD_NCTF_AK2
VSS_AK23
RSVD_NCTF_AK30
RSVD_NCTF_AK31
VSS_AL13
VSS_AL19
RSVD_NCTF_AL2
VSS_AL23
RSVD_NCTF_AL29
RSVD_NCTF_AL3
RSVD_NCTF_AL30
VSS_AL9
VSS_B13
VSS_B16
VSS_B19
VSS_B22
RSVD_NCTF_B30
RSVD_NCTF_B31
VSS_B5
VSS_B9
RSVD_NCTF_C1
VSS_C12
VSS_C21
VSS_C22
VSS_C25
RSVD_NCTF_C31
VSS_D22
RSVD_NCTF_E1
VSS_E10
VSS_E19
VSS_E21
VSS_E25
VSS_E8
VSS_F17
VSS_F19
PNV_22MM_REV1P10_0
PNV_22MM_REV1P10_0
VSS_F24
VSS_F28
VSS_F4
VSS_G15
VSS_G17
VSS_G22
VSS_G27
VSS_G31
VSS_H11
VSS_H15
VSS_H2
VSS_H21
VSS_H25
VSS_H8
VSS_J11
VSS_J13
VSS_J15
VSS_J4
VSS_K11
VSS_K13
VSS_K19
VSS_K26
VSS_K27
VSS_K28
VSS_K30
VSS_K4
VSS_K8
VSS_L1
VSS_L13
VSS_L18
VSS_L22
VSS_L24
VSS_L25
VSS_L29
VSS_M28
VSS_M3
VSS_N1
VSS_N13
VSS_N18
VSS_N24
VSS_N25
VSS_N28
VSS_N4
VSS_N5
VSS_N8
VSS_P13
VSS_P14
VSS_P16
VSS_P18
VSS_P19
VSS_P21
VSS_P3
VSS_P4
VSS_R25
VSS_R7
VSS_R8
VSS_T11
VSS_U22
VSS_U23
VSS_U24
VSS_U27
VSS_V14
VSS_V16
VSS_V18
VSS_V28
VSS_V29
VSS_W13
VSS_W2
VSS_W23
VSS_W25
VSS_W26
VSS_W28
VSS_W30
VSS_W4
VSS_W5
VSS_W6
VSS_W7
VSS_Y28
VSS_Y3
VSS_Y4
VSS_T29
1
F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4
T29
A A
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
5
4
3
2
was obtained with the expressed written consent of Bitland
Pineview-M POWER GND
Pineview-M POWER GND
Pineview-M POWER GND
BM5999
BM5999
BM5999
1
1.3
1.3
942
942
942
1.3
of
of
of
5
+V3.3AL 7,11,12,14,19,20,22,23,24,25,27,30,31,33,34
+V3.3S 6,7,8,9,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+V1.5S_PCIE_ICH 12
+V1.05S 6,8,9,11,12,29,34
U512A
U512A
A5
PAR
B15
PCI_DEVSEL#
T67ICTP T67ICTP
PCI_CLK_ICH
1
PCIRST#
PCI_IRDY#
PCI_SERR#
PCI_STOP#
PCI_LOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#
GNT2#
PCI_REQ#0
PCI_REQ#1
STRAP1#
STRAP2#
TPT_GPIO22_PU
ICH_GPIO1
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
STRAP0#
TPT_K9_RSVD_PU
TPT_M13_RSVD_PU
R3874 8.2K,5%R0402R3874 8.2K,5%R0402
R3875 0,5% R0402R3875 0,5% R0402
R3877 10K,5%R0402R3877 10K,5%R0402
R3878 8.2K,5%R0402R3878 8.2K,5%R0402
STRAP0#:This signal has a weak
internal pull-up
STRAP0#
If the signal is sampled low, this
indicates that the system is
strapped to the “top-block swap”
mode (Tiger Point inverts A16 for
all cycles targeting FWH BIOS space)
STRAP1#/STRAP2#:Signals have weak
internal pull-ups
1
STRAP1#
STRAP2#/GPIO[17] is MSB,
STRAP1#/GPIO[48] is LSB
STRAP2#
01-SPI
10-PCI
11-LPC
GNT2#:This signal has a weak
1
GNT2#
internal pull-up
This signal should not be pulled low.
PCI_CLK_ICH6
D D
+V3.3S
EC_RUNTIME_SCI#11,25
R3880
R3880
NC_1K,5%
NC_1K,5%
ns
ns
+V3.3S
R0402
R0402
T68ICTP T68ICTP
C C
R3881 1K,5% R0402R3881 1K,5% R0402
T69ICTP T69ICTP
B B
A A
5
DEVSEL#
J12
PCICLK
A23
PCIRST#
B7
IRDY#
C22
PME#
B11
SERR#
F14
STOP#
A8
PLOCK#
A10
TRDY#
D10
PERR#
A16
FRAME#
A18
GNT1#
E16
GNT2#
G16
REQ1#
A20
REQ2#
G14
GPIO48/ STRAP1#
A2
GPIO17/ STRAP2#
C15
GPIO22
C9
GPIO1
B2
PIRQA#
D7
PIRQB#
B3
PIRQC#
H10
PIRQD#
E8
PIRQE#/GPIO2
D6
PIRQF#/GPIO3
H8
PIRQG#/GPIO4
F8
PIRQH#/GPIO5
D11
STRAP0#
K9
RSVD01
M13
RSVD02
TGP_0
TGP_0
TGP
TGP
PCI
PCI
PCI_DEVSEL#
PCI_FRAME#
PCI_STOP#
PCI_REQ#1
INT_PIRQA#
INT_PIRQC#
INT_PIRQF#
INT_PIRQH#
INT_PIRQD#
PCI_TRDY#
PCI_PERR#
PCI_SERR#
INT_PIRQB#
PCI_IRDY#
INT_PIRQG#
INT_PIRQE#
PCI_LOCK#
PCI_REQ#0
4
RN34
RN8-0402_5938RN34
RN8-0402_5938
1 2
3 4
5 6
7 8
RN35
RN8-0402_5938RN35
RN8-0402_5938
1 2
3 4
5 6
7 8
RN36
RN8-0402_5938RN36
RN8-0402_5938
1 2
3 4
5 6
7 8
RN37
RN8-0402_5938RN37
RN8-0402_5938
1 2
3 4
5 6
7 8
R3883 8.2K,5%R0402R3883 8.2K,5%R0402
R3882 8.2K,5%R0402R3882 8.2K,5%R0402
4
C/BE0#
C/BE1#
C/BE2#
C/BE3#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
1
1
8.2K,5%
8.2K,5%
8.2K,5%
8.2K,5%
8.2K,5%
8.2K,5%
8.2K,5%
8.2K,5%
+V3.3S
3
+V3.3S
+V3.3S6,7,8,9,11,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
TGP
U512B
R3867
R3867
330ohm,5%
330ohm,5%
R0402
R0402
AE20
AD17
AC15
AD18
AA10
AA12
AD15
AE21
AE18
AD19
AC17
AB13
AC13
AB15
AB16
AE24
AE23
AA14
AD16
AB11
AB10
AD23
R23
R24
P21
P20
T21
T20
T24
T25
T19
T18
U23
U24
V21
V20
V24
V23
K21
K22
J23
J24
M18
M19
K24
K25
L23
L24
L22
M21
P17
P18
N25
N24
H24
J22
W23
W24
R12
Y12
Y10
W10
V12
U12
Y14
V14
U512B
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
DMI_ZCOMP
DMI_IRCOMP
DMI_CLKN
DMI_CLKP
TGP_0
TGP_0
U512C
U512C
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
GPIO36
TGP_0
TGP_0
2
2N7002
2N7002
SOT23
SOT23
B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1
H16
M15
C13
L16
DMI_ICH_MT_IR_0_DN7
DMI_ICH_MT_IR_0_DP7
DMI_ICH_IT_MR_0_DN7
DMI_ICH_IT_MR_0_DP7
DMI_ICH_MT_IR_1_DN7
DMI_ICH_MT_IR_1_DP7
DMI_ICH_IT_MR_1_DN7
DMI_ICH_IT_MR_1_DP7
PCIE_RXN0_LAN19
PCIE_RXP0_LAN19
PCIE_TXN0_LAN19
PCIE_TXP0_LAN19
PCIE_RXN1_SLOT22
PCIE_RXP1_SLOT22
PCIE_TXN1_SLOT22
PCIE_TXP1_SLOT22
+V1.5S_PCIE_ICH
CLK_DMI_ICH#6
CLK_DMI_ICH6
+V3.3S
R3888
R0402R3888
R0402
10K,5%
10K,5%
C3195 0.1,X7RC0402C3195 0.1,X7RC0402
C3196 0.1,X7RC0402C3196 0.1,X7RC0402
C3197 0.1,X7RC0402C3197 0.1,X7RC0402
C3198 0.1,X7RC0402C3198 0.1,X7RC0402
R3879
R0402R3879
R0402
DMI_IRCOMP_R
24.9,1%
24.9,1%
CLK_DMI_ICH#
CLK_DMI_ICH
C3199
C3199
0.1U,X7R
0.1U,X7R
C0402
C0402
DBGSTRP_SET_UP H_NMI
+V1.05S
1
SOT23
SOT23
THERMTRIP#
2 3
Q37MMBT3904-F
Q37MMBT3904-F
1
TGP
DMI
DMI
USB
USB
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
PCI-E
PCI-E
TGP
TGP
Q24
Q24
3
USBRBIAS
USBRBIAS#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA
SATA
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
SATALED#
A20GATE
CPUSLP#
INIT3_3V#
HOST
HOST
SERIRQ
STPCLK#
THERMTRIP#
R3869
R3869
0R,5%
0R,5%
R0402
R0402
R3870
R3870
0R,5%
0R,5%
R0402
R0402
BUF_PLT_RST#7,11,19,22,25
3
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
A20M#
IGNNE#
INIT#
INTR
FERR#
RCIN#
SMI#
3
3
OC0#
OC1#
OC2#
OC3#
OC4#
CLK48
2
2
NMI
H7
H6
H3
H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2
D4
C5
D3
D2
E5
E6
C2
C3
G2
G3
F4
AE6
SATA_RXN0
AD6
SATA_RXP0
AC7
AD7
AE8
AD8
AD9
AC9
AD4
AC4
AD11
AC11
AD25
U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20
EC_RST# 25
2
USB_RBIAS_PN
R3876 22.6,1%
R3876 22.6,1%
CLK_USB48_ICH
R3962
C3200 0.01UF/25V,X7RC0402 C3200 0.01UF/25V,X7RC0402
C3201 0.01UF/25V,X7RC0402 C3201 0.01UF/25V,X7RC0402
R3960
R3961
within 500 mils
of the ICH7-M
CLK_SATA_ICH#
CLK_SATA_ICH
SATARBIAS_ICH
R3885 10K,5%
R3885 10K,5%
H_A20GATE
H_A20M#
H_CPUSLP_N
H_IGNNE#
H_INIT#
H_INTR
H_FERR#
H_RCIN#
INT_SERIRQ
H_SMI#
H_STPCLK#
THERMTRIP#
FORCE_OFF# 33
2
USB_PORT_PN0 20
USB_PORT_PP0 20
USB_PORT_PN1 20
USB_PORT_PP1 20
MINICARD_USB_PN2 23
MINICARD_USB_PP2 23
MINICARD_USB_PN3 22
MINICARD_USB_PP3 22
USB_CR_PN4 17
USB_CR_PP4 17
USB_PORT_PN5 24
USB_PORT_PP5 24
USB_BT_PN6 21
USB_BT_PP6 21
USB_CAM_PN7 14
USB_CAM_PP7 14
USB_OC13# 20
R0402
R0402
R3873
R3873
10K,5%
10K,5%
USB_OC7# 24
R0402
R0402
R0402R3962
R0402
NC_3.3,1%
NC_3.3,1%
R0402nsR3960
R0402ns
NC_1K,5%
NC_1K,5%
R0402nsR3961
R0402ns
NC_1K,5%
NC_1K,5%
R0402
R0402
R3884 24.9,1%
R3884 24.9,1%
R0402
R0402
H_A20GATE 25
H_A20M# 8
1
T71 ICTPT71 ICTP
H_IGNNE# 8
H_INIT# 8
H_INTR 8
H_NMI 8
H_RCIN# 25
H_SMI# 8
H_STPCLK# 8
R3889 0,5% R0402R3889 0,5% R0402
atom 24.9%
+V3.3AL
CLK_USB48_ICH 6
C3272
C3272
NC_22P,X7R
NC_22P,X7R
C0402
C0402
SATA_RXN0 16
SATA_RXP0 16
SATA_TXN0 16
SATA_TXP0 16
CLK_SATA_ICH# 6
CLK_SATA_ICH 6
HDD_LED# 20
+V3.3S
+V1.05S
+V1.05S
1
+V3.3AL
R1
R1
10K,5%
10K,5%
R0402
R0402
MINI PCIE2 SLOT USB PORT
USB PORT1
BLUE TOOTH
USB PORT2
CARD READER
MINI PCIE1 SLOT USB PORT
CAMERA
USB PORT3
SATALED#:This signal has a weak internal pull-up
This signal should not be pulled low.
H_FERR# 8
+V3.3S
R3887
R3887
8.2K,5%
8.2K,5%
R0402
R0402
INT_SERIRQ 25
R3886
R3886
56,5%
56,5%
R0402
R0402
PM_THRMTRIP# 8
R3890
R3890
56,5%
56,5%
R0402
R0402
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
Tiger Piont PCI DMI USB HOST
Tiger Piont PCI DMI USB HOST
Tiger Piont PCI DMI USB HOST
BM5999
BM5999
BM5999
1
R2
R2
10K,5%
10K,5%
R0402
R0402
10 42
10 42
10 42
of
of
of
1.3
1.3
1.3
5
hexainf@hotmail.com
GRATIS - FOR FREE
4
3
2
1
+V3.3S
+V3.3S6,7,8,9,10,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
D D
+V3.3AL
R3900
R3900
2.2K,5%
2.2K,5%
R0402
R0402
SMB_DATA
SMB_CLK
C C
XS4_8038
XS4_8038
3
2
NC_32.7680KHZ
NC_32.7680KHZ
Y10
Y10
Co_lay Crystal 2010-4-17
C3202
C3202
22PF/50V,NPO
22PF/50V,NPO
4
1
22PF/50V,NPO
22PF/50V,NPO
RTCX1
RTCX2
C3203
C3203
C3204
C3204
22PF/50V,NPO
22PF/50V,NPO
HDA_BITCLK
HDA_SYNC
HDA_RST#
Q36
Q36
2N7002
2N7002
3
EC_RTC
3
RTCBAT1
RTCBAT1
1
R3929 1K,5% R0402R3929 1K,5% R0402
3
1
2
2
4
CONN2_R
CONN2_R
4
B B
ICH_EC_RTC
R3936
R3936
332K,1%
332K,1%
R0402
R0402
ICH_INTVRMEN
INTVRMEN:Need external pull-up
to 33o k via VccRTC
This signal enables the internal
VccSus1_5 suspend regulator when
connected to VccRTC. When
connected to GND, the internal
regulator is disabled
+V3.3S
R3901
R3901
R3902
R3902
R3903
2.2K,5%
2.2K,5%
R0402
R0402
2
Q35
Q35
2N7002
2N7002
15PF/50V,NPO
15PF/50V,NPO
15PF/50V,NPO
15PF/50V,NPO
ICH_EC_RTC
3
C3207
C3207
R3903
2.2K,5%
2.2K,5%
R0402
R0402
SMB_DATA_S 6,13
SMB_CLK_S 6,13
NC_10K,5%
NC_10K,5%
LPC_AD022,25
LPC_AD122,25
LPC_AD222,25
LPC_AD322,25
LPC_FRAME#22,25
HDA_BITCLK18
HDA_RST#18
HDA_SDATA_IN018
C3205
C3205
3
Y5
2
32.7680KHZY532.7680KHZ
1 4
C3206
C3206
R3928 20K,5%R0402R3928 20K,5%R0402
R3930
R3930
1M,5%
1M,5%
R0402
R0402
SM_INTRUDER#
An RC delay circuit with a
time delay in the range of
18 ms to 25 ms should be
provided.
HDA_SDOUT:This signal has a weak internal pull-down
PCI Express* Port Config bit 1
HDA_SYNC:This signal has a weak internal pull-down
PCI Express* Port Config bit 0
11 = 1 x4, Port 1 (x4)
10 = Reserved
01 = Reserved
00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3
(x1), Port 4 (x1)
These bits live in the resume well and are
only reset by RSMRST#.
HDA_SDOUT18
HDA_SYNC18
CLK_ICH146
NC_22PF/50V,NPO
NC_22PF/50V,NPO
C3209
C3209
C3208
C3208
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
R3913 33,5% R0402R3913 33,5% R0402
R3914 33,5% R0402R3914 33,5% R0402
R3918 33,5% R0402R3918 33,5% R0402
R3919 33,5% R0402R3919 33,5% R0402
R3926
NC_3.3,5%
NC_3.3,5%
R3927
R3927
10M,5%
10M,5%
R0402
R0402
12
J24
J24
RESISTOR_1
RESISTOR_1
NS
NS
T74ICTP T74ICTP
+V3.3S
R3907
R3907
R0402
R0402
ns
ns
R0402R3926
R0402
SMB_ALERT#
SMB_CLK
SMB_DATA
SMB_LINK_ALERT#
SMLINK0
SMLINK1
ICH_SPI_DATAIN
ICH_SPI_DATAOUT
ICH_SPI_CS#
ICH_SPI_CLK
1
SPI_ARB
R3908
R3908
NC_10K,5%
NC_10K,5%
R0402
R0402
ns
ns
ICH_GPIO23
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LDRQ0#
LPC_FRAME#
HDA_BIT_CLK
HDA_TGP_RST#
HDA_SDATA_IN0
HDA_TGP_SDOUT
HDA_TGP_SYNC
CLK_ICH14
RTCX1
RTCX2
RTC_RST#
2.2K,5%
2.2K,5%
R0402
R0402
3
1
2
1
+V3.3S
1
D95
D95
BAT54C
BAT54C
2
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
ICH_EC_RTC 12
+V3.3AL 7,10,12,14,19,20,22,23,24,25,27,30,31,33,34
+V3.3S 6,7,8,9,10,12,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+V5S 12,14,15,16,18,20,21,29,30,36
+V1.05S 6,8,9,10,12,29,34
TGP
U512D
U512D
AA5
LDRQ1#/GPIO23
V6
LAD0/FWH0
AA6
LAD1/FWH1
Y5
LAD2/FWH2
W8
LAD3/FWH3
Y8
LDRQ0#
Y4
LFRAME#
P6
HDA_BIT_CLK
U2
HDA_RST#
W2
HDA_SDIN0
V2
HDA_SDIN1
P8
HDA_SDIN2
AA1
HDA_SDOUT
Y1
HDA_SYNC
AA3
CLK14
U3
EE_CS
AE2
EE_DIN
T6
EE_DOUT
V3
EE_SHCLK
T4
LAN_CLK
P7
LANR_STSYNC
B23
LAN_RST#
AA2
LAN_RXD0
AD1
LAN_RXD1
AC2
LAN_RXD2
W3
LAN_TXD0
T7
LAN_TXD1
U4
LAN_TXD2
W4
RTCX1
V5
RTCX2
T5
RTCRST#
E20
SMBALERT#/GPIO11
H18
SMBCLK
E23
SMBDATA
H21
SMLALERT#
F25
SMLINK0
F24
SMLINK1
R2
SPI_MISO
T1
SPI_MOSI
M8
SPI_CS#
P9
SPI_CLK
R4
SPI_ARB
TGP_0
TGP_0
TGP
LPC AUDIO LAN
LPC AUDIO LAN
EPROM
EPROM
BM_BUSY#/GPIO0
CPUPWRGD/GPIO49
MISC
MISC
SUS_STAT#/LPCPD#
RTC SMB SPI
RTC SMB SPI
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
DPRSLPVR
STP_PCI#
STP_CPU#
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
CLKRUN#
GPIO33
GPIO34
GPIO38
GPIO39
THRM#
VRMPWRGD
MCH_SYNC#
PWRBTN#
SUSCLK
SYS_RESET#
PLTRSTB
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SPKR
SLP_S3#
SLP_S4#
SLP_S5#
BATLOW#
DPRSTP#
DPSLP#
RSVD31
AC_SPKR
SPKR:The signal has a weak internal pull-down
If the signal is sampled high, this indicates
that the system is strapped to the “No
Reboot” mode (Tiger Point chipset will
disable the TCO Timer system reboot feature).
The status of this strap is readable via the
NO REBOOT bit.
RSMRST#
This signal should be connected to
power monitoring logic and should go
high no sooner than 10 ms after both
VccSus3_3 have reached their nominal
voltages.
NOTE:The RSMRST# signal of the Tiger
Point chipset must transition from 20%
signal level to 80% signal level and
vice-versa in 50 μs or less.
LINKALERT#:This signal requires an
T15
ICH_GPIO0
W16
ICH_GPIO6
W14
ICH_GPIO7
K18
ICH_GPIO8
H19
ICH_GPIO9
M17
EXT_SMI#
A24
ICH_GPIO12
C23
ICH_GPIO13
P5
ICH_GPIO14
E24
ICH_GPIO15
AB20
PM_DPRSLPVR
Y16
AB19
R3
SPI_WP#
C24
ICH_GPIO25
D19
D20
F22
AC19
PM_CLKRUN#
U14
AC1
AC23
GSS_INT1
AC24
GSS_INT2
AB22
H_PWRGD
AB17
PM_THRM#
V16
AC18
MCH_ICH_SYNC#
E21
PM_PWRBTN#
H23
PM_RI#
RI#
G22
PM_SUS_STAT#
D22
SUSCLK
G18
PM_SYSRST#
G23
PLT_RST#
C25
PCIE_WAKE#
T8
SM_INTRUDER#
U10
PM_ICH_PWROK
AC3
ICH_RSMRST_N
AD3
ICH_INTVRMEN
J16
AC_SPKR
H20
PM_SLP_S3#
E25
PM_SLP_S4#
F21
PM_SLP_S5#
B25
PM_BATLOW#
AB23
PM_DPRSTP_TGP_N
AA18
H_DPSLP_TGP_N
F20
EXT_SMI# 25
0611 change from ICH GPIO6 to GPIO13
R3916 NC_0,5%R0402R3916 NC_0,5%R0402
R3917 0,5% R0402R3917 0,5% R0402
PM_DPRSLPVR 7,36
PM_STPPCI# 6
PM_STPCPU# 6
PM_CLKRUN# 25
H_PWRGD 8
PM_PWRBTN# 25
PM_SUS_STAT# 25
1
T73 ICTPT73 ICTP
PCIE_WAKE# 19,22,25
R3931
100,5%
100,5%
PC_BEEP 18
PM_SLP_S3# 25
PM_SLP_S4# 25
PM_SLP_S5# 25
R3935 0,5%
R3935 0,5%
R3937 0,5%
R3937 0,5%
VR_PWRGD_CLK_EN 6
R0402R3931
R0402
+V1.05S
R3933
R3933
NC_56,5%
NC_56,5%
R0402
R0402
R0402
R0402
ns
ns
R0402
R0402
R3934
R3934
NC_56,5%
NC_56,5%
R0402
R0402
ns
ns
external pull-up resistor.
This signal should not be pulled low.
DPRSLPVR:This signal has a weak internal
pull-down.
This signal should not be pulled high.
GPIO25:This signal has a weak internal
pull-up.
If the signal is sampled high, the DMI
interface is strapped to operate in DC
coupled mode (No coupling capacitors are
required on DMI differential pairs).
If the signal is sampled low, the DMI
interface is strapped to operate in AC
coupled mode (Coupling capacitors are
required on DMI differential pairs).
PM_RSMRST# 25
R3932
R3932
10K,5%
10K,5%
R0402
R0402
H_DPRSTP# 8,36
H_DPSLP# 8
EC_RUNTIME_SCI#10,25
EC_RUNTIME_SCI#
PM_CLKRUN#
PM_STPPCI#
PM_STPCPU#
PM_THRM#
ICH_GPIO6
GSS_INT1
GSS_INT2
MCH_ICH_SYNC#
ICH_GPIO0
0611 change form 10k to 8.2k
ICH_GPIO7
SMB_ALERT#
SMB_LINK_ALERT#
PM_RI#
SMLINK1
SMLINK0
PM_BATLOW#
PCIE_WAKE#
PM_SLP_S3#
PM_SYSRST#
EXT_SMI#
ICH_GPIO8
ICH_GPIO9
ICH_GPIO12
ICH_GPIO14
ICH_GPIO15
ICH_GPIO13
ICH_GPIO25
ICH_GPIO25
PM_DPRSLPVR
+V3.3S
R3891 1K,5% R0402 nsR3891 1K,5% R0402 ns
R3892 10K,5%R0402R3892 10K,5%R0402
R3893 8.2K,5%R0402R3893 8.2K,5%R0402
R3894 10K,5%R0402 nsR3894 10K,5%R0402 ns
R3895 10K,5%R0402 nsR3895 10K,5%R0402 ns
R3896 8.2K,5%R0402R3896 8.2K,5%R0402
R3897 10K,5%R0402R3897 10K,5%R0402
R3898 10K,5%R0402R3898 10K,5%R0402
R3899 10K,5%R0402R3899 10K,5%R0402
R3904 1K,5% R0402R3904 1K,5% R0402
R3905 8.2K,5%R0402R3905 8.2K,5%R0402
R3906 10K,5%R0402R3906 10K,5%R0402
+V3.3AL
OCD_PCH1
OCD_PCH1
10K,5%R0402
10K,5%R0402
RN38
RN38
1 2
3 4
5 6
7 8
R3909 8.2K,5%R0402R3909 8.2K,5%R0402
R3910 1K,5% R0402R3910 1K,5% R0402
R3911 10K,5%R0402 nsR3911 10K,5%R0402 ns
R3912 10K,5%R0402R3912 10K,5%R0402
R3915 10K,5%R0402R3915 10K,5%R0402
RN39
RN39
1 2
3 4
5 6
7 8
R3920 10K,5%R0402R3920 10K,5%R0402
R3921 10K,5%R0402R3921 10K,5%R0402
R3922 10K,5%R0402 nsR3922 10K,5%R0402 ns
R3923 1K,5% R0402R3923 1K,5% R0402
R3925 100K,5%
10K,5%
10K,5%
RN8-0402_5938
RN8-0402_5938
10K,5%
10K,5%
RN8-0402_5938
RN8-0402_5938
R0402
R0402
nsR3925 100K,5%
ns
3
C3210
C3210
0.1/10V,X7R
0.1/10V,X7R
C0402
C0402
4
R3946
R3946
100K,5%
100K,5%
R0402
R0402
+V3.3AL
53
U514
U514
1
VCC
VCC
2
GND
GND
SN74AHC1G08DBV
SN74AHC1G08DBV
PLT_RST#
PM_ICH_PWROK
A A
RTC_BAT1
RTC_BAT1
根据机构
定
Cable
+
+
-
-
RTCBAT with Cable
RTCBAT with Cable
assembly
assembly
<PCB Footprint>
<PCB Footprint>
尺寸
ICH_SPI_CS#
ICH_SPI_DATAIN
SPI_WP#
5
+V3.3S
R3938
R3938
R3939
R3939
8.2K,5%
8.2K,5%
4.7K,5%
4.7K,5%
R0402
R0402
R0402
R0402
R3943 22,5% R0402R3943 22,5% R0402
R3940
R3940
8.2K,5%
8.2K,5%
R0402
R0402
U513
U513
1
CE#
2
SO
3
WP#
4
GND
Winbond 25X16Mbit
Winbond 25X16Mbit
HOLD#
R3941
R3941
R3942
R3942
C3211
4.7K,5%
4.7K,5%
R0402
R0402
C3211
0.1/10V,X7R
0.1/10V,X7R
C0402
C0402
ICH_SPI_CLK
ICH_SPI_DATAOUT
BUF_PLT_RST#7,10,19,22,25
8.2K,5%
8.2K,5%
R0402
R0402
8
VDD
7
ICH_SPI_HOLD#
6
R3944 22,5% R0402R3944 22,5% R0402
SCK
5
R3945 22,5% R0402R3945 22,5% R0402
SI
4
C3212
C3212
0.1/10V,X7R
0.1/10V,X7R
C0402
C0402
4
R3947
R3947
10K,5%
10K,5%
R0402
R0402
+V3.3AL
53
U515
U515
1
VCC
VCC
2
GND
GND
SN74AHC1G08DBV
SN74AHC1G08DBV
2
EC_MAIN_PWROK 25
IMVP_PWRGD 7,25,36
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Page Name
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Project Name Rev
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Date: Sheet
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PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
Tiger point LPC ACPI
Tiger point LPC ACPI
Tiger point LPC ACPI
BM5999
BM5999
BM5999
1
11 42
11 42
11 42
of
of
of
1.3
1.3
1.3
5
ICH_EC_RTC 11
+V3.3AL 7,10,11,14,19,20,22,23,24,25,27,30,31,33,34
+V5AL 20,24,29,30,31,32,33,34
+V3.3S 6,7,8,9,10,11,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
+V5S 14,15,16,18,20,21,29,30,36
+V1.05S 6,8,9,10,11,29,34
+V1.5S 9,22,29,30
VCC5REF
VCCRTC
F12
F5
Y6
AE3
Y25
F6
W18
AA8
M9
M20
N22
J10
K17
P15
V10
H25
AD13
F10
G10
R10
T9
F18
N4
K7
F1
5
5
+V1.5S_PCIE_ICH 10
VCC5REF VCC5REF_SUS
VCC5REF
6mA
VCC5REF_SUS
10mA
VCCSATAPLL
45mA
2mA
VCCDMIPLL
24mA
VCCUSBPLL
10mA
C0402
C0402
14mA
1.422A
OCD_PCH2
OCD_PCH2
0.1,X7R
0.1,X7R
C0402
C0402
C0402
C0402
955mA
C3225
C3225
1UF/10V,X7R
1UF/10V,X7R
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
216mA
C3228
C3228
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C0402
C0402
Place near VCCPPC1,VCCPPC
92mA
C3234
C3234
1UF/10V,X7R
1UF/10V,X7R
0.1,X7R
0.1,X7R
C0402
C0402
D D
TGP
U512E
U512E
C C
B B
TGP_0
TGP_0
TGP
VCC5REF_SUS
VCCSATAPLL
VCCDMIPLL
VCCUSBPLL
V_CPU_IO
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
POWER
POWER
VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
D96 1N5819
D96 1N5819
R3948 100,5%R0603R3948 100,5%R0603
1UF/10V,X7R
1UF/10V,X7R
ICH_EC_RTC
C3219
C3219
0.01u,X7R
0.01u,X7R
C3221
C3221
0.1,X7R
0.1,X7R
C3226
C3226
C0603
C0603
C3229
C3229
0.1,X7R
0.1,X7R
C3235
C3235
C0603
C0603
4
1
1
SOD123
SOD123
Layout note:
C3213
C3213
0.1uF needs be placed
within 100mils of
C0603
C0603
TigerPoint F12
FB45
FB45
1 2
60ohm,1A
60ohm,1A
C3220
C3220
4.7U/10V,X5R
4.7U/10V,X5R
C0805
C0805
C3222
C3222
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C3227
C3227
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C3230
C3230
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C3236
C3236
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
+V3.3S
+V5S
+V1.5S
FB0603
FB0603
C0402
C0402
C3237
C3237
10UF/16V,Y5V
10UF/16V,Y5V
C0805
C0805
C3231
C3231
0.1,X7R
0.1,X7R
C3215
C3215
0.1,X7R
0.1,X7R
C0402
C0402
C3223
C3223
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
C3232
C3232
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
1 2
60ohm,1A
60ohm,1A
C3216
C3216
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
1 2
60ohm,1.5A
60ohm,1.5A
C3224
C3224
10UF/6.3V,X5R
10UF/6.3V,X5R
C0805
C0805
C3233
C3233
1UF/10V,X7R
1UF/10V,X7R
C0603
C0603
3
D97 1N5819
D97 1N5819
1
1
+V3.3AL
SOD123
SOD123
R3949 10,5%R0603R3949 10,5%R0603
C3214
C3214
0.1,X7R
0.1,X7R
C0402
C0402
+V1.5S ICH_EC_RTC
FB44
FB44
FB0603
FB0603
+V1.5S+V1.5S_PCIE_ICH
FB46
FB46
FB0603
FB0603
+V5AL
Layout note:
0.1uF needs be placed
within 100mils of pin
F5 of TP
C3217
C3217
0.1,X7R
0.1,X7R
C0402
C0402
Layout note:
PLACE NEAR PIN VCCAUPLL F6
+V1.05S
+V3.3S
+V3.3AL
C0402
C0402
+V3.3S6,7,8,9,10,11,13,14,15,17,18,19,20,21,22,23,25,28,29,30,36
C3218
C3218
0.1,X7R
0.1,X7R
+V3.3S
Layout note:
needs be placed
closed to pin
AE3 of ICH7M
2
U512F
U512F
1
U1LB
U1LB
TGP
TGP
VSS01
VSS02
VSS03
VSS04
VSS05
VSS06
VSS07
VSS08
VSS09
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
RSVD32
A1
A25
B6
B10
B16
B20
B24
E18
F16
G4
G8
H1
H4
H5
K4
K8
K11
K19
K20
L4
M7
M11
N3
N12
N13
N14
N23
P11
P13
P19
R14
R22
T2
T22
V1
V7
V8
V19
V22
V25
W12
W22
Y2
Y24
AB4
AB6
AB7
AB8
AC8
AD2
AD10
AD20
AD24
AE1
AE10
AE25
G24
AE13
F2
AE16
TGP_0
TGP_0
A A
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Page Name
Page Name
Page Name
Size
Size
Size
Project Name Rev
Project Name Rev
Project Name Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
5
4
3
2
was obtained with the expressed written consent of Bitland
Tiger Piont POWER GND
Tiger Piont POWER GND
Tiger Piont POWER GND
BM5999
BM5999
BM5999
1
12 42
12 42
12 42
of
of
of
1.3
1.3
1.3
5
hexainf@hotmail.com
GRATIS - FOR FREE
4
3
2
1
MA_A_A[14:0]7
D D
MA_A_BS#07
MA_A_BS#17
MA_A_BS#27
M_CS#07
M_CS#17
M_CLK_DDR07
M_CLK_DDR#07
M_CLK_DDR17
SMBus Address: A0H(W)/A1H(R)
R400 10K R0402R400 10K R0402
R401 10K R0402R401 10K R0402
C C
B B
M_CLK_DDR#17
M_CKE07
M_CKE17
MA_A_CAS#7
MA_A_RAS#7
MA_A_WE#7
SMB_CLK_S6,11
SMB_DATA_S6,11
M_ODT07
M_ODT17
MA_DM[7:0]7
MA_DQS[7:0]7
MA_DQS#[7:0]7
MA_A_A0
MA_A_A1
MA_A_A2
MA_A_A3
MA_A_A4
MA_A_A5
MA_A_A6
MA_A_A7
MA_A_A8
MA_A_A9
MA_A_A10
MA_A_A11
MA_A_A12
MA_A_A13
MA_A_A14
SA0_DIM0
SA1_DIM0
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS0
MA_DQS1
MA_DQS2
MA_DQS3
MA_DQS4
MA_DQS5
MA_DQS6
MA_DQS7
MA_DQS#0
MA_DQS#1
MA_DQS#2
MA_DQS#3
MA_DQS#4
MA_DQS#5
MA_DQS#6
MA_DQS#7
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120
11
28
46
63
136
153
170
187
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
CN2A
CN2A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DDR3_204P
DDR3_204P
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
MA_DATA1
7
MA_DATA0
15
MA_DATA3
17
MA_DATA2
4
MA_DATA5
6
MA_DATA4
16
MA_DATA7
18
MA_DATA6
21
MA_DATA8
23
MA_DATA9
33
MA_DATA10
35
MA_DATA11
22
MA_DATA13
24
MA_DATA12
34
MA_DATA15
36
MA_DATA14
39
MA_DATA16
41
MA_DATA17
51
MA_DATA18
53
MA_DATA19
40
MA_DATA21
42
MA_DATA20
50
MA_DATA22
52
MA_DATA23
57
MA_DATA25
59
MA_DATA24
67
MA_DATA31
69
MA_DATA30
56
MA_DATA28
58
MA_DATA29
68
MA_DATA27
70
MA_DATA26
129
MA_DATA36
131
MA_DATA37
141
MA_DATA35
143
MA_DATA34
130
MA_DATA32
132
MA_DATA33
140
MA_DATA38
142
MA_DATA39
147
MA_DATA45
149
MA_DATA44
157
MA_DATA43
159
MA_DATA42
146
MA_DATA41
148
MA_DATA40
158
MA_DATA46
160
MA_DATA47
163
MA_DATA52
165
MA_DATA49
175
MA_DATA54
177
MA_DATA55
164
MA_DATA48
166
MA_DATA53
174
MA_DATA51
176
MA_DATA50
181
MA_DATA61
183
MA_DATA60
191
MA_DATA62
193
MA_DATA63
180
MA_DATA56
182
MA_DATA57
192
MA_DATA59
194
MA_DATA58
DIMM_0
MA_DATA[63:0] 7
PM_EXTTS#07
DDR3_DRAMRST#7
DDR3_VREF
+V3.3S
C3314
C3314
0.1uF/25V,Y5V
0.1uF/25V,Y5V
C0402
C0402
C3312
C3312
0.1uF/25V,Y5V
0.1uF/25V,Y5V
C0402
C0402
C3310
C3310
0.1uF/25V,Y5V
0.1uF/25V,Y5V
C0402
C0402
C3315
C3315
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
R402 NC_0,5% R0402R402 NC_0,5% R0402
R403 0,5% R0402R403 0,5% R0402
C3313
C3313
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
DQ_VREF0
C3311
C3311
2.2UF/10V,X7R
2.2UF/10V,X7R
C0805
C0805
+V1.57,9,29,30,31
TS#_DIMM0
DQ_VREF0
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
77
122
125
198
30
1
126
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
CN2B
CN2B
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTEST
EVENT#
RESET#
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
DDR3_204P
DDR3_204P
+V3.3S6,7,8,9,10,11,12,14,15,17,18,19,20,21,22,23,25,28,29,30,36
NPTH1
NPTH2
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VTT1
VTT2
+V3.3S
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
203
204
207
G1
208
G2
DDR3_VREF
R404 0,5% R0402R404 0,5% R0402
C3316
(20 mil)
+V0.75S
C3316
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
Place these Caps near So-DIMM0
R415
R415
1k,5%
1k,5%
R0402
R0402
R408
R408
1k,5%
1k,5%
R0402
R0402
+V1.57,9,29,30,31
C3317
C3317
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
+V1.57,9,29,30,31
12
C3288
C3284
C3284
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
A A
5
C3288
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
Layout note:
+V1.57,9,29,30,31
C3286
C3286
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
+V1.57,9,29,30,31
C3283
C3283
2.2uF/10V,X7R
2.2uF/10V,X7R
C0805
C0805
C3289
C3289
10uF/6.3V,X5R
10uF/6.3V,X5R
C0805
C0805
电容靠近
C3287
C3287
2.2uF/10V,X7R
2.2uF/10V,X7R
C0805
C0805
C3295
C3295
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3291
C3294
C3294
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3291
2.2uF/10V,X7R
2.2uF/10V,X7R
C0805
C0805
DDR slot VDD PIN
C3292
C3292
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3282
C3282
2.2uF/10V,X7R
2.2uF/10V,X7R
C0805
C0805
4
C3293
C3293
2.2uF/10V,X7R
2.2uF/10V,X7R
C0805
C0805
C3290
C3290
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3280
C3280
2.2uF/10V,X7R
2.2uF/10V,X7R
C0805
C0805
C3285
C3285
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3296
C3296
2.2uF/10V,X7R
2.2uF/10V,X7R
C0805
C0805
PC156
PC156
NC_330U_6.3V_M
NC_330U_6.3V_M
7.3x4.3x1.9
7.3x4.3x1.9
12
+
PC13
+
+
+
PC13
330U_6.3V_3528
330U_6.3V_3528
6TPC47MB
6TPC47MB
3
+V0.75S
C3300
C3300
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3298
C3298
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3305
C3305
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
2
C3297
C3297
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
C3307
C3304
C3306
C3306
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
Page Name
Page Name
Page Name
Size
Size
Size
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
was obtained with the expressed written consent of Bitland
C3304
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
Project Name Rev
Project Name Rev
Project Name Rev
C3307
0.1uF/10V,X7R
0.1uF/10V,X7R
C0402
C0402
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
Bitland Information Technology Co.,Ltd
DDR3 SODIMM0
DDR3 SODIMM0
DDR3 SODIMM0
BM5999
BM5999
BM5999
1
13 42
13 42
13 42
of
of
of
1.3
1.3
1.3
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