LENOVO N480 Schematics

5

D D

4

3

2

1

Bitland Confidential

N480 MB Schematics Document

C C

Intel Ivy Bridge/Sandy Bridge Processor with PantherPoint HM76/HM70+ DDRIII

MotherBoard version：BM5238 Rev1.2

B B

2012-04-09

A A

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Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

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Document Number

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A3

A3 Date:

Date:

Wednesday, September 12, 2012 64

5

4

3

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Wednesday, September 12, 2012 64

Cover page

Notebook R&D Division

N480

Sheet of

1

Rev

1.2

1

5

4

3

2

1

1G DDR3

P56

Ivy Processor

D D

LVDS

GPU Robson-XT

PEG X16

Micro-FCPGA-988 (988-pin rPGA socket)

1600/1333 MHZ

37.5 mm X 37.5 mm

CRT

SO-DIMM 0 1600/1333 MHZ DDR(III)

204 pin

P20

IMVP7 (2+1)

P42

LVDS

WXGA

P23 P22

VGA

P4-P10

CRT(Option)

LVDS(Option) FDI

Int. Speaker

1.5Walt

C C

Combo Jack x1

DB

Realtek ALC269-VB6

P30

HDA

USB2.0

CPT/PPT

(USB x 14) (PCIE x 8) (SATA x 6) 989 mBGA

Internal Mic X1

PCIE

25 mm X 25 mm

DMI

PCIE

USB2.0 SPI

SATA3.0

SATA2.0

SATA HDD

P34

SATA ODD

P34

Harf Mini-Card WLAN

P27

USB 2.0 CONNx3

P33

P11-P19

CAMERA

RJ45

P29

Transformer

RTL8105E 100M LAN

USB2.0(Option)

LPC

P31

Flash BIOS 32Mbitx2

P11

RTS5179

B B

2in1 Conn

P36

ITE IT8518E

LQFP-128

P25

GPIO

Lid Switch

P25

GPIO

PS2

PWM/TACH

SPI

Keyboard

A A

5

P25 P37 P35

LED

P35 P35

4

FAN BATT CONN Power Button

Flash BIOS 512K bit

P26

3

SMBus0

Thermal Sensor

P32P32

Touchpad

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Wednesday, September 12, 2012 64

Date:

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Notebook R&D Division

Block Diagram

N480

Sheet of

1

Rev

1.2

2

1.2

5

A

Power Annotations

Power Plane AD+ DCBATOUT VHCORE +0_75V 0_75VRUN LDO power rail for DDR terminator +1_05VRUN

D D

+1.0V_VCCP +1_5VSUS 1.5V power rail for DDR +1_5V_CPU 1.5V switched power rail +1_8VRUN +3VALW

+3VSUS

+V3.3M_LAN +3VRUN +5VALW

+5VSUS

+5VRUN 5V switched power rail +3VALW_LDO +5VALW_LDO +VCCSA GFXCORE

+VDDC

Description Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU

1.05V switched power rail VCCP switched power rail

1.8V power rail for system

3.3V always on power rail

3.3V power rail for SB

3.3V power rail for LAN

3.3V switched power rail 5V always on power rail 5V switched power rail

3.3V power from TPS51125 LDO 5V power from TPS51125 LDO SA voltage for CPU GFXCORE voltage for CPU Graphic

CORE Power for discete GPU

C C

Voltage Rails

Power Plane

State

S0

S3

B B

S4&S5 (AC)

S3&S4 (Battery only)

S3&S4 (AC&Battery don't exist) OFF OFFOFFOFF

DCBATOUT +3VALW_LDO +5VALW_LDO

AD+ +3VALW +V3.3M_LAN +5VALW

ON

+1_5VSUS +3VSUS +5VSUS

ON

+0_75V +1_05VRUN +1.05V_VCCP +VCCSA VHCORE +1_5V_CPU +1_8VRUN +3VRUN +5VRUN GFXCORE +VDDC

ON ON

ON

OFF

OFFOFFOFF

4

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

EC SM Bus1 address

Device

Smart Battery

Address Address

0001 011X b

3

EC SM Bus2 address

Device

Thermal Sensor for DDR&VR

1001 100X b

2

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

1

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +V*ALW +V*SUS +V*RUN Clock

ON

ONONON ON

ON

OFF

LOW

OFF

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

HIGHHIGHHIGH

HIGH

LOWLOWLOW

HIGH

BOARD ID Table

+ECVCC 3.3V 5% R3863100K 5%

CPT/PPT SM Bus address

Device Address

DDR DIMM0 DDR DIMM1 Debug Port

1001 000Xb 1001 010Xb 1100 1000 b

Board ID 0 1 2

R387 0

8.2K 5% 18K 5% 33K 5%

V min V typ 0V

0.216V

0.436V

0.712V

0V

0.250V

0.503V

0.819V

V max Phase 0V

REV1.0

0.289V

REV1.1

0.538V

REV1.2 REV1.3

0.875V

USB Port Table

CPT/PPT SM Bus0 address

Device Address

SMBUS Control Table

SOURCE VGA BATT EC DIMM

SMB_EC_CK0 SMB_EC_DA0

SMB_EC_CK1 SMB_EC_DA1

SMBCLK SMBDATA

SML0CLK SML0DATA

SML1CLK SML1DATA

IT8105E

+3VALW

IT8105E

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

+ECVCC

V

X X X X V

+3VALW

CPT/PPT SM Bus1 address

EC

X V

WLAN

Thermal

WWAN

Sensor

X

V

X

+3VALW

X

AddressDevice

PCH GPU LAN

USB 2.0

USB 3.0

PORT-0 PORT-1 PORT-2 PORT-3 PORT-4 PORT-5 PORT-6 PORT-7 PORT-8 PORT-9 PORT-10 PORT-11 PORT-12 PORT-13 PORT-0 PORT-1 PORT-2 PORT-3

FunctionUSB PORT

Ext. Port(MB) Ext. Port(MB)

Card reader

Ext. Port(DB)

BT

CAMERA

OC pin

OC#0

OC#1

OC#2

OC#3

OC#4

OC#5

OC#6

A

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A2 Date:

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Wednesday, September 12, 2012 64

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Wednesday, September 12, 2012 64

NOTE LIST

1

Notebook R&D Division

N480

Sheet of

Rev

1.2

3

5

A

4

+1_05VRUN 5,7,11,13,17,18,26,40,42,44,48,49,51,52

3

2

1

CAD NOTE: PEG_ICOMPI and RCOMPO signals should be shorted and routed with

- max length = 500 mils

- typical impedance = 43 mohms

D D

PEG_ICOMPO signals should be routed with

- max length = 500 mils

- typical impedance = 14.5 mohms

+1_05VRUN

U55A

DMI_TXN[3:0]13

DMI_TXP[3:0]13

DMI_RXN[3:0]13

DMI_RXP[3:0]13

C C

FDI_TXN[7:0]13

add by lihong 0504

R7 1K_J R0402

R7 1K_J R0402 R8 1K_J R0402

R8 1K_J R0402 R40 1K_J R0402

R40 1K_J R0402 R41 1K_J R0402

R41 1K_J R0402 R42 1K_J R0402

R42 1K_J R0402

12 12 12 12 12

CAD NOTE: DP_COMPIO and

B B

ICOMPO signals should be shorted near balls and routed with

- typical impedance < 25 mohms

GPU

GPU GPU

GPU

FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1

+1_05VRUN

R2

24.9_F

r0402

1 2

FDI_TXP[7:0]13

FDI_FSYNC013 FDI_FSYNC113

FDI_INT13 FDI_LSYNC013

FDI_LSYNC113

DP_COMP

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

del R3 lihong 0504

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

DMI

Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9]

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_COMP

0.22uF->0.1uF lihong 0626

In order to support Gen 3 PCI Express Graphic, the value of the AC coupling capacitor should be 180 - 265 nF. As for Gen2 PCI Express ,the value of the AC coupling capacitor should be 100 - 220 nF

1 2

R1 24.9_F r0402R1 24.9_F r0402

GFX_RX0N_C 48 GFX_RX1N_C 48 GFX_RX2N_C 48 GFX_RX3N_C 48 GFX_RX4N_C 48 GFX_RX5N_C 48 GFX_RX6N_C 48 GFX_RX7N_C 48 GFX_RX8N_C 48

GFX_RX9N_C 48 GFX_RX10N_C 48 GFX_RX11N_C 48 GFX_RX12N_C 48 GFX_RX13N_C 48 GFX_RX14N_C 48 GFX_RX15N_C 48

GFX_RX0P_C 48

GFX_RX1P_C 48

GFX_RX2P_C 48

GFX_RX3P_C 48

GFX_RX4P_C 48

GFX_RX5P_C 48

GFX_RX6P_C 48

GFX_RX7P_C 48

GFX_RX8P_C 48

GFX_RX9P_C 48

GFX_RX10P_C 48 GFX_RX11P_C 48 GFX_RX12P_C 48 GFX_RX13P_C 48 GFX_RX14P_C 48 GFX_RX15P_C 48

1 2

C3510 0.1uF/10V,X5R GPUc0402C3510 0.1uF/10V,X5R GPUc0402

1 2

C3511 0.1uF/10V,X5R GPUc0402C3511 0.1uF/10V,X5R GPUc0402

1 2

C3512 0.1uF/10V,X5R GPUc0402C3512 0.1uF/10V,X5R GPUc0402

1 2

C3513 0.1uF/10V,X5R GPUc0402C3513 0.1uF/10V,X5R GPUc0402

1 2

C3514 0.1uF/10V,X5R GPUc0402C3514 0.1uF/10V,X5R GPUc0402

1 2

C3515 0.1uF/10V,X5R GPUc0402C3515 0.1uF/10V,X5R GPUc0402

1 2

C3516 0.1uF/10V,X5R GPUc0402C3516 0.1uF/10V,X5R GPUc0402

1 2

C3517 0.1uF/10V,X5R GPUc0402C3517 0.1uF/10V,X5R GPUc0402

1 2

C3502 0.1uF/10V,X5R GPUc0402C3502 0.1uF/10V,X5R GPUc0402

1 2

C3503 0.1uF/10V,X5R GPUc0402C3503 0.1uF/10V,X5R GPUc0402

1 2

C3504 0.1uF/10V,X5R GPUc0402C3504 0.1uF/10V,X5R GPUc0402

1 2

C3505 0.1uF/10V,X5R GPUc0402C3505 0.1uF/10V,X5R GPUc0402

1 2

C3506 0.1uF/10V,X5R GPUc0402C3506 0.1uF/10V,X5R GPUc0402

1 2

C3507 0.1uF/10V,X5R GPUc0402C3507 0.1uF/10V,X5R GPUc0402

1 2

C3508 0.1uF/10V,X5R GPUc0402C3508 0.1uF/10V,X5R GPUc0402

1 2

C3509 0.1uF/10V,X5R GPUc0402C3509 0.1uF/10V,X5R GPUc0402

1 2

C3518 0.1uF/10V,X5R GPUc0402C3518 0.1uF/10V,X5R GPUc0402

1 2

C3519 0.1uF/10V,X5R GPUc0402C3519 0.1uF/10V,X5R GPUc0402

1 2

C3520 0.1uF/10V,X5R GPUc0402C3520 0.1uF/10V,X5R GPUc0402

1 2

C3521 0.1uF/10V,X5R GPUc0402C3521 0.1uF/10V,X5R GPUc0402

1 2

C3522 0.1uF/10V,X5R GPUc0402C3522 0.1uF/10V,X5R GPUc0402

1 2

C3523 0.1uF/10V,X5R GPUc0402C3523 0.1uF/10V,X5R GPUc0402

1 2

C3524 0.1uF/10V,X5R GPUc0402C3524 0.1uF/10V,X5R GPUc0402

1 2

C3525 0.1uF/10V,X5R GPUc0402C3525 0.1uF/10V,X5R GPUc0402

1 2

C3526 0.1uF/10V,X5R GPUc0402C3526 0.1uF/10V,X5R GPUc0402

1 2

C3527 0.1uF/10V,X5R GPUc0402C3527 0.1uF/10V,X5R GPUc0402

1 2

C3528 0.1uF/10V,X5R GPUc0402C3528 0.1uF/10V,X5R GPUc0402

1 2

C3529 0.1uF/10V,X5R GPUc0402C3529 0.1uF/10V,X5R GPUc0402

1 2

C3530 0.1uF/10V,X5R GPUc0402C3530 0.1uF/10V,X5R GPUc0402

1 2

C3531 0.1uF/10V,X5R GPUc0402C3531 0.1uF/10V,X5R GPUc0402

1 2

C3532 0.1uF/10V,X5R GPUc0402C3532 0.1uF/10V,X5R GPUc0402

1 2

C3533 0.1uF/10V,X5R GPUc0402C3533 0.1uF/10V,X5R GPUc0402

GFX_TX0N_C 48 GFX_TX1N_C 48 GFX_TX2N_C 48 GFX_TX3N_C 48 GFX_TX4N_C 48 GFX_TX5N_C 48 GFX_TX6N_C 48 GFX_TX7N_C 48 GFX_TX8N_C 48 GFX_TX9N_C 48 GFX_TX10N_C 48 GFX_TX11N_C 48 GFX_TX12N_C 48 GFX_TX13N_C 48 GFX_TX14N_C 48 GFX_TX15N_C 48

GFX_TX0P_C 48 GFX_TX1P_C 48 GFX_TX2P_C 48 GFX_TX3P_C 48 GFX_TX4P_C 48 GFX_TX5P_C 48 GFX_TX6P_C 48 GFX_TX7P_C 48 GFX_TX8P_C 48 GFX_TX9P_C 48 GFX_TX10P_C 48 GFX_TX11P_C 48 GFX_TX12P_C 48 GFX_TX13P_C 48 GFX_TX14P_C 48 GFX_TX15P_C 48

MXM3.0 need put the CAP on the motherboard. Close to the MXM Slot

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Wednesday, September 12, 2012 64

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Date:

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CPU(DMI,DP,PEG,FDI)

Notebook R&D Division

N480

Sheet of

Rev

1.2

4

A

5

A

4

3

+3VALW 8,11,12,13,15,16,17,18,23,25,26,27,31,35,38,39,43,44,47 +1_5V_CPU 8,17,27,43,44,47,51,55,56,57 +3VRUN 11,12,13,14,15,16,17,18,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +1_05VRUN 4,7,11,13,17,18,26,40,42,44,48,49,51,52 +1_5VSUS 8,20,39,43,57

2

1

D D

+3VALW

U55B

A28

BCLK

A27

BCLK#

A16

DPLL_REF_CLK

R43 1K_J R0402R43 1K_J R0402

A15

R45 1K_J R0402R45 1K_J R0402

refer to DG no eDP lihong 0504

R8

PRDY#

PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TCK TMS

TDO

TDI

AK1 A5 A4

AP29 AP27

AR26 AR27 AP30

AR28 AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

DDR3_DRAMRST#_R

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PROCHOT#_R

H_PM_SYNC

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK#

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

H_SNB_IVB#16

ictpad_c20

20MIL

TP101

ictpad_c20

20MIL

TP105

H_PECI25

1

TP107

1

TP106

ictpad_c20

H_PM_SYNC13

H_CPUPWRGD16

PM_SYS_PWRGD_BUFF

BUF_CPU_RST#

1

TP126

TP105

H_PROCHOT#

del R8 lihong 0503

ictpad_c20

20MIL

H_PROCHOT#42

PM_THRMTRIP#16,26

ictpad_c20

20MIL

C C

ictpad_c20

20MIL

H_SNB_IVB#

1

SKTOCC#

1

H_CATERR#

1 2

56_J r0402

R459

del R15 lihong 0504

20MIL

56_J r0402

1

TP108

1 2

R29 10K_J r0402R29 10K_J r0402

1 2

R179 130_F r0402R179 130_F r0402

1 2

R636 43_F r0402R636 43_F r0402

H_CPUPWRGD

BUF_CPU_RST#_R

del RP1 RP2 refer to TCL lihong 0503

CLK_EXP_P 12 CLK_EXP_N 12

12 12

R10 140_F r0402R10 140_F r0402 R11 25.5_F r0402R11 25.5_F r0402 R12 200_F r0402R12 200_F r0402

1 2 1 2 1 2

+1_05VRUN

CAD NOTE: All DDR_COMP signals should be routed such that :-

- max length = 500 mils

- trace width = 15mils and

- MB trace impedance < 68 mohms (worst case resistance)

del R484 R485 lihong 0425

R5646 1K_J

R0402

dengrl

The OD buffer serves two purposes:

1.Voltage level shifter - from 3.3 V (EC) to 1.05 V (Processor).

2.Improve the Prochot signal quality at the Processor.

R117

10K_J

r0402

12

1 2

1

3 2

XDP_TDO XDP_TMS XDP_TDI XDP_PREQ# XDP_TCK XDP_TRST#

XDP_DBRESET#

Q3657

Q3657 LMBT3904LT1G

LMBT3904LT1G

SOT23-3

R53 51_J r0402R53 51_J r0402 R52 51_J r0402R52 51_J r0402 R60 51_J r0402R60 51_J r0402 R65 51_J nsr0402R65 51_J nsr0402 R54 51_J r0402R54 51_J r0402 R59 51_J r0402R59 51_J r0402

R241 1K_J r0402R241 1K_J r0402

OVT_EC# 25

+1_05VRUN+1_05VRUN

CAD Note: Capacitor need to be placed close to transistor

R6

1K_J

R0402

1 2

H_PROCHOT#

1 2 1 2 1 2 1 2 1 2

12

1 2

12

C2

C2 47PF/50V,NPO

47PF/50V,NPO

c0402

+1_05VRUN

+3VRUN

B B

+1_5VSUS

R21

+3VALW

12

C48

1 2

53

4

U4

U4 74AHC1G09GW

74AHC1G09GW

sot353

sot353 ns

ns

C48

0.1UF/10V,X5R

c0402

c0402 ns

ns

+1_5V_CPU

R72

R72 200_F

200_F

r0402

1 2

PM_SYS_PWRGD_BUFF

C365

C365 18PF/50V,NPO

18PF/50V,NPO

c0402

1 2

ns

+3VRUN +1_05VRUN

U12

U12 TC7SZ07F

TC7SZ07F

sot23-5

2

PLT_RST#

PLT_RST#15,25,26,27,31,48

1

A NC GND3Y

VCC

4

12

C3

0.1UF/10V,X5R

R785

c0402

1 2

R785 75_J

75_J

r0603

BUF_CPU_RST#

5

4

3

DDR3_DRAMRST#_R

del 0ohm R37 R69 lihong 0723

DRAMRST_CNTRL_PCH8,12

R66

R66 10K_J

10K_J

r0402

r0402 ns

ns

1 2

1P5S_1P8_0P75_PWRGD47

PM_DRAM_PWRGD13

R664 0_J r0402R664 0_J r0402

20111124 by dengrl

5

Q22 footprint SOT23_ld1_h43 -> sot23-3 lihong 0627

1 2

R36 0_J

nsr0402

S

D

32

G

Q22

1

BSS138-7

sot23-3

12

C1

0.047UF/10V,X7R

c0402

+3VALW

12

R30

4.99K_F

r0402

R132

R132 1K_J

1K_J

r0402

1 2

2

R21 1K_F

1K_F

r0402

1 2

R22 1K_F r0402R22 1K_F r0402

12

C332

0.01UF/25V,X7R

c0402

12

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A2

A2 Date:

Date:

Wednesday, September 12, 2012 64

DDR3_DRAMRST# 20

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

CPU(CLK,MISC,JTAG)

N480

Sheet of

1

Rev

1.2

5

A

5

A

U55C

4

3

U55D

2

1

AB6

SA_CK[0]

M_A_DQ[63:0]20

D D

C C

B B

M_A_BS020 M_A_BS120 M_A_BS220

M_A_CAS#20 M_A_RAS#20 M_A_WE#20

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8

M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8 AK9

AH8 AH9 AL9

AL8 AP11 AN11 AL12

AM12 AM11

AL11 AP12

AN12

AJ14

AH14

AL15 AK15 AL14 AK14

AJ15

AH15

AE10 AF10

AE8

AD9

AF9

F10

M8

M9 M7

AJ5 AJ6 AJ8

AJ9

C5 D5 D3 D2 D6 C6 C2 C3

F8 G9

F9 F7 G8 G7 K4 K5 K1

J1 J5 J4 J2

K2

N8 N7

N9

V6

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

SA_CLK#[0]

SA_CLK#[1]

SA_CLK#[2]

SA_CLK#[3]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

DDR SYSTEM MEMORY A

SA_CKE[0]

SA_CK[1]

SA_CKE[1]

SA_CK[2]

SA_CKE[2]

SA_CK[3]

SA_CKE[3]

SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]

SA_ODT[0]

SA_ODT[1] SA_ODT[2] SA_ODT[3]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8

M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_CLK_DDR0 20 M_CLK_DDR#0 20 M_CKE0 20

M_CLK_DDR1 20 M_CLK_DDR#1 20 M_CKE1 20

M_CS#0 20 M_CS#1 20

M_ODT0 20 M_ODT1 20

M_A_A[15:0] 20

M_A_DQS#[7:0] 20

M_A_DQS[7:0] 20

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9 AA7

AA10

AB8 AB9

C9 A7

C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2

K9

J10

K8 K7 M5 N4 N2 N1 M4 N5 M2 M1

R6

J7 J8

J9

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

AE2

SB_CK[0]

SB_CKE[0]

SB_CK[1]

SB_CKE[1]

SB_CK[2]

SB_CKE[2]

SB_CK[3]

SB_CKE[3]

SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3]

SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

SB_CLK#[0]

SB_CLK#[1]

SB_CLK#[2]

SB_CLK#[3]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

DDR SYSTEM MEMORY B

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

A

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A3

A3 Date:

Wednesday, September 12, 2012 64

Date:

Wednesday, September 12, 2012 64

Date:

Wednesday, September 12, 2012 64

CPU(DDR3)

Notebook R&D Division

N480

Sheet of

Rev

1.2

6

5

A

VHCORE 10,42 +1_05VRUN 4,5,11,13,17,18,26,40,42,44,48,49,51,52

4

3

+1_05VRUN

2

1

D D

POWER

U55F

94A

VHCORE

12

C14

C14 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C20

C20 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C23

C23 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C4

C4 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C12

C12 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C24

C24 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

VHCORE

12

VHCORE

12

C15

C15 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

C21

C21 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

C38

C38 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C5

C5 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C22

C22 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C77

C77 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C16

C16 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C13

C13 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C82

C82 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

C C

VHCORE

12

C64

C64 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

VHCORE

12

C39

C40

10uF/6.3V,X5R

c0805

del C44 Power suggest lihong 0517

VHCORE

12

C43

C43 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

VHCORE

B B

C3568

C3570

0.1UF/10V,X5R

C0402_BGA

VHCORE

470uF(1002-00254) -> 330uF(1002-00252) lihong 0516

12

PC163

+

330uF/2V

tc7343

ns

12

PC173

PC173 820uF/2.5V

820uF/2.5V

+

Ced_6d3x8

Decoupling capacitors for +Vcc_CORE rail [10+1PH] 0805, 10uF (644066-099) [16+3PH] 0805, 22uF (644066-070) [4+2PH] 470uF, 4.5mohm ESR (699013-025)

+

12

+

PC164

PC164 330uF/2V

330uF/2V

tc7343

ns

PC174

PC174 820uF/2.5V

820uF/2.5V

Ced_6d3x8

12

+

12

+

PC187

PC187 330uF/2V

330uF/2V

tc7343

ns

PC175

PC175 820uF/2.5V

820uF/2.5V

Ced_6d3x8

12

C41

C41 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C45

C45 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

C3574

0.1UF/10V,X5R

C0402_BGA

12

+

12

+

12

PC188

PC188 330uF/2V

330uF/2V

tc7343

ns

PC176

PC176 820uF/2.5V

820uF/2.5V

Ced_6d3x8

C42

C42 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

C46

C46 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

C3581

0.1UF/10V,X5R

C0402_BGA

12

C50

C50 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C47

C47 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

colay lihong 0424

VHCORE

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

PEG AND DDR

CORE SUPPLY

VSS_SENSE_VCCIO

SENSE LINES SVID

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

VCCP_SENSE VSSP_SENSE

12

C6

C6 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C28

C28 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

del R39 refer to Compal lihong 0504

+1_05VRUN +1_05VRUN

H_CPU_SVIDALRT#

add R453 R454 lihong 0514 del R453 R454 lihong 0503

del R453 R454 lihong 0724

VCCP_SENSE 40 VSSP_SENSE 40

12

C7

C7 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C29

C29 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

ns

12

R91

R91 130_F

130_F

r0402

1 2

R81 43_F r0402R81 43_F r0402

CAD Note: Place the PU resistors close to CPU

12

VHCORE

C17

C17 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

C30

C30 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

ns

12

PR312

PR312 100_F

100_F

r0402

12

PR313

PR313 100_F

100_F

r0402

VCCSENSE 42 VSSSENSE 42

Remove C18 C7 NC->Stuff lihong 0722

12

C8

C8 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

ns

12

C32

C32 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

ns

R89

R89 75_F

75_F

r0402

1 2

VR_SVID_ALERT# 42

VR_SVID_CLK 42

CAD Note: Place the PU resistors close to CPU

12

C34

C34 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

ns

VR_SVID_DATA 42

C3617

0.1UF/10V,X5R

C0402_BGA

12

C9

C9 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C31

C31 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

C3618

0.1UF/10V,X5R

C0402_BGA

12

C10

C10 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C33

C33 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

C3619

0.1UF/10V,X5R

C0402_BGA

12

C19

C19 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

C35

C35 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

C3620

0.1UF/10V,X5R

C0402_BGA

+1_05VRUN

8.65A

12

C11

Decoupling capacitors for Vccp rail

22uF/6.3V,X5R

[12+17PH] 0805, 22uF (644066-070)

c0805

[2+1PH] 330uF, 6mohm ESR (699013-021)

ns

+1_05VRUN

12

C36

C36 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

12

Move PC95 PC214 to PWM side lihong 0518

C37

C37 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

PC95 PC214 colay in top side lihong 0509

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A2

A2 Date:

Date:

Wednesday, September 12, 2012 64

5

4

3

2

Notebook R&D Division

CPU(POWER)

N480

Sheet of

1

7

A

Rev

1.2

5

A

4

3

2

1

GFXCORE +VCCSA

C3621

C3622

C3623

C3624

0.1UF/10V,X5R

C0402_BGA

iGPU

D D

GFXCORE

38A

12

C53

C53 22uF/6.3V,X5R

R3

R3 0_J

0_J

r0402

GPU

1 2

C C

+1_8VRUN

0.93A

22uF/6.3V,X5R

c0805

c0805 iGPU

iGPU

12

C58

C58 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

c0805 iGPU

iGPU

12

C83

C83 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

c0805 iGPU

iGPU

del reserved PC229 PC304

Decoupling capacitors for +Vcc_gfxcore rail [12+4PH] 0805, 22uF (644066-070) [2+2PH] 470uF, 4.5mohm ESR (699013-025)

del R7 lihong 0503

B B

12

C54

C54 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

c0805 iGPU

iGPU

12

C59

C59 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

c0805 iGPU

iGPU

12

C315

C315 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

ns

12

PC302

+

330uF/2V

tc7343

ns

12

PC177

PC177 820uF/2.5V

820uF/2.5V

+

Ced_6d3x8

iGPU

12

C196

C196 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

ns

Co_lay C88 ns lihong 0423

PC90(7343) C88(3528)->3528 0805 lihong 0502

C3624

0.1UF/10V,X5R

C0402_BGA

iGPU

12

C55

C51

22uF/6.3V,X5R

c0805

iGPU

12

C60

C61

22uF/6.3V,X5R

c0805

iGPU

ns

12

C316

C381

22uF/6.3V,X5R

c0805

iGPU

ns

470uF(1002-00254) ->

PC303

PC303 330uF/2V

330uF/2V

tc7343

ns

PC185

PC185 820uF/2.5V

820uF/2.5V

Ced_6d3x8

iGPU

12

330uF(1002-00252) lihong 0516

colay lihong 0424

12

C90

C197

10uF/6.3V,X5R

c0805

ns

+1_5V_CPU

C3625

12

C56

C56 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

c0805 iGPU

iGPU

12

C89

C89 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

C3625

0.1UF/10V,X5R

C0402_BGA

C3626

0.1UF/10V,X5R

C0402_BGA

12

C52

C52 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

c0805 iGPU

iGPU

12

C62

C62 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

c0805 iGPU

iGPU

12

C63

C63 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

ns

C91 C89 1uF/25V -> 1uF/6.3V lihong 0502

12

C91

C91 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

C3628

0.1UF/10V,X5R

C0402_BGA

U55G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

POWER

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

1.8V RAIL

VCCIO_SEL

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

del PC90 C88 lihong 0509 add C196 C197 place near CPU lihong 0514

PROCESSOR DRIVEN Vref PATH WAS STUFFED BY DEFAULT:

1 2

R251 0_J

nsr0402

删除Q42及预留的R252 R5385 lihong 0516 no DDR_WR_VREF01

GFXCORE 10,42 +1_5V_CPU 5,17,27,43,44,47,51,55,56,57 +1_5VSUS 5,20,39,43,57 +VCCSA 41 +1_8VRUN 16,17,40,43,44,47,49,51,52 +3VALW 5,11,12,13,15,16,17,18,23,25,26,27,31,35,38,39,43,44,47 +1_5V_CPU 5,17,27,43,44,47,51,55,56,57

add R532 R658 lihong 0514 del R532 R658 lihong 0503

AK35 AK34

AL1

B4

DDR_WR_VREF01

D1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

A19

Provides 1.0/1.05V selectable via VCCIO_SEL refer EDS PR235 should NC for chief river lihong

1 2

R532 R04020_J iGPUR532 R04020_J iGPU

1 2

R658 R04020_J iGPUR658 R04020_J iGPU

12

C65

C65 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C72

C72 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

VCCSA_SENSE

H_VCCP_SEL

PR235 100k_J nsr0402PR235 100k_J nsr0402

del 0ohm R470 lihong 0723

+V_SM_VREF_CNT

CAD Note: All traces starting with +V_SM_VREF* and DDR_WR_VREF* should have 20:20mils wherever possible

12

C66

C66 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C73

C73 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

1 2

GFX_VCC_SENSE 42 GFX_VSS_SENSE 42

12

C67

C67 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

+VCCSA

4.5A

T

C74

C74 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

C139 ns lihong 0423 C139 7343->3528 in top side lihong 0424

VCCSA_SELECT0 41 VCCSA_SELECT1 41

12

C68

C68 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

实测电流值(SNB)0.3857A lihong 0720

1

20MIL

TP130

12

Decoupling capacitors for +VccSA rail

C139

[1PH] 0603, 10uF (602433-075)

220UF/2.5V

+

[3] 0805, 10uF (644066-099)

TC3528

[1] 330uF, 6mohm ESR (699013-021)

ns

+3VALW

C69

C69 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

ictpad_c20

R515

R515 0_J

0_J

r0402

r0402 ns

ns

12

C70

C70 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

VCCSA_SENSE 41

+1_5V_CPU

12

C75

0.1UF/10V,X5R

c0402

1 2

max 5A

+V_SM_VREF_CNT

S3 circuit:- 1.5V input to IVB is gated & IVB Read Vref 0.75V is gated

+1_5V_CPU

move C71 to Page39 lihong 0509

Function

SNB HIGH

IVB HIGH

xxVccSA_Select[1] [[CPU PIN# C24 VID0 of VR ]]

0

PR128

PR128 1K_F

1K_F

r0402

PR139

PR139 1K_F

1K_F

r0402

dengrl

xxVccSA_Select[0] [[CPU PIN# C22 VID1 of VR ]]

0

1

VCCSA VR Vout

0.90V

0.725V

S

D

DDR_WR_VREF01

R5384

R5384 1K_J

1K_J

r0402

r0402 ns

ns

1 2

DRAMRST_CNTRL_PCH5,12

5

32

G

Q41

Q41 AO3424

AO3424

1

sot23-3

DDR_WR_VREF01_B4 20,57

Q41 footprint sot23_ld1_lp20 -> sot23-3 lihong 0620

CAD Note: Route with min. trace width of 10 mils

0.1uF capacitors need to be placed as close as possible to voltage divider

The FETs are needed in order to avoid potential leakage while system is in S3 state DRAMRST_CNTRL signal and FETs (with low Rdson) are required for S3 Power Reduction Circuitry. If the S3 Power Reduction Circuit isn’t implemented than these FETs can be unstuffed and R251 and R252 would have to be stuffed

4

3

SNB LOW

IVB LOW

2

1

0

1

0.80V

0.675V

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A2

A2 Date:

Date:

Wednesday, September 12, 2012 64

Notebook R&D Division

CPU(GRAPHICS POWER)

N480

Sheet of

1

A

Rev

1.2

8

5

A

4

3

2

1

D D

C C

B B

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

U55H

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

M34

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

T35 T34 T33 T32 T31 T30 T29 T28 T27 T26

N35 N34 N33 N32 N31 N30 N29 N28 N27 N26

L33 L30 L27

K35 K32 K29 K26 J34 J31

F34 F31 F29

U55I

VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A3

A3 Date:

Date:

Wednesday, September 12, 2012 64

CPU(GND)

Notebook R&D Division

N480

Sheet of

A

Rev

1.2

9

5

A

4

3

GFXCORE 8,42 VHCORE 7,42

U55E

2

1

D D

C C

B B

GFXCORE

R200

49.9_F

r0402

r0402 ns

ns

1 2

R198

49.9_F

r0402

r0402 ns

ns

1 2

CFG2 1:(Default) Normal Operation; Lane # definition matches socket pin map definition CFG2 0:Lane Reversed

CFG2

12

R55

R55 1K_F

1K_F

r0402

r0402 ns

ns

CGF[6：5] 11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG6 CFG5

12

R57

R57 1K_F

1K_F

r0402

r0402 ns

ns

CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion CFG7 0: PEG Wait for BIOS for training

CFG7

12

R62

R62 1K_F

1K_F

r0402

r0402 ns

ns

R184

49.9_F

r0402

r0402 ns

ns

1 2

CAD NOTE:Floating for probe use,

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

12

R58

R58 1K_F

1K_F

r0402

r0402 ns

ns

VHCORE

R191

49.9_F

r0402

r0402 ns

ns

1 2

R174

49.9_F

r0402

r0402 ns

ns

1 2

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

VAXG_VAL_SENSE

R149

49.9_F

r0402

r0402 ns

ns

1 2

VSSAXG_VAL_SENSE TP_H_CPU_RSVD3 TP_H_CPU_RSVD4

CAD NOTE:Floating for probe use,

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

Ivy_Bridge_rPGA_Rev0p7

mpga989_mcp_skt_37-5mm_sq_HR

CFG

VCC_DIE_SENSE

VSS_DIE_SENSE

RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7

RESERVED

RSVD_NCTF8 RSVD_NCTF9

RSVD_NCTF10

BCLK_ITP#

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

RSVD28 RSVD29 RSVD30 RSVD31

RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD51 RSVD52

BCLK_ITP

KEY

AH27 AH26

L7 AG7 AE7 AK2

W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AN35 AM35

AT2 AT1 AR1

B1

CLK_XDP_ITP_P CLK_XDP_ITP_N

1 1

TP45 20MIL ictv20_10TP45 20MIL ictv20_10 TP133 20MIL ictv20_10TP133 20MIL ictv20_10

1

TP40 20MIL ictv20_10TP40 20MIL ictv20_10

1

TP41 20MIL ictv20_10TP41 20MIL ictv20_10

CFG4

12

CGF4 1:Disabled; No Physical Display Port

R56

1K_J

attached to Embedded Display Port

r0402

ns

CGF4 0:Enabled; An external Display Port device is connected to the Embedded Display Port

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A3

A3 Date:

Date:

Wednesday, September 12, 2012 64

CPU(RESERVED)

Notebook R&D Division

N480

Sheet of

10

Rev

A

1.2

5

A

+ECVCC 25,26,35,37,38 VCCRTC 13,18,25 +3VRUN 5,12,13,14,15,16,17,18,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +5VRUN 12,18,22,25,29,30,32,34,35,40,42,43 +3VALW 5,8,12,13,15,16,17,18,23,25,26,27,31,35,38,39,43,44,47 +1_05VRUN 4,5,7,13,17,18,26,40,42,44,48,49,51,52

D D

1

RTC1

2

3

4

CN1

cns2_1d25_r

85204-02001

+3VALW

12

R269

R269 1K_J

1K_J

r0402

C C

Q19 Q20 footprint SOT23_ld1_h43 -> sot23-3 lihong 0627

IHDA_SYNC

IHDA_SDATAO

D1 footprint sot23_ld1_lp20 -> sot23-3 lihong 0620

+ECVCC

1

VCCRTC

W=20mils

1 2

R75 1K_J r0402R75 1K_J r0402

2

D1

D1 LBAT54CLT1G

LBAT54CLT1G

sot23-3

3

12

C96

C96 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

INTVRMEN H:Integrated VRM enable L:Integrated VRM disable INTVRMEN should always be pull high

+3VRUN

+5VRUN

1

3 2

D

Q19

Q19 BSS138-7

BSS138-7

sot23-3

1 2

R101 0_J nsr0402R101 0_J nsr0402

+5VRUN

1

3 2

D

Q20

Q20 BSS138-7

BSS138-7

sot23-3

1 2

R226 0_J nsr0402R226 0_J nsr0402

12

R237

R237 10K_J

10K_J

r0402

r0402 ns

+3VRUN

12

R239

R239 10K_J

10K_J

r0402

r0402 ns

ns

1 2

R189 33_J r0402R189 33_J r0402

R455

R455 1M_J

1M_J

r0402

1 2

R223 33_J r0402R223 33_J r0402

G

S

G

S

12

HDA_CODEC_SYNC 30

HDA_CODEC_SDATAOUT 30

4

R79 0_J r0402R79 0_J r0402

VCCRTC

del 0ohm R82 lihong 0723

1

TP17

1

TP18

1

TP19

1

TP20

1

TP22

SPI_CLK SPI_CS#0 SPI_CS#1

SPI_MOSI SPI_MISO

CO- LAYOUT

12

1 2

R80 330K_F r0402R80 330K_F r0402

20110712

20110621

The traces inside this

1 2

C95 15PF/50V,NPO c0402C95 15PF/50V,NPO c0402

1 2

C98 15PF/50V,NPO c0402C98 15PF/50V,NPO c0402

1 2

R76 20K_F r0402R76 20K_F r0402

1 2

R77

R77 1M_J

1M_J

R78 20K_J r0402R78 20K_J r0402

r0402

CRB 20K

12

C97

C97 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C99

C99 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

block should be wider.

RTC_32KX1

4

Y2

32.768KHZ

y_4p_smd8038

1

2 3

RTC_32KX2_R

21

GP1

GP1 OPEN_JUMP_OPEN2

OPEN_JUMP_OPEN2

OPEN2

HDA_SPKR30

HDA_CODEC_SDATAIN030

20MIL

ictv20_10

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

NOTE:Use one 33- Ω series-resistor per device if using two SPI devices and place it close to the devices. No series-resistor required if a single device is used.

Y6

y_4p_smd7014

32.768KHZ

ns

1

4

2 3

6 mils

R74

R74 10M_J

10M_J

r0402

RTCRST# SRTCRST# SM_INTRUDER# INTVRMEN

IHDA_BITCLK IHDA_SYNC HDA_SPKR IHDA_RESET#

HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

IHDA_SDATAO

HDA_DOCK_EN# HDA_DOCK_RST#

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

3

RTC_32KX1RTC_32KX2_R

RTC_X1

U54A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

RTCIHDA

JTAG

SPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

C38

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36

LPC_DRQ#0

K36 V5

INT_SERIRQ

AM3

SATA_RXN0

AM1

SATA_RXP0

AP7

SATA_TXN0

AP5

SATA_TXP0

AM10 AM8 AP11 AP10

SATA Port available

AD7

HM76 0~1 SATA3.0 2~5 SATA2.0

AD5 AH5

HM70 0 SATA3.0 2,4,5 SATA2.0

AH4 AB8

AB10 AF3 AF1

Y7

SATA_RXN1

Y5

SATA_RXP1

AD3

SATA_TXN1

AD1

SATA_TXP1

Y3 Y1 AB3 AB1

Y11 Y10

SATA_COMP

AB12 AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3 V14 P1

BBS_BIT0

LPC_AD0 25,27 LPC_AD1 25,27 LPC_AD2 25,27 LPC_AD3 25,27

LPC_FRAME# 25,27

1

TP16

1

TP15

INT_SERIRQ 25

SATA_RXN0 34 SATA_RXP0 34 SATA_TXN0 34 SATA_TXP0 34

SATA_RXN1 34 SATA_RXP1 34 SATA_TXN1 34 SATA_TXP1 34

1 2

R90 37.4_F r0402R90 37.4_F r0402

1 2

R93 49.9_F r0402R93 49.9_F r0402

1 2

R13 750_F r0402R13 750_F r0402

del R490 R460 lihong 0503

20MIL

20MIL 20MIL

20MIL

2

ictv20_10

ictv20_10 ictv20_10

ictv20_10

+1_05VRUN

HDD

ODD

SATA0GPSATA0GP

del mSATA lihong 0419

+3VRUN

12

R94

R94 10K_J

10K_J

del R100 lihong 0504

r0402

No HDD LED lihong 0510

BBS_BIT0

GPIO19 internal PU

+3VRUN

HDA_SPKR

INTVRMEN

R5386 330K_F

r0402 ns

12

Stuff for No-reboot Low=Default High=No-reboot

INTVRMEN- Integrated SUS 1.05V VRM Enable High - Enable Internal VRs Low - Enable External VRs

1

R105

R105 1K_J

1K_J

r0402

r0402 ns

ns

12

IHDA_RESET#

+3VRUN

IHDA_BITCLK

C3635

C3635 10PF/50V,NPO

10PF/50V,NPO

C0402

1 2

ns

R109

R109 0_J

0_J

r0402

1 2

VCC0

B B

del R182 lihong 0503

+3VALW

Q21 STUFF->NC no WP lihong 0615

PCH_ROM_LOCK16

1 2

RTC_BAT1

+

-

RTCBAT with Cable

SPONGE_RTC1

SPONGE_RTC1 RTCBAT GLUE

RTCBAT GLUE

5

1 2

R96 33_J r0402R96 33_J r0402

1 2

R99 33_J r0402R99 33_J r0402

EMI add C3635 lihong 0509

VCC0

R110

R110 20K_J

20K_J

r0402

1 2

SPI_MISO SPI0_MISO_R

R115 33_J r0402R115 33_Jr0402

32

D

Q21

1

L2SK801LT1G

G

SOT23

S

ns

R73

R73 100k_J

100k_J

r0402

SPI_MISO SPI1_MISO_R

R123 33_J

WP#0

r0402

HDA_CODEC_RST# 30 HDA_CODEC_BITCLK 30

VCC0VCC0

W25Q23BVSSIG: Manufacture ID: EFh Device ID: 4016h VSCC code: 2005h

U7

1

SPI_CS#0

12

WP#0

12

ns

SPI_CS#1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

FLASH_SOIC-8_32Mbit

sop8_1d27_8

U11

1

CS#

2

DO/IO1

3

WP#/IO2

4

GND

FLASH_SOIC-8_32Mbit

sop8_1d27_8

ns

VCC

HOLD#/IO3

DI/IO0

SPI ROM

HOLD#/IO3

8 7 6

CLK

5

VCC0 VCC0

8

VCC

7 6

CLK

5

DI/IO0

12

C100

0.1UF/10V,X5R

c0402

R124 33_Jr0402R124 33_Jr0402 R170 33_Jr0402R170 33_Jr0402

12

C195

0.1UF/10V,X5R

c0402

ns

12

R106

3.3K_J

r0402

EMI add C3636 lihong 0509

12

SPI_CLKSPI0_CLK_R

12

SPI_MOSISPI0_MOSI_R

12

R118

3.3K_J

r0402

ns

12

R143 33_J r0402

R143 33_J r0402 R171 33_J r0402

R171 33_J r0402

ns

12

ns

C3636

C3636 10PF/50V,NPO

10PF/50V,NPO

C0402

1 2

ns

SPI_CLKSPI1_CLK_R SPI_MOSISPI1_MOSI_R

1 2

FW_HW16,25

R86 100_J r0402R86 100_J r0402

IHDA_SDATAO

Low (0) When this signals is sampled low on the rising edge of PWROK then the security measures defined in the Flash Descriptor will be in effect (default) High (1) If sampled high, the Flash Descriptor Security will be overridden

Note:This strap should only be asserted high using external pull-up in manufacturing/debug environments ONLY. Asserting the HDA_SDO high on the rising edge of PWROK will also halt Intel ME after chipset bring up and disable runtime Intel ME features.

12

ns one rom lihong 0910

4

3

R84

4.7K_J

r0402

+3VRUN+ECVCC

改为RUN电

12

R83

R83 1K_J

1K_J

r0402

1 2

R85 1K_J r0402R85 1K_J r0402

32

D

1

G

Q5

S

L2SK801LT1G

SOT23

IHDA_SDATAO

12

R87

R87 1K_J

1K_J

r0402

r0402 ns

ns

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TCK

1 2

R107 210_F r0402R107 210_F r0402

1 2

R111 210_F r0402R111 210_F r0402

1 2

R113 210_F r0402R113 210_F r0402

1 2

R108 100_F r0402R108 100_F r0402

1 2

R112 100_F r0402R112 100_F r0402

1 2

R114 100_F r0402R114 100_F r0402

1 2

R116 51_J r0402R116 51_J r0402

dengrl

INT_SERIRQ SATA0GP

BBS_BIT0

1 2

R102 10K_J r0402R102 10K_J r0402

1 2

R103 10K_J r0402R103 10K_J r0402

1 2

R104 1K_J nsr0402R104 1K_J nsr0402

+3VALW

+3VRUN

BBS_BIT0 - BIOS BOOT STRAP BIT 0

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A2

A2 Date:

Date:

Wednesday, September 12, 2012 64

2

Notebook R&D Division

PCH(HDA,JTAG,SPI,SATA)

N480

Sheet of

11

1

Rev

1.2

A

5

A

WIFI Port1->Port2 lihong 0615

PCI-E Port Table

Port

D D

Function

Port1 Un-used

WLAN

Port2

LAN

Port3

Port4 Un-used

Un-used

Port5

Un-used

Port6

Test point

Port7

Un-used

Port8

MINI_RXN327 MINI_RXP327

MINI_TXN327 MINI_TXP327

LAN_RXN131 LAN_RXP131

LAN_TXN131 LAN_TXP131

C103 0.1UF/10V,X5R c0402C103 0.1UF/10V,X5R c0402 C104 0.1UF/10V,X5R c0402C104 0.1UF/10V,X5R c0402

C101 0.1UF/10V,X5R c0402C101 0.1UF/10V,X5R c0402 C102 0.1UF/10V,X5R c0402C102 0.1UF/10V,X5R c0402

PCIE Port available HM76 1~8 HM70 1~4

ictpad_c20

20MIL

TP23

20MIL

20MIL 20MIL

20MIL

TP23 TP24

TP24 TP25

TP25 TP27

TP27

ictpad_c20

ictpad_c20 ictpad_c20

ictpad_c20

1 2 1 2

Close to PCH

1 1 1 1

C C

1 2

+3VALW

+3VRUN

CLK_PCIE_MINI#27

CLK_PCIE_MINI27

MINI_CARD_DET#27

CLK_PCIE_LAN#31

B B

del 0ohm R47 R48 R20 lihong 0723

CLK_PCIE_LAN31

LAN_CLK_REQ#31

ictpad_c20

ictpad_c20 ictpad_c20

ictpad_c20

+3VRUN

+3VALW

LAN_CLK_REQ#

+3VALW

R151 10K_J r0402R151 10K_J r0402

R477 10K_J r0402R477 10K_J r0402

1 2

R156 10K_J r0402R156 10K_J r0402

R145 10K_J r0402R145 10K_J r0402

20MIL

TP110

20MIL

TP111

R148 10K_J r0402R148 10K_J r0402

R150 10K_J r0402R150 10K_J r0402

R152 10K_J r0402R152 10K_J r0402

R476 10K_J r0402R476 10K_J r0402

R475 10K_J r0402R475 10K_J r0402

1 2

1 2 1 1

1 2

4

MINI_TXN3_C MINI_TXP3_C

LAN_TXN1_C LAN_TXP1_C

MINI_CARD_DET#

U54B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_DATA1

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

CL_CLK1

CL_RST1#

2

+3VRUN 5,11,13,14,15,16,17,18,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +3VALW 5,8,11,13,15,16,17,18,23,25,26,27,31,35,38,39,43,44,47 +VCCDIFFCLKN 18

E12

WAKE_SCI#

H14

SMB_CLK_SB

C9

SMB_DATA_SB

A12

DRAMRST_CNTRL_PCH

C8

SML0_CLK

G12

SML0_DATA

C13

LPD_SPI_INTR#

E14

SMB_THRM_CLK

M16

SMB_THRM_DATA

M7

T11

P10

dengrl N401 to GPU Thermal sensor change port to SM1CLK

DRAMRST_CNTRL_PCH 5,8

del 0ohm R266 R362 lihong 0723

M10

PEG_CLKREQ#

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

CLK_DMI_PCH# CLK_DMI_PCH

CLK_MCH_BCLK# CLK_MCH_BCLK

DREFCLK# DREFCLK

CLK_PCIE_SATA# CLK_PCIE_SATA

REF_14M_PCH

XTAL25_IN XTAL25_OUT

XCLK_RCOMP

CLK_EXP_N 5

CLK_EXP_P 5

refer to DG no eDP lihong 0504

CLK_PCI_FB 15

R154 90.9_F r0402R154 90.9_F r0402

R31 NC->Stuff lihong 0720

K43 F47 H47 K49

CLKOUTLEX0

CLKOUTLEX2

1

TP26

1 2

R31 R040222_JR31 R040222_J

1

TP30

1 2

R38 R040222_J

Configure Flex1 and Flex3 as 27MHZ 48MHZ lihong 0411

+5VRUN 11,18,22,25,29,30,32,34,35,40,42,43

SMB_CLK_SB

SMB_DATA_SB

1

TP112

1

TP113

20MIL

20MIL 20MIL

20MIL

+VCCDIFFCLKN

ictv20_10

ns

ictpad_c20

ictpad_c20 ictpad_c20

ictpad_c20

PCIE_REFCLKN 48

PCIE_REFCLKP 48

C140 18PF/50V,NPO

c0402

C152 18PF/50V,NPO

c0402

+3VALW

12

R119

R121

2.2k_J

r0402

3 4

Q6A

Q6A L2N7002DW1T1G

L2N7002DW1T1G

sot363

XTAL25_IN XTAL25_OUT

1 2

ns

GPU_27MHZ 49

1 2

ns

Cardreader_48MHZ 36

Title

Title Size

Size

Size A3

A3

A3 Date:

Date:

1

+3VRUN

12

+5VRUN

5

G

S

D

S

D

2

G

6 1

D

+3VALW

12

R141

2.2k_J

r0402

PEG_CLKREQ# WAKE_SCI#

LPD_SPI_INTR# SML0_CLK SML0_DATA

CLK_DMI_PCH#

CLK_DMI_PCH

CLK_MCH_BCLK#

CLK_MCH_BCLK

DREFCLK#

DREFCLK

CLK_PCIE_SATA# CLK_PCIE_SATA REF_14M_PCH

R153

R153 1M_J

1M_J

r0402

Document Number

Wednesday, September 12, 2012 64

R120

R122

2.2k_J

r0402

S

Q6B

Q6B L2N7002DW1T1G

L2N7002DW1T1G

sot363

12

R142

2.2k_J

r0402

1 2

R128 10K_J r0402R128 10K_J r0402

1 2

R130 10K_J r0402R130 10K_J r0402

1 2

R134 10K_J r0402R134 10K_J r0402

1 2

R136 2.2k_J r0402R136 2.2k_J r0402

1 2

R138 2.2k_J r0402R138 2.2k_J r0402

1 2

R125 10K_J r0402R125 10K_J r0402

1 2

R126 10K_J r0402R126 10K_J r0402

1 2

R127 10K_J r0402R127 10K_J r0402

1 2

R129 10K_J r0402R129 10K_J r0402

1 2

R131 10K_J r0402R131 10K_J r0402

1 2

R133 10K_J r0402R133 10K_J r0402

1 2

R135 10K_J r0402R135 10K_J r0402

1 2

R137 10K_J r0402R137 10K_J r0402

1 2

R139 10K_J r0402R139 10K_J r0402

2

DIMM0 DIMM1

SMB_CLK_SUS 20

SMB_DATA_SUS 20

EC Thermal Sensor

SMB_THRM_CLK 25,53 SMB_THRM_DATA 25,53

1 2

C106 18PF/50V,NPO

c0402

3

Y3

4

25MHZ

y_4p_smd3225

1

1 2

C105 18PF/50V,NPO

c0402

del 0ohm R155 R157 lihong 0723

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

PCH(PCI-E,SMBUS,CLK)

Notebook R&D Division

N480

Sheet of

12

+3VALW

Rev

1.2

A

5

A

4

3

2

+3VRUN 5,11,12,14,15,16,17,18,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +3VALW 5,8,11,12,15,16,17,18,23,25,26,27,31,35,38,39,43,44,47 VCCRTC 11,18,25 +1_05VRUN 4,5,7,11,17,18,26,40,42,44,48,49,51,52

1

D D

U54C

DMI_RXN[3:0]4

DMI_RXP[3:0]4

DMI_TXN[3:0]4

DMI_TXP[3:0]4

+1_05VRUN

1 2

R159 49.9_F r0402R159 49.9_F r0402

C C

SUS_PWR_DN_ACK

SUSACK#25

PM_SYSRST#

SYS_PWROK47

PM_PCH_PWROK47

1 2

R160 750_F r0402R160 750_F r0402

1 2

R162 0_J r0402R162 0_J r0402

1 2

R164 0_J nsr0402R164 0_J nsr0402

1 2

R167 0_J r0402R167 0_J r0402

1 2

R168 0_J r0402R168 0_J r0402

1 2

R169 0_J r0402R169 0_J r0402

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

SUSACK#_R

PM_SYSRST#_R

PWROK

DMI_COMP_R

RBIAS_CPY

del PCH_APWROK and R170 R171 connect PCH Pin L10 and L22 together lihong 0516

B B

DGPU_HOLD_RST# CT GPIO50 follow CRB

2011.09.16

PM_DRAM_PWRGD5

1 2

PM_RSMRST#25,26

SUS_PWR_DN_ACK25

PWRBTN#25,26

AC_PRESENT25

SUSACK# is an input signal to the PCH from the Embedded Controller (EC), acknowledging EC has completed preparations as signalled by SUSWARN#. This signal is only used on platforms that support the Deep S4/S5 state. SUSACK# and SUSWARN# can be tied together if EC does not want to involve in the handshake mechanism for the Deep S4/S5 state entry and exit.

R172 0_J r0402R172 0_J r0402

1 2

R474 0_J r0402R474 0_J r0402

AC_PRESENT

PM_RSMRST#_R

SUS_PWR_DN_ACK

PM_PWRBTN#_R

PE_GPIO0

PM_RI#

U54C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DSWODVREN

PCH_DPWROK_R

PM_CLKRUN#SYS_PWROK_RSYS_PWROK

PE_GPIO1

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_M#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

FDI_TXN[7:0] 4

DSWODVREN - On Die Deep S4/S5 VR Enable 1: Enable 0: Disable

FDI_TXP[7:0] 4

DSWODVREN

del R268 R349 R358 R360 R438 lihong 0503

PM_CLKRUN# PM_SYSRST#

PCIE_WAKE# PM_RI# PM_SLP_LAN# PE_GPIO0 SUS_PWR_DN_ACK AC_PRESENT PE_GPIO1

dengrl use PCH PCIE_WAKE#

PM_RSMRST# PWROK SYS_PWROK_R

1 2

R165 0_J r0402R165 0_J r0402

1 2

R166 0_J nsr0402R166 0_J nsr0402

PM_RSMRST#_R

PCIE_WAKE# 25,27,31

PM_CLKRUN# 25

1

TP31

PM_SLP_S5# 25,26

PM_SLP_S4# 25,26

PM_SLP_S3# 25,26,47

1

TP33

1

TP29

H_PM_SYNC 5

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

PCH_DPWROK 25

ictv20_10

20MIL

ictv20_10

20MIL

ictv20_10

20MIL

R161 330K_F r0402R161 330K_F r0402 R163 330K_F nsr0402R163 330K_F nsr0402

12 12

1 2

R173 8.2K_J r0402R173 8.2K_J r0402

1 2

R207 1K_J r0402R207 1K_J r0402

1 2

R175 10K_J r0402R175 10K_J r0402

1 2

R176 10K_J r0402R176 10K_J r0402

1 2

R177 10K_J nsr0402R177 10K_J nsr0402

1 2

R178 8.2K_J r0402R178 8.2K_J r0402

1 2

R180 10K_J r0402R180 10K_J r0402

1 2

R181 10K_J r0402R181 10K_J r0402

1 2

R568 10K_J r0402R568 10K_J r0402

1 2

R185 10K_J r0402R185 10K_J r0402

1 2

R186 10K_J nsr0402R186 10K_J nsr0402

1 2

R183 10K_J nsr0402R183 10K_J nsr0402

dengrl R183 stuff to NC

VCCRTC

+3VRUN

+3VALW

APWROK:For platforms not supporting Intel AMT it can be connected to PWROK

PWRBTN#:This signal is internally pulled-up in PCH to 3.3-V

A

standby through a weak pull-up resistor (24-k nominal)

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A3

A3 Date:

Wednesday, September 12, 2012 64

Date:

Wednesday, September 12, 2012 64

Date:

Wednesday, September 12, 2012 64

PCH(DMI,FDI,GPIO)

Notebook R&D Division

N480

Sheet of

Rev

1.2

13

5

A

4

3

+3VRUN 5,11,12,13,15,16,17,18,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53

2

1

D D

U54D

AR_INV_EN23 AR_LCDVCC_EN23

AR_BRADJ23

L_DDC_CLK23 L_DDC_DATA23

1 2

R187 2.37K_F r0402

ictv20_10

20MIL

AR_L_CLKIN-23 AR_L_CLKIN+23

AR_L_RXIN0-23

C C

ictpad_c20

AR_L_RXIN1-23 AR_L_RXIN2-23

20MIL

AR_L_RXIN0+23 AR_L_RXIN1+23 AR_L_RXIN2+23

20MIL

TP32

TP35

TP36

1

iGPU

L_DDC_CLK L_DDC_DATA

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

EMI lihong 0509

C3638

C3637

3.3PF/50V,NPO

C0402

1 2

ns

AR_BLUE22 AR_GREEN22 AR_RED22

B B

AR_DDCCLK22 AR_DDCDATA22

AR_HSYNC22 AR_VSYNC22

1 2

R196 1K_F r0402R196 1K_F r0402

the accuracy of R196 should better be 0.5% Place it close to PCH

C3638

3.3PF/50V,NPO

C0402

1 2

ns

C3639

3.3PF/50V,NPO

C0402

1 2

ns

CRT_IREF

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPB_HPD

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

CRT

DDPD_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

no HDMI

+3VRUN

1 2

R190 2.2k_J r0402

1 2

R188 2.2k_J r0402

1 2

R192 2.2k_J r0402

1 2

R193 2.2k_J r0402

1 2

R197 150_F r0402

1 2

R199 150_F r0402

1 2

R201 150_F r0402

+3VRUN

1 2

R194 2.2k_J r0402

1 2

R195 2.2k_J r0402

iGPU

iGPU iGPU

iGPU

iGPU iGPU

iGPU

iGPU iGPU

iGPU

add R194 R195 lihong 0507

L_DDC_CLK L_DDC_DATA

L_CTRL_CLK L_CTRL_DATA

AR_BLUE AR_GREEN AR_RED

AR_DDCCLK AR_DDCDATA

del R194 R195 lihong 0503

A

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A3

A3 Date:

Wednesday, September 12, 2012 64

Date:

Wednesday, September 12, 2012 64

Date:

Wednesday, September 12, 2012 64

Notebook R&D Division

PCH(LVDS,DDI)

N480

Sheet of

Rev

1.2

14

5

A

+3VRUN

1 2

R236 10K_J

r0402

INT_PIRQA#

D D

+3VRUN

R255 10K_J

r0402

C C

PCI_REQ#2

12

R341

4.7K_J

r0402

r0402 ns

ns

Boot BIOS Location:(GNT1,GNT0) 00:LPC 11:SPI 10:PCI 01:RESERVED

r0402

BBS_BIT011

B B

MPC OFF:R208 no stuff MPC ON :R208 stuff

PCI_GNT#3： Low = A16 swap override High = Default

RP11

1

8

2

7

3

6

4 5

10K_J

8p4r_79x39

RP18

1

8

2

7

3

6

4 5

10K_J

8p4r_79x39

add R255 lihong 0503

1 2

BBS_BIT0 BBS_BIT1

12

R204

R204 1K_J

1K_J

r0402

r0402 ns

ns

ictv20_10

PCLK_JIG27

20MIL

CLK_KBCPCI25

20MIL

CLK_PCI_FB12

12

R208

R208 1K_J

1K_J

r0402

r0402 ns

ns

12

R202

R202 1K_J

1K_J

r0402

r0402 ns

ns

EMI lihong 0507

PCI_REQ#1 INT_PIRQF# INT_PIRQB# PCI_REQ#0

INT_PIRQG# INT_PIRQC# INT_PIRQE# INT_PIRQH#

PCI_REQ#2

TP12920MIL

ictpad_c20

del USB3.0 lihong 0418

USB3.0 Port available HM76 1~4 HM70 1~2

del MXM_PWR_EN(GPIO54) and R35 lihong 0419

R34 Option stuff->ZPO lihong 0720

TP43

TP43 TP44

TP44

INT_PIRQD#16

1 2

R34 0_J

ODD_DA#25,34

R34 0_J

r0402

R466 STUFF->NC lihong 0615

1 2

R466 22_J r0402

1

1 2

R467 22_J r0402R467 22_J r0402

1

1 2

R468 22_J r0402R468 22_J r0402

ZPO

1

ns

4

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#

PCI_REQ#0 PCI_REQ#1 PCI_REQ#2

PCI_GNT#2 PCI_GNT#3

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

PCI_PME# BUF_PLT_RST#

CLK_PCI_JIG CLK_PCI_KBC CLK_PCI_FB_R

U54E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

RSVD

PCI

USB

USBRBIAS#

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

Each EHCI provides support for a USB 2.0 debug port on the second lowest port on

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS

AV5 AV10

AT8

USB2.0 Port available

AY5

HM76 0~5 8~13

BA2

HM70 0~3 8~11

AT12 BF3

C24

USB_PN0

A24

USB_PP0

C25

USB_PN1

B25

USB_PP1

C26 A26 K28

USB_PN_CD

H28

USB_PP_CD

E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

Change port for HM70 20111123

USB_PN9 USB_PP9 USB_PN10 USB_PP10 USB_PN12 USB_PP12

USBRBIAS

USB_OC#0

USB_OC#4

USB_OC#N

+3VRUN 5,11,12,13,14,16,17,18,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +3VALW 5,8,11,12,13,16,17,18,23,25,26,27,31,35,38,39,43,44,47

12

53

4

PLT_RST#PLT_RST#

74AHC1G08GW

sot353

12 12 12

C108

0.1UF/10V,X5R

c0402

12

R209

R209 100k_J

100k_J

r0402

USB_OC#0 USB_OC#4 USB_OC#N

BUF_PLT_RST#

R147 10K_J r0402R147 10K_J r0402 R213 10K_J r0402R213 10K_J r0402 R216 10K_J r0402R216 10K_J r0402

+3VALW

U9

1 2

Buffer to reduce loading on PLT_RST#

del Port2 no 3G lihong 0419

2

USB_PN0 58 USB_PP0 58 USB_PN1 58 USB_PP1 58

USB_PN_CD 36 USB_PP_CD 36

USB_PN9 33 USB_PP9 33 USB_PN10 27 USB_PP10 27 USB_PN12 23 USB_PP12 23

1 2

R203 22.6_F r0402R203 22.6_F r0402

USB_OC#0 58

USB_OC#4 33

USB PORT Function

PORT-0 PORT-1

USB2.0 Port

USB2.0 Port OC#0 PORT-2 PORT-3

CR PORT-4 PORT-5 PORT-6 PORT-7 PORT-8 PORT-9 PORT-10 PORT-11

Ext. Port

BLUE TOOTH

CAMERA PORT-12 PORT-13

1

+3VALW

PLT_RST# 5,25,26,27,31,48

OC pin

OC#4

each EHCI controller (Port 1 on EHCI #1 and Port 9 on EHCI #2).

PCLK_JIG CLK_KBCPCI

C3641

C3640

C3640 10PF/50V,NPO

10PF/50V,NPO

C0402

1 2

ns

C3641 10PF/50V,NPO

10PF/50V,NPO

C0402

1 2

ns

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A3

Wednesday, September 12, 2012 64

Date:

Notebook R&D Division

PCH(PCI,USB,NVRAM)

N480

Sheet of

Rev

1.2

15

A

5

A

D D

+3VALW

Dengrl R212 NC to Stuff

1 2

R211 1K_J r0402R211 1K_J r0402

1 2

R212 10K_J r0402R212 10K_J r0402

1 2

R214 10K_J r0402R214 10K_J r0402

+3VRUN

RP16

1

8

2

7

3

6

4 5

10K_J

8p4r_79x39

+3VRUN

C C

+3VRUN

1 2

+3VRUN

B B

+3VRUN

RP10

1

8

2

7

3

6

4 5

10K_J

8p4r_79x39

R512

R512 1K_J

1K_J

r0402

r0402 ns

ns

FDI_OVRVLTG

PR90

PR90 100k_J

100k_J

r0402

RP17

1

8

2

7

3

6

4 5

10K_J

8p4r_79x39

1 2

R225 10K_J nsr0402R225 10K_J nsr0402

1 2

R498 10K_J r0402R498 10K_J r0402

1 2

R307 10K_J r0402R307 10K_J r0402

1 2

R1801 200K_J r0402R1801 200K_J r0402

1 2

R227 10K_J r0402R227 10K_J r0402

1 2

R444 1K_J nsr0402R444 1K_J nsr0402

1 2

R229 1K_J nsr0402R229 1K_J nsr0402

1 2

R230 10K_J r0402R230 10K_J r0402

HOST_ALERT#1_R PCH_GPIO57 PM_LANPHY_ENABLE

CRIT_TEMP_REP# SATA_DET#4_R PCIE_RST# PCH_GPIO48

PCH_GPIO6 RUNTIME_SCI# INT_PIRQD# PCH_GPIO17

BMBUSY# H_A20GATE H_RCIN# STP_PCI#

SATA_PWR_EN#1_R PCH_GPIO22 EXTSMI# SATA_ODD_PRSNT#_R

SATA_PWR_EN#1_R PLL_ODVR_EN ICC_EN# PCH_GPIO27

R270 Option stuff->ZPO lihong 0720

del PARK-XT_PGOOD GPIO17 lihong 0419

INT_PIRQD# 15

PCH_GPIO27_EC25 PCH_GPIO28_EC25

R275 R281 NC->1K_J lihong 0615

del PCIE_RST# lihong 0516

PLL_ODVR_EN:PLL ON DIE VR ENABLE HIGH-------ENABLED (R444 ns) LOW--------DISABLED (R444 stuff)

ICC_EN#:Enable for CK505 Powergood LOW---------ENABLED HIGH--------DISABLED

4

BMBUSY#

EXTSMI#25

RUNTIME_SCI#25

PM_LANPHY_ENABLE

del R28 lihong 0418

ODD_DETECT#34

PCH_ROM_LOCK11

1 2

R275 1K_J R0402R275 1K_J R0402

1 2

R281 1K_J R0402R281 1K_J R0402

CRIT_TEMP_REP#25

FW_HW11,25

3

+3VRUN 5,11,12,13,14,15,17,18,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +3VALW 5,8,11,12,13,15,17,18,23,25,26,27,31,35,38,39,43,44,47 +1_8VRUN 8,17,40,43,44,47,49,51,52

U54F

1 2

R514 100_J r0402R514 100_J r0402

EXTSMI# PCH_GPIO6 RUNTIME_SCI# ICC_EN#

HOST_ALERT#1_R

1 2

R270 0_J

r0402

1 2

R242 0_J

ictpad_c20

ictpad_c20 ictpad_c20

ictpad_c20

SATA_DET#4_R

ZPO

PCH_GPIO17 PCH_GPIO22 PCH_ROM_LOCK PCH_GPIO27 PLL_ODVR_EN STP_PCI# SATA_PWR_EN#1_R SATA_ODD_PRSNT#_R FDI_OVRVLTG PCIE_RST# GFX_CRB_DET PCH_GPIO48

nsr0402

20MIL

20MIL 20MIL

20MIL

PCH_GPIO57

TP52

TP52 TP54

TP54 TP56

TP56 TP58

TP58 TP60

TP60 TP62

TP62 TP64

TP64 TP66

TP66 TP68

TP68 TP70

TP70 TP72

TP72 TP74

TP74 TP76

TP76 TP78

TP78

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

1

A4

VSS_NCTF_1

1

A44

VSS_NCTF_2

1

A45

VSS_NCTF_3

1

A46

VSS_NCTF_4

1

A5

VSS_NCTF_5

1

A6

VSS_NCTF_6

1

B3

VSS_NCTF_7

1

B47

VSS_NCTF_8

1

BD1

VSS_NCTF_9

1

BD49

VSS_NCTF_10

1

BE1

VSS_NCTF_11

1

BE49

VSS_NCTF_12

1

BF1

VSS_NCTF_13

1

BF49

VSS_NCTF_14

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

GPIO

NCTF

CPU/MISC

TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

2

R215

R215 10K_J

10K_J

r0402

1 2

C40 B41

RSVD_TESTMODE

C41

RSVD_USB3_P4#

A40

RSVD_USB3_P5#

P4

1

AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

TP98

PCH_THRMTRIP#_R INIT3_3V# NV_CLE

1

TP47

del R221 R222 R228 R224 lihong 0503

1

TP48

1

TP49

1

TP50

1

TP51

1

TP53

1

TP55

1

TP57

1

TP59

1

TP61

1

TP63

1

TP65

1

TP67

1

TP69

1

TP71

1

TP73

1

TP75

1

TP77

1

TP79

H_A20GATE 25

20MIL ictpad_c20

H_RCIN# 25

H_CPUPWRGD 5

R218 392_F r0402R218 392_F r0402

1

R5395 1K_J r0402R5395 1K_J r0402

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

ictpad_c20

20MIL

R371

R371 10K_J

10K_J

r0402

1 2

20MIL ictv20_10

TP46

1 2

+3VRUN

PR316

PR315

100k_J

r0402

1 2

ODD_EN 34

The drawback for routing PECI signal to PCH instead of EC is the loss of CPU turbo control

PM_THRMTRIP# 5,26

DMI & FDI Termination Voltage NV_CLE:Set to Vss when LOW Set to Vcc when HIGH

H_SNB_IVB#: Sandy bridge -- Vcc Ivy bridge -- Vss

+3VRUN

R502

R502 10K_J

10K_J

r0402

r0402 ns

ns

1 2

GFX_CRB_DET

R231

R231 100k_J

100k_J

r0402

1 2

1

+1_8VRUN

12

R217

2.2k_J

r0402

H_SNB_IVB# 5

A

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

PCH(GPIO,VSS_NCTF,RSVD)

Size

Document Number

Size

Document Number

Size

Document Number

A3

Date:

Wednesday, September 12, 2012 64

Notebook R&D Division

N480

Sheet of

Rev

1.2

16

5

A

+1_05VRUN

+1_05VRUN 4,5,7,11,13,18,26,40,42,44,48,49,51,52 +3VRUN 5,11,12,13,14,15,16,18,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +1_05VRUN 4,5,7,11,13,18,26,40,42,44,48,49,51,52 +1_8VRUN 8,16,40,43,44,47,49,51,52 +1_5V_CPU 5,8,27,43,44,47,51,55,56,57 +3VALW 5,8,11,12,13,15,16,18,23,25,26,27,31,35,38,39,43,44,47

2.04A

12

+1_05VRUN

30mA

C114

C114 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

l0805L6

l0805

C124

C124 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+3VRUN

R433 0_J

+1_05VRUN

30mA

12

C113

C113 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

L6 90nh/7.96MHZ,1.5A ns

90nh/7.96MHZ,1.5A ns

12

C123

C123 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

C3629

0.1UF/10V,X5R

C0402_BGA

D D

C0402_BGA

+1_05VRUN

50mA

C C

+1_05VRUN

2.7A

C3630

0.1UF/10V,X5R

C0402_BGA

12

C122

C122 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

B B

12

C115

C115 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+1_05VRUN

15mA

+V1.05S_VCCAPLL_EXP

12

C125

C125 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

1mA

C129

0.1UF/10V,X5R

1 2

c0402

+VCCAFDI_VRM1

1 2

4

12

C116

C116 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C323

C323 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

c0805 ns

ns

12

C126

C126 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+V1.05S_VCCAPLL_FDI

nsr0603

+V1.05S_VCC_DMI

15mA

U54G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

POWER

VCC CORE

VCCIO

FDI

3

CRTLVDS

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

DMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

+VCCA_LVDS

+VCCAFDI_VRM1

20mA

12

C110

0.01UF/25V,X7R

c0402

1 2

R234 0_J r0603

1 2

PR311 0_J

12

C121

0.1UF/10V,X5R

c0402

1 2

+VCCAFDI_VRM1

R240 0_J r0603R240 0_J r0603

12

C127

C127 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C327

C327 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

c0805 ns

ns

+V3.3M_VCCPSPI

12

C132

C132 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

2

12

C111

0.1UF/10V,X5R

c0402

C117

0.01UF/25V,X7R

c0402

iGPU

R238 0_J r0603R238 0_J r0603

1 2

C128

0.1UF/10V,X5R

C0402_BGA

12

C112

C112 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

+3VRUN

30mA

iGPU

r0402PR311 0_J

r0402

GPU

+VCCTX_LVDS

12

C118

0.01UF/25V,X7R

c0402

iGPU

1 2

60mA

1 2

L37 10uH/2MHz/1.15ohm l0805L37 10uH/2MHz/1.15ohm l0805

+1_8VRUN

60mA

C130

0.1UF/10V,X5R

c0402

1 2

R246 0_J r0603R246 0_J r0603

1 2

R247 0_J r0603

ns

WOL：R247

12

30mA

+1_05VRUN+V1.05S_VCC_DMI

+3VRUN

+3VALW

1

+VCCA_DAC

L4 220ohm/100MHZ

l0603

1 2

PR317 0_J

C119

C119 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

iGPU

+3VRUN

add PR314 for pureGPU lihong 0507

PR314

PR314 0_J

0_J

r0402

GPU

1 2

+1_05VRUN

nsr0402

L5 90nh/7.96MHZ,1.5A

l0805

+3VRUN

70mA

iGPU

20mA

70mA

+1_8VRUN

dengrl R246 Stuff to NC R247 NC to Stuff

+VCCAFDI_VRM1

1 2

R243 0_J r0603R243 0_J r0603

12

C364

C363

0.1UF/10V,X5R

c0402

1 2

C364 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+1_5V_CPU CT +1_5V_WLAN for easily layout 20110914

+1_5V_WLAN改为+1_5V_CPU lihong 0419

+1_5V_CPU

Stuff R246 lihong 0502

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Size

Document Number

Size

Document Number

Size

Document Number

A3

Date:

Wednesday, September 12, 2012 64

PCH(POWER1/2)

Notebook R&D Division

N480

Sheet of

A

Rev

1.2

17

5

A

D D

+3VALW

2mA

1 2

R249 0_J r0603R249 0_J r0603

del R233 lihong 0504

+3VRUN

20mA

+1_05VRUN

C C

+1_05VRUN

R262 0_J r0603R262 0_J r0603

B B

+1_05VRUN

R265 0_J r0603R265 0_J r0603

+1_05VRUN

L10

L10 10uH/2MHz/1.15ohm

10uH/2MHz/1.15ohm

l0805

Note: (For CPT) VCCSUS and VCCSUS1 are shorted in package. Default mode: INTERNAL VR C138, C324 unstuffed External VR mode: Stuff C138, C324 (decaps)

1.81A

C302

0.1UF/10V,X5R

C0402_BGA

1 2

R436 0_J

r0603 ns

12

+VCCDIFFCLK

12

+V1.05S_SSCVCC

+1_05VRUN

1 2

R271 0_J

r0603

C165

4.7uF/6.3V,X5R

c0603

1 2

+VCCPDSW

C134

0.1UF/10V,X5R

c0402

1 2

12

C141

C141 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C145

C145 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

L11

L11 10uH/2MHz/1.15ohm

10uH/2MHz/1.15ohm

l0805

l0805 ns

ns

12

C155

C155 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C159

C159 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

200mA

1 2

4

C135 Unstuff always for CPT

C135 0.1UF/10V,X5R

12

C137

C137 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C146

C146 22uF/6.3V,X5R

22uF/6.3V,X5R

c0805

+VCCAPLL_CPY_PCH

12

C330

C330 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

c0805 ns

ns

+1_05VRUN

R267 0_J

R473 0_J

V_CPU_IO

C166

0.1UF/10V,X5R

c0402

20mA

12

r0603

12

C167

0.1UF/10V,X5R

c0402

1 2

+1_05VRUN

nsc0402

12

C147

C147 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+VCCDIFFCLKN

163mA

12

nsr0603

12

C168

C168 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

1 2

R435 0_J

r0603 ns

PCH_VCCDSW

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

30mA

+1_05VRUN

12

C138

C138 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

c0402 ns

ns

12

C157 0.1UF/10V,X5R

12

C162

C162 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

C164 0.1UF/10V,X5R

c0402

12

C148

C148 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

+VCCRTCEXT

c0402

+VCCAFDI_VRM1

+V1.05S_VCCA_A_DPL +V1.05S_VCCA_B_DPL

50mA

+VCCDIFFCLK

+V1.05S_SSCVCC

150mA

12

+V1.05M_VCCSUS

1 2

C324 1uF/6.3V,X5R

nsc0402

VCCRTC

C169

0.1UF/10V,X5R

c0402

1 2

+VCCACLK

+VCCSUS1

C149

C149 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

VCCSST

C170

0.1UF/10V,X5R

c0402

1 2

3

+1_05VRUN 4,5,7,11,13,17,26,40,42,44,48,49,51,52 +3VALW 5,8,11,12,13,15,16,17,23,25,26,27,31,35,38,39,43,44,47 +3VRUN 5,11,12,13,14,15,16,17,20,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +5VRUN 11,12,22,25,29,30,32,34,35,40,42,43 VCCRTC 11,13,25 +5VALW 29,33,35,38,40,41,43,44,47,58 +VCCDIFFCLKN 12

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

30mA

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA USB

CPURTC

HDA

VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5]

VCC3_3[1] VCC3_3[8] VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12] VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2] VCCIO[3] VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

N26 P26 P28 T27 T29

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

+VCCA_USBSUS +3VALW

30mA 30mA 120mA

20mA 20mA 20mA

12

+1_05VRUN

POWER

U54J

+1_05VRUN

12

C133

C133 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C136

0.1UF/10V,X5R

c0402

C144 1uF/6.3V,X5R nsc0402C144 1uF/6.3V,X5R nsc0402

1

C158

C158 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

C229

0.1UF/10V,X5R

C0402_BGA

12

R253 0_J

r0603

12

+1_05VRUN

1 2

TP128 20MIL ictv20_10TP128 20MIL ictv20_10

12

C150

C150 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C153

0.1UF/10V,X5R

c0402

12

C154

0.1UF/10V,X5R

c0402

+1_05VRUN

450mA

C407

0.1UF/10V,X5R

C0402_BGA

+V1.05S_VCCAPLL_SATA3

+VCCAFDI_VRM1

12

C163

C163 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

C406

0.1UF/10V,X5R

C0402_BGA

15mA

12

+3VALW

2

+1_05VRUN +V1.05S_VCCA_A_DPL

1 2

L8 10uH/2MHz/1.15ohm

l0805

420mA

L9 10uH/2MHz/1.15ohm

10mA

+3VALW

12

R254 0_J

C142

0.1UF/10V,X5R

c0402

r0603

60mA

70mA

R260 0_J r0603R260 0_J r0603

R261 0_J r0603R261 0_J r0603

12

VCCAPLLSATA

1.05 V analog power supply for SATA PLL. This power is supplied by core well. This rail requires an LC filter when power is supplied from an external VR. NOTE: This pin can be left as no connect

+1_05VRUN

del reserved C331 L12 R635 refer to TCL lihong 0504

1 2

R273 0_J r0603R273 0_J r0603

C171

C171 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

CAP5

+

220uF/2.5V

tc3528

tc3528 ns

ns

1 2

l0805

80mA

R263 0_J r0603R263 0_J r0603

C156

0.1UF/10V,X5R

c0402

1

Co_lay

12

CAP4

+

220uF/2.5V

tc3528

tc3528 ns

ns

Co_lay

+3VALW

D2

D2 LBAT54HT1G

LBAT54HT1G

SOD323

2 1

R256 10_J r0402R256 10_J r0402

12

C143

0.1UF/10V,X5R

c0402

+3VALW

+3VRUN

12

TP131 20MIL ictv20_10TP131 20MIL ictv20_10

+3VALW+VCCSUSHDA

12

C161

C161 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C190

C190 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

+3VRUN

D3

D3 LBAT54HT1G

LBAT54HT1G

SOD323

2 1

R259 10_Jr0402R259 10_Jr0402

12

C151

C151 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+3VRUN

12

C179

C179 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C191

C191 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C80

C80 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+V1.05S_VCCA_B_DPL

12

C81

C81 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+5VALW

12

1

+5VRUN

A

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A2

A2 Date:

Date:

Wednesday, September 12, 2012 64

5

4

3

2

Notebook R&D Division

PCH(POWER2/2)

N480

Sheet of

1

Rev

1.2

18

5

A

U54H

H5

D D

C C

B B

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

4

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

3

U54I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

CPT_PPT_Rev_0p7

BGA989_PCH_25X25

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

2

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A3

A3 Date:

Wednesday, September 12, 2012 64

Date:

Wednesday, September 12, 2012 64

Date:

Wednesday, September 12, 2012 64

1

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

PCH(GND)

Notebook R&D Division

N480

Sheet of

19

Rev

1.2

A

1

M_A_A[15:0]6

A A

M_A_BS06 M_A_BS16 M_A_BS26 M_CS#06 M_CS#16 M_CLK_DDR06 M_CLK_DDR#06 M_CLK_DDR16 M_CLK_DDR#16 M_CKE06 M_CKE16 M_A_CAS#6 M_A_RAS#6

R279 10K_J r0402R279 10K_J r0402 R280 10K_J r0402R280 10K_J r0402

B B

12 12

M_A_WE#6

SMB_CLK_SUS12 SMB_DATA_SUS12

M_ODT06 M_ODT16

SMBus Address: A0H(W)/A1H(R)

M_A_DQS[7:0]6

M_A_DQS#[7:0]6

C C

2

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

SA0_DIM0 SA1_DIM0

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

CN2A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

80011-1021

ddr_as0a626_u2sn_7f

3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

5

M_A_DQ1

7

M_A_DQ0

15

M_A_DQ3

17

M_A_DQ2

4

M_A_DQ5

6

M_A_DQ4

16

M_A_DQ7

18

M_A_DQ6

21

M_A_DQ8

23

M_A_DQ9

33

M_A_DQ10

35

M_A_DQ11

22

M_A_DQ13

24

M_A_DQ12

34

M_A_DQ15

36

M_A_DQ14

39

M_A_DQ16

41

M_A_DQ17

51

M_A_DQ18

53

M_A_DQ19

40

M_A_DQ21

42

M_A_DQ20

50

M_A_DQ22

52

M_A_DQ23

57

M_A_DQ25

59

M_A_DQ24

67

M_A_DQ31

69

M_A_DQ30

56

M_A_DQ28

58

M_A_DQ29

68

M_A_DQ27

70

M_A_DQ26

129

M_A_DQ36

131

M_A_DQ37

141

M_A_DQ35

143

M_A_DQ34

130

M_A_DQ32

132

M_A_DQ33

140

M_A_DQ38

142

M_A_DQ39

147

M_A_DQ45

149

M_A_DQ44

157

M_A_DQ43

159

M_A_DQ42

146

M_A_DQ41

148

M_A_DQ40

158

M_A_DQ46

160

M_A_DQ47

163

M_A_DQ52

165

M_A_DQ49

175

M_A_DQ54

177

M_A_DQ55

164

M_A_DQ48

166

M_A_DQ53

174

M_A_DQ51

176

M_A_DQ50

181

M_A_DQ61

183

M_A_DQ60

191

M_A_DQ62

193

M_A_DQ63

180

M_A_DQ56

182

M_A_DQ57

192

M_A_DQ59

194

M_A_DQ58

DIMM_0

4

M_A_DQ[63:0] 6

5

+1_5VSUS 5,8,39,43,57 +3VRUN 5,11,12,13,14,15,16,17,18,22,23,25,26,27,30,31,32,34,35,36,39,40,41,42,43,44,47,48,49,51,53 +0_75VRUN 39,43,47

DDR3_DRAMRST#5

+V_VREF_DQ_DIMM08,57 +V_VREF_CA_DIMM057

CAD Note: All VREF traces should have 10 mil trace width

CAP6 ns lihong 0423

12

+

PC28

PC28 220uF/6.3V

220uF/6.3V

tc3528

ns

12

+

CAP6

CAP6 330uF/2V

330uF/2V

tc7343

ns

+3VRUN

12

C172

2.2UF/6.3V,X5R

c0603

TS#_DIMM32

12

+V_VREF_DQ_DIMM0

12

C177

2.2UF/6.3V,X5R

c0603

c0603 ns

ns

+1_5VSUS

12

C184

C184 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

6

12

C173

0.1UF/10V,X5R

c0402

1 2

R277 0_J

12

C185

C185 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

12

C178

0.1UF/10V,X5R

c0402

C175

2.2UF/6.3V,X5R

c0603

c0603 ns

ns

+1_5VSUS

TS#_DIMM0

nsr0402

C176

0.1UF/10V,X5R

c0402

12

C186

C186 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

CN2B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

80011-1021

ddr_as0a626_u2sn_7f

12

C187

C187 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

7

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

NPTH1 NPTH2

VTT1 VTT2

G1 G2

12

C188

C188 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

8

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

205 206

203 204

207 208

12

C189

C189 10uF/6.3V,X5R

10uF/6.3V,X5R

c0805

+0_75VRUN

Place this cap between two DIMM

Place these Caps near So-DIMM0

2A

+1_5VSUS

4

12

C194

0.1UF/10V,X5R

c0402

12

C192

0.1UF/10V,X5R

c0402

3

12

C193

0.1UF/10V,X5R

c0402

C182

C182 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+0_75VRUN

12

C183

C183 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

+0_75VRUN

12

C216

0.1UF/10V,X5R

c0402

D D

1

12

C180

C180 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C181

C181 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

2

12

C395

0.1UF/10V,X5R

c0402

Colay

+1_5VSUS

12

C394

C394 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

5

12

C393

C393 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C391

C391 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

12

C392

C392 1uF/6.3V,X5R

1uF/6.3V,X5R

c0402

Bitland Information Techonogy Co.,Ltd.

Bitland Information Techonogy Co.,Ltd. Notebook R&D Division

Notebook R&D Division

Title

Title Size

Document Number

Size

Document Number

Size

Document Number

A3

A3 Date:

Date:

Wednesday, September 12, 2012 64

6

Wednesday, September 12, 2012 64

7

DDR3(SO-DIMM_0) 1/2

Notebook R&D Division

N480

Sheet of

Rev

1.2

20

8

LENOVO N480 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual