Lenovo MTQ45MK Schematic
5
4
3
2
1
Model Name: PANDA(MTQ45MK-LE)
SHEETTITLE
01
COVER SHEET
02
DD
CC
BB
BOM & PCB MODIFY HISTORY
03
LGA775_A
04
LGA775_B
05
LGA775_C
06
LGA775_DATX,SPI(BIOS),MECH HOLD
07
GMCH-HOST,PCIE,DMI
08
GMCH-DDRIII
09
GMCH-VGA,MISC
10
GMCH-GND
11
GMCH-POWER
12
DDRIII CHANNEL A
13
DDRIII CHANNEL B
14
DDRIII TERMINATION
15
SWITCH&DVI
16
PCIE SLOT X16,X1
17
ICH10-PCI,PCIE,USB,DMI
18
ICH10-HOST,HDA,LAN,RTC,SPI,LPC,SATA
19
ICH10-POWER,GND
20
PCI SLOT
21
CKG IDT CV184
22
SIO SCH5617, TH, FDD
23
COM, KB/MS, LPT
WPCT200AA, ST19WP18
24
25
FRONT PANEL,BUZZER
Revision 1.0
SHEETTITLE
28
DISCRETE POWER 1
29
DISCRETE POWER 2
30
VCORE PWM_NCP5392
31
AUDIO CODEC
32
AUDIO JACK
33
34
INTEL 82567LM/LF
NB&SB for GPIO LIST & STRAP
35
Other GPIO LIST & STRAP
36
POWER DELIVERY
37
38
POWER SEQUENCE
39
BOM & PCB MODIFY HISTORY
40
41
42
Example Fab Drawing Note
Trace Width
(mils)
BEARLAKE Impedance Requirements by Interface
Interface
FSB(ALL)
Controller Link 50 ohm, single-ended
PCI Express*2.0
DMI
VGA
Differential
ImpedanceTolerance
Spacing
(mils)
4
6.5
7.5
9.5
4
4.5
5585 ohm, differential
50 ohm, single-ended15%
NA
NA
40 ohm, single-ended
NA
37 ohm, single-ended
NA
32 ohm, single-ended
8
95 ohm, differential
7.5
90 ohm, differential
Impedance Required
4x signals 42Ω others 50Ω, single-ended
85 ohm, single-ended
95 ohm, differential
37 ohm, single-ended at (G)MCH breakout,
then 50 ohm single-ended to VGA connector.
15%
15%
15%
20%, reference only
20%, reference only
4-layer stack-up total thickness=59mils
SIGNAL LAYER
PREPREG 1080HR
VCC Layer1.2 MILS (1 OZ COPPER)
CORE
GND Layer
PREPREG 1080HR
SIGNAL LAYER
1.9 MILS (Final thickness after plating)
2.7 MILS
47 MILS +8/-5 mils
1.2 MILS (1 OZ COPPER)
2.7 MILS
1.9 MILS (Final thickness after plating)
26
FRONT USB & REAL USB
27
FAN CONTROL
AA
5
4
ICH10 Impedance Requirements by Interface
Interface
PCI
Controller Link 50 ohm, single-ended
Miscellanceous
PCIE & DMI
SATA
USB
Impedance Required
50 ohm, single-ended
50 ohm, single-ended
95 ohm, differential
95 ohm, differential
90 ohm, differential
3
GIGABYTE TEHCHNOLOGIES , INC.
Title
SizeDocument NumberRev
C
2
Date:Sheet of
Cover Sheet
PANDA(MTQ45MK)
1
139Tuesday, September 09, 2008
1.0
5
4
3
2
1
BLOCK DIAGRAM
INTEL
LGA775(FSB800/1066/1333)
CLOCK GENERATOR
IDT V184
DD
PAGE=21
PCI EXPRESS X16
HOST(adds,control)
PAGE=3
HOST(data),VTT_GMCH
PAGE=4
Non-GTL+,Asynchronous Sideband,Misc. Control
PAGE=5
POWER,GND
PAGE=6
VRM11.1
CPU VRM 11.1
ON NCP5392
PAGE=30
PAGE=16
AGTL+ BUS
CHANNEL A(800/1066/1333]
Display Port
SW
PAGE=15
PAGE=15
Intel 82567 (PHY)
CC
Gigabit LAN
PAGE=34
PCI EXPRESS
GLCI & LCI
GMCH
Eaglelake-Q45
HOST,PCIE,DMI
PAGE=7
DDRIII
PAGE=8
VGA,MISC
PAGE=9
POWER,GND
PAGE=10,11
DMI BUS
MEMORY BUS
SATA BUS
DDR DIMM X Ⅲ2
PAGE=12
CHANNEL B(800/1066/1333]
DDR DIMM X Ⅲ2
PAGE=13
ICH10
PCI EXPRESS X1
PAGE=16
BB
FROUNT USB PORTS 6-9
PAGE=26
REAL USB PORTS 0-5
PAGE=26,34
HDA ADI_1882
PAGE=31
AUDIO JACK
PAGE=32
AA
DISCRETE POWER1
VCC1_15VDUALVTT_GMCH3VDUAL
DDRVTTDDR15V
PAGE=28
DISCRETE POWER2
VCC1_1_CLVCC1_5
PAGE=29
5
PCI EXPRESS
USB BUS
Azalia BUS
HOST,HDA,LAN,SATA,SPI
PAGE=17
PCI,PCIE,USB,DMI
PAGE=18
POWER,GND
PAGE=19
PAGE=20
4
PCI BUS
PCI SLOT X2
QST
FAN CONTROL
CPU FANSYS FANPWR FAN
PAGE=27
FRONT PANEL,BUZZER
PAGE=25
SERIAL ATA X4
RAID 0/1/0+1/5
PAGE=17
SPI BIOS
SPI BUS
PAGE=33
LPC BUS
LPC I/O SMSC5617
LTPCOMFDD
PAGE=22
COM, KB/MS, LPT
PAGE=23
3
2
GIGABYTE TEHCHNOLOGIES , INC.
Title
SizeDocument NumberRev
Custom
Date:Sheet of
BLOCK DIAGRAM
PANDA(MTQ45MK)
1
239Tuesday, September 09, 2008
1.0
5
HA[3..16][7]
DD
HA[17..35][7]
CC
BB
HA[3..16]
HA[17..35]
HA3
HA4
HA5
HA6
HA7
HA8
HA9
HA10
HA11
HA12
HA13
HA14
HA15
HA16
-HREQ0
-HREQ0[7]
-HREQ1
-HREQ1[7]
-HREQ2
-HREQ2[7]
-HREQ3
-HREQ3[7]
-HREQ4
-HREQ4[7]
-HADSTB0[7]
-HADSTB1[7]
-HADSTB0
HA17
HA18
HA19
HA20
HA21
HA22
HA23
HA24
HA25
HA26
HA27
HA28
HA29
HA30
HA31
HA32
HA33
HA34
HA35
-HADSTB1
VCORE
C6
22u/12/X5R/6.3V/M
4
LGA775-D:FOOTPRINT
LGA775A
L5
A<3>*
P6
A<4>*
M5
A<5>*
L4
A<6>*
M4
A<7>*
R4
A<8>*
T5
A<9>*
U6
A<10>*
T4
A<11>*
U5
A<12>*
U4
A<13>*
V5
A<14>*
V4
A<15>*
W5
A<16>*
N4
RSVD_3
P5
RSVD_4
K4
REQ<0>*
J5
REQ<1>*
M6
REQ<2>*
K6
REQ<3>*
J6
REQ<4>*
R6
ADSTB<0>*
AB6
A<17>*
W6
A<18>*
Y6
A<19>*
Y4
A<20>*
AA4
A<21>*
AD6
A<22>*
AA5
A<23>*
AB5
A<24>*
AC5
A<25>*
AB4
A<26>*
AF5
A<27>*
AF4
A<28>*
AG6
A<29>*
AG4
A<30>*
AG5
A<31>*
AH4
A<32>*
AH5
A<33>*
AJ5
A<34>*
AJ6
A<35>*
AC4
RSVD_1
AE4
RSVD_2
AD5
ADSTB<1>*
CPU-SK/775/S/15
C7
22u/12/X5R/6.3V/M
LGA775
(1/8)
TESTHI_8
TESTHI_9
TESTHI_10
GTLREF0
GTLREF1
GTLREF2
GTLREF_SEL
C8
22u/12/X5R/6.3V/M
ADS*
BNR*
RSP*
BPRI*
DBSY*
DRDY*
HITM*
IERR*
INIT*
LOCK*
TRDY*
BINIT*
DEFER*
MCERR*
AP<0>*
AP<1>*
BR<0>*
DP<0>*
DP<1>*
DP<2>*
DP<3>*
RESET*
RS<0>*
RS<1>*
RS<2>*
HIT*
-HADS
D2
-BNR
C2
-HIT
D4
H4
-BPRI
G8
-DBSY
B2
-DRDY
C1
-HITM
E4
-IERR
AB2
P3
-HLOCK
C3
-HTRDY
E3
AD3
-DEFER
G7
AB3
U2
U3
-BR0
F3
TESTHI8
G3
TESTHI9
G4
TESTHI10
H5
J16
H15
H16
J17
GTLREF0
H1
GTLREF1
H2
E24
H29
-CPURST
G23
-RS0
B3
-RS1
F5
-RS2
A3
C9
22u/12/X5R/6.3V/M
-HINIT
3
-HADS[7]
-BNR[7]
-HIT[7]
-BPRI[7]
-DBSY[7]
-DRDY[7]
-HITM[7]
-HINIT[17]
-HLOCK[7]
-HTRDY[7]
-DEFER[7]
-BR0[7]
-RS0[7]
-RS1[7]
-RS2[7]
22u/12/X5R/6.3V/M
-CPURST[4,7]
39p/4/NPO/50V/J
C11
22u/12/X5R/6.3V/M
NEXT VER UNSTUFF
MMBT2222A/SOT23/600mA/40/X
ICH_GPO18[17]
ICH_GPIO35[17]
R41K/4/X
MMBT2222A/SOT23/600mA/40
VTT_OR
VTT_OL
CRB 1.2 update
2
+12V
R1
8.2K/4/X
Q3
132
R61K/4/X
R957.6/4/1
R1357.6/4/1
3
D
GS
2
2N7002/SOT23/25pF/5/X
+12V
SOT23
R5
8.2K/4/X
Q4
132
R11
100/4/1
R15
100/4/1
GTLREF1
3
D
Q1
1
R3
576/4/1/X
SOT23
Q2
GS
2N7002/SOT23/25pF/5/X
2
1
R2
1.3K/4/1/X
SOT23
GPO35GPO18
0
SOT23
1
0
0
1
11
need remove GTLREF3&0 componet
R10 change to 50/4/1
GTLREF3
R80/4C1
C3
220p/4/NPO/50V/J
R120/4
C5
220p/4/NPO/50V/JC10
GTLREF0
GTLREF0
GTLREF1
GTLREF2
R1010/4
C2
1u/4/X5R/6.3V/K
R1410/4
C4
1u/4/X5R/6.3V/K
1
0.615*VTT0
0.63*VTT
0.65*VTT
0.667*VTT
R70/4/X
R160/4/X
GTLREF3GTLREF1
GTLREF3[5]
GTLREF2[5]
GTLREF2
VCORE
C12
22u/12/X5R/6.3V/M
VCORE
AA
5
C18
22u/12/X5R/6.3V/M
C13
22u/12/X5R/6.3V/M
C19
22u/12/X5R/6.3V/M
C14
22u/12/X5R/6.3V/M
C20
22u/12/X5R/6.3V/M
4
C15
22u/12/X5R/6.3V/M
C21
22u/12/X5R/6.3V/M
C16
22u/12/X5R/6.3V/M
C22
22u/12/X5R/6.3V/M
3
C17
22u/12/X5R/6.3V/M
C23
22u/12/X5R/6.3V/M
VTT_GMCH
VTT_OR
VTT_OL
2
R1762/4
R1862/4
R1962/4
7 8
5 6
3 4
1 2
GIGABYTE TEHCHNOLOGIES , INC.
Title
SizeDocument NumberRev
B
Date:Sheet of
RN1
51/8P4R/4
-CPURST
-IERR
-BR0
BPM0
BPM0[5]
TESTHI8
TESTHI9
TESTHI10
P4_LGA775-A
PANDA(MTQ45MK)
339Tuesday, September 09, 2008
1
1.0
5
HD[0..15]
HD[0..15][7]
DD
FSA
FSBSEL0
HD[16..31]
FSB
FSBSEL1
HD[16..31][7]
CC
01
1
10
0
0
1
1
0
BB
AA
5
-DBI0[7]
STBN0[7]
STBP0[7]
-DBI1[7]
STBN1[7]
STBP1[7]
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
-DBI0
STBN0
STBP0
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
FSC
FSBSEL2
1
0
0
0
-DBI1
STBN1
STBP1
B4
C5
A4
C6
A5
B6
B7
A7
A10
A11
B10
C11
D8
B12
C12
D11
A8
C8
B9
G9
F8
F9
E9
D7
E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
G11
G12
E12
Clock
100MHz
133MHz
166MHz
200MHz
266MHz0
333MHz2/2.4(3/4)001
D<0>*
LGA775
D<1>*
D<2>*
(2/8)
D<3>*
D<4>*
D<5>*
D<6>*
D<7>*
D<8>*
D<9>*
D<10>*
D<11>*
D<12>*
D<13>*
D<14>*
D<15>*
DB1<0>*
DSTBN<0>*
DSTBP<0>
D<16>*
D<17>*
D<18>*
D<19>*
D<20>*
D<21>*
D<22>*
D<23>*
D<24>*
D<25>*
D<26>*
D<27>*
D<28>*
D<29>*
D<30>*
D<31>*
DB1<1>*
DSTBN<1>*
DSTBP<1>
(4)
3.33/4(2.5/3)
2.5/3(2/3.33/4)
4
LGA775B
D<32>*
D<33>*
D<34>*
D<35>*
D<36>*
D<37>*
D<38>*
D<39>*
D<40>*
D<41>*
D<42>*
D<43>*
D<44>*
D<45>*
D<46>*
D<47>*
DBI<2>*
DSTBN<2>*
DSTBP<2>
D<48>*
D<49>*
D<50>*
D<51>*
D<52>*
D<53>*
D<54>*
D<55>*
D<56>*
D<57>*
D<58>*
D<59>*
D<60>*
D<61>*
D<62>*
D<63>*
DBI<3>*
DSTBN<3>*
DSTBP<3>
CPU-SK/775/S/15
CPUPWROK[5,17]
4
HD32
G16
HD33
E15
HD34
E16
HD35
G18
HD36
G17
HD37
F17
HD38
F18
HD39
E18
HD40
E19
HD41
F20
HD42
E21
HD43
F21
HD44
G21
HD45
E22
HD46
D22
HD47
G22
-DBI2
D19
G20
G19
D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
C20
A16
C17
r0402-2-nomask
-DBI2[7]
STBN2
STBN2[7]
STBP2[7]
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63
-DBI3
STBN3
STBP3
-BPM5
-BPM4
-BPM3
-BPM2
-BPM1
-BPM0
R5310/4/X
TCK
HD[32..47]
HD[48..63]
-DBI3[7]
STBN3[7]
STBP3[7]
XPT
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
2x30/[10NH8-000230-11R]/X
3
HD[32..47][7]
HD[48..63][7]
R20
1K/4/X
FSBSEL0[21]
FSBSEL1
FSBSEL1[21]
MP chnage to NOPAST Footprint
20
R531;R532;R533:r0402-2-nomask
XPT:H2X30-SMD-NOMSK
the risitro put in forks
XDP_CLK
-XDP_CLK
R5321K/4/X
R5330/4/X
TDO
-TRST
TDI
TMS
3
-CPURST
-SYS_RST
r0402-2-nomask
TCK
TDI
TDO
TMS
-TRST
-BPM0
-BPM1
-BPM2
-BPM3
-BPM4
-BPM5
-SYS_RST
FSBSEL0
FSBSEL1
FSBSEL2
BPM1
RN3
7 8
5 6
3 4
1 2
10K/8P4R/4
XDP_CLK[21]
-XDP_CLK[21]
VTT_ORVTT_OR
-CPURST[3,7]
-SYS_RST[17,25]
AE1
AD1
AF1
AC1
AG1
AJ2
AJ1
AD2
AG2
AF2
AG3
AC2
AK3
AJ3
G29
H30
G30
N5
C9
E7
AE6
D16
A20
E23
TCK
TDI
TDO
TMS
TRST*
BPM<0>*
BPM<1>*
BPM<2>*
BPM<3>*
BPM<4>*
BPM<5>*
DBR*
ITPCLK<0>
ITPCLK<1>
BSEL<0>
BSEL<1>
BSEL<2>
SPARE0
SPARE1
SPARE2
SPARE4
NC_DSS2
NC_DSS3
NC
BSEL0FSBSEL0
BSEL1
BSEL2FSBSEL2
LE request
LGA775D
LGA775
(4/8)
VTT_PWRGD
VTT_OUT_1
VTT_OUT_2
EXTBGREF
CPU-SK/775/S/15
BSEL0[9]
BSEL1[9]
BSEL2[9]FSBSEL2[21]
2
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_SEL
SFRANAD
SFRANAC
DCLKPH
ACLKPH
HFPLL
2
VTT_GMCH
A29
B25
B29
B30
C29
A26
B27
C28
A25
A28
A27
C30
A30
C25
C26
C27
B26
D27
D28
D25
D26
B28
D29
D30
VR_RDY
AM6
AA1
J1
VTTSEL
F27
F23
D14
E6
E5
J3
D1
Title
SizeDocument NumberRev
B
Date:Sheet of
VR_RDY[17,30]
VTT_OL
VTTSEL[29]
VTT_OR
VTT_OR
VTT_OR
VTT_OR
VTT_OR
VTT_GMCH
VTT_OR
C25
0.1u/4/X7R/16V/K
R211K/4
R2262/4
RN2
51/8P4R/4
R2351/4
R2451/4
R67762/4
R67862/4
R67962/4
R68062/4
RN5
7 8
5 6
3 4
1 2
470/8P4R/4
R2551/4
GIGABYTE TEHCHNOLOGIES , INC.
1
VTT_OR
C24
0.1u/4/Y5V/16V/Z
C26
0.1u/4/X7R/16V/K
0.1u/4/Y5V/16V/Z/X
VR_RDY
TMS
-BPM1
12
-BPM0
34
-BPM5
56
-BPM3
78
-BPM4
-BPM2
TCK
-TRST
TDI
TDO
FSBSEL0
FSBSEL1
FSBSEL2
VTTSEL
BPM1
P4_LGA775-C
PANDA(MTQ45MK)
1
VTT_OR
439Tuesday, September 09, 2008
C27
1.0
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