Lenovo Ideapad G50-70M Schematic

A

1 1

B

C

D

E

LCFC Confidential

AMD 2 Chip M/B Schematics Document

2 2

AMD Kaveri Processor with DDRIIIL + Bolton FCH

AMD GPU JET PRO/TOPAZ XT S3

www.rosefix.com

2013-09-25

3 3

REV:0.1

4 4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.

A

B

2013/05/17

2013/05/17

2013/05/17

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2012/12/21

2012/12/21

2012/12/21

D

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

Monday, December 16, 2013

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

E

1 52

1 52

1 52

0.1

0.1

0.1

A

LCFC confidential

File Name : ACLU7&8

AMD Jet Pro/ Topaz XT S3
23mmX23mm Dual Rank

Page 18~24

VRAM 256/128*16

DDR3L*4 4GB/2GB

1 1

Page 25~26

B

PCI-Express

8x Gen2

PEG 0~7

AMD FP3 APU

C

Memory BUS (DDR3L)
Dual Channel

1.35V DDR3L 1600 MT/s

D

DDR3L-SO-DIMM X2

Page 11,12

UP TO 8G x 2

E

eDP Conn

Int. Camera

Int. MIC Conn.

Page 28

USB2.0 Port3

HDMI Conn.

Page 29

HDMI

DP1

eDP x2 Lane

DP0

DPx4 Lane

DP2

For VGA translator

Kaveri
BGA 854 pin
32mm x 29mm

Page 5~10

x4 UMI Gen. 2

PCIe 1x

PCIe 1x

LAN Realtek

RTL8111GUL (1G)
RTL8106EUL (10M/100M)

Page 37

NGFF Card
WLAN&BT

Page 34

PCIe Port0

PCIe Port2
USB2.0 Port6

RJ45 Conn.

Page 38

5.0GT/s per lane

2 2

CRT Conn.

Page 30

USB2.0 1x

SATA HDD

Page 33

SATA ODD

Page 33

SPI ROM

8MB

Page 12

3 3

SATA Port0

SATA Port1

SATA Gen3

SATA Gen1

SPI BUS

HD Audio

Bolton M3

uFCBGA-656

24.5mm x 24.5mm

Page 11~15

USB 2.0 1x

USB 3.0 1x

USB 2.0 2x

USB2.0 1x

USB2.0 1x

USB2.0 1x

USB Left

USB 3.0 Port1
USB 2.0 Port1

USB 2.0 Port2

Page 32

USB right

USB2.0 Port10

Cardreader Realtek
RTS5170

USB2.0 Port4

Touch Screen

USB2.0 Port8

Page 28

SD/MMC Conn.

USB Board

Codec

Conexant CX20752

Page 36

SPK Conn.

Page 36

EC
ITE IT8586E-LQFP

Page 41

Sub-board ( 14' & 15")

POWER BOARD(for 14")

I/O Board(USB,Audio,Card Read)

HP&Mic Combo Conn.

USB Board

Touch Pad Int.KBD

Page 31 Page 31

Thermal Sensor
NCT7718W

Page 40

Sub-board ( Only 15")

POWER BOARD(for 15")

I/O Board(USB,Audio,Card Read)

4 4

ODD Board

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

C

2013/05/17

2013/05/17

2013/05/17

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2012/12/21

2012/12/21

2012/12/21

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

E

2 52

2 52

2 52

0.1

0.1

0.1

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

S5 S4/AC Only

S5 S4
Battery only

S5 S4
AC & Battery
don't exist

( O --> Means ON , X --> Means OFF )

+3VALW

B+

+1.5V

+5VALW

O

O

O

O

X X

O O O

OO

O

X

X X

X

+5VS

+3VS

+1.5VS

+VCCSA

+V1.5S_VCCP

+CPU_CORE

+VGA_CORE

+GFX_CORE

+1.8VS

+1.05VS

+0.75VS

+3.3VS_VGA

+1.5VS_VGA

+1.05VS_VGA

X

X

X

X

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

USB Port Table

USB 3.0USB 2.0 Port

XHCI

EHCI1

EHCI2

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

0

1

1

2

3

4

USB Port (Right Side)

2

USB Port (Left Side)

3

4
5

USB Port (Right Side)

6

7
8
9

10

Mini Card(WLAN)

11
12
13

HIGH

LOWLOWLOW

4 External
USB Port

Camera

Blue Tooth

HIGHHIGHHIGH

HIGH

HIGH

ONONON ON

ON

ON

ON

ON

OFF

ON

OFF

BOM Structure Table

@
100M@
14@
15@
AOAC@
GIGA@
JET@
ME@

DIS@
UMA@
TS@

TOPAZ@

A10@
A4@

EMC@

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

BTO ItemBOM Structure

Not stuff

100M LAN Part

For 14" part

For 15" part

AOAC support part

GIGA LAN Part

For AMD Jet GPU part

ME part(connector, hole)

Discrete GPU SKU part

UMA SKU part

For support touch panel sku part

For AMD Topaz GPU part

For APU Kaveri A10(19W)S IC KAVERI

For APU Kaveri A4(17W)S IC KAVERI

EMC components

SMBUS Control Table

Main

SOURCE

3 3

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

PM_SMBCLK
PM_SMBDATA

EC SM Bus1 address

Device

Smart Battery

4 4

IT8580EEC_SMB_CK1

+3VALW

IT8580E

+3VS

PCH

+3V_PCH

Address

0001 011X b

A

+3VS +3VS

2nd

BATT SODIMM

+3VALW

X

IT8580E

X

VGA

VGA

X

X X XV

V

V

X X X X X

EC SM Bus2 address

Device

Thermal Sensor EMC1403-2

Master VGA

Slave VGA

WLAN

Thermal

WiMAX

Sensor

X

X

X

V V

+3VS

V

X

+3VS

V

PCH SM Bus address

Address

1001_101xb

0x9E
0x9C

B

Device Address

DDR DIMM0

DDR DIMM2

PCH

V

+3V_PCH

+3V_PCH+3VS

CP
Module

XX

X

V

+3VS

PCIE PORT LIST

Port Device

1
2
3
4
5
6
7
8

1001 000Xb

1001 010Xb

C

LAN
WLAN

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/12/05

2012/12/05

2012/12/05

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/12/05

2014/12/05

2014/12/05

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

E

3 52

3 52

3 52

0.4

0.4

0.4

5

4

3

2

1

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE

Power-Up/Down Sequence

"Topaz" has the following requirements with regards to power-supply sequencing to

D D

avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/米s.
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10
before VDDC, VDDCI, and VMEMIO start to ramp up.
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≒ 50 mV/米s).
For power down, reversing the ramp-up sequence is recommended.

米

s

0 ~ 20ms

C C

VDDR3(+3VGS)

0 ~ 20ms

VDD_CT(+1.8VGS)

PCIE_VDDC(+0.95VGS)

10us min.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

PERSTb(GPU_RST#)

100ms min.

100us min.

REFCLK(CLK_PCIE_VGA)

B B

GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

MLPS Bit DescriptionStrap Name

ROM_CONFIG[0]

PS_0[1]

ROM_CONFIG[1]

PS_0[2]

ROM_CONFIG[2]

PS_0[3]

PS_0[4] N/A

AUD_PORT_CONN_
PINSTRAP[0]

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_A

PS_1[2]

STRAP_BIF_CLK_PM_EN

PS_1[3]

STRAP_TX_CFG_DRV_
FULL_SWING

PS_1[4]

PS_1[5]

STRAP_TX_DEEMPH_EN

PS_2[1]

PS_2[2]

PS_2[3]

STRAP_BIOS_ROM_EN

PS_2[4]

STRAP_BIF_VGA_DIS

PS_2[5]

PS_3[1]
PS_3[2]
PS_3[3]

PS_3[4]

PS_3[5]

N/A Reserved 1

BOARD_CONFIG[0]
BOARD_CONFIG[1]
BOARD_CONFIG[2]

AUD_PORT_CONN_
PINSTRAP[1]

AUD_PORT_CONN_
PINSTRAP[2]

Define the ROM type when STRAP_BIOS_ROM_EN = 1,
Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.

Reserved for internal use only. Must be 1 at reset.

The LSB (least significant bit) of the strap option that
indicates the number of audio-capable display outputs.

1 = PCIe GEN3 is supported.
0 = PCIe GEN3 is not supported.

0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled

N/A

0 = The transmitter half-swing is enabled
1 = The transmitter full-swing is enabled

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

N/A

Reserved.

N/A

Reserved.

0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system＊s VGA
controller.

Board configuration related strapping, such as for memory ID

000 = Hynix 256M*16
100 = Samsung 256M*16
010 = Micron 256M*16

Determines the maximum number of digital display audio endpoints
that will be presented to the OS and user.(Combine with PS_0[5])
111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.

001 = Hynix 128M*16
011 = Samsung 128M*16
111 = Micron 128M*16

VRAM ID config

VRAM ID PU resistor PD resistor

PS_3[3:1]

100

111

110

000

010

001

128Mx16

256Mx16

Memory Type

Hynix

H5TC2G63FFR-11C

Micron

MT41J128M16JT-093G

Samsung

K4W2G1646Q-BC1A

Hynix

H5TC4G63AFR-11C

Micron

MT41J256M16HA-093G

Samsung

K4W4G1646D-BC1A

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

100 = 256MB

0= Not support

1= Enable

0= Disable

111= No usable endpoints.

RV33 RV36

4.53K 4.99K

NC 4.75K

4.53K 2K

8.45K 2K

RECOMMENDED
SETTINGS

X

1

1

X

0

0Reserved for internal use only. Must be 0 at reset.

1

X

0

0

X

1

X

11

NC4.75K

10K3.4K

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/05

2013/08/05

2013/08/05

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

1

4 52

4 52

4 52

0.1

0.1

0.1

5

4

3

2

1

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

D D

PCIE_CRX_GTX_P05,17
PCIE_CRX_GTX_N05,17
PCIE_CRX_GTX_P15,17
PCIE_CRX_GTX_N15,17
PCIE_CRX_GTX_P25,17
PCIE_CRX_GTX_N25,17

GPU

C C

LAN

WLAN

+0.95VS_VDDP

B B

PCIE_CRX_GTX_P35,17
PCIE_CRX_GTX_N35,17
PCIE_CRX_GTX_P45,17
PCIE_CRX_GTX_N45,17
PCIE_CRX_GTX_P55,17
PCIE_CRX_GTX_N55,17
PCIE_CRX_GTX_P65,17
PCIE_CRX_GTX_N65,17
PCIE_CRX_GTX_P75,17
PCIE_CRX_GTX_N75,17

PCIE_CRX_DTX_P035
PCIE_CRX_DTX_N035

PCIE_CRX_DTX_P233
PCIE_CRX_DTX_N233

FCH

RC1 196_0402_0.5%

UMI_CRX_FTX_P012
UMI_CRX_FTX_N012
UMI_CRX_FTX_P112
UMI_CRX_FTX_N112
UMI_CRX_FTX_P212
UMI_CRX_FTX_N212
UMI_CRX_FTX_P312

1 2

PCIE_CRX_GTX_P[7..0] 5,17

PCIE_CRX_GTX_N[7..0] 5,17

UC1A

AG7

AN18

Y8
Y9

Y4
W5
W7
W8

U5

V4

U7

U8

T4

R5

R7

R8

P8

P7

P4

P5
M8
M7
M5
M4

L6

L5

L8

L9

J5

K4

J7

J8

H4

H5

AH4
AH3

AF6
AE8
AE7
AE5
AF4
AC9
AC8
AC6
AC5
AB9
AB8
AB4
AB5

AJ7
AJ8
AK6
AK7
AK5
AJ5
AL4
AK4

P_GFX_RXP0/RSVD

P_GFX_RXN0/RSVD

P_GFX_RXP1/RSVD

P_GFX_RXN1/RSVD

P_GFX_RXP2/RSVD

P_GFX_RXN2/RSVD

P_GFX_RXP3/RSVD

P_GFX_RXN3/RSVD

P_GFX_RXP4/RSVD

P_GFX_RXN4/RSVD

P_GFX_RXP5/RSVD

P_GFX_RXN5/RSVD

P_GFX_RXP6/RSVD

P_GFX_RXN6/RSVD

P_GFX_RXP7/RSVD

P_GFX_RXN7/RSVD

P_GFX_RXP8/RSVD

P_GFX_RXN8/RSVD

P_GFX_RXP9/RSVD

P_GFX_RXN9/RSVD

P_GFX_RXP10/RSVD

P_GFX_RXN10/RSVD

P_GFX_RXP11/RSVD

P_GFX_RXN11/RSVD

P_GFX_RXP12/RSVD

P_GFX_RXN12/RSVD

P_GFX_RXP13/RSVD

P_GFX_RXN13/RSVD

P_GFX_RXP14/RSVD

P_GFX_RXN14/RSVD

P_GFX_RXP15/RSVD

P_GFX_RXN15/RSVD

P_GPP_RXP0

P_GPP_RXN0

P_GPP_RXP1

P_GPP_RXN1

P_GPP_RXP2

P_GPP_RXN2

P_GPP_RXP3

P_GPP_RXN3

P_GPP_RXP4/RSVD

P_GPP_RXN4/RSVD

P_GPP_RXP5/RSVD

P_GPP_RXN5/RSVD

P_GPP_RXP6/RSVD

P_GPP_RXN6/RSVD

P_GPP_RXP7/RSVD

P_GPP_RXN7/RSVD

P_UMI_RXP0

P_UMI_RXN0

P_UMI_RXP1

P_UMI_RXN1

P_UMI_RXP2

P_UMI_RXN2

P_UMI_RXP3

P_UMI_RXN3

P_ZVDDP

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

PCIE_CRX_DTX_P0
PCIE_CRX_DTX_N0

PCIE_CRX_DTX_P2
PCIE_CRX_DTX_N2

UMI_CRX_FTX_P0
UMI_CRX_FTX_N0
UMI_CRX_FTX_P1
UMI_CRX_FTX_N1
UMI_CRX_FTX_P2
UMI_CRX_FTX_N2
UMI_CRX_FTX_P3
UMI_CRX_FTX_N3

KAVERI-2M186092H4467_BGA854

A10@

PCI EXPRESS

UMI GPP GRAPHICS

FP3 REV 0.52

P_GFX_TXP0/DP6_TXP4

P_GFX_TXN0/DP6_TXN4

P_GFX_TXP1/DP6_TXP5

P_GFX_TXN1/DP6_TXN5

P_GFX_TXP2/DP6_TXP6

P_GFX_TXN2/DP6_TXN6

P_GFX_TXP3/RSVD

P_GFX_TXN3/RSVD

P_GFX_TXP4/DP6_TXP0

P_GFX_TXN4/DP6_TXN0

P_GFX_TXP5/DP6_TXP1

P_GFX_TXN5/DP6_TXN1

P_GFX_TXP6/DP6_TXP2

P_GFX_TXN6/DP6_TXN2

P_GFX_TXP7/DP6_TXP3

P_GFX_TXN7/DP6_TXN3

P_GFX_TXP8/DP5_TXP0

P_GFX_TXN8/DP5_TXN0

P_GFX_TXP9/DP5_TXP1

P_GFX_TXN9/DP5_TXN1

P_GFX_TXP10/DP5_TXP2

P_GFX_TXN10/DP5_TXN2

P_GFX_TXP11/DP5_TXP3

P_GFX_TXN11/DP5_TXN3

P_GFX_TXP12/DP4_TXP0

P_GFX_TXN12/DP4_TXN0

P_GFX_TXP13/DP4_TXP1

P_GFX_TXN13/DP4_TXN1

P_GFX_TXP14/DP4_TXP2

P_GFX_TXN14/DP4_TXN2

P_GFX_TXP15/DP4_TXP3

P_GFX_TXN15/DP4_TXN3

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_GPP_TXP4/DP3_TXP0

P_GPP_TXN4/DP3_TXN0

P_GPP_TXP5/DP3_TXP1

P_GPP_TXN5/DP3_TXN1

P_GPP_TXP6/DP3_TXP2

P_GPP_TXN6/DP3_TXN2

P_GPP_TXP7/DP3_TXP3

P_GPP_TXN7/DP3_TXN3

P_UMI_TXP0

P_UMI_TXN0

P_UMI_TXP1

P_UMI_TXN1

P_UMI_TXP2

P_UMI_TXN2

P_UMI_TXP3

P_UMI_TXN3

P_ZVSS

PCIE_CTX_C_GRX_P[7..0]

PCIE_CTX_C_GRX_N[7..0]

FP3 Kaveri APU supports
PCIE Gen2, AC copling capactiors value 0.1U.
PCIE GEN3, AC copling capactiors value 0.22U

AB2

PCIE_CTX_GRX_P0

AB1

PCIE_CTX_GRX_N0

AB3

PCIE_CTX_GRX_P1

AA2

PCIE_CTX_GRX_N1

AA1

PCIE_CTX_GRX_P2

Y1

PCIE_CTX_GRX_N2

Y2

PCIE_CTX_GRX_P3

W2

PCIE_CTX_GRX_N3 PCIE_CTX_C_GRX_N3

V2

PCIE_CTX_GRX_P4

V1

PCIE_CTX_GRX_N4

V3

PCIE_CTX_GRX_P5

U2

PCIE_CTX_GRX_N5

U1

PCIE_CTX_GRX_P6

T1

PCIE_CTX_GRX_N6

T2

PCIE_CTX_GRX_P7

R2

PCIE_CTX_GRX_N7 PCIE_CTX_C_GRX_N7

P2
P1
P3
N2
N1
M1
M2
L2
K2
K1
K3
J2
J1
H1
H2
G2

AM2

PCIE_CTX_DRX_P0

AM1

PCIE_CTX_DRX_N0

AL2
AL1
AK2

PCIE_CTX_DRX_P2

AK1

PCIE_CTX_DRX_N2

AK3
AJ2
AJ1
AH1
AH2
AG2
AF2
AF1
AF3
AE2

AM9

UMI_CTX_FRX_P0

AM10

UMI_CTX_FRX_N0

AN8

UMI_CTX_FRX_P1

AN9

UMI_CTX_FRX_N1

AM7

UMI_CTX_FRX_P2

AM8

UMI_CTX_FRX_N2

AN6

UMI_CTX_FRX_P3

AM6

UMI_CTX_FRX_N3 UMI_CTX_FRX_N3_C

AM18

P_ZVSSP_ZVDDP

1 2

RC2 196_0402_0.5%

1 2

CC1 0.1U_0402_16V7-KDIS@

1 2

CC2 0.1U_0402_16V7-KDIS@

1 2

CC3 0.1U_0402_16V7-KDIS@

1 2

CC4 0.1U_0402_16V7-KDIS@

1 2

CC5 0.1U_0402_16V7-KDIS@

1 2

CC6 0.1U_0402_16V7-KDIS@

1 2

CC7 0.1U_0402_16V7-KDIS@

1 2

CC8 0.1U_0402_16V7-KDIS@

1 2

CC106 0.1U_0402_16V7-KDIS@

1 2

CC107 0.1U_0402_16V7-KDIS@

1 2

CC108 0.1U_0402_16V7-KDIS@

1 2

CC109 0.1U_0402_16V7-KDIS@

1 2

CC110 0.1U_0402_16V7-KDIS@

1 2

CC111 0.1U_0402_16V7-KDIS@

1 2

CC112 0.1U_0402_16V7-KDIS@

1 2

CC113 0.1U_0402_16V7-KDIS@

1 2

CC9 0.1U_0402_10V7-K

1 2

CC10 0.1U_0402_10V7-K

1 2

CC13 0.1U_0402_10V7-K

1 2

CC14 0.1U_0402_10V7-K

1 2

CC15 0.1U_0402_10V7-K

1 2

CC16 0.1U_0402_10V7-K

1 2

CC17 0.1U_0402_10V7-K

1 2

CC18 0.1U_0402_10V7-K

1 2

CC19 0.1U_0402_10V7-K

1 2

CC20 0.1U_0402_10V7-K

1 2

CC21 0.1U_0402_10V7-K

1 2

CC22 0.1U_0402_10V7-K

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P7

PCIE_CTX_C_DRX_P0
PCIE_CTX_C_DRX_N0

PCIE_CTX_C_DRX_P2
PCIE_CTX_C_DRX_N2

UMI_CTX_FRX_P0_C
UMI_CTX_FRX_N0_C
UMI_CTX_FRX_P1_C
UMI_CTX_FRX_N1_C
UMI_CTX_FRX_P2_C
UMI_CTX_FRX_N2_C
UMI_CTX_FRX_P3_C

PCIE_CTX_C_GRX_P[7..0] 5,17

PCIE_CTX_C_GRX_N[7..0] 5,17

PCIE_CTX_C_GRX_P0 5,17

PCIE_CTX_C_GRX_N0 5,17
PCIE_CTX_C_GRX_P1 5,17
PCIE_CTX_C_GRX_N1 5,17
PCIE_CTX_C_GRX_P2 5,17
PCIE_CTX_C_GRX_N2 5,17
PCIE_CTX_C_GRX_P3 5,17
PCIE_CTX_C_GRX_N3 5,17

PCIE_CTX_C_GRX_P4 5,17

PCIE_CTX_C_GRX_N4 5,17
PCIE_CTX_C_GRX_P5 5,17
PCIE_CTX_C_GRX_N5 5,17
PCIE_CTX_C_GRX_P6 5,17
PCIE_CTX_C_GRX_N6 5,17
PCIE_CTX_C_GRX_P7 5,17
PCIE_CTX_C_GRX_N7 5,17

PCIE_CTX_C_DRX_P0 35
PCIE_CTX_C_DRX_N0 35

PCIE_CTX_C_DRX_P2 33
PCIE_CTX_C_DRX_N2 33

UMI_CTX_FRX_P0_C 12
UMI_CTX_FRX_N0_C 12
UMI_CTX_FRX_P1_C 12
UMI_CTX_FRX_N1_C 12
UMI_CTX_FRX_P2_C 12
UMI_CTX_FRX_N2_C 12
UMI_CTX_FRX_P3_C 12
UMI_CTX_FRX_N3_C 12UMI_CRX_FTX_N312

GPU

LAN

WLAN

FCH

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

2012/12/05

2012/12/05

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/12/05

2014/12/05

2014/12/05

Title

APU PEG/PCIe/UMI

APU PEG/PCIe/UMI

APU PEG/PCIe/UMI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

1

5 52

5 52

5 52

0.4

0.4

0.4

1

2

3

4

5

UC1B

A A

B B

C C

+1.35V_APU_VDDIO

12

RC5
1K_0402_1%

+VREF_DQA

1

1

RC6

1K_0402_1%

12

+1.35V_APU_VDDIO +1.35V_APU_VDDIO

0.1U_0402_10V7-K

CC117

2

2

1000P_0402_50V7K

DDRA_MA[0..15]10

DDRA_BA0#10
DDRA_BA1#10
DDRA_BA2#10

DDRA_MA_DM[0..7]10

DDRA_DQS010
DDRA_DQS#010
DDRA_DQS110
DDRA_DQS#110
DDRA_DQS210
DDRA_DQS#210
DDRA_DQS310
DDRA_DQS#310
DDRA_DQS410
DDRA_DQS#410
DDRA_DQS510
DDRA_DQS#510
DDRA_DQS610
DDRA_DQS#610
DDRA_DQS710
DDRA_DQS#710

DDRA_CLK010
DDRA_CLK0#10
DDRA_CLK110
DDRA_CLK1#10

DDRA_CKE010
DDRA_CKE110

DDRA_ODT010
DDRA_ODT110

DDRA_CS0#10
DDRA_CS1#10

DDRA_RAS#10
DDRA_CAS#10

DDRA_RESET#10
DDRA_EVENT#10

@

1 2

RC21

RC4

CC116

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_MA14
DDRA_MA15

DDRA_BA0#
DDRA_BA1#
DDRA_BA2#

DDRA_MA_DM0
DDRA_MA_DM1
DDRA_MA_DM2
DDRA_MA_DM3
DDRA_MA_DM4
DDRA_MA_DM5
DDRA_MA_DM6
DDRA_MA_DM7

DDRA_DQS0
DDRA_DQS#0
DDRA_DQS1
DDRA_DQS#1
DDRA_DQS2
DDRA_DQS#2
DDRA_DQS3
DDRA_DQS#3
DDRA_DQS4
DDRA_DQS#4
DDRA_DQS5
DDRA_DQS#5
DDRA_DQS6
DDRA_DQS#6
DDRA_DQS7
DDRA_DQS#7

DDRA_CLK0
DDRA_CLK0# DDRB_CLK0#
DDRA_CLK1
DDRA_CLK1#

DDRA_CKE0
DDRA_CKE1

DDRA_ODT0
DDRA_ODT1

DDRA_CS0#
DDRA_CS1#

DDRA_RAS#
DDRA_CAS#
DDRA_WE#

DDRA_RESET#
DDRA_EVENT#
M_VREF

0_0402_5%

+VREF_DQA_C +VREF_DQB_C

1 2

MA_ZVDDIO

39.2_0402_1%

AB31

MA_ADD0

U33

MA_ADD1

U32

MA_ADD2

R30

MA_ADD3

T34

MA_ADD4

R31

MA_ADD5

R33

MA_ADD6

P33

MA_ADD7

P32

MA_ADD8

P30

MA_ADD9

AD34

MA_ADD10

P34

MA_ADD11

M30

MA_ADD12

AF33

MA_ADD13

M31

MA_ADD14

L32

MA_ADD15

AC33

MA_BANK0

AB30

MA_BANK1

M34

MA_BANK2

E13

MA_DM0

D18

MA_DM1

H22

MA_DM2

H27

MA_DM3

AG30

MA_DM4

AK26

MA_DM5

AK20

MA_DM6

AF14

MA_DM7

F34

MA_DM8

F14

MA_DQS_H0

G14

MA_DQS_L0

H19

MA_DQS_H1

J19

MA_DQS_L1

D24

MA_DQS_H2

E24

MA_DQS_L2

F28

MA_DQS_H3

E28

MA_DQS_L3

AJ30

MA_DQS_H4

AK30

MA_DQS_L4

AH24

MA_DQS_H5

AG24

MA_DQS_L5

AG19

MA_DQS_H6

AF19

MA_DQS_L6

AH14

MA_DQS_H7

AJ14

MA_DQS_L7

G31

MA_DQS_H8

F31

MA_DQS_L8

Y30

MA_CLK_H0

Y29

MA_CLK_L0

Y32

MA_CLK_H1

Y33

MA_CLK_L1

W33

MA_CLK_H2

W34

MA_CLK_L2

W30

MA_CLK_H3

W31

MA_CLK_L3

L33

MA_CKE0

L30

MA_CKE1

K34

MA_CKE2

J30

MA_CKE3

AH34

MA0_ODT0

AH33

MA0_ODT1

AE30

MA1_ODT0

AJ34

MA1_ODT1

AE31

MA0_CS_L0

AG31

MA0_CS_L1

AC30

MA1_CS_L0

AF32

MA1_CS_L1

AC32

MA_RAS_L

AF34

MA_CAS_L

AE33

MA_WE_L

J33

MA_RESET_L

AB33

MA_EVENT_L

V36

M_VREF

H11

MA_VREFDQ

U30

MA_ZVDDIO

M33

RSVD_3

AB34

RSVD_4

KAVERI-2M186092H4467_BGA854

MEMORY CHANNEL A

FP3 REV 0.52

MA_DATA0

MA_DATA1

MA_DATA2

MA_DATA3

MA_DATA4

MA_DATA5

MA_DATA6

MA_DATA7

MA_DATA8

MA_DATA9

MA_DATA10

MA_DATA11

MA_DATA12

MA_DATA13

MA_DATA14

MA_DATA15

MA_DATA16

MA_DATA17

MA_DATA18

MA_DATA19

MA_DATA20

MA_DATA21

MA_DATA22

MA_DATA23

MA_DATA24

MA_DATA25

MA_DATA26

MA_DATA27

MA_DATA28

MA_DATA29

MA_DATA30

MA_DATA31

MA_DATA32

MA_DATA33

MA_DATA34

MA_DATA35

MA_DATA36

MA_DATA37

MA_DATA38

MA_DATA39

MA_DATA40

MA_DATA41

MA_DATA42

MA_DATA43

MA_DATA44

MA_DATA45

MA_DATA46

MA_DATA47

MA_DATA48

MA_DATA49

MA_DATA50

MA_DATA51

MA_DATA52

MA_DATA53

MA_DATA54

MA_DATA55

MA_DATA56

MA_DATA57

MA_DATA58

MA_DATA59

MA_DATA60

MA_DATA61

MA_DATA62

MA_DATA63

MA_CHECK0

MA_CHECK1

MA_CHECK2

MA_CHECK3

MA_CHECK4

MA_CHECK5

MA_CHECK6

MA_CHECK7

RSVD_5

RSVD_6

RSVD_7

RSVD_8

H13
F13
H16
F16
G11
E11
E14
J14

J17
F17
H21
E21
E16
G17
F19
D20

D22
E22
D26
E25
G21
F22
G24
H24

E27
G27
E30
G30
F25
H25
D30
H28

AJ31
AK32
AK28
AF27
AJ33
AK33
AH28
AJ28

AF25
AH25
AG22
AJ22
AH27
AJ27
AE24
AF22

AH21
AJ21
AF17
AJ17
AK22
AF21
AJ19
AE17

AF16
AJ16
AF13
AE13
AH17
AE16
AJ13
AG13

E33
F33
H31
J31
D32
D34
H33
H34

E19
D28
AK24
AG16

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7

DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15

DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23

DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39

DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47

DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55

DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

DDRA_DQ[0..63] 10

+VREF_DQB

DDRB_MA[0..15]11

DDRB_BA0#11
DDRB_BA1#11
DDRB_BA2#11

DDRB_MB_DM[0..7]11

DDRB_DQS011
DDRB_DQS#011
DDRB_DQS111
DDRB_DQS#111
DDRB_DQS211
DDRB_DQS#211
DDRB_DQS311
DDRB_DQS#311
DDRB_DQS411
DDRB_DQS#411
DDRB_DQS511
DDRB_DQS#511
DDRB_DQS611
DDRB_DQS#611
DDRB_DQS711
DDRB_DQS#711

MB_CLK shift 0 to 1.from 1 to 2MB_CLK shift 0 to 1.from 1 to 2

DDRB_CLK011
DDRB_CLK0#11
DDRB_CLK111
DDRB_CLK1#11

DDRB_CKE011
DDRB_CKE111

DDRB_ODT011
DDRB_ODT111

DDRB_CS0#11
DDRB_CS1#11

DDRB_RAS#11
DDRB_CAS#11
DDRB_WE#11DDRA_WE#10

DDRB_RESET#11
DDRB_EVENT#11

@

1 2

RC22

RC3

0_0402_5%

1 2

39.2_0402_1%

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_MA14
DDRB_MA15

DDRB_BA0#
DDRB_BA1#
DDRB_BA2#

DDRB_MB_DM0
DDRB_MB_DM1
DDRB_MB_DM2
DDRB_MB_DM3
DDRB_MB_DM4
DDRB_MB_DM5
DDRB_MB_DM6
DDRB_MB_DM7

DDRB_DQS0
DDRB_DQS#0
DDRB_DQS1
DDRB_DQS#1
DDRB_DQS2
DDRB_DQS#2
DDRB_DQS3
DDRB_DQS#3
DDRB_DQS4
DDRB_DQS#4
DDRB_DQS5
DDRB_DQS#5
DDRB_DQS6
DDRB_DQS#6
DDRB_DQS7
DDRB_DQS#7

DDRB_CLK0

DDRB_CLK1
DDRB_CLK1#

DDRB_CKE0
DDRB_CKE1

DDRB_ODT0
DDRB_ODT1

DDRB_CS0#
DDRB_CS1#

DDRB_RAS#
DDRB_CAS#
DDRB_WE#

DDRB_RESET#
DDRB_EVENT#

MB_ZVDDIO

UC1C

AC36

MB_ADD0

U36

MB_ADD1

U37

MB_ADD2

T35

MB_ADD3

T37

MB_ADD4

T36

MB_ADD5

R36

MB_ADD6

P37

MB_ADD7

P36

MB_ADD8

N36

MB_ADD9

AD36

MB_ADD10

P35

MB_ADD11

N37

MB_ADD12

AH37

MB_ADD13

M36

MB_ADD14

L36

MB_ADD15

AD35

MB_BANK0

AD37

MB_BANK1

M37

MB_BANK2

A20

MB_DM0

C24

MB_DM1

A30

MB_DM2

B35

MB_DM3

AL35

MB_DM4

AN32

MB_DM5

AN26

MB_DM6

AN21

MB_DM7

E37

MB_DM8

C20

MB_DQS_H0

B20

MB_DQS_L0

B25

MB_DQS_H1

A25

MB_DQS_L1

C30

MB_DQS_H2

B30

MB_DQS_L2

B36

MB_DQS_H3

A36

MB_DQS_L3

AN36

MB_DQS_H4

AM36

MB_DQS_L4

AN31

MB_DQS_H5

AM31

MB_DQS_L5

AM25

MB_DQS_H6

AL26

MB_DQS_L6

AM20

MB_DQS_H7

AL20

MB_DQS_L7

F37

MB_DQS_H8

F36

MB_DQS_L8

MB_CLK_H0

AA37

MB_CLK_L0

AA36

MB_CLK_H1

Y37
Y36

MB_CLK_L1

Y34

MB_CLK_H2

Y35

MB_CLK_L2

V35

MB_CLK_H3

W36

MB_CLK_L3

K36

MB_CKE0

K37

MB_CKE1

K35

MB_CKE2

J37

MB_CKE3

AH36

MB0_ODT0

AJ37

MB0_ODT1

AF35

MB1_ODT0

AK35

MB1_ODT1

AF36

MB0_CS_L0

AJ36

MB0_CS_L1

AE36

MB1_CS_L0

AH35

MB1_CS_L1

AE37

MB_RAS_L

AG36

MB_CAS_L

AF37

MB_WE_L

MB_RESET_L

J36

AB36

MB_EVENT_L

MB_VREFDQ

B17
V37

MB_ZVDDIO

M35

RSVD_9

AB35

RSVD_10

KAVERI-2M186092H4467_BGA854

MEMORY CHANNEL B

FP3 REV 0.52

MB_DATA0

MB_DATA1

MB_DATA2

MB_DATA3

MB_DATA4

MB_DATA5

MB_DATA6

MB_DATA7

MB_DATA8

MB_DATA9

MB_DATA10

MB_DATA11

MB_DATA12

MB_DATA13

MB_DATA14

MB_DATA15

MB_DATA16

MB_DATA17

MB_DATA18

MB_DATA19

MB_DATA20

MB_DATA21

MB_DATA22

MB_DATA23

MB_DATA24

MB_DATA25

MB_DATA26

MB_DATA27

MB_DATA28

MB_DATA29

MB_DATA30

MB_DATA31

MB_DATA32

MB_DATA33

MB_DATA34

MB_DATA35

MB_DATA36

MB_DATA37

MB_DATA38

MB_DATA39

MB_DATA40

MB_DATA41

MB_DATA42

MB_DATA43

MB_DATA44

MB_DATA45

MB_DATA46

MB_DATA47

MB_DATA48

MB_DATA49

MB_DATA50

MB_DATA51

MB_DATA52

MB_DATA53

MB_DATA54

MB_DATA55

MB_DATA56

MB_DATA57

MB_DATA58

MB_DATA59

MB_DATA60

MB_DATA61

MB_DATA62

MB_DATA63

MB_CHECK0

MB_CHECK1

MB_CHECK2

MB_CHECK3

MB_CHECK4

MB_CHECK5

MB_CHECK6

MB_CHECK7

RSVD_11

RSVD_12

RSVD_13

RSVD_14

C18
B19
C22
A22
A18
B18
A21
B21

B24
A24
B27
A28
B22
B23
B26
C26

A29
B29
B32
C32
B28
C28
B31
A32

C34
A34
C36
C37
A33
B33
D35
B37

AL36
AM37
AN34
AM34
AK37
AK36
AN35
AL34

AL32
AM32
AN29
AL28
AM33
AN33
AM30
AM29

AM27
AM26
AN24
AM24
AN28
AM28
AN25
AL24

AN22
AL22
AK18
AL18
AM23
AM22
AN20
AM19

E36
F35
H36
H37
D36
D37
G36
H35

A26
B34
AL30
AM21

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7

DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15

DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23

DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31

DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39

DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47

DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55

DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

DDRB_DQ[0..63] 11

add cap on 20131002

D D

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

APU DDRA/B

APU DDRA/B

APU DDRA/B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

6 52

6 52

6 52

1.A

1.A

1.A

1

APU_EDP_TX0+27

EDP

OK

A A

FCH

OK

SPEC HDMI on Port 2

Follow Edge to delete RC7,RC8,RC9
and reserve resisotr on PWR page 52 on 20131009

OK

To Power schematics

B B

HDMI

OK

APU_EDP_TX0-27

APU_EDP_TX1+27
APU_EDP_TX1-27

APU_VGA_TXP013
APU_VGA_TXN013

APU_VGA_TXP113
APU_VGA_TXN113

APU_VGA_TXP213
APU_VGA_TXN213

APU_VGA_TXP313
APU_VGA_TXN313

APU_HDMI_TX2+28
APU_HDMI_TX2-28

APU_HDMI_TX1+28
APU_HDMI_TX1-28

APU_HDMI_TX0+28
APU_HDMI_TX0-28

APU_HDMI_CLK+28
APU_HDMI_CLK-28

EC_SMBLV_CK14
EC_SMBLV_DA14

Check connect t o FCH or EC

To Power schematics

Follow Edge to delete RC27,RC28,RC46
and reserve resisotr on PWR page 52 on 20131009

APU_EDP_TX0+
APU_EDP_TX0-

APU_EDP_TX1+
APU_EDP_TX1-

CC31 0.1U_0402_10V7-K
CC32 0.1U_0402_10V7-K

CC33 0.1U_0402_10V7-K
CC34 0.1U_0402_10V7-K

CC35 0.1U_0402_10V7-K
CC36 0.1U_0402_10V7-K

CC37 0.1U_0402_10V7-K
CC38 0.1U_0402_10V7-K

OK

OK

APU_SVC52
APU_SVD52
APU_SVT52

1 2

RC10 0_0402_5%@

1 2

RC11 0_0402_5%@

OK

VSS_SENSE52
VDD_SENSE52

VDDNB_SENSE52

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

APU_RESET#12

APU_PWROK12,52

APU_VGA_TXP0_C
APU_VGA_TXN0_C

APU_VGA_TXP1_C
APU_VGA_TXN1_C

APU_VGA_TXP2_C
APU_VGA_TXN2_C

APU_VGA_TXP3_C
APU_VGA_TXN3_C

APU_HDMI_TX2+
APU_HDMI_TX2-

APU_HDMI_TX1+
APU_HDMI_TX1-

APU_HDMI_TX0+
APU_HDMI_TX0-

APU_HDMI_CLK+
APU_HDMI_CLK-

APU_CLKP12
APU_CLKN12

DISP_CLKP12
DISP_CLKN12

APU_CLKP
APU_CLKN

DISP_CLKP
DISP_CLKN

APU_SVC
APU_SVD
APU_SVT

SIC
SID

APU_RESET#
APU_PWROK

APU_PROCHOT#
THERMTRIP#
ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

VSS_SENSE

VDD_SENSE

VDDNB_SENSE

+1.35V_APU_VDDIO

RC67 39.2_0402_1%@

C C

RC68 39.2_0402_1%@

VSS_SENSE

12

12

100_0402_5%

APU_TEST31

12

RC49

+VDD_CORE

RC47 100_0402_5%

+VDDNB_CORE

RC48 100_0402_5%

1 2

1 2

VDD_SENSE

HDT Debug conn

VDDNB_SENSE

+1.35V_APU_VDDIO_RUN

1 2

RC14 300_0402_5%

1 2

RC15 300_0402_5%

APU_RESET#
APU_PWROK

+1.35V_APU_VDDIO

1 2

RC17 1K_0402_1%

1 2

RC18 1K_0402_1%

1 2

RC19 1K_0402_1%

1 2

RC37 1K_0402_1%

D D

1 2

RC38 1K_0402_1%

1 2

RC39 1K_0402_1%

1 2

RC40 1K_0402_1%

1 2

RC41 1K_0402_1%

SIC
SID
ALERT#
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#

1

RC50

1 2

1 2

RC51 10K_0402_5%

1 2

RC52 10K_0402_5%

1 2

RC53 10K_0402_5%

0_0402_5%

2

UC1D

AL6

DP0_TXP0

AM5

DP0_TXN0

AN5

DP0_TXP1

AM4

DP0_TXN1

AN4

DP0_TXP2

AN3

DP0_TXN2

AM3

DP0_TXP3

AN2

DP0_TXN3

F2

DP1_TXP0

F1

DP1_TXN0

F3

DP1_TXP1

E2

DP1_TXN1

E1

DP1_TXP2

D1

DP1_TXN2

D2

DP1_TXP3

C1

DP1_TXN3

A2

DP2_TXP0

A3

DP2_TXN0

B4

DP2_TXP1

A4

DP2_TXN1

C4

DP2_TXP2

B5

DP2_TXN2

A5

DP2_TXP3

A6

DP2_TXN3

AM13

CLKIN_H

AN13

CLKIN_L

AM11

DISP_CLKIN_H

AN11

DISP_CLKIN_L

AJ10

RSVD_16

B16

SVC

C16

SVD

A16

SVT

AL14

SIC

AK14

SID

AM14

RESET_L

AL12

PWROK

AL10

PROCHOT_L

AK11

THERMTRIP_L

AN15

ALERT_L

A14

TDI

C14

TDO

B15

TCK

B14

TMS

D14

TRST_L

A13

DBRDY

B13

DBREQ_L

E10

VSS_SENSE_A

D9

VDD_SENSE

D10

VDDNB_SENSE

F10

VDDIO_SENSE

AE10

VDDP_SENSE

AF11

VDDR_SENSE

AF10

VSS_SENSE_B

KAVERI-2M186092H4467_BGA854

+1.35V_APU_VDDIO

HDT_TRST#APU_TRST#

2

ANALOG/DISPLAY/MISC

DISPLAY PORT 0

DISPLAY PORT

MISC.

DISPLAY PORT 1

DISPLAY PORT 2

TEST

SER. CLK

CTRL

JTAG

SENSE

FP3 REV 0.52

mount RC57 and RC58 if need JHDT1

JHDT1

1

1

3

3

5

5

7

7

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

SAMTE_ASP-136446-07-B

ME@

DP_STEREOSYNC

RSVD

AUDIO MISC

2

APU_TCK

2

4

APU_TMS

4

6

APU_TDI

6

8

APU_TDO

8

10

APU_PWROK

12

APU_RESET#

14

APU_DBRDY

16

HDT_DBREQ# APU_DBREQ#

18

APU_TEST19

20

APU_TEST18

DP0_AUXP

DP0_AUXN

DP1_AUXP

DP1_AUXN

DP2_AUXP

DP2_AUXN

DP3_AUXP

DP3_AUXN

DP4_AUXP

DP4_AUXN

DP5_AUXP

DP5_AUXN

DP0_HPD

DP1_HPD

DP2_HPD

DP3_HPD

DP4_HPD

DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST6

TEST9

TEST10

TEST14

TEST15

TEST16

TEST17

TEST18

TEST19

TEST20

TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

RSVD_15

DMAACTIVE_L

TEST4

TEST5

CORETYPE

RSVD_1

RSVD_2

RSVD_17

RSVD_18

RSVD_19

RSVD_20

RSVD_21

AG8
AG10

B2
B1

B6
B7

H7
G7

Y6
Y5

AD2
AC2

AH7
B3
D7
F8
AB6
AD1

D12
B11
C12

D3

DP_AUX_ZVSS

L27
P27
P28
C10
B9
A10
B10
A12
B12
C8
D8
AM12
AN12
A8
B8
AA27
AA28
V28
Y27
Y28

AK10
AM15

T27
T28

A9

D16

A17
K28

F7
E4
E5
E7
D5

1 2

RC56

0_0402_5%

APU_EDP_AUX
APU_EDP_AUX#

APU_VGA_AUX
APU_VGA_AUX#

APU_HDMI_CLK
APU_HDMI_DATA

APU_EDP_HPD
APU_VGA_HPD
APU_HDMI_HPD

APU_ENBKL_R
APU_ENVDD
APU_EDP_PWM_R

APU_TEST6
APU_TEST9
APU_TEST10
APU_TEST14
APU_TEST15
APU_TEST16
APU_TEST17
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST24
APU_TEST25_H
APU_TEST25_L
APU_TEST28_H
APU_TEST28_L
APU_TEST30_H
APU_TEST30_L
APU_TEST31
APU_TEST32_H
APU_TEST32_L

ALLOW_STOP

APU_TEST35

Test_Point

3

4

EC_SMB_3

APU_EDP_AUX 27
APU_EDP_AUX# 27

APU_VGA_AUX 13
APU_VGA_AUX# 13

APU_HDMI_CLK 28
APU_HDMI_DATA 28

APU_EDP_HPD 27

APU_VGA_HPD 13

APU_HDMI_HPD 28

APU_ENVDD 27

1 2

RC12 150_0402_1%

1 2

RC59 1K_0402_1%@

1 2

RC60 1K_0402_1%@

1 2

RC61 1K_0402_1%@

1 2

RC62 1K_0402_1%@

1 2

RC63 1K_0402_1%

1 2

RC64 1K_0402_1%

1 2

RC65 1K_0402_1%

1 2

RC66 1K_0402_1%

1 2

RC35 510_0402_5%

1 2

RC36 510_0402_5%

1 2

1 2

@

12

RC13 1K_0402_1%

RC42 300_0402_5%

RC20 300_0402_5%

EDP

FCH

HDMI

+0.95VS_VDDP

+1.35V_APU_VDDIO

ALLOW_STOP 12

+1.35V_APU_VDDIO

Please doucle confirm RC71 and RC72 value

EC_SMB_CK314,18,37,38

EC_SMB_DA314,18,37,38

EC_SMB_CK3

EC_SMB_DA3

APU_ENBKL_R

RC31
100K_0402_5%

RC44

APU_ENBKL_R

RC43
100K_0402_5%

1 2

1 2

2.2K_0402_5%

2

B

QC7

MMST3904-7-F_SOT323-3

E

APU_PROCHOT#

VSS_SENSE
VDD_SENSE
VDDNB_SENSE
APU_TEST6
APU_TEST10
APU_TEST15
APU_TEST28_H
APU_TEST28_L
APU_TEST30_H
APU_TEST30_L
APU_TEST32_H
APU_TEST32_L

1

TPC1 Test_Point_40MIL

1

TPC2 Test_Point_40MIL

1

TPC3 Test_Point_40MIL

1

TPC4 Test_Point_40MIL

1

TPC5 Test_Point_40MIL

1

TPC6 Test_Point_40MIL

1

TPC7 Test_Point_40MIL

1

TPC8 Test_Point_40MIL

1

TPC9 Test_Point_40MIL

1

TPC10 Test_Point_40MIL

1

TPC11 Test_Point_40MIL

1

TPC12 Test_Point_40MIL

+1.35V_APU_VDDIO

H_PROCHOT#38

+1.35V_APU_VDDIO_RUN

+3VALW

RPC1

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

THERMTRIP#

H_THERMTRIP#14,18

To EDP_PWM Conn

OK

RC33
47K_0402_5%

RC32

APU_EDP_PWM_R

RC74

4.7K_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

1 2

1 2

Deciphered Date

Deciphered Date

Deciphered Date

4

2.2K_0402_5%

MMST3904-7-F_SOT323-3

QC5

2014/07/01

2014/07/01

2014/07/01

+3VS

RC71

1 2

G

2

1 3

D

33K_0402_5%

1 3

S

QC12

BSS138_SOT23-3

12

RC72
30K_0402_1%

G

2

D

S

QC3

BSS138_SOT23-3

SIC

SID

+3VS

RC30

2.2K_0402_5%

1 2

RC29 0_0402_5%

1 2

1 2

13

D

2

QC4
2N7002KW_SOT323-3

G

SB00000YY00

S

C

APU_ENBKL

APU_BKOFF#

3 1

+1.35V_APU_VDDIO

12

RC23

B

2

E

3 1

QC1
MMST3904-7-F_SOT323-3

1K_0402_1%

C

RC45

APU_PROCHOT#

1 2

0_0402_5%

H_PROCHOT# pull up +3VS on VR_HOT# on PWR page 52

+1.35V_APU_VDDIO

12

RC26

APU Msic

APU Msic

APU Msic

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

1K_0402_1%

THERMTRIP#

APU_EDP_PWM 27

2

B

E

31

C

QC2

MMST3904-7-F_SOT323-3

+3VS

RC34

4.7K_0402_5%

1 2

1 2

C

2

B

E

3 1

APU_EDP_PWM

13

D

2

QC9

G

2N7002KW_SOT323-3

SB00000YY00

S

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

5

EC_SMB_CK3

@

EC_SMB_DA3

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

1

CH87
22P_0402_50V8-J

2

1

CH88
22P_0402_50V8-J

@

2

APU_ENBKL 38

APU_BKOFF# 27

FCH_PROCHOT# 12

7 52

7 52

7 52

1.A

1.A

1.A

1

2

3

4

5

+VDD_CORE

CC48

CC44

A A

CC45

.01U_0402_16V7-K

.01U_0402_16V7-K

1

+VDDNB_CORE

+0.95VS_VDDR

2

CC66

CC65

180P_0402_50V7-K

180P_0402_50V7-K

1

2

CC82

CC81

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

2

CC86

CC85

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

2

CC95

CC94

0.22U_0402_10V6-K

0.22U_0402_10V6-K

2

1

+VDD_CORE +VDDNB_CORE

B B

C C

UC1E

T11

VDD_1

T14

VDD_2

T17

VDD_3

T21

VDD_4

T24

VDD_5

V10

VDD_6

V13

VDD_7

V16

VDD_8

V19

VDD_9

V22

VDD_10

V24

VDD_11

Y7

VDD_12

Y10

VDD_13

Y13

VDD_14

Y16

VDD_15

Y19

VDD_16

Y22

VDD_17

Y25

VDD_18

AA4

VDD_19

AA11

VDD_20

AA14

VDD_21

AA17

VDD_22

AA21

VDD_23

AA24

VDD_24

AB7

VDD_25

AC4

VDD_26

AC10

VDD_27

AC13

VDD_28

AC16

VDD_29

AC19

VDD_30

AC22

VDD_31

AC25

VDD_32

AD4

VDD_33

AD11

VDD_34

AD14

VDD_35

AD17

VDD_36

AD21

VDD_37

AD24

VDD_38

AE6

VDD_39

AE22

VDD_40

AE25

VDD_41

AF5

VDD_42

AF8

VDD_43

AG11

VDD_44

AH5

VDD_45

AH8

VDD_46

AH10

VDD_47

AK8

VDD_48

FP3 REV 0.52

KAVERI-2M186092H4467_BGA854

POWER

VDDNB_1

VDDNB_2

VDDNB_3

VDDNB_4

VDDNB_5

VDDNB_6

VDDNB_7

VDDNB_8

VDDNB_9

VDDNB_10

VDDNB_11

VDDNB_12

VDDNB_13

VDDNB_14

VDDNB_15

VDDNB_16

VDDNB_17

VDDNB_18

VDDNB_19

VDDNB_20

VDDNB_21

VDDNB_22

VDDNB_23

VDDNB_24

VDDNB_25

VDDNB_26

VDDNB_27

VDDNB_28

VDDNB_29

VDDNB_30

VDDNB_31

VDDNB_32

VDDNB_33

VDDNB_34

VDDNB_35

VDDNB_36

VDDNB_37

VDDNB_38

VDDNB_39

VDDNB_40

VDDNB_41

VDDNB_42

E8
F4
F5
G4
G8
G10
H3
H6
H10
J10
J13
J22
J25
K11
K14
K17
K21
K24
L4
L7
L10
L13
L16
L19
L22
L25
M3
N11
N14
N17
N21
N24
P10
P13
P16
P19
P22
P25
R4
R6
R9
T3

CC79

22U_0603_6.3V6-M

1

2

+1.35V_APU_VDDIO

+0.95VS_VDDP

CC80

1

@

2

UC1F

L29

VDDIO_1

L31

VDDIO_2

L34

VDDIO_3

L37

VDDIO_4

M29

VDDIO_5

M32

VDDIO_6

N27

VDDIO_7

N34

VDDIO_8

P29

VDDIO_9

P31

VDDIO_10

R29

VDDIO_11

R32

VDDIO_12

R34

VDDIO_13

R37

VDDIO_14

U29

VDDIO_15

U31

VDDIO_16

U34

VDDIO_17

V27

VDDIO_18

V34

VDDIO_19

W29

VDDIO_20

W32

VDDIO_21

W37

VDDIO_22

Y31

VDDIO_23

AA34

VDDIO_24

AB29

VDDIO_25

AB32

VDDIO_26

AB37

VDDIO_27

AC29

VDDIO_28

AC31

VDDIO_29

AC34

VDDIO_30

AC37

VDDIO_31

AE32

VDDIO_32

AE34

VDDIO_33

AF30

VDDIO_34

AF31

VDDIO_35

AG34

VDDIO_36

AG37

VDDIO_37

AK16

VDDP_1

AL16

VDDP_2

AM16

VDDP_3

AN16

VDDP_4

AC11

VDDP_CAP

22U_0603_6.3V6-M

KAVERI-2M186092H4467_BGA854

POWER

FP3 REV 0.52

VDDR_1

VDDR_2

VDDR_3

VDDR_CAP

VDDA_1

VDDA_2

RSVD_22

AK17
AM17
AN17

AC27

AH11
AJ11

D6

+0.95VS_VDDR

+VDDR_CAP

+1.35V_APU_VDDIO

+1.35V_APU_VDDIO

+1.8VS_VDDA

CC47

CC46

.01U_0402_16V7-K

180P_0402_50V7-K

1

1

2

2

CC67

CC68

180P_0402_50V7-K

1

2

1

2

1

2

2

1

180P_0402_50V7-K

1

2

CC84

CC83

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

2

CC88

CC87

4.7U_0603_6.3V6-K

22U_0603_6.3V6-M

1

2

CC97

CC96

0.22U_0402_10V6-K

0.22U_0402_10V6-K

2

1

+0.95VS_VDDP

CC69

22U_0603_6.3V6-M

1

2

CC71

CC70

22U_0603_6.3V6-M

1

2

CC72

22U_0603_6.3V6-M

0.22U_0402_10V6-K

1

2

CC49

CC42

CC43

0.22U_0402_10V6-K

180P_0402_50V7-K

180P_0402_50V7-K

1

1

2

1

2

1

2

1

2

2

1

2

1

1

2

2

CC63

CC62

0.22U_0402_10V6-K

0.22U_0402_10V6-K

2

2

1

1

CC23

CC24

0.22U_0402_10V6-K

0.22U_0402_10V6-K

2

2

1

1

CC90

CC89

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

1

1

2

2

CC99

CC98

0.22U_0402_10V6-K

0.22U_0402_10V6-K

2

2

1

1

CC74

CC73

0.22U_0402_10V6-K

1

2

2

1

180P_0402_50V7-K

0.22U_0402_10V6-K

2

2

1

1

CC64

0.22U_0402_10V6-K

2

1

22u 6.3V *11 @*2 Design Guide

0.22u 10V *2

0.01u 10V *3

CC26

CC25

180P_0402_50V7-K

180P_0402_50V7-K

1

1

2

2

4.7U_0603_6.3V6-K

0.22U_0402_10V6-K

CC92

CC101

CC93

4.7U_0603_6.3V6-K

1

1

2

2

CC102

0.22U_0402_10V6-K

2

2

1

1

4.7U_0603_6.3V6-K

0.22U_0402_10V6-K

CC91

1

2

CC100

2

1

+1.8VS_VDDA

CC75

1

2

CC76

4.7U_0603_6.3V6-K

1

2

180p *3

22u 6.3V *10 @*2 Design Guide

0.22u 10V *3
180p 10V *4

22u 6.3V *3

0.22u 10V *2
180p 10V *2

22u 6.3V *4

0.22u 10V *2
180p 10V *2

4.7u 6.3V *1

0.22u 10V *1

3.3n 10V *1

CC105

CC104

CC103

180P_0402_50V7-K

0.22U_0402_10V6-K

2

1

CC77

0.22U_0402_10V6-K

2

1

180P_0402_50V7-K

1

1

2

2

+VDDR_CAP

CC78

CC27

CC28

3.3n_0402_50V6-K

2

1

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

1

2

2

180P_0402_50V7-K

3.3n need apply PN

D D

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

APU Power

APU Power

APU Power

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

8 52

8 52

8 52

1.A

1.A

1.A

1

2

3

4

5

A A

B B

UC1G

VSS

A1

VSS_1

A7

VSS_2

A11

VSS_3

A15

VSS_4

A19

VSS_5

A23

VSS_6

A27

VSS_7

A31

VSS_8

A35

VSS_9

A37

VSS_10

C2

VSS_11

C3

VSS_12

C6

VSS_13

C35

VSS_14

D4

VSS_15

D11

VSS_16

D13

VSS_17

D15

VSS_18

D17

VSS_19

D19

VSS_20

D21

VSS_21

D23

VSS_22

D25

VSS_23

D27

VSS_24

D29

VSS_25

D31

VSS_26

D33

VSS_27

E17

VSS_28

E31

VSS_29

E34

VSS_30

F11

VSS_31

F21

VSS_32

F24

VSS_33

F27

VSS_34

F30

VSS_35

G1

VSS_36

G13

VSS_37

G16

VSS_38

G19

VSS_39

G22

VSS_40

G25

VSS_41

G28

VSS_42

G34

VSS_43

G37

VSS_44

H8

VSS_45

H14

VSS_46

H17

VSS_47

H30

VSS_48

H32

VSS_49

J4

VSS_50

J6

VSS_51

J11

VSS_52

J16

VSS_53

J21

VSS_54

J24

VSS_55

J27

VSS_56

J28

VSS_57

J32

VSS_58

J34

VSS_59

K10

VSS_60

FP3 REV 0.52

VSS_61

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_74

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

K13
K16
K19
K22
K25
L1
L11
L14
L17
L21
L24
L28
M6
M9
N4
N10
N13
N16
N19
N22
N25
N28
P6
P9
P11
P14
P17
P21
P24
R1
T10
T13
T16
T19
T22
T25
U4
U6
U9
V11
V14
V17
V21
V25
W1
W4
W6
W9
Y3
Y11
Y14
Y17
Y21
Y24
AA10
AA13
AA16
AA19
AA22
AA25

KAVERI-2M186092H4467_BGA854

UC1H

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS_180

VSS

FP3 REV 0.52

AC14
AC17
AC21
AC24
AC28

AD10
AD13
AD16
AD19
AD22
AD25
AD28

AE14
AE19
AE21
AE27
AE28

AF24
AF28

AG14
AG17
AG21
AG25
AG27
AG28
AH13
AH16
AH19
AH22
AH30
AH31

AJ24
AJ25

AK12
AK13
AK15
AK19
AK21
AK23
AK25
AK27
AK29
AK31
AK34

AL37

AM35

AC1
AC7

AD3

AE1
AE4

AF7

AG1
AG4

AJ4

AK9

AL3
AL8

AN1
AN7

KAVERI-2M186092H4467_BGA854

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185

VSS_186

VSS_187

VSS_188

VSS_189

VSS_190

AN10
AN14
AN19
AN23
AN27
AN30
AN37
AD27
K27
AE11

C C

D D

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

APU GND

APU GND

APU GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

9 52

9 52

9 52

1.A

1.A

1.A

5

4

3

2

1

DDR3 SO-DIMM A

VSS_2

VSS_4
DQS0#

DQS0

VSS_6

VSS_8

DQ12
DQ13

VSS_10

RESET#
VSS_12

DQ14
DQ15

VSS_14

DQ20
DQ21

VSS_16

VSS_18

DQ22
DQ23

VSS_20

DQ28
DQ29

VSS_22

DQS3#

DQS3

VSS_24

DQ30
DQ31

VSS_26

CKE1

VDD_2

VDD_4

VDD_6

VDD_8

VDD_10

CK1#

VDD_12

RAS#

VDD_14

ODT0

VDD_16

ODT1

NC_2

VDD_18

VREF_CA

VSS_28

DQ36
DQ37

VSS_30

VSS_32

DQ38
DQ39

VSS_34

DQ44
DQ45

VSS_35

DQS5#

DQS5

VSS_38

DQ46
DQ47

VSS_40

DQ52
DQ53

VSS_42

VSS_44

DQ54
DQ55

VSS_46

DQ60
DQ61

VSS_48

DQS7#

DQS7

VSS_50

DQ62

DQ63
VSS_52
EVENT#

VTT_2

GND2

BOSS2

+1.35V_DDR_VDDIOSUS+1.35V_DDR_VDDIOSUS

2
4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

DM4

DM6

SDA

SCL

DDRA_DQ4

6

DDRA_DQ5

8
10

DDRA_DQS#0

12

DDRA_DQS0

14
16

DDRA_DQ6

18

DDRA_DQ7

20
22

DDRA_DQ12

24

DDRA_DQ13

26
28

DDRA_MA_DM1

30

DDRA_RESET#

32
34

DDRA_DQ14

36

DDRA_DQ15

38
40

DDRA_DQ20

42

DDRA_DQ21

44
46

DDRA_MA_DM2

48
50

DDRA_DQ22

52

DDRA_DQ23DDRA_DQ18

54
56

DDRA_DQ28

58

DDRA_DQ29

60
62

DDRA_DQS#3

64

DDRA_DQS3

66
68

DDRA_DQ30

70

DDRA_DQ31

72

74

DDRA_CKE1

76
78

DDRA_MA15

80

DDRA_MA14

82
84

DDRA_MA11

86

DDRA_MA7

88
90

DDRA_MA6

92

DDRA_MA4

94
96

DDRA_MA2

98

DDRA_MA0

100
102

DDRA_CLK1

104

DDRA_CLK1#

106
108

DDRA_BA1#

110

DDRA_RAS#

112
114

DDRA_CS0#

116

DDRA_ODT0

118
120

DDRA_ODT1

122
124
126
128
130

DDRA_DQ36

132

DDRA_DQ37

134
136

DDRA_MA_DM4

138
140

DDRA_DQ38

142

DDRA_DQ39

144
146

DDRA_DQ44

148

DDRA_DQ45

150
152

DDRA_DQS#5

154

DDRA_DQS5

156
158

DDRA_DQ46

160

DDRA_DQ47

162
164

DDRA_DQ52

166

DDRA_DQ53

168
170

DDRA_MA_DM6

172
174

DDRA_DQ54

176

DDRA_DQ55

178
180

DDRA_DQ60

182

DDRA_DQ61

184
186

DDRA_DQS#7

188

DDRA_DQS7

190
192

DDRA_DQ62

194

DDRA_DQ63

196
198

DDRA_EVENT#

200

SMB0_DATA

202

SMB0_CLK

204

206
208

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDRA_MA_DM1 6

DDRA_RESET# 6

DDRA_MA_DM2 6

DDRA_CKE1 6

DDRA_CLK1 6
DDRA_CLK1# 6

DDRA_BA1# 6
DDRA_RAS# 6

DDRA_CS0# 6
DDRA_ODT0 6

DDRA_ODT1 6

DDRA_MA_DM4 6

DDRA_MA_DM6 6

DDRA_EVENT# 6
SMB0_DATA 11,14,33
SMB0_CLK 11,14,33

+0.675VS

+VREF_DQA_D

RD17

@

0_0402_5%

1 2
1 2

1 2

0_0402_5%

CD1

@

Close to JDDR3H.1

DDRA_SA0
DDRA_SA1

1

CD2

2

0.1U_0402_10V7-K

2.2U_0603_6.3V6-K

DDRA_MA_DM06

1

2

1000P_0402_50V7-K

DDRA_MA_DM36

DDRA_CKE06

DDRA_BA2#6

DDRA_CLK06
DDRA_CLK0#6

DDRA_BA0#6

DDRA_WE#6
DDRA_CAS#6

DDRA_CS1#6

DDRA_MA_DM56

SPD setting (SA0, SA1)
PU/PD by Channel A/B

->Channel A 00

->Channel B 01

DDRA_MA_DM76

+3VS

CD3

1

2

1

CD4

0.1U_0402_10V6-K

2

DDRA_DQ0
DDRA_DQ1

DDRA_MA_DM0

DDRA_DQ2
DDRA_DQ3

DDRA_DQ8
DDRA_DQ9

DDRA_DQS#1
DDRA_DQS1

DDRA_DQ10
DDRA_DQ11

DDRA_DQ16
DDRA_DQ17

DDRA_DQS#2
DDRA_DQS2

DDRA_DQ19

DDRA_DQ24
DDRA_DQ25

DDRA_MA_DM3

DDRA_DQ26
DDRA_DQ27

DDRA_CKE0

DDRA_BA2#

DDRA_MA12
DDRA_MA9

DDRA_MA8
DDRA_MA5

DDRA_MA3
DDRA_MA1

DDRA_CLK0
DDRA_CLK0#

DDRA_MA10
DDRA_BA0#

DDRA_WE#
DDRA_CAS#

DDRA_MA13
DDRA_CS1#

DDRA_DQ32
DDRA_DQ33

DDRA_DQS#4
DDRA_DQS4

DDRA_DQ34
DDRA_DQ35

DDRA_DQ40
DDRA_DQ41

DDRA_MA_DM5

DDRA_DQ42
DDRA_DQ43

DDRA_DQ48
DDRA_DQ49

DDRA_DQS#6
DDRA_DQS6

DDRA_DQ50
DDRA_DQ51

DDRA_DQ56
DDRA_DQ57

DDRA_MA_DM7

DDRA_DQ58
DDRA_DQ59

DDRA_SA0

DDRA_SA1

D D

C C

B B

A A

+VREF_DQA

RD167
RD168 0_0402_5%

3A@1.5V

JDDR1

1

VREF_DQ

3

VSS_1

5

DQ0

7

DQ1

9

VSS_3

11

DM0

13

VSS_5

15

DQ2

17

DQ3

19

VSS_7

21

DQ8

23

DQ9

25

VSS_9

27

DQS1#

29

DQS1

31

VSS_11

33

DQ10

35

DQ11

37

VSS_13

39

DQ16

41

DQ17

43

VSS_15

45

DQS2#

47

DQS2

49

VSS_17

51

DQ18

53

DQ19

55

VSS_19

57

DQ24

59

DQ25

61

VSS_21

63

DM3

65

VSS_23

67

DQ26

69

DQ27

71

VSS_25

73

CKE0

75

VDD_1

77

NC_1

79

BA2

81

VDD_3

83

A12/BC#

85

A9

87

VDD_5

89

A8

91

A5

93

VDD_7

95

A3

97

A1

99

VDD_9

101

CK0

103

CK0#

105

VDD_11

107

A10/AP

109

BA0

111

VDD_13

113

WE#

115

CAS#

117

VDD_15

119

A13

121

S1#

123

VDD_17

125

TEST

127

VSS_27

129

DQ32

131

DQ33

133

VSS_29

135

DQS4#

137

DQS4

139

VSS_31

141

DQ34

143

DQ35

145

VSS_33

147

DQ40

149

DQ41

151

VSS_36

153

DM5

155

VSS_37

157

DQ42

159

DQ43

161

VSS_39

163

DQ48

165

DQ49

167

VSS_41

169

DQS6#

171

DQS6

173

VSS_43

175

DQ50

177

DQ51

179

VSS_45

181

DQ56

183

DQ57

185

VSS_47

187

DM7

189

VSS_49

191

DQ58

193

DQ59

195

VSS_51

197

SA0

199

VDDSPD

201

SA1

203

VTT_1

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

DDRA_DQ[0..63] 6

DDRA_DQS[0..7] 6

DDRA_DQS#[0..7] 6

DDRA_MA[0..15] 6

All VREF traces should have 20 mil trace width

1

1

CD5

CD6

2

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

close to JDDR3L.126

+V_SM_VREF_CNT

DDR Decoupling

+1.35V_DDR_VDDIOSUS

CD59

+0.675VS

1

@

2

CD7

1

2

0.1U_0402_10V7-K

CD11

@

0.1U_0402_10V7-K

1

2

CD49

1

2

0.1U_0402_10V7-K

CD20

4.7U_0603_6.3V6K
1U_0402_6.3V6-K

1

2

10U_0603_6.3V6-M

CD21

CD8

0.1U_0402_10V7-K

CD12

@

CD50

0.1U_0402_10V7-K

1

2

CD9

CD10

1

1

2

2

0.1U_0402_10V7-K

@

CD47

CD13

@

10U_0603_6.3V6-M

0.1U_0402_10V7-K

1

1

1

2

2

2

CD51

1

1

2

2

0.1U_0402_10V7-K

CD22

1U_0402_6.3V6-K

1U_0402_6.3V6-K

1

2

Layout Note :

1

1. Placed near JDDR3L

2. Place these 4 Caps near Command

2

and Control signals of DIMMA

0.1U_0402_10V7-K

@

CD15

CD14

10U_0603_6.3V6-M

1

1

2

2

0.1U_0402_10V7-K

CD52

1

2

0.1U_0402_10V7-K

CD23

Layout Note : Placed near
JDDR3L1.Pin203, 204

1

2

0.1U_0402_10V7-K

+1.35V_DDR_VDDIOSUS

1uF *4, 10uF *7, 330uF *1

CD16

CD17

1

1

2

2

0.1U_0402_10V7-K

0.1U_0402_10V7-K

+VREF_DQA_D

12

RD11
1K_0402_1%

12

RD12
1K_0402_1%

CD18

10U_0603_6.3V6-M

1

2

0.1U_0402_10V7-K

DDRA_EVENT#

CD42

CD19

330U_D2_2VM_R9M

1

1

+

@

2

2

+1.35V_DDR_VDDIOSUS

12

RD6
1K_0402_1%

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

2012/12/05

2012/12/05

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/12/05

2014/12/05

2014/12/05

Title

DDR3 SO-DIMMA/1

DDR3 SO-DIMMA/1

DDR3 SO-DIMMA/1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

1

of

10 52

10 52

10 52

0.4

0.4

0.4

5

4

3

2

1

DDR3 SO-DIMM B

+VREF_DQB_D

RD18

@

1 2

+VREF_DQB

D D

0_0402_5%

CD24

DDRB_MB_DM06

1

1

CD25

@

2

2

0.1U_0402_10V7-K
1000P_0402_50V7-K

Close to JDDR3L.1

DDRB_MB_DM36

C C

B B

SPD setting (SA0, SA1)
PU/PD by Channel A/B

->Channel A 00

->Channel B 01

+3VS

2.2U_0603_6.3V6-K

A A

CD26

1

2

+3VS

1

CD27

0.1U_0402_10V6-K

2

DDRB_CKE06

DDRB_BA2#6

DDRB_CLK06
DDRB_CLK0#6

DDRB_BA0#6

DDRB_WE#6
DDRB_CAS#6

DDRB_CS1#6

DDRB_MB_DM56

DDRB_MB_DM76

1 2

R167 10K_0402_5%

RD170

DDRB_DQ0
DDRB_DQ1

DDRB_MB_DM0

DDRB_DQ2
DDRB_DQ3

DDRB_DQ8
DDRB_DQ9

DDRB_DQS#1
DDRB_DQS1

DDRB_DQ10
DDRB_DQ11

DDRB_DQ16
DDRB_DQ17

DDRB_DQS#2
DDRB_DQS2

DDRB_DQ18
DDRB_DQ19

DDRB_DQ24
DDRB_DQ25

DDRB_MB_DM3

DDRB_DQ26
DDRB_DQ27

DDRB_CKE0

DDRB_BA2#

DDRB_MA12
DDRB_MA9

DDRB_MA8
DDRB_MA5

DDRB_MA3
DDRB_MA1

DDRB_CLK0
DDRB_CLK0#

DDRB_MA10
DDRB_BA0#

DDRB_WE#
DDRB_CAS#

DDRB_MA13
DDRB_CS1#

DDRB_DQ32
DDRB_DQ33

DDRB_DQS#4
DDRB_DQS4

DDRB_DQ34
DDRB_DQ35

DDRB_DQ40
DDRB_DQ41

DDRB_MB_DM5

DDRB_DQ42
DDRB_DQ43

DDRB_DQ48
DDRB_DQ49

DDRB_DQS#6
DDRB_DQS6

DDRB_DQ50
DDRB_DQ51

DDRB_DQ56
DDRB_DQ57

DDRB_MB_DM7

DDRB_DQ58
DDRB_DQ59

1 2

0_0402_5%

+1.35V_DDR_VDDIOSUS

DDRB_SA0

DDRB_SA1

3A@1.5V

JDDR2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

+1.35V_DDR_VDDIOSUS

DQ4
DQ5

VSS3

DQS#0

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

A15
A14

VDD4

A11

A7

VDD6

A6
A4

VDD8

A2
A0

CK1
CK1#

VDD12

BA1
RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL
VTT2

G2

2
4

DDRB_DQ4

6

DDRB_DQ5

8
10

DDRB_DQS#0

12

DDRB_DQS0

14
16

DDRB_DQ6

18

DDRB_DQ7

20
22

DDRB_DQ12

24

DDRB_DQ13

26
28

DDRB_MB_DM1

30

DDRB_RESET#

32
34

DDRB_DQ14

36

DDRB_DQ15

38
40

DDRB_DQ20

42

DDRB_DQ21

44
46

DDRB_MB_DM2

48
50

DDRB_DQ22

52

DDRB_DQ23

54
56

DDRB_DQ28

58

DDRB_DQ29

60
62

DDRB_DQS#3

64

DDRB_DQS3

66
68

DDRB_DQ30

70

DDRB_DQ31

72

74

DDRB_CKE1

76
78

DDRB_MA15

80

DDRB_MA14

82
84

DDRB_MA11

86

DDRB_MA7

88
90

DDRB_MA6

92

DDRB_MA4

94
96

DDRB_MA2

98

DDRB_MA0

100
102

DDRB_CLK1

104

DDRB_CLK1#

106
108

DDRB_BA1#

110

DDRB_RAS#

112
114

DDRB_CS0#

116

DDRB_ODT0

118
120

DDRB_ODT1

122
124
126
128
130

DDRB_DQ36

132

DDRB_DQ37

134
136

DDRB_MB_DM4

138
140

DDRB_DQ38

142

DDRB_DQ39

144
146

DDRB_DQ44

148

DDRB_DQ45

150
152

DDRB_DQS#5

154

DDRB_DQS5

156
158

DDRB_DQ46

160

DDRB_DQ47

162
164

DDRB_DQ52

166

DDRB_DQ53

168
170

DDRB_MB_DM6

172
174

DDRB_DQ54

176

DDRB_DQ55

178
180

DDRB_DQ60

182

DDRB_DQ61

184
186

DDRB_DQS#7

188

DDRB_DQS7

190
192

DDRB_DQ62

194

DDRB_DQ63

196
198

DDRB_EVENT#

200

SMB0_DATA

202

SMB0_CLK

204

206

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDRB_MB_DM1 6

DDRB_RESET# 6

DDRB_MB_DM2 6

DDRB_CKE1 6

DDRB_CLK1 6
DDRB_CLK1# 6

DDRB_BA1# 6
DDRB_RAS# 6

DDRB_CS0# 6
DDRB_ODT0 6

DDRB_ODT1 6

DDRB_MB_DM4 6

DDRB_MB_DM6 6

DDRB_EVENT# 6

SMB0_DATA 10,14,33
SMB0_CLK 10,14,33

+0.675VS

DDRB_DQ[0..63] 6

DDRB_DQS[0..7] 6

DDRB_DQS#[0..7] 6

DDRB_MA[0..15] 6

1

CD28

1

CD29

2

2

0.1U_0402_10V7-K
1000P_0402_50V7-K

Close to JDDR3H.126

+V_SM_VREF_CNT

DDR Decoupling

+1.35V_DDR_VDDIOSUS

0.1U_0402_10V7-K

+0.675VS

4.7U_0603_6.3V6K

1

CD58

@

2

DDRB_EVENT#

CD31

CD30

1

2

0.1U_0402_10V7-K

CD35

CD34

@

10U_0603_6.3V6-M

1

2

CD61

CD62

1

2

0.1U_0402_10V7-K

0.1U_0402_10V7-K

CD43

CD44

1U_0402_6.3V6-K

1

1

2

2

+1.35V_DDR_VDDIOSUS

12

1

2

10U_0603_6.3V6-M

1

2

1

2

CD45

1U_0402_6.3V6-K

1

2

RD8
1K_0402_1%

CD32

0.1U_0402_10V7-K

CD36

CD64

0.1U_0402_10V7-K

1U_0402_6.3V6-K

1

2

CD54

@

10U_0603_6.3V6-M

1

2

1

2

CD33

Layout Note :

1

1. Placed near JDDR3H

2. Place these 4 Caps near Command

2

and Control signals of DIMMA

0.1U_0402_10V7-K

@

CD55

CD37

@

@

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

2

CD63

1

2

0.1U_0402_10V7-K

CD46

1

2

+1.35V_DDR_VDDIOSUS

1

1

2

2

Layout Note : Placed near

1U_0402_6.3V6-K

JDDR3H.Pin203, 204

12

RD5
1K_0402_1%

12

RD7
1K_0402_1%

1uF *4, 10uF *7, 330uF *1

CD39

CD38

10U_0603_6.3V6-M

0.1U_0402_10V7-K

+V_SM_VREF_CNT

1

2

1

2

0.1U_0402_10V7-K

+1.35V_DDR_VDDIOSUS

0.1U_0402_10V7-K

CD40

1

2

12

RD9
1K_0402_1%

12

RD10
1K_0402_1%

CD41

1

2

0.1U_0402_10V7-K

+VREF_DQB_D

CRB: DDRB_SA1 pull low / DDRB_SA0 pull high
Edge: DDRB_SA1 pull high / DDRB_SA0 pull low

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

2012/12/05

2012/12/05

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/12/05

2014/12/05

2014/12/05

Title

DDR3 SO-DIMMB/2

DDR3 SO-DIMMB/2

DDR3 SO-DIMMB/2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

1

of

11 52

11 52

11 52

0.4

0.4

0.4

1

2

3

4

5

CH82

1 2

150P_0402_50V8-J

CH15

@

1 2

A A

UMI_CRX_FTX_P05
UMI_CRX_FTX_N05
UMI_CRX_FTX_P15
UMI_CRX_FTX_N15
UMI_CRX_FTX_P25
UMI_CRX_FTX_N25
UMI_CRX_FTX_P35
UMI_CRX_FTX_N35

B B

OK

APU

OK

APU

GPU

LAN

C C

WLAN

PLT_RST#17,33,35
EC_A_RST#38

+VDDAN_11_PCIE

+VDDAN_11_CLK

DISP_CLKP7
DISP_CLKN7

APU_CLKP7
APU_CLKN7

GFX_CLKP17
GFX_CLKN17

PCIE_LAN_CLK_P035
PCIE_LAN_CLK_N035

PCIE_WLAN_CLK_P233
PCIE_WLAN_CLK_N233

150P_0402_50V8-J

EC_A_RST#

UMI_CRX_FTX_P0
UMI_CRX_FTX_N0
UMI_CRX_FTX_P1
UMI_CRX_FTX_N1
UMI_CRX_FTX_P2
UMI_CRX_FTX_N2
UMI_CRX_FTX_P3
UMI_CRX_FTX_N3

UMI_CTX_FRX_P0_C5
UMI_CTX_FRX_N0_C5
UMI_CTX_FRX_P1_C5
UMI_CTX_FRX_N1_C5
UMI_CTX_FRX_P2_C5
UMI_CTX_FRX_N2_C5
UMI_CTX_FRX_P3_C5
UMI_CTX_FRX_N3_C5

CH1 0.1U_0402_10V7-K
CH2 0.1U_0402_10V7-K
CH3 0.1U_0402_10V7-K
CH4 0.1U_0402_10V7-K
CH5 0.1U_0402_10V7-K
CH6 0.1U_0402_10V7-K
CH7 0.1U_0402_10V7-K
CH8 0.1U_0402_10V7-K

RH4 590_0402_1%
RH3 2K_0402_1%

RH5 2K_0402_1%

RH6 0_0402_5%
RH7 0_0402_5%

RH8 0_0402_5%
RH9 0_0402_5%

RH10 0_0402_5%
RH11 0_0402_5%

RH12 0_0402_5%
RH13 0_0402_5%

RH16 0_0402_5%
RH17 0_0402_5%

RH1

1 2

RH2

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

@

33_0402_5%
33_0402_5%

PCIE_CALRP
PCIE_CALRN

DISP_CLKP_R
DISP_CLKN_R

APU_CLKP_R
APU_CLKN_R

GFX_CLKP_R
GFX_CLKN_R

PCIE_LAN_CLK_P0_R
PCIE_LAN_CLK_N0_R

PCIE_WLAN_CLK_P2_R
PCIE_WLAN_CLK_N2_R

PCH Crystal

FCH_XTAL25_IN

FCH_XTAL25_OUT

10P_0402_50V8J

1

CH16

2

1 2

RH18 1M_0402_5%

YH1

1

OSC1

GND12OSC2

GND2

4

3

25MHZ_10PF_7V25000014

1

CH17
10P_0402_50V8J

2

Change to 7V25000014 (TXC),. Cap 10pF*2 on 2013/12/5

D D

1 2

RH91

PLT_RST_R#PLT_RST#
A_RST#

UMI_CRX_FTX_P0_C
UMI_CRX_FTX_N0_C
UMI_CRX_FTX_P1_C
UMI_CRX_FTX_N1_C
UMI_CRX_FTX_P2_C
UMI_CRX_FTX_N2_C
UMI_CRX_FTX_P3_C
UMI_CRX_FTX_N3_C

UMI_CTX_FRX_P0_C
UMI_CTX_FRX_N0_C
UMI_CTX_FRX_P1_C
UMI_CTX_FRX_N1_C
UMI_CTX_FRX_P2_C
UMI_CTX_FRX_N2_C
UMI_CTX_FRX_P3_C
UMI_CTX_FRX_N3_C

CLK_CALRN

FCH_XTAL25_IN

FCH_XTAL25_OUT

EC_A_RST#P LT_RST#

0_0402_5%

UH2A

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

218084401A1BOLTONM3_FCBGA656

BOLTON-M3

+3VALW

CLK_PCI_EC

Part 1 of 5

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI EXPRESS INTERFACES

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41

REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

LPC

LDRQ1#/CLK_REQ6#/GPIO49

APU

S5 PLUS

PCICLK0

PCICLK1/GPO36

PCICLK2/GPO37

PCICLK3/GPO38

PCIRST#

AD0/GPIO0

AD1/GPIO1

AD2/GPIO2

AD3/GPIO3

AD4/GPIO4

AD5/GPIO5

AD6/GPIO6

AD7/GPIO7

AD8/GPIO8

AD9/GPIO9

AD10/GPIO10

AD11/GPIO11

AD12/GPIO12

AD13/GPIO13

AD14/GPIO14

AD15/GPIO15

AD16/GPIO16

AD17/GPIO17

AD18/GPIO18

AD19/GPIO19

AD20/GPIO20

AD21/GPIO21

AD22/GPIO22

AD23/GPIO23

AD24/GPIO24

AD25/GPIO25

AD26/GPIO26

AD27/GPIO27

AD28/GPIO28

AD29/GPIO29

AD30/GPIO30

AD31/GPIO31

CBE0#

CBE1#

CBE2#

CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

STOP#

PERR#

SERR#

REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

CLKRUN#

LOCK#

INTE#/GPIO32

INTF#/GPIO33

INTG#/GPIO34

INTH#/GPIO35

LPCCLK0

LPCCLK1

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

32K_X1

32K_X2

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

AF3

PCICLK0

AF1

PCICLK1

AF5
AG2

PCICLK3

AF6

PCICLK4

AB5

AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10

PAR

AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9

AF18
AE18
AC16
AD18

TPV38 Test_Point_20MIL

Spare one PCH pin to add FCH_WLAN_OFF#

Change DGPU_PWROK_R from UH2.AG26 to UH2.AH14

1

TPH2

HOLD_RST#_R
DGPU_PWREN_R

1

TPH1

ODD_DA_INTH#

Add ODD_DA_INTH# Core Power Well on 20130930

B25

LPC_CLK0

D25

LPC_CLK1

D27

LPC_AD0

LAD0

C28

LPC_AD1

LAD1

A26

LPC_AD2

LAD2

A29

LPC_AD3

LAD3

A31

LPC_FRAME#

B27
AE27
AE19

SERIRQ

G25

ALLOW_STOP

E28

FCH_PROCHOT#

E26

APU_PWROK

G26
F26

APU_RESET#

G2

FCH_XTAL32X1

G4

FCH_XTAL32X2

H7

FCH_S5

F1

RTC_CLK

F3
E6

+RTCBATT_R

1U_0402_10V6-K

1

FCH_WLAN_OFF#

PCH_BT_DISABLE#

PCI_AD23 16
PCI_AD24 16
PCI_AD25 16
PCI_AD26 16
PCI_AD27 16

Test_Point_12MIL

Test_Point_12MIL

internal PU 8.2K

33_0402_5%

1 2

W=20mils

1

1K_0402_1%

CH18

2

PCICLK0 33

PCICLK1 16

PCICLK3 16
PCICLK4 16

1 2

RH85

12
12

ODD_DA_INTH# 32

RH86

12

LPC_CLK1 16

LPC_AD0 38
LPC_AD1 38
LPC_AD2 38
LPC_AD3 38

LPC_FRAME# 38

SERIRQ 38

ALLOW_STOP 7
FCH_PROCHOT# 7

APU_PWROK 7,52

APU_RESET# 7

FCH_S5 38

RTC_CLK 16

RH21

FCH_WLAN_OFF# 33

PCH_BT_DISABLE# 33

DGPU_PWROKDGPU_PWROK_R

0_0402_5%

RH880_0402_5% DIS@
RH900_0402_5% DIS@

DGPU_HOLD_RST# 17

DGPU_PWREN 17,24,51

CLK_PCI_EC 16,38

VCCRTC

Follow Edge to ch ange UE1.Pin35 from VSB_ON to FCH_S5 on 0927

JCMOS1
SHORT PADS

@

1 2

PCH_BT_DISABLE#

FCH_WLAN_OFF#

DGPU_PWROK 38,51

LPC_CLK0

1

CH22
22P_0402_50V8-J

@

2

HOLD_RST#_R

RH148 10K_0402_5%

Follow Edge to put pull down 10k for HOLD_RST#_R

DGPU_PWREN_R

DGPU_PWROK_R

Follow Edge to put pull down 100k for DGPU_PWROK_R

Follow Edge to put pull down 100k for
DGPU_PWREN_R

Check DGPU_PWREN_R and DGPU_PWROK_R pull up or down with AMD and PWR

RTC Crystal

1

CH19

22P_0402_50V8-J

2

1 2

RH99 10K_0402_5%@

1 2

RH23 10K_0402_5%

1 2

RH25 10K_0402_5%

1 2

1 2

RH146 100K_0402_5%

@

1 2

RH147 100K_0402_5%

RH31

1 2

20M_0402_5%

1 2

YH2

32.768KHZ_12.5PF_200458-PG14

+3VS

FCH_XTAL32X1

FCH_XTAL32X2

1

22P_0402_50V8-J

2

+3VS

+3VS

CH20

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

FCH PCIe/PCI/LPC/APU/S5+

FCH PCIe/PCI/LPC/APU/S5+

FCH PCIe/PCI/LPC/APU/S5+

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

12 52

12 52

12 52

1.A

1.A

1.A

1

2

3

4

5

Add table on 2013 1001

BOARD ID
Config.

UH2B

SERIAL ATA

HW MONITOR

Part 2 of 5

SD_CLK/SCLK_0/GPIO73

SD_CMD/SLOAD_0/GPIO74

SD_DATA0/SDATI_0/GPIO77

SD_DATA1/SDATO_0/GPIO78

SD CARD

GBE LAN

ROM_RST#/SPI_WP#/GPIO161

SPI ROM

VGA DAC

VGA MAINLINK

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

SD_CD#/GPIO75

SD_WP/GPIO76

SD_DATA2/GPIO79

SD_DATA3/GPIO80

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3

GBE_RXD2

GBE_RXD1

GBE_RXD0

GBE_RXCTL/RXDV

GBE_RXERR

GBE_TXCLK

GBE_TXD3

GBE_TXD2

GBE_TXD1

GBE_TXD0

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

VGA_RED

VGA_GREEN

VGA_BLUE

VGA_HSYNC/GPO68

VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P

AUX_VGA_CH_N

AUXCAL

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

ML_VGA_HPD/GPIO229

VIN0/GPIO175

VIN1/GPIO176

VIN2/SDATI_1/GPIO177

VIN5/SCLK_1/GPIO180

AL14
AN14
AJ12

SKU ID

AH12

PANEL ID

AK13

CMOS_ON#

AM13
AH15
AJ14

AC4
AD3

delete BT_DET# on UH2.AM13 on 2013 0927

AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9

delete PROJECT ID on UH2.AN14 on 2013 1001

AG6
AE8
AD8
AB9

GBE_PHY_INTR

AC2
AA7
W9

GBE_PHY_INTR

V6

SPI_SI

V5

SPI_SO

V3

SPI_CLK

T6

SPI_CS1#

V1

SPI_WP#

L30

L32

M29

M28

FCH_CRT_HSYNC

N30

FCH_CRT_VSYNC

M33

FCH_CRT_DDC_DATA

N32

FCH_CRT_DDC_CLK

K31

RH151 715_0402_1%

V28

APU_VGA_AUX_C

V29

APU_VGA_AUX#_C

U28

RH150 100_0402_5%

T31

APU_VGA_TXP0

T33

APU_VGA_TXN0

T29

APU_VGA_TXP1

T28

APU_VGA_TXN1

R32

APU_VGA_TXP2

R30

APU_VGA_TXN2

P29

APU_VGA_TXP3

P28

APU_VGA_TXN3

C29

FCH_CRT_HPD

N2

GPIO175

M3

GPIO176

L2

GPIO177

N4

GPIO178

P1

GPIO179

P3

GPIO180

M1

GPIO181

M5

GPIO182

AG16

NC1

AH10

NC2

A28

NC3

G27

NC4

L4

NC5

GPIO175
GPIO176

GPIO182

CMOS_ON# 27

1 2

RH82 10K_0402_5%

SPI_SI 38

SPI_SO 38

SPI_CLK 38
SPI_CS1# 38

1 2

RH19 150_0402_5%

1 2

RH20 150_0402_5%

1 2

RH29 150_0402_5%

1 2

1 2

CC115 .1U_0402_16V7K

1 2

CC114 .1U_0402_16V7K

1 2

1

TPH43

Test_Point_12MIL

1

TPH44

Test_Point_12MIL

1

TPH45

Test_Point_12MIL

1

TPH46

Test_Point_12MIL

1

TPH47

Test_Point_12MIL

RPH2

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

SPI_WP#

SPI_HOLD#_8MB
SPI_CS1#_8MB

@

Need to enable internal
pull down to leave
unconnected
GPIO177~181 need bios
Pull down internally

RPH6

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

A A

HDD

ODD

B B

+VDDAN_11_SATA

SATA_FTX_DRX_P032
SATA_FTX_DRX_N032

SATA_FRX_DTX_N032
SATA_FRX_DTX_P032

SATA_FTX_DRX_P132
SATA_FTX_DRX_N132

SATA_FRX_DTX_N132
SATA_FRX_DTX_P132

1 2

RH32 1K_0402_1%

1 2

RH33 931_0402_1%

RH83 10K_0402_5%@

+3VS

1 2

RH108 10K_0402_5%

12

SATA_FTX_DRX_P0
SATA_FTX_DRX_N0

SATA_FRX_DTX_N0
SATA_FRX_DTX_P0

SATA_FTX_DRX_P1
SATA_FTX_DRX_N1

SATA_FRX_DTX_N1
SATA_FRX_DTX_P1

FCH_GPIO67

FCH_GPIO67

SATA_CALRP

SATA_CALRN

AK19
AM19

AN20

AN22

AH20

AH22

AM23
AK23

AH24

AN24

AN26

AH26

AN29

AK27
AM27

AN31

AH33
AH31

AD22

AL20

AL22

AJ20

AJ22

AJ24

AL24

AL26

AJ26

AL28

AL29

AL31
AL33

AJ33
AJ31

AF28
AF27

AF21

AG21

AH16
AM15

ODD_EN

GPIO172
GPIO173
GPIO174

AK15
AN16

AJ16

AL16

M6

C C

D D

ODD_EN32

RPH3

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

BOLTON-M3

SATA_TX0P

SATA_TX0N

SATA_RX0N

SATA_RX0P

SATA_TX1P

SATA_TX1N

SATA_RX1N

SATA_RX1P

SATA_TX2P

SATA_TX2N

SATA_RX2N

SATA_RX2P

SATA_TX3P

SATA_TX3N

SATA_RX3N

SATA_RX3P

SATA_TX4P

SATA_TX4N

SATA_RX4N

SATA_RX4P

SATA_TX5P

SATA_TX5N

SATA_RX5N

SATA_RX5P

NC6

NC7

NC8

NC9

NC10

NC11

NC12

NC13

SATA_CALRP

SATA_CALRN

SATA_ACT#/GPIO67

SATA_X1

SATA_X2

FANOUT0/GPIO52

FANOUT1/GPIO53

FANOUT2/GPIO54

FANIN0/GPIO56

FANIN1/GPIO57

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

TEMPIN3/TALERT#/GPIO174

218084401A1BOLTONM3_FCBGA656

Function

SKU ID

0

UMA@

1

DIS@

+3VALW

FCH_CRT_R 29

FCH_CRT_G 29

FCH_CRT_B 29

FCH_CRT_HSYNC 29
FCH_CRT_VSYNC 29

FCH_CRT_DDC_DATA 29
FCH_CRT_DDC_CLK 29

APU_VGA_AUX 7
APU_VGA_AUX# 7

VDDAN_11_ML

APU_VGA_TXP0 7
APU_VGA_TXN0 7
APU_VGA_TXP1 7
APU_VGA_TXN1 7
APU_VGA_TXP2 7
APU_VGA_TXN2 7
APU_VGA_TXP3 7
APU_VGA_TXN3 7

+3V_SPI

PANEL ID

0

1

Function

14@

15@

SKU ID

PANEL ID

8M SPI ROM

SPI_SO

SPI_SI

SPI_CLK

SPI_CS1#

short +3V_SPI and +3VALW directly

+3VALW +3V_SPI

UH1

SPI_CS1#_8MB

SPI_SI_8MB

SPI_WP# SPI_CLK_8MB

1

CS#

2

DO

3

WP#

GND4DI

W25Q64FVSSIG_SO8

SA000039A2J

HOLD#

VCC

CLK

To APU_VGA_HPD

+3VALW

RH122
10K_0402_5%

1 2

1 3

D

2N7002KW_SOT323-3

RH121 0_0402_5%@

+3VS

RH94

10K_0402_5%

DIS@

1 2

RH95

10K_0402_5%

UMA@

1 2

1 2

RH70 0_0402_5%

1 2

RH71 0_0402_5%

1 2

RH72 0_0402_5%

1 2

RH73 0_0402_5%

+3V_SPI

8

7

SPI_HOLD#_8MB

6

5

SPI_SO_8MB

2

1

Modify level shift on 2013 1001

+3VS

2

G

QH4

1 2

RH120
10K_0402_5%

1 2

S

APU_VGA_HPDFCH_CRT_HPD

RH96
10K_0402_5%

15@

1 2

RH97
10K_0402_5%

14@

1 2

SPI_SO_8MB

SPI_SI_8MB

SPI_CLK_8MB

SPI_CS1#_8MB

CH21

0.1U_0402_10V7-K

SPI_HOLD#_8MB 14

APU_VGA_HPD 7

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

FCH SATA/GBE/SPI

FCH SATA/GBE/SPI

FCH SATA/GBE/SPI

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

of

13 52

13 52

13 52

1.A

1.A

1.A

1

2

3

4

5

+3VS

1 2

RH53 10K_0402_5%

RPC14

1 8
2 7

+3VALW

A A

3 6
4 5

2.2K_0804_5%

SD30922018J

@

1 2

RH38 10K_0402_5%

RH87 10K_0402_5%

RH37 10K_0402_5%@

RH98 10K_0402_5%@

RH100 10K_0402_5%

1 2

1 2

RPH1

1 8
2 7
3 6
4 5

12

12

10K_0804_8P4R_5%

1 2

RH68 10K_0402_5%@

1 2

RH67 10K_0402_5%@

1 2

RH105 10K_0402_5%@

1 2

RH106 10K_0402_5%@

1 2

B B

C C

D D

RH107 10K_0402_5%@

HDA_BITCLK_AUDIO34
HDA_SDOUT_AUDIO34
HDA_SYNC_AUDIO34
HDA_RST_AUDIO#34

WD_PWRGD

FCH_SMB0CLK
FCH_SMB0DATA
FCH_SMB1CLK
FCH_SMB1DATA

WD_PWRGD

PBTN_OUT#

EC_WAKE#

ODD_DA#_FCH

AC_PRESENT

FCH_SMB2CLK
FCH_SMB2DATA

USB_OC1#
USB_OC0#

With S5 plus,PBTN _OUT# pull Up /With out S5 plus,PBTN_OUT # pull low

GPU_WAKE#18

PM_SLP_S3#38
PM_SLP_S5#38
PBTN_OUT#38
FCH_PWROK38

GPU_WAKE#

PM_SLP_S3#
PM_SLP_S5#

PBTN_OUT#

FCH_PWROK

Test_Point_12MIL
Test_Point_12MIL

Test_Point_12MIL

GATEA2038
KBRST#38
EC_SCI#38

delete net name EC_SMI# on UH2.C26 on 20130928

Change net nam e from PCIE_WAKE# to EC_WAKE# on 20130928

EC_WAKE#18,38

H_THERMTRIP#7,18

EC_RSMRST#38

Reserve CH9 and unmounted on 20130927

LAN_CLKREQ#35

FCH_SPKR34

HDA_SDIN0
HDA_BITCLK_AUDIO
AZ_SDIN1
AZ_SDIN2
AZ_SDIN3

SPI_HOLD#_8MB13

CLKREQ_WLAN#33

delete BATT_LEN# on UH1.J2

1 2

RH77 0_0402_5%

GPU_CLKREQ17

Change DGPU_PWROK_R from UH2.AG26 to UH2.AH14

ODD_DA#_FCH32

ODD_DETECT#32
AC_PRESENT38

USB_OC1#31

HDA_BITCLK_AUDIO

HDA_SDOUT_AUDIO

HDA_SYNC_AUDIO
HDA_RST_AUDIO#

RPH5

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

SD300003700

AZ_BITCLK
AZ_SDOUT

AZ_SYNC

AZ_RST#

USB_OC0#30

HDA_SDIN034

RH102

1 2

RH143 0_0402_5%

1 2

RH145

1 2

0_0402_5%

1

TPH3

1

TPH4

1

TPH5

Test_Point_12MIL

delete EC_LID_OUT# from UE1.Pin21 and UH2.R2 ,add GPU_WAKE#_R on U H2.R2

UH2D

AB6

PCIE_RST2#/GEVENT4#

R2

RI#/GEVENT22#

W7

0_0402_5%

FCH_PWROK_R

TEST0
TEST1
TEST2
GATEA20
KBRST#
EC_SCI#

EC_WAKE#

H_THERMTRIP#
WD_PWRGD

EC_RSMRST#

LAN_CLKREQ#

FCH_SPKR
FCH_SMB0CLK
FCH_SMB0DATA
FCH_SMB1CLK
FCH_SMB1DATA
CLKREQ_WLAN#

SPI_HOLD#

GPU_CLKREQ

ODD_DA#_FCH

ODD_DETECT#
AC_PRESENT

USB_OC1#
USB_OC0#

AZ_BITCLK
AZ_SDOUT
HDA_SDIN0
AZ_SDIN1
AZ_SDIN2
AZ_SDIN3
AZ_SYNC
AZ_RST#

PM_SLP_S3#_R
PM_SLP_S5#_R

TPH27

1

1

TPH6Test_Point_12MIL

1

TPH7Test_Point_12MIL

1

TPH30Test_Point_12MIL

1

TPH31Test_Point_12MIL

1

TPH26Test_Point_12MIL

1

TPH28Test_Point_12MIL

1

TPH8Test_Point_12MIL

1

TPH9Test_Point_12MIL

1

TPH10Test_Point_12MIL

1

TPH11Test_Point_12MIL

1

TPH12Test_Point_12MIL

1

TPH13Test_Point_12MIL

1

TPH14Test_Point_12MIL

1

TPH15Test_Point_12MIL

1

TPH16Test_Point_12MIL

1

TPH17Test_Point_12MIL

1

TPH18Test_Point_12MIL

1

TPH19Test_Point_12MIL

1

TPH20Test_Point_12MIL

1

TPH21Test_Point_12MIL

1

TPH22Test_Point_12MIL

1

TPH23Test_Point_12MIL

1

TPH24Test_Point_12MIL

1

TPH25Test_Point_12MIL

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVENT2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN#/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/GEVENT12#/TRST

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/XDB0/GPIO223

B17

KSO_15/XDB1/GPIO224

A24

KSO_16/XDB2/GPIO225

D17

KSO_17/XDB3/GPIO226

BOLTON-M3

Part 4 of 5

HD AUDIO

218084401A1BOLTONM3_FCBGA656

EMBEDDED CTRL

USBCLK/14M_25M_48M_OSC

USB MISC

USB 1.1

ACPI / WAKE UP EVENTS

USB 2.0

GPIO

USB OC

USB 3.0

EC_PWM0/EC_TIMER0/GPIO197

EC_PWM1/EC_TIMER1/GPIO198

EC_PWM2/EC_TIMER2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER3/GPIO200

USB_RCOMP

USB_FSD1P/GPIO186

USB_FSD1N

USB_FSD0P/GPIO185

USB_FSD0N

USB_HSD13P

USB_HSD13N

USB_HSD12P

USB_HSD12N

USB_HSD11P

USB_HSD11N

USB_HSD10P

USB_HSD10N

USB_HSD9P

USB_HSD9N

USB_HSD8P

USB_HSD8N

USB_HSD7P

USB_HSD7N

USB_HSD6P

USB_HSD6N

USB_HSD5P

USB_HSD5N

USB_HSD4P

USB_HSD4N

USB_HSD3P

USB_HSD3N

USB_HSD2P

USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P

USB_HSD0N

USBSS_CALRP

USBSS_CALRN

USB_SS_TX3P

USB_SS_TX3N

USB_SS_RX3P

USB_SS_RX3N

USB_SS_TX2P

USB_SS_TX2N

USB_SS_RX2P

USB_SS_RX2N

USB_SS_TX1P

USB_SS_TX1N

USB_SS_RX1P

USB_SS_RX1N

USB_SS_TX0P

USB_SS_TX0N

USB_SS_RX0P

USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194

SCL3_LV/GPIO195

SDA3_LV/GPIO196

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

G8

B9

H1
H3

H6
H5

H10
G10

K10
J12

G12
F12

K12
K13

B11
D11

E10
F10

C10
A10

H9
G9

A8
C8

F8
E8

C6
A6

C5
A5

C1
C3

E1
E3

C16
A16

A14
C14

C12
A12

D15
B15

E14
F14

F15
G15

H13
G13

J16
H16

J15
K15

H19
G19
G22
G21
E22
H22
J22
H21

K21
K22
F22
F24
E24
B23
C24
F18

USB_RCOMP

RH45 11.8K_0402_5%

USB20_P12
USB20_N12

USB20_P6
USB20_N6

USB20_P5
USB20_N5

USB20_P8
USB20_N8

USB20_P11
USB20_N11

USB20_P4
USB20_N4

USB20_P10
USB20_N10

USBSS_CALRP
USBSS_CALRN

USB30_TX_P1
USB30_TX_N1

USB30_RX_P1
USB30_RX_N1

FCH_SMB2CLK
FCH_SMB2DATA
EC_SMBLV_CK
EC_SMBLV_DA

1

TPH29

EC_PWM2

GPU, EC, Thermal Sensor

1 2

USB20_P12 31
USB20_N12 31

USB20_P6 33
USB20_N6 33

USB20_P5 27
USB20_N5 27

USB20_P8 27
USB20_N8 27

USB20_P11 31
USB20_N11 31

USB20_P4 30
USB20_N4 30

USB20_P10 30
USB20_N10 30

1 2

RH46 1K_0402_1%

1 2

RH47 1K_0402_1%

USB30_TX_P1 31
USB30_TX_N1 31

USB30_RX_P1 31
USB30_RX_N1 31

Test_Point_12MIL

EC_PWM2 16

RH39

10K_0402_5%

1 2

APU SIC/SIV

RH40

10K_0402_5%

1 2

+3VS

2N7002KDWH

2

G

Vth= min 1V, max 2.5V
ESD 2KV

FCH_SMB1CLK EC_SMB_CK3

FCH_SMB1DATA EC_SMB_DA3

6 1

5

G

3 4

S

D

QH1B
2N7002KDWH_SOT363-6

SB00000EO1J

S

D

QH1A
2N7002KDWH_SOT363-6

SB00000EO1J

JUSB2(Left)

WLAN

Camera

Touch Screen(Reserved)

JUSB1(Left)

Card Reader

USB/B (Right)

+VDDAN_11_SSUSB_S

JUSB2(Left)

EC_SMBLV_CK 7
EC_SMBLV_DA 7

Follow Edge to connect with 0 ohm directly on 20131009

RH153

0_0402_5%

FCH_SMB0CLK

FCH_SMB0DATA

1 2

1 2

RH154

0_0402_5%

SMB0_CLK

SMB0_DATA

EC_SMB_CK3 7,18,37,38

EC_SMB_DA3 7,18,37,38

SMB0_CLK 10,11,33

SMB0_DATA 10,11,33

Delete Security EEPROM USROM3 ,unused

1

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

FCH ACPI/USB/GPIO

FCH ACPI/USB/GPIO

FCH ACPI/USB/GPIO

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

14 52

14 52

14 52

1.A

1.A

1.A

1

2

3

4

5

VDDPL_33_SATA & PCIE & SYS

+3VS

22u *1, 1u*1 for circuit check list

+VDDCR_11+3VS

CH44

0.1U_0402_10V7-K

1

0_0805_5%

2

+VDDAN_11_CLK

CH49

22U_0603_6.3V6-M

1

2

+VDDAN_11_PCIE

1 2

0_0603_5%

+VDDAN_11_SATA

0_0805_5%

+3VALW +3VALW

RH79

CH65

+3VALWVDDAN_33_HWM

LH9

CH63

+3VS

RH81

RH101

+1.5VS

0_0402_5%

0_0603_5%

RH78

1 2

A A

+VDDPL_33_SYS

VDDPL_33_DACML

VDDAN_33_DAC_R

+VDDPL_33_SSUSB_S
+VDDPL_33_USB_S
+VDDPL_33_PCIE
+VDDPL_33_SATA

+1.1VS

LH17

1 2

BLM18BB470SN1D_2P~D

RH149

1 2

0_0603_5%

VDDAN_11_ML

B B

VDDIO_33_PCIGP

22U_0603_6.3V6-M

1

1

CH23

CH24

2

2

0.1U_0402_10V7-K

1 2

RH57 0_0402_5%

1 2

RH58 0_0402_5%

1 2

CH27 2.2U_0402_6.3V6-M@

CH12

CH13

CH14

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

1

2

2

1

1

CH25

2

0.1U_0402_10V7-K

VDDPL_33_DAC

VDDPL_33_ML

0.1U_0402_10V7-K

2

1

1

CH26

2

0.1U_0402_10V7-K

226mA

102mA

47mA

20mA

12mA

AB17
AB18

AD10

AC13
AB12
AB13
AB14
AB16

AH29
AG28

AB10

AB11
AA11

AA10

AE9

AG7

H24
V22
U22

T22
L18

D7

M31

V21

Y22
V23
V24
V25

AA9

UH2C

BOLTON-M3

VDDIO_33_PCIGP_1

VDDIO_33_PCIGP_2

VDDIO_33_PCIGP_3

VDDIO_33_PCIGP_4

VDDIO_33_PCIGP_5

VDDIO_33_PCIGP_6

VDDIO_33_PCIGP_7

VDDIO_33_PCIGP_8

VDDIO_33_PCIGP_9

VDDIO_33_PCIGP_10

VDDPL_33_SYS

VDDPL_33_DAC

VDDPL_33_ML

VDDAN_33_DAC

VDDPL_33_SSUSB_S

VDDPL_33_USB_S

VDDPL_33_PCIE

VDDPL_33_SATA

LDO_CAP

VDDPL_11_DAC

VDDAN_11_ML_1

VDDAN_11_ML_2

VDDAN_11_ML_3

VDDAN_11_ML_4

VDDIO_33_GBE_S

VDDCR_11_GBE_S_1

VDDCR_11_GBE_S_2

VDDIO_GBE_S_1

VDDIO_GBE_S_2

Part 3 of 5

PCI/GPIO I/O

CLKGEN I/O

MAIN LINK

PCI EXPRESS

SERIAL ATA

GBE LAN

CORE S0

VDDCR_11_1

VDDCR_11_2

VDDCR_11_3

VDDCR_11_4

VDDCR_11_5

VDDCR_11_6

VDDCR_11_7

VDDCR_11_8

VDDCR_11_9

VDDAN_11_CLK_1

VDDAN_11_CLK_2

VDDAN_11_CLK_3

VDDAN_11_CLK_4

VDDAN_11_CLK_5

VDDAN_11_CLK_6

VDDAN_11_CLK_7

VDDAN_11_CLK_8

VDDAN_11_PCIE_1

VDDAN_11_PCIE_2

VDDAN_11_PCIE_3

VDDAN_11_PCIE_4

VDDAN_11_PCIE_5

VDDAN_11_PCIE_6

VDDAN_11_PCIE_7

VDDAN_11_PCIE_8

VDDAN_11_SATA_1

VDDAN_11_SATA_4

VDDAN_11_SATA_2

VDDAN_11_SATA_3

VDDAN_11_SATA_5

VDDAN_11_SATA_6

VDDAN_11_SATA_7

VDDAN_11_SATA_8

VDDAN_11_SATA_9

VDDAN_11_SATA_10

T14
T17
T20
U16
U18
V14
V17
V20
Y17

H26
J25
K24
L22
M22
N21
N22
P22

AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27

AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19

1007mA

CH40

CH45

CH50

CH53

CH41

10U_0603_6.3V6-M

1

2

CH46

1U_0402_10V6-K

1

2

CH51

1U_0402_10V6-K

1

2

CH54

1U_0402_10V6-K

1

2

CH43

CH42

1U_0402_10V6-K

1

2

1U_0402_10V6-K

1

2

0.1U_0402_10V7-K

1

2

1U_0402_10V6-K

1

2

CH47

CH52

CH55

0.1U_0402_10V7-K

1U_0402_10V6-K

1

1

2

2

CH48

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1

1

2

2

22U_0603_6.3V6-M

1

2

CH56

22U_0603_6.3V6-M

0.1U_0402_10V7-K

1

1

2

2

+VDDAN_33_USB_S+3VALW

LH1

1 2

BLM15BD221SN1D_2P

CH28

CH29

CH30

CH31

10U_0603_6.3V6-M

10U_0603_6.3V6-M

1

1

2

2

CH32

1U_0402_10V6-K

1U_0402_10V6-K

1

1

2

2

+VDDAN_11_USB_S

+VDDCR_1.1V_USB

12

RH62
0_0402_5%

+VDDAN_11_SSUSB_S+1.1VALW

CH33

1

2

+VDDCR_11_SSUSB_S

CH36

1

2

CH34

CH35

1U_0402_10V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1

1

2

2

CH37

10U_0603_6.3V6-M

CH39

CH38

1U_0402_10V6-K

1

2

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1

1

2

2

LH2

1 2

BLM18BB470SN1D_2P~D

C C

+1.1VALW

LH3

1 2

BLM18BB470SN1D_2P~D

@

470mA

G7

0.1U_0402_25V7-K

1

2

VDDAN_33_USB_S_1

H8

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

3.3V_S5 I/O

USB

USB SS

POWER

218084401A1BOLTONM3_FCBGA656

VDDIO_33_S_1

VDDIO_33_S_2

VDDIO_33_S_3

VDDIO_33_S_4

VDDIO_33_S_5

VDDIO_33_S_6

VDDIO_33_S_7

VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1

VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM_S

VDDIO_AZ_S

N18
L19
M18
V12
V13
Y12
Y13
W11

G24

N20
M20

J24

M8

AA4

VDDIO_33_S

VDDXL_33_S

VDDCR_11_S

VDDPL_11_SYS_S

VDDIO_AZ_S

CH57

CH59

CH61

CH62

1U_0402_10V6-K

1

2

0.1U_0402_10V7-K

1

2

2.2U_0402_6.3V6-M

1

2

1 2

0_0603_5%

1 2

BLM15BD221SN1D_2P

1 2

0_0402_5%

@

1 2

CH58

1U_0402_10V6-K

2.2U_0402_6.3V6-M

1

1

2

2

CH60

2.2U_0402_6.3V6-M

1

2

RH61

RH63

RH84

0_0805_5%

RH89

1U_0402_10V6-K

1

2

0.1U_0402_10V7-K

1

2

CH67

CH66

CH64

+1.1VS

12

+1.1VS

+1.1VS

12

+1.1VS

12

LH7

1 2

2.2U_0402_6.3V6-M

BLM15BD221SN1D_2P

1

2

RH80 0_0603_5%

1 2

1U_0402_10V6-K

1

2

LH8

1 2

2.2U_0402_6.3V6-M

BLM15BD221SN1D_2P

1

2

VDDCR_1.1V_USB

VDDAN_11_USB_S

+1.1VALW

+1.1VALW

VDDPL_33_USB_S

VDDPL_33_SSUSB_S

LH12

1 2

BLM15BD221SN1D_2P

LH13

1 2

BLM15BD221SN1D_2P

LH14

1 2

BLM15BD221SN1D_2P

+1.1VALW

+1.1VALW

+VDDAN_33_USB_S +VDDPL_33_USB_S

VDDPL_33_DACMLVDDAN_33_DAC_R+3VS

LH18

1 2

BLM18PG221SN1D_2P

D D

+3VALW

+3VS

+1.1VALW

+1.1VS

+VDDAN_33_HWM,+VDDAN_33_USB_S,VDDPL_33_SSUSB_S,+VDDPL_33_USB_S

+VDDPL_33_SATA,+VDDPL_33_PCIE,+VDDPL_33_SYS

+VDDCR_11_SSUSB_S,+VDDAN_11_SSUSB_S,+VDDAN_11_USB_S,
+VDDAN_11_USB_S,+VDDCR_1.1V_USB

+VDDCR_11,+VDDAN_11_CLK,+VDDAN_11_PCIE,+VDDAN_11_SATA,

1

2

1

CH86

2

2.2U_0402_6.3V6-M

RH152

1 2

0_0603_5%

1

CH85

2

0.1U_0402_10V7-K

1

1

CH84

2

2

2.2U_0402_6.3V6-M

3

Add RH101 to reserve power rail +1.5VS

CH83

0.1U_0402_10V7-K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

1 2

BLM15BD221SN1D_2P

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

LH15

1 2

BLM15BD221SN1D_2P

LH16

1 2

BLM15BD221SN1D_2P

LH10

1 2

BLM15BD221SN1D_2P

LH11

Title

Title

Title

FCH POWER/GND

FCH POWER/GND

FCH POWER/GND

+VDDPL_33_SATA

+VDDPL_33_PCIE

+VDDPL_33_SYS

+VDDCR_1.1V_USB

1

CH76

2

+VDDAN_11_USB_S

1

CH79

2

1

2

+VDDPL_33_SSUSB_S+3VALW

1

2

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

1

2

1

2

1

2

1

2

10U_0603_6.3V6-M

1

2

2.2U_0402_6.3V6-M

CH68

2.2U_0402_6.3V6-M

CH70

2.2U_0402_6.3V6-M

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

CH74

CH77

CH80

1

2

1

2

CH72

2.2U_0402_6.3V6-M

CH73

2.2U_0402_6.3V6-M

2.2U_0402_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K

CH69

CH71

1

CH75

2

1

CH78

2

0.1U_0402_10V7-K

1

CH81

2

0.1U_0402_10V7-K

1U_0402_10V6-K

0.1U_0402_10V7-K

15 52

15 52

15 52

0.1U_0402_10V7-K

1.A

1.A

1.A

1

2

3

4

5

UH2E

BOLTON-M3

A3

VSS_1

A33

VSS_2

B7

VSS_3

B13

VSS_4

A A

B B

C C

D9

VSS_5

D13

VSS_6

E5

VSS_7

E12

VSS_8

E16

VSS_9

E29

VSS_10

F7

VSS_11

F9

VSS_12

F11

VSS_13

F13

VSS_14

F16

VSS_15

F17

VSS_16

F19

VSS_17

F23

VSS_18

F25

VSS_19

F29

VSS_20

G6

VSS_21

G16

VSS_22

G32

VSS_23

H12

VSS_24

H15

VSS_25

H29

VSS_26

J6

VSS_27

J9

VSS_28

J10

VSS_29

J13

VSS_30

J28

VSS_31

J32

VSS_32

K7

VSS_33

K16

VSS_34

K27

VSS_35

K28

VSS_36

L6

VSS_37

L12

VSS_38

L13

VSS_39

L15

VSS_40

L16

VSS_41

L21

VSS_42

M13

VSS_43

M16

VSS_44

M21

VSS_45

M25

VSS_46

N6

VSS_47

N11

VSS_48

N13

VSS_49

N23

VSS_50

N24

VSS_51

P12

VSS_52

P18

VSS_53

P20

VSS_54

P21

VSS_55

P31

VSS_56

P33

VSS_57

R4

VSS_58

R6

VSS_59

R11

VSS_60

R25

VSS_61

R28

VSS_62

T11

VSS_63

T16

VSS_64

T18

VSS_65

N8

VSSAN_HWM

K25

VSSXL

H25

VSSPL_SYS

218084401A1BOLTONM3_FCBGA656

Part 5 of 5

T25

VSS_66

T27

VSS_67

U6

VSS_68

U14

VSS_69

U17

VSS_70

U20

VSS_71

U21

VSS_72

U30

VSS_73

U32

VSS_74

V11

VSS_75

V16

VSS_76

V18

VSS_77

W4

VSS_78

W6

VSS_79

W25

VSS_80

W28

VSS_81

Y14

VSS_82

Y16

VSS_83

Y18

VSS_84

AA6

VSS_85

AA12

VSS_86

AA13

VSS_87

AA14

VSS_88

AA16

VSS_89

AA17

VSS_90

AA25

VSS_91

AA28

VSS_92

AA30

VSS_93

AA32

VSS_94

AB25

VSS_95

GROUND

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSSPL_DAC

VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33

T21
L28
K33
N28

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCICLK112

PCICLK312

PCICLK412

CLK_PCI_EC12,38

LPC_CLK112

EC_PWM214

RTC_CLK12

PCI_CLK3

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAP

DEFAULT

PCI_CLK4 CLK_PCI_EC

NON_FUSION
CLOCK MODE

FUSION
CLOCK
MODE

DEFAULT

RH128 10K_0402_5%

12

RH140 10K_0402_5%

12

@

EC
ENABLED

EC
DISABLED

DEFAULT

+3VS+3VS+3VS

RH132 10K_0402_5%

RH134 10K_0402_5%

12

12

@

@

RH137 10K_0402_5%

RH139 10K_0402_5%

12

12

+3VALW

12

12

RTC_CLKLPC_CLK1

S5 PLUS
MODE
DISABLED

S5 PLUS
MODE
ENABLED

DEFAULT

RH135 10K_0402_5%

@

RH144 10K_0402_5%

EC_PWM2

CLKGEN
ENABLED

DEFAULT

CLKGEN
DISABLE

+3VALW+3VALW

RH136 10K_0402_5%

12

12

@

RH141 10K_0402_5%

12

12

LPC ROM

SPI ROM

DEFAULT

+3VALW

RH133 10K_0402_5%

RH138 10K_0402_5%

12

@

R156 2.2K_0402_5%

RH142 10K_0402_5%

12

@

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD25 PCI_AD24

USE FC
PLL

BYPASS
FC PLL

RH126 10K_0402_5%

12

@

PULL
HIGH

PULL
LOW

PCI_AD2712

PCI_AD2612

PCI_AD2512

PCI_AD2412

PCI_AD2312

PCI_AD27 PCI_AD26

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

DISABLE
ILA
AUTORUN

DEFAULT

ENABLE
ILA
AUTORUN

need confirm AD26

RH127 10K_0402_5%

12

@

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

RH125 10K_0402_5%

12

@

PCI_AD23

DISABLE PCI
MEM BOOT

DEFAULTDEFAULT

ENABLE PCI
MEM BOOT

RH124 10K_0402_5%

12

@

RH123 10K_0402_5%

12

@

D D

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

FCH GND

FCH GND

FCH GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

16 52

16 52

16 52

1.A

1.A

1.A

1

2

3

4

5

UV3G

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

NC_121

U31

NC_122

U29

NC_123

T28

NC_124

T30

NC_125

R31

NC_126

R29

NC_127

P28

NC_128

P30

NC_129

N31

NC_130

N29

NC_131

M28

NC_132

M30

NC_133

L31

NC_134

L29

NC_135

K30

NC_136

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

TEST_PG

AL27

PERSTB

216-0858020-A0_FCBGA631

PCI EXPRESS INTERFACE

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

NC_137
NC_138

NC_139
NC_140

NC_141
NC_142

NC_143
NC_144

NC_145
NC_146

NC_147
NC_148

NC_149
NC_150

NC_151
NC_152

AH30
AG31

AG29
AF28

AF27
AF26

AD27
AD26

AC25
AB25

Y23
Y24

AB27
AB26

Y27
Y26

W24
W23

V27
U26

U24
U23

T26
T27

T24
T23

P27
P26

P24
P23

M27
N26

Y22

AA22

1 2

RV47 1.69K_0402_1%DIS@

RV48

1 2

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0

PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1

PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2

PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3

PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4

PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5

PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6

PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7

1K_0402_1%DIS@

+0.95VS_VGA

+3VS_VGA

12

RV50
10K_0402_5%

RV49

@

DGPU_PWREN12,24,51

GPU_CLKREQ14

10K_0402_5%

CV141

@

12

0.1U_0402_10V7-K

1

2

CV140

0.1U_0402_10V7-K

1

@

2

1 3

D

2N7002KW_SOT323-3

SB00000YY00

1 2

RV51 0_0402_5%

@

+3VS_VGA

12

@

RV52

QV7

2

G

@

S

@

10K_0402_5%

CLK_REQ_GPU#

RV53
10K_0402_5%

@

1 2

CLK_REQ_GPU# 18

RV42

0_0402_5%

PCIE_CTX_C_GRX_N[0..7]

PCIE_CTX_C_GRX_P[0..7]

PCIE_CRX_GTX_N[0..7]

PCIE_CRX_GTX_P[0..7]

+3VS

@

1

IN1

2

IN2

DIS@

5

VCC

GND

3

UV4

4

OUT

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3

PCIE_CRX_C_GTX_P4PCIE_CRX_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P5PCIE_CRX_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P6PCIE_CRX_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P7PCIE_CRX_GTX_P7
PCIE_CRX_C_GTX_N7

+3VS_VGA

12

RV43
10K_0402_5%

@

PLT_RST_VGA#

RV44

100K_0402_5%

DIS@

1 2

PLT_RST_VGA#

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

PLT_RST_VGA# 18,51

1 2

RV40 1K_0402_5%DIS@

1 2

RV41 0_0402_5%DIS@

GFX_CLKP
GFX_CLKN

GFX_CLKP12
GFX_CLKN12

PCIE_CTX_C_GRX_N[0..7]5

PCIE_CTX_C_GRX_P[0..7]5

PCIE_CRX_GTX_N[0..7]5

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_N4

PCIE_CRX_GTX_N5

PCIE_CRX_GTX_N6

PCIE_CRX_GTX_N7

PLT_RST#12,33,35

PCIE_CRX_GTX_P[0..7]5

CV132 0.1U_0402_16V7-KDIS@
CV133 0.1U_0402_16V7-KDIS@
CV134 0.1U_0402_16V7-KDIS@
CV135 0.1U_0402_16V7-KDIS@
CV136 0.1U_0402_16V7-KDIS@
CV137 0.1U_0402_16V7-KDIS@
CV138 0.1U_0402_16V7-KDIS@
CV139 0.1U_0402_16V7-KDIS@

CV157 0.1U_0402_16V7-KDIS@
CV158 0.1U_0402_16V7-KDIS@
CV159 0.1U_0402_16V7-KDIS@
CV175 0.1U_0402_16V7-KDIS@
CV176 0.1U_0402_16V7-KDIS@
CV177 0.1U_0402_16V7-KDIS@
CV178 0.1U_0402_16V7-KDIS@
CV179 0.1U_0402_16V7-KDIS@

PLT_RST#

DGPU_HOLD_RST#

MC74VHC1G08DFT2G_SC70-5

DIS@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

A A

B B

DGPU_HOLD_RST#12

C C

D D

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

2012/07/01

2012/07/01

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

2014/07/01

2014/07/01

2014/07/01

Title

Topaz & Jet PCIE

Topaz & Jet PCIE

Topaz & Jet PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Monday, December 16, 2013

Monday, December 16, 2013

Monday, December 16, 2013

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7

ACLU7ACLU7

ACLU7ACLU7

ACLU7ACLU7

5

17 65

17 65

17 65

1.A

1.A

1.A