Lenovo Ideapad G50-70M Schematic

A

1 1

B

C

D

E

LCFC Confidential

AMD 2 Chip M/B Schematics Document

2 2

AMD Kaveri Processor with DDRIIIL + Bolton FCH

AMD GPU JET PRO/TOPAZ XT S3

www.rosefix.com

2013-09-25

3 3

REV:0.1

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF LC FUTURE CENTER.

A

B

2013/05/17

C

LC Future Center Secret Data

Deciphered Date

2012/12/21

D

Title

Cover Page

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

Monday, December 16, 2013

ACLU7

ACLU7ACLU7

E

1 52

0.1

A

LCFC confidential

File Name : ACLU7&8

AMD Jet Pro/ Topaz XT S3 23mmX23mm Dual Rank

Page 18~24

VRAM 256/128*16

DDR3L*4 4GB/2GB

1 1

Page 25~26

B

PCI-Express

8x Gen2

PEG 0~7

AMD FP3 APU

C

Memory BUS (DDR3L) Dual Channel

1.35V DDR3L 1600 MT/s

D

DDR3L-SO-DIMM X2

Page 11,12

UP TO 8G x 2

E

eDP Conn

Int. Camera

Int. MIC Conn.

Page 28

USB2.0 Port3

HDMI Conn.

Page 29

HDMI

DP1

eDP x2 Lane

DP0

DPx4 Lane

DP2

For VGA translator

Kaveri BGA 854 pin 32mm x 29mm

Page 5~10

x4 UMI Gen. 2

PCIe 1x

LAN Realtek

RTL8111GUL (1G) RTL8106EUL (10M/100M)

Page 37

NGFF Card WLAN&BT

Page 34

PCIe Port0

PCIe Port2 USB2.0 Port6

RJ45 Conn.

Page 38

5.0GT/s per lane

2 2

CRT Conn.

Page 30

USB2.0 1x

SATA HDD

Page 33

SATA ODD

Page 33

SPI ROM

8MB

Page 12

3 3

SATA Port0

SATA Port1

SATA Gen3

SATA Gen1

SPI BUS

HD Audio

Bolton M3

uFCBGA-656

24.5mm x 24.5mm

Page 11~15

USB 2.0 1x

USB 3.0 1x

USB 2.0 2x

USB2.0 1x

USB Left

USB 3.0 Port1 USB 2.0 Port1

USB 2.0 Port2

Page 32

USB right

USB2.0 Port10

Cardreader Realtek RTS5170

USB2.0 Port4

Touch Screen

USB2.0 Port8

Page 28

SD/MMC Conn.

USB Board

Codec

Conexant CX20752

Page 36

SPK Conn.

Page 36

EC ITE IT8586E-LQFP

Page 41

Sub-board ( 14' & 15")

POWER BOARD(for 14")

I/O Board(USB,Audio,Card Read)

HP&Mic Combo Conn.

USB Board

Touch Pad Int.KBD

Page 31 Page 31

Thermal Sensor NCT7718W

Page 40

Sub-board ( Only 15")

POWER BOARD(for 15")

I/O Board(USB,Audio,Card Read)

4 4

ODD Board

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

C

2013/05/17

LC Future Center Secret Data

Deciphered Date

D

2012/12/21

Title

Block Diagram

Size Document Number Rev

C

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

E

2 52

0.1

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

S5 S4/AC Only

S5 S4 Battery only

S5 S4 AC & Battery don't exist

( O --> Means ON , X --> Means OFF )

+3VALW

B+

+1.5V

+5VALW

O

X X

O O O

OO

O

X

X X

X

+5VS

+3VS

+1.5VS

+VCCSA

+V1.5S_VCCP

+CPU_CORE

+VGA_CORE

+GFX_CORE

+1.8VS

+1.05VS

+0.75VS

+3.3VS_VGA

+1.5VS_VGA

+1.05VS_VGA

X

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

USB Port Table

USB 3.0USB 2.0 Port

XHCI

EHCI1

EHCI2

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

0

1

2

3

4

USB Port (Right Side)

2

USB Port (Left Side)

3

4 5

USB Port (Right Side)

6

7 8 9

10

Mini Card(WLAN)

11 12 13

HIGH

LOWLOWLOW

4 External USB Port

Camera

Blue Tooth

HIGHHIGHHIGH

HIGH

ONONON ON

ON

OFF

ON

OFF

BOM Structure Table

@ 100M@ 14@ 15@ AOAC@ GIGA@ JET@ ME@

DIS@ UMA@ TS@

TOPAZ@

A10@ A4@

EMC@

ON

OFF

LOW

OFF

BTO ItemBOM Structure

Not stuff

100M LAN Part

For 14" part

For 15" part

AOAC support part

GIGA LAN Part

For AMD Jet GPU part

ME part(connector, hole)

Discrete GPU SKU part

UMA SKU part

For support touch panel sku part

For AMD Topaz GPU part

For APU Kaveri A10(19W)S IC KAVERI

For APU Kaveri A4(17W)S IC KAVERI

EMC components

SMBUS Control Table

Main

SOURCE

3 3

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

PM_SMBCLK PM_SMBDATA

EC SM Bus1 address

Device

Smart Battery

4 4

IT8580EEC_SMB_CK1

+3VALW

IT8580E

+3VS

PCH

+3V_PCH

Address

0001 011X b

A

+3VS +3VS

2nd

BATT SODIMM

+3VALW

X

IT8580E

X

VGA

X

X X XV

V

X X X X X

EC SM Bus2 address

Device

Thermal Sensor EMC1403-2

Master VGA

Slave VGA

WLAN

Thermal

WiMAX

Sensor

X

V V

+3VS

V

X

+3VS

V

PCH SM Bus address

Address

1001_101xb

0x9E 0x9C

B

Device Address

DDR DIMM0

DDR DIMM2

PCH

V

+3V_PCH

+3V_PCH+3VS

CP Module

XX

X

V

+3VS

PCIE PORT LIST

Port Device

1 2 3 4 5 6 7 8

1001 000Xb

1001 010Xb

C

LAN WLAN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/12/05

LC Future Center Secret Data

Deciphered Date

D

2014/12/05

Title

Notes List

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

E

3 52

0.4

5

4

3

2

1

CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE

Power-Up/Down Sequence

"Topaz" has the following requirements with regards to power-supply sequencing to

D D

avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred. The maximum slew rate on all rails is 50 mV/米s. It is recommended that the 3.3-V rail ramp up first. The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 before VDDC, VDDCI, and VMEMIO start to ramp up. The power rails that are shared with other components on the system should be gated for the dGPU so that when the dGPU is powered down (for example AMD PowerXpress idle state), all the power rails are removed from the dGPU. The gate circuits must meet the slew rate requirement (such as ≒ 50 mV/米s). For power down, reversing the ramp-up sequence is recommended.

米

s

0 ~ 20ms

C C

VDDR3(+3VGS)

0 ~ 20ms

VDD_CT(+1.8VGS)

PCIE_VDDC(+0.95VGS)

10us min.

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

PERSTb(GPU_RST#)

100ms min.

100us min.

REFCLK(CLK_PCIE_VGA)

B B

GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

MLPS Bit DescriptionStrap Name

ROM_CONFIG[0]

PS_0[1]

ROM_CONFIG[1]

PS_0[2]

ROM_CONFIG[2]

PS_0[3]

PS_0[4] N/A

AUD_PORT_CONN_ PINSTRAP[0]

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_A

PS_1[2]

STRAP_BIF_CLK_PM_EN

PS_1[3]

STRAP_TX_CFG_DRV_ FULL_SWING

PS_1[4]

PS_1[5]

STRAP_TX_DEEMPH_EN

PS_2[1]

PS_2[2]

PS_2[3]

STRAP_BIOS_ROM_EN

PS_2[4]

STRAP_BIF_VGA_DIS

PS_2[5]

PS_3[1] PS_3[2] PS_3[3]

PS_3[4]

PS_3[5]

N/A Reserved 1

BOARD_CONFIG[0] BOARD_CONFIG[1] BOARD_CONFIG[2]

AUD_PORT_CONN_ PINSTRAP[1]

AUD_PORT_CONN_ PINSTRAP[2]

Define the ROM type when STRAP_BIOS_ROM_EN = 1, Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.

Reserved for internal use only. Must be 1 at reset.

The LSB (least significant bit) of the strap option that indicates the number of audio-capable display outputs.

1 = PCIe GEN3 is supported. 0 = PCIe GEN3 is not supported.

0 = The CLKREQB power management capability is disabled 1 = The CLKREQB power management capability is enabled

N/A

0 = The transmitter half-swing is enabled 1 = The transmitter full-swing is enabled

0 = Tx deemphasis disabled. 1 = Tx deemphasis enabled.

N/A

Reserved.

N/A

Reserved.

0 = Disable the external BIOS ROM device. 1 = Enable the external BIOS ROM device.

0 = VGA controller capacity enabled. 1 = The device will not be recognized as the system＊s VGA controller.

Board configuration related strapping, such as for memory ID

000 = Hynix 256M*16 100 = Samsung 256M*16 010 = Micron 256M*16

Determines the maximum number of digital display audio endpoints that will be presented to the OS and user.(Combine with PS_0[5]) 111 = No usable endpoints. 110 = One usable endpoint. 101 = Two usable endpoints. 100 = Three usable endpoints. 011 = Four usable endpoints. 010 = Five usable endpoints. 001 = Six usable endpoints. 000 = All endpoints are usable.

001 = Hynix 128M*16 011 = Samsung 128M*16 111 = Micron 128M*16

VRAM ID config

VRAM ID PU resistor PD resistor

PS_3[3:1]

100

111

110

000

010

001

128Mx16

256Mx16

Memory Type

Hynix

H5TC2G63FFR-11C

Micron

MT41J128M16JT-093G

Samsung

K4W2G1646Q-BC1A

Hynix

H5TC4G63AFR-11C

Micron

MT41J256M16HA-093G

Samsung

K4W4G1646D-BC1A

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

100 = 256MB

0= Not support

1= Enable

0= Disable

111= No usable endpoints.

RV33 RV36

4.53K 4.99K

NC 4.75K

4.53K 2K

8.45K 2K

RECOMMENDED SETTINGS

X

1

X

0

0Reserved for internal use only. Must be 0 at reset.

1

X

0

X

1

X

11

NC4.75K

10K3.4K

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/08

LC Future Center Secret Data

Deciphered Date

2

2013/08/05

Title

VGA Notes List

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

1

4 52

0.1

5

4

3

2

1

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

D D

PCIE_CRX_GTX_P05,17 PCIE_CRX_GTX_N05,17 PCIE_CRX_GTX_P15,17 PCIE_CRX_GTX_N15,17 PCIE_CRX_GTX_P25,17 PCIE_CRX_GTX_N25,17

GPU

C C

LAN

WLAN

+0.95VS_VDDP

B B

PCIE_CRX_GTX_P35,17 PCIE_CRX_GTX_N35,17 PCIE_CRX_GTX_P45,17 PCIE_CRX_GTX_N45,17 PCIE_CRX_GTX_P55,17 PCIE_CRX_GTX_N55,17 PCIE_CRX_GTX_P65,17 PCIE_CRX_GTX_N65,17 PCIE_CRX_GTX_P75,17 PCIE_CRX_GTX_N75,17

PCIE_CRX_DTX_P035 PCIE_CRX_DTX_N035

PCIE_CRX_DTX_P233 PCIE_CRX_DTX_N233

FCH

RC1 196_0402_0.5%

UMI_CRX_FTX_P012 UMI_CRX_FTX_N012 UMI_CRX_FTX_P112 UMI_CRX_FTX_N112 UMI_CRX_FTX_P212 UMI_CRX_FTX_N212 UMI_CRX_FTX_P312

1 2

PCIE_CRX_GTX_P[7..0] 5,17

PCIE_CRX_GTX_N[7..0] 5,17

UC1A

AG7

AN18

Y8 Y9

Y4 W5 W7 W8

U5

V4

U7

U8

T4

R5

R7

R8

P8

P7

P4

P5 M8 M7 M5 M4

L6

L5

L8

L9

J5

K4

J7

J8

H4

H5

AH4 AH3

AF6 AE8 AE7 AE5 AF4 AC9 AC8 AC6 AC5 AB9 AB8 AB4 AB5

AJ7 AJ8 AK6 AK7 AK5 AJ5 AL4 AK4

P_GFX_RXP0/RSVD

P_GFX_RXN0/RSVD

P_GFX_RXP1/RSVD

P_GFX_RXN1/RSVD

P_GFX_RXP2/RSVD

P_GFX_RXN2/RSVD

P_GFX_RXP3/RSVD

P_GFX_RXN3/RSVD

P_GFX_RXP4/RSVD

P_GFX_RXN4/RSVD

P_GFX_RXP5/RSVD

P_GFX_RXN5/RSVD

P_GFX_RXP6/RSVD

P_GFX_RXN6/RSVD

P_GFX_RXP7/RSVD

P_GFX_RXN7/RSVD

P_GFX_RXP8/RSVD

P_GFX_RXN8/RSVD

P_GFX_RXP9/RSVD

P_GFX_RXN9/RSVD

P_GFX_RXP10/RSVD

P_GFX_RXN10/RSVD

P_GFX_RXP11/RSVD

P_GFX_RXN11/RSVD

P_GFX_RXP12/RSVD

P_GFX_RXN12/RSVD

P_GFX_RXP13/RSVD

P_GFX_RXN13/RSVD

P_GFX_RXP14/RSVD

P_GFX_RXN14/RSVD

P_GFX_RXP15/RSVD

P_GFX_RXN15/RSVD

P_GPP_RXP0

P_GPP_RXN0

P_GPP_RXP1

P_GPP_RXN1

P_GPP_RXP2

P_GPP_RXN2

P_GPP_RXP3

P_GPP_RXN3

P_GPP_RXP4/RSVD

P_GPP_RXN4/RSVD

P_GPP_RXP5/RSVD

P_GPP_RXN5/RSVD

P_GPP_RXP6/RSVD

P_GPP_RXN6/RSVD

P_GPP_RXP7/RSVD

P_GPP_RXN7/RSVD

P_UMI_RXP0

P_UMI_RXN0

P_UMI_RXP1

P_UMI_RXN1

P_UMI_RXP2

P_UMI_RXN2

P_UMI_RXP3

P_UMI_RXN3

P_ZVDDP

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

PCIE_CRX_DTX_P0 PCIE_CRX_DTX_N0

PCIE_CRX_DTX_P2 PCIE_CRX_DTX_N2

UMI_CRX_FTX_P0 UMI_CRX_FTX_N0 UMI_CRX_FTX_P1 UMI_CRX_FTX_N1 UMI_CRX_FTX_P2 UMI_CRX_FTX_N2 UMI_CRX_FTX_P3 UMI_CRX_FTX_N3

KAVERI-2M186092H4467_BGA854

A10@

PCI EXPRESS

UMI GPP GRAPHICS

FP3 REV 0.52

P_GFX_TXP0/DP6_TXP4

P_GFX_TXN0/DP6_TXN4

P_GFX_TXP1/DP6_TXP5

P_GFX_TXN1/DP6_TXN5

P_GFX_TXP2/DP6_TXP6

P_GFX_TXN2/DP6_TXN6

P_GFX_TXP3/RSVD

P_GFX_TXN3/RSVD

P_GFX_TXP4/DP6_TXP0

P_GFX_TXN4/DP6_TXN0

P_GFX_TXP5/DP6_TXP1

P_GFX_TXN5/DP6_TXN1

P_GFX_TXP6/DP6_TXP2

P_GFX_TXN6/DP6_TXN2

P_GFX_TXP7/DP6_TXP3

P_GFX_TXN7/DP6_TXN3

P_GFX_TXP8/DP5_TXP0

P_GFX_TXN8/DP5_TXN0

P_GFX_TXP9/DP5_TXP1

P_GFX_TXN9/DP5_TXN1

P_GFX_TXP10/DP5_TXP2

P_GFX_TXN10/DP5_TXN2

P_GFX_TXP11/DP5_TXP3

P_GFX_TXN11/DP5_TXN3

P_GFX_TXP12/DP4_TXP0

P_GFX_TXN12/DP4_TXN0

P_GFX_TXP13/DP4_TXP1

P_GFX_TXN13/DP4_TXN1

P_GFX_TXP14/DP4_TXP2

P_GFX_TXN14/DP4_TXN2

P_GFX_TXP15/DP4_TXP3

P_GFX_TXN15/DP4_TXN3

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_GPP_TXP4/DP3_TXP0

P_GPP_TXN4/DP3_TXN0

P_GPP_TXP5/DP3_TXP1

P_GPP_TXN5/DP3_TXN1

P_GPP_TXP6/DP3_TXP2

P_GPP_TXN6/DP3_TXN2

P_GPP_TXP7/DP3_TXP3

P_GPP_TXN7/DP3_TXN3

P_UMI_TXP0

P_UMI_TXN0

P_UMI_TXP1

P_UMI_TXN1

P_UMI_TXP2

P_UMI_TXN2

P_UMI_TXP3

P_UMI_TXN3

P_ZVSS

PCIE_CTX_C_GRX_P[7..0]

PCIE_CTX_C_GRX_N[7..0]

FP3 Kaveri APU supports PCIE Gen2, AC copling capactiors value 0.1U. PCIE GEN3, AC copling capactiors value 0.22U

AB2

PCIE_CTX_GRX_P0

AB1

PCIE_CTX_GRX_N0

AB3

PCIE_CTX_GRX_P1

AA2

PCIE_CTX_GRX_N1

AA1

PCIE_CTX_GRX_P2

Y1

PCIE_CTX_GRX_N2

Y2

PCIE_CTX_GRX_P3

W2

PCIE_CTX_GRX_N3 PCIE_CTX_C_GRX_N3

V2

PCIE_CTX_GRX_P4

V1

PCIE_CTX_GRX_N4

V3

PCIE_CTX_GRX_P5

U2

PCIE_CTX_GRX_N5

U1

PCIE_CTX_GRX_P6

T1

PCIE_CTX_GRX_N6

T2

PCIE_CTX_GRX_P7

R2

PCIE_CTX_GRX_N7 PCIE_CTX_C_GRX_N7

P2 P1 P3 N2 N1 M1 M2 L2 K2 K1 K3 J2 J1 H1 H2 G2

AM2

PCIE_CTX_DRX_P0

AM1

PCIE_CTX_DRX_N0

AL2 AL1 AK2

PCIE_CTX_DRX_P2

AK1

PCIE_CTX_DRX_N2

AK3 AJ2 AJ1 AH1 AH2 AG2 AF2 AF1 AF3 AE2

AM9

UMI_CTX_FRX_P0

AM10

UMI_CTX_FRX_N0

AN8

UMI_CTX_FRX_P1

AN9

UMI_CTX_FRX_N1

AM7

UMI_CTX_FRX_P2

AM8

UMI_CTX_FRX_N2

AN6

UMI_CTX_FRX_P3

AM6

UMI_CTX_FRX_N3 UMI_CTX_FRX_N3_C

AM18

P_ZVSSP_ZVDDP

1 2

RC2 196_0402_0.5%

1 2

CC1 0.1U_0402_16V7-KDIS@

1 2

CC2 0.1U_0402_16V7-KDIS@

1 2

CC3 0.1U_0402_16V7-KDIS@

1 2

CC4 0.1U_0402_16V7-KDIS@

1 2

CC5 0.1U_0402_16V7-KDIS@

1 2

CC6 0.1U_0402_16V7-KDIS@

1 2

CC7 0.1U_0402_16V7-KDIS@

1 2

CC8 0.1U_0402_16V7-KDIS@

1 2

CC106 0.1U_0402_16V7-KDIS@

1 2

CC107 0.1U_0402_16V7-KDIS@

1 2

CC108 0.1U_0402_16V7-KDIS@

1 2

CC109 0.1U_0402_16V7-KDIS@

1 2

CC110 0.1U_0402_16V7-KDIS@

1 2

CC111 0.1U_0402_16V7-KDIS@

1 2

CC112 0.1U_0402_16V7-KDIS@

1 2

CC113 0.1U_0402_16V7-KDIS@

1 2

CC9 0.1U_0402_10V7-K

1 2

CC10 0.1U_0402_10V7-K

1 2

CC13 0.1U_0402_10V7-K

1 2

CC14 0.1U_0402_10V7-K

1 2

CC15 0.1U_0402_10V7-K

1 2

CC16 0.1U_0402_10V7-K

1 2

CC17 0.1U_0402_10V7-K

1 2

CC18 0.1U_0402_10V7-K

1 2

CC19 0.1U_0402_10V7-K

1 2

CC20 0.1U_0402_10V7-K

1 2

CC21 0.1U_0402_10V7-K

1 2

CC22 0.1U_0402_10V7-K

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P3

PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_P7

PCIE_CTX_C_DRX_P0 PCIE_CTX_C_DRX_N0

PCIE_CTX_C_DRX_P2 PCIE_CTX_C_DRX_N2

UMI_CTX_FRX_P0_C UMI_CTX_FRX_N0_C UMI_CTX_FRX_P1_C UMI_CTX_FRX_N1_C UMI_CTX_FRX_P2_C UMI_CTX_FRX_N2_C UMI_CTX_FRX_P3_C

PCIE_CTX_C_GRX_P[7..0] 5,17

PCIE_CTX_C_GRX_N[7..0] 5,17

PCIE_CTX_C_GRX_P0 5,17

PCIE_CTX_C_GRX_N0 5,17 PCIE_CTX_C_GRX_P1 5,17 PCIE_CTX_C_GRX_N1 5,17 PCIE_CTX_C_GRX_P2 5,17 PCIE_CTX_C_GRX_N2 5,17 PCIE_CTX_C_GRX_P3 5,17 PCIE_CTX_C_GRX_N3 5,17

PCIE_CTX_C_GRX_P4 5,17

PCIE_CTX_C_GRX_N4 5,17 PCIE_CTX_C_GRX_P5 5,17 PCIE_CTX_C_GRX_N5 5,17 PCIE_CTX_C_GRX_P6 5,17 PCIE_CTX_C_GRX_N6 5,17 PCIE_CTX_C_GRX_P7 5,17 PCIE_CTX_C_GRX_N7 5,17

PCIE_CTX_C_DRX_P0 35 PCIE_CTX_C_DRX_N0 35

PCIE_CTX_C_DRX_P2 33 PCIE_CTX_C_DRX_N2 33

UMI_CTX_FRX_P0_C 12 UMI_CTX_FRX_N0_C 12 UMI_CTX_FRX_P1_C 12 UMI_CTX_FRX_N1_C 12 UMI_CTX_FRX_P2_C 12 UMI_CTX_FRX_N2_C 12 UMI_CTX_FRX_P3_C 12 UMI_CTX_FRX_N3_C 12UMI_CRX_FTX_N312

GPU

LAN

WLAN

FCH

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

APU PEG/PCIe/UMI

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

1

5 52

0.4

1

2

3

4

5

UC1B

A A

B B

C C

+1.35V_APU_VDDIO

12

RC5 1K_0402_1%

+VREF_DQA

1

RC6

1K_0402_1%

12

+1.35V_APU_VDDIO +1.35V_APU_VDDIO

0.1U_0402_10V7-K

CC117

2

1000P_0402_50V7K

DDRA_MA[0..15]10

DDRA_BA0#10 DDRA_BA1#10 DDRA_BA2#10

DDRA_MA_DM[0..7]10

DDRA_DQS010 DDRA_DQS#010 DDRA_DQS110 DDRA_DQS#110 DDRA_DQS210 DDRA_DQS#210 DDRA_DQS310 DDRA_DQS#310 DDRA_DQS410 DDRA_DQS#410 DDRA_DQS510 DDRA_DQS#510 DDRA_DQS610 DDRA_DQS#610 DDRA_DQS710 DDRA_DQS#710

DDRA_CLK010 DDRA_CLK0#10 DDRA_CLK110 DDRA_CLK1#10

DDRA_CKE010 DDRA_CKE110

DDRA_ODT010 DDRA_ODT110

DDRA_CS0#10 DDRA_CS1#10

DDRA_RAS#10 DDRA_CAS#10

DDRA_RESET#10 DDRA_EVENT#10

@

1 2

RC21

RC4

CC116

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13 DDRA_MA14 DDRA_MA15

DDRA_BA0# DDRA_BA1# DDRA_BA2#

DDRA_MA_DM0 DDRA_MA_DM1 DDRA_MA_DM2 DDRA_MA_DM3 DDRA_MA_DM4 DDRA_MA_DM5 DDRA_MA_DM6 DDRA_MA_DM7

DDRA_DQS0 DDRA_DQS#0 DDRA_DQS1 DDRA_DQS#1 DDRA_DQS2 DDRA_DQS#2 DDRA_DQS3 DDRA_DQS#3 DDRA_DQS4 DDRA_DQS#4 DDRA_DQS5 DDRA_DQS#5 DDRA_DQS6 DDRA_DQS#6 DDRA_DQS7 DDRA_DQS#7

DDRA_CLK0 DDRA_CLK0# DDRB_CLK0# DDRA_CLK1 DDRA_CLK1#

DDRA_CKE0 DDRA_CKE1

DDRA_ODT0 DDRA_ODT1

DDRA_CS0# DDRA_CS1#

DDRA_RAS# DDRA_CAS# DDRA_WE#

DDRA_RESET# DDRA_EVENT# M_VREF

0_0402_5%

+VREF_DQA_C +VREF_DQB_C

1 2

MA_ZVDDIO

39.2_0402_1%

AB31

MA_ADD0

U33

MA_ADD1

U32

MA_ADD2

R30

MA_ADD3

T34

MA_ADD4

R31

MA_ADD5

R33

MA_ADD6

P33

MA_ADD7

P32

MA_ADD8

P30

MA_ADD9

AD34

MA_ADD10

P34

MA_ADD11

M30

MA_ADD12

AF33

MA_ADD13

M31

MA_ADD14

L32

MA_ADD15

AC33

MA_BANK0

AB30

MA_BANK1

M34

MA_BANK2

E13

MA_DM0

D18

MA_DM1

H22

MA_DM2

H27

MA_DM3

AG30

MA_DM4

AK26

MA_DM5

AK20

MA_DM6

AF14

MA_DM7

F34

MA_DM8

F14

MA_DQS_H0

G14

MA_DQS_L0

H19

MA_DQS_H1

J19

MA_DQS_L1

D24

MA_DQS_H2

E24

MA_DQS_L2

F28

MA_DQS_H3

E28

MA_DQS_L3

AJ30

MA_DQS_H4

AK30

MA_DQS_L4

AH24

MA_DQS_H5

AG24

MA_DQS_L5

AG19

MA_DQS_H6

AF19

MA_DQS_L6

AH14

MA_DQS_H7

AJ14

MA_DQS_L7

G31

MA_DQS_H8

F31

MA_DQS_L8

Y30

MA_CLK_H0

Y29

MA_CLK_L0

Y32

MA_CLK_H1

Y33

MA_CLK_L1

W33

MA_CLK_H2

W34

MA_CLK_L2

W30

MA_CLK_H3

W31

MA_CLK_L3

L33

MA_CKE0

L30

MA_CKE1

K34

MA_CKE2

J30

MA_CKE3

AH34

MA0_ODT0

AH33

MA0_ODT1

AE30

MA1_ODT0

AJ34

MA1_ODT1

AE31

MA0_CS_L0

AG31

MA0_CS_L1

AC30

MA1_CS_L0

AF32

MA1_CS_L1

AC32

MA_RAS_L

AF34

MA_CAS_L

AE33

MA_WE_L

J33

MA_RESET_L

AB33

MA_EVENT_L

V36

M_VREF

H11

MA_VREFDQ

U30

MA_ZVDDIO

M33

RSVD_3

AB34

RSVD_4

KAVERI-2M186092H4467_BGA854

MEMORY CHANNEL A

FP3 REV 0.52

MA_DATA0

MA_DATA1

MA_DATA2

MA_DATA3

MA_DATA4

MA_DATA5

MA_DATA6

MA_DATA7

MA_DATA8

MA_DATA9

MA_DATA10

MA_DATA11

MA_DATA12

MA_DATA13

MA_DATA14

MA_DATA15

MA_DATA16

MA_DATA17

MA_DATA18

MA_DATA19

MA_DATA20

MA_DATA21

MA_DATA22

MA_DATA23

MA_DATA24

MA_DATA25

MA_DATA26

MA_DATA27

MA_DATA28

MA_DATA29

MA_DATA30

MA_DATA31

MA_DATA32

MA_DATA33

MA_DATA34

MA_DATA35

MA_DATA36

MA_DATA37

MA_DATA38

MA_DATA39

MA_DATA40

MA_DATA41

MA_DATA42

MA_DATA43

MA_DATA44

MA_DATA45

MA_DATA46

MA_DATA47

MA_DATA48

MA_DATA49

MA_DATA50

MA_DATA51

MA_DATA52

MA_DATA53

MA_DATA54

MA_DATA55

MA_DATA56

MA_DATA57

MA_DATA58

MA_DATA59

MA_DATA60

MA_DATA61

MA_DATA62

MA_DATA63

MA_CHECK0

MA_CHECK1

MA_CHECK2

MA_CHECK3

MA_CHECK4

MA_CHECK5

MA_CHECK6

MA_CHECK7

RSVD_5

RSVD_6

RSVD_7

RSVD_8

H13 F13 H16 F16 G11 E11 E14 J14

J17 F17 H21 E21 E16 G17 F19 D20

D22 E22 D26 E25 G21 F22 G24 H24

E27 G27 E30 G30 F25 H25 D30 H28

AJ31 AK32 AK28 AF27 AJ33 AK33 AH28 AJ28

AF25 AH25 AG22 AJ22 AH27 AJ27 AE24 AF22

AH21 AJ21 AF17 AJ17 AK22 AF21 AJ19 AE17

AF16 AJ16 AF13 AE13 AH17 AE16 AJ13 AG13

E33 F33 H31 J31 D32 D34 H33 H34

E19 D28 AK24 AG16

DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7

DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15

DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23

DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31

DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39

DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47

DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55

DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63

DDRA_DQ[0..63] 10

+VREF_DQB

DDRB_MA[0..15]11

DDRB_BA0#11 DDRB_BA1#11 DDRB_BA2#11

DDRB_MB_DM[0..7]11

DDRB_DQS011 DDRB_DQS#011 DDRB_DQS111 DDRB_DQS#111 DDRB_DQS211 DDRB_DQS#211 DDRB_DQS311 DDRB_DQS#311 DDRB_DQS411 DDRB_DQS#411 DDRB_DQS511 DDRB_DQS#511 DDRB_DQS611 DDRB_DQS#611 DDRB_DQS711 DDRB_DQS#711

MB_CLK shift 0 to 1.from 1 to 2MB_CLK shift 0 to 1.from 1 to 2

DDRB_CLK011 DDRB_CLK0#11 DDRB_CLK111 DDRB_CLK1#11

DDRB_CKE011 DDRB_CKE111

DDRB_ODT011 DDRB_ODT111

DDRB_CS0#11 DDRB_CS1#11

DDRB_RAS#11 DDRB_CAS#11 DDRB_WE#11DDRA_WE#10

DDRB_RESET#11 DDRB_EVENT#11

@

1 2

RC22

RC3

0_0402_5%

1 2

39.2_0402_1%

DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13 DDRB_MA14 DDRB_MA15

DDRB_BA0# DDRB_BA1# DDRB_BA2#

DDRB_MB_DM0 DDRB_MB_DM1 DDRB_MB_DM2 DDRB_MB_DM3 DDRB_MB_DM4 DDRB_MB_DM5 DDRB_MB_DM6 DDRB_MB_DM7

DDRB_DQS0 DDRB_DQS#0 DDRB_DQS1 DDRB_DQS#1 DDRB_DQS2 DDRB_DQS#2 DDRB_DQS3 DDRB_DQS#3 DDRB_DQS4 DDRB_DQS#4 DDRB_DQS5 DDRB_DQS#5 DDRB_DQS6 DDRB_DQS#6 DDRB_DQS7 DDRB_DQS#7

DDRB_CLK0

DDRB_CLK1 DDRB_CLK1#

DDRB_CKE0 DDRB_CKE1

DDRB_ODT0 DDRB_ODT1

DDRB_CS0# DDRB_CS1#

DDRB_RAS# DDRB_CAS# DDRB_WE#

DDRB_RESET# DDRB_EVENT#

MB_ZVDDIO

UC1C

AC36

MB_ADD0

U36

MB_ADD1

U37

MB_ADD2

T35

MB_ADD3

T37

MB_ADD4

T36

MB_ADD5

R36

MB_ADD6

P37

MB_ADD7

P36

MB_ADD8

N36

MB_ADD9

AD36

MB_ADD10

P35

MB_ADD11

N37

MB_ADD12

AH37

MB_ADD13

M36

MB_ADD14

L36

MB_ADD15

AD35

MB_BANK0

AD37

MB_BANK1

M37

MB_BANK2

A20

MB_DM0

C24

MB_DM1

A30

MB_DM2

B35

MB_DM3

AL35

MB_DM4

AN32

MB_DM5

AN26

MB_DM6

AN21

MB_DM7

E37

MB_DM8

C20

MB_DQS_H0

B20

MB_DQS_L0

B25

MB_DQS_H1

A25

MB_DQS_L1

C30

MB_DQS_H2

B30

MB_DQS_L2

B36

MB_DQS_H3

A36

MB_DQS_L3

AN36

MB_DQS_H4

AM36

MB_DQS_L4

AN31

MB_DQS_H5

AM31

MB_DQS_L5

AM25

MB_DQS_H6

AL26

MB_DQS_L6

AM20

MB_DQS_H7

AL20

MB_DQS_L7

F37

MB_DQS_H8

F36

MB_DQS_L8

MB_CLK_H0

AA37

MB_CLK_L0

AA36

MB_CLK_H1

Y37 Y36

MB_CLK_L1

Y34

MB_CLK_H2

Y35

MB_CLK_L2

V35

MB_CLK_H3

W36

MB_CLK_L3

K36

MB_CKE0

K37

MB_CKE1

K35

MB_CKE2

J37

MB_CKE3

AH36

MB0_ODT0

AJ37

MB0_ODT1

AF35

MB1_ODT0

AK35

MB1_ODT1

AF36

MB0_CS_L0

AJ36

MB0_CS_L1

AE36

MB1_CS_L0

AH35

MB1_CS_L1

AE37

MB_RAS_L

AG36

MB_CAS_L

AF37

MB_WE_L

MB_RESET_L

J36

AB36

MB_EVENT_L

MB_VREFDQ

B17 V37

MB_ZVDDIO

M35

RSVD_9

AB35

RSVD_10

KAVERI-2M186092H4467_BGA854

MEMORY CHANNEL B

FP3 REV 0.52

MB_DATA0

MB_DATA1

MB_DATA2

MB_DATA3

MB_DATA4

MB_DATA5

MB_DATA6

MB_DATA7

MB_DATA8

MB_DATA9

MB_DATA10

MB_DATA11

MB_DATA12

MB_DATA13

MB_DATA14

MB_DATA15

MB_DATA16

MB_DATA17

MB_DATA18

MB_DATA19

MB_DATA20

MB_DATA21

MB_DATA22

MB_DATA23

MB_DATA24

MB_DATA25

MB_DATA26

MB_DATA27

MB_DATA28

MB_DATA29

MB_DATA30

MB_DATA31

MB_DATA32

MB_DATA33

MB_DATA34

MB_DATA35

MB_DATA36

MB_DATA37

MB_DATA38

MB_DATA39

MB_DATA40

MB_DATA41

MB_DATA42

MB_DATA43

MB_DATA44

MB_DATA45

MB_DATA46

MB_DATA47

MB_DATA48

MB_DATA49

MB_DATA50

MB_DATA51

MB_DATA52

MB_DATA53

MB_DATA54

MB_DATA55

MB_DATA56

MB_DATA57

MB_DATA58

MB_DATA59

MB_DATA60

MB_DATA61

MB_DATA62

MB_DATA63

MB_CHECK0

MB_CHECK1

MB_CHECK2

MB_CHECK3

MB_CHECK4

MB_CHECK5

MB_CHECK6

MB_CHECK7

RSVD_11

RSVD_12

RSVD_13

RSVD_14

C18 B19 C22 A22 A18 B18 A21 B21

B24 A24 B27 A28 B22 B23 B26 C26

A29 B29 B32 C32 B28 C28 B31 A32

C34 A34 C36 C37 A33 B33 D35 B37

AL36 AM37 AN34 AM34 AK37 AK36 AN35 AL34

AL32 AM32 AN29 AL28 AM33 AN33 AM30 AM29

AM27 AM26 AN24 AM24 AN28 AM28 AN25 AL24

AN22 AL22 AK18 AL18 AM23 AM22 AN20 AM19

E36 F35 H36 H37 D36 D37 G36 H35

A26 B34 AL30 AM21

DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7

DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15

DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23

DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31

DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39

DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47

DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55

DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63

DDRB_DQ[0..63] 11

add cap on 20131002

D D

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

APU DDRA/B

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

6 52

1.A

1

APU_EDP_TX0+27

EDP

OK

A A

FCH

OK

SPEC HDMI on Port 2

Follow Edge to delete RC7,RC8,RC9 and reserve resisotr on PWR page 52 on 20131009

OK

To Power schematics

B B

HDMI

OK

APU_EDP_TX0-27

APU_EDP_TX1+27 APU_EDP_TX1-27

APU_VGA_TXP013 APU_VGA_TXN013

APU_VGA_TXP113 APU_VGA_TXN113

APU_VGA_TXP213 APU_VGA_TXN213

APU_VGA_TXP313 APU_VGA_TXN313

APU_HDMI_TX2+28 APU_HDMI_TX2-28

APU_HDMI_TX1+28 APU_HDMI_TX1-28

APU_HDMI_TX0+28 APU_HDMI_TX0-28

APU_HDMI_CLK+28 APU_HDMI_CLK-28

EC_SMBLV_CK14 EC_SMBLV_DA14

Check connect t o FCH or EC

To Power schematics

Follow Edge to delete RC27,RC28,RC46 and reserve resisotr on PWR page 52 on 20131009

APU_EDP_TX0+ APU_EDP_TX0-

APU_EDP_TX1+ APU_EDP_TX1-

CC31 0.1U_0402_10V7-K CC32 0.1U_0402_10V7-K

CC33 0.1U_0402_10V7-K CC34 0.1U_0402_10V7-K

CC35 0.1U_0402_10V7-K CC36 0.1U_0402_10V7-K

CC37 0.1U_0402_10V7-K CC38 0.1U_0402_10V7-K

OK

APU_SVC52 APU_SVD52 APU_SVT52

1 2

RC10 0_0402_5%@

1 2

RC11 0_0402_5%@

OK

VSS_SENSE52 VDD_SENSE52

VDDNB_SENSE52

1 2 1 2

APU_RESET#12

APU_PWROK12,52

APU_VGA_TXP0_C APU_VGA_TXN0_C

APU_VGA_TXP1_C APU_VGA_TXN1_C

APU_VGA_TXP2_C APU_VGA_TXN2_C

APU_VGA_TXP3_C APU_VGA_TXN3_C

APU_HDMI_TX2+ APU_HDMI_TX2-

APU_HDMI_TX1+ APU_HDMI_TX1-

APU_HDMI_TX0+ APU_HDMI_TX0-

APU_HDMI_CLK+ APU_HDMI_CLK-

APU_CLKP12 APU_CLKN12

DISP_CLKP12 DISP_CLKN12

APU_CLKP APU_CLKN

DISP_CLKP DISP_CLKN

APU_SVC APU_SVD APU_SVT

SIC SID

APU_RESET# APU_PWROK

APU_PROCHOT# THERMTRIP# ALERT#

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

VSS_SENSE

VDD_SENSE

VDDNB_SENSE

+1.35V_APU_VDDIO

RC67 39.2_0402_1%@

C C

RC68 39.2_0402_1%@

VSS_SENSE

12

100_0402_5%

APU_TEST31

12

RC49

+VDD_CORE

RC47 100_0402_5%

+VDDNB_CORE

RC48 100_0402_5%

1 2

VDD_SENSE

HDT Debug conn

VDDNB_SENSE

+1.35V_APU_VDDIO_RUN

1 2

RC14 300_0402_5%

1 2

RC15 300_0402_5%

APU_RESET# APU_PWROK

+1.35V_APU_VDDIO

1 2

RC17 1K_0402_1%

1 2

RC18 1K_0402_1%

1 2

RC19 1K_0402_1%

1 2

RC37 1K_0402_1%

D D

1 2

RC38 1K_0402_1%

1 2

RC39 1K_0402_1%

1 2

RC40 1K_0402_1%

1 2

RC41 1K_0402_1%

SIC SID ALERT# APU_TDI APU_TCK APU_TMS APU_TRST# APU_DBREQ#

1

RC50

1 2

RC51 10K_0402_5%

1 2

RC52 10K_0402_5%

1 2

RC53 10K_0402_5%

0_0402_5%

2

UC1D

AL6

DP0_TXP0

AM5

DP0_TXN0

AN5

DP0_TXP1

AM4

DP0_TXN1

AN4

DP0_TXP2

AN3

DP0_TXN2

AM3

DP0_TXP3

AN2

DP0_TXN3

F2

DP1_TXP0

F1

DP1_TXN0

F3

DP1_TXP1

E2

DP1_TXN1

E1

DP1_TXP2

D1

DP1_TXN2

D2

DP1_TXP3

C1

DP1_TXN3

A2

DP2_TXP0

A3

DP2_TXN0

B4

DP2_TXP1

A4

DP2_TXN1

C4

DP2_TXP2

B5

DP2_TXN2

A5

DP2_TXP3

A6

DP2_TXN3

AM13

CLKIN_H

AN13

CLKIN_L

AM11

DISP_CLKIN_H

AN11

DISP_CLKIN_L

AJ10

RSVD_16

B16

SVC

C16

SVD

A16

SVT

AL14

SIC

AK14

SID

AM14

RESET_L

AL12

PWROK

AL10

PROCHOT_L

AK11

THERMTRIP_L

AN15

ALERT_L

A14

TDI

C14

TDO

B15

TCK

B14

TMS

D14

TRST_L

A13

DBRDY

B13

DBREQ_L

E10

VSS_SENSE_A

D9

VDD_SENSE

D10

VDDNB_SENSE

F10

VDDIO_SENSE

AE10

VDDP_SENSE

AF11

VDDR_SENSE

AF10

VSS_SENSE_B

KAVERI-2M186092H4467_BGA854

+1.35V_APU_VDDIO

HDT_TRST#APU_TRST#

2

ANALOG/DISPLAY/MISC

DISPLAY PORT 0

DISPLAY PORT

MISC.

DISPLAY PORT 1

DISPLAY PORT 2

TEST

SER. CLK

CTRL

JTAG

SENSE

FP3 REV 0.52

mount RC57 and RC58 if need JHDT1

JHDT1

1

3

5

7

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

ME@

DP_STEREOSYNC

RSVD

AUDIO MISC

2

APU_TCK

2

4

APU_TMS

4

6

APU_TDI

6

8

APU_TDO

8

10

APU_PWROK

12

APU_RESET#

14

APU_DBRDY

16

HDT_DBREQ# APU_DBREQ#

18

APU_TEST19

20

APU_TEST18

DP0_AUXP

DP0_AUXN

DP1_AUXP

DP1_AUXN

DP2_AUXP

DP2_AUXN

DP3_AUXP

DP3_AUXN

DP4_AUXP

DP4_AUXN

DP5_AUXP

DP5_AUXN

DP0_HPD

DP1_HPD

DP2_HPD

DP3_HPD

DP4_HPD

DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST6

TEST9

TEST10

TEST14

TEST15

TEST16

TEST17

TEST18

TEST19

TEST20

TEST24

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

RSVD_15

DMAACTIVE_L

TEST4

TEST5

CORETYPE

RSVD_1

RSVD_2

RSVD_17

RSVD_18

RSVD_19

RSVD_20

RSVD_21

AG8 AG10

B2 B1

B6 B7

H7 G7

Y6 Y5

AD2 AC2

AH7 B3 D7 F8 AB6 AD1

D12 B11 C12

D3

DP_AUX_ZVSS

L27 P27 P28 C10 B9 A10 B10 A12 B12 C8 D8 AM12 AN12 A8 B8 AA27 AA28 V28 Y27 Y28

AK10 AM15

T27 T28

A9

D16

A17 K28

F7 E4 E5 E7 D5

1 2

RC56

0_0402_5%

APU_EDP_AUX APU_EDP_AUX#

APU_VGA_AUX APU_VGA_AUX#

APU_HDMI_CLK APU_HDMI_DATA

APU_EDP_HPD APU_VGA_HPD APU_HDMI_HPD

APU_ENBKL_R APU_ENVDD APU_EDP_PWM_R

APU_TEST6 APU_TEST9 APU_TEST10 APU_TEST14 APU_TEST15 APU_TEST16 APU_TEST17 APU_TEST18 APU_TEST19 APU_TEST20 APU_TEST24 APU_TEST25_H APU_TEST25_L APU_TEST28_H APU_TEST28_L APU_TEST30_H APU_TEST30_L APU_TEST31 APU_TEST32_H APU_TEST32_L

ALLOW_STOP

APU_TEST35

Test_Point

3

4

EC_SMB_3

APU_EDP_AUX 27 APU_EDP_AUX# 27

APU_VGA_AUX 13 APU_VGA_AUX# 13

APU_HDMI_CLK 28 APU_HDMI_DATA 28

APU_EDP_HPD 27

APU_VGA_HPD 13

APU_HDMI_HPD 28

APU_ENVDD 27

1 2

RC12 150_0402_1%

1 2

RC59 1K_0402_1%@

1 2

RC60 1K_0402_1%@

1 2

RC61 1K_0402_1%@

1 2

RC62 1K_0402_1%@

1 2

RC63 1K_0402_1%

1 2

RC64 1K_0402_1%

1 2

RC65 1K_0402_1%

1 2

RC66 1K_0402_1%

1 2

RC35 510_0402_5%

1 2

RC36 510_0402_5%

1 2

@

12

RC13 1K_0402_1%

RC42 300_0402_5%

RC20 300_0402_5%

EDP

FCH

HDMI

+0.95VS_VDDP

+1.35V_APU_VDDIO

ALLOW_STOP 12

+1.35V_APU_VDDIO

Please doucle confirm RC71 and RC72 value

EC_SMB_CK314,18,37,38

EC_SMB_DA314,18,37,38

EC_SMB_CK3

EC_SMB_DA3

APU_ENBKL_R

RC31 100K_0402_5%

RC44

APU_ENBKL_R

RC43 100K_0402_5%

1 2

2.2K_0402_5%

2

B

QC7

MMST3904-7-F_SOT323-3

E

APU_PROCHOT#

VSS_SENSE VDD_SENSE VDDNB_SENSE APU_TEST6 APU_TEST10 APU_TEST15 APU_TEST28_H APU_TEST28_L APU_TEST30_H APU_TEST30_L APU_TEST32_H APU_TEST32_L

1

TPC1 Test_Point_40MIL

1

TPC2 Test_Point_40MIL

1

TPC3 Test_Point_40MIL

1

TPC4 Test_Point_40MIL

1

TPC5 Test_Point_40MIL

1

TPC6 Test_Point_40MIL

1

TPC7 Test_Point_40MIL

1

TPC8 Test_Point_40MIL

1

TPC9 Test_Point_40MIL

1

TPC10 Test_Point_40MIL

1

TPC11 Test_Point_40MIL

1

TPC12 Test_Point_40MIL

+1.35V_APU_VDDIO

H_PROCHOT#38

+1.35V_APU_VDDIO_RUN

+3VALW

RPC1

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

THERMTRIP#

H_THERMTRIP#14,18

To EDP_PWM Conn

OK

RC33 47K_0402_5%

RC32

APU_EDP_PWM_R

RC74

4.7K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2012/07/01

LC Future Center Secret Data

1 2

Deciphered Date

4

2.2K_0402_5%

MMST3904-7-F_SOT323-3

QC5

2014/07/01

+3VS

RC71

1 2

G

2

1 3

D

33K_0402_5%

1 3

S

QC12

BSS138_SOT23-3

12

RC72 30K_0402_1%

G

2

D

S

QC3

BSS138_SOT23-3

SIC

SID

+3VS

RC30

2.2K_0402_5%

1 2

RC29 0_0402_5%

1 2

13

D

2

QC4 2N7002KW_SOT323-3

G

SB00000YY00

S

C

APU_ENBKL

APU_BKOFF#

3 1

+1.35V_APU_VDDIO

12

RC23

B

2

E

3 1

QC1 MMST3904-7-F_SOT323-3

1K_0402_1%

C

RC45

APU_PROCHOT#

1 2

0_0402_5%

H_PROCHOT# pull up +3VS on VR_HOT# on PWR page 52

+1.35V_APU_VDDIO

12

RC26

APU Msic

Monday, December 16, 2013

1K_0402_1%

THERMTRIP#

APU_EDP_PWM 27

2

B

E

31

C

QC2

MMST3904-7-F_SOT323-3

+3VS

RC34

4.7K_0402_5%

1 2

C

2

B

E

3 1

APU_EDP_PWM

13

D

2

QC9

G

2N7002KW_SOT323-3

SB00000YY00

S

Title

Size Document Number Rev

C

Date: Sheet of

5

EC_SMB_CK3

@

EC_SMB_DA3

ACLU7

ACLU7ACLU7

5

1

CH87 22P_0402_50V8-J

2

1

CH88 22P_0402_50V8-J

@

2

APU_ENBKL 38

APU_BKOFF# 27

FCH_PROCHOT# 12

7 52

1.A

1

2

3

4

5

+VDD_CORE

CC48

CC44

A A

CC45

.01U_0402_16V7-K

1

+VDDNB_CORE

+0.95VS_VDDR

2

CC66

CC65

180P_0402_50V7-K

1

2

CC82

CC81

22U_0603_6.3V6-M

1

2

CC86

CC85

22U_0603_6.3V6-M

1

2

CC95

CC94

0.22U_0402_10V6-K

2

1

+VDD_CORE +VDDNB_CORE

B B

C C

UC1E

T11

VDD_1

T14

VDD_2

T17

VDD_3

T21

VDD_4

T24

VDD_5

V10

VDD_6

V13

VDD_7

V16

VDD_8

V19

VDD_9

V22

VDD_10

V24

VDD_11

Y7

VDD_12

Y10

VDD_13

Y13

VDD_14

Y16

VDD_15

Y19

VDD_16

Y22

VDD_17

Y25

VDD_18

AA4

VDD_19

AA11

VDD_20

AA14

VDD_21

AA17

VDD_22

AA21

VDD_23

AA24

VDD_24

AB7

VDD_25

AC4

VDD_26

AC10

VDD_27

AC13

VDD_28

AC16

VDD_29

AC19

VDD_30

AC22

VDD_31

AC25

VDD_32

AD4

VDD_33

AD11

VDD_34

AD14

VDD_35

AD17

VDD_36

AD21

VDD_37

AD24

VDD_38

AE6

VDD_39

AE22

VDD_40

AE25

VDD_41

AF5

VDD_42

AF8

VDD_43

AG11

VDD_44

AH5

VDD_45

AH8

VDD_46

AH10

VDD_47

AK8

VDD_48

FP3 REV 0.52

KAVERI-2M186092H4467_BGA854

POWER

VDDNB_1

VDDNB_2

VDDNB_3

VDDNB_4

VDDNB_5

VDDNB_6

VDDNB_7

VDDNB_8

VDDNB_9

VDDNB_10

VDDNB_11

VDDNB_12

VDDNB_13

VDDNB_14

VDDNB_15

VDDNB_16

VDDNB_17

VDDNB_18

VDDNB_19

VDDNB_20

VDDNB_21

VDDNB_22

VDDNB_23

VDDNB_24

VDDNB_25

VDDNB_26

VDDNB_27

VDDNB_28

VDDNB_29

VDDNB_30

VDDNB_31

VDDNB_32

VDDNB_33

VDDNB_34

VDDNB_35

VDDNB_36

VDDNB_37

VDDNB_38

VDDNB_39

VDDNB_40

VDDNB_41

VDDNB_42

E8 F4 F5 G4 G8 G10 H3 H6 H10 J10 J13 J22 J25 K11 K14 K17 K21 K24 L4 L7 L10 L13 L16 L19 L22 L25 M3 N11 N14 N17 N21 N24 P10 P13 P16 P19 P22 P25 R4 R6 R9 T3

CC79

22U_0603_6.3V6-M

1

2

+1.35V_APU_VDDIO

+0.95VS_VDDP

CC80

1

@

2

UC1F

L29

VDDIO_1

L31

VDDIO_2

L34

VDDIO_3

L37

VDDIO_4

M29

VDDIO_5

M32

VDDIO_6

N27

VDDIO_7

N34

VDDIO_8

P29

VDDIO_9

P31

VDDIO_10

R29

VDDIO_11

R32

VDDIO_12

R34

VDDIO_13

R37

VDDIO_14

U29

VDDIO_15

U31

VDDIO_16

U34

VDDIO_17

V27

VDDIO_18

V34

VDDIO_19

W29

VDDIO_20

W32

VDDIO_21

W37

VDDIO_22

Y31

VDDIO_23

AA34

VDDIO_24

AB29

VDDIO_25

AB32

VDDIO_26

AB37

VDDIO_27

AC29

VDDIO_28

AC31

VDDIO_29

AC34

VDDIO_30

AC37

VDDIO_31

AE32

VDDIO_32

AE34

VDDIO_33

AF30

VDDIO_34

AF31

VDDIO_35

AG34

VDDIO_36

AG37

VDDIO_37

AK16

VDDP_1

AL16

VDDP_2

AM16

VDDP_3

AN16

VDDP_4

AC11

VDDP_CAP

22U_0603_6.3V6-M

KAVERI-2M186092H4467_BGA854

POWER

FP3 REV 0.52

VDDR_1

VDDR_2

VDDR_3

VDDR_CAP

VDDA_1

VDDA_2

RSVD_22

AK17 AM17 AN17

AC27

AH11 AJ11

D6

+0.95VS_VDDR

+VDDR_CAP

+1.35V_APU_VDDIO

+1.8VS_VDDA

CC47

CC46

.01U_0402_16V7-K

180P_0402_50V7-K

1

2

CC67

CC68

180P_0402_50V7-K

1

2

1

2

1

2

1

180P_0402_50V7-K

1

2

CC84

CC83

22U_0603_6.3V6-M

1

2

CC88

CC87

4.7U_0603_6.3V6-K

22U_0603_6.3V6-M

1

2

CC97

CC96

0.22U_0402_10V6-K

2

1

+0.95VS_VDDP

CC69

22U_0603_6.3V6-M

1

2

CC71

CC70

22U_0603_6.3V6-M

1

2

CC72

22U_0603_6.3V6-M

0.22U_0402_10V6-K

1

2

CC49

CC42

CC43

0.22U_0402_10V6-K

180P_0402_50V7-K

1

2

1

2

1

2

1

2

1

2

1

2

CC63

CC62

0.22U_0402_10V6-K

2

1

CC23

CC24

0.22U_0402_10V6-K

2

1

CC90

CC89

4.7U_0603_6.3V6-K

1

2

CC99

CC98

0.22U_0402_10V6-K

2

1

CC74

CC73

0.22U_0402_10V6-K

1

2

1

180P_0402_50V7-K

0.22U_0402_10V6-K

2

1

CC64

0.22U_0402_10V6-K

2

1

22u 6.3V *11 @*2 Design Guide

0.22u 10V *2

0.01u 10V *3

CC26

CC25

180P_0402_50V7-K

1

2

4.7U_0603_6.3V6-K

0.22U_0402_10V6-K

CC92

CC101

CC93

4.7U_0603_6.3V6-K

1

2

CC102

0.22U_0402_10V6-K

2

1

4.7U_0603_6.3V6-K

0.22U_0402_10V6-K

CC91

1

2

CC100

2

1

+1.8VS_VDDA

CC75

1

2

CC76

4.7U_0603_6.3V6-K

1

2

180p *3

22u 6.3V *10 @*2 Design Guide

0.22u 10V *3 180p 10V *4

22u 6.3V *3

0.22u 10V *2 180p 10V *2

22u 6.3V *4

0.22u 10V *2 180p 10V *2

4.7u 6.3V *1

0.22u 10V *1

3.3n 10V *1

CC105

CC104

CC103

180P_0402_50V7-K

0.22U_0402_10V6-K

2

1

CC77

0.22U_0402_10V6-K

2

1

180P_0402_50V7-K

1

2

+VDDR_CAP

CC78

CC27

CC28

3.3n_0402_50V6-K

2

1

@

22U_0603_6.3V6-M

1

2

180P_0402_50V7-K

3.3n need apply PN

D D

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

APU Power

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

8 52

1.A

1

2

3

4

5

A A

B B

UC1G

VSS

A1

VSS_1

A7

VSS_2

A11

VSS_3

A15

VSS_4

A19

VSS_5

A23

VSS_6

A27

VSS_7

A31

VSS_8

A35

VSS_9

A37

VSS_10

C2

VSS_11

C3

VSS_12

C6

VSS_13

C35

VSS_14

D4

VSS_15

D11

VSS_16

D13

VSS_17

D15

VSS_18

D17

VSS_19

D19

VSS_20

D21

VSS_21

D23

VSS_22

D25

VSS_23

D27

VSS_24

D29

VSS_25

D31

VSS_26

D33

VSS_27

E17

VSS_28

E31

VSS_29

E34

VSS_30

F11

VSS_31

F21

VSS_32

F24

VSS_33

F27

VSS_34

F30

VSS_35

G1

VSS_36

G13

VSS_37

G16

VSS_38

G19

VSS_39

G22

VSS_40

G25

VSS_41

G28

VSS_42

G34

VSS_43

G37

VSS_44

H8

VSS_45

H14

VSS_46

H17

VSS_47

H30

VSS_48

H32

VSS_49

J4

VSS_50

J6

VSS_51

J11

VSS_52

J16

VSS_53

J21

VSS_54

J24

VSS_55

J27

VSS_56

J28

VSS_57

J32

VSS_58

J34

VSS_59

K10

VSS_60

FP3 REV 0.52

VSS_61

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_74

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

K13 K16 K19 K22 K25 L1 L11 L14 L17 L21 L24 L28 M6 M9 N4 N10 N13 N16 N19 N22 N25 N28 P6 P9 P11 P14 P17 P21 P24 R1 T10 T13 T16 T19 T22 T25 U4 U6 U9 V11 V14 V17 V21 V25 W1 W4 W6 W9 Y3 Y11 Y14 Y17 Y21 Y24 AA10 AA13 AA16 AA19 AA22 AA25

KAVERI-2M186092H4467_BGA854

UC1H

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSS_130

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

VSS_143

VSS_144

VSS_145

VSS_146

VSS_147

VSS_148

VSS_149

VSS_150

VSS_151

VSS_152

VSS_153

VSS_154

VSS_155

VSS_156

VSS_157

VSS_158

VSS_159

VSS_160

VSS_161

VSS_162

VSS_163

VSS_164

VSS_165

VSS_166

VSS_167

VSS_168

VSS_169

VSS_170

VSS_171

VSS_172

VSS_173

VSS_174

VSS_175

VSS_176

VSS_177

VSS_178

VSS_179

VSS_180

VSS

FP3 REV 0.52

AC14 AC17 AC21 AC24 AC28

AD10 AD13 AD16 AD19 AD22 AD25 AD28

AE14 AE19 AE21 AE27 AE28

AF24 AF28

AG14 AG17 AG21 AG25 AG27 AG28 AH13 AH16 AH19 AH22 AH30 AH31

AJ24 AJ25

AK12 AK13 AK15 AK19 AK21 AK23 AK25 AK27 AK29 AK31 AK34

AL37

AM35

AC1 AC7

AD3

AE1 AE4

AF7

AG1 AG4

AJ4

AK9

AL3 AL8

AN1 AN7

KAVERI-2M186092H4467_BGA854

VSS_181

VSS_182

VSS_183

VSS_184

VSS_185

VSS_186

VSS_187

VSS_188

VSS_189

VSS_190

AN10 AN14 AN19 AN23 AN27 AN30 AN37 AD27 K27 AE11

C C

D D

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

APU GND

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

9 52

1.A

5

4

3

2

1

DDR3 SO-DIMM A

VSS_2

VSS_4 DQS0#

DQS0

VSS_6

VSS_8

DQ12 DQ13

VSS_10

RESET# VSS_12

DQ14 DQ15

VSS_14

DQ20 DQ21

VSS_16

VSS_18

DQ22 DQ23

VSS_20

DQ28 DQ29

VSS_22

DQS3#

DQS3

VSS_24

DQ30 DQ31

VSS_26

CKE1

VDD_2

VDD_4

VDD_6

VDD_8

VDD_10

CK1#

VDD_12

RAS#

VDD_14

ODT0

VDD_16

ODT1

NC_2

VDD_18

VREF_CA

VSS_28

DQ36 DQ37

VSS_30

VSS_32

DQ38 DQ39

VSS_34

DQ44 DQ45

VSS_35

DQS5#

DQS5

VSS_38

DQ46 DQ47

VSS_40

DQ52 DQ53

VSS_42

VSS_44

DQ54 DQ55

VSS_46

DQ60 DQ61

VSS_48

DQS7#

DQS7

VSS_50

DQ62

DQ63 VSS_52 EVENT#

VTT_2

GND2

BOSS2

+1.35V_DDR_VDDIOSUS+1.35V_DDR_VDDIOSUS

2 4

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A11

A7

A6 A4

A2 A0

CK1

BA1

S0#

DM4

DM6

SDA

SCL

DDRA_DQ4

6

DDRA_DQ5

8 10

DDRA_DQS#0

12

DDRA_DQS0

14 16

DDRA_DQ6

18

DDRA_DQ7

20 22

DDRA_DQ12

24

DDRA_DQ13

26 28

DDRA_MA_DM1

30

DDRA_RESET#

32 34

DDRA_DQ14

36

DDRA_DQ15

38 40

DDRA_DQ20

42

DDRA_DQ21

44 46

DDRA_MA_DM2

48 50

DDRA_DQ22

52

DDRA_DQ23DDRA_DQ18

54 56

DDRA_DQ28

58

DDRA_DQ29

60 62

DDRA_DQS#3

64

DDRA_DQS3

66 68

DDRA_DQ30

70

DDRA_DQ31

72

74

DDRA_CKE1

76 78

DDRA_MA15

80

DDRA_MA14

82 84

DDRA_MA11

86

DDRA_MA7

88 90

DDRA_MA6

92

DDRA_MA4

94 96

DDRA_MA2

98

DDRA_MA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_BA1#

110

DDRA_RAS#

112 114

DDRA_CS0#

116

DDRA_ODT0

118 120

DDRA_ODT1

122 124 126 128 130

DDRA_DQ36

132

DDRA_DQ37

134 136

DDRA_MA_DM4

138 140

DDRA_DQ38

142

DDRA_DQ39

144 146

DDRA_DQ44

148

DDRA_DQ45

150 152

DDRA_DQS#5

154

DDRA_DQS5

156 158

DDRA_DQ46

160

DDRA_DQ47

162 164

DDRA_DQ52

166

DDRA_DQ53

168 170

DDRA_MA_DM6

172 174

DDRA_DQ54

176

DDRA_DQ55

178 180

DDRA_DQ60

182

DDRA_DQ61

184 186

DDRA_DQS#7

188

DDRA_DQS7

190 192

DDRA_DQ62

194

DDRA_DQ63

196 198

DDRA_EVENT#

200

SMB0_DATA

202

SMB0_CLK

204

206 208

[email protected]

[email protected][email protected]

DDRA_MA_DM1 6

DDRA_RESET# 6

DDRA_MA_DM2 6

DDRA_CKE1 6

DDRA_CLK1 6 DDRA_CLK1# 6

DDRA_BA1# 6 DDRA_RAS# 6

DDRA_CS0# 6 DDRA_ODT0 6

DDRA_ODT1 6

DDRA_MA_DM4 6

DDRA_MA_DM6 6

DDRA_EVENT# 6 SMB0_DATA 11,14,33 SMB0_CLK 11,14,33

+0.675VS

+VREF_DQA_D

RD17

@

0_0402_5%

1 2 1 2

1 2

0_0402_5%

CD1

@

Close to JDDR3H.1

DDRA_SA0 DDRA_SA1

1

CD2

2

0.1U_0402_10V7-K

2.2U_0603_6.3V6-K

DDRA_MA_DM06

1

2

1000P_0402_50V7-K

DDRA_MA_DM36

DDRA_CKE06

DDRA_BA2#6

DDRA_CLK06 DDRA_CLK0#6

DDRA_BA0#6

DDRA_WE#6 DDRA_CAS#6

DDRA_CS1#6

DDRA_MA_DM56

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

DDRA_MA_DM76

+3VS

CD3

1

2

1

CD4

0.1U_0402_10V6-K

2

DDRA_DQ0 DDRA_DQ1

DDRA_MA_DM0

DDRA_DQ2 DDRA_DQ3

DDRA_DQ8 DDRA_DQ9

DDRA_DQS#1 DDRA_DQS1

DDRA_DQ10 DDRA_DQ11

DDRA_DQ16 DDRA_DQ17

DDRA_DQS#2 DDRA_DQS2

DDRA_DQ19

DDRA_DQ24 DDRA_DQ25

DDRA_MA_DM3

DDRA_DQ26 DDRA_DQ27

DDRA_CKE0

DDRA_BA2#

DDRA_MA12 DDRA_MA9

DDRA_MA8 DDRA_MA5

DDRA_MA3 DDRA_MA1

DDRA_CLK0 DDRA_CLK0#

DDRA_MA10 DDRA_BA0#

DDRA_WE# DDRA_CAS#

DDRA_MA13 DDRA_CS1#

DDRA_DQ32 DDRA_DQ33

DDRA_DQS#4 DDRA_DQS4

DDRA_DQ34 DDRA_DQ35

DDRA_DQ40 DDRA_DQ41

DDRA_MA_DM5

DDRA_DQ42 DDRA_DQ43

DDRA_DQ48 DDRA_DQ49

DDRA_DQS#6 DDRA_DQS6

DDRA_DQ50 DDRA_DQ51

DDRA_DQ56 DDRA_DQ57

DDRA_MA_DM7

DDRA_DQ58 DDRA_DQ59

DDRA_SA0

DDRA_SA1

D D

C C

B B

A A

+VREF_DQA

RD167 RD168 0_0402_5%

[email protected]

JDDR1

1

VREF_DQ

3

VSS_1

5

DQ0

7

DQ1

9

VSS_3

11

DM0

13

VSS_5

15

DQ2

17

DQ3

19

VSS_7

21

DQ8

23

DQ9

25

VSS_9

27

DQS1#

29

DQS1

31

VSS_11

33

DQ10

35

DQ11

37

VSS_13

39

DQ16

41

DQ17

43

VSS_15

45

DQS2#

47

DQS2

49

VSS_17

51

DQ18

53

DQ19

55

VSS_19

57

DQ24

59

DQ25

61

VSS_21

63

DM3

65

VSS_23

67

DQ26

69

DQ27

71

VSS_25

73

CKE0

75

VDD_1

77

NC_1

79

BA2

81

VDD_3

83

A12/BC#

85

A9

87

VDD_5

89

A8

91

A5

93

VDD_7

95

A3

97

A1

99

VDD_9

101

CK0

103

CK0#

105

VDD_11

107

A10/AP

109

BA0

111

VDD_13

113

WE#

115

CAS#

117

VDD_15

119

A13

121

S1#

123

VDD_17

125

TEST

127

VSS_27

129

DQ32

131

DQ33

133

VSS_29

135

DQS4#

137

DQS4

139

VSS_31

141

DQ34

143

DQ35

145

VSS_33

147

DQ40

149

DQ41

151

VSS_36

153

DM5

155

VSS_37

157

DQ42

159

DQ43

161

VSS_39

163

DQ48

165

DQ49

167

VSS_41

169

DQS6#

171

DQS6

173

VSS_43

175

DQ50

177

DQ51

179

VSS_45

181

DQ56

183

DQ57

185

VSS_47

187

DM7

189

VSS_49

191

DQ58

193

DQ59

195

VSS_51

197

SA0

199

VDDSPD

201

SA1

203

VTT_1

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

DDRA_DQ[0..63] 6

DDRA_DQS[0..7] 6

DDRA_DQS#[0..7] 6

DDRA_MA[0..15] 6

All VREF traces should have 20 mil trace width

1

CD5

CD6

2

0.1U_0402_10V7-K

2.2U_0402_6.3V6-M

close to JDDR3L.126

+V_SM_VREF_CNT

DDR Decoupling

+1.35V_DDR_VDDIOSUS

CD59

+0.675VS

1

@

2

CD7

1

2

0.1U_0402_10V7-K

CD11

@

0.1U_0402_10V7-K

1

2

CD49

1

2

0.1U_0402_10V7-K

CD20

4.7U_0603_6.3V6K 1U_0402_6.3V6-K

1

2

10U_0603_6.3V6-M

CD21

CD8

0.1U_0402_10V7-K

CD12

@

CD50

0.1U_0402_10V7-K

1

2

CD9

CD10

1

2

0.1U_0402_10V7-K

@

CD47

CD13

@

10U_0603_6.3V6-M

0.1U_0402_10V7-K

1

2

CD51

1

2

0.1U_0402_10V7-K

CD22

1U_0402_6.3V6-K

1

2

Layout Note :

1

1. Placed near JDDR3L

2. Place these 4 Caps near Command

2

and Control signals of DIMMA

0.1U_0402_10V7-K

@

CD15

CD14

10U_0603_6.3V6-M

1

2

0.1U_0402_10V7-K

CD52

1

2

0.1U_0402_10V7-K

CD23

Layout Note : Placed near JDDR3L1.Pin203, 204

1

2

0.1U_0402_10V7-K

+1.35V_DDR_VDDIOSUS

1uF *4, 10uF *7, 330uF *1

CD16

CD17

1

2

0.1U_0402_10V7-K

+VREF_DQA_D

12

RD11 1K_0402_1%

12

RD12 1K_0402_1%

CD18

10U_0603_6.3V6-M

1

2

0.1U_0402_10V7-K

DDRA_EVENT#

CD42

CD19

330U_D2_2VM_R9M

1

+

@

2

+1.35V_DDR_VDDIOSUS

12

RD6 1K_0402_1%

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

DDR3 SO-DIMMA/1

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet

Date: Sheet of

ACLU7

ACLU7ACLU7

1

of

10 52

0.4

5

4

3

2

1

DDR3 SO-DIMM B

+VREF_DQB_D

RD18

@

1 2

+VREF_DQB

D D

0_0402_5%

CD24

DDRB_MB_DM06

1

CD25

@

2

0.1U_0402_10V7-K 1000P_0402_50V7-K

Close to JDDR3L.1

DDRB_MB_DM36

C C

B B

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

+3VS

2.2U_0603_6.3V6-K

A A

CD26

1

2

+3VS

1

CD27

0.1U_0402_10V6-K

2

DDRB_CKE06

DDRB_BA2#6

DDRB_CLK06 DDRB_CLK0#6

DDRB_BA0#6

DDRB_WE#6 DDRB_CAS#6

DDRB_CS1#6

DDRB_MB_DM56

DDRB_MB_DM76

1 2

R167 10K_0402_5%

RD170

DDRB_DQ0 DDRB_DQ1

DDRB_MB_DM0

DDRB_DQ2 DDRB_DQ3

DDRB_DQ8 DDRB_DQ9

DDRB_DQS#1 DDRB_DQS1

DDRB_DQ10 DDRB_DQ11

DDRB_DQ16 DDRB_DQ17

DDRB_DQS#2 DDRB_DQS2

DDRB_DQ18 DDRB_DQ19

DDRB_DQ24 DDRB_DQ25

DDRB_MB_DM3

DDRB_DQ26 DDRB_DQ27

DDRB_CKE0

DDRB_BA2#

DDRB_MA12 DDRB_MA9

DDRB_MA8 DDRB_MA5

DDRB_MA3 DDRB_MA1

DDRB_CLK0 DDRB_CLK0#

DDRB_MA10 DDRB_BA0#

DDRB_WE# DDRB_CAS#

DDRB_MA13 DDRB_CS1#

DDRB_DQ32 DDRB_DQ33

DDRB_DQS#4 DDRB_DQS4

DDRB_DQ34 DDRB_DQ35

DDRB_DQ40 DDRB_DQ41

DDRB_MB_DM5

DDRB_DQ42 DDRB_DQ43

DDRB_DQ48 DDRB_DQ49

DDRB_DQS#6 DDRB_DQS6

DDRB_DQ50 DDRB_DQ51

DDRB_DQ56 DDRB_DQ57

DDRB_MB_DM7

DDRB_DQ58 DDRB_DQ59

1 2

0_0402_5%

+1.35V_DDR_VDDIOSUS

DDRB_SA0

DDRB_SA1

[email protected]

JDDR2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

+1.35V_DDR_VDDIOSUS

DQ4 DQ5

VSS3

DQS#0

DQS0 VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

A15 A14

VDD4

A11

A7

VDD6

A6 A4

VDD8

A2 A0

CK1 CK1#

VDD12

BA1 RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

G2

2 4

DDRB_DQ4

6

DDRB_DQ5

8 10

DDRB_DQS#0

12

DDRB_DQS0

14 16

DDRB_DQ6

18

DDRB_DQ7

20 22

DDRB_DQ12

24

DDRB_DQ13

26 28

DDRB_MB_DM1

30

DDRB_RESET#

32 34

DDRB_DQ14

36

DDRB_DQ15

38 40

DDRB_DQ20

42

DDRB_DQ21

44 46

DDRB_MB_DM2

48 50

DDRB_DQ22

52

DDRB_DQ23

54 56

DDRB_DQ28

58

DDRB_DQ29

60 62

DDRB_DQS#3

64

DDRB_DQS3

66 68

DDRB_DQ30

70

DDRB_DQ31

72

74

DDRB_CKE1

76 78

DDRB_MA15

80

DDRB_MA14

82 84

DDRB_MA11

86

DDRB_MA7

88 90

DDRB_MA6

92

DDRB_MA4

94 96

DDRB_MA2

98

DDRB_MA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDRB_BA1#

110

DDRB_RAS#

112 114

DDRB_CS0#

116

DDRB_ODT0

118 120

DDRB_ODT1

122 124 126 128 130

DDRB_DQ36

132

DDRB_DQ37

134 136

DDRB_MB_DM4

138 140

DDRB_DQ38

142

DDRB_DQ39

144 146

DDRB_DQ44

148

DDRB_DQ45

150 152

DDRB_DQS#5

154

DDRB_DQS5

156 158

DDRB_DQ46

160

DDRB_DQ47

162 164

DDRB_DQ52

166

DDRB_DQ53

168 170

DDRB_MB_DM6

172 174

DDRB_DQ54

176

DDRB_DQ55

178 180

DDRB_DQ60

182

DDRB_DQ61

184 186

DDRB_DQS#7

188

DDRB_DQS7

190 192

DDRB_DQ62

194

DDRB_DQ63

196 198

DDRB_EVENT#

200

SMB0_DATA

202

SMB0_CLK

204

206

[email protected]

[email protected][email protected]

DDRB_MB_DM1 6

DDRB_RESET# 6

DDRB_MB_DM2 6

DDRB_CKE1 6

DDRB_CLK1 6 DDRB_CLK1# 6

DDRB_BA1# 6 DDRB_RAS# 6

DDRB_CS0# 6 DDRB_ODT0 6

DDRB_ODT1 6

DDRB_MB_DM4 6

DDRB_MB_DM6 6

DDRB_EVENT# 6

SMB0_DATA 10,14,33 SMB0_CLK 10,14,33

+0.675VS

DDRB_DQ[0..63] 6

DDRB_DQS[0..7] 6

DDRB_DQS#[0..7] 6

DDRB_MA[0..15] 6

1

CD28

1

CD29

2

0.1U_0402_10V7-K 1000P_0402_50V7-K

Close to JDDR3H.126

+V_SM_VREF_CNT

DDR Decoupling

+1.35V_DDR_VDDIOSUS

0.1U_0402_10V7-K

+0.675VS

4.7U_0603_6.3V6K

1

CD58

@

2

DDRB_EVENT#

CD31

CD30

1

2

0.1U_0402_10V7-K

CD35

CD34

@

10U_0603_6.3V6-M

1

2

CD61

CD62

1

2

0.1U_0402_10V7-K

CD43

CD44

1U_0402_6.3V6-K

1

2

+1.35V_DDR_VDDIOSUS

12

1

2

10U_0603_6.3V6-M

1

2

1

2

CD45

1U_0402_6.3V6-K

1

2

RD8 1K_0402_1%

CD32

0.1U_0402_10V7-K

CD36

CD64

0.1U_0402_10V7-K

1U_0402_6.3V6-K

1

2

CD54

@

10U_0603_6.3V6-M

1

2

1

2

CD33

Layout Note :

1

1. Placed near JDDR3H

2. Place these 4 Caps near Command

2

and Control signals of DIMMA

0.1U_0402_10V7-K

@

CD55

CD37

@

10U_0603_6.3V6-M

1

2

CD63

1

2

0.1U_0402_10V7-K

CD46

1

2

+1.35V_DDR_VDDIOSUS

1

2

Layout Note : Placed near

1U_0402_6.3V6-K

JDDR3H.Pin203, 204

12

RD5 1K_0402_1%

12

RD7 1K_0402_1%

1uF *4, 10uF *7, 330uF *1

CD39

CD38

10U_0603_6.3V6-M

0.1U_0402_10V7-K

+V_SM_VREF_CNT

1

2

1

2

0.1U_0402_10V7-K

+1.35V_DDR_VDDIOSUS

0.1U_0402_10V7-K

CD40

1

2

12

RD9 1K_0402_1%

12

RD10 1K_0402_1%

CD41

1

2

0.1U_0402_10V7-K

+VREF_DQB_D

CRB: DDRB_SA1 pull low / DDRB_SA0 pull high Edge: DDRB_SA1 pull high / DDRB_SA0 pull low

5

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

DDR3 SO-DIMMB/2

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet

Date: Sheet of

ACLU7

ACLU7ACLU7

1

of

11 52

0.4

1

2

3

4

5

CH82

1 2

150P_0402_50V8-J

CH15

@

1 2

A A

UMI_CRX_FTX_P05 UMI_CRX_FTX_N05 UMI_CRX_FTX_P15 UMI_CRX_FTX_N15 UMI_CRX_FTX_P25 UMI_CRX_FTX_N25 UMI_CRX_FTX_P35 UMI_CRX_FTX_N35

B B

OK

APU

OK

APU

GPU

LAN

C C

WLAN

PLT_RST#17,33,35 EC_A_RST#38

+VDDAN_11_PCIE

+VDDAN_11_CLK

DISP_CLKP7 DISP_CLKN7

APU_CLKP7 APU_CLKN7

GFX_CLKP17 GFX_CLKN17

PCIE_LAN_CLK_P035 PCIE_LAN_CLK_N035

PCIE_WLAN_CLK_P233 PCIE_WLAN_CLK_N233

150P_0402_50V8-J

EC_A_RST#

UMI_CRX_FTX_P0 UMI_CRX_FTX_N0 UMI_CRX_FTX_P1 UMI_CRX_FTX_N1 UMI_CRX_FTX_P2 UMI_CRX_FTX_N2 UMI_CRX_FTX_P3 UMI_CRX_FTX_N3

UMI_CTX_FRX_P0_C5 UMI_CTX_FRX_N0_C5 UMI_CTX_FRX_P1_C5 UMI_CTX_FRX_N1_C5 UMI_CTX_FRX_P2_C5 UMI_CTX_FRX_N2_C5 UMI_CTX_FRX_P3_C5 UMI_CTX_FRX_N3_C5

CH1 0.1U_0402_10V7-K CH2 0.1U_0402_10V7-K CH3 0.1U_0402_10V7-K CH4 0.1U_0402_10V7-K CH5 0.1U_0402_10V7-K CH6 0.1U_0402_10V7-K CH7 0.1U_0402_10V7-K CH8 0.1U_0402_10V7-K

RH4 590_0402_1% RH3 2K_0402_1%

RH5 2K_0402_1%

RH6 0_0402_5% RH7 0_0402_5%

RH8 0_0402_5% RH9 0_0402_5%

RH10 0_0402_5% RH11 0_0402_5%

RH12 0_0402_5% RH13 0_0402_5%

RH16 0_0402_5% RH17 0_0402_5%

RH1

1 2

RH2

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2

1 2

1 2 1 2

@

33_0402_5% 33_0402_5%

PCIE_CALRP PCIE_CALRN

DISP_CLKP_R DISP_CLKN_R

APU_CLKP_R APU_CLKN_R

GFX_CLKP_R GFX_CLKN_R

PCIE_LAN_CLK_P0_R PCIE_LAN_CLK_N0_R

PCIE_WLAN_CLK_P2_R PCIE_WLAN_CLK_N2_R

PCH Crystal

FCH_XTAL25_IN

FCH_XTAL25_OUT

10P_0402_50V8J

1

CH16

2

1 2

RH18 1M_0402_5%

YH1

1

OSC1

GND12OSC2

GND2

4

3

25MHZ_10PF_7V25000014

1

CH17 10P_0402_50V8J

2

Change to 7V25000014 (TXC),. Cap 10pF*2 on 2013/12/5

D D

1 2

RH91

PLT_RST_R#PLT_RST# A_RST#

UMI_CRX_FTX_P0_C UMI_CRX_FTX_N0_C UMI_CRX_FTX_P1_C UMI_CRX_FTX_N1_C UMI_CRX_FTX_P2_C UMI_CRX_FTX_N2_C UMI_CRX_FTX_P3_C UMI_CRX_FTX_N3_C

UMI_CTX_FRX_P0_C UMI_CTX_FRX_N0_C UMI_CTX_FRX_P1_C UMI_CTX_FRX_N1_C UMI_CTX_FRX_P2_C UMI_CTX_FRX_N2_C UMI_CTX_FRX_P3_C UMI_CTX_FRX_N3_C

CLK_CALRN

FCH_XTAL25_IN

FCH_XTAL25_OUT

EC_A_RST#P LT_RST#

0_0402_5%

UH2A

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

218084401A1BOLTONM3_FCBGA656

BOLTON-M3

+3VALW

CLK_PCI_EC

Part 1 of 5

PCICLK4/14M_OSC/GPO39

PCI CLKS

PCI EXPRESS INTERFACES

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41

REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

LPC

LDRQ1#/CLK_REQ6#/GPIO49

APU

S5 PLUS

PCICLK0

PCICLK1/GPO36

PCICLK2/GPO37

PCICLK3/GPO38

PCIRST#

AD0/GPIO0

AD1/GPIO1

AD2/GPIO2

AD3/GPIO3

AD4/GPIO4

AD5/GPIO5

AD6/GPIO6

AD7/GPIO7

AD8/GPIO8

AD9/GPIO9

AD10/GPIO10

AD11/GPIO11

AD12/GPIO12

AD13/GPIO13

AD14/GPIO14

AD15/GPIO15

AD16/GPIO16

AD17/GPIO17

AD18/GPIO18

AD19/GPIO19

AD20/GPIO20

AD21/GPIO21

AD22/GPIO22

AD23/GPIO23

AD24/GPIO24

AD25/GPIO25

AD26/GPIO26

AD27/GPIO27

AD28/GPIO28

AD29/GPIO29

AD30/GPIO30

AD31/GPIO31

CBE0#

CBE1#

CBE2#

CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

STOP#

PERR#

SERR#

REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

CLKRUN#

LOCK#

INTE#/GPIO32

INTF#/GPIO33

INTG#/GPIO34

INTH#/GPIO35

LPCCLK0

LPCCLK1

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

32K_X1

32K_X2

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

AF3

PCICLK0

AF1

PCICLK1

AF5 AG2

PCICLK3

AF6

PCICLK4

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10

PAR

AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

TPV38 Test_Point_20MIL

Spare one PCH pin to add FCH_WLAN_OFF#

Change DGPU_PWROK_R from UH2.AG26 to UH2.AH14

1

TPH2

HOLD_RST#_R DGPU_PWREN_R

1

TPH1

ODD_DA_INTH#

Add ODD_DA_INTH# Core Power Well on 20130930

B25

LPC_CLK0

D25

LPC_CLK1

D27

LPC_AD0

LAD0

C28

LPC_AD1

LAD1

A26

LPC_AD2

LAD2

A29

LPC_AD3

LAD3

A31

LPC_FRAME#

B27 AE27 AE19

SERIRQ

G25

ALLOW_STOP

E28

FCH_PROCHOT#

E26

APU_PWROK

G26 F26

APU_RESET#

G2

FCH_XTAL32X1

G4

FCH_XTAL32X2

H7

FCH_S5

F1

RTC_CLK

F3 E6

+RTCBATT_R

1U_0402_10V6-K

1

FCH_WLAN_OFF#

PCH_BT_DISABLE#

PCI_AD23 16 PCI_AD24 16 PCI_AD25 16 PCI_AD26 16 PCI_AD27 16

Test_Point_12MIL

internal PU 8.2K

33_0402_5%

1 2

W=20mils

1

1K_0402_1%

CH18

2

PCICLK0 33

PCICLK1 16

PCICLK3 16 PCICLK4 16

1 2

RH85

12 12

ODD_DA_INTH# 32

RH86

12

LPC_CLK1 16

LPC_AD0 38 LPC_AD1 38 LPC_AD2 38 LPC_AD3 38

LPC_FRAME# 38

SERIRQ 38

ALLOW_STOP 7 FCH_PROCHOT# 7

APU_PWROK 7,52

APU_RESET# 7

FCH_S5 38

RTC_CLK 16

RH21

FCH_WLAN_OFF# 33

PCH_BT_DISABLE# 33

DGPU_PWROKDGPU_PWROK_R

0_0402_5%

RH880_0402_5% DIS@ RH900_0402_5% DIS@

DGPU_HOLD_RST# 17

DGPU_PWREN 17,24,51

CLK_PCI_EC 16,38

VCCRTC

Follow Edge to ch ange UE1.Pin35 from VSB_ON to FCH_S5 on 0927

JCMOS1 SHORT PADS

@

1 2

PCH_BT_DISABLE#

FCH_WLAN_OFF#

DGPU_PWROK 38,51

LPC_CLK0

1

CH22 22P_0402_50V8-J

@

2

HOLD_RST#_R

RH148 10K_0402_5%

Follow Edge to put pull down 10k for HOLD_RST#_R

DGPU_PWREN_R

DGPU_PWROK_R

Follow Edge to put pull down 100k for DGPU_PWROK_R

Follow Edge to put pull down 100k for DGPU_PWREN_R

Check DGPU_PWREN_R and DGPU_PWROK_R pull up or down with AMD and PWR

RTC Crystal

1

CH19

22P_0402_50V8-J

2

1 2

RH99 10K_0402_5%@

1 2

RH23 10K_0402_5%

1 2

RH25 10K_0402_5%

1 2

RH146 100K_0402_5%

@

1 2

RH147 100K_0402_5%

RH31

1 2

20M_0402_5%

1 2

YH2

32.768KHZ_12.5PF_200458-PG14

+3VS

FCH_XTAL32X1

FCH_XTAL32X2

1

22P_0402_50V8-J

2

+3VS

CH20

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

FCH PCIe/PCI/LPC/APU/S5+

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

12 52

1.A

1

2

3

4

5

Add table on 2013 1001

BOARD ID Config.

UH2B

SERIAL ATA

HW MONITOR

Part 2 of 5

SD_CLK/SCLK_0/GPIO73

SD_CMD/SLOAD_0/GPIO74

SD_DATA0/SDATI_0/GPIO77

SD_DATA1/SDATO_0/GPIO78

SD CARD

GBE LAN

ROM_RST#/SPI_WP#/GPIO161

SPI ROM

VGA DAC

VGA MAINLINK

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

SD_CD#/GPIO75

SD_WP/GPIO76

SD_DATA2/GPIO79

SD_DATA3/GPIO80

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3

GBE_RXD2

GBE_RXD1

GBE_RXD0

GBE_RXCTL/RXDV

GBE_RXERR

GBE_TXCLK

GBE_TXD3

GBE_TXD2

GBE_TXD1

GBE_TXD0

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

VGA_RED

VGA_GREEN

VGA_BLUE

VGA_HSYNC/GPO68

VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P

AUX_VGA_CH_N

AUXCAL

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

ML_VGA_HPD/GPIO229

VIN0/GPIO175

VIN1/GPIO176

VIN2/SDATI_1/GPIO177

VIN5/SCLK_1/GPIO180

AL14 AN14 AJ12

SKU ID

AH12

PANEL ID

AK13

CMOS_ON#

AM13 AH15 AJ14

AC4 AD3

delete BT_DET# on UH2.AM13 on 2013 0927

AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9

delete PROJECT ID on UH2.AN14 on 2013 1001

AG6 AE8 AD8 AB9

GBE_PHY_INTR

AC2 AA7 W9

GBE_PHY_INTR

V6

SPI_SI

V5

SPI_SO

V3

SPI_CLK

T6

SPI_CS1#

V1

SPI_WP#

L30

L32

M29

M28

FCH_CRT_HSYNC

N30

FCH_CRT_VSYNC

M33

FCH_CRT_DDC_DATA

N32

FCH_CRT_DDC_CLK

K31

RH151 715_0402_1%

V28

APU_VGA_AUX_C

V29

APU_VGA_AUX#_C

U28

RH150 100_0402_5%

T31

APU_VGA_TXP0

T33

APU_VGA_TXN0

T29

APU_VGA_TXP1

T28

APU_VGA_TXN1

R32

APU_VGA_TXP2

R30

APU_VGA_TXN2

P29

APU_VGA_TXP3

P28

APU_VGA_TXN3

C29

FCH_CRT_HPD

N2

GPIO175

M3

GPIO176

L2

GPIO177

N4

GPIO178

P1

GPIO179

P3

GPIO180

M1

GPIO181

M5

GPIO182

AG16

NC1

AH10

NC2

A28

NC3

G27

NC4

L4

NC5

GPIO175 GPIO176

GPIO182

CMOS_ON# 27

1 2

RH82 10K_0402_5%

SPI_SI 38

SPI_SO 38

SPI_CLK 38 SPI_CS1# 38

1 2

RH19 150_0402_5%

1 2

RH20 150_0402_5%

1 2

RH29 150_0402_5%

1 2

CC115 .1U_0402_16V7K

1 2

CC114 .1U_0402_16V7K

1 2

1

TPH43

Test_Point_12MIL

1

TPH44

Test_Point_12MIL

1

TPH45

Test_Point_12MIL

1

TPH46

Test_Point_12MIL

1

TPH47

Test_Point_12MIL

RPH2

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

SPI_WP#

SPI_HOLD#_8MB SPI_CS1#_8MB

@

Need to enable internal pull down to leave unconnected GPIO177~181 need bios Pull down internally

RPH6

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

A A

HDD

ODD

B B

+VDDAN_11_SATA

SATA_FTX_DRX_P032 SATA_FTX_DRX_N032

SATA_FRX_DTX_N032 SATA_FRX_DTX_P032

SATA_FTX_DRX_P132 SATA_FTX_DRX_N132

SATA_FRX_DTX_N132 SATA_FRX_DTX_P132

1 2

RH32 1K_0402_1%

1 2

RH33 931_0402_1%

RH83 10K_0402_5%@

+3VS

1 2

RH108 10K_0402_5%

12

SATA_FTX_DRX_P0 SATA_FTX_DRX_N0

SATA_FRX_DTX_N0 SATA_FRX_DTX_P0

SATA_FTX_DRX_P1 SATA_FTX_DRX_N1

SATA_FRX_DTX_N1 SATA_FRX_DTX_P1

FCH_GPIO67

SATA_CALRP

SATA_CALRN

AK19 AM19

AN20

AN22

AH20

AH22

AM23 AK23

AH24

AN24

AN26

AH26

AN29

AK27 AM27

AN31

AH33 AH31

AD22

AL20

AL22

AJ20

AJ22

AJ24

AL24

AL26

AJ26

AL28

AL29

AL31 AL33

AJ33 AJ31

AF28 AF27

AF21

AG21

AH16 AM15

ODD_EN

GPIO172 GPIO173 GPIO174

AK15 AN16

AJ16

AL16

M6

C C

D D

ODD_EN32

RPH3

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

BOLTON-M3

SATA_TX0P

SATA_TX0N

SATA_RX0N

SATA_RX0P

SATA_TX1P

SATA_TX1N

SATA_RX1N

SATA_RX1P

SATA_TX2P

SATA_TX2N

SATA_RX2N

SATA_RX2P

SATA_TX3P

SATA_TX3N

SATA_RX3N

SATA_RX3P

SATA_TX4P

SATA_TX4N

SATA_RX4N

SATA_RX4P

SATA_TX5P

SATA_TX5N

SATA_RX5N

SATA_RX5P

NC6

NC7

NC8

NC9

NC10

NC11

NC12

NC13

SATA_CALRP

SATA_CALRN

SATA_ACT#/GPIO67

SATA_X1

SATA_X2

FANOUT0/GPIO52

FANOUT1/GPIO53

FANOUT2/GPIO54

FANIN0/GPIO56

FANIN1/GPIO57

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

TEMPIN3/TALERT#/GPIO174

218084401A1BOLTONM3_FCBGA656

Function

SKU ID

0

UMA@

1

DIS@

+3VALW

FCH_CRT_R 29

FCH_CRT_G 29

FCH_CRT_B 29

FCH_CRT_HSYNC 29 FCH_CRT_VSYNC 29

FCH_CRT_DDC_DATA 29 FCH_CRT_DDC_CLK 29

APU_VGA_AUX 7 APU_VGA_AUX# 7

VDDAN_11_ML

APU_VGA_TXP0 7 APU_VGA_TXN0 7 APU_VGA_TXP1 7 APU_VGA_TXN1 7 APU_VGA_TXP2 7 APU_VGA_TXN2 7 APU_VGA_TXP3 7 APU_VGA_TXN3 7

+3V_SPI

PANEL ID

0

1

Function

14@

15@

SKU ID

PANEL ID

8M SPI ROM

SPI_SO

SPI_SI

SPI_CLK

SPI_CS1#

short +3V_SPI and +3VALW directly

+3VALW +3V_SPI

UH1

SPI_CS1#_8MB

SPI_SI_8MB

SPI_WP# SPI_CLK_8MB

1

CS#

2

DO

3

WP#

GND4DI

W25Q64FVSSIG_SO8

SA000039A2J

HOLD#

VCC

CLK

To APU_VGA_HPD

+3VALW

RH122 10K_0402_5%

1 2

1 3

D

2N7002KW_SOT323-3

RH121 0_0402_5%@

+3VS

RH94

10K_0402_5%

DIS@

1 2

RH95

10K_0402_5%

UMA@

1 2

RH70 0_0402_5%

1 2

RH71 0_0402_5%

1 2

RH72 0_0402_5%

1 2

RH73 0_0402_5%

+3V_SPI

8

7

SPI_HOLD#_8MB

6

5

SPI_SO_8MB

2

1

Modify level shift on 2013 1001

+3VS

2

G

QH4

1 2

RH120 10K_0402_5%

1 2

S

APU_VGA_HPDFCH_CRT_HPD

RH96 10K_0402_5%

15@

1 2

RH97 10K_0402_5%

14@

1 2

SPI_SO_8MB

SPI_SI_8MB

SPI_CLK_8MB

SPI_CS1#_8MB

CH21

0.1U_0402_10V7-K

SPI_HOLD#_8MB 14

APU_VGA_HPD 7

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

FCH SATA/GBE/SPI

Size Document Number Rev

C

Monday, December 16, 2013

Date: Sheet

Date: Sheet of

ACLU7

ACLU7ACLU7

5

of

13 52

1.A

1

2

3

4

5

+3VS

1 2

RH53 10K_0402_5%

RPC14

1 8 2 7

+3VALW

A A

3 6 4 5

2.2K_0804_5%

SD30922018J

@

1 2

RH38 10K_0402_5%

RH87 10K_0402_5%

RH37 10K_0402_5%@

RH98 10K_0402_5%@

RH100 10K_0402_5%

1 2

RPH1

1 8 2 7 3 6 4 5

12

10K_0804_8P4R_5%

1 2

RH68 10K_0402_5%@

1 2

RH67 10K_0402_5%@

1 2

RH105 10K_0402_5%@

1 2

RH106 10K_0402_5%@

1 2

B B

C C

D D

RH107 10K_0402_5%@

HDA_BITCLK_AUDIO34 HDA_SDOUT_AUDIO34 HDA_SYNC_AUDIO34 HDA_RST_AUDIO#34

WD_PWRGD

FCH_SMB0CLK FCH_SMB0DATA FCH_SMB1CLK FCH_SMB1DATA

WD_PWRGD

PBTN_OUT#

EC_WAKE#

ODD_DA#_FCH

AC_PRESENT

FCH_SMB2CLK FCH_SMB2DATA

USB_OC1# USB_OC0#

With S5 plus,PBTN _OUT# pull Up /With out S5 plus,PBTN_OUT # pull low

GPU_WAKE#18

PM_SLP_S3#38 PM_SLP_S5#38 PBTN_OUT#38 FCH_PWROK38

GPU_WAKE#

PM_SLP_S3# PM_SLP_S5#

PBTN_OUT#

FCH_PWROK

Test_Point_12MIL Test_Point_12MIL

Test_Point_12MIL

GATEA2038 KBRST#38 EC_SCI#38

delete net name EC_SMI# on UH2.C26 on 20130928

Change net nam e from PCIE_WAKE# to EC_WAKE# on 20130928

EC_WAKE#18,38

H_THERMTRIP#7,18

EC_RSMRST#38

Reserve CH9 and unmounted on 20130927

LAN_CLKREQ#35

FCH_SPKR34

HDA_SDIN0 HDA_BITCLK_AUDIO AZ_SDIN1 AZ_SDIN2 AZ_SDIN3

SPI_HOLD#_8MB13

CLKREQ_WLAN#33

delete BATT_LEN# on UH1.J2

1 2

RH77 0_0402_5%

GPU_CLKREQ17

Change DGPU_PWROK_R from UH2.AG26 to UH2.AH14

ODD_DA#_FCH32

ODD_DETECT#32 AC_PRESENT38

USB_OC1#31

HDA_BITCLK_AUDIO

HDA_SDOUT_AUDIO

HDA_SYNC_AUDIO HDA_RST_AUDIO#

RPH5

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SD300003700

AZ_BITCLK AZ_SDOUT

AZ_SYNC

AZ_RST#

USB_OC0#30

HDA_SDIN034

RH102

1 2

RH143 0_0402_5%

1 2

RH145

1 2

0_0402_5%

1

TPH3

1

TPH4

1

TPH5

Test_Point_12MIL

delete EC_LID_OUT# from UE1.Pin21 and UH2.R2 ,add GPU_WAKE#_R on U H2.R2

UH2D

AB6

PCIE_RST2#/GEVENT4#

R2

RI#/GEVENT22#

W7

0_0402_5%

FCH_PWROK_R

TEST0 TEST1 TEST2 GATEA20 KBRST# EC_SCI#

EC_WAKE#

H_THERMTRIP# WD_PWRGD

EC_RSMRST#

LAN_CLKREQ#

FCH_SPKR FCH_SMB0CLK FCH_SMB0DATA FCH_SMB1CLK FCH_SMB1DATA CLKREQ_WLAN#

SPI_HOLD#

GPU_CLKREQ

ODD_DA#_FCH

ODD_DETECT# AC_PRESENT

USB_OC1# USB_OC0#

AZ_BITCLK AZ_SDOUT HDA_SDIN0 AZ_SDIN1 AZ_SDIN2 AZ_SDIN3 AZ_SYNC AZ_RST#

PM_SLP_S3#_R PM_SLP_S5#_R

TPH27

1

TPH6Test_Point_12MIL

1

TPH7Test_Point_12MIL

1

TPH30Test_Point_12MIL

1

TPH31Test_Point_12MIL

1

TPH26Test_Point_12MIL

1

TPH28Test_Point_12MIL

1

TPH8Test_Point_12MIL

1

TPH9Test_Point_12MIL

1

TPH10Test_Point_12MIL

1

TPH11Test_Point_12MIL

1

TPH12Test_Point_12MIL

1

TPH13Test_Point_12MIL

1

TPH14Test_Point_12MIL

1

TPH15Test_Point_12MIL

1

TPH16Test_Point_12MIL

1

TPH17Test_Point_12MIL

1

TPH18Test_Point_12MIL

1

TPH19Test_Point_12MIL

1

TPH20Test_Point_12MIL

1

TPH21Test_Point_12MIL

1

TPH22Test_Point_12MIL

1

TPH23Test_Point_12MIL

1

TPH24Test_Point_12MIL

1

TPH25Test_Point_12MIL

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVENT2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN#/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/GEVENT12#/TRST

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/XDB0/GPIO223

B17

KSO_15/XDB1/GPIO224

A24

KSO_16/XDB2/GPIO225

D17

KSO_17/XDB3/GPIO226

BOLTON-M3

Part 4 of 5

HD AUDIO

218084401A1BOLTONM3_FCBGA656

EMBEDDED CTRL

USBCLK/14M_25M_48M_OSC

USB MISC

USB 1.1

ACPI / WAKE UP EVENTS

USB 2.0

GPIO

USB OC

USB 3.0

EC_PWM0/EC_TIMER0/GPIO197

EC_PWM1/EC_TIMER1/GPIO198

EC_PWM2/EC_TIMER2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER3/GPIO200

USB_RCOMP

USB_FSD1P/GPIO186

USB_FSD1N

USB_FSD0P/GPIO185

USB_FSD0N

USB_HSD13P

USB_HSD13N

USB_HSD12P

USB_HSD12N

USB_HSD11P

USB_HSD11N

USB_HSD10P

USB_HSD10N

USB_HSD9P

USB_HSD9N

USB_HSD8P

USB_HSD8N

USB_HSD7P

USB_HSD7N

USB_HSD6P

USB_HSD6N

USB_HSD5P

USB_HSD5N

USB_HSD4P

USB_HSD4N

USB_HSD3P

USB_HSD3N

USB_HSD2P

USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P

USB_HSD0N

USBSS_CALRP

USBSS_CALRN

USB_SS_TX3P

USB_SS_TX3N

USB_SS_RX3P

USB_SS_RX3N

USB_SS_TX2P

USB_SS_TX2N

USB_SS_RX2P

USB_SS_RX2N

USB_SS_TX1P

USB_SS_TX1N

USB_SS_RX1P

USB_SS_RX1N

USB_SS_TX0P

USB_SS_TX0N

USB_SS_RX0P

USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194

SCL3_LV/GPIO195

SDA3_LV/GPIO196

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

G8

B9

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12 K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16 A16

A14 C14

C12 A12

D15 B15

E14 F14

F15 G15

H13 G13

J16 H16

J15 K15

H19 G19 G22 G21 E22 H22 J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

USB_RCOMP

RH45 11.8K_0402_5%

USB20_P12 USB20_N12

USB20_P6 USB20_N6

USB20_P5 USB20_N5

USB20_P8 USB20_N8

USB20_P11 USB20_N11

USB20_P4 USB20_N4

USB20_P10 USB20_N10

USBSS_CALRP USBSS_CALRN

USB30_TX_P1 USB30_TX_N1

USB30_RX_P1 USB30_RX_N1

FCH_SMB2CLK FCH_SMB2DATA EC_SMBLV_CK EC_SMBLV_DA

1

TPH29

EC_PWM2

GPU, EC, Thermal Sensor

1 2

USB20_P12 31 USB20_N12 31

USB20_P6 33 USB20_N6 33

USB20_P5 27 USB20_N5 27

USB20_P8 27 USB20_N8 27

USB20_P11 31 USB20_N11 31

USB20_P4 30 USB20_N4 30

USB20_P10 30 USB20_N10 30

1 2

RH46 1K_0402_1%

1 2

RH47 1K_0402_1%

USB30_TX_P1 31 USB30_TX_N1 31

USB30_RX_P1 31 USB30_RX_N1 31

Test_Point_12MIL

EC_PWM2 16

RH39

10K_0402_5%

1 2

APU SIC/SIV

RH40

10K_0402_5%

1 2

+3VS

2N7002KDWH

2

G

Vth= min 1V, max 2.5V ESD 2KV

FCH_SMB1CLK EC_SMB_CK3

FCH_SMB1DATA EC_SMB_DA3

6 1

5

G

3 4

S

D

QH1B 2N7002KDWH_SOT363-6

SB00000EO1J

S

D

QH1A 2N7002KDWH_SOT363-6

SB00000EO1J

JUSB2(Left)

WLAN

Camera

Touch Screen(Reserved)

JUSB1(Left)

Card Reader

USB/B (Right)

+VDDAN_11_SSUSB_S

JUSB2(Left)

EC_SMBLV_CK 7 EC_SMBLV_DA 7

Follow Edge to connect with 0 ohm directly on 20131009

RH153

0_0402_5%

FCH_SMB0CLK

FCH_SMB0DATA

1 2

RH154

0_0402_5%

SMB0_CLK

SMB0_DATA

EC_SMB_CK3 7,18,37,38

EC_SMB_DA3 7,18,37,38

SMB0_CLK 10,11,33

SMB0_DATA 10,11,33

Delete Security EEPROM USROM3 ,unused

1

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

FCH ACPI/USB/GPIO

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

14 52

1.A

1

2

3

4

5

VDDPL_33_SATA & PCIE & SYS

+3VS

22u *1, 1u*1 for circuit check list

+VDDCR_11+3VS

CH44

0.1U_0402_10V7-K

1

0_0805_5%

2

+VDDAN_11_CLK

CH49

22U_0603_6.3V6-M

1

2

+VDDAN_11_PCIE

1 2

0_0603_5%

+VDDAN_11_SATA

0_0805_5%

+3VALW +3VALW

RH79

CH65

+3VALWVDDAN_33_HWM

LH9

CH63

+3VS

RH81

RH101

+1.5VS

0_0402_5%

0_0603_5%

RH78

1 2

A A

+VDDPL_33_SYS

VDDPL_33_DACML

VDDAN_33_DAC_R

+VDDPL_33_SSUSB_S +VDDPL_33_USB_S +VDDPL_33_PCIE +VDDPL_33_SATA

+1.1VS

LH17

1 2

BLM18BB470SN1D_2P~D

RH149

1 2

0_0603_5%

VDDAN_11_ML

B B

VDDIO_33_PCIGP

22U_0603_6.3V6-M

1

CH23

CH24

2

0.1U_0402_10V7-K

1 2

RH57 0_0402_5%

1 2

RH58 0_0402_5%

1 2

CH27 2.2U_0402_6.3V6-M@

CH12

CH13

CH14

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

1

2

1

CH25

2

0.1U_0402_10V7-K

VDDPL_33_DAC

VDDPL_33_ML

0.1U_0402_10V7-K

2

1

CH26

2

0.1U_0402_10V7-K

226mA

102mA

47mA

20mA

12mA

AB17 AB18

AD10

AC13 AB12 AB13 AB14 AB16

AH29 AG28

AB10

AB11 AA11

AA10

AE9

AG7

H24 V22 U22

T22 L18

D7

M31

V21

Y22 V23 V24 V25

AA9

UH2C

BOLTON-M3

VDDIO_33_PCIGP_1

VDDIO_33_PCIGP_2

VDDIO_33_PCIGP_3

VDDIO_33_PCIGP_4

VDDIO_33_PCIGP_5

VDDIO_33_PCIGP_6

VDDIO_33_PCIGP_7

VDDIO_33_PCIGP_8

VDDIO_33_PCIGP_9

VDDIO_33_PCIGP_10

VDDPL_33_SYS

VDDPL_33_DAC

VDDPL_33_ML

VDDAN_33_DAC

VDDPL_33_SSUSB_S

VDDPL_33_USB_S

VDDPL_33_PCIE

VDDPL_33_SATA

LDO_CAP

VDDPL_11_DAC

VDDAN_11_ML_1

VDDAN_11_ML_2

VDDAN_11_ML_3

VDDAN_11_ML_4

VDDIO_33_GBE_S

VDDCR_11_GBE_S_1

VDDCR_11_GBE_S_2

VDDIO_GBE_S_1

VDDIO_GBE_S_2

Part 3 of 5

PCI/GPIO I/O

CLKGEN I/O

MAIN LINK

PCI EXPRESS

SERIAL ATA

GBE LAN

CORE S0

VDDCR_11_1

VDDCR_11_2

VDDCR_11_3

VDDCR_11_4

VDDCR_11_5

VDDCR_11_6

VDDCR_11_7

VDDCR_11_8

VDDCR_11_9

VDDAN_11_CLK_1

VDDAN_11_CLK_2

VDDAN_11_CLK_3

VDDAN_11_CLK_4

VDDAN_11_CLK_5

VDDAN_11_CLK_6

VDDAN_11_CLK_7

VDDAN_11_CLK_8

VDDAN_11_PCIE_1

VDDAN_11_PCIE_2

VDDAN_11_PCIE_3

VDDAN_11_PCIE_4

VDDAN_11_PCIE_5

VDDAN_11_PCIE_6

VDDAN_11_PCIE_7

VDDAN_11_PCIE_8

VDDAN_11_SATA_1

VDDAN_11_SATA_4

VDDAN_11_SATA_2

VDDAN_11_SATA_3

VDDAN_11_SATA_5

VDDAN_11_SATA_6

VDDAN_11_SATA_7

VDDAN_11_SATA_8

VDDAN_11_SATA_9

VDDAN_11_SATA_10

T14 T17 T20 U16 U18 V14 V17 V20 Y17

H26 J25 K24 L22 M22 N21 N22 P22

AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27

AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19

1007mA

CH40

CH45

CH50

CH53

CH41

10U_0603_6.3V6-M

1

2

CH46

1U_0402_10V6-K

1

2

CH51

1U_0402_10V6-K

1

2

CH54

1U_0402_10V6-K

1

2

CH43

CH42

1U_0402_10V6-K

1

2

1U_0402_10V6-K

1

2

0.1U_0402_10V7-K

1

2

1U_0402_10V6-K

1

2

CH47

CH52

CH55

0.1U_0402_10V7-K

1U_0402_10V6-K

1

2

CH48

0.1U_0402_10V7-K

1

2

22U_0603_6.3V6-M

1

2

CH56

22U_0603_6.3V6-M

0.1U_0402_10V7-K

1

2

+VDDAN_33_USB_S+3VALW

LH1

1 2

BLM15BD221SN1D_2P

CH28

CH29

CH30

CH31

10U_0603_6.3V6-M

1

2

CH32

1U_0402_10V6-K

1

2

+VDDAN_11_USB_S

+VDDCR_1.1V_USB

12

RH62 0_0402_5%

+VDDAN_11_SSUSB_S+1.1VALW

CH33

1

2

+VDDCR_11_SSUSB_S

CH36

1

2

CH34

CH35

1U_0402_10V6-K

0.1U_0402_10V7-K

1

2

CH37

10U_0603_6.3V6-M

CH39

CH38

1U_0402_10V6-K

1

2

0.1U_0402_10V7-K

1

2

LH2

1 2

BLM18BB470SN1D_2P~D

C C

+1.1VALW

LH3

1 2

BLM18BB470SN1D_2P~D

@

470mA

G7

0.1U_0402_25V7-K

1

2

VDDAN_33_USB_S_1

H8

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

3.3V_S5 I/O

USB

USB SS

POWER

218084401A1BOLTONM3_FCBGA656

VDDIO_33_S_1

VDDIO_33_S_2

VDDIO_33_S_3

VDDIO_33_S_4

VDDIO_33_S_5

VDDIO_33_S_6

VDDIO_33_S_7

VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1

VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM_S

VDDIO_AZ_S

N18 L19 M18 V12 V13 Y12 Y13 W11

G24

N20 M20

J24

M8

AA4

VDDIO_33_S

VDDXL_33_S

VDDCR_11_S

VDDPL_11_SYS_S

VDDIO_AZ_S

CH57

CH59

CH61

CH62

1U_0402_10V6-K

1

2

0.1U_0402_10V7-K

1

2

2.2U_0402_6.3V6-M

1

2

1 2

0_0603_5%

1 2

BLM15BD221SN1D_2P

1 2

0_0402_5%

@

1 2

CH58

1U_0402_10V6-K

2.2U_0402_6.3V6-M

1

2

CH60

2.2U_0402_6.3V6-M

1

2

RH61

RH63

RH84

0_0805_5%

RH89

1U_0402_10V6-K

1

2

0.1U_0402_10V7-K

1

2

CH67

CH66

CH64

+1.1VS

12

+1.1VS

12

+1.1VS

12

LH7

1 2

2.2U_0402_6.3V6-M

BLM15BD221SN1D_2P

1

2

RH80 0_0603_5%

1 2

1U_0402_10V6-K

1

2

LH8

1 2

2.2U_0402_6.3V6-M

BLM15BD221SN1D_2P

1

2

VDDCR_1.1V_USB

VDDAN_11_USB_S

+1.1VALW

VDDPL_33_USB_S

VDDPL_33_SSUSB_S

LH12

1 2

BLM15BD221SN1D_2P

LH13

1 2

BLM15BD221SN1D_2P

LH14

1 2

BLM15BD221SN1D_2P

+1.1VALW

+VDDAN_33_USB_S +VDDPL_33_USB_S

VDDPL_33_DACMLVDDAN_33_DAC_R+3VS

LH18

1 2

BLM18PG221SN1D_2P

D D

+3VALW

+3VS

+1.1VALW

+1.1VS

+VDDAN_33_HWM,+VDDAN_33_USB_S,VDDPL_33_SSUSB_S,+VDDPL_33_USB_S

+VDDPL_33_SATA,+VDDPL_33_PCIE,+VDDPL_33_SYS

+VDDCR_11_SSUSB_S,+VDDAN_11_SSUSB_S,+VDDAN_11_USB_S, +VDDAN_11_USB_S,+VDDCR_1.1V_USB

+VDDCR_11,+VDDAN_11_CLK,+VDDAN_11_PCIE,+VDDAN_11_SATA,

1

2

1

CH86

2

2.2U_0402_6.3V6-M

RH152

1 2

0_0603_5%

1

CH85

2

0.1U_0402_10V7-K

1

CH84

2

2.2U_0402_6.3V6-M

3

Add RH101 to reserve power rail +1.5VS

CH83

0.1U_0402_10V7-K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

1 2

BLM15BD221SN1D_2P

Size Document Number Rev

Custom

Date: Sheet of

LH15

1 2

BLM15BD221SN1D_2P

LH16

1 2

BLM15BD221SN1D_2P

LH10

1 2

BLM15BD221SN1D_2P

LH11

Title

FCH POWER/GND

+VDDPL_33_SATA

+VDDPL_33_PCIE

+VDDPL_33_SYS

+VDDCR_1.1V_USB

1

CH76

2

+VDDAN_11_USB_S

1

CH79

2

1

2

+VDDPL_33_SSUSB_S+3VALW

1

2

Monday, December 16, 2013

1

2

1

2

1

2

1

2

10U_0603_6.3V6-M

1

2

2.2U_0402_6.3V6-M

CH68

2.2U_0402_6.3V6-M

CH70

2.2U_0402_6.3V6-M

ACLU7

ACLU7ACLU7

5

CH74

CH77

CH80

1

2

1

2

CH72

2.2U_0402_6.3V6-M

CH73

2.2U_0402_6.3V6-M

0.1U_0402_10V7-K

CH69

CH71

1

CH75

2

1

CH78

2

0.1U_0402_10V7-K

1

CH81

2

0.1U_0402_10V7-K

1U_0402_10V6-K

0.1U_0402_10V7-K

15 52

0.1U_0402_10V7-K

1.A

1

2

3

4

5

UH2E

BOLTON-M3

A3

VSS_1

A33

VSS_2

B7

VSS_3

B13

VSS_4

A A

B B

C C

D9

VSS_5

D13

VSS_6

E5

VSS_7

E12

VSS_8

E16

VSS_9

E29

VSS_10

F7

VSS_11

F9

VSS_12

F11

VSS_13

F13

VSS_14

F16

VSS_15

F17

VSS_16

F19

VSS_17

F23

VSS_18

F25

VSS_19

F29

VSS_20

G6

VSS_21

G16

VSS_22

G32

VSS_23

H12

VSS_24

H15

VSS_25

H29

VSS_26

J6

VSS_27

J9

VSS_28

J10

VSS_29

J13

VSS_30

J28

VSS_31

J32

VSS_32

K7

VSS_33

K16

VSS_34

K27

VSS_35

K28

VSS_36

L6

VSS_37

L12

VSS_38

L13

VSS_39

L15

VSS_40

L16

VSS_41

L21

VSS_42

M13

VSS_43

M16

VSS_44

M21

VSS_45

M25

VSS_46

N6

VSS_47

N11

VSS_48

N13

VSS_49

N23

VSS_50

N24

VSS_51

P12

VSS_52

P18

VSS_53

P20

VSS_54

P21

VSS_55

P31

VSS_56

P33

VSS_57

R4

VSS_58

R6

VSS_59

R11

VSS_60

R25

VSS_61

R28

VSS_62

T11

VSS_63

T16

VSS_64

T18

VSS_65

N8

VSSAN_HWM

K25

VSSXL

H25

VSSPL_SYS

218084401A1BOLTONM3_FCBGA656

Part 5 of 5

T25

VSS_66

T27

VSS_67

U6

VSS_68

U14

VSS_69

U17

VSS_70

U20

VSS_71

U21

VSS_72

U30

VSS_73

U32

VSS_74

V11

VSS_75

V16

VSS_76

V18

VSS_77

W4

VSS_78

W6

VSS_79

W25

VSS_80

W28

VSS_81

Y14

VSS_82

Y16

VSS_83

Y18

VSS_84

AA6

VSS_85

AA12

VSS_86

AA13

VSS_87

AA14

VSS_88

AA16

VSS_89

AA17

VSS_90

AA25

VSS_91

AA28

VSS_92

AA30

VSS_93

AA32

VSS_94

AB25

VSS_95

GROUND

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

VSSPL_DAC

VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCICLK112

PCICLK312

PCICLK412

CLK_PCI_EC12,38

LPC_CLK112

EC_PWM214

RTC_CLK12

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

PCI_CLK4 CLK_PCI_EC

NON_FUSION CLOCK MODE

FUSION CLOCK MODE

DEFAULT

RH128 10K_0402_5%

12

RH140 10K_0402_5%

12

@

EC ENABLED

EC DISABLED

DEFAULT

+3VS+3VS+3VS

RH132 10K_0402_5%

RH134 10K_0402_5%

12

@

RH137 10K_0402_5%

RH139 10K_0402_5%

12

+3VALW

12

RTC_CLKLPC_CLK1

S5 PLUS MODE DISABLED

S5 PLUS MODE ENABLED

DEFAULT

RH135 10K_0402_5%

@

RH144 10K_0402_5%

EC_PWM2

CLKGEN ENABLED

DEFAULT

CLKGEN DISABLE

+3VALW+3VALW

RH136 10K_0402_5%

12

@

RH141 10K_0402_5%

12

LPC ROM

SPI ROM

DEFAULT

+3VALW

RH133 10K_0402_5%

RH138 10K_0402_5%

12

@

R156 2.2K_0402_5%

RH142 10K_0402_5%

12

@

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD25 PCI_AD24

USE FC PLL

BYPASS FC PLL

RH126 10K_0402_5%

12

@

PULL HIGH

PULL LOW

PCI_AD2712

PCI_AD2612

PCI_AD2512

PCI_AD2412

PCI_AD2312

PCI_AD27 PCI_AD26

USE PCI PLL

DEFAULT

BYPASS PCI PLL

DISABLE ILA AUTORUN

DEFAULT

ENABLE ILA AUTORUN

need confirm AD26

RH127 10K_0402_5%

12

@

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

RH125 10K_0402_5%

12

@

PCI_AD23

DISABLE PCI MEM BOOT

DEFAULTDEFAULT

ENABLE PCI MEM BOOT

RH124 10K_0402_5%

12

@

RH123 10K_0402_5%

12

@

D D

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

FCH GND

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

16 52

1.A

1

2

3

4

5

UV3G

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

NC_121

U31

NC_122

U29

NC_123

T28

NC_124

T30

NC_125

R31

NC_126

R29

NC_127

P28

NC_128

P30

NC_129

N31

NC_130

N29

NC_131

M28

NC_132

M30

NC_133

L31

NC_134

L29

NC_135

K30

NC_136

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

TEST_PG

AL27

PERSTB

216-0858020-A0_FCBGA631

PCI EXPRESS INTERFACE

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

NC_137 NC_138

NC_139 NC_140

NC_141 NC_142

NC_143 NC_144

NC_145 NC_146

NC_147 NC_148

NC_149 NC_150

NC_151 NC_152

AH30 AG31

AG29 AF28

AF27 AF26

AD27 AD26

AC25 AB25

Y23 Y24

AB27 AB26

Y27 Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

Y22

AA22

1 2

RV47 1.69K_0402_1%DIS@

RV48

1 2

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0

PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1

PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2

PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3

PCIE_CRX_C_GTX_P4 PCIE_CRX_C_GTX_N4

PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5

PCIE_CRX_C_GTX_P6 PCIE_CRX_C_GTX_N6

PCIE_CRX_C_GTX_P7 PCIE_CRX_C_GTX_N7

1K_0402_1%DIS@

+0.95VS_VGA

+3VS_VGA

12

RV50 10K_0402_5%

RV49

@

DGPU_PWREN12,24,51

GPU_CLKREQ14

10K_0402_5%

CV141

@

12

0.1U_0402_10V7-K

1

2

CV140

0.1U_0402_10V7-K

1

@

2

1 3

D

2N7002KW_SOT323-3

SB00000YY00

1 2

RV51 0_0402_5%

@

+3VS_VGA

12

@

RV52

QV7

2

G

@

S

@

10K_0402_5%

CLK_REQ_GPU#

RV53 10K_0402_5%

@

1 2

CLK_REQ_GPU# 18

RV42

0_0402_5%

PCIE_CTX_C_GRX_N[0..7]

PCIE_CTX_C_GRX_P[0..7]

PCIE_CRX_GTX_N[0..7]

PCIE_CRX_GTX_P[0..7]

+3VS

@

1

IN1

2

IN2

DIS@

5

VCC

GND

3

UV4

4

OUT

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3

PCIE_CRX_C_GTX_P4PCIE_CRX_GTX_P4 PCIE_CRX_C_GTX_N4 PCIE_CRX_C_GTX_P5PCIE_CRX_GTX_P5 PCIE_CRX_C_GTX_N5 PCIE_CRX_C_GTX_P6PCIE_CRX_GTX_P6 PCIE_CRX_C_GTX_N6 PCIE_CRX_C_GTX_P7PCIE_CRX_GTX_P7 PCIE_CRX_C_GTX_N7

+3VS_VGA

12

RV43 10K_0402_5%

@

PLT_RST_VGA#

RV44

100K_0402_5%

DIS@

1 2

PLT_RST_VGA#

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7

PLT_RST_VGA# 18,51

1 2

RV40 1K_0402_5%DIS@

1 2

RV41 0_0402_5%DIS@

GFX_CLKP GFX_CLKN

GFX_CLKP12 GFX_CLKN12

PCIE_CTX_C_GRX_N[0..7]5

PCIE_CTX_C_GRX_P[0..7]5

PCIE_CRX_GTX_N[0..7]5

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PCIE_CRX_GTX_N4

PCIE_CRX_GTX_N5

PCIE_CRX_GTX_N6

PCIE_CRX_GTX_N7

PLT_RST#12,33,35

PCIE_CRX_GTX_P[0..7]5

CV132 0.1U_0402_16V7-KDIS@ CV133 0.1U_0402_16V7-KDIS@ CV134 0.1U_0402_16V7-KDIS@ CV135 0.1U_0402_16V7-KDIS@ CV136 0.1U_0402_16V7-KDIS@ CV137 0.1U_0402_16V7-KDIS@ CV138 0.1U_0402_16V7-KDIS@ CV139 0.1U_0402_16V7-KDIS@

CV157 0.1U_0402_16V7-KDIS@ CV158 0.1U_0402_16V7-KDIS@ CV159 0.1U_0402_16V7-KDIS@ CV175 0.1U_0402_16V7-KDIS@ CV176 0.1U_0402_16V7-KDIS@ CV177 0.1U_0402_16V7-KDIS@ CV178 0.1U_0402_16V7-KDIS@ CV179 0.1U_0402_16V7-KDIS@

PLT_RST#

DGPU_HOLD_RST#

MC74VHC1G08DFT2G_SC70-5

DIS@

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

A A

B B

DGPU_HOLD_RST#12

C C

D D

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

Topaz & Jet PCIE

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

17 65

1.A

5

D D

+3VS_VGA

RV128 0_0402_5%

1 2

@

1 2

RV56

0_0402_5%

G

2

G

S

2N7002KDWH_SOT363-6

5

QV2B

SB00000EO1J

34

D

Pull high 2.2K to +3VS at EC SIDE

VGA_AC_BATT

SMBCLK

SMBDAT

2N7002KDWH_SOT363-6

C C

VGA_AC_BATT38

Add net name GPU_VR_HOT for GPIO5 & GPIO6 of GPU and RV130,R131 on 1002

@

RV131 0_0402_5%

GPU_VR_HOT#38,51

GPU_VR_HOT#

1 2

QV2A

SB00000EO1J

61

D

RB751V-40_SOD323-2

SCS00006S00

DIS@

RV130 0_0402_5%@

1 2

RV132 0_0402_5%@

1 2

+3VS_VGA

RV61 10K_0402_5%

TOPAZ@

1 2

DV2

1 2

12

RV57

RV58

+3VS_VGA

RV62

1 2

1K_0402_5%

OCP_L deleted ,reserve for PCC for Topaz

+3VS_VGA

B B

RV104 10K_0402_5%

@

A A

12

RV64 10K_0402_5%

@

12

RV65 10K_0402_5%

@

XTALOUT

12

RV66 10K_0402_5%

@

RV101

DIS@

1 2

0_0402_5%

modify YV1 to SJ10000GI00 S CRYSTAL 27MHZ 16PF +-10PPM 7V27000050 on 20131205

RV67 10K_0402_5%

12

@

JTAG_TRSTB

JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

27MHZ_10PF_7V27000050

1

CV143

8.2P_0402_50V8-J

2

DIS@

12

EC_WAKE#14,38

GPU_WAKE#14

RV68

DIS@

1 2

1M_0402_5%

YV1

DIS@

4

3

NC2

OSC2

1

2

OSC1

NC1

@

100K_0402_5%

@

100K_0402_5%

RV111 10K_0402_5%DIS@

TOPAZ@

XTALIN

1

CV144

8.2P_0402_50V8-J

2

DIS@

PLT_RST_VGA# 17,51

+3VS_VGA

EC_SMB_CK3 7,14,37,38

+3VS_VGA

EC_SMB_DA3 7,14,37,38

1 2

GPIO5_AC_BATT

GPIO6

1

CV142

0.1U_0402_16V7-K

TOPAZ@

2

EC_WAKE#

1 2

RV123 0_0402_5%@

Add GPU_WAKE#

4

+1.8VS_VGA +1.8VS_VGA

RV54

4.7K_0402_5%

TOPAZ@

TPV1Test_Point_20MIL

1 1

TPV2Test_Point_20MIL

+3VS_VGA

CLK_REQ_GPU#17

+3VS_VGA

RV129 0_0402_5%

1 2

@

RV115

TOPAZ@

1 2

4.7K_0402_5%

12

RV124

10K_0402_5%

@

1

TPV7Test_Point_20MIL TPV8Test_Point_20MIL

1 1

TPV9Test_Point_20MIL TPV10Test_Point_20MIL

1

TPV11Test_Point_20MIL

1

2N7002KW_SOT323-3

SB00000YY00

TOPAZ@

12

RV55

4.7K_0402_5%

TOPAZ@

RV72 45.3K_0402_1%DIS@

RV73 45.3K_0402_1%DIS@

SMBDAT SMBCLK

GPIO6

12

GPIO19_CTF

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

+3VS_VGA

RV76 5.11K_0402_1%@

RV99 1K_0402_5%DIS@

PUll down RV106 for OBBF design

+3VS_VGA

2

G

QV4

1 3

D

S

+1.8VS_VGA

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1

1 2

GPIO5_AC_BATT

1

GPIO8_ROMSO

TPV3Test_Point_20MIL TPV4Test_Point_20MIL

1

GPIO9_ROMSI

TPV5Test_Point_20MIL

1

GPIO10_ROMSCK

GPIO15

Test_Point_20MIL

GPIO20

TPV6Test_Point_20MIL

1

CV145

DIS@

1 2 1 2

1 2

1 2 1 2

1U_0402_10V6-K

1

2

TOPAZ@

GPIO22_ROMCSB

1

TPV13Test_Point_20MIL

XTALIN XTALOUT

TPV36

1 1

TPV37

RV84

RV112 0_0402_5%@ RV75 100_0402_5%@

1 2

RV79 0_0402_5%@

RV103 4.7K_0402_5%

RV106 4.7K_0402_5%

RV81 16.2K_0402_1%

RV82 10K_0402_5%DIS@ RV83 10K_0402_5%DIS@

Test_Point_20MIL Test_Point_20MIL

TPV17Test_Point_20MIL TPV18Test_Point_20MIL TPV19Test_Point_20MIL TPV20Test_Point_20MIL TPV21Test_Point_20MIL TPV22Test_Point_20MIL TPV23Test_Point_20MIL TPV24Test_Point_20MIL TPV25Test_Point_20MIL TPV26Test_Point_20MIL TPV27Test_Point_20MIL TPV28Test_Point_20MIL TPV29Test_Point_20MIL TPV30Test_Point_20MIL TPV31Test_Point_20MIL TPV32Test_Point_20MIL TPV33Test_Point_20MIL TPV34Test_Point_20MIL

TPV35Test_Point_20MIL

TPV12

GPU_DPLUS GPU_DMINUS

FDO

JET@

1 2

10K_0402_5%

3

UV3A

N9

NC_DBG_DATA16

L9

NC_DBG_DATA15

AE9

NC_DBG_DATA14

Y11

NC_DBG_DATA13

AE8

NC_DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

AL9

NC_DBG_CNTL0

U1

BP_0

U3

BP_1

AM26

DIECRACKMON

W6

NC_2

V6

NC_3

AC6

NC_4

AC5

NC_5

AA5

NC_6

AA6

NC_7

Y6

NC_8

I2C

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6_TACH

T7

NC_GPIO_7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

1

GPIO_17_THERMAL_INT

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC_9

W8

NC_GENERICB

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC_10

AB16

PX_EN

AJ27

WAKEB

AC16

NC_DBG_VREFG

PLL/CLOCK

AA1

PLL_ANALOG_IN

AA3

PLL_ANALOG_OUT

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

AE19

TS_A

216-0858020-A0_FCBGA631

FDO

THERMAL

2

RV87

RV88 100K_0402_5%

DIS@

1 2

+3VS_VGA

GPIO15_L

GPIO20_L

CV152

1

JET@

2

+3VS_VGA

+1.8VS_VGA

12

@

12

+1.8VS_VGA

RV63

RV70

10U_0603_6.3V6-M

12

1 2

2.2K_0402_5%

CV149

JET@

1 2

RV119 10K_0402_5%

@

1 2

0.1U_0402_10V7-K

1

2

RV95

10K_0402_5%

JET@

CV16

1

@

2

CV19

1

@

2

DIS@

+3VS_VGA

SVI2_SVD

SVI2_SVC

PS_1

0.1U_0402_10V7-K

PS_3

0.1U_0402_10V7-K

CV148

DIS@

UV9

1

2

3

5

74AVCH2T45GD_XSON8_3X2

1 2

RV86

47K_0402_5%DIS@

1 2

GPIO15_L

GPIO20_L

GPIO19_CTF

RV133

RV134

PLT_RST_VGA#

@

1 2

@

1 2

0_0201_5%

DV1

1 2

RB751V-40_SOD323-2

SCS00006S00

DIS@

SVI2_SVD_L

SVI2_SVC_L

Reserve RV133 RV134 if UV9 bypass not used on 20131205

+3VS_VGA

12

RV89 33_0402_5%JET@

RV90 33_0402_5%JET@

VID CODES

SVC (GPIO20)

0 0

1

1 2 1 2 1 2

PS_0

PS_1

PS_2

PS_3

1 2

SVD (GPIO15)

0 1

0

1

8.45K_0402_1%

2K_0402_1%

4.99K_0402_1%

4.75K_0402_1%

DIS@

RV71

DIS@

RV60

RV69

DIS@

+1.8VS_VGA

RV77

+1.8VS_VGA

@

RV91 10K_0402_5%

RV93 10K_0402_5%

JET@

Boot Voltage

SVI2_SVD SVI2_SVT SVI2_SVC

12

1 2

12

RV92 10K_0402_5%

JET@

@

12

RV94 10K_0402_5%

@

CV151

JET@

1.1V

1.0V

0.9V(Default)

0.8V

SVI2_SVD 51 SVI2_SVT 51 SVI2_SVC 51

1 2

SVI2_SVD

SVI2_SVT

SVI2_SVC

4.99K_0402_1%

PS_0

CV15

0.1U_0402_10V7-K

1

@

2

4.75K_0402_1%

Update location number to sync with ALCU5 on 0927

4.99K_0402_1%

PS_2

CV18

0.1U_0402_10V7-K

1

@

2

4.99K_0402_1%

0.1U_0402_10V7-K

1

2

RV118 10K_0402_5%

@

DIS@

X76@

RV74

RV80

AF2

NC_13

AF4

NC_14

AG3

NC_15

AG5

NC_16

NC_DPA

DBG

NC_DPB

NC_DPC

NC_DAC1

NC_GENLK_VSYNC

MLPS&SVI2

NC_DDC/AUX

NC_DDCVGADATA

NC_17 NC_18

NC_19 NC_20

NC_21 NC_22

NC_23 NC_24

NC_25 NC_26

NC_27 NC_28

NC_29 NC_30

NC_31

NC_32 NC_33

NC_34

NC_35

NC_G

NC_AVSSN_1

NC_AVSSN_2

NC_B

NC_AVSSN_3

NC_HSYNC

NC_RSET

NC_AVDD

NC_AVSSQ

NC_VDD1DI NC_VSS1DI

NC_CEC_1

GPIO_SVD GPIO_SVT GPIO_SVC

NC_GENLK_CLK

NC_SWAPLOCKA

NC_SWAPLOCKB

NC_DDC1CLK

NC_DDC1DATA

NC_AUX1P NC_AUX1N

NC_AUX2P NC_AUX2N

NC_36 NC_37

NC_DDCVGACLK

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

V2

Y4 W5

GPIO15

GPIO20

Y2

J8

AL25

AK26

AJ25 AH24

AG25

AH26

AD22

AG24 AE22

AE23 AD23

AM12

AK12

RV107 0_0402_5%TOPAZ@ RV108 0_0402_5%TOPAZ@

AL11 AJ11

RV109 0_0402_5%TOPAZ@

AL13 AJ13

AG13

AC19

PS_0

AH12

AD19

PS_1

AE17

PS_2

AE20

PS_3

AE6 AE5

AD2 AD4

AD13 AD11

AE16 AD16

AC1 AC3

RV110

C

QV3

2

B

MMST3904-7-F_SOT323-3

0.1U_0402_25V6-K

E

DIS@

3 1

1

2

JET@

VCC(B)

RV121 10K_0402_5%

@

1 2

RV122 10K_0402_5%

DIS@

1 2

8

7

1B

6

2B

4

GND

VCC(A)

1A

2A

DIR

RV120 10K_0402_5%

@

Please check if change Bit4 and 5 value to 1 o n PS2

Bits5

PS0

PS1

PS2

PS3

1

DIS@

1 2

0_0402_5%

SVI2_SVD_L

SVI2_SVC_L

+1.8VS_VGA

CV150

1

JET@

2

0.1U_0402_10V7-K

RV96 33_0402_5%JET@

RV97 33_0402_5%JET@

1 2

RV125 10K_0402_5%

DIS@

RV126 10K_0402_5%

@

H_THERMTRIP# 7,14

1 2

Bits4 Bits3 Bits2 Bits1

1

1 0 0 1

1 1 000

0 0 000

1 1 ???

SVI2_SVD

SVI2_SVC

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

2012/07/01

2

LC Future Center Secret Data

Deciphered Date

2014/07/01

Title

Topaz & Jet GPIO

Size Document Number Rev

Custom

Date: Sheet of

ACLU7

ACLU7ACLU7

Monday, December 16, 2013

1

18 65

1.A

1

2

3

4

5

TPV14

Change power rail from +1.5VS_VGA to +1.35VS_VGA

+1.35VS_VGA

LV3

DIS@

LV4

DIS@

LV5

DIS@

CV8

CV2

0.1U_0402_10V7-K

1

DIS@

2

CV3

10U_0603_6.3V6-M

2.2U_0402_6.3V6-K

1

DIS@

2

CV9

1U_0402_10V6-K

1

DIS@

2

CV10

1U_0402_10V6-K

1

DIS@

2

CV17

10U_0603_6.3V6-M

1

DIS@

2

CV20

10U_0603_6.3V6-M

1

DIS@

2

CV24

1U_0402_10V6-K

1

DIS@

2

+1.8VS_VGA

+3VS_VGA

+1.8VS_VGA

+0.95VS_VGA

CV1

.01U_0402_16V7-K

1

DIS@

2

1 2

BLM18PG221SN1D_2P

1 2

BLM18PG121SN1D_2P

1 2

BLM18PG121SN1D_2P

A A

B B

C C

CV154

DIS@

CV21

DIS@

CV25

DIS@

CV5

CV4

1

2

1

2

1

2

2.2U_0402_6.3V6-K

1

DIS@

2

CV156

10U_0603_6.3V6-M

1U_0402_10V6-K

1

DIS@

2

1U_0402_10V6-K

0.1U_0402_10V7-K

CV6

DIS@

2.2U_0402_6.3V6-K

1

2

CV7

DIS@

MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

2.2U_0402_6.3V6-K

1

2

90mA

75mA

100mA

UV3B

MEM I/O

H13

VMEMIO_1

H16

VMEMIO_2

H19

VMEMIO_3

J10

VMEMIO_4

J23

VMEMIO_5

J24

VMEMIO_6

J9

VMEMIO_7

K10

VMEMIO_8

K23

VMEMIO_9

K24

VMEMIO_10

K9

VMEMIO_11

L11

VMEMIO_12

L12

VMEMIO_13

L13

VMEMIO_14

L20

VMEMIO_15

L21

VMEMIO_16

L22

VMEMIO_17

LEVEL TRANSLATION

AA20

VDD_GPIO18_1

AA21

VDD_GPIO18_2

AB20

VDD_GPIO18_3

AB21

VDD_GPIO18_4

I/O

AA17

VDD_GPIO33_1

AA18

VDD_GPIO33_2

AB17

VDD_GPIO33_3

AB18

VDD_GPIO33_4

V12

NC_VDDR4_1

Y12

NC_VDDR4_2

U12

NC_VDDR4_3

PLL

L8

MPLL_PVDD

H7

SPLL_PVDD

H8

SPLL_VDDC

J7

SPLL_PVSS

216-0858020-A0_FCBGA631

PCIE_PVDD

PCIE

NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 NC_44 NC_45

PCIE_VDDC_1 PCIE_VDDC_2 PCIE_VDDC_3 PCIE_VDDC_4 PCIE_VDDC_5 PCIE_VDDC_6 PCIE_VDDC_7 PCIE_VDDC_8

PCIE_VDDC_9 PCIE_VDDC_10 PCIE_VDDC_11 PCIE_VDDC_12

CORE

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20

POWER

VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36

FB_VDDC

FB_GND_1

BIF_VDDC_1 BIF_VDDC_2

ISOLATED CORE I/O

VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4 VDDCI_5 VDDCI_6 VDDCI_7 VDDCI_8

FB_VDDCI

FB_GND_2

VDDC_SEN51

VDDC_RTN51

VDDC_SEN

VDDC_RTN

Test_Point_32MIL

1

AM30

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11 AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13

AC20 AD20

R21 U21

M13 M15 M16 M17 M18 M20 M21 N20

W1 W3

CV29

DIS@

CV37

DIS@

CV51

DIS@

Only available on TOPAZ, NC balls on JET

TOPAZ_VDDC_SEN TOPAZ_VDDC_RTN

CV59

10U_0603_6.3V6-M

1

DIS@

2

FOR JET,PUT VIAS UNDER ASIC

1 2

RV1 0_0402_5%JET@

1 2

RV2 0_0402_5%JET@

CV60

CV31

1U_0402_10V6-K

1

DIS@

2

CV39

CV38

CV52

1

DIS@

2

2.2U_0402_6.3V6-K

1

DIS@

2

CV53

2.2U_0402_6.3V6-K

1

DIS@

2

CV61

10U_0603_6.3V6-M

1U_0402_10V6-K

1

DIS@

2

10U_0603_6.3V6-M

1

2

2.2U_0402_6.3V6-K

1

2

2.2U_0402_6.3V6-K

1

2

CV62

DIS@

CV32

DIS@

CV40

DIS@

CV54

DIS@

1U_0402_10V6-K

1

2

1U_0402_10V6-K

1

2

2.2U_0402_6.3V6-K

1

2

2.2U_0402_6.3V6-K

1

2

CV63

DIS@

+VGA_CORE

CV26

10U_0603_6.3V6-M

1

DIS@

2

CV33

1U_0402_10V6-K

1

DIS@

2

CV41

2.2U_0402_6.3V6-K

1

DIS@

2

CV55

2.2U_0402_6.3V6-K

1

DIS@

2

CV64

1U_0402_10V6-K

1

DIS@

2

CV27

1U_0402_10V6-K

1

DIS@

2

CV34

1U_0402_10V6-K

1

DIS@

2

CV42

2.2U_0402_6.3V6-K

1

DIS@

2

CV56

2.2U_0402_6.3V6-K

1

@

2

+0.95VS_VGA

0.1U_0402_10V7-K

1

2

CV35

DIS@

CV43

DIS@

CV57

@

+VGA_CORE

CV65

0.1U_0402_10V7-K

1

DIS@

2

+1.8VS_VGA

1U_0402_10V6-K

1

2

2.2U_0402_6.3V6-K

1

2

2.2U_0402_6.3V6-K

1

2

CV36

CV44

CV58

+0.95VS_VGA

1U_0402_10V6-K

1

DIS@

2

+VGA_CORE

CV48

CV49

CV50

10U_0603_6.3V6-M

1

DIS@

2

10U_0603_6.3V6-M

1

DIS@

@

2

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

1

DIS@

2

2.2U_0402_6.3V6-K

1

@

2

CV22

1U_0402_10V6-K

1

DIS@

2

10U_0603_6.3V6-M

1

DIS@

2

CV47

CV46

CV45

TOPAZ@

D D

1

2

VDDC_SEN

VDDC_RTN

1 2

RV3 0_0402_5%

TOPAZ@

1 2

RV4 0_0402_5%

3

TOPAZ_VDDC_SEN

TOPAZ_VDDC_RTN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

Topaz & Jet Core Power

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

19 65

1.A

5

4

3

2

1

UV3C

DP POWER

AG15

NC_DP_VDDR_1

AG16

NC_DP_VDDR_2

AF16

NC_DP_VDDR_3

D D

+1.8VS_VGA

+0.95VS_VGA

C C

ASIC Ball

U10,T10 AB13,W9 AB11,AB12 AC11,AC13 AC14,Y9,W10

AC20

AD20

W1

B B

W3

AJ11

AK12

AL11

N6

N5

N3

AJ27

T8

AA3

AA1

CV66

CV67

10U_0603_6.3V6-M

1U_0402_10V6-K

1

DIS@

2

CV71

CV70

0.1U_0402_10V7-K

1U_0402_10V6-K

1

DIS@

2

Topaz Jet JetTopazASIC Ball

VDDC

FB_VDDC

FB_VDDCI N C

GPIO_SVC

GPIO_SVD

GPIO_SVT

GPIO_11

GPIO_13

WAKEB NC_VS YNC

PCC/GPIO_6

PLL_ANALOG_OUT NC

PLL_ANALOG_IN

NC

NCFB_VSS

NC_SVI2

NC_GPIO11

NC_GPIO12GP IO_12

NC_GPIO13

GPIO_6

NC

AG17

NC_DP_VDDR_4

AG18

NC_DP_VDDR_5

AG19

NC_DP_VDDR_6

AF14

DP_VDDR

AG20

NC_DP_VDDC_1

AG21

NC_DP_VDDC_2

AF22

NC_DP_VDDC_3

AG22

NC_DP_VDDC_4

AD14

DP_VDDC

AG14

NC_DP_VSSR_1

AH14

NC_DP_VSSR_2

AM14

NC_DP_VSSR_3

AM16

NC_DP_VSSR_4

AM18

NC_DP_VSSR_5

AF23

NC_DP_VSSR_6

AG23

NC_DP_VSSR_7

AM20

NC_DP_VSSR_8

AM22

NC_DP_VSSR_9

AM24

NC_DP_VSSR_10

AF19

NC_DP_VSSR_11

AF20

NC_DP_VSSR_12

AE14

DP_VSSR

AF17

NC_UPHYAB_DP_CALR

216-0858020-A0_FCBGA631

U1

U3 BP_1 NC

Y11 NC DBG _DATA13

AE9 NC DBG _DATA14

L9

N9

AE8

AL9

H13,H16,H19,J10 J23,J24,J9,K10 K23,K24,K9,L11 L12,L13,L20,L21 L22

AA17,AA18 AB17,AB18

AA20,AA21 AB20,AB21

NC/DP POWER

NC_50 NC_51 NC_52 NC_53 NC_54 NC_55

NC_56 NC_57 NC_58 NC_59

NC_60 NC_61 NC_62 NC_63 NC_64 NC_65 NC_66 NC_67 NC_68 NC_69 NC_70 NC_71

NC_72

VMEMIO

VDD_GPIO33

AE11 AF11 AE13 AF13 AG8 AG10

AF6 AF7 AF8 AF9

AE1 AE3 AG1 AG6 AH5 AF10 AG9 AH8 AM6 AM8 AG7 AG11

AE10

NCBP_0

NCDIECRACKMONAM26

DBG_DATA15NC

DBG_DATA16NC

DBG_DATA12NC

DBG_CNTL0NC

VDDR1

VDDR3

VDD_CTVDD_GPIO18

UV3D

NC_UPHYAB_TMDPA_TX0N NC_UPHYAB_TMDPA_TX0P

NC_UPHYAB_TMDPA_TX1N NC_UPHYAB_TMDPA_TX1P

NC_UPHYAB_TMDPA_TX2N NC_UPHYAB_TMDPA_TX2P

NC_UPHYAB_TMDPA_TX3N NC_UPHYAB_TMDPA_TX3P

NC_TXOUT_L3P

NC_TXOUT_L3N

NC_TMDP

NC_UPHYAB_TMDPB_TX0N NC_UPHYAB_TMDPB_TX0P

NC_UPHYAB_TMDPB_TX1N NC_UPHYAB_TMDPB_TX1P

NC_UPHYAB_TMDPB_TX2N NC_UPHYAB_TMDPB_TX2P

NC_UPHYAB_TMDPB_TX3N NC_UPHYAB_TMDPB_TX3P

NC_TXOUT_U3P NC_TXOUT_U3N

216-0858020-A0_FCBGA631

AL15 AK14

AH16 AJ15

AL17 AK16

AH18 AJ17

AL19 AK18

AH20 AJ19

AL21 AK20

AH22 AJ21

AL23 AK22

AK24 AJ23

UV3E

AA27

GND_1

AB24

GND_2

AB32

GND_3

AC24

GND_4

AC26

GND_5

AC27

GND_6

AD25

GND_7

AD32

GND_8

AE27

GND_9

AF32

GND_10

AG27

GND_11

AH32

GND_12

K28

GND_13

K32

GND_14

L27

GND_15

M32

GND_16

N25

GND_17

N27

GND_18

P25

GND_19

P32

GND_20

R27

GND_21

T25

GND_22

T32

GND_23

U25

GND_24

U27

GND_25

V32

GND_26

W25

GND_27

W26

GND_28

W27

GND_29

Y25

GND_30

Y32

GND_31

M6

GND_32

N13

GND_33

N16

GND_34

N18

GND_35

N21

GND_36

P6

GND_37

P9

GND_38

R12

GND_39

R15

GND_40

R17

GND_41

R20

GND_42

T13

GND_43

T16

GND_44

T18

GND_45

T21

GND_46

T6

GND_47

U15

GND_48

U17

GND_49

U20

GND_50

U9

GND_51

V13

GND_52

V16

GND_53

V18

GND_54

Y10

GND_55

Y15

GND_56

Y17

GND_57

Y20

GND_58

R11

GND_59

T11

GND_60

AA11

GND_61

M12

GND_62

N11

GND_63

V11

GND_64

216-0858020-A0_FCBGA631

GND

GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98

GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119

VSS_MECH_1 VSS_MECH_2 VSS_MECH_3

A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6

A32 AM1 AM32

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

Topaz & Jet DP Power/GND

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

1

20 65

1.A

1

2

3

4

5

FBA_MA[15..0] 22,23

+1.35VS_VGA

DIS@

FBA_BA[2..0] 22,23

Change power rail from +1.5VS_VGA to +1.35VS_VGA

12

RV7

40.2_0402_1%

DIS@

CV73

1U_0402_10V6-K

RV10

1 2

10_0402_5%

4.99K_0402_1%

DIS@

1

DIS@

2

RV11

DIS@

1 2

1

2

RV8 100_0402_1%

12

+1.35VS_VGA

12

DIS@

1 2

1

CV75 68P_0402_50V8-J

@

2

RV5

40.2_0402_1%

DIS@

RV6 100_0402_1%

CV72

1

DIS@

2

CV76

@

1U_0402_10V6-K

0.1U_0402_25V6-K

1

2

12

RV12

51.1_0402_1%

@

1 2

RV14 120_0402_1%DIS@

1

TPV15 Test_Point_32MIL

1

TPV16 Test_Point_32MIL

0.1U_0402_25V6-K

CV77

1

@

2

12

RV13

51.1_0402_1%

@

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

A A

B B

C C

FBA_DQS[7..0]22,23

FBA_DQM[7..0]22,23

FBA_DQS#[7..0]22,23

FBA_D[0..63]22,23

Change power rail from +1.5VS_VGA to +1.35VS_VGA

FBA_RST#

FBA_D[0..63]

1 2

51.1_0402_1%

CV74 120P_0402_50V8-J

DIS@

RV9

UV3F

GDDR5/DDR3

K27

DQA0_0

J29

DQA0_1

H30

DQA0_2

H32

DQA0_3

G29

DQA0_4

F28

DQA0_5

F32

DQA0_6

F30

DQA0_7

C30

DQA0_8

F27

DQA0_9

A28

DQA0_10

C28

DQA0_11

E27

DQA0_12

G26

DQA0_13

D26

DQA0_14

F25

DQA0_15

A25

DQA0_16

C25

DQA0_17

E25

DQA0_18

D24

DQA0_19

E23

DQA0_20

F23

DQA0_21

D22

DQA0_22

F21

DQA0_23

E21

DQA0_24

D20

DQA0_25

F19

DQA0_26

A19

DQA0_27

D18

DQA0_28

F17

DQA0_29

A17

DQA0_30

C17

DQA0_31

E17

DQA1_0

D16

DQA1_1

F15

DQA1_2

A15

DQA1_3

D14

DQA1_4

F13

DQA1_5

A13

DQA1_6

C13

DQA1_7

E11

DQA1_8

A11

DQA1_9

C11

DQA1_10

F11

DQA1_11

A9

DQA1_12

C9

DQA1_13

F9

DQA1_14

D8

DQA1_15

E7

DQA1_16

A7

DQA1_17

C7

DQA1_18

F7

DQA1_19

A5

DQA1_20

E5

DQA1_21

C3

DQA1_22

E1

DQA1_23

G7

DQA1_24

G6

DQA1_25

G1

DQA1_26

G3

DQA1_27

J6

DQA1_28

J1

DQA1_29

J3

DQA1_30

J5

DQA1_31

K26

MVREFDA_1

J26

MVREFSA_2

J25

NC_120

K25

MEM_CALRP0

L10

DRAM_RST

K8

CLKTESTA

L7

CLKTESTB

216-0858020-A0_FCBGA631

GDDR5/DDR3

K17

MAA0_0 MAA0_1 MAA0_2 MAA0_3 MAA0_4 MAA0_5 MAA0_6 MAA0_7 MAA0_8 MAA0_9

MAA1_0 MAA1_1 MAA1_2 MAA1_3 MAA1_4 MAA1_5 MAA1_6 MAA1_7 MAA1_8 MAA1_9

WCKA0_0

WCKA0B_0

MEMORY INTERFACE

WCKA0_1

WCKA0B_1

WCKA1_0

WCKA1B_0

WCKA1_1

WCKA1B_1

EDCA0_0 EDCA0_1 EDCA0_2 EDCA0_3 EDCA1_0 EDCA1_1 EDCA1_2 EDCA1_3

DDBIA0_0 DDBIA0_1 DDBIA0_2 DDBIA0_3 DDBIA1_0 DDBIA1_1 DDBIA1_2 DDBIA1_3

ADBIA0 ADBIA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

FBA_MA0

J20

FBA_MA1

H23

FBA_MA2

G23

FBA_MA3

G24

FBA_MA4

H24

FBA_MA5

J19

FBA_MA6

K19

FBA_MA7

G20

FBA_MA13

L17

FBA_MA15

J14

FBA_MA8

K14

FBA_MA9

J11

FBA_MA10

J13

FBA_MA11

H11

FBA_MA12

G11

FBA_BA2

J16

FBA_BA0

L15

FBA_BA1

G14

FBA_MA14

L16

E32

FBA_DQM0

E30

FBA_DQM1

A21

FBA_DQM2

C21

FBA_DQM3

E13

FBA_DQM4

D12

FBA_DQM5

E3

FBA_DQM6

F4

FBA_DQM7

H28

FBA_DQS0

C27

FBA_DQS1

A23

FBA_DQS2

E19

FBA_DQS3

E15

FBA_DQS4

D10

FBA_DQS5

D6

FBA_DQS6

G5

FBA_DQS7

H27

FBA_DQS#0

A27

FBA_DQS#1

C23

FBA_DQS#2

C19

FBA_DQS#3

C15

FBA_DQS#4

E9

FBA_DQS#5

C5

FBA_DQS#6

H4

FBA_DQS#7

L18

FBA_ODTA0

K16

FBA_ODTA1

H26

FBA_CLKA0

H25

FBA_CLKA0#

G9

FBA_CLKA1

H9

FBA_CLKA1#

G22

FBA_RASA0#

G17

FBA_RASA1#

G19

FBA_CASA0#

G16

FBA_CASA1#

H22

FBA_CSA0#

J22

G13

FBA_CSA1#

K13

K20

FBA_CKEA0

J17

FBA_CKEA1

G25

FBA_WEA0#

H10

FBA_WEA1#

FBA_ODTA0 22 FBA_ODTA1 23

FBA_CLKA0 22 FBA_CLKA0# 22

FBA_CLKA1 23 FBA_CLKA1# 23

FBA_RASA0# 22 FBA_RASA1# 23

FBA_CASA0# 22 FBA_CASA1# 23

FBA_CSA0# 22

FBA_CSA1# 23

FBA_CKEA0 22 FBA_CKEA1 23

FBA_WEA0# 22 FBA_WEA1# 23FBA_RST#22,23

D D

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

Topaz & Jet MEM Interface

Size Document Number Rev

C

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

21 65

1.A

1

2

3

4

5

Memory Partition A - Lower 32 bits

UV5

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLKA0 FBA_CLKA0# FBA_CKEA0

FBA_ODTA0 FBA_CSA0# FBA_RASA0# FBA_CASA0# FBA_WEA0#

FBA_DQS0 FBA_DQS3

FBA_DQM0 FBA_DQM3

FBA_DQS#0 FBA_DQS#3

FBA_MA15

CV82

1U_0402_10V6-K

1

DIS@

2

CV87

0.1U_0402_10V7-K

1

DIS@

2

M8

H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M2

N8

M3

J7 K7 K9

K1 L2

J3 K3 L3

F3 C7

E7 D3

G3

B7

T2

L8

J1 L1

J9 L9

M7

K4W4G1646B-HC11_FBGA96

DIS@

CV83

1U_0402_10V6-K

1

DIS@

2

CV88

0.1U_0402_10V7-K

1

DIS@

2

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ

NC1 NC2 NC3 NC4 NC5

96-BALL SDRAM DDR3

+FBA_VREFC0_U

A A

B B

FBA_RST#21,23

12

RV15 10K_0402_5%

@

C C

+1.35VS_VGA +1.35VS_VGA

CV78

10U_0603_6.3V6-M

1

DIS@

2

+1.35VS_VGA +1.35VS_VGA

+FBA_VREFD0_U

FBA_CLKA021 FBA_CLKA0#21 FBA_CKEA021

FBA_ODTA021 FBA_CSA0#21 FBA_RASA0#21 FBA_CASA0#21 FBA_WEA0#21

FBA_RST#

12

RV16 243_0402_1%

DIS@

UV6 SIDE UV7 SIDE

CV80

CV79

DIS@

CV84

DIS@

CV81

1U_0402_10V6-K

1

2

1

2

1

DIS@

2

UV6 SIDE UV7 SIDE

CV85

CV86

0.1U_0402_10V7-K

1

DIS@

2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

FBA_D1 FBA_D6 FBA_D2 FBA_D7 FBA_D0 FBA_D5 FBA_D3 FBA_D4

FBA_D31 FBA_D27 FBA_D30 FBA_D25 FBA_D28 FBA_D24 FBA_D29 FBA_D26

+1.35VS_VGA

Group0 (IN3)

VRAM SWAP on 20130930

Group3 (BOT)

CV89

CV90

10U_0603_6.3V6-M

1

DIS@

2

CV95

DIS@

CV92

CV91

1U_0402_10V6-K

1

DIS@

2

CV96

CV97

0.1U_0402_10V7-K

1

DIS@

2

RV17 243_0402_1%

DIS@

CV94

CV93

DIS@

CV98

DIS@

1U_0402_10V6-K

1

DIS@

2

CV99

0.1U_0402_10V7-K

1

DIS@

2

1U_0402_10V6-K

1

DIS@

2

0.1U_0402_10V7-K

1

DIS@

2

+FBA_VREFC0_L +FBA_VREFD0_L

12

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLKA0 FBA_CLKA0# FBA_CKEA0

FBA_ODTA0 FBA_CSA0# FBA_RASA0# FBA_CASA0# FBA_WEA0#

FBA_DQS2 FBA_DQS1

FBA_DQM2 FBA_DQM1

FBA_DQS#2 FBA_DQS#1

FBA_RST#

FBA_MA15

UV6

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC1

L1

NC2

J9

NC3

L9

NC4

M7

NC5

96-BALL SDRAM DDR3

K4W4G1646B-HC11_FBGA96

DIS@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

FBA_D19 FBA_D16 FBA_D23 FBA_D21 FBA_D22 FBA_D18 FBA_D20 FBA_D17

FBA_D9 FBA_D10 FBA_D13 FBA_D12 FBA_D8 FBA_D14 FBA_D15 FBA_D11

+1.35VS_VGA

Group2 (IN1)

VRAM SWAP on 20130930

Group1 (TOP)

FBA_MA[15..0] 21,23

FBA_BA[2..0] 21,23

FBA_DQS[7..0] 21,23

FBA_DQM[7..0] 21,23

FBA_DQS#[7..0] 21,23

FBA_D[0..63] 21,23

+1.35VS_VGA

12

RV18

4.99K_0402_1%

DIS@

CV100

12

RV19

4.99K_0402_1%

DIS@

RV22

4.99K_0402_1%

@

RV23

4.99K_0402_1%

@

12

CV102

12

FBA_CLKA0

FBA_CLKA0#

DIS@

@

+FBA_VREFC0_U

0.1U_0402_10V7-K

1

2

0.1U_0402_10V7-K

1

2

RV26

40.2_0402_1%

DIS@

RV27

40.2_0402_1%

DIS@

1 2

RV78 0_0402_5%

DIS@

12

+1.35VS_VGA

RV20

4.99K_0402_1%

DIS@

RV21

4.99K_0402_1%

DIS@

+1.35VS_VGA+1.35VS_VGA

RV24

4.99K_0402_1%

@

RV25

4.99K_0402_1%

@

CV104

DIS@

1 2

.01U_0402_16V7-K

12

+FBA_VREFC0_L

CV101

0.1U_0402_10V7-K

12

1

DIS@

2

RV98

0_0402_5%

DIS@

1 2

12

+FBA_VREFD0_L+FBA_VREFD0_U

0.1U_0402_10V7-K

12

CV103

1

@

2

D D

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

Topaz & Jet DDR3 VRAM U

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

22 65

1.A

1

2

3

4

5

Memory Partition A - Upper 32 bits

UV7

+FBA_VREFC1_U

A A

FBA_CLKA121 FBA_CLKA1#21 FBA_CKEA121

FBA_ODTA121 FBA_CSA1#21 FBA_RASA1#21 FBA_CASA1#21

B B

C C

FBA_WEA1#21

FBA_RST#21,22

RV28 243_0402_1%

DIS@

+1.35VS_VGA +1.35VS_VGA

+FBA_VREFD1_U +FBA_VREFC1_L

12

CV106

CV105

10U_0603_6.3V6-M

1U_0402_10V6-K

1

DIS@

2

M8

VREFCA

H1

VREFDQ

N3

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLKA1 FBA_CLKA1# FBA_CKEA1

FBA_ODTA1 FBA_CSA1# FBA_RASA1# FBA_CASA1# FBA_WEA1#

FBA_DQS4 FBA_DQS5

FBA_DQM4 FBA_DQM5

FBA_DQS#4 FBA_DQS#5

FBA_RST#

FBA_MA15

CV107

1

DIS@

2

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC1

L1

NC2

J9

NC3

L9

NC4

M7

NC5

96-BALL SDRAM DDR3

K4W4G1646B-HC11_FBGA96

DIS@

UV8 SIDE UV9 SIDE

CV108

1U_0402_10V6-K

DIS@

CV110

CV109

1U_0402_10V6-K

1

DIS@

2

E3

FBA_D38

DQL0

F7

FBA_D35

DQL1

F2

FBA_D37

DQL2

F8

FBA_D32

DQL3

H3

FBA_D36

DQL4

H8

FBA_D34

DQL5

G2

FBA_D39 FBA_D62

DQL6

H7

FBA_D33

DQL7

D7

FBA_D40

DQU0

C3

FBA_D45

DQU1

C8

FBA_D43

DQU2

C2

FBA_D44

DQU3

A7

FBA_D42

DQU4

A2

FBA_D46

DQU5

B8

FBA_D41

DQU6

A3

FBA_D47

DQU7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

1U_0402_10V6-K

1

2

+1.35VS_VGA

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group4 (IN1)

Group5 (TOP)

VRAM SWAP on 20130930

CV117

CV116

10U_0603_6.3V6-M

1

DIS@

2

RV29 243_0402_1%

DIS@

CV118

1U_0402_10V6-K

1

DIS@

2

CV120

CV119

1U_0402_10V6-K

1

DIS@

2

CV121

1U_0402_10V6-K

1

2

1U_0402_10V6-K

1

DIS@

2

12

+FBA_VREFD1_L

FBA_MA0 FBA_MA1 FBA_MA2 FBA_MA3 FBA_MA4 FBA_MA5 FBA_MA6 FBA_MA7 FBA_MA8 FBA_MA9 FBA_MA10 FBA_MA11 FBA_MA12 FBA_MA13 FBA_MA14

FBA_BA0 FBA_BA1 FBA_BA2

FBA_CLKA1 FBA_CLKA1# FBA_CKEA1

FBA_ODTA1 FBA_CSA1# FBA_RASA1# FBA_CASA1# FBA_WEA1#

FBA_DQS7 FBA_DQS6

FBA_DQM7 FBA_DQM6

FBA_DQS#7 FBA_DQS#6

FBA_RST#

FBA_MA15

UV8

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC1

L1

NC2

J9

NC3

L9

NC4

M7

NC5

96-BALL SDRAM DDR3

K4W4G1646B-HC11_FBGA96

DIS@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

VRAM SWAP on 20130930

E3

FBA_D56

F7

FBA_D59

F2

FBA_D57

F8

FBA_D61

H3

FBA_D60

H8 G2

FBA_D63

H7

FBA_D58

D7

FBA_D55

C3

FBA_D51

C8

FBA_D54

C2

FBA_D48

A7

FBA_D52

A2

FBA_D50

B8

FBA_D53

A3

FBA_D49

+1.35VS_VGA

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Group7 (IN3)

Group6 (BOT)

RV30

4.99K_0402_1%

DIS@

RV31

4.99K_0402_1%

DIS@

RV34

4.99K_0402_1%

@

RV35

4.99K_0402_1%

@

FBA_MA[15..0] 21,22

FBA_BA[2..0] 21,22

FBA_DQS[7..0] 21,22

FBA_DQM[7..0] 21,22

FBA_DQS#[7..0] 21,22

FBA_D[0..63] 21,22

+1.35VS_VGA

12

+FBA_VREFC1_U

0.1U_0402_10V7-K

12

CV127

1

DIS@

2

RV102 0_0402_5%

DIS@

1 2

12

+FBA_VREFD1_U +FBA_VREFD1_L

0.1U_0402_10V7-K

12

CV129

1

@

2

FBA_CLKA1

12

RV38

40.2_0402_1%

FBA_CLKA1#

DIS@

RV39

40.2_0402_1%

DIS@

CV131

1 2

.01U_0402_16V7-K

12

RV32

4.99K_0402_1%

DIS@

RV33

4.99K_0402_1%

DIS@

RV36

4.99K_0402_1%

@

RV37

4.99K_0402_1%

@

DIS@

+1.35VS_VGA

+1.35VS_VGA+1.35VS_VGA

12

+FBA_VREFC1_L

CV128

0.1U_0402_10V7-K

12

1

DIS@

2

RV105 0_0402_5%

DIS@

1 2

12

CV130

0.1U_0402_10V7-K

12

1

@

2

+1.35VS_VGA +1.35VS_VGA

D D

1

UV8 SIDE UV9 SIDE

CV111

DIS@

CV113

CV112

0.1U_0402_10V7-K

1

DIS@

2

CV114

CV115

0.1U_0402_10V7-K

1

2

0.1U_0402_10V7-K

1

DIS@

2

0.1U_0402_10V7-K

1

DIS@

2

CV122

DIS@

CV123

0.1U_0402_10V7-K

1

DIS@

2

CV125

CV124

0.1U_0402_10V7-K

1

DIS@

2

CV126

0.1U_0402_10V7-K

1

2

0.1U_0402_10V7-K

1

DIS@

2

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

Topaz & Jet DDR3 VRAM L

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

23 65

1.A

1

2

3

4

5

A A

B B

+0.95VS to +0.95VS_VGA

+/- 1.5%

CV181

10U_0805_25V6K

DIS@

AON6414AL VDS=30V VGS=20V, ID=50A, Rds=8mohm @ VGS=10V VGS(th)=2.5V Max

+0.95VS

QV47 AON6414AL_DFN8-5

1

2

5

Reserve for GPU/APU share +0.95V

DIS@

+0.95VS_VGA

1 2 3

4

10U_0603_6.3V6M

DIS@

1 2

RV85 0_0402_5%

1

CV180

0.1U_0402_16V4Z

DIS@

2

+/- 3% 2A

1

CV174

2

DIS@

12

RV209 120K_0402_5%

DIS@

1

CV182

2

@

10U_0603_6.3V6M

13

D

QV37

S

2N7002KW_SOT323-3

DIS@

1

CV183 1U_0603_25V6M

2

DIS@

RV210

12

100K_0402_5%

2

G

DGPU_PWREN#

AON4304 VDS=30V VGS=20V, ID=18A, Rds=6mohm @ VGS=10V VGS(th)=2.4V Max

7m OHM is requr ied ???

+VSB

+1.35VP TO +1.35VS_VGA

+VSB

DGPU_PWREN#

DIS@

1 2

180K_0402_1%

RV113

2

10U_0603_6.3V6M

G

DIS@

Add 1.35VP to _+1.35VS_VGA on 20130925, RDS on less than 8,need to check, 4A for totally

+1.35VP +1.35VS_VGA

Need OPEN

CV209

CV208

1

2

DIS@

10U_0603_6.3V6M

13

D

QV11

S

2N7002KW_SOT323-3

JV5

12

RV127 120K_0402_5%

DIS@

5

112

JUMP_43X118

AON6414AL_DFN8-5

QV9

4

1

CV213

0.1U_0402_16V4Z

DIS@

2

DIS@

@

CV214

1

330U_D2_2V_Y

2 3

CV210

1

+

@

2

DIS@

10U_0603_6.3V6M

CV212

CV211

1

2

@

.1U_0402_16V7K

DIS@

10U_0603_6.3V6M

12

RV114 470_0603_5%

@

13

D

QV10

G

S

2N7002KW_SOT323-3

@

2

DGPU_PWREN#

Check if QV46 need to replaced by LP2301ALT1G_SOT23-3 .

+1.8VS to +1.8VS_VGA

+/- 2%

AON6414AL VDS=30V VGS=20V, ID=50A, Rds=8mohm @ VGS=10V VGS(th)=2.5V Max

C C

+1.8VS

QV48 AON6414AL_DFN8-5

5

Reserve for GPU/APU share +1.8V

DIS@

+1.8VS_VGA

1 2 3

4

10U_0603_6.3V6M

DIS@

1 2

RV117 0_0402_5%

1

CV161

0.1U_0402_16V4Z

DIS@

2

+/- 3% 0.5A

1

CV170

@

2

12

RV197 120K_0402_5%

DIS@

1

2

13

D

QV36

S

2N7002KW_SOT323-3

DIS@

36m OHM is requ ried

CV163 1U_0603_25V6M

@

DIS@

12

RV198 100K_0402_5%

2

G

+VSB

DGPU_PWREN#

+3VS to +3VS_VGA

+5VALW

1 2

RV59

DIS@

20K_0402_5%

DGPU_PWREN12,17,51

DGPU_PWREN

DGPU_PWREN#

2

G

DIS@

Need OPEN

+3VS +3VS_VGA

JV1

JUMP_43X39

S

QV6

LP2301ALT1G_SOT23-3

1 2

RV100

DIS@

20K_0402_5%

13

D

QV8

S

2N7002KW_SOT323-3

112

D

13

G

2

1

CV147

0.1U_0402_16V4Z

DIS@

2

DIS@

2

@

1

CV162

@

2

4.7U_0603_6.3V6-K

12

RV116 470_0603_5%

@

13

D

QV12

G

S

2N7002KW_SOT323-3

@

2

DGPU_PWREN#

GPU Power Discharger

12

RV172

@

150_0603_5%

13

D

QV32

2

D D

G

S

2N7002KW_SOT323-3@

DGPU_PWREN# DGPU_PWREN#DGPU_PWREN#

reserve RV167 change to 10 ohm to meet power off sequence on 1202

1

+0.95VS_VGA +VGA_CORE+1.8VS_VGA

12

RV168 470_0603_5%

@

13

D

QV5

2

G

S

2N7002KW_SOT323-3@

2

12

RV167 10_0603_5%

@

13

D

QV19

2

G

S

2N7002KW_SOT323-3@

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

Topaz & Jet SWITCH POWER

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

24 65

1.A

5

D D

C C

4

3

2

1

BLANK

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/12/05

LC Future Center Secret Data

Deciphered Date

2

2014/12/05

Title

Topaz & Jet BLANK

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

1

25 65

0.4

ZZZ1

PCB_MB

5

Kaveri CPU PN

UC1

4

UL1

A4@

100M@

TL1

100M@

3

2

1

PCB NM-A291

DA60000UD00

D D

C C

Kaveri A4(17W)

SA000063G00

RTL8106EUL-CG

SA000060Q00

LAN chip

TST1284A LF

SP050008C00

Transformer

B B

Board ID

BOARD_ID000BOARD_ID1

*

A A

00

01 1

BOARD_ID3BOARD_ID2

0 0

111

0

5

01

0011

0

10

Description

BDW + Jet-LE sku

BDW + Topaz-XT sku0 0

BDW + N15V-GM sku10 00

BDW + N15S-GT sku10 01

HSW + Jet-LE sku001 0

HSW + Topaz-XT sku0101

HSW + N15V-GM sku

HSW + N15S-GT sku

BDW + UMA sku

HSW + UMA sku

Stuff Resistor

RC107,RC108,RC109,RC123

RC107,RC108,RC102,RC123

RC107,RC101,RC109,RC123

RC107,RC101,RC102,RC123

RC100,RC108,RC109,RC123

RC100,RC108,RC102,RC123

RC100,RC101,RC109,RC123

RC100,RC101,RC102,RC123

RC107,RC108,RC109,RC121

RC100,RC108,RC109,RC121

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2013/08/05

LC Future Center Secret Data

Deciphered Date

2

2013/08/05

Title

Virtual Symbol

Size Document Number Rev

C

Date: Sheet of

ACLU7

ACLU7ACLU7

Monday, December 16, 2013

26 52

1

26 52

0.1

5

4

3

2

1

+3VS

2

G

R13

4.7K_0402_5%

1 2

LCD_ENVDD

13

D

Q17 2N7002KW_SOT323-3

SB00000YY00

S

1

C1 1U_0402_6.3V6-K

2

B+

LED POWER

R47 0_0805_5%

D D

From PCH

APU_ENVDD7

APU_ENVDD

R8 100K_0402_5%

1 2

R9 100K_0402_5%

R7

1 2

2.2K_0402_5%

MMST3904-7-F_SOT323-3

1 2

C

2

B

E

3 1

Q2

LCD POWER CIRCUIT

U7

OUT

IN2

GND

IN14EN

G5243AT11U_SOT23-5

SA00005XJ00

1

2

3

+LCDVDD_CON

LCD_ENVDD

1

C8

4.7U_0805_25V6-K

2

5

1 2

4.7U_0603_6.3V6-K

+LEDVDD

+LCDVDD_CON+3VS

2A 80 mil2A 80 mil

1

2

+LEDVDD

C2

CMOS Camera

CMOS_ON#13

+3VS

W=40 mils W=40mils

R6

@

1 2

100K_0402_5%

1 2

R82 0_0805_5%

Q23

@

AO3413_SOT23-3

D

S

13

G

2

1

@

C4

0.1U_0402_10V7-K

2

+3VS_CMOS

1

2

C6

@

0.1U_0402_10V7-K

Follow CRB and Edge schematic to enable LCD_ENVDD

D

13

C25

0.1U_0402_10V7-K

@

+3VS_TS

Touch Screen

1

2

680P_0402_50V7K

1 2

C C

+3VALW

EC_TS_ON#38

+3VS

1 2

R22 0_0402_5%TS@

1 2

R24 0_0402_5%@

R19

1 2

TS@

100K_0402_5%

R48 0_0402_5%@

LP2301ALT1G_SOT23-3

Q5 TS@

2

C23

0.1U_0402_10V7-K

1

TS@

S

G

2

Touch Screen reserved

TS_RS

+3VS_TS

JTS1

@

1

2

3

4

5

GND1

6

GND2

ACES_87213-00601-P01

Touch Screen

7 8

+3VS_TS

1 2 1 2

12

USB20_N8_CONN USB20_P8_CONN

R69 10K_0402_5%@

USB20_N814

B B

USB20_P814

R20 0_0402_5%TS@ R21 0_0402_5%TS@

+3VS

C22

@

eDP Conn

1

2

+LEDVDD

W=80mils

1 2

APU_EDP_TX0+7 APU_EDP_TX0-7

APU_EDP_TX1+7 APU_EDP_TX1-7

APU_EDP_AUX7 APU_EDP_AUX#7

APU_EDP_PWM7

APU_EDP_HPD7

DMIC_DATA34

DMIC_CLK34

USB20_P514 USB20_N514

APU_BKOFF#7

EC_BKOFF#38

R10 100K_0402_5%

C17 0.1U_0402_10V7-K

1 2

C18 0.1U_0402_10V7-K

1 2

C16 0.1U_0402_10V7-K

1 2

C19 0.1U_0402_10V7-K

1 2

C20 0.1U_0402_10V7-K

1 2

C21 0.1U_0402_10V7-K

1 2

R148 100K_0402_5%

1 2

R18 0_0402_5%@

+LCDVDD_CON

+3VS

1 2

R183 0_0402_5%

1 2

R186 0_0402_5%

+3VS_CMOS

@

1 2

R11 0_0402_5%

1 2

R12 0_0402_5%

1 2

add Pull down R14 100k on EC_BKOFF#

W=60mils

W=40mils

EDP_TX0+ EDP_TX0-

EDP_TX1+ EDP_TX1-

EDP_AUX EDP_AUX#

DISPOFF#

APU_EDP_PWM

USB20_P5_CONN USB20_N5_CONN

DISPOFF#

JEDP1

ME@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

G1

27

G2

28

G3

29

G4

30

G5

ACES_50406-03071-001

31 32 33 34 35

USB20_P5_CONN

+3VS_TS

USB20_N5_CONN

1

@

D2

1

2

A A

5

AZ5215-01F_DFN1006P2E2

3

2

1

D1 AZC199-02S.R7G_SOT23-3

@

4

USB20_N8 USB20_P5_CONN

L17

4

1

@

WCM2012F2S-900T04_0805

3

2

3

USB20_N8_CONN

2

USB20_P8_CONNUSB20_P8

EMI request

USB20_P5

USB20_N5

3

L18

1

4

WCM2012F2S-900T04_0805@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

2

3

2

3

USB20_N5_CONN

2013/08/08

DMIC_CLK DISPOFF#

C11

1

2

@

100P_0402_50V8J

LC Future Center Secret Data

Deciphered Date

2

C12

1

2

@

2013/08/05

470P_0402_50V7K

+3VS_CMOS

2

C24

0.047U_0402_16V7K

Title

eDP/ CMOS/Touch screen

Size Document Number Rev

C

Monday, December 16, 2013

Date: Sheet of

1

ACLU7

ACLU7ACLU7

1

27 52

0.1

5

4

3

2

1

D D

12

R44

4.7K_0402_5%

APU_HDMI_CLK7 APU_HDMI_HPD7

APU_HDMI_DATA7

APU_HDMI_DATA

4.7K_0402_5%

12

R45

S

+3VS +3VS+5VS_HDMI+3VS

G

2

S

61

5

Q43A 2N7002KDWH_SOT363-6

SB00000EO1J

34

D

G

Q43B 2N7002KDWH_SOT363-6

SB00000EO1J

R25

2.2K_0402_5%

1 2

R26

2.2K_0402_5%

1 2

HDMI_CLK_CON HDMI_DET_CONAPU_HDMI_CLK

HDMI_DAT_CON

1M_0402_5%

APU_HDMI_HPD

R27

Q7

G

1 2

2

S

2N7002KW_SOT323-3

SB00000YY00

13

D

R46 20K_0402_1%

1 2

+CRT_VCC_CON and +5VS_HDMI trace width 100 mils

1

C34

2

20 21

22 23

+CRT_VCC_CON

R23

1 2

0_0805_5%

APU_HDMI_CLK+7

C C

APU_HDMI_CLK-7

APU_HDMI_TX0+7

APU_HDMI_TX0-7

APU_HDMI_TX1+7

APU_HDMI_TX1-7

APU_HDMI_TX2+7

B B

APU_HDMI_TX2-7

APU_HDMI_CLK+

APU_HDMI_TX0+

APU_HDMI_TX0-

APU_HDMI_TX1+

APU_HDMI_TX1-

APU_HDMI_TX2+

APU_HDMI_TX2-

1 2

C26 0.1U_0402_10V7-K

1 2

C27 0.1U_0402_10V7-K

1 2

C28 0.1U_0402_10V7-K

1 2

C29 0.1U_0402_10V7-K

1 2

C30 0.1U_0402_10V7-K

1 2

C31 0.1U_0402_10V7-K

1 2

C32 0.1U_0402_10V7-K

1 2

C33 0.1U_0402_10V7-K

HDMI_CLK+_CHDMI_CLK+_C HDMI_CLK+_CON

HDMI_TX0+_CHDMI_TX0+_C

HDMI_TX0-_CHDMI_TX0-_C HDMI_TX0-_CON

HDMI_TX1+_CHDMI_TX1+_C

HDMI_TX1-_CHDMI_TX1-_C HDMI_TX1-_CON

HDMI_TX2+_CHDMI_TX2+_C

HDMI_TX2-_CHDMI_TX2-_C HDMI_TX2-_CON

R32 0_0402_5%@

4

1

R35 0_0402_5%@

R36 0_0402_5%@

4

1

R37 0_0402_5%@

R38 0_0402_5%@

4

EMC@

1

R39 0_0402_5%@

R41 0_0402_5%@

4

EMC@

1

R42 0_0402_5%@

1 2

4

1

1 2

4

1

1 2

4

1

1 2

4

1

1 2

3

HDMI2012F2SF-900T04_4PEMC@

L2

2

3

HDMI2012F2SF-900T04_4PEMC@

L3

2

3

HDMI2012F2SF-900T04_4P

L4

2

3

HDMI2012F2SF-900T04_4P

L5

2

HDMI_CLK-_CONHDMI_CLK-_CHDM I_CLK-_CAPU_HDMI_CLK-

HDMI_TX0+_CON

HDMI_TX1+_CON

HDMI_TX2+_CON

1

C36 2200P_0402_50V7-K

2

+5VS +5VS_HDMI

1

2

HDMI_DET_CON

+5VS_HDMI

HDMI_DAT_CON HDMI_CLK_CON

HDMI_CLK-_CON

HDMI_CLK+_CON HDMI_TX0-_CON

HDMI_TX0+_CON HDMI_TX1-_CON

HDMI_TX1+_CON HDMI_TX2-_CON

HDMI_TX2+_CON

U6

1

APL3517AI-TRG_SOT23-3

C35

0.1U_0402_10V7-K

VIN

SA00004ZB0J

19 18 17 16 15 14 13 12 11 10

3

VOUT

2

GND

JHDMI1

ME@

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CK-

GND1

CK_shield

GND2

CK+

9

D0-

8 7 6 5 4 3 2 1

GND3

D0_shield

GND4 D0+ D1D1_shield D1+ D2D2_shield D2+

FOX_QJ111A1-RC0AH1-8H

0.1U_0402_10V7-K

HDMI_CLK-_CON HDMI_CLK+_CON HDMI_TX0-_CON HDMI_TX0+_CON

HDMI_TX1-_CON HDMI_TX1+_CON HDMI_TX2-_CON HDMI_TX2+_CON

A A

5

1 2

R28

1 2

R29 665_0402_1%

1 2

R30 665_ 0402_1%

1 2

R31 665_ 0402_1%

1 2

R33

1 2

R34 665_0402_1%

1 2

R43 665_ 0402_1%

1 2

R40 665_ 0402_1%

665_0402_1%

+3VS

HDMI_GND

2

G

13

D

Q6 2N7002KW_SOT323-3

SB00000YY00

S

4

For ESD

D3

@

+5VS_HDMI +5VS_HDMI

HDMI_DET_CON HDMI_DET_CON

HDMI_DAT_CON HDMI_DAT_CON

HDMI_CLK_CON HDMI_CLK_CON

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

9

10

8

9

7

6

65

2013/08/08

D4

@

Deciphered Date

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

HDMI_CLK-_CON HDMI_CLK-_CON

HDMI_CLK+_CON HD MI_CLK+_CON

HDMI_TX0-_CON HDMI_TX0-_CON

HDMI_TX0+_CON HDMI_TX0+_CON

LC Future Center Secret Data

2

9

10

8

9

7

6

65

2013/08/05

D5

@

HDMI_TX1-_CON HDMI_TX1-_CON

HDMI_TX1+_CON HDMI_TX1+_CON

HDMI_TX2-_CON HDMI_TX2-_CON

HDMI_TX2+_CON HDMI_TX2+_CON

Title

Size Document Number Rev

Custom

Date: S heet of

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

HDMI_CONN

Monday, December 16, 2013

10

9

7

65

ACLU7

ACLU7ACLU7

1

9

8

7

6

28 52

0.1

5

4

3

2

1

CRT Connector

+5VS +CRT_VCC

@

D18

2

D D

3

PMEG2010ET_SOT23-3

1

0.5A_8V_KMC3S050RY

W=40mils

+CRT_VCC_CON

F2

@

21

+CRT_VCC_CON

1

@

C155

0.1U_0402_10V7-K

2

check GPIO pin

1 2

FCH_CRT_R13

FCH_CRT_G13

FCH_CRT_B13

1 2

@

C50

RH130 150_0402_1%

+CRT_VCC_CON

1

2

A2Y

+CRT_VCC_CON

A2Y

RH131 150_0402_1%

1 2

OE#

U1

1

5

74AHCT1G125GW_SOT353-5

P

4

CRT_HSYNC_1

OE#

G

3

OE#

U2

1

5

74AHCT1G125GW_SOT353-5

P

4

CRT_VSYNC_1 VSYNC_CON

OE#

G

3

RH129 150_0402_1%

1 2

C C

0.1U_0402_10V7-K

FCH_CRT_HSYNC13

B B

FCH_CRT_VSYNC13

10P_0402_50V8J

1

2

10P_0402_50V8J

1

C43

C44

2

L6 BLM18BB 470SN1D_2P~D

1 2

L7 BLM18BB 470SN1D_2P~D

1 2

L8 BLM18BB 470SN1D_2P~D

10P_0402_50V8J

1

C45

2

L9

NBQ100505T-800Y-N_2P

1 2

L10

NBQ100505T-800Y-N_2P

1 2

10P_0402_50V8J

1

C51

2

10P_0402_50V8J

1

C53

2

HSYNC_CON

EMC@

10P_0402_50V8J

1

C46

2

10P_0402_50V8J

1

C47

C48

2

TVG1PAD@

FCH_CRT_DDC_DATA13

FCH_CRT_DDC_CLK13

1

CRT_DET# CRT_R_CON

CRT_DDC_DAT_CON CRT_G_CON

HSYNC_CON CRT_B_CON

VSYNC_CON

CRT_DDC_CLK_CON

1

C49

2

100P_0402_50V8J

R93 0_0402_5%

R94 0_0402_5%

JCRT1

ME@

6

11

1 7

12

2 8

13

3 9

14

4

10

16

G

15

17

G

5

SUYIN_070546HR015M25KZR

1 2

+CRT_VCC_CON

12

R52

4.7K_0402_5%

1

C54

@

100P_0402_50V8J

2

12

1

@

2

R53

4.7K_0402_5%

CRT_DDC_DAT_CON

CRT_DDC_CLK_CON

C55 100P_0402_50V8J

D20

1

CRT_R_CON CRT_R_CON

CRT_G_CON CRT_G_CON

CRT_B_CON CRT_B_CON

CRT_DET# CRT_DET#

A A

5

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

@

9

10

8

9

7

6

65

VSYNC_CON

HSYNC_CON

CRT_DDC_CLK_CON

CRT_DDC_DAT_CON

For EMC

4

D22

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

@

9

10

8

9

7

6

65

VSYNC_CON

HSYNC_CON

CRT_DDC_CLK_CON

CRT_DDC_DAT_CON

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2013/08/08

LC Future Center Secret Data

Deciphered Date

2

2013/08/05

Title

CRT_CONN

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: S heet of

Monday, December 16, 2013

ACLU7

ACLU7ACLU7

1

29 52

0.1

5

4

3

2

1

ON/OFF switch

+3VL +3VALW

R90 100K_0402_5%

1 2

NOVO#

NOVO#38

R102 0_0402_5%

D D

ON/OFF

1 2

Power Button

ON/OFF switch

Power Button TOP Side

Bottom Side

1

2

SW5

6

1 2

SHORT PADS

SMT1-05_4P

5

J19

@

3

4

@

R91 100K_0402_5%

1 2

D15

2

1

NOVO_BTN#

3

DAN202UT106_SOT323-3

Reserved SW5 for debug on 20130926

+3VALW

R121 100K_0402_5%@

ON/OFFBTN#

R127

1 2

0_0402_5%

1 2

ON/OFF

+3VL

R122 100K_0402_5%

1 2

ON/OFF 3 8

K/B Connector

KSI[0..7]

KSO[0..17]

CAPS_LED#38

KSI[0..7] 38

KSO[0..17] 38

CAPS_LED# PWR_CAPS_LED KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1

+3VS

OK OK

14" 15"

JKB2

27

GND1

28

GND2

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_88514-02601-07 1

ME@

R96

300_0402_5%

12

R97 300_0402_5%

NUM_LED#38

NUM_LED# PWR_NUM_LED CAPS_LED# PWR_CAPS_LED KSO17 KSO16 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1

JKB1

30

GND1

29

GND2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_50504-3041-001

ME@

31 32

TP/B Connector

C C

+5VS

R170

+3VS

R169

For 14" For 15"

1

VDD

2

CLK

3

DAT

4

B B

GND

5

TP-L

6

TP-R

1 2

0_0402_5%

1 2

0_0402_5%

1

2

3

4

5

6

@

VDD

CLK

DAT

GND

TP-L

TP-R

TP_PWR

0.1U_0402_10V7-K

TP_CLK TP_DATA

TP_LEFT Button

1A12

5

A

GND1

B3B1

GND2

EVQPLHA15_4P

4

6

TP_RIGHT Button

1A12

5

A

GND1

B3B1

GND2

EVQPLHA15_4P

4

6

312

DT1

AZC199-02S.R7G_SOT23-3@

TP_P5

AZ5215-01F_DFN1006P2E2

1

DT3

1

2

@

2

TP_P6

AZ5215-01F_DFN1006P2E2

1

DT5

1

2

@

2

JTP1

1

TP_CLK38 TP_DATA38

1

2

C114

@

1

2

C115

TP_CLK TP_DATA

@

TP_P5

1

TP_P6

2

C116

100P_0402_50V8J

TP_LEFT Button

1A12

5

SW1

A

GND1

B3B1

GND2

14@

4

6

OK

TP_RIGHT Button

1A12

5

SW3

A

GND1

B3B1

GND2

14@

4

6

2

3

4

5

7

6

GND1

6

8

GND2

ACES_50503-0060N-001

ME@

TP_P5

AZ5215-01F_DFN1006P2E2

1

DT2

1

EVQPLHA15_4P

2

@

2

TP_P6

AZ5215-01F_DFN1006P2E2

1

DT4

1

2

@

2

For EMC

SW2

15@

SW4

15@

USB I/O Connector

OK

USB20_P1014

OK

USB20_N1014

OK

USB20_P414

OK

USB20_N414

HP_OUTR34

OK

HP_OUTL34

OK

RING2_CONN34

OK

RING3_CONN34

PLUG_IN34

OK

PWR/B Connector

1

D17

1

2

@

2

AZ5215-01F_DFN1006P2E2

For EMC

NOVO_BTN# ON/OFFBTN# LID_SW#

+3VS

USB20_P10 USB20_N10

USB20_P4 USB20_N4

HP_OUTR HP_OUTL

RING2_CONN

RING3_CONN PLUG_IN

+3VL

JPWRB1

1

2

3

4

5

6

ACES_50503-0060N-001

ME@

LID_SW# 38

+USB_VCCB

GND1 GND2

7 8

JUSB3

18

G2

17

G1

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

ACES_50505-0184N-P01

ME@

20 19

For 14" For 15"

Right Side USB2.0 Port X 1 (USB/B)

LED

LED1

LED4

LED2

LED5

LED3

LED6

1 2

LTW-C193TS5

1 2

LTW-C193TS5

1 2

LTST-C193KFKT-LC

1 2

LTST-C193KFKT-LC

1 2

LTW-C193TS5

1 2

LTW-C193TS5

PWR_LED#38

BATT_LOW_LED#38

A A

BATT_CHG_LED#38

PWR_LED#

BATT_LOW_LED#

BATT_CHG_LED#

14@

15@

14@

15@

14@

15@

Add LED4,LED5,LED6 for 15"

300_0402_5%

1 2

R150

470_0402_5%

1 2

R151

R152 300_0402_5%

1 2

+5VALW

+3VALW

+5VALW

Delete JLED1 on due to both G14 and G15 move LED to MB

C130

1 2

2.2U_0603_10V6-K

USB_ON#31,38

U5

1

GND

2

VIN1

3

VIN2

EN/EN4FLAG

AP2820CMMTR-G1_MSOP8

Low Active 2A

VOUT3

VOUT2

VOUT1

+USB_VCCB+5VALW

8

7

6

5

USB_OC0#USB_ON#

1

C131 1000P_0402_50V7K

@

2

USB_OC0# 14

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/08

LC Future Center Secret Data

Deciphered Date

2

2013/08/05

Title

KBD/PWR/IO/LED/TP Conn

Size Document Number Rev

Custom

Date: Sheet of

Monday, December 16, 2013

1

ACLU7

ACLU7ACLU7

30 52

0.1

A

B

C

D

E

USB20_P11_R

LEFT SIDE USB3.0 PORT X2

8

7

6

5

+USB_VCCA

1

C72 1000P_0402_50V7K

@

2

B

USB_OC1# 14

D12

USB30_RX_R_N1

USB30_RX_R_P1

USB30_TX_R_P1

USB30_TX_P114

USB30_TX_N114

USB20_P1214

USB20_N1214

USB30_RX_P114

USB30_RX_N114

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

9

10

8

9

7

6

6 5

AZ1045-04F_DFN2510P10E-10-9

USB20_N12 USB20_N12_R

USB30_RX_N1 USB30_RX_R_N1

2013/08/08

C

@

1

USB30_RX_R_N1

1

2

USB30_RX_R_P1

2

4

USB30_TX_R_N1USB30_TX_R_N1

4

5

USB30_TX_R_P1

3

8

USB20_N1114

USB20_P1114

1 2

C75 0.1U_0402_10V7-K

1 2

C76 0.1U_0402_10V7-K

LC Future Center Secret Data

Deciphered Date

USB30_TX_C_P1USB30_TX_P1 USB30_TX_R_P1

+5VALW

1 1

2.2U_0603_10V6-K

1 2

C69

USB_ON#30,38

USB_ON# USB_OC1#

U4

1

GND

2

VIN1

3

VIN2

4

EN/EN

AP2820CMMTR-G1_MSOP8

VOUT3

VOUT2

VOUT1

FLAG

Low Active 2A

2 2

L13

USB20_N11

USB20_P11

3 3

4 4

USB30_RX_P1

USB30_RX_N1

USB30_TX_C_P1

USB30_TX_C_N1

USB20_N12

USB20_P12

For EMC

1

4

CMM21T-900M-N_4P

EMC@

L14

HDMI2012F2SF-900T04_4P

2

3

EMC@

L15

DLW21SN900HQ2L_4P

2

3

EMC@

L16

4

1

CMM21T-900M-N_4P

EMC@

A

2

3

1

USB30_RX_R_P1

1

4

USB30_RX_R_N1

4

1

USB30_TX_R_P1

1

4

USB30_TX_R_N1

4

3

2

USB20_N11_R

USB20_P11_R

USB20_N12_R

USB20_P12_R

USB20_N11_R

USB20_P12_R

USB20_N12_R

R75 0_0402_5%@

R76 0_0402_5%@ R77 0_0402_5%@

R78 0_0402_5%@ R79 0_0402_5%@

R80 0_0402_5%@

2013/08/05

1

2

AZ5425-01F_DFN1006P2E2

1

2

AZ5425-01F_DFN1006P2E2

R72 0_0402_5%@ R71 0_0402_5%@

1 2

1 2 1 2

1 2

D

D9

@

D13

@

1 2 1 2

1

D10

1

2

@

2

AZ5425-01F_DFN1006P2E2

1

D14

1

2

@

2

AZ5425-01F_DFN1006P2E2

USB30_TX_R_N1USB30_TX_C_N1USB30_TX_N1 USB20_P12_RUSB20_P12

USB30_RX_R_P1USB30_RX_P1

Title

USB 3.0 PORT (LEFT)

Size Document Number Rev

Custom

Date: Sheet of

+USB_VCCA

1

D11

1

2

@

2

AZ5425-01F_DFN1006P2E2

+USB_VCCA

1 2

C66

1 2

C67

1 2

C68

USB20_N11_RUSB20_N11 USB20_P11_RUSB20_P11

+USB_VCCA

1 2

C73

1 2

C74

JUSB2

9

StdA_SSTX+

1

VBUS

8

StdA_SSTX-

3

D+

7

GND_DRAIN

2

D-

6

StdA_SSRX+

4

GND_5

5

StdA_SSRX-

SUYIN_020053GR009M2736L

ACLU7

ACLU7ACLU7

Monday, December 16, 2013

ACLU7ACLU7

+

220U_6.3V_M

1U_0603_25V6M@

470P_0402_50V7K@

JUSB1

1

VBUS

2

D-

3

D+

4

GND

C-K_20267-5K11-02

1U_0603_25V6M@

470P_0402_50V7K@

ME@

E

ME@

GND1 GND2 GND3 GND4

GND_1 GND_2 GND_3 GND_4

31 52

5 6 7 8

10 11 12 13

0.1

A

B

C

D

E

F

G

H

SATA HDD Conn.

ME@

JHDD2

1

1 2

C77 .01U_0402_16V7-K

1 2

C78 .01U_0402_16V7-K

1 2

C79 .01U_0402_16V7-K

1 2

C80 .01U_0402_16V7-K

Need short

+5VS

@

1

C87 1U_0603_25V6M

2

1 2

100K_0402_5%

ODD_EN#

J4

112

JUMP_43X79

1

C88 10U_0805_25V6K

2

R83

12

@

1 2

SATA_FTX_DRX_P0 SATA_FTX_DRX_N0

SATA_FRX_DTX_N0 SATA_FRX_DTX_P0

1

C86

0.1U_0402_10V7-K

2

+5VS +5V_ODD+5VALW

12

13

D

Q13

2

G

S

R84 10K_0402_5%

R86

2N7002KW_SOT323-3

SATA_FTX_DRX_P013

1 1

2 2

3 3

SATA_FTX_DRX_N013

SATA_FRX_DTX_N013

SATA_FRX_DTX_P013

+5VS

@

For EMC

ODD_EN13

1

C85 1000P_0402_50V7K

2

10K_0402_5%

R89

100K_0402_5%

SATA_FTX_C_DRX_P0 SATA_FTX_C_DRX_N0

SATA_FRX_C_DTX_N0 SATA_FRX_C_DTX_P0

@

2

+5VS_HDD

1

@

C89 10U_0805_25V6K

2

Need open

J5

@

112

JUMP_43X79

LP2301ALT1G_SOT23-3

S

G

2

D

13

1

C98 .01U_0402_16V7-K

2

Q12

GND_1

2

A+

3

A-

4

GND_2

5

B-

6

B+

7

GND_3

8

V33_1

9

V33_2

10

V33_3

11

GND_4

12

GND_5

13

GND_6

14

V5_1

15

V5_2

16

V5_3

17

GND_7

18

DAS/DSS

19

GND_8

20

V12_1

21

V12_2

22

V12_3

SUYIN_127043HR022M32QZR

1

2

C97

C96

10U_0805_25V6K

0.1U_0402_10V7-K

ODD_EN#

SATA_FTX_DRX_P113 SATA_FTX_DRX_N113

SATA_FRX_DTX_N113 SATA_FRX_DTX_P113

ODD_DETECT#14

12

R87 470_0603_5%

@

13

D

Q14

2

G

S

2N7002KW_SOT323-3@

SATA_FTX_DRX_P1 SATA_FTX_DRX_N1

SATA_FRX_DTX_N1 SATA_FRX_DTX_P1

SATA_FTX_DRX_P1 SATA_FTX_DRX_N1

SATA_FRX_DTX_N1 SATA_FRX_DTX_P1

1U_0603_10V6-K

C81 .01U_0402_16V7-K14@ C82 .01U_0402_16V7-K14@

C83 .01U_0402_16V7-K14@ C84 .01U_0402_16V7-K14@

C90 .01U_0402_16V7-K15@ C91 .01U_0402_16V7-K15@

C92 .01U_0402_16V7-K15@ C93 .01U_0402_16V7-K15@

R81

1 2

0_0402_5%

C156

ODD_DA#_R

R74

R158

1 2 1 2

1

@

2

1 2

0_0402_5%

1 2

@

0_0402_5%

SATA_FTX_C_DRX_P1_14 SATA_FTX_C_DRX_N1_14

SATA_FRX_C_DTX_N1_14 SATA_FRX_C_DTX_P1_14

ODD_DETECT#_R

+5V_ODD ODD_DA#_R

SATA_FTX_C_DRX_P1_15 SATA_FTX_C_DRX_N1_15

SATA_FRX_C_DTX_N1_15 SATA_FRX_C_DTX_P1_15

ODD_DETECT#_R

+5V_ODD ODD_DA#_R

R155

@

0_0402_5%

1 2

+3VS

@

R85

1 2

10K_0402_5%

Follow Edge ODD_DA#_R schematic and reserve ODD_DA_EC# on 20130930

G

2

Q15

13

D

S

2N7002KW_SOT323-3

SB00000YY00

ODD_DA_EC#

@

FOR 14"

SATA ODD Conn.

JODD1

1

GND_1

2

RX+

3

RX-

4

GND_2

5

TX-

6

TX+

7

GND_3

8

DP

9

+5V_1

10

+5V_2

11

MD

12 13

GND1

GND_4

GND2

GND_5

SUYIN_127382FB013S255ZL

ME@

FOR 15"

SATA ODD FFC Conn

JODD2

1

2

3

4

5

6

7

8

9

10

11

GND_1

12

GND_2

ACES_51524-01001-003

ME@

SUS Power Well

ODD_DA#_FCH 14

Core Power Well

ODD_DA_INTH# 12

ODD_DA_EC# 38

14 15

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

D

2013/08/08

LC Future Center Secret Data

Deciphered Date

E

F

2013/08/05

Title

HDD/ODD CONN

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

Monday, December 16, 2013

G

ACLU7

ACLU7ACLU7

32 52

H

0.1

A

1 1

B

C

D

E

Mini-Express Card(WLAN/WiMAX)

JWLAN1

1

GND1

USB20_P614 USB20_N614

2 2

PCIE_CTX_C_DRX_P25 PCIE_CTX_C_DRX_N25

PCIE_CRX_DTX_P25 PCIE_CRX_DTX_N25

PCIE_WLAN_CLK_P212 PCIE_WLAN_CLK_N212

1 2

R99 0_0402_5%

1 2

+3VALW

+3VS_WLAN

+3VS

2

G

Q11

CLKREQ_WLAN#14

3 3

1 3

D

2N7002KW_SOT323-3

1 2

R68 0_0402_5%

R67 10K_0402_5%

@

1 2

S

WLAN_CLKREQ_Q#

R147 10K_0402_5%

1 2

R157 10K_0402_5%@

WLAN_CLKREQ_Q#

WLAN_WAKE#_R

3 5 7

9 11 13 15

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75

76

USB_D+

USB_D-

GND2

NC NC NC NC

MLDIR_SENSE

DP_ML3N

DP_ML3P

GND3

DP_ML2N

DP_ML2P

GND4

DP_HPD

GND5

PETP0

PETN0

GND6

PERP0

PERN0

GND7

REFCLKP0

REFCLKN0

GND8

CLKREQ0#

PEWAKE0#

GND9

PETP1

PETN1

GND10

PERP1

PERN1

GND11

REFCLKP1

REFCLKN1

GND12

PEG1

RESERVED1 RESERVED2 RESERVED3

RESERVED/W_DISABLE#2

W_DISABLE#1

I2C_ALERT# RESERVED4

JAE_SM3ZS067U410BAR1000

CLKREQ1# PEWAKE1#

3.3VAUX1

3.3VAUX2 LED#1

NC NC NC NC

LED#2

GND16 DP_AUXN DP_AUXP

GND13

DP_ML1N DP_ML1P

GND14

DP_ML0N DP_ML0P

GND15

COEX3 COEX2 COEX1

SUSCLK

PERST0#

I2C_DATA

I2C_CLK

PERST1#

3.3VAUX4

3.3VAUX5

PEG2

+3VS_WLAN

2 4

1

6

8 10 12 14

16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74

77

T15@

1

T16@

1 2

R60

1

22_0402_5%

1K_0402_1%

@

T17

AOAC@

100K_0402_5%

AOAC_ON#38

EC_TX_RSVD EC_TX_R EC_RX_RSVD BT_OFF#

SUSCLK_R PLT_RST# BT_OFF# WLAN_OFF# FCH_WLAN_OFF# SMB_DATA_S3_R SMB_CLK_S3_R

EC_TX_R

1 2

R64 0_0402_5%@

1 2

R88 0_0402_5%@

1 2

R61

R62

1 2 1 2

R63 0_0402_5%

1 2

R65 0_0402_5%@

1 2

R66 0_0402_5%@

+3VS_WLAN

follow edge to add debug port on 20131001

+3VS

+3VALW

LP2301ALT1G_SOT23-3

Q10

1

C65

0.1U_0402_10V7-K

AOAC@

2

PCICLK0 12 PLT_RST# 12,17,35

PCH_BT_DISABLE# 12

SMB0_DATA 10,11,14 SMB0_CLK 10,11,14

BT_OFF#

R184 100_0402_1%

R185 100_0402_1%

12

R187 100K_0402_5%

S

G

2

1 2

J3

112

JUMP_43X79

D

13

AOAC@

+3VS_WLAN

@

2

1

C64

0.1U_0402_10V7-K

AOAC@

2

FCH_WLAN_OFF# 12WLAN_WAKE#38

EC_TXEC_TX_R

EC_TX 38

EC_RX 38

Connect CLKREQ_WLAN# and WLAN_CLKREQ_Q# directly and reserve Q11 on 20131004

Change R67 power rail from 3VS to +3VS_WLAN on 20131011

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

C

2013/08/08

LC Future Center Secret Data

Deciphered Date

D

2013/08/05

Title

NGFF-Card / SSD

Size Document Number Rev

C

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

E

33 52

0.1

5

4

3

2

1

+3VS

+5VS

D D

Follow common design on 2013/10/9

BEEP#38

FCH_SPKR14

C C

PLUG_IN30

B B

RA17

RA36

1

CA15

2

4.7U_0603_10V6-K

5.11K_0402_1%

1 2

39.2K_0402_1%

1 2

20K_0402_1%

2

CA18

CA16

1

4.7U_0603_10V6-K

RA15

2

1

0.1U_0402_10V7-K

Close to Pin11,13,16

RB751V-40_SOD323-2 @

EC_MUTE#38

A A

EC_MUTE#

5

DA4

RA35

Mounted DA4 for EC mirror function on 2013/12/5

1 2

RA2 0 _0603_5%

1 2

RA7 0 _0603_5%

1 2

RA10 0_0603_5%

DA1

2

3

BAT54CW_SOT323-3

+3.3VD

1 2

JSENSE

+5VD

CA19

0.1U_0402_10V7-K

1 2

0_0402_5%

+3.3VD

+5VA

+5VD

.1U_0402_10V6-K

1

PC_BEEP1

HDA_RST_AUDIO#14

HDA_BITCLK_AUDIO1 4

HDA_SYNC_AUDIO14

HDA_SDIN014

HDA_SDOUT_AUDIO14

DMIC_CLK27 DMIC_DATA27

+3.3VD

12

RA28 47K_0402_5%

SPKR_MUTE#

CA2

12

RA14 10K_0402_5%

1 2

PC_BEEP

HDA_RST_AUDIO#

HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO

33_0402_5%

HDA_SDOUT_AUDIO

1 2 1 2

CA14 1U_0402_6.3V6K

CA17 2.2U_0603_6.3V6K

CA22

1

2

@

22P_0402_50V8-J

1 2

RA1833_0402_5% RA190_0402_5%

+5VD

1 2

'delete 1.5VS power rail on DVDD_IO on 2013/10/9

+3VS

RA16

1 2

RA11 0_0402_5%

SDATA_IN

1 2

RA27

1

2

33P_0402_50V8J

CA25

@

10 39

38 37

40

11

13 16

19 20

21

41

1 2

@

27_0402_5%

PC_BEEP SPKR_MUTE#

JSENSE

DMIC_CLK_R DMIC_DATA_R

0.1U_0402_10V7-K

CA13

UA1

9

RESET#

5

BIT_CLK

8

SYNC

6

SDATA_IN

4

SDATA_OUT

CX20751-11Z

PC_BEEP SPKR_MUTE#

JSENSE GPIO1/PORTC_R_MIC

MUSIC_REQ/GPIO0/PORTC_L_MIC36MICBIASC DMIC_CLK/MUSIC_REQ/GPIO0

1

DMIC_DAT/GPIO1

CLASS-D_REF

LPWR_5.0 RPWR_5.0

FLY_P FLY_N

AVEE

GND

CX20752-21Z_QFN40_5X5

HDA_RST_AUDIO#

HDA_BITCLK_AUDIO

DVDD_IO

2

CA1

1

0.1U_0402_10V7-K

Close to Pin7

FILT_1.8V

VDDO_3.3 DVDD_3.3

AVDD_3.3

VREF_1.65V

AVDD_5V

MICBIASB

PORTB_R_LINE

PORTB_L_LINE

PORTD_A_MIC PORTD_B_MIC

AVDD_HP

PORTA_R

PORTA_L

CA27

220P_0402_50V7K

VDD_IO

LEFT+

LEFT-

RIGHT+

RIGHT-

HGNDA HGNDB

@

2

1

@

2

CA28

1

220P_0402_50V7K

3

FILT_1.8V

7

DVDD_IO

2 18

27

AVDD_3.3

29

VREF_1.65V

28

+5VA

12

SPK_L+

14

SPK_L-

17

SPK_R+

15

SPK_R-

35 34

MICBIASB

33

LINE_B_R

32

LINE_B_L

30

PORTD_A_MIC

31

PORTD_B_MIC

25

RING2_CONN

26

RING3_CONN

24

23

HPOUT_R

22

HPOUT_L

Close to Pin24

@

2

CA29

CA30

1

220P_0402_50V7K

Close to Pin3

@

2

1

CA3

0.1U_0402_10V7-K

+3VALW

2

1

0.1U_0402_10V7-K

1 2

1 2 1 2

1

2

CA4

CA12

@

@1 2

@ @

4.7U_0603_10V6-K

+3.3VD

MICBIASB

RA2515_0402_5% RA2915_0402_5% RA3215_0402_5% RA3315_0402_5%

CA16 close to Pin18 CA17 close to Pin2

2

1

CA7

1

2

1U_0402_6.3V6K

0.1U_0402_10V7-K

DA5

BAT54AWT1G_SOT323-3

1

3

2

2.2K_0402_1%

12

RA37

PORTD_A_MIC PORTD_B_MIC

SPK_R+ SPK_RSPK_L+ SPK_L-

RA38

RA22

1 2 1 2

RA23

1 2

RA26 0_0603_5%

1 2

RA31 0_0603_5%

1 2

RA30 0_0603_5%

1 2

RA34 0_0603_5%

Short GND and GNDA on groud layer of layout on 2013/11/17

1 2

RA1 0_0402_5%

@

GND GNDA

Close to Pin27

CA8

100_0402_5% 100_0402_5%

1

2

CA5

2

1

2.2U_0603_6.3V6K

0.1U_0402_10V7-K

2

1

CA9

1

2

1U_0402_6.3V6K

0.1U_0402_10V7-K

Close to Pin29

RA43

100_0402_5%

CA35

4.7U_0603_10V6-K

CA20 2.2U_0603_6.3V6K CA21 2.2U_0603_6.3V6K

SPK_R+_CONN SPK_R-_CONN SPK_L+_CONN SPK_L-_CONN

CA6

CA10

LINE_B_R

12

1

2

1 2 1 2

+5VA

Close to Pin28

LINE_B_L

12

RA40 100_0402_5%

1

CA38

4.7U_0603_10V6-K

2

RA20

1 2

RA21

1 2

CA32

CA31

1

2

@

1000P_0402_50V7K

2

1

1000P_0402_50V7K

CA11

0.1U_0402_10V7-K

75_0402_1% 75_0402_1%

CA33

1

2

@

CA34

1

2

@

1000P_0402_50V7K

HP_OUTR 30 HP_OUTL 30

RING3_CONN 3 0 RING2_CONN 3 0

JSPK1

ME@

1

2

3

4

5

GND1

6

GND2

ACES_88231-04001

For EMI

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2013/08/08

LC Future Center Secret Data

Deciphered Date

2

2013/08/05

Title

Codec_CX20752

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: S heet of

Monday, December 16, 2013

ACLU7

ACLU7ACLU7

1

34 52

0.1

5

4

3

2

1

+3VALW TO +3VALW_LAN

JUMP_43X79

112

@

2

PLT_RST#12,17,33 PCIE_CRX_DTX_N05 PCIE_CRX_DTX_P05

JL1

D D

+3VALW_LAN

RL5

4.7K_0402_5%

@

1 2

C C

+3VS

12

RL9 1K_0402_1%

ISOLATE#

RL11 15K_0402_5%

LAN_WAKE#38

LAN_WAKE#

+3VALW_LAN rising time (10%~90%):

0.5msˉspecˉ100ms

width : 40 mils

4.7U_0603_6.3V6-K

CL1

1

@

2

Close to Pin11

RL7

1 2

CL10 0.1U_0 402_10V7-K

1 2

CL11 0.1U_0 402_10V7-K

4.7U_0603_6.3V6-K

CL5

1

@

2

Close to Pin32

1 2

2.49K_0402_1%

CL6

Close to Pin11

+3VALW_LAN RSET +LAN_VDD10 LAN_XTALO LAN_XTALI

+LAN_REGOUT +LAN_VDDREG +LAN_VDD10 LAN_WAKE# ISOLATE# PLT_RST# PCIE_CRX_C_DTX_N0 PCIE_CRX_C_DTX_P0

1

2

CL7

0.1U_0402_10V7-K

1

2

0.1U_0402_10V7-K

Close to Pin32

UL1

33

GND

32

AVDD33_2

31

RSET

30

AVDD10

29

CKXTAL2

28

CKXTAL1

27

LED0

26

LED1/GPIO

25

LED2

24

REGOUT

23

VDDREG

22

DVDD10

21

LANWAK EB

20

ISOLATEB

19

PERSTB

18

HSON

17

HSOP

RTL8111G-CG_QFN32_4X4

GIGA@

REFCLK_N REFCLK_P

HSIN

HSIP CLKREQB AVDD33_1

MDIN3

MDIP3

AVDD10_2

MDIN2

MDIP2

MDIN1

MDIP1

AVDD10_1

MDIN0

MDIP0

+3VALW_LAN +LAN_VDDREG+3VALW +3VALW_LAN

1 2

RL1 0_0603_5%

16

PCIE_LAN_CLK_N0

15

PCIE_LAN_CLK_P0

14

PCIE_CTX_C_DRX_N0

13

PCIE_CTX_C_DRX_P0

12

LAN_CLKREQ#

11

+3VALW_LAN

10

LAN_MDI3-

9

LAN_MDI3+

8

+LAN_VDD10

7

LAN_MDI2-

6

LAN_MDI2+

5

LAN_MDI1-

4

LAN_MDI1+

3

+LAN_VDD10

2

LAN_MDI0-

1

LAN_MDI0+

1

CL2

4.7U_0603_6.3V6K

2

PCIE_LAN_CLK_N0 12 PCIE_LAN_CLK_P0 12 PCIE_CTX_C_DRX_N0 5 PCIE_CTX_C_DRX_P0 5

LAN_CLKREQ# 14

LAN_MDI3- 36 LAN_MDI3+ 36

LAN_MDI2- 36 LAN_MDI2+ 36 LAN_MDI1- 36 LAN_MDI1+ 36

LAN_MDI0- 36 LAN_MDI0+ 36

1

CL3

0.1U_0402_10V7-K

2

LAN_CLKREQ#

RL4 4.7K_0402_5%

Vendor recommand reseve the PU resistor close LAN chip

+3VS

1 2

B B

A A

delete LAN_PWR_ON# on 20131003

1

12P_0402_50V8-J

5

CL12

25MHZ_10PF_7V25000014

2

YL1

OSC1

GND2

GND12OSC2

LAN_XTALI

4

3

LAN_XTALO

1

CL13 12P_0402_50V8-J

2

+LAN_REGOUT

4

Reserve for RTL8111GS (SWR mode)

1 2

LL1

2.2UH_NLC252018T-2R2J-N_5%

Layout Note: LL1 must be within 200mil to Pin36, CL15,CL16 must be within 200mil to LL1 +LAN_REGOUT: Width =60mil

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

CL15

4.7U_0603_6.3V6K

2013/08/08

1

CL16

0.1U_0402_10V7-K

2

LC Future Center Secret Data

+LAN_VDD10

Deciphered Date

Close to Pin8,30

1

CL17

0.1U_0402_10V7-K

2

2013/08/05

1

CL18

0.1U_0402_10V7-K

2

Close to Pin3,22

1

CL19

0.1U_0402_10V7-K

2

Title

LAN_RTL8106E/8111G

Size Document Number Rev

Custom

Date: Sheet of

1

CL20

0.1U_0402_10V7-K

2

ACLU7

ACLU7ACLU7

Monday, December 16, 2013

ACLU7ACLU7

35 52

1

35 52

0.1

5

4

3

2

1

DL1/DL2 1'S PN:SC300003M00

D D

DL1

9

I/O4

2

NC1

4

NC2

+3VALW_LAN

LAN_MDI2- LAN_MDI3-

5

VDD

6

NC3

7

I/O3

AZ3033-04F_DFN2525P10 E10

Place Close to TL1

DL2

9

I/O4

2

C C

+3VALW_LAN

NC1

4

NC2

5

VDD

6

NC3

7

I/O3

AZ3033-04F_DFN2525P10 E10

I/O2

NC5

GND

NC4

I/O1

I/O2

NC5

GND

NC4

I/O1

3

LAN_MDI3+LAN_MDI2+

10

EMC@

11

8

1

2

CL24

3

10

11

8

1

LAN_MDI0+LAN_MDI1+

EMC@

LAN_MDI0-LAN_MDI1-

0.1U_0603_25V7K

LAN_MDI0-35

LAN_MDI0+35

LAN_MDI1-35

LAN_MDI1+35

LAN_MDI2+35

LAN_MDI2-35

LAN_MDI3+35

LAN_MDI3-35

LAN_MDI0- LAN_MDO0-

LAN_MDI0+

LAN_MDI1- LAN_MDO1-

LAN_MDI1+

LAN_MDI2+

LAN_MDI2-

LAN_MDI3+

LAN_MDI3-

TL1

24

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19

MX2-

18

MCT3

17

MX3+

16

MX3-

15

MCT4

14

MX4+

13

MX4-

BOTH_GST5009-E-LF

GIGA@

TCT1

TD1+

TD1-

TCT2

TD2+

TD2-

TCT3

TD3+

TD3-

TCT4

TD4+

TD4-

1

2

3

4

5

6

7

8

9

10

11

12

MCT

LAN_MDO0+

MCT

LAN_MDO1+

MCT

LAN_MDO2+

LAN_MDO2-

MCT

LAN_MDO3+

LAN_MDO3-

CL33

10P_0603_50V8-J

@

12

1

2

CHASSIS1_GND

RL20 75_0603_5%

1

CL32 1000P_1206_2KV7-K

2

1

DL4

1

BS4200N-C-LV_SMB-F2

2

Place Close to TL2

SANTA_130460-3

B B

1 2

CL26 470P_0402_50V7K@

1 2

CL27 10U_0805_10V6K@

1 2

CL28 0.1U_0603_25V7K

1 2

CL29 0.1U_0603_25V7K

CL30 1 0U_0603_6.3V6-M@

A A

CHASSIS1_GND

Reserve for EMI go rural solution

5

1 2

CL31 470P_0402_50V7K@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

2013/08/08

3

LC Future Center Secret Data

Deciphered Date

2013/08/05

LAN_MDO0+

LAN_MDO0-

LAN_MDO1+

LAN_MDO2+

LAN_MDO2-

LAN_MDO1-

LAN_MDO3+

LAN_MDO3-

2

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

JRJ1

Title

LAN_Transformer

Size Docum ent Number Rev

B

Date: Sheet of

ME@

GND_4

GND_3

GND_2

GND_1

ACLU7

ACLU7ACLU7

Monday, December 16, 2013

ACLU7ACLU7

12

11

10

9

CHASSIS1_GND

1

36 52

0.1

5

4

3

2

1

D D

Close U3

C57

2200P_0 402_50V7K

1

2

REMOTE+ _R

REMOTE-_ R

C59

0.1U_040 2_10V7-K

+3VS

SMSC thermal sensor placed near DIMM

U3

1

VDD

R54

REMOTE+ _R

REMOTE-_ R

@

10K_040 2_5%

1

2

+3VS

12

2

D+

3

D-

4

T_CRIT#

NCT7718 W_MSOP8

SCL

SDA

ALERT#

GND

8

EC_SMB_ CK3

7

EC_SMB_ DA3

6

5

EC_SMB_ CK3 7,14,18,3 8

EC_SMB_ DA3 7,14,18,3 8

Address 1001_101xb

C C

REMOTE1 +

REMOTE2 +

REMOTE2 -

REMOTE1 -

DIS@

1 2

R55 0_0402_ 5%

UMA@

1 2

R56 0_0402_ 5%

UMA@

1 2

R57 0_0402_ 5%

DIS@

1 2

R58 0_0402_ 5%

REMOTE+ _R

REMOTE-_ R

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: Trace width/space:10/10 mil

REMOTE1 +

C58

100P_04 02_50V8J

DIS@

REMOTE1 -

REMOTE2 +

C70

100P_04 02_50V8J

REMOTE2 -

1

2

1

2

Near GPU&VRAM

C

2

Q9

B

MMST390 4-7-F_SOT323-3

E

DIS@

3 1

Near CPU core

C

2

Q16

B

MMBT390 4WH_SOT32 3-3

E

3 1

Trace length:<8"

FAN Conn

B B

10U_080 5_25V6K

C60

+5VS

1 2

R59

0_0603_ 5%

2

0.1U_040 2_10V7-K

1

C61

@

+5VS_FA N

1

2

EC_FAN_ SPEED38 EC_FAN_ PWM38

JFAN1

1

2

3

4

5

GND1

6

GND2

ACES_85 205-04001

ME@

A A

Title

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/ 08

3

LC Future Center Secret Data

Deciphered Date

2013/08/ 05

2

Title

Thermal sensor/FAN CONN

Size Docu ment Number Rev

Custom

Date: Sheet of

Monday, December 16, 2013

ACLU7

ACLU7ACLU7

1

37 52

0.1

5

4

3

2

1

1 2

RE1 0_0603 _5%

@

1 2

Close EC

1 2

RE4

0_0402_5%

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

RE42

@

1 2

0_0402_5%

EC_RSMRST#

0_0402_5%

@

+3VL_VSTBY0

EC_WAKE#

1

CE14 47P_0402_50V8J

@

2

CE3

1 2

0.1U_0402_10V7-K

Dlete +RTCBATT at UE1.3 on 1003

1 2

RE6 0_0402 _5%

@

UE1

4

KBRST#/GPB6

5

SERIRQ/GPM6

6

LFRAME#/GPM5

7

LAD3/GPM3

8

LAD2/GPM2

9

LAD1/GPM1

10

LAD0/GPM0

13

LPCCLK/GPM4

14

WRST#

15

ECSMI#/GPD4

16

PWUREQ#/BBO/SMCLK2ALT/GPC 7

17

LPCPD#/GPE6

22

LPCRST#/GPD2

23

ECSCI#/GPD3

126

GA20/GPB5

58

KSI0/STB#

59

KSI1/AFD#

60

KSI2/INIT#

61

KSI3/SLIN#

62

KSI4

63

KSI5

64

KSI6

65

KSI7

36

KSO0/PD0

37

KSO1/PD1

38

KSO2/PD2

39

KSO3/PD3

40

KSO4/PD4

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

56

KSO16/SMOSI/GPC3

57

KSO17/SMISO/GPC5

110

PWRSW#

111

XLP_OUT

115

SMCLK1/GPC1

116

SMDAT1/GPC2

117

SMCLK2/PECI/GPF6

118

SMDAT2/PECIRQT#/GPF7

94

CRX1/SIN1/SMCLK3/GPH1/ID1

95

CTX1/SOUT1/GPH2/SMDAT3/ID2

112

VSTBY0

125

GPE4

33

GINT/CTS0#/GPD5

35

RTS1#/GPE5

93

CLKRUN#/GPH0/ID0

2

CK32KE/GPJ7

128

CK32K/GPJ6

IT8586E-AX_LQFP128_14X1 4

H_PROCHOT# 7

VCOREVCC

3

Int. K/B Matrix

12

VBAT

D D

Change RE6 to 0ohm jump

Please change net name VGA_AC_DET on page51 to another net name XXX and spare one EC pin for this pin name XXX !!!

+3VALW_R

1 2

DE1

RB751V-40_SOD323- 2

1 2

RE8 100K_040 2_5%

C C

22P_0402_50V8-J

CE90

1

CE12 1U_0402_6.3V6K

2

KSI[0..7]30

KSO[0..17]30

EC_SMB_CK1

1

@

2

reserved CE90 for EMC request

Follow Edge to change UE1.Pin117 from PECI_EC to VDDAPWROK on 0927

+3VL

Change RE24 to 0ohm jump

B B

+3VS+5VS

1 2

RE37 0_0402 _5%

1 2

RE39 0_0402 _5%@

EC_TX EC_RX

12

RE41

100K_0402_5% @

AC_PRESENT1 4

J80P1

1

2

3

4

5

GND1

6

GND2

ACES_85205-04001

Follow Edge to delete VGA_AC_DET on 0927

ME@

VR_HOT#52

LPC_FRAME#12

LPC_AD312 LPC_AD212 LPC_AD112 LPC_AD012

CLK_PCI_EC12,16

GPU_VR_HOT#18,51

EC_A_RST#12

delete net name EC_SMI# on UE1.Pin15 on 20130928 Add GPU_VR_HOT on UE1.Pin15 on 20130930

KSI[0..7]

KSO[0..17]

EC_SMB_DA1

KSI7 KSI6 WRST#

For factory EC flash

ON/OFF30

EC_SMB_CK144,45 EC_SMB_DA144,45

VDDAPWROK50,52

EC_SMB_CK37,14,18,37 EC_SMB_DA37,14,18,37

USB_ON#30 ,31

FCH_S512

EC_RSMRST#14

AC_PRESENT

RE34 0_0402_5%

H_PROCHOT#_EC

LAN_WAKE#35

1 2

2N7002KW_SOT32 3-3

KBRST#

KBRST#14

SERIRQ

SERIRQ12

LPC_FRAME# LPC_AD3

LPC_AD2 LPC_AD1

LPC_AD0

CLK_PCI_EC

WRST#

GPU_VR_HOT#

EC_RX

EC_RX33

EC_TX

EC_TX33

EC_A_RST#

EC_SCI#

EC_SCI#14

GATEA20

GATEA2014

1

PAD @

IT1

1

PAD @

IT2

1

PAD @

IT3

1

PAD @

IT4

1

PAD @

IT5

1

PAD @

IT6

1

PAD @

IT7

1

PAD @

IT8

ON/OFF

EC_SMB_CK1 EC_SMB_DA1 VDDAPWROK

delete LAN_PWR_ON# on 20131003

EC_SMB_CK3 EC_SMB_DA3

Delete LAN_PWR_ON# at UE1.118 on 20131003

1 2

RE27 0_0402_5%@

LAN_WAKE#

USB_ON#

FCH_S5

Follow Edge to change UE1.Pin35 from VSB_ON to FCH_S5 on 0927

EC_WAKE#14,18

1 2

RE33

13

D

QE1

2

G

S

RE3 0_0603 _5%

+3VALW_EC

+3VS

11

50

92

114

121

127

VCC

VCORE

VSTBY2

VSTBY3

VSTBY4

VSTBY126VSTBY5

VSTBY(PLL)

LPC

IT8586E/AX LQFP-128L

EXTERNAL SERIAL FLASH

SPI Flash ROM

SM Bus

WAKE UP

GPIO

Clock

VSS1

VSS2

VSS4

VSS349VSS6

1

27

91

+3VALW_R

minimum trace width 12 mil

74

AVCC

PWM

DAC

PS2

UART

GPIO

AVSS

VSS5

75

113

122

EC_AGND

+3VL

+3VALW

All capacitors close to EC

1

CE6

2

0.1U_0402_10V7-K

PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5

PWM6/SSCK/GPA6

PWM7/RIG1#/GPA7

TMRI0/GPC4 TMRI1/GPC6

ADC0/GPI0 ADC1/GPI1 ADC2/GPI2

ADC

ADC3/GPI3

ADC4/GPI4 ADC5/DCD1#/GPI5 ADC6/DSR1#/GPI6 ADC7/CTS1#/GPI7

DAC2/TACH0B/GPJ2 DAC3/TACH1B/GPJ3

DAC4/DCD0#/GPJ4

DAC5/RIG0#/GPJ5

PS2CLK0/TMB0/CEC/GPF0

PS2DAT0/TMB1/GPF1

GPF2

GPF3 PS2CLK2/GPF4 PS2DAT2/GPF5

GPH3/ID3 GPH4/ID4 GPH5/ID5 GPH6/ID6

NC1 NC2 NC3 NC4

AC_IN#

LID_SW#

EGAD/GPE1 EGCS#/GPE2 EGCLK/GPE3

GPJ1 SSCE0#/GPG2 SSCE1#/GPG0

DSR0#/GPG6

DTR1#/SBUSY/GPG1/ID7

CRX0/GPC0

CTX0/TMA0/GPB2

RI1#/GPD0 RI2#/GPD1

TACH2/GPJ0

TACH1A/TMA1/GPD7

TACH0A/GPD6

L80HLAT/BAO/GPE0

L80LLAT/GPE7

1

CE7

2

24 25 28 29 30 31 32 34 120 124

66 67 68 69 70 71 72 73

78 79 80 81

85 86 87 88 89 90

96 97 98 99

101 102 103 105

Follow Edge to change UE1.Pin108 from ACIN# to ACPRN on 20131003

108 109

Delete VDDQ_PGOOD EC pin83 and VGA_GATE# pin82 to add FCH_PWR_EN

82 83 84

77 100 106 104 107 119 123 18 21 76 48 47 19 20

1

CE9

CE8

2

0.1U_0402_10V7-K

VGA_AC_BATT

EC_FAN_PWM

S5_1.1V_EN

SUSP#

BATT_TEMP Board_ID

Need to check with PWR and Edge schematic if change net name ADAPTER_ID to ADP_ID!!

H_PROCHOT#_EC

DGPU_PWROK_E

0_0402_5%

delete PM_SLP_SUS# on UE1.87 ,this net for Intel deep sleep ,no need

TP_CLK TP_DATA

CAPS_LED#

EC_SPI_CS1# EC_SPI_SI EC_SPI_SO EC_SPI_CLK

ACPRN LID_SW#

0_0402_5%

RE16

@

12

RE50

EC_ON_R EC_ONEC_ON

0_0402_5%

PM_SLP_S5#

EC_MUTE#

FCH_PWR_EN

Delete BATT_OUT EC pin106 and add FCH_PWR_EN on UE1.106

SYSON EC_BKOFF#

delete EC_LID_OUT# from UE1.Pin21 and UH2.R2 ,due to EC_WAKE# can handle its function,too

EC_FAN_SPEED WLAN_WAKE#

Follow Edge to add PL resistor 100K for AOAC_ON# on 20130929

1

CE10

CE11

@

2

0.1U_0402_10V7-K

PWR_LED# 30 BATT_CHG_LED# 30 BATT_LOW_LED# 30

VGA_AC_BATT 18

ODD_DA_EC# 32

EC_FAN_PWM 37

BEEP# 34

S5_1.1V_EN 49

BATT_LEN# 44

SUSP# 39,47,48,50,51

NTC_V 43

Delete TURBO_V on UE1.67 ,PWR unused

BATT_TEMP 44,45

ADP_I 45 APU_IMON 52 ADAPTER_ID 43

IMVPPOK 52

MAINPWON 43,46

APU_ENBKL 7

@

RE109

12

DGPU_PWROK

PBTN_OUT# 14

TP_CLK 30 TP_DATA 30

CAPS_LED# 30 APUPWR_EN 52 ACOFF 45 FCH_PWROK 14

ACPRN 45

LID_SW# 30

VDDQ_PGOOD

VDDQ_PGOOD 47

12

EC_ON 46,49

ADAPTER_ID_ON# 43

PM_SLP_S5# 14

EC_MUTE# 34

FCH_PWR_EN 44

SYSON 47

EC_BKOFF# 27

PM_SLP_S3# 14

NOVO# 30

EC_TS_ON# 27

EC_FAN_SPEED 37 WLAN_WAKE# 33

NUM_LED# 30

delete VGA_AC_DET from UE1.Pin19 ,change to net name to WLAN_WAKE# .And change to VGA_AC_BATT control

AOAC_ON#

+3VALW_R

Follow Edge to change UE1.Pin120 from LAN_WAKE# to BATT_LEN# on 0927

BATT_LEN# for S5 plus function on 20130927

Follow Edge to change UE1.Pin29 from BATT_LEN# to VGA_AC_BATT on 0927

check with AMD one EC pin to add VGA_IMON,change VGA_IMON to APU_IMON on 1003

Follow Edge to change UE1.Pin78 from 1V_ALW_EN to IMVPPOK on 0927

DGPU_PWROK 12,51

add DGPU_PWROK to UE1.85

Follow Edge to change UE1.Pin97 from FCH_PWR_EN to APUPWR_EN

1 2

RE23 100K_0402_5%

+3VALW_R

1 2

LE1 BLM18PG181SN1D_06 03

1 2

LE2 BLM18PG1 81SN1D_0603

AOAC_ON# 33

1

CE4

0.1U_0402_10V7-K

2

EC_AGND

LAN_WAKE#

SUSP#

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK3 EC_SMB_DA3

EC_FAN_SPEED

EC_FAN_PWM

LPC_FRAME#

TP_CLK

TP_DATA

ON/OFF

LID_SW#

USB_ON#

SUSP#

SYSON

BATT_TEMP

ON/OFF

AC IN

ACPRN

EC_ON

EC_AGND

100K_0402_5%

1

2

RE5 10K_0402 _5%

RE18 100K_0402_ 5%

RE10 10K_0 402_5%

RE11 10K_0402_5 %@

RE7 10K_0402 _5%

RE12 4.7K_0402 _5%

RE13 4.7K_0402 _5%

RE35 10K_0402_5 %@

RE38 10K_0402_5 %

RE15 10K_0402_5%

RE19 100K_0402_ 5%

RE21 100K_0402_ 5%@

CE16 100P_0 402_50V8J@

CE18 1U_0 402_6.3V6K@

RE25 10K_0402 _5%

Mounted for EC mirror function on 2013/12/5

RE51

+3VALW_EC

CE5 1000P_0402_50V7K

1 2

@

1 2

RPC15

1 8 2 7 3 6 4 5

2.2K_0804_5%

SD30922018J

1 2

12

1 2

@

1 2

@

RE54

1 2

100K_0402_5%

EC_RSMRST#

12

Mounted for EC mirror function on 2013/12/5

@

+3VALW_R

+3VS

+3VL

+5VALW

+3VL

when mirror, RE45 RE47 RE48 RE49 mounted when no mirror, RE45 RE47 RE48 RE49 reserved

EC_SPI_CS1#

EC_SPI_SI

EC_SPI_SO

EC_SPI_CLK

A A

EC_MUTE#

@

12

RE45 0_0402_5%

@

12

RE47 0_0402_5%

@

12

RE48 0_0402_5%

@

12

RE49 0_0402_5%

Mounted RE43 for EC mirror function on 2013/12/5

when mirror, GPG2 pull high when no mirror, GPG2 pull low

Mounted RE43 for EC mirror function on 2013/12/5

@

12

RE43 10K_0402_5 %

12

RE46 10K_0402_5 %@

1 2

100K_0402_5%

RE44

5

SPI_CS1#

SPI_SI

SPI_SO

SPI_CLK

+3VL

+3VALW_R

SPI_CS1# 1 3

SPI_SI 13

SPI_SO 13

SPI_CLK 13

EMI/ESD

EC_A_RST#

1

CE1 220P_0402_50V7K

2

CLK_PCI_EC

4

1 2

RE2 10_040 2_5%@

10P_0402_50V8J

SYSON

1

CE2

2

0.1U_0402_10V7-K

@

+3VS

1

CE19

CE13

0.1U_0402_10V7-K

@

2

Add Board ID ,please check with Edge

3.3V +/- 5%

+3VL

RE52 10K_0402_5%

@

1 2

Board_ID

RE53 10K_0402_5%

@

1 2

3

Vcc

100K +/- 1%

RE33

Board ID

RE34

0K +/- 5%

0

8.2K +/- 5%

1

18K +/- 5%

2

33K +/- 5%

3

4.7K +/- 5%

4

24K +/- 5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

min

V V

0.216 V 0.250 V

0.436 V

0.712 V

0.612 V 0. 638 V 0.6 64 V5

2013/08 /08

AD_BID

0 V

LC Future Center Secret Data

2

V

AD_BID

0 V 0 V

0.503 V

0.819 V

0.148 V

Deciphered Date

typ

AD_BID

0.289 V

0.538 V

0.875 V

0.155 V0.141 V

2013/08 /05

Phasema x

SDV

Title

EC ITE8586LQFP

Size Document Number Rev

Custom

Date: Sheet of

ACLU7

ACLU7ACLU7

Monday, December 16, 2013

1

38 52

0.1

A

1 1

Load Switch +5VALW To +5VS +3VALW To +3VS

+3VALW

1

C162

@

1U_0402_6.3V6-K

2

2 2

+5VALW

1

2

+5VALW

C161

@

1U_0402_6.3V6-K

Load Switch

+5VS, C159 --> 1.5ms +3VS, C160 --> 2.5ms

VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm

3VSON

5VSON

U13

1

VOUT1_2

VIN1_1

2

VOUT1_1

VIN1_2

3

4

5

6 7

TPS22966DPUR_WSON14_2X3

ON1

VBIAS

ON2

VIN2_1 VIN2_2

VOUT2_2 VOUT2_1

GPAD

CT1

GND

CT2

1.1VS :4A

+1.1VALW to +1.1VS

C167

1

2

+VSB

1 2

100K_0402_5%

SUSP

3 3

For DisCharge

SUSP#38,47,48,50,51

10U_0603_6.3V6M

R161

13

D

2

Q21

G

S

2N7002KW_SOT323-3

+5VALW +0.675VS

12

R153

100K_0402_5%

SUSP

SUSP# SUSP

2N7002KDWH_SOT363-6

SB00000EO1J

61

D

2

Q44A

G

S

B

14

+3VS_LS

13

12

1 2

C160 1000P_0402_25V7-K

11

10

1 2

C157 2200P_0402_25V7-K

9 8

+5VS_LS

15

Update Load Switch +1.1VALW to +1.1VS to AON6414AL on 20130926

+1.1VALW +1.1VS

Need OPEN

J20

5

12

R160 120K_0402_5%

112

JUMP_43X118

AON6414AL_DFN8-5

U14

12

R149 22_0805_5%

34

DSQ44B

5

G

2N7002KDWH_SOT363-6

SB00000EO1J

2

@

1 2 3

4

1

C168

0.1U_0402_16V4Z

2

J9

@

112

JUMP_43X118

J10

@

112

JUMP_43X118

2

+5VS

1

2

C166

1

2

10U_0603_6.3V6M

+3VS

1

C159

0.1U_0402_10V7-K

2

C158

@

0.1U_0402_10V7-K

C

R164

1 2

0_0402_5%

1U_0402_6.3V6-K

R165

@

SUSP#

1 2

0_0402_5%

1U_0402_6.3V6-K

R164 and R165 to adjust 3VALW and 5VALW timing

+VDDIO to +VDDIO_RUN

C233

12

1

R162 470_0603_5%

@

2

.1U_0402_16V7K

13

D

Q22

2

SUSP

G

S

2N7002KW_SOT323-3

@

From FCH

+0.95VS +0.95VS_VDDR

D

3VSON

1

C146

2

5VSON

1

C147

2

Delete +3VALW To +3VALW_FCH on 20131001

E

Need OPEN

+1.35V_APU_VDDIO +1.35V_APU_VDDIO_RUN

112

JUMP_43X39

S

G

2

1

2

@

1

C234

D

13

0.1U_0402_10V7-K C128

@

2

.1U_0402_16V7K

+1.8VS +1.8VS_VDDA

+1.35V_DDR_VDDIOSUS +1. 35V_APU_VDDIO

R159

1 2

0_0805_5%

0.5A

@

D

@

S

12

R163 470_0603_5%

13

Q24

2

G

2N7002KW_SOT323-3

SUSP

J18

@

112

JUMP_43X118

J15

@

112

JUMP_43X118

SUSP

2

J11

Q27

LP2301ALT1G_SOT23-3

R154

1 2

0_0402_5%

+0.95VS_VDDP+0.95VS

Short +1.35V_DDR_VDDIOSUS & +1.35V_APU_VDDIO directly on 20130930

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

C

2013/08/08

LC Future Center Secret Data

Deciphered Date

D

2013/08/05

Title

DC V TO VS INTERFACE

Size Document Number Rev

C

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

E

39 52

0.1

1

2

3

4

5

A A

H7 HOLEA

1

PAD_CT6P5B5P0D4P0

H25 HOLEA

1

Pad_C6P0D3P3

PCH Plate

B B

C C

CPU Plate

H8 HOLEA

1

PAD_CT6P5B5P0D4P0

H26 HOLEA

1

Pad_C6P0D3P3

pad_sht7p0x6p65b10p66x9p9d2p8

H9 HOLEA

PAD_CT6P5B5P0D4P0

H1 HOLEA

1

H13 HOLEA

1

pad_cb8p0d7p0

1

PAD_CT6P5B5P0D4P0

PAD_CT6P0B7P0D2P3

H14 HOLEA

pad_ct6p0shapeb8p0x6p75d2p3

H2 HOLEA

1

H10 HOLEA

1

NH5 HOLEA

1

PAD_C2P3D2P3N

Close to H7

H3 HOLEA

1

H15 HOLEA

1

Pad_ct8p0b9p0d2p8

PAD_CT6P0shapeb10p04x10p0d2p8

H4 HOLEA

1

pad_ct6p0b7p0d2p3

NH6 HOLEA

1

PAD_O2P3X2P8D2P3X2P8N

H5 HOLEA

1

PAD_SHAPET8P8X8P0B9P0D2P8

H16 HOLEA

1

H17 HOLEA

pad_shapet6p8x8p0cb8p0d2p5

PAD_SHAPET8P8X8P0CB9P0D2P8

1

NH7 HOLEA

1

PAD_O2P3X2P8D2P3X2P8N

H6 HOLEA

1

H19 HOLEA

1

PAD_SHAPET5P0X6P0-D

H18 HOLEA

1

PAD_SHAPET5P0X6P0-U

NH1 HOLEA

1

PAD_C2P3D2P3N

H20 HOLEA

1

PAD_CT5P5B6P0D3P3

H22 HOLEA

1

PAD_CT5P5B6P0D3P3

H11 HOLEA

1

pad_ct6p0d4p3

H23 HOLEA

1

PAD_CT5P5B6P0D3P3

H12 HOLEA

1

Pad_ct6p0b8p0d4p6

H24 HOLEA

1

PAD_CT5P5B6P0D3P3

H21 HOLEA

1

CHASSIS1_GND

PAD_CT5P5B8P0D2P5

PCB Fedical Mark PAD

FD1

FD2

1

D D

1

FD4

FD3

1

FD5

FD6

1

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

4

2014/07/01

Title

SCREW

Size Document Number Rev

Custom

Monday, December 16, 2013

Date: Sheet of

ACLU7

ACLU7ACLU7

5

40 52

1.A

5

4

3

2

1

D D

AMD Kaveri Platform System power on G3 --> S5 --> S0

BTY Charger

Singnal

PBT

Power

RTC BTY

+RTCBATT

1

System Ready!!

EC_RSMRST#

C C

AMD FCH Bolton

BGA-656

24.5mm*24.5mm

B B

APU_PWROK

24

PLT_RST

25

APU_RESET

26

10

PBTN_OUT#

12

PM_SLP_S5#

13

PM_SLP_S3#

14

FCH_PWROK

23

FCH_S5

7

AMD APU Kaveri

BGA-631 32mm*29mm

11

ON/OFFBTN#

EC ITE IT8586E-CX

22

+VDD_CORE

21

+VDDNB_CORE

21

5

ACPRN

IMVPPOK

+3VL/+VL

9

+3VALW

PU14

VIN GATE

PU6

4

6

8

SYSON

15

SUSP#

17

3

B+

PU5

EC_ON

S5_1.1_EN

19

VDDAPWROK

APUPWR_EN

20

+VIN

+5VALW

PU10

PU7

U13

PU8

PU10

PU15

2

9

16

18

PU9

BTY

AC in

+1.1VALW

+1.35VS +0.675VS

+3VS +5VS

+1.5VS

+1.1VS

+1.8VS

21

+0.95VS

1.+RTCBATT

G3

2.+VIN

3.B+

4.+3VL/+VL

5.ACPRN

S5

6.EC_ON

7.FCH_S5

8.S5_1.1_EN

(BTY Charger to EC)

(EC to Power IC)

(FCH to EC)

(EC to Power IC)

9.+5VALW/+3VALW/+1.1VALW

10.EC_RSMRST#

11.ON/OFFBTN#

(EC to FCH)

(PBTN to EC)

12.PBTN_OUT#

13.PM_SLP_S5#

14.PM_SLP_S3#

15.SYSON

(EC to Power IC)

16.+1.35VS/+0.675VS

17.SUSP#

(EC to Power IC)

18.+3VS/+5VS

18.+1.5VS

S0

18.+1.1VS

18.+1.8VS

19.VDDAPWROK

20.APUPWR_EN

(Power IC to EC)

(EC to VRM)

21.+0.95VS

21.+VDD_VORE/+VDDNB_VORE

22.IMVPPOK

23.FCH_PWROK

24.APU_PWROK

25.PLT_RST

26.APU_RESET

(VRM to EC)

(EC to FCH)

(FCH to APU)

(EC to FCH)

(FCH to EC)

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2013/08/08

LC Future Cen ter Secret Data

Deciphered Date

2013/08/05

Title

Power sequence block

Size Document Number Rev

D

Date: Sheet of

Monday, December 16, 2013

1

ACLU7

ACLU7ACLU7

41 5 2

0.1

5

D D

C C

4

3

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/08

3

LC Future Center Secret Data

Deciphered Date

2013/08/05

2

Title

Virtual symbol

Size Docum ent Number Rev

B

Monday, December 16, 2013

Date: Sheet of

Monday, December 16, 2013

ACLU7

ACLU7ACLU7

1

42 52

0.1

5

4

3

2

1

PL28

HCB2012 KF-121T50_080 5

1 2

JDCIN1

1

ME@

2

3

4

5

D D

ACES_50 299-00501-003

C C

PF1

7A_24VD C_429007.W RML

ADAPTER _ID 3 8

+3VALW

12

PR79 750_060 3_1%

21

APDIN1APDINAPDIN

12

PC1

@

1000P_0402_50V7K

VIN

12

PR80 1M_0402 _5%

PL27

HCB2012 KF-121T50_080 5

1 2

PC2

470P_0402_50V7K

VIN

12

PC4

PC3

@

470P_0402_50V7K

1000P_0402_50V7K

JRTC1

FDK_ML1 220-TT28

PH1 under CPU botten side : CPU thermal protection at 92+-3 degree C

RTC_VCC VCCRTC+3VL

PR1

560_060 3_5%

12

1 2

PR4

560_060 3_5%

1 2

BAT_D

PD1

RB751V-4 0_SOD323-2

12

PD2

RB751V-4 0_SOD323-2

Recovery at 56 +-3 degree C

61

D

2

PR84

0_0402_ 5%

@

1 2

12

B B

PC45

0.1U_0402_25V6

S

1

2

ADAPTER _ID_ON#_G

G

PQ28A

2N7002K DWH_SOT36 3-6

ADAPTER _ID

1

PD6

AZ5425-0 1F_DFN1006P2 E2

2

PR89 1M_0402 _5%

12

61

D

2

G

S

2N7002K DWH_SOT36 3-6

ADAPTER _ID_ON# 38

PQ27A

+5VLP

MAINPWON38,46

SDV

2

PC12

@

0.1U_040 2_25V6-K

1

@

0_0402_ 5%

PR29

12

OTP_N_0 03

PU2

1

VCC

TMSNS1

2

GND

RHYST1

3

OT1

TMSNS2

4

RHYST2

OT2

G718TM1 U_SOT23-8

@

8

7

6

5

NTC_V_1

OTP_N_0 02

PR30

@

47K_040 2_1%

10K_040 2_1%

+3VALW

12

PR21

@

+3VL

12

PR18

13.7K_04 02_1%

12

PR82 0_0402_ 5%

1 2

12

@

PR19

61.9K_04 02_1%

12

100K_04 02_1%_NCP15W F104F03R C

SDV

PH1

NTC_V38

A A

Title

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/ 15

3

LC Future Center Secret Data

Deciphered Date

2013/08/ 15

2

Title

DCIN / RTC

Size Docu ment Number Rev

Custom

Date: Sheet of

Monday, December 16, 2013

G(AMD Beema)

G(AMD Beema)G(AMD Beema)

1

43 43

0.1

5

4

3

2

1

SDV

JBATT1

1 2

GND1 GND2

ME@

3 4 5 6 7

D D

SUYIN_200082 GR007G232ZR

1 2 3 4 5 6 7 8 9

EC_SMCA EC_SMDA

VMB2

BATT_TE MP_IN

PF2

8A_24V_ F1206HI8000V02 4T

1 2

PR16 100_040 2_1%

1 2

PR15 100_040 2_1%

PR23

100K_04 02_1%

1 2

PR27

10K_040 2_5%

+3VALW

VMB

EC_SMB_ CK1 38,45 EC_SMB_ DA1 38,45

BATT_TE MP 38,45

12

PC11

1000P_0 402_50V7K

PL29

HCB2012 KF-121T50_080 5

1 2

PL30

HCB2012 KF-121T50_080 5

1 2

12

PC10

0.01U_04 02_25V7K

BATT+

For 14

C C

P2

12

VMB2

12

PR44

220K_04 02_1%

@

12

PC18

B B

0.1U_0402_25V6

PR47

150K_04 02_1%

PC15

0.01U_04 02_25V7K

1 2

PR45

10K_040 2_1%

8

3

P

+_1

2

-_1

G

4

1 2

PR49

10K_040 2_1%

10M_040 2_5%

1 2

1

O1

PU3A

AS393MT R-G1_SO8

+3VL

BATT_LE N#38

+3VALW +3VALW

PR72

DC_UVP_ 2

2N7002K DWH_SOT36 3-6

100K_04 02_1%

10K_040 2_1%

1 2

PR41

100K_04 02_1%

1 2

5

G

PQ25B

+3VALW

PR50

1 2

PR52

PQ25A

2N7002K DWH_SOT36 3-6

PR42

100K_04 02_1%

1 2

34

D

S

2

G

BATT_OU T 45

ALW _PWRGD46,48,50

FCH_PW R_EN38

61

D

S

SDV

SUYIN_200082 GR007G232ZR

PR48

@

0_0402_ 5%

1 2

PR51

1K_0402 _1%

1 2

JBATT2

1 2 3 4 5 6

7 GND1 GND2

ME@

For 15

VSBP_1

12

VMB2

1 2 3

EC_SMCA

4

EC_SMDA

5

BATT_TE MP_IN

6 7 8 9

PD9

@

AZ5215-0 1F_DFN1006P2 E2

B+ +VSBP

2

G

PC19

@

1U_0402 _6.3V6K

PR46

22K_040 2_1%

1 2

VSBP_2

13

D

PQ5

S

2N7002K W_SOT323 -3

3

1

2

12

PC16

PR43

100K_0402_1%

0.22U_0603_25V7K

2

1

PR40

0_0603_ 5%

1 2

VSBP_3

TP0610K -T1-E3_SOT23-3

PD10

@

AZC199-0 2S.R7G_SOT23-3

@

13

12

2

PQ4

PJ1

JUMP_43 X39

2

112

PC17

0.1U_060 3_25V7-M

+VSB+VSBP

A A

Title

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/ 15

3

LC Future Center Secret Data

Deciphered Date

2013/08/ 15

2

Title

BATTERY CONN/OTP

Size Docu ment Number Rev

Custom

Date: Sheet of

Monday, December 16, 2013

G(AMD Beema)

G(AMD Beema)G(AMD Beema)

1

44 44

0.1

5

4

3

2

1

PR53

737_ACP

1 2

2

ACP

PU4

ILIM10BM#

737_ILIM

12

737_ACN

1

ACN

CMPIN

4

PR76

B+

4

3

1

2

3

CMPOUT

SRN12SRP

SRN_1

12

6.8_0603_5%

1 2

0.1U_0402_25V6-K

2

1

SDV

PC30

0.1U_0402_25V6-K

BQ24737_VDD

14

GND

BTST

REGN

HIDRV

PHASE

LODRV

PAD

13

SRP_1

12

PR77

10_0603_5%

PC42

PC43

0.1U_0402_25V6-K

17

16

18

19

15

21

PC34 1U_0603_25V6M

1 2

PD5

RB751V-40_SOD323-2

12

BST_CHG

2

PC41

0.1U_0402_25V6-K

1

SDV

PR66

2.2_0603_5%

1 2

PC20

@

0.1U_0402_25V6-K

0.047U_0603_25V7-K

DH_CHG

LX_CHG

DL_CHG

PQ8

AO4407AL_SO8

1 2

PR56

PD3

1SS355_SOD323-2

5

PACIN_N

12

PR62

1M_0402_5%

PL3

1 2

12

PR71

2.2_0805_5%

12

PC40

1500P_0402_50V7K

3 6

ACOFF-1

1 2

1SS355_SOD323-2

PC33

0.1U_0402_25V6-K

SDVSD V

2

PC25

PC26

1 2

4.7U_0805_25V6-K

PC27

1 2

4.7U_0805_25V6-K

2N7002KDWH_SOT363-6

PQ11

AO4466L_SO8

PQ12

AO4466L_SO8

1 2

1

PC36

12

@

PQ26B

4

PC28

4

2200P_0402_50V7K

6

578

123

6

123

DISCHG_G

47K_0402_1%

1 2

PR57 10K_0402_1%

1 2

DISCHG_G-1

34

D

G

S

4.7UH_PCMB063T-4R7MS_5.5A_20%

8 7

5

4

VIN

PR58 200K_0402_1%

1 2

PACIN_P

PD4

61

D

2

1

CHG

2

S

PR70

0.01_1206_1%

2

PACIN737_VCC

G

PQ26A

2N7002KDWH_SOT363-6

4

3

12

PC38

PC39

10U_0805_25V6K

BATT+

12

SDV

737_SRP

737_SRN

co-work with EE(Neil) for layout reserve.

B+

SDV

P2 P3

PQ6

AO4407AL_SO8

8

D D

C C

SDV

B B

VIN

12

PR54

200K_0402_5%

P2_G1

34

D

5

G

S

ACOFF38

BATT_OUT

PR85

@

0_0402_5%

BATT_TEMP38,44

1 2

7

5

PQ9

LTA044EUBFS8TL_UMT3F-3

2

P2_G2

13

2

PQ30B

2N7002KDWH_SOT363-6

47K_0402_1%

1 2

PACIN

PR68

10K_0402_5%

1 2

ACOFF-1

5

G

12

S

PR73

1M_0402_5%

1 2 36

4

1 3

PQ10 LTC015EUBFS8TL_UMT3F-3

PR60

68K_0402_1%

PR63

34

D

5

G

PACIN_G

61

D

2

G

S

PQ28B

2N7002KDWH_SOT363-6

SDV

2

1

PC24

0.1U_0402_25V6-K

2N7002KDWH_SOT363-6

12

PR55 200K_0402_1%

P2-1

12

P2-2

34

DSPQ29B

2N7002KDWH_SOT363-6

SDV

EC_SMB_CK138,44

EC_SMB_DA138,44

PQ29A

PQ7

SI4483_SO8

1 2 3 6

4

2200P_0402_50V7K

12

PR59

20K_0402_1%

61

D

2

G

S

PQ30A

2N7002KDWH_SOT363-6

PR65

59K_0402_1%

1 2

PC35

0.1U_0402_25V6-K

1 2

8 7

5

PC22

1 2

SDV

BATT_OUT 44

VIN

12

PR67

0_0402_5%

1 2

ADP_I38

100P_0402_50V8J

+3VALW

HCB2012KF-121T50_0805

1 2

@

P2

1U_0603_25V6M

PR64

390K_0603_1%

PR69

0_0402_5%

ADP_I

PC37

PL34

1 2

PL33

1 2

PC21

10U_0805_25V6K

0.1U_0402_25V6-K

10_1206_5%

PC31

12

737_ACDET

ACPRN

737_SCL

737_SDA

1 2

40.2K_0402_1%

316K_0402_1%

1 2

PC23

@

PC29

0.1U_0402_25V6-K

PR61

12

6

5

9

8

7

PR74

PR78

1 2

10U_0805_25V6K

ACDET

ACOK

SCL

SDA

IOUT

90.9K_0402_1%

0.01_1206_1%

1

2

1

PC32

20

VCC

BQ24737RGRR_VQFN20_3P5X3P5

11

BM#

12

PR75

2

BQ24737_VDD

+3VL

12

PR83

PR81

10K_0402_1%

1 2

ACPRN38

A A

ACPRN

PQ27B

2N7002KDWH_SOT363-6

5

10K_0402_1%

PACIN

12

34

D

5

G

S

PR88 12K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2013/08/15

LC Future Center Secret Data

Deciphered Date

SDV

2013/08/15

2

PC72

1

@

0.1U_0402_25V6-K

2

PC133

1

@

0.1U_0402_25V6-K

2

PC71

@

PC134

@

PC126

PC125

1

@

0.1U_0402_25V6-K

2

PC135

PC136

1

@

0.1U_0402_25V6-K

Title

CHARGER

Size Document Number Rev

C

Monday, December 16, 2013

Date: Sheet of

2

PC127

1

@

0.1U_0402_25V6-K

2

PC163

1

@

0.1U_0402_25V6-K

PC128

PC129

1

@

0.1U_0402_25V6-K

G(AMD Beema)

G(AMD Beema)G(AMD Beema)

1

2

1

2

PC130

PC131

PC132

1

@

0.1U_0402_25V6-K

45 45

1

@

0.1U_0402_25V6-K

0.1

@

0.1U_0402_25V6-K

5

4

3

2

1

D D

B+

EC_ON

MAINPWON

RB751V-40_SOD323-2

@

112

JUMP_43X79

PR92

0_0402_5%

1 2

PD14

PJ3

2

12

PC46

12

0.1U_0402_25V6

PC53

@

0.1U_0402_25V6

12

PC250

PC255

10U_0805_25V6K

2200P_0402_25V7-K

12

SDV

12

PR91

PC47

@

1M_0402_5%

10U_0805_25V6K

12

PR94

1M_0402_5%

SDV

C C

B+

@

PJ7

2

112

JUMP_43X79

PR99

0_0402_5%

B B

EC_ON38,49

MAINPWON38,43

1 2

PD13

RB751V-40_SOD323-2

0.1U_0402_25V6

PC66

12

PC256

PC57

0.1U_0402_25V6

12

@

12

PC59

PC58

10U_0805_25V6K

2200P_0402_25V7-K

12

PR101

1M_0402_5%

1U_0603_25V6M

+3V_VIN

+3VALW_FB

PC61

1 2

+5V_VIN

+5VVCC

+5VFB

PU5

7

EN2

8

IN

9

GND

1

EN1

3

FB

PU6

8

9

5

1

3

2

+3V_PWRGD

PG

PR280

2.2_0603_5%

1 2

6

BS

10

+3VLX

LX

4

+3VALW_P+3VALW_EN

OUT

100mA

SY8206BQNC_QFN10_3X3

5

LDO

12

2

IN

GND

VCC

EN

FB

+5V_PWRGD

PG

2.2_0603_5%

1 2

6

BS

10

+5VLX

LX

4

+5VALW_P+5VALW_EN

OUT

100mA

SY8208CQNC_QFN10_3X3

7

LDO

+3VLP

PC54

4.7U_0603_6.3V6K

PR281

12

0.1U_0603_25V7-M

1 2

1

PTP1 PAD

0.1U_0603_25V7-M

+5VLP

PC67

4.7U_0603_6.3V6K

PC48

1 2

PL4

2.2UH_PCMB063T-2R2MS_8A_20%

1 2

PR93

@

4.7_0603_5%

1 2 12

PC55

@

680P_0402_50V7K

PC56

1 2

0.01U_0402_25V7K

PC60

PL5

3.3UH_PCMB063T-3R3MS_6.5A_20%

1 2

PR100

@

4.7_0603_5%

1 2 12

PC68

@

680P_0402_50V7K

PC69

6800P_0402_25V7-K

1 2

PR95

1 2

1K_0402_1%

PR102

1K_0402_1%

1 2

12

SDV

+3VALW_P

12

PC50

PC49

22U_0805_6.3V6M

12

PC51

22U_0805_6.3V6M

12

PC62

22U_0805_6.3V6M

12

PC254

PC52

PC63

PC253

22U_0805_6.3V6M

0.1U_0402_25V6

2200P_0402_25V7-K

12

PC65

PC64

22U_0805_6.3V6M

+5VALW_P

12

PC252

JUMP_43X79

12

PC251

0.1U_0402_25V6 2200P_0402_25V7-K

@

PJ4

112

2

PJ8

2

JUMP_43X118@

+3VALW TDC:6A OCP:8A

+3VALW

PJ5

@

JUMP_43X39

2

112

+5VALW TDC:6.5A OCP:11A

+5VALW

112

+3VL+3VLP

+3VALW

PR96

@

PR97

0_0402_5%

A A

+3V_PWRGD

+5V_PWRGD

1 2

PR98

0_0402_5%

1 2

5

@

100K_0402_5%

@

1 2

ALW_PWRGD 44,48,50

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2013/08/15

LC Future Center Secret Data

Deciphered Date

2

2013/08/15

Title

PWR_3VALW/5VALW

Size Document Number Rev

C

Date: Sheet of

G(AMD Beema)

G(AMD Beema)G(AMD Beema)

Monday, December 16, 2013

46 46

1

46 46

0.1

A

1 1

PJ13

B+

+1.35VP

2

JUMP_43X79

@

112

B+_1.35V

12

PC74

PC73

0.1U_0402_25V6

2200P_0402_25V7-K

12

PC75

PC76

10U_0805_25V6-K

PQ13

FSW=285KHz TDC:11A OCP:13A

2 2

SDV

+1.35VP

12

PC80

0.1U_0402_25V6

2200P_0402_25V7-K

1

12

+

PC82

PC81

2

330U_2.5V_M

10K_0402_1%

12

PR109

1

470P_0402_50V7K

PR110

7.87K_0402_1%

2

12

PC84

@

PL6

0.68UH_PCMB063T-R 68MS_16A_+-20%

1 2

PC86

@

680P_0402_50V7K

AON6414AL_DFN

PR107

4.7_0603_5%@

1 2

12

123 5

B

4

PQ14

AON6414AL_DFN

4

+3VALW

PC79

1 2

0.22U_0603_25V7K

PR106

2.2_0603_5%

1 2

DH_1.35V

LX_1.35V

DL_1.35V

PR103

100K_0402_1%@

12

PR104

100K_0402_1%

1 2

14

11CS13

PGND

18

BOOT

17

UGATE

16

PHASE

RT8231AGQW_WQFN20_3X3

15

LGATE

5

VDDQ

FB

6

PR105 205K_0402_1%

12

C

PJ10

2

JUMP_43X118@

PJ11

2

JUMP_43X118@

PJ12

12

+1.35VP

PC70

10U_0603_6.3V6M

2

JUMP_43X39

@

D

112

+1.35V_DDR_VDDIOSUS+1.35VP

+0.675VS+0.675VSP

+0.675VSP

12

+1.35VP

+0.675VSP

20

19

S3

VTT

PAD

VTTGND

VTTSNS

GND

VTTREF

VDD

PGOOD

10

21

1

2

+0.675VSP

3

4

VTTREF_0.675V

12

PR111

100K_0402_1%

1 2

PR108

5.1_0603_5%

1

PC85 1U_0402_6.3V6K

2

12

+5VALW

+3VALW

VID

VLDOIN

PU7

S5

TON

8

7

9

S5_1.35V

S3_1.35V

TON_1.35V

12

PC77

PC78

0.1U_0402_10V6-K

10U_0603_6.3V6M

VTTREF_0.675V

12

PC83

0.047U_0402_16V7K

+0.675VSP TDC:1.3A

FB_1.35V

B+_1.35V

3 3

PR113 0_0402_5%

SUSP#38,39,48,50,51

SYSON38

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

1 2

0_0402_5%@

1 2

0_0402_5%

PR114

PR115

PR112

887K_0402_1%

12

2013/08/01

1 2

S3_1.35V

PC87

0.1U_0402_10V6-K

S5_1.35V

PC88

0.1U_0402_10V6-K

LC Future Center Secret Data

Deciphered Date

C

PR819 0_0402_5%

12

VDDQ_PGOOD 38

2014/08/01

Title

+1.35VP/+0.675VSP

Size D ocument Number Rev

Custom

Date: Sheet of

Monday, December 16, 2013

AAVE1

AAVE1AAVE1

D

47 47

0.1

A

B

C

D

1 1

SDV

PC90

@

4.7U_0603_6.3V6K

1 2

PR118

@

0_0402_5%

1U_0402_6.3V6K

+3VALW

300mA

PR116

0_0603_5%

1 2

@

12

PC89

@

1.5VS_VIN

EN_1_5VSPSUSP#

PC92

0.1U_0402_10V6-K

+5VALW

12

@

6 5 9

8 7

12

PR120

100K_0402_5%

PU8

@

VCNTL VIN

VOUT1

TP

VOUT2

EN POK

FB

GND

1

APL5930KAI-TRG_SO8

@

+1.5VSP

3 4

2

1.5VS_FB

12

PR117

21.5K_0402_1%

12

PR119

24K_0402_1%

@

300mA

12

PC91

@

10U_0603_6.3V6M

VFB=0.8V Vo=VFB*(1+PR613/PR615) OCP:Min 4A

PJ15

2

JUMP_43X39

@

112

+1.5VS+1.5VSP

+3VS

PR121

@

SDV

B+_0.95VS

12

PC95

1 2

100K_0402_5%

0.1U_0402_25V6

PR125

@

0_0402_5%

1 2

PR122

0_0402_5%

1 2

12

PC96

10U_0805_25V6K

12

1M_0402_5%

PC97

10U_0805_25V6K

0.95VS_LIMT

PR126

12

PC93

0.1U_0402_10V6-K

@

+3VALW

1 2

0.95VS_EN

8

IN

9

GND

3

ILMT

SYX198DQNC

2

PG

PR129

10K_0402_5%

PU9

12

PR142

1M_0402_5%

1

PR123

EN

0_0603_5%

1 2

6

BS

10

LX

4

FB

7

BYP

5

0.95VS_LDO

LDO

12

PC105

4.7U_0603_6.3V6K

0.95VS_LX

+3VALW

12

PC106

4.7U_0603_6.3V6K

PC94

0.1U_0603_25V7K

1 2

PL7

0.68UH_PCMB063T-R68MS_16A_+-20%

1 2

PR124

@

4.7_0603_5%

1 2

SNUB_0.95V

12

680P_0402_50V7K

@

0.95VS_FB

PC108

12

PC107

330P_0402_50V8J

PR128

1 2

1K_0402_1%

12

PR127 20K_0402_1%

12

PR130

34K_0402_1%

@

12

PC99

PC98

22U_0805_6.3V6M

12

PC100

PC101

22U_0805_6.3V6M

12

PC102

22U_0805_6.3V6M

12

PC124

22U_0805_6.3V6M

+0.95VSP

PC103

0.1U_0402_25V6

+0.95VSP TDC:9.5A OCP:12A

12

PC104

2200P_0402_25V7-K

PJ17

2

JUMP_43X118

+0.95VSP

@

112

+0.95VS

2 2

ALW_PWRGD44,46,50

SUSP#38,39,47,50,51

PJ16

2

B+

112

JUMP_43X79

@

SDV

+3VALW

3 3

Current limit s etting pin. The current limit is set to 8A, 12A or 16A when this pin i s pull low, flo ating or pull high re spectively.

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

A

B

2013/08/15

LC Future Center Secret Data

Deciphered Date

C

2013/08/15

Title

+1.35VS_VGA/+1.5VS

Size Document Number Rev

C

Date: Sheet of

G(AMD Beema)

G(AMD Beema)G(AMD Beema)

Monday, December 16, 2013

D

48 48

0.1

5

PR131

0_0402_5%

D D

S5_1.1V_EN38

1 2

4

3

2

1

112

1 2

1K_0402_1%

PR132

@

12

PC111

10U_0805_25V6-K

PR136 0_0402_5%@

1 2

PR137

12

100K_0402_5%

100K_0402_1%

1 2

12

PC112

0.1U_0402_25V6

@

PR143

1 2

PR138 0_0402_5%

12

PC109

@

0.1U_0402_10V6-K

8

9

3

2

1M_0402_5%

1 2

IN

GND

PU10

ILMT

SYX198DQNC

PG

PR133

EN

BS

LX

FB

BYP

LDO

1

6

10

4

7

5

PC120

BS_1.1VS

SW_1.1VS

FB_1.1VS

12

4.7U_0603_6.3V6K

PC113

12

4.7U_0603_6.3V6K

PR134

0_0603_5%

1 2

+3VALW

SDV

PC110

0.1U_0603_25V7K

1 2

PL8

0.68UH_PCMB063T-R68MS_16A_+- 20%

1 2

PR135

4.7_0603_5%@

1 2 12

PC121

@

680P_0402_50V7K

12

PC122

330P_0402_50V7-K

1 2

PR140 1K_0402_1%

1 2

12

PR139 100K_0402_1%

PR141 115K_0402_1%

+1.1VALWP FSW=800KHz TDC:5A OCP:8A

+1.1VALWP

1

2

PC115

PC114

22U_0805_6.3V6-M

1

2

PC116

22U_0805_6.3V6-M

12

2

PC117

PC118

PC119

0.1U_0402_25V6

2200P_0402_25V7-K

22U_0805_6.3V6-M

PJ19

2

112

JUMP_43X79@

+1.1VALW+1.1VALWP

EC_ON38,46

PJ18

B+

C C

B B

2

JUMP_43X79@

+3VALW

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/01

3

LC Future Center Secret Data

Deciphered Date

2014/08/01

2

Title

+1.1VALWP

Size Docum ent Number Rev

B

Monday, December 16, 2013

Date: Sheet of

Monday, December 16, 2013

AAVE1

AAVE1AAVE1

1

49 49

0.1

5

4

3

2

1

+3VS

D D

PR296

0_0402_5%

VDDAPWROK38,52

1 2

+3VALW

1

12

2

PC259

PC261

C C

SDV

0.1U_0402_10V6-K 2200P_0402_50V7K

ALW_PWRGD44,46,48

SUSP#38,39,47,48,51

B B

1

PC249

PC257

2

22U_0805_6.3V6-M

@

22U_0805_6.3V6-M

PR287

0_0402_5%

1 2

PR282

0_0402_5%

1 2

PR286

1M_0402_5%

12

PR255 100K_0402_1%

+1.8VS

SY8032ABC_SOT23-6

4

IN

5

PG

FB6EN

@

12

PC260

0.1U_0402_10V6-K

1 2

LX

GND

PU15

EN_1.8VSP

3

2

1

1.8VSP_LX

1UH_PH041H-1R0MS_3.8A_20 %

12

PL19

1 2

PR284

@

4.7_0603_5%

PC263

@

680P_0402_50V7-K

12

PR285 20K_0402_1%

12

PR283 10K_0402_1%

12

PC266

68P_0402_50V8J

1

PC262

2

22U_0805_6.3V6-M

+1.8VSP

1

12

PC264

2

PC265

0.1U_0402_25V6

22U_0805_6.3V6-M

PJ20

2

JUMP_43X39

@

12

PC123

PC258

2200P_0402_50V7K

112

TDC: 1 A OCP: 4.5 A

+1.8VSP

2200P_0402_25V7-K

+1.8VS

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/15

3

LC Future Center Secret Data

Deciphered Date

2013/08/15

2

Title

+1.05VS/+1.05VS_VGA

Size Docum ent Number Rev

B

Monday, December 16, 2013

Date: Sheet of

Monday, December 16, 2013

G(AMD Beema)

G(AMD Beema)G(AMD Beema)

1

50 50

0.1

5

4

3

2

1

+VGA1_B+

PL25

DIS@

HCB2012KF-121T50_0805

1 2

12

PC138

PC139

10U_0805_25V6K

DIS@

0.36UH_PCMB063T-R36MS_20A_20%

PR163

DIS@

PR164

DIS@

PR165

DIS@

+VGA2_B+

HCB2012KF-121T50_0805

12

PC149

10U_0805_25V6K

DIS@

PR182

10K_0402_1%

1 2

ISEN2

PR183

3.65K_0402_1%

1 2

VSUM+

PR180 10_0402_1%

1 2

VSUM-

PL10

DIS@

1 2

SDV

PL21

DIS@

1 2

PL11

DIS@

1 2

DIS@

0.36UH_PCMB063T-R36MS_20A_20%

DIS@

ISEN1

VSUM+

VSUM-

DIS@

PR178

4.7_0603_5%

1 2

12

PC154 1000P_0402_50V7-K

SDV

PC147

0.1U_0402_25V6

PC137

0.1U_0402_25V6

DIS@

10K_0402_1%

1 2

3.65K_0402_1%

1 2

10_0402_1%

1 2

12

PC148

DIS@

D D

1 2

+3VS_VGA

SDV

12

PR86

@

10K_0402_5%

GPU_VR_HOT#

+1.8VS_VGA

C C

+3VS_VGA

DGPU_PWREN

SUSP#38,39,47,48,50

PR175

DIS@

27.4K_0402_1%

1 2

DIS@

1 2

6277_NTC_1

12

PR179

10.7K_0402_1%

B B

A A

PH2

470K_0402_3%_NCP15WM474E03RC

DIS@

PC167 .1U_0402_10V6-K@

PR298 0_0402_5%DIS@

PR299 0_0402_5%@

1 2

DIS@

0_0402_5%

62771NTC

+5VS

ISEN2

ISEN1

12

PR170

PR172

PR184

10K_0402_5%

12

@

SDV

PR181

10K_0402_5%

@

VSUM-

PH3 10K_0402_NTC

VSUM+

SVI2_SVC_P

SVI2_SVD_P

1 2

PC290

PC291

@

10P_0402_50V8J

PR161 100K_0402_1%DIS@

1 2

PR162 100K_0402_1%DIS@

1 2

12

DIS@

PR171

0_0402_5%

PR176

130K_0402_1%

DIS@

12

1 2

PR288 0_0402_5%DIS@

SVI2_SVC18

PR166 0_0402_5%DIS@

PR173 0_0402_5%DIS@

SVI2_SVD18

PR289 0_0402_5%DIS@

SVI2_SVT18

PLT_RST_VGA#17,18

DIS@

1 2

PC146

.1U_0402_10V6-K

PR822

1.91K_0402_1%

DIS@

+3VS_VGA

SDV

SVI2_SVC_P

VRHOT_L

SVI2_SVD_P

ENABLE

PWROK

VGA_IMON

1 2

@

0_0402_5%

PU12

1

NTC_NB

2

IMON_NB

3

SVC

4

VR_HOT_L

5

SVD

6

VDDIO

7

SVT

8

ENABLE

9

PWROK

10

IMON

PC150

0.1U_0402_25V6-K

DIS@

SDV

PC157

0.1U_0402_25V6DIS@

1 2

PR193

@

10K_0402_5%

12

PC164

0.033U_0402_16V7K

62771NTC

DIS@

12

@

0.22U_0402_10V6K

12

PR190

2.61K_0402_1%

DIS@

1 2

PC155

DIS@

12

PC156

0.22U_0402_10V6K

12

PR192

11K_0402_1%

DIS@

0.033U_0402_16V7K

DIS@

PC166

12

PR154

PR186

1 2

1.02K_0402_1%

12

PC162

0.22U_0402_10V6K

@

12

PR155

10K_0402_5%

37

38

39

40

FB_NB

VSEN_NB

ISUMP_NB

ISUMN_NB

ISL62771HRTZ_TQFN40_5X5

ISUMP14ISEN212NTC

13

11

SDV

DIS@

1 2

@

1000P_0402_50V7K

36

PC177

VGA_CORE_SUMN

DIS@

PC161

DIS@

12

DIS@

PR156

PR157

10K_0402_5%

31

32

33

34

35

COMP_NB

16

VGA_CORE_SEN

BOOT_NB

LGATE_NB

PHASE_NB

UGATE_NB

PGOOD_NB

VSEN

BOOT2

UGATE2

PHASE2

LGATE2

VDDP

LGATE1

PHASE1

UGATE1

BOOT1

RTN17ISUMN15ISEN1

COMP

FB18PGOOD

19

20

62771_FB

62771_COMP

VGA_VSS_SEN

PR158

DIS@

0_0402_5%

12

30

BOOT2

29

UGATE2

28

PHASE2

27

LGATE2

26

62771_VDDP

25

62771_VDD

VDD

24

LGATE1

23

PHASE1

22

UGATE1

21

BOOT1

PR174

@

TP

41

100K_0402_1%

DIS@

0_0402_5%

PR211

PR290

12

DIS@

12

PR169

DIS@

1_0603_5%

1 2

12

PC144

1U_0603_25V6M

DIS@

+3VS

+3VS_VGA

DGPU_PWROK 12,38

12

SDV

PC159 100P_0402_50V8J

PR189

DIS@

30K_0402_1%

1 2

PR194

2K_0402_1%

12

DIS@

1 2

150P_0402_50V8-J

6277_FB_1

DIS@

12

6277_FB_36277_FB_3

VDDC_SEN 19

VDDC_RTN 19

PC160

DIS@

1 2

PC165

680P_0402_50V7K

1 2

PR187

32.4K_0402_1%

1 2

DIS@

330P_0402_50V8J

12

100P_0402_50V8J

12

PC158

1 2

10_0402_1%

330P_0402_50V8J

10_0402_1%

DIS@

62771_FB_2

PR188

DIS@

619_0402_1%

1 2

+VGA_CORE

PR293

DIS@

1 2

DIS@

PC176

PR294

DIS@

1 2

PR185

DIS@

499_0402_1%

1 2

DIS@

0_0402_5%

DIS@

0_0402_5%

PR291

PR292

PC145

1U_0603_25V6M

DIS@

@

PR168 0_0402_5%

UGATE1

PHASE1

BOOT1

LGATE1

DIS@

12

PR159

2.2_0603_5%

1 2

+5VS

UGATE2

PHASE2

BOOT2

LGATE2

DIS@

1 2

PC140

0.22U_0603_25V7K

PR177

DIS@

2.2_0603_5%

1 2

0.22U_0603_25V7K

DIS@

4

1 2

PC151

DIS@

PQ15

DIS@

AON6414AL_DFN

123 5

PQ16

AON6554_DFN

PR160

4.7_0603_5%

1 2

12

PC143

DIS@

123 5

1000P_0402_50V7-K

SDV

PQ17

4

DIS@

AON6414AL_DFN

123 5

PQ18

AON6554_DFN

DIS@

123 5

B+

+VGA_CORE

TDC :20A OCP :35A

+VGA_CORE

1

12

+

PC142

PC141

2

@

PC268

2

330U_D2_2V_Y

0.1U_0402_25V6

DIS@

B+

1

12

+

PC152

PC267

PC153

2

330U_D2_2V_Y

DIS@

12

PC173

PC172

22U_0805_6.3V6M

@

0.1U_0402_25V6

DIS@

12

PC174

DIS@

PC175

22U_0805_6.3V6M

DIS@

22U_0805_6.3V6M

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

2013/08/15

LC Future Center Secret Data

Deciphered Date

2

2013/08/15

Title

+VGA_CORE

Size Document Number Rev

Custom

G(AMD Beema)

G(AMD Beema)G(AMD Beema)

Monday, December 16, 2013

Date: Sheet of

1

51 51

0.1

5

+5VS

12

PR195 0_0402 _5%

12

10.7K_0 402_1%

1 2

PR269 1K_040 2_1%

PR273

220_04 02_5%@

12

0.22U_0402_10V6K

PR218

12

SDV

12

.1U_0402 _10V6-K

@

PC186

1 2

0.1U_0402_25V6-K

EN_+VDD

PC228

@

12

0.22U_0402_10V6K

VSUMP_NB

VSUMN_NB

PC206

+1.35V_A PU_VDD IO_RUN

APU_IMON38

+VDDNB_CORE

PC184

VDDNB_SENSE7

12

PR208

2.61K_0 402_1%

PH4

10K_04 02_NTC

1 2

PR216

27.4K_0 402_1%

1 2

PH7

470K_0 402_3% _NCP15 WM474E 03RC

VR_HOT#38

PR226

10K_04 02_1%

ISEN2_A PU

ISEN1_A PU

12

PC194

PR210

11K_04 02_1%

PC197

1000P_ 0402_5 0V7K

+1.35V_APU_VDDIO_RUN

1 2

12

PR295

0_0402 _5%

PR243

0_0402 _5%

12

PR244

0_0402 _5%

VSUM-_APU

PR254

2.61K_0 402_1%

PH6

10K_04 02_NTC

VSUM+_APU

.1U_0402_10V6-K

12

APU_PWROK7,12

PR236

130K_0402_1%

PR197

100_04 02_1%

1 2

PR203

0_0402 _5%

1 2

12

1 2

APU_SVC7

APU_SVD7

APU_SVT7

EN_+VDD

12

PC219

12

1 2

PC195

.1U_0402_10V6-K

1 2

0.1U_0402_25V6-K

SDV

12

0.22U_0402_10V6K

12

PR260

11K_0402_1%

ISEN2_NB

D D

C C

PRE-PWR OK METAL VID C ODES

0

110 0.9V

APUPWR_EN38

VDDAPWROK38,50

B B

ISEN1_NB

VSUMN_NB

PR225

130K_0 402_1%

SVDSVC

Boot Voltage

00

1.1V

1.0V(Default)

11

0.8V

PR245 0_0402 _5%

1 2

PR247

10K_04 02_1%@

+1.35V_APU_VDDIO_RUN

12

@

PR267

@

PR268

1K_040 2_1%

1K_0402_1%

APU_SVC _P

APU_SVD _P

APU_SVT _P

A A

PR271

@

220_04 02_5%

12

PR272

@

220_0402_5%

PC192

1000P_ 0402_5 0V7K

590_04 02_1%

1 2

PC199

@

0.22U_04 02_10V 6K

PR219 0_0402 _5% PR222 0_0402 _5% PR227 0_0402 _5% PR228 0_0402 _5% PR231 0_0402 _5% PR233 0_0402 _5% PR235 0_0402 _5%

PR297

27.4K_0 402_1%

PC213

12

470K_0 402_3% _NCP15 WM474E 03RC

PR239

10.7K_0 402_1%

12

@

PR246

PC220

0.22U_0402_10V6K

12

PC236

.1U_0402_10V6-K

680P_0 402_50 V7K

SDV

1 2

@

SDV

PR212

10K_04 02_5%

1 2

10K_0402_5%

PC182

100P_0 402_50 V8J

PR214

PH5

0.1U_040 2_25V6

12

PC237

12

1.21K_0 402_1%

1 2

PC187

12

@

12

+5VS

PC222

1 2

.1U_0402_10V6-K

PR198

1 2

ISEN2_NB

IMON_NB

APU_SVC _P

APU_SVD _P

APU_SVT _P

10K_04 02_5%

2K_040 2_1%

1 2

PR204

499_04 02_1%

ISEN1_NB

PR240

0_0402 _5%

PR241

0_0402 _5%

1 2

ISEN2_6 277A

ISEN1_6 277A

PR259

PR196

12

PU14

1

2

3

4

5

6

7

8

9

10

11

12

49

12

@

PR251 619_04 02_1%

1 2

@

4

1 2

PR199

137K_0 402_1%

1 2

48

ISEN2_NB

NTC_NB

IMON_NB

SVC

VR_HOT_L

SVD

VDDIO

SVT

ENABLE

PWROK

IMON

NTC

PAD

ISEN3

13

SDV

1 2

12

PC232

0.22U_04 02_10V 6K

PC183

150P_0 402_50 V8-J

1 2

PR200

32.4K_0 402_1%

PC188

47P_04 02_50V 8J

PR213

@

1 2

45

44

43

42

47

ISEN1_NB

41

46

FB_NB

VSEN_NB

FCCM_NB

COMP_NB

ISUMP_NB

ISUMN_NB

PGOOD_NB

ISL6277AHRZ_QFN48_6X6

RTN

ISEN214ISEN115ISUMN17VSEN18ISUMP16FB220FB21COMP22PGOOD

19

6277A_RTN

6277A_VSEN

6277A_FB2

6277A_ISUMN

1 2

100P_0 402_50 V8J

12

@

SDV

PC233

330P_0402_50V8J

12

PC238

1000P_ 0402_5 0V7K

57.6K_0402_1%

40

6277A_FB

PWM2_NB

@

39

LGATEX

6277A_COMP

PC227

PGOOD_ NB

37

PHASEX38UGATEX

UGATE2

PHASE2

LGATE2

PWM_Y

LGATE1

PHASE1

UGATE1

23

24

1 2

PR256

1.5K_04 02_1%

10_040 2_1%

0_0402 _5%

10_040 2_1%

BOOTX

BOOT2

VDDP

BOOT1

PR264

PR265

PR266

PR270

PWM2_NB

LGATE_ NB1

PHASE_NB 1

UGATE_NB 1

VIN

VDD

1 2

499_04 02_1%

1

36

35

34

33

32

31

30

29

28

27

26

25

+3VS

PR252

12

PTP2 PAD

BOOT_NB 1

BOOT2_ APU

UGATE2_ APU

PHASE2_ APU

LGATE2 _APU

6277A_VDDP

6277A_VDD

LGATE1 _APU

PHASE1_ APU

UGATE1_ APU

BOOT1_ APU

12

PR242 100K_0 402_1%

10P_04 02_50V 8J

1 2

PR257

137K_0 402_1%

PR262

2K_040 2_1%

+VDD_CORE

PC218

1 2

PC223

47P_04 02_50V 8J

1 2

150P_0 402_50 V8-J

12

VDD_SENSE 7

VSS_SENSE 7

PR221

0_0603 _5%

12

PC205

0.22U_06 03_25V 7K

1 2

PR232

1_0603 _5%

1 2

PC211

1U_0603_10V6K

IMVPPOK 38

1 2

PR250

32.4K_0 402_1%

PC230

1 2

PC235

680P_0 402_50 V7K

3

PQ31

PR201

2.2_060 3_5%

1 2

PQ35

PC221

AON6414 AL_DFN

1 2

0.22U_06 03_16V 7K

BOOT_NB1_R

1 2

2.2_060 3_5%

PHASE_NB 2

LGATE_ NB2

4

PQ37

PC245

0.22U_06 03_16V 7K

PR220

4

AON6414 AL_DFN

1 2

PC185

AON6414 AL_DFN

1 2

PC204

0.22U_06 03_16V 7K

123 5

PQ36

AON6554_DFN

123 5

UGATE_NB 1

PHASE_NB 1

BOOT_NB 1

LGATE_ NB1

12

PWM2_NB

PC198

0.22U_06 03_25V 7K

1 2

6

7

FCCM

3

PWM

4

GND

9

TP

PU13

ISL620 8BCRZ-T _QFN8_ 2X2

UGATE2_ APU

PHASE2_ APU

PR248

2.2_060 3_5%

1 2

BOOT2_ APU

LGATE2 _APU

UGATE1_ APU

PHASE1_ APU

BOOT1_ APU

LGATE1 _APU

UGATE1VCC

PHASE

LGATE

BOOT

2.2_060 3_5%

1 2

PR274

UGATE_NB 2

2

BOOT_NB 2

8

5

1 2

0.22U_06 03_16V 7K

AON6414 AL_DFN

+5VALW

B+

12

PR223

0_0402 _5%

12

PR229

0_0402 _5%

1 2

PC212

1U_0603_10V6K

@

+5VALW

+5VS

1 2

PR215 0_ 0402_5 %

PR217 0_ 0402_5 %

4

PQ33

12

PR249

@

4.7_060 3_5%

1 2

APU_SNB1

12

@

680P_0 402_50 V7K

PQ38

AON6554_DFN

123 5

4

PC214

10U_0805_25V6K

PC231

12

PR275

@

4.7_060 3_5%

1 2

APU_SNB2

12

@

680P_0 402_50 V7K

PQ32

12

10U_0805_25V6K

PC248

2

AON6554_DFN

123 5

PC215

10U_0805_25V6K

ISEN2_A PU

VSUM+_APU

VSUM-_APU

ISEN1_A PU

PC243

12

PQ34

12

PC178

10U_0805_25V6K

AON6554_DFN

VDD1_B+

PC216

2200P_0402_50V7K

10K_04 02_1%

1 2

3.65K_0 402_1%

1 2

10_040 2_1%

1 2

10K_04 02_1%

1 2

PC239

10U_0805_25V6K

ISEN1_A PU

VSUM+_APU

VSUM-_APU

ISEN2_A PU

VDDNB1_B+

12

PC179

10U_0805_25V6K

@

4.7_060 3_5%

1 2

NB1_SNB

12

@

680P_0 402_50 V7K

12

PC200

10U_0805_25V6K

1 2

NB2_SNB

12

1 2

PC217

0.01U_0402_25V7K

PR253

PR258

VSUM+_APU1_R

PR261

VSUM-_APU1_R

PR263

@

VDD2_B+

12

PC240

2200P_0402_50V7K

PR202

12

@

4.7_060 3_5%

@

680P_0 402_50 V7K

1 2

HCB2012 KF-121T 50_08 05

12

PC180

1 2

PC181

0.01U_0402_25V7K

2200P_0402_50V7K

ISEN1_NB

VSUMP_NB

PC193

VSUMN_NB

ISEN2_NB

VDDNB2_B+

12

PC202

PC201

1 2

0.01U_0402_25V7K

2200P_0402_50V7K

10U_0805_25V6K

PR224

PC210

PL23

HCB2012 KF-121T 50_08 05

1 2

PL16

0.36UH 20% P DME064 T-R36MS1 R405 2 4A

134

2

PL24

HCB2012 KF-121T 50_08 05

1 2

PC241

0.01U_0402_25V7K

0.36UH 20% P DME064 T-R36MS1 R405 2 4A

PR276

10K_04 02_1%

1 2

PR277

3.65K_0 402_1%

1 2

VSUM+_APU2 _R

PR278

10_040 2_1%

1 2

VSUM-_APU2_ R

PR279

@

10K_04 02_1%

12

PL20

1 2

PR205

10K_04 02_1%

1 2

PR206

3.65K_0 402_1%

1 2

PR207 10_040 2_1%

1 2

PR209 10K_04 02_1%

PL22

HCB2012 KF-121T 50_08 05

1 2

PC203

ISEN2_NB

VSUMP_NB

VSUMN_NB

ISEN1_NB

1

+

PC242

PC244

2

68U_25V_M

B+

PL18

134

2

@

12

PR230

10K_04 02_1%

1 2

PR234

3.65K_0 402_1%

1 2

PR237

10_040 2_1%

1 2

PR238

10K_04 02_1%

1

+

2

68U_25V_M

VSUMP_NB1_R

VSUMN_NB1_R

@

PC226

B+

PL13

0.36UH 20% P DME064 T-R36MS1 R405 2 4A

134

2

B+

0.36UH 20% P DME064 T-R36MS1 R405 2 4A

VSUMP_NB2_R

VSUMN_NB2_R

12

B+

1

+

PC224

330U_D2_2V_Y

2

PC246

330U_D2_2V_Y

PL14

134

2

PC225

330U_D2_2V_Y

1

+

2

1

+VDDNB_CORE FSW=300KHz TDC=32A OCP=50A

+VDDNB_CORE

1

PC189

+

330U_D2_2V_Y

2

1

+

PC190

PC191

330U_D2_2V_Y

2

+VDDNB_CORE

1

12

PC207

+

330U_D2_2V_Y

2

+VDD_CORE FSW=300KHz TDC=30A OCP=46A

PC209

PC208

10U_0603_6.3V6M

.1U_0402 _10V6-K

1 2

+VDD_CORE

1

+

PC229 .1U_0402 _10V6-K

1 2

2

+VDD_CORE

12

PC247

10U_0603_6.3V6M

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2

2013/08/05

LC Future Cen ter Secret Data

Deciphered Date

2013/08/05

Title

PWR_CPU Core

Size Document Number R ev

D

Date: Sheet of

Monday, December 16, 2013

1

ACLU7

ACLU7ACLU7

52 52

0.1

5

4

3

2

1

D D

C C

+VDDNB_CORE

1

PC269

22U_0805_6.3V6-M

2

1

PC274

22U_0805_6.3V6-M

2

1

PC270

22U_0805_6.3V6-M

2

1

PC275

22U_0805_6.3V6-M

2

1

PC271

22U_0805_6.3V6-M

2

1

PC276

22U_0805_6.3V6-M

2

1

PC272

22U_0805_6.3V6-M

2

1

PC277

22U_0805_6.3V6-M

2

1

PC273

22U_0805_6.3V6-M

2

1

PC278

22U_0805_6.3V6-M

2

+VDD_CORE

1

PC279

22U_0805_6.3V6-M

2

1

PC284

22U_0805_6.3V6-M

2

B B

1

PC289

22U_0805_6.3V6-M

2

1

PC280

22U_0805_6.3V6-M

2

1

PC285

22U_0805_6.3V6-M

2

1

PC281

22U_0805_6.3V6-M

2

1

PC286

22U_0805_6.3V6-M

2

1

PC282

22U_0805_6.3V6-M

2

1

PC287

22U_0805_6.3V6-M

2

1

PC283

22U_0805_6.3V6-M

2

1

PC288

22U_0805_6.3V6-M

2

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/01

3

LC Future Center Secret Data

Deciphered Date

2014/08/01

2

Title

VCCCPUCORE DECOUPLING

Size Docum ent Number Rev

B

Monday, December 16, 2013

Date: Sheet of

Monday, December 16, 2013

AAVE1

AAVE1AAVE1

1

53 53

0.1

5

4

3

2

1

B+

Adaptor

EC_ON

D D

Silergy

SY8208CQNC

Converter

FOR SYSTEM

EN PGOOD

Silergy

SY8206BQNC

Converter

FOR SYSTEM

EC_ON

EN PGOOD

Richtek

TI

BQ24737RGRR

SYSON

SUSP#

RT8231AGQW

Switch Mode

S5

S3

FOR DDR

Battery Charger

Switch Mode

C C

Intersil

ISL6277AHRZ

SMBus

APUPWR_EN

Switch Mode

FOR APU/NB Core

PGOOD_NB

+5VLP/ 100mA

+5VALW/8A

ALW_PWRGD

+3VLP/ 100mA

+3VALW/ 6A

ALW_PWRGD

+1.35V/11A

+0.675VS/1.3A

PGOOD

APU Core/30A/46 A

APU Core NB/32A /50A

PGOODEN

IMVPPOK

SUSP#

Silergy

SY8032ABC

Converter

EN PGOOD

ANPEC

APL5930KAI-TRG

LDO

FOR APU VDDIO

PGOODEN

+1.8VALW/1A

+1.5VSP/150mA

Battery

Li-ion

4S1P/41WH

SUSP#

B B

Silergy

SYX198DQNC

Converter

FOR APU VDD

EN PGOOD

+0.95VS/9.5A

APUALW_PWRGD

Silergy

SYX198DQNC

Converter

S5_1.1V_EN

A A

5

DGPU_PWREN

4

FOR APU VDD

EN PGOOD

Interisl

ISL62771HRTZ

Switch Mode

VIDs

EN

FOR GPU VDDC

PGOOD

+1.1VALW/5A

APUALW_PWRGD

+VGA_CORE/20A

DGPU_PWROK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2013/08/15

LC Future Center Secret Data

Deciphered Date

2

2013/08/15

Title

Power Diagram

Size Document Number Rev

C

NM-A281

NM-A281NM-A281

Monday, December 16, 2013

Date: Sheet of

1

54 54

0.2