Lenovo IdeaPad 310-15IKB, IdeaPad CG413-CG513 Schematic

A

B

C

D

E

1

1

LCFC Confidential

CG413/CG513 MB Schematics Document

Intel Skylake-U22&U23/Kabylake-U22&U23 with DDR4

2

2016-06-12

REV:1.0

2

3

4 4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPER TY O F L C F UT URE CE NTE R. AN D C ONT AINS CO NFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPER TY O F L C F UT URE CE NTE R. AN D C ONT AINS CO NFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PR OPER TY O F L C F UT URE CE NTE R. AN D C ONT AINS CO NFIDENTIAL

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2016/08/20

2016/08/20

2016/08/20

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

1 60

1 60

of

of

E

1 60

1.0

1.0

1.0

3

HDMI Conn.

Conn.

eDP Conn

DP to VGA

ITE IT6516BFN

page 35

DP x2 Lane (DDI 2)

DP x2 Lane (DDI 2)

DP x2 Lane (DDI 2)

eDP x2 Lane

USB2.0 x1

USB3.0 x1

USB2.0 x1

USB2.0 x1

USB3.0 Right Conn 1 (Optional)

USB3.0 Port2

Page 45

USB2.0 Right Conn 1

USB2.0 Port3

USB2.0 Right Conn 2

USB2.0 Port2

Page 45

Page 45

USB2.0 x1

USB2.0 x1

USB2.0 x1

PCIe Genl x1

Card Reader

Realtek RTS5170

USB2.0 Port5

NGFF WLAN&BT

A B C

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2

S3
Battery only

S5 S4
AC Only

S5 S4
Battery only

S5 S4
AC & Battery
don't exist

SMBUS Control Table

3

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK3

EC_SMB_DA3

( O --> Means ON , X --> Means OFF )

+3VALW

+5VALW

V20B+

+3VALW_PCH

+1.8VALW

+1.0VALW

O

O

O

O X

O

XX

SOURCE

IT8586EEC_SMB_CK1

+3VL_EC

IT8586E

+3VS

IT8586E

+3VL_EC

BATT

V

X

ChargerVDGPU

X

X

V

+3VG_AON

+1.2V

+2.5V_DDR

+VCCST

O

O

O

O

XX

O

O

O

X

X

X

IT8586E

V

+3VL_EC

V

+3VS

V

+3VL_EC

Memory
Down

X

XX

PCH

X

V

+3VALW_PCH

+5VS

+3VS

+VCCIO

+VCCSTG

+VCCSA

+VCC_GT

+CPU_CORE

+0.6VS

O

X

X

X

SODIMM

PMIC

X

VXXX X X XX

Thermal
Sensor

X

X

X

V

WLAN
WiMAX

X

X

X

STATE

Full ON

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

HSIO PORT

1

2

USB3.0

USB2.0

PCIE

SATA

3

4

5

6

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9~12

X4 PCIE

0

1A

1B

2

SLP_S3# SLP_S4# SLP_S5# +VAL W +V +VS Clock

ON

HIGH HIGH HIGH

LOW

HIGH

LOWLOW

Function

USB3.0 Conn Left

USB3.0 Conn Right(optional)

3D Camera(optional)

NC

NC

NC

USB3.0 Conn Left

USB2.0 Conn1 Right

USB2.0 Conn2 Right

Camera

Cardreader

Touch Panel

Bluetooth

NC

NC

NC

NC

NC

NC

NC

LAN

WLAN

used as SATA

used as SATA

HIGH

LOW

ON ON ON

ON

ON

ON

OFF

ON

OFFLOW LOW LOW

@
14@
15@
14or15@
14or17@

Cannonlake@
CD@
DUALMIC@
EMC@
EMC_15@
EMC_NS@
EMC_PX@
EMC_PXNS@
ES@
EXO@

ME@
NTS@

PX@
RANKA@

DGPU

HDD

ODD

used as PCIE

used as PCIE

RANKB@
Realtek_SD@
SINGLEMIC@
SINGLERANK@
DUALRANK@
TS@
TPM@
UMA@

OFF

OFF

OFF

OFF

OFF

OFF

BTO ItemBOM Structure

Not stuff

For 14" part

For 15" part

For 14" or 15" part

For 14" or 17" part

For Cannonlake part

For C cost down

For Dual MIC part

For EMC part

For EMC 15" part

For EMC nu-stuff part

For EMC PX part

For EMC PX nu-stuff part

For ES CPU

For EXO GPU

For ME part

For nu-touch part

For PX part

For VRAM rank A part

For VRAM rank B part

For Realtek SD part

For single MIC part

For single VRAN rank part

For dual VRAN rank part

For touch screen part

For TPM part

For UMA part

2

3

PCH_SMB_CLK

PCH_SMB_DATA

EC SMBus1 address

Device

Smart Battery

4 4

Charger

PCH

+3VALW_PCH

need to update

0001 0010 b

X

X

X

X

XX

EC SMBus2 address

Device

Thermal Sensor(NCT7718W)

PCH

DGPU

A

1001_100xb

need to update

need to update

V

+3VALW_PCH

EC SMBus3 address

Device AddressAddre ss

PMIC

B

V

+3VS

need to update

X

V

+3VS

PCH SM Bus address

Device AddressAddre ss

DDR4 SODIMM

Wlan

Security Classification

Security Classificati on

Security Classificati on

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSE NT OF LC FUTURE C ENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSE NT OF LC FUTURE C ENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSE NT OF LC FUTURE C ENTER.

C

need to update

Reserved

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Dat e

Deciphered Dat e

D

2016/08/20

2016/08/20

2016/08/20

Titl e

Titl e

Titl e

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

E

3 60

3 60

of

of

3 60

1.0

1.0

1.0

5

D D

HDMI D2

HDMI D1

HDMI D0

HDMI CLK

DP TO VGA Conv erter

+VCCIO

C

check PROCHOT# circuit with PWR

H_PROCHOT#44,55

check H_THRMTRIP# if need to connector to EC

B

+VCCSTG

+VCCST_CPU

+3VS

HDMI_TX2-34
HDMI_TX2+34
HDMI_TX1-34
HDMI_TX1+34

HDMI_TX0-34
HDMI_TX0+34
HDMI_CLK-34
HDMI_CLK+34

VGA_TX0-35

VGA_TX0+35
VGA_TX1-35

VGA_TX1+35

DDPB_CLK34

DDPB_DATA34

RC4 24.9_0402_1%

12

RC19
1K_0402_5%

12

RC143
1K_0402_5%

12

1 2

RC20 499 +-1% 0402

RC155 49.9_0402_1%

RC156 49.9_0402_1%

RC157 49.9_0402_1%U23E@

RC170 49.9_0402_1%U23E@

check DDPC_CLK pull high or not?

RPC19

18
27

36

5

4

2.2K_0804_8P4R_5%

+VCCIO&EDP_COMP :
Trace Wid th: 20mil
Isolation Spac ing: 25m il
Max lengt h: 100mil

1 2

2

1

1 2

1 2

DDPC_CLK

DDPC_DATA

DDPB_CLK

DDPB_DATA

HDMI_TX2­HDMI_TX2+

HDMI_TX1-

HDMI_TX1+

HDMI_TX0-

HDMI_TX0+

HDMI_CLK­HDMI_CLK+

VGA_TX0-

VGA_TX0+

VGA_TX1-

VGA_TX1+

DDPB_CLK

DDPB_DATA

DDPC_CLK

DDPC_DATA

EDP_COMP

H_PECI44

4

+VCCST_CPU

@

TC11PAD @
TC12PAD @
TC13PAD

@

TC14PAD @

TC162@PAD

TC163@PAD

12

RC1625

49.9_0402_1%

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

REV = 1
@

CATERR#

H_PECI

H_PROCHOT#_R

H_THRMTRIP#

XDP_BPM0#

1

XDP_BPM1#

1

XDP_BPM2#

1

XDP_BPM3#

1

GPP_E3

1

GPP_E7

1

PROC_OPI_RCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP

DDI

DISPLAY SIDEBANDS

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U_BGA1356

REV = 1
@

SKL_ULT

?

CPU MISC

1 OF 20

SKL_ULT

EDP

?

1 OF 20

3

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN

EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP

DDI2_AUXN
DDI2_AUXP

DDI3_AUXN

DDI3_AUXP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1

GPP_E15/DDPD_HPD2

GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

JTAG

PROC_TCK

PROC_TDI

PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

1 2

RC1601 10K_0402_5%@

1 2

1 2

1

+3VS

+VCCSTG

2

C47

C46

D46

C45

A45

B45

A47

B47

E45

F45

B52

G50
F50

E48
F48

G46

F46

L9
L7

L6

N9

L10

R12

R11

U13

?

B61
D60
A61

C60
B59

B56
D59

A56
C59
C61

A59

?

CPU_EDP_TX0-

CPU_EDP_TX0+

CPU_EDP_TX1­CPU_EDP_TX1+

CPU_EDP_AUX#

CPU_EDP_AUX

VGA_AUX#
VGA_AUX

HDMI_HPD

DP_VGA_HPD

GPP_E15

CPU_EDP_HPD

PCH_ENBKL
PCH_EDP_PWM
PCH_ENVDD

XDP_TCK

XDP_TDI
XDP_TDO
XDP_TMS

XDP_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS
PCH_JTAG_TRST#

JTAGX

CPU_EDP_TX0- 33
CPU_EDP_TX0+ 33
CPU_EDP_TX1- 33
CPU_EDP_TX1+ 33

CPU_EDP_AUX# 33

CPU_EDP_AUX 33

VGA_AUX# 35

VGA_AUX 35

HDMI_HPD 34

1 2

@

RC181 0_0402_5%

PCH_ENBKL 33

PCH_EDP_PWM 33
PCH_ENVDD 33

XDP_TCK

XDP_TDO

1

PAD @

TC15

1

1

1

1

1

1
1
1

1

1

TC16

TC17

TC18

TC27

TC29

TC31

TC35
TC36

TC42

TC43

PAD

PAD @

PAD

PAD @

PAD @

PAD @

PAD
PAD @

PAD @

PAD @

@

@

@

confirmed with ITE, the HPD
pull down resistor should follow
ITE recommended resistor 4.7k~10Kohm

GPP_E15

RC37
100K_0402_5%

1 2

1

RC13
100K_0402_5%

2

2

1

RC1546 0_0402_5%@

1 2

RC1547 0_0402_5%@

XDP_TDI PCH_JTAG_TDI

XDP_TMS

XDP_TRST#

1

RC1548 0_0402_5%

1 2

RC1549 0_0402_5%@

1

RC1550 0_0402_5%@

JTAGX

PCH_JTAG_TDO

2

@

2

DP_VGA_HPD 35
EC_SCI# 44

CPU_EDP_HPD 33

PCH_JTAG_TMS

PCH_JTAG_TRST#

check JTAG circuit?

RC1551 51_0402_5%

RC1543 51_0402_5%

C

B

DDP*_CTRLDATA strapping sampled on t he rising edge of PWROK

Port

Strap Enable Disable

Port 1

DDPB_CTRLDATA

Port 2

DDPC_CTRLDATA

A

5

Pull up to 3.3 V
with 2.2Kohm

Pull up to 3.3 V
with 2.2Kohm

NC

NC

A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WR ITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WR ITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WR ITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Fut ure C enter Secret Data

LC Fut ure C enter Secret Data

LC Fut ure C enter Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Titl e

MCP (DDI,EDP)

MCP (DDI,EDP)

MCP (DDI,EDP)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

1

4 60

4 60

of

4 60

of

1.0

1.0

1.0

5

DDRA_DQ[0..63]17

D D

C

DDRA_DQ0

DDRA_DQ1

DDRA_DQ2

DDRA_DQ3
DDRA_DQ4

DDRA_DQ5
DDRA_DQ6

DDRA_DQ7
DDRA_DQ8

DDRA_DQ9
DDRA_DQ10

DDRA_DQ11
DDRA_DQ12

DDRA_DQ13

DDRA_DQ14

DDRA_DQ15

DDRA_DQ16

DDRA_DQ17

DDRA_DQ18

DDRA_DQ19

DDRA_DQ20

DDRA_DQ21
DDRA_DQ22

DDRA_DQ23
DDRA_DQ24

DDRA_DQ25

DDRA_DQ26
DDRA_DQ27

DDRA_DQ28

DDRA_DQ29

DDRA_DQ30

DDRA_DQ31

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36

DDRA_DQ37
DDRA_DQ38
DDRA_DQ39

DDRA_DQ40

DDRA_DQ41

DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45

DDRA_DQ46
DDRA_DQ47

DDRA_DQ48

DDRA_DQ49

DDRA_DQ50

DDRA_DQ51
DDRA_DQ52

DDRA_DQ53

DDRA_DQ54

DDRA_DQ55

DDRA_DQ56
DDRA_DQ57

DDRA_DQ58

DDRA_DQ59
DDRA_DQ60

DDRA_DQ61

DDRA_DQ62
DDRA_DQ63

4

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

REV = 1

@

?

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

1 OF 20

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]

DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

3

AU53
AT53
AU55

AT55

BA56
BB56

AW56
AY56

AU45

AU43

AT45
AT43

BA51
BB54
BA52
AY52
AW52

AY55

AW54
BA54
BA55

AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48

AT50
BB50
AY50

BA50

BB52

DDRA_DQS#0

AM70

DDRA_DQS0

AM69

DDRA_DQS#1

AT69

DDRA_DQS1

AT70

DDRA_DQS#2

BA64

DDRA_DQS2

AY64

DDRA_DQS#3

AY60

DDRA_DQS3

BA60

DDRA_DQS#4

BA38

DDRA_DQS4

AY38

DDRA_DQS#5

AY34

DDRA_DQS5

BA34

DDRA_DQS#6

BA30

DDRA_DQS6

AY30

DDRA_DQS#7

AY26

DDRA_DQS7

BA26

AW50
AT52

AY67
AY68
BA67

DDR_VTT_CNTL

AW67

?

DDRA_CLK0# 17

DDRA_CLK0 17

DDRA_CKE0 17

DDRA_CS0# 17

DDRA_ODT0 17

DDRA_MA5 17
DDRA_MA9 17
DDRA_MA6 17

DDRA_MA8 17

DDRA_MA7 17

DDRA_BG0 17

DDRA_MA12 17
DDRA_MA11 17
DDRA_ACT# 17

DDRA_MA13 17

DDRA_MA15_CAS# 17
DDRA_MA14_WE# 17
DDRA_MA16_RAS# 17

DDRA_BS0# 17

DDRA_MA2 17

DDRA_BS1# 17
DDRA_MA10 17
DDRA_MA1 17

DDRA_MA0 17
DDRA_MA3 17
DDRA_MA4 17

DDRA_ALERT# 17
DDRA_PAR 17

DDR_SA_VREFCA 17

DDR_SB_VREFCA 18

DDRA_DQS#[0..7]

DDRA_DQS[0..7]

2

DDRA_DQS#[0..7] 17

DDRA_DQS[0..7] 17

SMVREF

WIDTH:20MIL
SPACING: 20MIL

1

C

B

+3VALW

1

RC30
100K_0402_5%

B

2

+1.2V

1

RC3

1K_0402_5%

DDR_VTT_CNTL

A

5

4

2

RC29

10K_0402_5%

1

C

2

QC18

B

E

3

MMBT3904WH_SOT323-3

@

1 2

CPU_DRAMPG_CNTL 55

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF L C FUT URE C ENTE R. AND CONTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF L C FUT URE C ENTE R. AND CONTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPER TY OF L C FUT URE C ENTE R. AND CONTAIN S CON FIDENTIAL

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND T RADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE U SED BY OR DISCLOSED TO ANY T HIRD PARTY W ITHOUT PR IOR WRITTEN CONSENT OF LC F UTURE CENT ER.

MAY BE U SED BY OR DISCLOSED TO ANY T HIRD PARTY W ITHOUT PR IOR WRITTEN CONSENT OF LC F UTURE CENT ER.

MAY BE U SED BY OR DISCLOSED TO ANY T HIRD PARTY W ITHOUT PR IOR WRITTEN CONSENT OF LC F UTURE CENT ER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

MCP (DDR4)

MCP (DDR4)

MCP (DDR4)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

1

of

5 60

of

5 60

of

5 60

A

1.0

1.0

1.0

5

DDRB_DQ[0..63]18

D D

C

B

DDRB_DQ0

DDRB_DQ1

DDRB_DQ2

DDRB_DQ3

DDRB_DQ4

DDRB_DQ5

DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9

DDRB_DQ10

DDRB_DQ11

DDRB_DQ12

DDRB_DQ13

DDRB_DQ14

DDRB_DQ15
DDRB_DQ16
DDRB_DQ17

DDRB_DQ18

DDRB_DQ19
DDRB_DQ20

DDRB_DQ21
DDRB_DQ22

DDRB_DQ23
DDRB_DQ24
DDRB_DQ25

DDRB_DQ26

DDRB_DQ27

DDRB_DQ28
DDRB_DQ29

DDRB_DQ30
DDRB_DQ31

DDRB_DQ32

DDRB_DQ33

DDRB_DQ34

DDRB_DQ35
DDRB_DQ36

DDRB_DQ37
DDRB_DQ38
DDRB_DQ39

DDRB_DQ40

DDRB_DQ41

DDRB_DQ42
DDRB_DQ43

DDRB_DQ44

DDRB_DQ45

DDRB_DQ46

DDRB_DQ47

DDRB_DQ48
DDRB_DQ49

DDRB_DQ50
DDRB_DQ51
DDRB_DQ52

DDRB_DQ53

DDRB_DQ54

DDRB_DQ55

DDRB_DQ56

DDRB_DQ57

DDRB_DQ58

DDRB_DQ59

DDRB_DQ60
DDRB_DQ61

DDRB_DQ62

DDRB_DQ63

4

AF65
AF64
AK65
AK64

AF66
AF67
AK67
AK66
AF70

AF68
AH71
AH68
AF71
AF69
AH70
AH69
AT66
AU66
AP65

AN65
AN66
AP66

AT65
AU65

AT61

AU61
AP60

AN60
AN61
AP61

AT60
AU60
AU40

AT40
AT37
AU37
AR40
AP40
AP37
AR37

AT33
AU33
AU30

AT30

AR33
AP33

AR30
AP30
AU27
AT27
AT25

AU25
AP27
AN27

AN25
AP25
AT22
AU22

AU21
AT21
AN22

AP22
AP21
AN21

UC1C

DDR1_DQ[0]/DDR0_DQ[16]
DDR1_DQ[1]/DDR0_DQ[17]
DDR1_DQ[2]/DDR0_DQ[18]
DDR1_DQ[3]/DDR0_DQ[19]

DDR1_DQ[4]/DDR0_DQ[20]
DDR1_DQ[5]/DDR0_DQ[21]
DDR1_DQ[6]/DDR0_DQ[22]
DDR1_DQ[7]/DDR0_DQ[23]
DDR1_DQ[8]/DDR0_DQ[24]

DDR1_DQ[9]/DDR0_DQ[25]
DDR1_DQ[10]/DDR0_DQ[26]
DDR1_DQ[11]/DDR0_DQ[27]
DDR1_DQ[12]/DDR0_DQ[28]
DDR1_DQ[13]/DDR0_DQ[29]
DDR1_DQ[14]/DDR0_DQ[30]
DDR1_DQ[15]/DDR0_DQ[31]
DDR1_DQ[16]/DDR0_DQ[48]
DDR1_DQ[17]/DDR0_DQ[49]

DDR1_DQ[18]/DDR0_DQ[50]
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQ[21]/DDR0_DQ[53]

DDR1_DQ[22]/DDR0_DQ[54]
DDR1_DQ[23]/DDR0_DQ[55]

DDR1_DQ[24]/DDR0_DQ[56]

DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[26]/DDR0_DQ[58]

DDR1_DQ[27]/DDR0_DQ[59]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_DQ[29]/DDR0_DQ[61]

DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]

DDR1_DQ[33]/DDR1_DQ[17]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_DQ[38]/DDR1_DQ[22]
DDR1_DQ[39]/DDR1_DQ[23]

DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQ[41]/DDR1_DQ[25]
DDR1_DQ[42]/DDR1_DQ[26]

DDR1_DQ[43]/DDR1_DQ[27]

DDR1_DQ[44]/DDR1_DQ[28]

DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_DQ[47]/DDR1_DQ[31]
DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]

DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]

DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]

DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]

DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]

SKYLAKE-U_BGA1356

REV = 1
@

3

?

SKL_ULT

DDR1_CKN[0]
DDR1_CKN[1]

DDR1_CKP[0]

DDR1_CKP[1]

DDR1_CKE[0]

DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]

DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

1 OF 20

DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET#

DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

DDR1_PAR

AN45
AN46

AP45

AP46

AN56

AP55
AN55
AP53

BB42
AY42

BA42
AW42

AY48

AP50

BA48
BB48
AP48

AP52
AN50

AN48

AN53

AN52

BA43
AY43

AY44

AW44
BB44

AY47

BA44

AW46

AY46
BA46

BB46
BA47

AH66

AH65

AG69

AG70

AR66

AR65

AR61

AR60

AT38

AR38
AT32

AR32

AR25

AR27
AR22
AR21

AN43
AP43

AT13

AR18
AT18
AU18

?

DDRB_DQS#0

DDRB_DQS0

DDRB_DQS#1
DDRB_DQS1
DDRB_DQS#2

DDRB_DQS2
DDRB_DQS#3
DDRB_DQS3

DDRB_DQS#4
DDRB_DQS4

DDRB_DQS#5

DDRB_DQS5
DDRB_DQS#6

DDRB_DQS6

DDRB_DQS#7

DDRB_DQS7

CPU_DRAMRST#_R

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

2

DDRB_CLK0# 18
DDRB_CLK1# 18

DDRB_CLK0 18

DDRB_CLK1 18

DDRB_CKE0 18

DDRB_CKE1 18

DDRB_CS0# 18

DDRB_CS1# 18

DDRB_ODT0 18
DDRB_ODT1 18

DDRB_MA5 18

DDRB_MA9 18

DDRB_MA6 18
DDRB_MA8 18
DDRB_MA7 18

DDRB_BG0 18

DDRB_MA12 18

DDRB_MA11 18
DDRB_ACT# 18

DDRB_BG1 18

DDRB_MA13 18

DDRB_MA15_CAS# 18

DDRB_MA14_WE# 18
DDRB_MA16_RAS# 18
DDRB_BS0# 18

DDRB_MA2 18

DDRB_BS1# 18

DDRB_MA10 18
DDRB_MA1 18
DDRB_MA0 18
DDRB_MA3 18

DDRB_MA4 18

DDRB_DQS#[0..7]

DDRB_DQS[0..7]

DDRB_ALERT# 18

DDRB_PAR 18

1

RC24 121_0402_1%

RC25 80.6_0402_1%

RC26 100_0402_1%

2

1

2

1

2

1

DDRB_DQS#[0..7] 18

DDRB_DQS[0..7] 18

C

B

+1.2V

1

RC22
470_0402_5%

Issued Date

Issued Date

Issued Date

2

1

CC1

0.01U_0201_25V6-K

EMC_NS@

2

3

CPU_DRAMRST#17,18

A

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1 2

RC23 0_0402_5%@

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

CPU_DRAMRST#_R

2

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

MCP (DDR4)

MCP (DDR4)

MCP (DDR4)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

6 60

6 60

1

6 60

A

1.0

1.0

1.0

5

RC1539 15_0402_5%

1

SPI_CLK44

SPI_CLK_1

SPI_SO

SPI_SO44

D D

Check with BIOS, SPI is Dual mode or quad mode

SPI_WP#_R

C

SPI_HOLD#_R

SPI_WP#_R SPI_WP#_1

SPI_HOLD#_R

+3VALW_PCH

B

A

SPI_SO_1

SPI_SI

SPI_SI44

SPI_SI_1

SPI_CS0#

SPI_CS0#44

SPI_CS1#

1

2

RC54 15_0402_5%@

2

1

RC55 15_0402_5%@

2

1

RC176 33_0402_5%

@

1

2

RC178 33_0402_5%@

Follow CRB, need to check the strap ?

2

RC1568 20K_0402_5%@

RC1565 20K_0402_5%@

RC1578 20K_0402_5%@

RC1580 20K_0402_5%

RC1567 4.7K_0402_5%@

RC1566 4.7K_0402_5%@

RC1581 4.7K_0402_5%@

RC64 1K_0402_5%ES@

Based on WW36 SKL U&Y WOM, RC64 populated,

and RC61 de-populated for SKL U ES sample.
In this cas e, custom ers must en sure tha t the
SPI flash device on the platfo rm
has HOLD functionality disabled by default.

1

1

2

1

2

12

@

Follow CRB, need to check the strap ?

1

2

2

1

2

1

2

1

2

1 2

RC1538 33_0402_5%@

2

RC53 15_0402_5%

1

RC177 33_0402_5%@

1

2

1

2

RC52 15_0402_5%
RC175 33_0402_5%@

1 2

@

RC51 0_0402_5%

1

2

RC174 0_0402_5%@

2

1

+3V_SPI

1

1

RC60

1K_0402_5%

2

2

+3V_SPI

1

1

RC179

1K_0402_5%

@

2

2

SPI_SO_R

SPI_SI_R

SPI_WP#_R

SPI_HOLD#_R

SPI_SO_R

SPI_SI_R

SPI_WP#_R

SPI_HOLD#_R

RC61
1K_0402_5%

SPI_WP#

SPI_HOLD#

RC180
1K_0402_5%

@

SPI_HOLD#_1

SPI_SO_R

SPI_SI_R

SPI_CS0#_R

SPI_CS1#_R

BOARD_ID48

KBRST#44

SERIRQ32,44

+3VS

+3VALW_PCH

+3V_SPI

*

1. If support DS3, connect to +3VS and don't support EC mirror code;

2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

SPI_CS0#

SPI_SO

SPI_WP#

SPI_CS1#

SPI_SO_1

SPI_WP#_1

1

2

3

1
2
3

4

SPI_CLK_RSPI_CLK SPI_CLK_R
SPI_SO_R

SPI_SI_R

SPI_WP#_R
SPI_HOLD#_R

SPI_CS0#_R

SPI_CS1#_R

BOARD_ID4

KBRST#

SERIRQ

1

RC171 0_0402_5%@

RC172 0_0402_5%@

1

UC3

CS#

DO

HOLD#

WP#

GND4DI

W25Q64FVSSIQ_SO8

UC6

VCC

CS#

HOLD#

DO

CLK

WP#

GND

W25Q32FVSSIQ_SO8

@

4

?

1

CC8

0.1u_0201_10V6K

2

CC97

0.1u_0201_10V6K

@

SKL_ULT

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

LPC

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

1 OF 20

check CLKRUN# / SUS_STAT# signal if need to connect

PM_CLKRUN#

SERIRQ

KBRST#

KBRST#

2.2K_0404_4P2R_5%

GPP_C2/SMBALERT#

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

RC11 8.2K_0402_5%

RC12 10K_0402_5%

RC10 10K_0402_5%

CC1255 1000P_0201_50V7-K

PCH_SML1_CLK

PCH_SML1_DAT

UC1E

SPI - FLASH

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

SPI - TOUCH

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

C LINK

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

AW13

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

SKYLAKE-U_BGA1356

REV = 1

@

+3V_SPI

2

2

+3V_SPI

8

VCC

SPI_HOLD#

7

SPI_CLK

6

CLK

SPI_SI

5

+3V_SPI

8

SPI_HOLD#_1

7

SPI_CLK_1

6

SPI_SI_1

5

DI

1

2

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C3/SML0CLK

GPP_C6/SML1CLK

GPP_A8/CLKRUN#

1 2

1 2

1

1

EMC_NS@

+3VALW_PCH

RPC25

3

PCH_SMB_CLK

R7

PCH_SMB_DATA

R8

SMB_ALERT#

R10

SML0_CLK

R9

SML0_DATA

W2

SML0_ALERT#

W1

PCH_SML1_CLK

W3

PCH_SML1_DAT

V3

SML1_ALERT#

AM7

AY13
BA13
BB13
AY12
BA12

SUS_STAT#

BA11

CLK_PCI_EC_R

AW9

CLK_PCI_TPM_R

AY9

PM_CLKRUN#

AW11

?

DIMM, NGFF

GPU, EC, Thermal Sensor

LPC_AD0 32,44
LPC_AD1 32,44

LPC_AD2 32,44
LPC_AD3 32,44
LPC_FRAME# 32,44

RC173 22_0402_5%

2

TPM@

RC1541 22_0402_5%

2

+3VS

1

1

1

TC81@

CLK_PCI_EC 44
CLK_PCI_TPM 32

PM_CLKRUN# 32

2

RPC20

2.2K_0404_4P2R_5%

PCH_SMB_CLK

PCH_SMB_DATA

+3VALW_PCH

3

2

4

1

QC2A

SMB_ALERT#

SML0_CLK
SML0_DATA

+3VS

2

G

1

6

S

D

2N7002KDWH_SOT363-6

QC2B

2N7002KDWH_SOT363-6

2.2K_0404_4P2R_5%

5

G

3 4

D

2

2.2K_0402_5%

RPC23

4

3

+3VS

4

3

1

2

S

RC1562

1

1

2

2

2

+3VS

2

1 4

2 3

G

6

QC10A

D

2N7002KDWH_SOT363-6

1

@

S

5

QC10B

3

D

2N7002KDWH_SOT363-6

G

@

4

S

EC_SMB_CK2 39,44

EC_SMB_DA2 39,44

SML0_ALERT#

This signal has a wea k internal pu ll-down.
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.
Notes:

1. The internal pull-do wn is disabled a fter RSMRST#
de-asserts.

2. This signal is in the primary wel
Rising edge of RSMRST#

SML1_ALERT#

To e na b l e D i re c t C o nn e ct In t er f ac e (D C I) , a 1 5 0K p ull up resistor will need to be
added to PCHHOT# pin. This pin must be low during the rising e dge of RSMRST#.
(Refer to WW52_MOW)

12

RC1564 2.2K_0402_5%@

1

2

RC1569 150K_0402_5%

RPC24

2.2K_0404_4P2R_5%

+3VALW_PCH

+3VALW_PCH

+3VALW_PCH

+3VALW_PCH

1

SMB_CLK_S3 18,40

SMB_DATA_S3 18,40

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF E NGINEERING DR AWING IS THE PROP RIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF E NGINEERING DR AWING IS THE PROP RIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF E NGINEERING DR AWING IS THE PROP RIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SE CRET I NFORMATION. THI S SHEE T MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SE CRET I NFORMATION. THI S SHEE T MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SE CRET I NFORMATION. THI S SHEE T MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC F UTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC F UTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC F UTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED B Y OR DISCL OSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED B Y OR DISCL OSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC F UTURE CENTER.

5

4

3

MAY BE USED B Y OR DISCL OSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC F UTURE CENTER.

2015/08/20

2015/08/20

2015/08/20

LC Fut ure Center Secret Data

LC Fut ure Center Secret Data

LC Fut ure Center Secret Data

2

Deciphered Date

Deciphered Date

Deciphered Date

2016/08/20

2016/08/20

2016/08/20

Title

MCP (MISC,JTAG,SPI,LPC,SMB)

MCP (MISC,JTAG,SPI,LPC,SMB)

MCP (MISC,JTAG,SPI,LPC,SMB)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

1

CG413

CG413

CG413

7 60

7 60

of

7 60

of

1.0

1.0

1.0

5

RC1561 2.2K_0402_5%@

+3VS

D D

1

12

1

1

1 2

DGPU_PWROK

PCH_CMOS_ON#

PCH_WLAN_OFF#

PCH_BT_OFF#

2

HDA_SDIN0

1

RC45 33_0402_5%

1

RC46 0_0402_5%@

HDA_SDOUT

1

RC1558 10K_0402_5%UMA@

+3VS

C

+3VALW_PCH

*

HDA_SDO This signal has a w eak internal pull-down.
0 = Enable security measures def ined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This st rap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.

2

2

RC1595 10K_0402_5%@

RC1596 10K_0402_5%

2

RC1597 10K_0402_5%

double check if need the pull up resisor

+3VS

RC1600 1K_0402_5%@

RC47 1K_0402_5%@

For EMI

1

CC7
10P_0201_50V8F

EMC_NS@

2

HDA_SDOUT_AUDIO43

B

ME_FLASH44

PCH_CMOS_ON#33

UART_RX_DEBUG40

UART_TX_DEBUG40

PCH_WLAN_OFF#40
PCH_BT_OFF#40

HDA_SDOUT

2

2

RC1563 2.2K_0402_5%@

HDA_SYNC_AUDIO43

HDA_BITCLK_AUDIO43

HDA_SDIN043

HDA_RST_AUDIO#43

PCH_BEEP43

4

2

1

1

2

1

RC43 33_0402_5%

1

RC42 33_0402_5%

1

RC44 33_0402_5%

GPP_B18

PCH_CMOS_ON#

GPP_B22

DGPU_PWROK

PCH_WLAN_OFF#
PCH_BT_OFF#

2

2

2

+3VS

HDA_SYNC

HDA_BCLK

HDA_SDOUT

HDA_SDIN0

HDA_RST#

BOARD_ID10

BOARD_ID9

PCH_BEEP

1 2

RC14 2.2K_0402_5%@

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-U_BGA1356

REV = 1
@

3

?

AUDIO

SKL_ULT

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

1 OF 20

?

SKL_ULT

1 OF 20

LPSS ISH

UC1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKYLAKE-U_BGA1356

REV = 1
@

PCH_BEEP

GPP_D9

GPP_D10

GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A18/ISH_GP0

GPP_A19/ISH_GP1
GPP_A20/ISH_GP2

GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

SDIO/SDXC

GPP_G0/SD_CMD

GPP_G1/SD_DATA0

GPP_G2/SD_DATA1

GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

?

GPP_F23

2

RC1613

1

10K_0402_5%

2

RC1614

1

10K_0402_5%

@

@

TS@

NTS@

00

01

10

11

0

1

0

1

0

1

0

1

1

RC1632

2

10K_0402_5%

1

RC1635

2

10K_0402_5%

1

DUALRANK@

2

2

OPT@

RC1611

RC1609

1

1

10K_0402_5%

10K_0402_5%

SINGLERANK@

2

2

UMA@

RC1612

RC1610

1

1

10K_0402_5%

10K_0402_5%

14"

15"

17"

Reserved

Touch

DIS

SingleRankRC1607

DualRank

DualMIC

510Z@

1

RC1633

2

10K_0402_5%

310G@

1

RC1636

2

10K_0402_5%

DUALMIC@

2

RC1608

1

10K_0402_5%

SINGLEMIC@

2

RC1607

1

10K_0402_5%

Stuff R

RC1616

RC1614

RC1616 RC1613

RC1615

RC1614

RC1612

RC1611

RC1610

RC1609

RC1608

RC123

RC1606

@

KBL@

1

RC1639

2

10K_0402_5%

NKBL@

@

12

RC1640

10K_0402_5%

+3VS

+3VS

2

RC1606

1

10K_0402_5%

2

RC123

10K_0402_5%

1

12

RC1651

10K_0402_5%

1

RC1652

2

10K_0402_5%

2

2

15@

17@

BOARD_ID0

P2

BOARD_ID1

P3

P4

BOARD_ID3

P1

BOARD_ID6

M4

BOARD_ID5

N3

BOARD_ID7

N1

BOARD_ID8

N2

AD11
AD12

U1

U2

U3

U4

AC1
AC2

AC3
AB4

AY8

BA8
BB7

BA7
AY7
AW7

AP13

?

BOARD_ID29

BOARD_ID47

BOARD_ID0
BOARD_ID1
BOARD_ID2

BOARD_ID3
BOARD_ID4
BOARD_ID5

RC1615

1

10K_0402_5%

2

14or15@

14or17@

RC1616

1

10K_0402_5%

Board ID Description

Board_ID[0:1]

Board_ID2 Non-touch

Board_ID3 UMA

Board_ID4

AB11
AB13

AB12

W12
W11

W10
W8
W7

BA9
BB9

AB7

AF13

SD_RCOMP

1

RC49
200_0402_1%

2

BOARD_ID6

BOARD_ID7

BOARD_ID8
BOARD_ID9

BOARD_ID10

Board_ID5 SingleMIC

@

1

RC1631

2

10K_0402_5%

@

12

RC1634

10K_0402_5%

C

B

510Z

Non-KBL

KBL1

Stuff R

RC1634 RC1635

RC1634 RC1632

RC1631

RC1631

RC1634 RC1635

RC1634

RC1631

RC1631

RC1636310G

RC1633

RC1652

RC1651

CG413

CG413

CG413

1

RC1640

RC1640

RC1635

RC1640

RC1640

RC1632

RC1639

RC1632 RC1639

RC1635 RC1639

RC1632 RC1639

8 60

8 60

8 60

of

A

1.0

1.0

1.0

Default

Pin Name Strap Description Configuration

SPKR /

Top Swap

GPP_B14

Override

GSPI0_MOSI

No Reboot

/GPP_B18

GSPI1_MOSI

Boot BIOS

/GPP_B22

Strap Bit
BBS

A

5

Internal PD

0 = Disable “ Top Swap”
mode. (Default)
1 = Enable “ Top Swap”
mode.

Internal PD

0 = Disable “ No Reboot”
mode. (Default)
1 = Enable “ No Reboot”
mode

Internal PD
0 = SPI (Default)
1 = LPC

*

When

Value

Sampled

0*Rising edge

of PCH_PWROK

0*Rising edge

of PCH_PWROK

Rising edge

0

of PCH_PWROK

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF LC FUTU RE C ENTE R. AN D C ONTAIN S C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF LC FUTU RE C ENTE R. AN D C ONTAIN S C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERTY OF LC FUTU RE C ENTE R. AN D C ONTAIN S C ONFIDENTIAL

AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISC LOSED TO AN Y THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO AN Y THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISC LOSED TO AN Y THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Board ID Description

Board_ID
[6,7,9]

000

010

100

110

001

011

101

Samsung 8Gb

2133 MT/s

Hynix 8Gb

2133 MT/s

Micron 8Gb

2133 MT/s

Reserved

Samsung 8Gb

2400 MT/s

Hynix 8Gb

2400 MT/s

Micron 8Gb

2400 MT/s

111 Reserved

Board_ID8

Board_ID10

0

1

0

Title

Title

Title

MCP (LPSS,ISH,AUDIO,SDIO)

MCP (LPSS,ISH,AUDIO,SDIO)

MCP (LPSS,ISH,AUDIO,SDIO)

Size Do cument Number Rev

Size Do cument Number Rev

Size Do cument Number Rev

Custom

Custom

Custom

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

Date: Sheet of

Date: Sheet

Date: Sheet of

5

4

3

2

1

D D

UC1H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE_PRX_DTX_N537

C

LAN

WLAN

SATA HDD

SATA ODD

B

A

DGPU

PCIE_PRX_DTX_P537

PCIE_PTX_C_DRX_N537
PCIE_PTX_C_DRX_P537

PCIE_PRX_DTX_N640

PCIE_PRX_DTX_P640
PCIE_PTX_C_DRX_N640
PCIE_PTX_C_DRX_P640

SATA_PRX_DTX_N042
SATA_PRX_DTX_P042
SATA_PTX_DRX_N042
SATA_PTX_DRX_P042

SATA_PRX_DTX_N142
SATA_PRX_DTX_P142
SATA_PTX_DRX_N142

SATA_PTX_DRX_P142

RC119 100_0402_1%

PCIE_RCOMPN and PCIE_RCOMPP
Trace Width: 12-15mil
Differential between RCOMPP/RCOMPN

+3VS

1 2

CC22 0.1u_0201_10V6K

2

1

CC23 0.1u_0201_10V6K

2

1

CC24 0.1u_0201_10V6K

2

1

CC25 0.1u_0201_10V6K

2

1

TC20PAD @

TC19PAD @

RPC2

1

2 7

3
4

10K_0804_8P4R_5%

8

6
5

ODD_DETECT#
SATA0GP

SATA2GP
PIRQA#

PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5

PCIE_PTX_DRX_N5

PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_DRX_N6

PCIE_PTX_DRX_P6

SATA_PRX_DTX_N0

SATA_PRX_DTX_P0

SATA_PTX_DRX_N0

SATA_PTX_DRX_P0

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

PCIE_RCOMPN
PCIE_RCOMPP

XDP_PRDY#

1

XDP_PREQ#

1

PIRQA#

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

REV = 1
@

USB_OC0#
USB_OC1#

USB_OC3#

USB_OC2#

SKL_ULT

10K_0804_8P4R_5%

?

1 OF 20

8

6

USB2

RPC17

SSIC / USB3

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

1

27
3

45

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN

USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN

USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#

GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1

GPP_E6/DEVSLP2

GPP_E8/SATALED#

?

+3VALW_PCH

H8
G8
C13
D13

J6
H6

B13
A13

J10
H10
B15

A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3

AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8

AF9

AG1
AG2

AH7
AH8

AB6

AG3
AG4

A9
C9
D9

B9

J1
J2

J3

H2
H3
G4

H1

USB30_RX_N1

USB30_RX_P1
USB30_TX_N1
USB30_TX_P1

USB30_RX_N2
USB30_RX_P2
USB30_TX_N2

USB30_TX_P2

USB20_N1

USB20_P1

USB20_N2
USB20_P2

USB20_N3

USB20_P3

USB20_N4
USB20_P4

USB20_N5
USB20_P5

USB20_N6
USB20_P6

USB20_N7
USB20_P7

USB2_COMP

USB2_ID

USB2_VBUSSENSE

USB_OC0#
USB_OC1#

USB_OC2#
USB_OC3#

GPP_E4
GPP_E5

SATA0GP

ODD_DETECT#

SATA2GP

BOARD_ID2

GPP_E4

USB30_RX_N1 41

USB30_RX_P1 41
USB30_TX_N1 41

USB30_TX_P1 41

USB30_RX_N2 45
USB30_RX_P2 45
USB30_TX_N2 45

USB30_TX_P2 45

USB20_N1 41
USB20_P1 41

USB20_N2 45
USB20_P2 45

USB20_N3 45
USB20_P3 45

USB20_N4 33

USB20_P4 33

USB20_N5 30
USB20_P5 30

USB20_N6 33

USB20_P6 33

USB20_N7 40
USB20_P7 40

1

2

RC118 113_0402_1%

1

RC1626 0_0402_5%@

RC1627 1K_0402_5%

USB_OC1# 41
USB_OC2# 45

1

BOARD_ID2 8

RC1617 10K_0402_5%@

2

1

2

TC202PAD@

2016/05/03: Implement as Power Button
function for Windows RedStone support

1

2

LEFT USB (3.0)

Right USB (3.0) (Optional)

LEFT USB (3.0)

RIGHT USB (2.0)

RIGHT USB (2.0)

Camera

Card reader

Touch panel

BT

USBRBIAS

Width 20Mil
Space 15Mil
Length 500Mil

2

1

RC1628 0_0402_5%

+3VS

EC_SMI# 44

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

MCP (PCIE,SATA,USB3,USB2)

MCP (PCIE,SATA,USB3,USB2)

MCP (PCIE,SATA,USB3,USB2)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

9 60

9 60

of

9 60

1

of

1.0

1.0

1.0

5

D D

check the Pull up resistor

+3VS

RPC4

1

8

2

7

3

6
5

4

10K_0804_8P4R_5%

C

GPU_CLKREQ#
LAN_CLKREQ#

WLAN_CLKREQ#

PCIE CLK0 DGPU

PCIE CLK4

PCIE CLK5

B

LAN

WLAN

CLK_PCIE_LAN#37

CLK_PCIE_LAN37

LAN_CLKREQ#37

CLK_PCIE_WLAN#40

CLK_PCIE_WLAN40
WLAN_CLKREQ#40

4

GPU_CLKREQ#

CLK_PCIE_LAN#

CLK_PCIE_LAN
LAN_CLKREQ#

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U_BGA1356

REV = 1
@

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

REV = 1
@

UC1I

CSI-2

SKL_ULT

SKL_ULT

?

1 OF 20

?

CLOCK SIGNALS

3

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0

GPP_F14/EMMC_DATA1

GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4

GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

1 OF 20

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

?

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

SRTCRST#

RTCRST#

C37

D37
C32

D32

C29
D29
B26

A26

E13

B7

AP2

AP1

AP3
AN3

AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

RTCX1

RTCX2

?

CSI2_COMP

EMMC_RCOMP

CLK_PCIE_XDP#

F43

CLK_PCIE_XDP

E43

BA17

SUSCLK

XTAL24_IN

E37

XTAL24_OUT

E35

DIFFCLK_BIASREF

E42

RTC_X1

AM18

RTC_X2

AM20

SRTC_RST#

AN18

RTC_RST#

AM16

2

1

RC73 100_0402_1%

RC50 200_0402_1%

2

2

1

1

TC85 @

1

TC87 @

SUSCLK 40

1

RC72 2.7K_0402_1%

VCCRTC

2

1

RC33 20K_0402_1%

1

RC34 20K_0402_1%

1U_0402_6.3V6K

2

2

1U_0402_6.3V6K

+VCCCLK5

CC3

CC6

1

2

1

2

SRTC_RST#

RTC_RST#

1

JCMOS1
SHORT PADS

@

2

SUSCLK

DIFFCLK_BIASREF

RC1624

1

1

1

Cannonlake@

2

0_0402_5%

2

2

RC95 1K_0402_5%@

RC1555 60.4_0402_1%

1

@

EC_RTC_RST# 44

C

B

1

2

RC71 1M_0402_5%

YC2

1

2

GND12OSC2

1

OSC1

24MHZ_6PF_7V24000032

XTAL24_IN

CC12

3.3P_0402_50V8-C

A

5

need to use 38.4MHz (30ohm) for Cannonlake-u

4

GND2

3

4

XTAL24_OUT

1

CC11

2.7P_0402_50V9-B

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

RC32 10M_0402_5%

32.768KHZ_9PF_X1A0001410002

2

CC4
7P_0402_50V8J

1

2015/08/20

2015/08/20

2015/08/20

1

2

YC1

1

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

RTC_X1

RTC_X2

2

CC5
7P_0402_50V8J

1

Deciphered Date

Deciphered Date

Deciphered Date

when single end external clock generator used,
this pin should be grounded

Title

Title

Title

MCP (CSI2,EMMC,CLOCK)

MCP (CSI2,EMMC,CLOCK)

MCP (CSI2,EMMC,CLOCK)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

2

2016/08/20

2016/08/20

2016/08/20

A

1.0

1.0

10 60

10 60

1

10 60

1.0

of

of

5

D D

+3VALW

1 2

RC74 10K_0402_5%

1 2

RC75 8.2K_0402_5%

RC76 1K_0402_5%

1

C

RC90 10K_0402_5%

+3VALW_PCH

PLT_RST#32,37,40,44

EC_RSMRST#44

SYS_PWROK44
PCH_PWROK44

SUSWARN#44

SUSACK#44

PCIE_WAKE#37,40,44

AC_PRESENT_R

12

2

BATLOW#

WAKE#

PCH_LAN_WAKE#

VCCST_PWRGD_R

Follow CRB change to 1kohm

TC21PAD @

1

Reserve for DS3

4

1

@

1 2

1

1 2
1 2

1 2

1

1

2

2

2

2

RC84 0_0402_5%

RC85 0_0402_5%@

RC93 60.4_0402_1%

RC139 0_0402_5%@

RC126 0_0402_5%@

RC86 0_0402_5%@

RC79 0_0402_5%@

RC91 0_0402_5%@

PLT_RST#_R

SYS_RESET#

PCH_RSMRST#_R

CPU_PROCPWRGD
VCCST_PWRGD

SYS_PWROK_R
PCH_PWROK_R

PCH_DPWROK_R

SUSWARN#_R
SUSACK#_R

WAKE#

PCH_LAN_WAKE#

UC1K

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKYLAKE-U_BGA1356

REV = 1
@

3

SKL_ULT

?

1 OF 20

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B11/EXT_PWR_GATE#

INTRUDER#

GPP_B2/VRALERT#

2

AT11

PM_SLP_S3#_R

AP15

PM_SLP_S4#_R

BA16
AY16

PM_SLP_SUS#_R

AN15

AW15
BB17
AN16

PBTN_OUT#_R

BA15

AC_PRESENT_R

AY15
AU13

BATLOW#

AU11

PME#

AP16

INTVRMEN

AM10
AM11

?

1

TC89@

AC_PRESENT44

1
1

1 2

2

2

RC96 0_0402_5%@

RC97 0_0402_5%@

RC89 0_0402_5%@

Reserve for DS3

2

1

RC87 0_0402_5%@

RC41 330K_0402_5%

12

1

RC88 0_0402_5%@

ACIN#44

2

VCCRTC

2

G

PM_SLP_S3# 13,44
PM_SLP_S4# 44

PM_SLP_SUS# 44

PBTN_OUT# 44

AC_PRESENT_R

13

D

QC8
2N7002KW_SOT323-3

@

S

1

C

2

1

RC78 10K_0402_5%@

+3VS

1

RC80 10K_0402_5%

B

2

2

1

2

1

1

2

2

1

1

2

SUSWARN#_R

SYS_RESET#

PCH_RSMRST#_R

CC12541000P_0201_50V7-K

EMC_NS@

Stuff to fix Reset&PWRGD test fail issue

PCH_PWROK

CC1040.01U_0201_10V6K

PCH_DPWROK_R

CC1031000P_0201_50V7-K

EMC_NS@

SYS_PWROK

CC10147P_0201_25V8-J

EC_RSMRST#

CC12780.01U_0201_10V6K

+VCCST_CPU

+3VALW

RC136
10K_0402_5%

@

1 2

6

D

1 2

EC_VCCST_PWRGD44

RC138 0_0402_5%@

1

CC46

0.01U_0201_25V6-K

EMC_NS@

2

2

G

QC6A
2N7002KDWH_SOT363-6

@

S

1

2

RC137
1K_0402_5%

1

3

D

5

G

S

4

+VCCSTG

2

1

VCCST_PWRGD_R

QC6B
2N7002KDWH_SOT363-6

@

RC1554
1K_0402_5%

@

2

CC140
1000P_0201_50V7-K

EMC_NS@

1

B

Add to fix Reset&PWRGD test fail issue

1

RPC21

1

2

3
4

10K_0804_8P4R_5%

2

2

A

PCH_RSMRST#_R

8

PCH_PWROK

7

SYS_PWROK

6
5

PLT_RST#_R

1

RC92100K_0402_5%

PCH_DPWROK_R

1

RC94100K_0402_1% @

PM_SLP_S3#

1

DC4

RB751V-40_SOD323-2

2

@

RC1599 0_0402_5%@

2

EC_RSMRST#

DPWROK_EC 44

A

PCH_DPWROK_R

1

1 2

@

2

RC182 0_0402_5%@

RC81 0_0402_5%

Reserve for DS3

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

MCP (SYSTEM PWR MANAGEMENT)

MCP (SYSTEM PWR MANAGEMENT)

MCP (SYSTEM PWR MANAGEMENT)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

11 60

of

of

11 60

of

1

11 60

1.0

1.0

1.0

5

+CPU_CORE

D D

1

TC90@

+V1.8S_EDRAM

2

1

CC1085

2

10U_0402_6.3V6M

CD@

3.2A

0.05A

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO_SENSE
VSSEOPIO_SENSE

C

+VCCOPC_1.0V

+1.8VALW

RC1641

VCCOPC_SENSE57
VSSOPC_SENSE57

1

U23E@

0_0402_5%

+VCCEOPIO

For UMA 2+3e

+CPU_CORE

13x10uF 0402, SIT update to 0603 package

1

CC1086

2

10U_0402_6.3V6M

@

1

2

CC1080

10U_0603_6.3V6M

UC1L

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD_K32

AK32

RSVD_AK32

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO_AE62

AG62

VCCEOPIO_AG62

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

SKYLAKE-U_BGA1356

REV = 1
@

1

2

SKL_ULT

CPU POWER 1 OF 4

CC1236

10U_0603_6.3V6M

?

VCC_G32
VCC_G33

VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37
VCC_J40

VCC_K33

VCC_K35
VCC_K37
VCC_K38

VCC_K40
VCC_K42

VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

1 OF 20

1

1

CC1237

CC1093

2

2

10U_0603_6.3V6M

?

1

1

CC1092

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

G32
G33

G35
G37
G38
G40
G42
J30

J33
J37

J40
K33

K35
K37
K38

K40
K42

K43

E32

E33

B63
A63

D64

G20

CC1091

10U_0603_6.3V6M

+CPU_CORE

4

VCORE_VCC_SEN

VCORE_VSS_SEN

CPU_SVID_ALERT#_R
CPU_SVID_CLK_R

CPU_SVID_DAT_R

1

CC1089

2

10U_0603_6.3V6M

+VCCSTG

1

CC1238

2

10U_0603_6.3V6M

VCORE_VCC_SEN

VCORE_VSS_SEN

VCORE_VCC_SEN 59

VCORE_VSS_SEN 59

1

RC77 100_0402_1%

RC82 100_0402_1%

+VCC_GT

1

2

@

2

1

2

VR_SVID_ALRT#59

VR_SVID_CLK59

VR_SVID_DAT59

Backside Cap 8x10uF 0402, SIT update

1

1

CC1122

CC1123

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

@

@

3

+CPU_CORE

SVID

2

12

RC131

RC1544

1

56_0402_5%

100_0402_1%

@

1, Alert# Route Between CLK and Data

1

CC1124

2

10U_0402_6.3V6M

1

1

CC1125

2

10U_0402_6.3V6M

@

1

CC1127

CC1128

CC1126

2

2

10U_0402_6.3V6M

10U_0402_6.3V6M

CD@

CD@

VCCGT_VCC_SEN

VCCGT_VSS_SEN

+VCCST_CPU

1

RC132

2

100_0402_1%

RC133 220_0402_1%

RC134 0_0402_5%@

RC1545 0_0402_5%@

1

CC1129

2

10U_0402_6.3V6M

10U_0402_6.3V6M

1

1

CC42

0.1u_0201_10V6K

@

2

2

2

2

RC83 100_0402_1%

RC98 100_0402_1%

1

2

1

1

1 2

+VCC_GT

CPU_SVID_ALERT#_R

CPU_SVID_CLK_R

CPU_SVID_DAT_R

VCCGT_VCC_SEN59
VCCGT_VSS_SEN59

2

VCCGT_VCC_SEN
VCCGT_VSS_SEN

+VCC_GT

UC1M

A48

VCCGT_A48

A53

VCCGT_A53

A58

VCCGT_A58

A62

VCCGT_A62

A66

VCCGT_A66

AA63

VCCGT_AA63

AA64

VCCGT_AA64

AA66

VCCGT_AA66

AA67

VCCGT_AA67

AA69

VCCGT_AA69

AA70

VCCGT_AA70

AA71

VCCGT_AA71

AC64

VCCGT_AC64

AC65

VCCGT_AC65

AC66

VCCGT_AC66

AC67

VCCGT_AC67

AC68

VCCGT_AC68

AC69

VCCGT_AC69

AC70

VCCGT_AC70

AC71

VCCGT_AC71

J43

VCCGT_J43

J45

VCCGT_J45

J46

VCCGT_J46

J48

VCCGT_J48

J50

VCCGT_J50

J52

VCCGT_J52

J53

VCCGT_J53

J55

VCCGT_J55

J56

VCCGT_J56

J58

VCCGT_J58

J60

VCCGT_J60

K48

VCCGT_K48

K50

VCCGT_K50

K52

VCCGT_K52

K53

VCCGT_K53

K55

VCCGT_K55

K56

VCCGT_K56

K58

VCCGT_K58

K60

VCCGT_K60

L62

VCCGT_L62

L63

VCCGT_L63

L64

VCCGT_L64

L65

VCCGT_L65

L66

VCCGT_L66

L67

VCCGT_L67

L68

VCCGT_L68

L69

VCCGT_L69

L70

VCCGT_L70

L71

VCCGT_L71

M62

VCCGT_M62

N63

VCCGT_N63

N64

VCCGT_N64

N66

VCCGT_N66

N67

VCCGT_N67

N69

VCCGT_N69

J70

VCCGT_SENSE

J69

VSSGT_SENSE

SKYLAKE-U_BGA1356

REV = 1
@

SKL_ULT

CPU POWER 2 OF 4

?

1 OF 20

VCCGT_N70
VCCGT_N71
VCCGT_R63
VCCGT_R64

VCCGT_R65
VCCGT_R66
VCCGT_R67
VCCGT_R68
VCCGT_R69
VCCGT_R70
VCCGT_R71
VCCGT_T62

VCCGT_U65
VCCGT_U68
VCCGT_U71

VCCGT_W63
VCCGT_W64
VCCGT_W65
VCCGT_W66
VCCGT_W67

VCCGT_W68

VCCGT_W69

VCCGT_W70

VCCGT_W71

VCCGT_Y62

VCCGTX_AK42

VCCGTX_AK43

VCCGTX_AK45

VCCGTX_AK46

VCCGTX_AK48

VCCGTX_AK50

VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56

VCCGTX_AK58

VCCGTX_AK60

VCCGTX_AK70
VCCGTX_AL43

VCCGTX_AL46

VCCGTX_AL50

VCCGTX_AL53

VCCGTX_AL56

VCCGTX_AL60

VCCGTX_AM48

VCCGTX_AM50

VCCGTX_AM52

VCCGTX_AM53

VCCGTX_AM56

VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

1

+VCC_GT

N70
N71
R63
R64

R65
R66

R67

R68
R69
R70
R71
T62

U65
U68
U71

W63
W64
W65
W66
W67

W68

W69

W70

W71

Y62

AK42

AK43

AK45

AK46

AK48

AK50

AK52
AK53
AK55
AK56

AK58

AK60

AK70
AL43

AL46

AL50

AL53

AL56

AL60

AM48

AM50
AM52

AM53

AM56

AM58

AU58

AU63

BB57

BB66

AK62

AL61

?

+VCC_GT

For UMA 2+3e

VCCGTX_SENSE

VSSGTX_SENSE

1

TC133 @

1

TC134 @

C

B

For UMA 2+3e

A

+CPU_CORE

1

CC1095

2

1U_0402_6.3V6K

+VCCOPC_1.0V

RC1642 0_0805_5%U23E@

+VCCOPC_1.0V

1

2

U23E@

15x1uF 0201, SIT update to 0402 package

1

1

CC1096

2

1U_0402_6.3V6K

CC1268

10U_0402_6.3V6-M

CC1097

1U_0402_6.3V6K

1

U23E@

1

1

CC1098

CC1099

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCEOPIO

2

1

1

1

CC1270

CC1269

2

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

U23E@

U23E@

5

1

1

CC1101

CC1100

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CC1271

CC1272

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

U23E@

U23E@

+VCC_GT

Backside Cap 12x1uF 0201, SIT update

1

10U_0402_6.3V6-M

1

CC1108

2

@

+V1.8S_EDRAM

1

CC1277

2

@

4

CC1109

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

VCCOPC_SENSE

VSSOPC_SENSE

1U_0402_6.3V6K

VCCEOPIO_SENSE

VSSEOPIO_SENSE

VCCOPC_SENSE

VSSOPC_SENSE

1

CC1102

2

1U_0402_6.3V6K

1

CC1273

2

1U_0201_6.3V6-M

U23E@

1

1

CC1104

CC1105

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCEOPIO

1

1

U23E@

CC1275

CC1276

2

2

10U_0402_6.3V6-M

U23E@

CC1274

1U_0201_6.3V6-M

1

CC1111

2

1U_0402_6.3V6K

RC1643 100_0402_1%U23E@

RC1644 100_0402_1%

RC1645 100_0402_1%

RC1646 100_0402_1%U23E@

RC1647 0_0402_5%@

RC1648 0_0402_5%@

1U_0402_6.3V6K

2

1

1

2

U23E@

1

2

U23E@

1

2

1

2

1

2

1

CC1114

2

1

CC1116

CC1115

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCOPC_1.0V

+VCCEOPIO

VCCEOPIO_SENSE

VSSEOPIO_SENSE

1

1

2

3

1

CC1119

CC1118

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CC1241

CC1240

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCC_GT

Security Classification

Security Classification

Security Classification

THIS S HEE T OF ENGIN EERIN G DR AWIN G IS THE PRO PRIETAR Y PROPE RTY OF L C FUTURE CENTER. AND CON TAINS CONFIDENTIAL

THIS S HEE T OF ENGIN EERIN G DR AWIN G IS THE PRO PRIETAR Y PROPE RTY OF L C FUTURE CENTER. AND CON TAINS CONFIDENTIAL

THIS S HEE T OF ENGIN EERIN G DR AWIN G IS THE PRO PRIETAR Y PROPE RTY OF L C FUTURE CENTER. AND CON TAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

Backside Cap 8x10uF 0402

1

1

CC1261

CC1260

2

2

10U_0402_6.3V6-M

U23E@

U23E@

Issued Date

Issued Date

Issued Date

10U_0402_6.3V6-M

U23E@

1

1

1

CC1263

CC1262

2

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

U23E@

U23E@

2015/08/20

2015/08/20

2015/08/20

1

1

CC1264

CC1266

CC1265

2

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

U23E@

U23E@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

1

CC1267

2

10U_0402_6.3V6-M

10U_0402_6.3V6-M

U23E@

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

MCP (CPU PWR1)

MCP (CPU PWR1)

MCP (CPU PWR1)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

1

of

12 60

12 60

of

12 60

B

A

1.0

1.0

1.0

5

+1.2V

D D

1

2

CD@

+1.2V

C

2A , 3x22uF, 6x10uF, 4x1uF, SIT update

1

1

CC1256

2

22U_0603_6.3V6-M

1

1

CC1257

RC1497 0_0402_5%

RC104 0_0402_5%

CC1168

CC1258

2

2

2

10U_0603_6.3V6M

CD@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

2

@

1

2

@

CC1169

10U_0402_6.3V6M

+VDDQ_CPU_CLK

@

+VCCSFR_OC

1

1

1

1

1

CC1222

CC1171

CC1223

2

2

10U_0402_6.3V6M

1

1

CC1229

2

2

1U_0201_6.3V6-M

1

CC85

2

1U_0201_6.3V6-M

CC1243

2

2

10U_0603_6.3V6M

CC1228

10U_0402_6.3V6M

2

10U_0603_6.3V6M

10U_0402_6.3V6M

@

@

+VCCIO

+VCCST_CPU

Reserved for VCCST/VCCSTG/VCCPLL
power optimized

+VCCST_CPU

1

CC1244

CC1224

2

1U_0201_6.3V6-M

10U_0402_6.3V6M

CD@

1 2

RC103 0_0402_5%@

1 2

RC1604 0_0402_5%@

RC105 0_0402_5%@

1

1

CC1225

CC1226

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

@

CD@

+VCCSTG

1

2

4

+1.2V

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

1

CC1227

2

1U_0201_6.3V6-M

@

+VCCST_CPU

+VDDQ_CPU_CLK

+VCCST_CPU

+VCCSTG

+VCCSFR_OC

+VCCPLL_CPU

AM40

AL23

A18

A22

K20

K21

VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20

VCCPLL_K21

UC1N

CPU POWER 3 OF 4

SKL_ULT

?

120mA

1

1

2

CC87

1U_0402_6.3V6K

CC86

2

+VCCPLL_CPU

SKYLAKE-U_BGA1356

REV = 1

1U_0402_6.3V6K

@

1 OF 20

120mA

1

1

CC84

CC1249

2

2

1U_0402_6.3V6K

0.1u_0201_10V6K

VCCIO_AK28

VCCIO_AK30

VCCIO_AL30

VCCIO_AL42
VCCIO_AM28
VCCIO_AM30

VCCIO_AM42

VCCSA_AK23
VCCSA_AK25

VCCSA_G23

VCCSA_G25

VCCSA_G27

VCCSA_G28

VCCSA_J22

VCCSA_J23

VCCSA_J27

VCCSA_K23

VCCSA_K25

VCCSA_K27

VCCSA_K28

VCCSA_K30

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

3

AK28

AK30

AL30
AL42
AM28
AM30

AM42

AK23
AK25

G23

G25

G27

G28

J22

J23

J27
K23

K25

K27

K28

K30

AM23

AM22

H21

H20

?

VCCSA_VCC_SEN

VCCSA_VSS_SEN

+VCCIO

+VCCSA

VCCIO_SENSE

VSSIO_SENSE

VCCSA_VSS_SEN

VCCSA_VCC_SEN

1
1

1

RC101 100_0402_1%

1

RC102 100_0402_1%

TC136 @
TC137 @

VCCSA_VSS_SEN 59

VCCSA_VCC_SEN 59

2

2

+VCCSA

2

+VCCIO

3.1A 2x10uF, 4x1uF

+VCCSA

1

1

CC1152

2

2

10U_0402_6.3V6M

1

1

CC1153

CC1158

CC1159

2

2

1U_0201_6.3V6-M

10U_0402_6.3V6M

1U_0201_6.3V6-M

@

@

4.5A 10x10uF, 7x1uF, SIT update

1

1

1

2

2

CC1132

10U_0603_6.3V6M

1

CC1134

CC1133

CC1135

2

2

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

@

@

1

1

1

CC1160

2

2

1U_0201_6.3V6-M

@

@

1

1

CC1136

2

2

10U_0603_6.3V6M

1

1

CC1161

CC1218

2

2

1U_0402_6.3V6K

1U_0201_6.3V6-M

1

CC1137

2

10U_0603_6.3V6M

1

1

CC1230

CC1251

CC1232

CC1231

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

@

1

1

CC1252

2

2

10U_0402_6.3V6M

@

@

1

1

CC1253

2

10U_0402_6.3V6M

1

1

CC1140

CC1139

CC1142

2

2

2

1U_0402_6.3V6K

CD@

1U_0402_6.3V6K

CD@

1U_0402_6.3V6K

1

1

CC1145

2

1U_0402_6.3V6K

1

CC1143

CC1141

CC1144

2

2

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CD@

1U_0201_6.3V6-M

C

+1.0VALW

1

+5VALW

VCCST_EN#

2

Deciphered Date

Deciphered Date

Deciphered Date

2

2

RC1650 47K_0402_5%@

RC142

5

G

+3VALW

RC1605 0_0402_5%@

V20B+

1

RC141

47K_0402_5%

EC_VCCST_EN

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Reserved for VCCST/VCCSTG/VCCPLL power optimized

B

1

1

CC72

CC71

2

2

@

1 2

1

2

2

G

3

D

QC12B
2N7002KDWH_SOT363-6

S

4

22U_0603_6.3V6-M

6

D

2N7002KDWH_SOT363-6

S

1

4

+5VALW

RC1649 47K_0402_5%@

V20B+

+3VALW

RC128

2

RC1575

47K_0402_5%

@

A

EC_VCCIO_EN44

PM_SLP_S3#11,44

RC1577 0_0402_5%@

DC1

5

2

1

2

1

RB751V-40_SOD323-2

1

VCCIO_EN

@

RC1621 100K_0402_5%

VCCIO_EN#

1

2

47K_0402_5%

5

G

+1.0VALW

@

10U_0603_6.3V6M

QC12A

1

2

CC1279

5

0.1u_0201_10V6K

AON7408L_DFN8-5
QC11

D

G

4

1

2

+VCCIO

1

S1

2

S2

3

S3

@

1

CC77

2

0.01U_0201_25V6-K

1

2

CC1280

0.1u_0201_10V6K

RC125
820K_0402_5%

CC1250

1

1

C1102

2

2

@

10U_0603_6.3V6M

22U_0603_6.3V6-M

VCCIO_EN#

1

RC124
470_0603_5%

@

2

13

D

2

QC13

G

2N7002KW_SOT323-3

@

S

EC_VCCST_EN44

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS S HEE T OF ENGIN EERIN G DR AWIN G IS THE PRO PRIETAR Y PROPE RTY OF L C FUTURE CENTER. AND CON TAINS CONFIDENTIAL

THIS S HEE T OF ENGIN EERIN G DR AWIN G IS THE PRO PRIETAR Y PROPE RTY OF L C FUTURE CENTER. AND CON TAINS CONFIDENTIAL

THIS S HEE T OF ENGIN EERIN G DR AWIN G IS THE PRO PRIETAR Y PROPE RTY OF L C FUTURE CENTER. AND CON TAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

2015/08/20

2015/08/20

2

1

1 2

100K_0402_5%

2

G

34

D

QC16B
2N7002KDWH_SOT363-6

S

+VCCST_CPU

+1.0VALW

CC79

61

D

S

2016/08/20

2016/08/20

2016/08/20

1

1

@

2

2

10U_0603_6.3V6M

CC1281

0.1u_0201_10V6K

QC16A
2N7002KDWH_SOT363-6

QC19
AO3402_SOT-23-3

D1S

+VCCST_CPU

3

G

2

1

2

1

1

CC80

@

2

@

2

10U_0603_6.3V6M

CC1282

0.1u_0201_10V6K

VCCST_EN#

2

RC1584
120K_0402_5%

CC81

1

0.01U_0201_25V6-K

1

RC135
470_0603_5%

@

2

13

D

2

G

S

+VCCST_CPU switch

Title

Title

Title

MCP (CPU PWR2)

MCP (CPU PWR2)

MCP (CPU PWR2)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

1

QC14
2N7002KW_SOT323-3

@

13 60

of

13 60

of

13 60

B

A

1.0

1.0

1.0

5

4

3

2

1

+3VALW_PCH

1

RC1503 0_0603_5%@

+1.0VALW

RC1504 BLM18EG221TN1D_2P

D D

+1.0VALW +VCCAPLL_1P0

+1.0VALW

2

1

2

1

RC1620 0_0402_5%@

+VCCAMPHY

+VCCHDA

1

+3VALW_PCH

VCCMPHYON_1P0_L1

2

RC1586 BLM18EG221TN1D_2P

2

1

RC1622 0_0402_5%@

2

+VCCPGPPG

1

CC144

2

C

B

+VCCAMPHY

+VCCAPLL_1P0

+1.0VALW

1U_0402_6.3V6K

1

2

CC153

1U_0402_6.3V6K

VCCMPHYON_1P0_L1

11mA

+1.0VALW

0.696A

Near AB19

33mA

1

CC141

2

@

1U_0402_6.3V6K

1

CC169

2

AB19

AB20

P18

AF18

AF19

V20

V21

AL1

K17

L1

N15
N16

N17
P15
P16

K15

L15

V15

AB17

Y18

AD17
AD18
AJ17

AJ19

AJ16

AF20
AF21

T19

T20

AJ21

AK20

N18

1U_0402_6.3V6K

SKYLAKE-U_BGA1356

REV = 1
@

UC1O

VCCPRIM_1P0_AB19

VCCPRIM_1P0_AB20
VCCPRIM_1P0_P18

VCCPRIM_CORE_AF18

VCCPRIM_CORE_AF19
VCCPRIM_CORE_V20

VCCPRIM_CORE_V21

DCPDSW_1P0

VCCMPHYAON_1P0_K17
VCCMPHYAON_1P0_L1

VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16

VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0_K15
VCCAMPHYPLL_1P0_L15

VCCAPLL_1P0

VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0_AF20
VCCSRAM_1P0_AF21

VCCSRAM_1P0_T19

VCCSRAM_1P0_T20

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

SKL_ULT

CPU POWER 4 OF 4

?

1 OF 20

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD

VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

+1.0VALW

1

2

CC145

1U_0402_6.3V6K

+3VALW

68mA

+3VALW_PCH

2.574A22mA

1

CC158

2

@

Near AF18

22U_0603_6.3V6-M

0.118A

+1.0VALW

Near N15

88mA

1

CC151

2

1U_0402_6.3V6K

1

CC154

2

1U_0402_6.3V6K

@

Near K15

22mA

+1.0VALW

1

CC159

2

CD@

1U_0402_6.3V6K

1.5A

1

CC148

2

47U_0805_4V6-M

Near AF20

1

CC147

2

1U_0201_6.3V6-M

0.642A

+3VALW_PCH

+VCCHDA

+1.0VALW

1

C1096

2

@

22U_0603_6.3V6-M

1

C1097

2

0.1u_0201_10V6K

+VCCDSW_1P0

1

CC171

2

CD@

1U_0402_6.3V6K

+1.0VALW

PCH Internal VRM

1

CC165

2

0.1u_0201_10V6K

75mA

+1.0VALW

Near A18

+3VALW_PCH

1

1

CC156

2

@

20mA

AK15

4mA

AG15

6mA

Y16

8mA

Y15

6mA

T16

161mA

AF16

61mA

AD15

V19

T1

6mA

AA1

1mA

AK17

AK19
BB14

BB10

VCCRTCEXT

35mA

A14

29mA

K19

24mA

L21

33mA

N20

4mA

L19

10mA

A10

AN11
AN13

?

1U_0402_6.3V6K

1mA

1

1

1

CC173

CC164

CC172

2

2

2

@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

Near Y15

+1.8VALW

+1.0VALW

+1.0VALW

+1.0VALW

+VCCCLK4

+VCCCLK5

+VCCPGPPG

CC174

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC57

2

1U_0402_6.3V6K

1

2

@

+1.0VALW

1

RC1588 0_0603_5%@

1

C1099

2

@

22U_0603_6.3V6-M

1

RC1589 0_0603_5%@

1

C1100

2

@

22U_0603_6.3V6-M

CC175

1U_0402_6.3V6K

1

2

2

2

1

CC176

2

@

1U_0402_6.3V6K

1

RC1587 0_0603_5%@

1

CC56

2

@

1U_0402_6.3V6K

+1.0VALW+VCCCLK4

+1.0VALW+VCCCLK5

C1098

22U_0603_6.3V6-M

+3VALW_PCH

2

+1.8VALW

1

CC142

2

1U_0402_6.3V6K

+1.0VALW

1

CC149

2

0.1u_0201_10V6K

1

CC55

2

0.1u_0201_10V6K

+3VALW_PCH

1

CC143

2

1U_0402_6.3V6K

VCCRTC

1

1

CC146

CC1242

2

2

1U_0402_6.3V6K

0.1u_0201_10V6K

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF E NGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF E NGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF E NGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SEC RET INF ORMATION. THIS SHEET MAY N OT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SEC RET INF ORMATION. THIS SHEET MAY N OT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SEC RET INF ORMATION. THIS SHEET MAY N OT B E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED B Y LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY O R DISC LOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY O R DISC LOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY O R DISC LOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

MCP (PCH PWR)

MCP (PCH PWR)

MCP (PCH PWR)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet

Date: Sheet of

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

1

of

14 60

14 60

14 60

A

1.0

1.0

1.0

5

?

SKL_ULT

UC1P

GND 1 OF 3

A5

VSS_A5

A67

VSS_A67

A70

D D

C

B

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD13

AD16

VSS_AD16

AD19

VSS_AD19

AD20

VSS_AD20

AD21

VSS_AD21

AD62

VSS_AD62

AD8

VSS_AD8

AE64

VSS_AE64

AE65

VSS_AE65

AE66

VSS_AE66

AE67

VSS_AE67

AE68

VSS_AE68

AE69

VSS_AE69

AF1

VSS_AF1

AF10

VSS_AF10

AF15

VSS_AF15

AF17

VSS_AF17

AF2

VSS_AF2

AF4

VSS_AF4

AF63

VSS_AF63

AG16

VSS_AG16

AG17

VSS_AG17

AG18

VSS_AG18

AG19

VSS_AG19

AG20

VSS_AG20

AG21

VSS_AG21

AG71

VSS_AG71

AH13

VSS_AH13

AH6

VSS_AH6

AH63

VSS_AH63

AH64

VSS_AH64

AH67

VSS_AH67

AJ15

VSS_AJ15

AJ18

VSS_AJ18

AJ20

VSS_AJ20

AJ4

VSS_AJ4

AK11

VSS_AK11

AK16

VSS_AK16

AK18

VSS_AK18

AK21

VSS_AK21

AK22

VSS_AK22

AK27

VSS_AK27

AK63

VSS_AK63

AK68

VSS_AK68

AK69

VSS_AK69

AK8

VSS_AK8

AL2

VSS_AL2

AL28

VSS_AL28

AL32

VSS_AL32

AL35

VSS_AL35

AL38

VSS_AL38

AL4

VSS_AL4

AL45

VSS_AL45

AL48

VSS_AL48

AL52

VSS_AL52

AL55

VSS_AL55

AL58

VSS_AL58

AL64

VSS_AL64

SKYLAKE-U_BGA1356

REV = 1
@

1 OF 20

VSS_AL65

VSS_AL66
VSS_AM13
VSS_AM21
VSS_AM25

VSS_AM27
VSS_AM43

VSS_AM45
VSS_AM46
VSS_AM55

VSS_AM60
VSS_AM61
VSS_AM68
VSS_AM71

VSS_AM8

VSS_AN20

VSS_AN23

VSS_AN28

VSS_AN30

VSS_AN32

VSS_AN33

VSS_AN35

VSS_AN37

VSS_AN38

VSS_AN40

VSS_AN42

VSS_AN58

VSS_AN63

VSS_AP10

VSS_AP18

VSS_AP20

VSS_AP23

VSS_AP28

VSS_AP32

VSS_AP35

VSS_AP38

VSS_AP42

VSS_AP58

VSS_AP63

VSS_AP68

VSS_AP70

VSS_AR11

VSS_AR15

VSS_AR16

VSS_AR20

VSS_AR23

VSS_AR28

VSS_AR35

VSS_AR42

VSS_AR43

VSS_AR45

VSS_AR46

VSS_AR48

VSS_AR5
VSS_AR50
VSS_AR52

VSS_AR53
VSS_AR55

VSS_AR58
VSS_AR63

VSS_AR8

VSS_AT2
VSS_AT20
VSS_AT23

VSS_AT28
VSS_AT35

VSS_AT4

VSS_AT42
VSS_AT56
VSS_AT58

4

AL65
AL66
AM13
AM21
AM25

AM27
AM43

AM45
AM46
AM55

AM60
AM61
AM68
AM71
AM8

AN20
AN23
AN28
AN30
AN32

AN33
AN35
AN37

AN38
AN40
AN42
AN58
AN63
AP10

AP18
AP20
AP23
AP28
AP32
AP35
AP38

AP42
AP58

AP63
AP68
AP70
AR11

AR15
AR16
AR20
AR23
AR28

AR35
AR42
AR43
AR45
AR46
AR48

AR5
AR50
AR52

AR53
AR55

AR58
AR63

AR8
AT2
AT20

AT23
AT28
AT35
AT4

AT42
AT56
AT58

?

3

UC1Q

AT63

VSS_AT63

AT68

VSS_AT68

AT71

VSS_AT71

AU10

VSS_AU10

AU15

VSS_AU15

AU20

VSS_AU20

AU32

VSS_AU32

AU38

VSS_AU38

AV1

VSS_AV1

AV68

VSS_AV68

AV69

VSS_AV69

AV70

VSS_AV70

AV71

VSS_AV71

AW10

VSS_AW10

AW12

VSS_AW12

AW14

VSS_AW14

AW16

VSS_AW16

AW18

VSS_AW18

AW21

VSS_AW21

AW23

VSS_AW23

AW26

VSS_AW26

AW28

VSS_AW28

AW30

VSS_AW30

AW32

VSS_AW32

AW34

VSS_AW34

AW36

VSS_AW36

AW38

VSS_AW38

AW41

VSS_AW41

AW43

VSS_AW43

AW45

VSS_AW45

AW47

VSS_AW47

AW49

VSS_AW49

AW51

VSS_AW51

AW53

VSS_AW53

AW55

VSS_AW55

AW57

VSS_AW57

AW6

VSS_AW6

AW60

VSS_AW60

AW62

VSS_AW62

AW64

VSS_AW64

AW66

VSS_AW66

AW8

VSS_AW8

AY66

VSS_AY66

B10

VSS_B10

B14

VSS_B14

B18

VSS_B18

B22

VSS_B22

B30

VSS_B30

B34

VSS_B34

B39

VSS_B39

B44

VSS_B44

B48

VSS_B48

B53

VSS_B53

B58

VSS_B58

B62

VSS_B62

B66

VSS_B66

B71

VSS_B71

BA1

VSS_BA1

BA10

VSS_BA10

BA14

VSS_BA14

BA18

VSS_BA18

BA2

VSS_BA2

BA23

VSS_BA23

BA28

VSS_BA28

BA32

VSS_BA32

BA36

VSS_BA36

F68

VSS_F68

BA45

VSS_BA45

SKYLAKE-U_BGA1356

REV = 1
@

SKL_ULT

GND 2 OF 3

?

1 OF 20

VSS_BA49

VSS_BA53

VSS_BA57

VSS_BA6

VSS_BA62

VSS_BA66

VSS_BA71

VSS_BB18

VSS_BB26

VSS_BB30

VSS_BB34

VSS_BB38

VSS_BB43

VSS_BB55

VSS_BB6

VSS_BB60

VSS_BB64

VSS_BB67
VSS_BB70

VSS_C1

VSS_C25

VSS_C5

VSS_D10

VSS_D11

VSS_D14

VSS_D18

VSS_D22

VSS_D25

VSS_D26

VSS_D30

VSS_D34

VSS_D39

VSS_D44

VSS_D45

VSS_D47
VSS_D48

VSS_D53

VSS_D58

VSS_D6

VSS_D62

VSS_D66

VSS_D69

VSS_E11

VSS_E15

VSS_E18

VSS_E21

VSS_E46

VSS_E50

VSS_E53

VSS_E56

VSS_E6

VSS_E65

VSS_E71

VSS_F1

VSS_F13

VSS_F2

VSS_F22

VSS_F23

VSS_F27

VSS_F28

VSS_F32

VSS_F33

VSS_F35

VSS_F37

VSS_F38

VSS_F4

VSS_F40

VSS_F42

VSS_BA41

2

?

SKL_ULT

BA49

BA53

BA57

BA6

BA62

BA66

BA71

BB18

BB26

BB30

BB34
BB38

BB43

BB55

BB6

BB60

BB64

BB67
BB70

C1

C25

C5

D10

D11

D14

D18

D22

D25

D26

D30

D34

D39

D44

D45

D47
D48

D53

D58

D6

D62

D66

D69
E11

E15

E18

E21

E46

E50

E53

E56

E6
E65

E71

F1

F13
F2

F22

F23
F27

F28
F32

F33

F35

F37

F38

F4

F40

F42

BA41

?

UC1R

GND 3 OF 3

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

VSS_K63

K64

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

SKYLAKE-U_BGA1356

REV = 1
@

1 OF 20

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8
VSS_N10
VSS_N13
VSS_N19
VSS_N21

VSS_N6
VSS_N65
VSS_N68
VSS_P17

VSS_P19
VSS_P20
VSS_P21
VSS_R13

VSS_R6
VSS_T15

VSS_T17

VSS_T18

VSS_T2

VSS_T21

VSS_T4
VSS_U10

VSS_U63
VSS_U64
VSS_U66

VSS_U67
VSS_U69
VSS_U70
VSS_V16
VSS_V17
VSS_V18

VSS_W13

VSS_W6
VSS_W9

VSS_Y17

VSS_Y19

VSS_Y20

VSS_Y21

L18
L2
L20
L4

L8
N10
N13
N19
N21
N6
N65
N68
P17
P19

P20
P21
R13

R6
T15

T17

T18
T2

T21
T4
U10

U63
U64
U66

U67
U69
U70
V16
V17
V18
W13

W6
W9
Y17

Y19

Y20
Y21

?

1

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PRO PERT Y OF L C FU TU RE CEN TER . AND CO NTAIN S CON FIDENTIAL

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRAD E SECR ET INFORMATION . THIS SH EET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISC LOSED TO AN Y THIR D PART Y W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

MCP (VSS)

MCP (VSS)

MCP (VSS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

Date: Sheet

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

CG413

CG413

CG413

of

15 60

15 60

of

1

15 60

A

1.0

1.0

1.0

5

CPU_CFG0

D D

2

RC1618
1K_0402_5%

@

1

C

B

2

RC106
1K_0402_5%

1

2

RC162

49.9_0402_1%

1

Pin Name Strap Description Configura tion

A

CFG[4] Display Port

Presence strap

—1 = eDP Disabled
—0 = eDP Enabled

5

TC142PAD@
TC143PAD@

@

TC144PAD

@

TC146PAD

TC147PAD@

TC148PAD@

TC153PAD@
TC150PAD@
TC151PAD@

TC152PAD@

TC157PAD@

TC154PAD@

TC155PAD@

TC156PAD@

TC159PAD@

TC158PAD@

TC161PAD@

TC160PAD@

TC166PAD

@

TC186PAD@

TC189PAD@
TC191PAD@

TC171PAD@

TC172PAD@

TC169PAD@

TC170PAD@

Default
Value

1

*

CPU_CFG1

1

CPU_CFG2

1

XDP_CPU_CFG3

1

CPU_CFG4
CPU_CFG5

1

CPU_CFG6

1

CPU_CFG7

1

CPU_CFG8

1

CPU_CFG9

1

CPU_CFG10

1

CPU_CFG11

1

CPU_CFG12

1

CPU_CFG13

1

CPU_CFG14

1

CPU_CFG15

1

CPU_CFG16

1

CPU_CFG17

1

CPU_CFG18

1

CPU_CFG19

1

CFG_RCOMP

XDP_ITP_PMODE

1

1

1

1

1

1

1

1

4

E68
B67

D65

D67
E70

C68
D68
C67

F71
G69
F70

G68
H70
G71

H69
G70

E63
F63

E66
F66

E60

E8

AY2

AY1

D1
D3

K46
K45

AL25
AL27

C71
B70

F60

A52

BA70
BA68

J71

J68

F65
G65

F61
E61

SKYLAKE-U_BGA1356

REV = 1
@

4

UC1S

CFG[0]
CFG[1]

CFG[2]

CFG[3]
CFG[4]

CFG[5]
CFG[6]
CFG[7]

CFG[8]
CFG[9]

CFG[10]
CFG[11]
CFG[12]
CFG[13]

CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2

RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25
RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70
RSVD_TP_BA68

RSVD_J71

RSVD_J68

VSS_F65
VSS_G65

RSVD_F61
RSVD_E61

SKL_ULT

RESERVED SIGNALS-1

?

1 OF 20

3

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13

RSVD_TP_AK12

RSVD_TP_AW71
RSVD_TP_AW70

PROC_SELECT#

BB68
BB69

AK13

AK12

BB2

RSVD_BB2

BA3

RSVD_BA3

AU5

TP5

AT5

TP6

D5

RSVD_D5

D4

RSVD_D4

B2

RSVD_B2

C2

RSVD_C2

B3

RSVD_B3

A3

RSVD_A3

AW1

RSVD_AW1

E1

RSVD_E1

E2

RSVD_E2

BA4

RSVD_BA4

BB4

RSVD_BB4

A4

RSVD_A4

C4

RSVD_C4

BB5

TP4

A69

RSVD_A69

B69

RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54

RSVD_D54

TP1
TP2

VSS_AY71

ZVM#

MSM#

?

Security Classifica tion

Security Classifica tion

Security Classifica tion

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERT Y O F LC F UTU RE CE NT ER. AND C ONTA INS CO NFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERT Y O F LC F UTU RE CE NT ER. AND C ONTA INS CO NFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERT Y O F LC F UTU RE CE NT ER. AND C ONTA INS CO NFIDENTIAL

AND T RADE S ECRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND T RADE S ECRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND T RADE S ECRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTEN CONSENT OF LC FUTURE CENTER.

AY3

D71
C70

C54

D54

AY4
BB3

AY71

AR56

AW71

AW70

AP56

C64

RSVD_AY3

VSS_AY71

PROC_SELECT#

3

2015/08/20

2015/08/20

2015/08/20

1

TC173 PAD@

1

TC174 PAD@

1

TC175 PAD@

1

TC176 PAD@

1

TC183 PAD@

1

TC185 PAD@

1

TC184 PAD@

1

TC181 PAD@

1

TC187 PAD

@

1

TC182 PAD@

1

TC188 PAD@

1

TC193 PAD@

1

TC190 PAD@

1

TC192 PAD@

ZVM# 57

1

TC177 PAD@

1

TC178 PAD@

1

TC168 PAD@

2

1

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+1.8VALW

need to check with Intel

need to check with Intel

For UMA 2+3e

R22100K_0402_5% Cannonlake@

2

Cannonlake@

2

RC1582 0_0402_5%

2

RC1583 0_0402_5%

Cannonlake@

+VCCST_CPU

2

1

1

2016/08/20

2016/08/20

2016/08/20

2

1

2

1

RSVD_U12
RSVD_U11

RC107
0_0402_5%

RC108
0_0402_5%

1

F6
E3

C11
B11
A11
D12

C12
F52

+VCCST_CPU

RSVD_F52

16 60

16 60

16 60

12

RC1619
150_0402_5%

@

of

?

SKL_ULT

UC1T

AW69

AW68

AU56

AW48

C7
U12
U11
H11

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

Date: Sheet of

SPARE

RSVD_AW69

RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11

SKYLAKE-U_BGA1356

REV = 1
@

MCP (CFG,RESERVED)

MCP (CFG,RESERVED)

MCP (CFG,RESERVED)

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

1 OF 20

RSVD_F6
RSVD_E3

RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12

RSVD_C12
RSVD_F52

CG413

CG413

CG413

?

1

1.0

1.0

1.0

C

B

A

5

DDRA_MA0

DDRA_MA1

DDRA_MA2

DDRA_MA3

DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7

DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11

DDRA_MA12

DDRA_MA13

D D

C

B

A

DDRA_MA14_WE#5
DDRA_MA15_CAS#5
DDRA_MA16_RAS#5

DDRA_CLK0#5
DDRA_CLK05

DDRA_CKE05

+1.2V

RD65 0_0402_5%

RD68 0_0402_5%

DDRA_BS0#5
DDRA_BS1#5

DDRA_ACT#5
DDRA_CS0#5

DDRA_ALERT#5

DDRA_BG05

DDRA_ODT05

DDRA_PAR5

RD94 10K_0402_5%

CPU_DRAMRST#6,18

+1.2V

RD87 0_0402_5%@

RD88 0_0402_5%@

RD96 10K_0402_5%

1

1

1

1

1

1

DDRA_MA14_WE#
DDRA_MA15_CAS#

DDRA_MA16_RAS#

DDRA_CLK0#
DDRA_CLK0

DDRA_CKE0

DDRA_DQS#0

DDRA_DQS0

DDRA_DQS#1

DDRA_DQS1

DDRA_DM1

2

@

DDRA_DM0

2

@

DDRA_BS0#

DDRA_BS1#

DDRA_ACT#

DDRA_CS0#

DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD1 TEN_UD2

2

CPU_DRAMRST#

@

1

2

CD47

0.1u_0201_10V6K

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3

DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8

DDRA_MA9
DDRA_MA10

DDRA_MA11
DDRA_MA12
DDRA_MA13

DDRA_MA14_WE#
DDRA_MA15_CAS#
DDRA_MA16_RAS#

DDRA_CLK0#
DDRA_CLK0

DDRA_CKE0

DDRA_DQS#5

DDRA_DQS5
DDRA_DQS#4
DDRA_DQS4

DDRA_DM4

2

DDRA_DM5 DDRA_DM6

2

DDRA_BS0#
DDRA_BS1#

DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD3

2

CPU_DRAMRST#

@

1

2

0.1u_0201_10V6K

CD107

UD1

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD39

MT40A512M16HA083EA_FBGA96

240_0402_1%

UD3

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

1

MT40A512M16HA083EA_FBGA96

RD43
240_0402_1%

2

VDD10

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8
VDDQ9

VDDQ10

VREFCA

VDD10

VDDQ1

VDDQ2

VDDQ3

VDDQ4
VDDQ5

VDDQ6

VDDQ7
VDDQ8
VDDQ9

VDDQ10

VREFCA

DQ0

DQ1

DQ2

DQ3

DQ4
DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VPP1

VPP2

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

@

DDRA_DQ2

G2

DDRA_DQ3

DQ0

F7

DDRA_DQ7

DQ1

H3

DDRA_DQ1

DQ2

H7

DDRA_DQ4

DQ3

H2

DDRA_DQ0

DQ4

H8

DDRA_DQ6

DQ5

J3

DDRA_DQ5

DQ6

J7

DDRA_DQ11

DQ7

A3

DDRA_DQ8

DQ8

B8

DDRA_DQ14

DQ9

C3

DDRA_DQ13

DQ10

C7

DDRA_DQ15

DQ11

C2

DDRA_DQ12

DQ12

C8

DDRA_DQ10

DQ13

D3

DDRA_DQ9

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

L9

VDD9

T9

A1

C1

G1

F2
J2

F8

J8
A9

D9
G9

B1

VPP1

R9

VPP2

VSS1

VSS2

VSS3
VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

@

NC

+VREF_CA_MD

M1

E1

K1

N1

T1
B2

G8

E9

K9

M9

T7

NC

G2

F7

H3

H7
H2
H8

J3

J7

A3

B8

C3

C7

C2

C8

D3

D7

D1

J1

L1

R1

B3

G7

B9

J9

L9

T9

A1

C1

G1

F2
J2

F8

J8

A9
D9

G9

B1

R9

M1

E1

K1

N1

T1

B2

G8

E9

K9

M9

T7

DDRA_DQ43

DDRA_DQ44
DDRA_DQ46

DDRA_DQ40
DDRA_DQ47
DDRA_DQ45

DDRA_DQ42
DDRA_DQ41

DDRA_DQ34
DDRA_DQ37
DDRA_DQ39
DDRA_DQ32
DDRA_DQ35
DDRA_DQ33

DDRA_DQ38

DDRA_DQ36

+1.2V

+VREF_CA_MD

1

2

.047U_0201_6.3V6K

CD113

1

2

.047U_0201_6.3V6K

CD115

4

DDRA_MA0
DDRA_MA1
DDRA_MA2

R3

DDRA_MA3
DDRA_MA4

DDRA_MA5
DDRA_MA6
DDRA_MA7

R8

DDRA_MA8

R2

DDRA_MA9

R7

DDRA_MA10

M3

DDRA_MA11
DDRA_MA12

M7

DDRA_MA13

DDRA_MA14_WE#
DDRA_MA15_CAS#

M8

DDRA_MA16_RAS#

DDRA_CLK0#

DDRA_CLK0

DDRA_CKE0

DDRA_DQS#2
DDRA_DQS2

G3

DDRA_DQS#3

+1.2V

1

RD66 0_0402_5%@

1

RD69 0_0402_5%@

+2.5V_DDR

1

1

1

2

0.1u_0201_10V6K

CD120

1

2

0.1u_0201_10V6K

CD149

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD123

CD121

+2.5V_DDR

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD150

CD151

+1.2V

RD89 0_0402_5%@

RD90 0_0402_5%

RD97 10K_0402_5%

1

RD95 10K_0402_5%

1

1

@

1

DDRA_DQS3

DDRA_DM3

2

DDRA_DM2

2

DDRA_BS0#

DDRA_BS1#

DDRA_ACT#

DDRA_CS0#

DDRA_ALERT#

DDRA_BG0

M2

DDRA_ODT0

DDRA_PAR

2

CPU_DRAMRST#

@

1

2

CD48

0.1u_0201_10V6K

DDRA_MA0
DDRA_MA1

DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6

DDRA_MA7
DDRA_MA8
DDRA_MA9

DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13

DDRA_MA14_WE#

DDRA_MA15_CAS#
DDRA_MA16_RAS#

DDRA_CLK0#
DDRA_CLK0

DDRA_CKE0

DDRA_DQS#7
DDRA_DQS7
DDRA_DQS#6
DDRA_DQS6

2

DDRA_DM7

2

DDRA_BS0#
DDRA_BS1#

DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD4

2

CPU_DRAMRST#

@

1

2

0.1u_0201_10V6K

CD108

D2

D8

C9

1

RD40
240_0402_1%

2

UD4

P3

P7

R3

N7

N3

P8

P2

R8

R2

R7

M3

T2

M7

T8

L2

M8

L8

K8

K7

K2

F3

G3

A7

B7

E2

E7

N2

N8

L3

L7

P9

M2

K3

T3

N9

P1

F1
H1

A2

D2
E3

A8
D8

E8

C9

H9

F9

1

RD44

MT40A512M16HA083EA_FBGA96

240_0402_1%

2

UD2

P3

A0

P7

A1

A2

N7

A3

N3

A4

P8

A5

P2

A6

A7

A8

A9

A10/AP

T2

A11

A12/BC_N

T8

A13

L2

WE_N/A14

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C
LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

VSSQ4

E3

VSSQ5

A8

VSSQ6

VSSQ7

E8

VSSQ8

VSSQ9

H9

VSSQ10

F9

ZQ

MT40A512M16HA083EA_FBGA96

A0
A1

A2

A3
A4

A5

A6

A7

A8

A9

A10/AP

A11

A12/BC_N

A13

WE_N/A14
CAS_N/A15

RAS_N/A16

CK_C

CK_T

CKE

LDQS_C

LDQS_T

UDQS_C

UDQS_T

NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N

BA0

BA1

ACT_N

CS_N

ALERT_N

BG0

ODT

PAR

TEN

RESET_N

VSSQ1

VSSQ2
VSSQ3

VSSQ4

VSSQ5
VSSQ6
VSSQ7

VSSQ8

VSSQ9

VSSQ10

ZQ

VDD10

VDDQ1

VDDQ2

VDDQ3
VDDQ4

VDDQ5
VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VREFCA

3

@

DDRA_DQ18

G2

DDRA_DQ19

DQ0

F7

DDRA_DQ16

DQ1

H3

DDRA_DQ21

DQ2

H7

DDRA_DQ22

DQ3

H2

DDRA_DQ17

DQ4

H8

DDRA_DQ23

DQ5

J3

DDRA_DQ20

DQ6

J7

DDRA_DQ30

DQ7

A3

DDRA_DQ28

DQ8

B8

DDRA_DQ26

DQ9

C3

DDRA_DQ25

DQ10

C7

DDRA_DQ31

DQ11

C2

DDRA_DQ29

DQ12

C8

DDRA_DQ27

DQ13

D3

DDRA_DQ24

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

L9

VDD9

T9

VDD10

A1

VDDQ1

C1

VDDQ2

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

VDDQ10

B1

VPP1

R9

VPP2

VREFCA

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

@

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6
DQ7

DQ8

DQ9

DQ10
DQ11

DQ12

DQ13

DQ14

DQ15

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

VPP1

VPP2

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7
VSS8

VSS9

NC

+VREF_CA_MD

M1

E1

K1

N1
T1

B2

G8
E9

K9

M9

T7

NC

G2

F7

H3

H7

H2

H8
J3
J7

A3

B8

C3

C7
C2

C8

D3

D7

D1

J1

L1

R1

B3

G7

B9

J9

L9
T9

A1

C1

G1

F2

J2

F8

J8

A9
D9

G9

B1

R9

M1

E1

K1

N1

T1

B2

G8

E9

K9

M9

T7

DDRA_DQ59

DDRA_DQ60

DDRA_DQ62

DDRA_DQ56

DDRA_DQ63

DDRA_DQ61

DDRA_DQ58
DDRA_DQ57

DDRA_DQ54
DDRA_DQ52

DDRA_DQ51

DDRA_DQ49

DDRA_DQ50

DDRA_DQ53
DDRA_DQ55
DDRA_DQ48

+1.2V

+VREF_CA_MD

1

1

2

2

0.1u_0201_10V6K

.047U_0201_6.3V6K

CD114

CD122

1

1

2

2

0.1u_0201_10V6K

.047U_0201_6.3V6K

CD153

CD116

DDR_SA_VREFCA5

+2.5V_DDR

1

1

2

2

1U_0402_6.3V6K

CD125

CD124

+2.5V_DDR

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD155

CD154

1U_0402_6.3V6K

0.022U_0201_6.3V6-K

24.9_0402_1%

CD111

RD48

0.1u_0201_10V6K

RD46

1

2

1

2

+2.5V_DDR

2

1

CD119

2

1

2

2.7_0402_1%

+1.2V

(1uF_0402_6.3V) *16
Place 4 near each DRAM

1

1

2

2

1U_0402_6.3V6K

CD@

CD126

CD127

+1.2V

(1OuF_0603_6.3V) *5
Place around the DRAMs

1

2

10U_0603_6.3V6M

CD142

1

2

10U_0603_6.3V6M

CD152

+0.6VS

1

1

2

2

1U_0402_6.3V6K

CD159

CD158

+1.2V

1

RD45

1.8K_0402_1%

2

1

RD47

1.8K_0402_1%

2

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD128

CD129

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD143

CD144

(1OuF_0603_6.3V) *3
Place around the DRAMs

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD156

CD147

(1uF_0402_6.3V) *8
Place 2 near each DRAM

1

1

1

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD160

CD162

CD161

+VREF_CA_MD

1

CD112

0.1u_0201_10V6K

2

1

2

1U_0402_6.3V6K

CD130

1

2

10U_0603_6.3V6M

CD145

1

2

1U_0402_6.3V6K

CD@

CD163

1

2

1U_0402_6.3V6K

CD@

CD131

1

2

CD@

CD146

1

2

1U_0402_6.3V6K

CD164

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD133

CD132

10U_0603_6.3V6M

(1OuF_0603_6.3V) *2
Place around the DRAMs

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD165

1

2

CD@

CD166

DDRA_DQ[0..63]

DDRA_DQS#[0..7]

DDRA_DQS[0..7]

DDRA_MA[0..13]

1

2

1U_0402_6.3V6K

CD134

1

2

10U_0603_6.3V6M

CD167

1

2

CD135

+1.2V

+2.5V_DDR

10U_0603_6.3V6M

1U_0402_6.3V6K

CD136

1

CD109
22P_0402_50V8-J

RF@

2

1

CD157
22P_0402_50V8-J

RF@

2

DDRA_CLK0#
DDRA_CLK0

DDRA_CS0#

DDRA_ODT0

DDRA_CKE0

DDRA_MA0

DDRA_MA1
DDRA_MA2
DDRA_MA3

DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7

DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11

DDRA_MA12

DDRA_MA13

DDRA_MA14_WE#
DDRA_MA15_CAS#

DDRA_MA16_RAS#

DDRA_BG0

DDRA_BS0#
DDRA_BS1#

DDRA_ACT#
DDRA_PAR

DDRA_ALERT#

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CD@

CD137

DDRA_DQ[0..63] 5

DDRA_DQS#[0..7] 5

DDRA_DQS[0..7] 5

DDRA_MA[0..13] 5

1

1 2

RD49 36_0402_1%

2

1

RD50 36_0402_1%

2

1

RD51 34.8_0402_1%

1

2

RD52 34.8_0402_1%

2

1

RD53 34.8_0402_1%

1

2

RD54 34.8_0402_1%

1

2

RD55 34.8_0402_1%

1 2

RD56 34.8_0402_1%

2

1

RD57 34.8_0402_1%

2

1

RD58 34.8_0402_1%

1

2

RD59 34.8_0402_1%

1

2

RD60 34.8_0402_1%

2

1

RD61 34.8_0402_1%

1

2

RD62 34.8_0402_1%

1

2

RD63 34.8_0402_1%

2

1

RD64 34.8_0402_1%

1

2

RD67 34.8_0402_1%

2

1

RD70 34.8_0402_1%

2

1

RD71 34.8_0402_1%

1

2

RD72 34.8_0402_1%

1

2

RD73 34.8_0402_1%

1

2

RD74 34.8_0402_1%

2

1

RD75 34.8_0402_1%

2

1

RD76 34.8_0402_1%

2

1

RD77 34.8_0402_1%

2

1

RD78 34.8_0402_1%

1

2

RD79 34.8_0402_1%

2

1

RD86 49.9_0402_1%

1

1

1

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CD@

CD140

CD139

CD110
22P_0402_50V8-J

RF@

CD148
22P_0402_50V8-J

RF@

+0.6VS

1

CD168
22P_0402_50V8-J

RF@

2

CD141

CD138

1

2

1

2

+0.6VS

+1.2V

1

2

1U_0402_6.3V6K

1

CD169
22P_0402_50V8-J

RF@

2

C

B

A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE US ED BY OR DI SCLOS ED TO A NY THIRD PARTY WITHOUT P RIOR W RITTE N CONSE NT OF LC F UTURE CE NTER.

MAY BE US ED BY OR DI SCLOS ED TO A NY THIRD PARTY WITHOUT P RIOR W RITTE N CONSE NT OF LC F UTURE CE NTER.

5

4

3

MAY BE US ED BY OR DI SCLOS ED TO A NY THIRD PARTY WITHOUT P RIOR W RITTE N CONSE NT OF LC F UTURE CE NTER.

2

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2016/08/20

2016/08/20

2016/08/20

Title

DDR4 Memory Down

DDR4 Memory Down

DDR4 Memory Down

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet of

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

1

CG413

CG413

CG413

17 60

of

17 60

of

17 60

1.0

1.0

1.0

5

DDR4 SO-DIMM

+1.2V +1.2V +1.2V +1.2V

+1.2V +1.2V +1.2V

DDRB_DQ12

DDRB_DQ13

DDRB_DQS#1

DDRB_DQS1

D D

+1.2V

1

RD92

240_0402_1%

2

C

DDRB_CKE06

DDRB_BG16
DDRB_BG06

DDRB_MA126
DDRB_MA96

DDRB_MA86

DDRB_MA66

B

DDR_SB_VREFCA5

A

DDRB_DQ10

DDRB_DQ14

DDRB_DQ0

DDRB_DQ6

DDRB_DQ7

DDRB_DQ3

DDRB_DQ18

DDRB_DQ16

DDRB_DQS#2
DDRB_DQS2

DDRB_DQ22

DDRB_DQ23

DDRB_DQ27

DDRB_DQ28

DDRB_DQ25

DDRB_DQ30

12

RD93
240_0402_1%

DDRB_DQS#8

DDRB_DQS8

DDRB_CKE0

DDRB_BG1
DDRB_BG0

DDRB_MA12
DDRB_MA9

DDRB_MA8
DDRB_MA6

1

CD13

0.022U_0201_6.3V6-K

2

1

RD6

24.9_0402_1%

2

+3VS +3VS

1

RD7
0_0402_5%

@

2

1

RD10
0_0402_5%

@

2

0.1u_0201_10V6K

DDRB_SA0 DDRB_SA1 DDRB_SA2

RD4

CD117

1

2_0402_5%

1

3
5

7

9

11

13

15

17

19

21

23

25

27
29
31

33

35

37
39

41

43

45

47

49

51
53

55

57

59

61

63

65

67
69

71

73
75

77

79

81

83

85

87

89
91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

JDDR1A

VSS_1

DQ5

VSS_3

DQ1

VSS_5

DM0_n/DBIO_n/NC

DQS0_C

DQS0_t

VSS_8

DQ7

VSS_10

DQ3

VSS_12

DQ13

VSS_14

DQ9

VSS_16

DM1_n/DBl1_n/NC

VSS_17

DQ15
VSS_19

DQ10
VSS_21

DQ21

VSS_23

DQ17

VSS_25

DM2_n/DBl2_n/NC

DQS2_c

DQS2_t

VSS_28

DQ23

VSS_30

DQ19

VSS_32

DQ29
VSS_34

DQ25

VSS_36
DM3_n/DBl3_n/NC

VSS_37

DQ30

VSS_39

DQ26

VSS_41

CB5/NC
VSS_43

CB1/NC

VSS_45

DM8_n/DBI8_n/NC

DQS8_c

DQS8_t

VSS_48

CB2/NC

VSS_50

CB3/NC

VSS_52

CKE0

VDD_1
BG1

BG0

VDD_3

A12

A9

VDD_5

A8

A6

VDD_7

ARGOS_D4AS0-26001-1P60

ME@

+1.2V

1

1

2

RD3
1K_0402_1%

2

2

1

RD5
1K_0402_1%

2

1

RD8
0_0402_5%

@

2

1

RD11
0_0402_5%

@

2

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15

DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24

VSS_35

DQS3_c

DQS3_t

VSS_38

DQ31

VSS_40

DQ27

VSS_42

CB4/NC

VSS_44

CB0/NC

VSS_46

VSS_47

CB6/NC

VSS_49

CB7/NC

VSS_51

RESET_n

CKE1

VDD_2

ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

DQ4

DQ0

DQ6

DQ2

DQ8

A11

A7

A5

A4

SPD Address = 2H

5

4

2

4

6

8

10

12

14
16

18

20

22

24

26
28

30

32

34

36
38

40

42

44

46
48

50

52

54

56

58

60
62

64

66

68
70

72

74

76

78

80

82

84
86

88

90

92

94
96

98

100

102

104

106

108

110

112

114

116

118

120
122

124

126

128

130

Note:
VREF trace width:20 mils at least

Spacing:20mils to other signal/planes
Place near DIMM scoket

+VREF_CA_DIMM

1

CD14

0.1u_0201_10V6K

2

+3VS

1

RD9
0_0402_5%

@

2

1

RD12
0_0402_5%

@

2

4

DDRB_DQ9

DDRB_DQ8

DDRB_DQ11

DDRB_DQ15

DDRB_DQ5

DDRB_DQ4

DDRB_DQS#0
DDRB_DQS0

DDRB_DQ1

DDRB_DQ2

DDRB_DQ20

DDRB_DQ21

DDRB_DQ17

DDRB_DQ19

DDRB_DQ24

DDRB_DQ29

DDRB_DQS#3

DDRB_DQS3

DDRB_DQ26

DDRB_DQ31

CPU_DRAMRST#

DDRB_CKE1

DDRB_ACT#

DDRB_ALERT#

DDRB_MA11
DDRB_MA7

DDRB_MA5
DDRB_MA4

DDRB_DQ[0..63]

DDRB_DQS#[0..7]

DDRB_DQS[0..7]

DDRB_CKE1 6

DDRB_ACT# 6

DDRB_ALERT# 6

DDRB_MA11 6
DDRB_MA7 6

DDRB_MA5 6

DDRB_MA4 6

3

DDRB_DQ[0..63] 6

DDRB_DQS#[0..7] 6

DDRB_DQS[0..7] 6

DDRB_MA36
DDRB_MA16

DDRB_CLK06
DDRB_CLK0#6

DDRB_PAR6

DDRB_BS1#6

DDRB_CS0#6

DDRB_MA14_WE#6

DDRB_ODT06
DDRB_CS1#6

DDRB_ODT16

CPU_DRAMRST# 6,17

1

CD3

0.1u_0201_10V6K

@

2

SMB_CLK_S37,40 SMB_DATA_S3 7,40

2

1

RD1

10U_0603_6.3V6M

4.7U_0402_6.3V6M

3

0_0603_5%

2.2U_0402_6.3V6M

1 2

RD2

0_0603_5%

1

2

10U_0603_6.3V6M

CD21

1

EMC_NS@

2

0.1u_0201_10V6K

CD17

@

1

CD4

2

@

Layout Note:
Place near DIMM

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD23

CD22

CD@

RF@

1

EMC_NS@

2

0.1u_0201_10V6K

CD18

CD36

Near JDDRL1

2015/08/20

2015/08/20

2015/08/20

1

2

1

2

33P_0402_50V8J

CD5

0.1u_0201_10V6K

1

2

CD24

+3VS

+2.5V_DDR

+1.2V

1

1

2

2

10U_0603_6.3V6M

CD20

CD19

CD@

+1.2V

1

1

EMC_NS@

EMC_NS@

2

2

4.7U_0402_6.3V6M

CD15

CD16

For EMC

Security Classifi cation

Security Classifi cation

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERT Y O F LC FU TUR E CENT ER. AN D CON TAINS C ONFI DENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERT Y O F LC FU TUR E CENT ER. AN D CON TAINS C ONFI DENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PRO PERT Y O F LC FU TUR E CENT ER. AN D CON TAINS C ONFI DENTIAL

AND TRAD E SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D

AND TRAD E SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D

AND TRAD E SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIO N OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+1.2V

DDRB_MA3
DDRB_MA1

DDRB_CLK0

DDRB_CLK0#

DDRB_PAR

DDRB_BS1#

DDRB_CS0#
DDRB_MA14_WE#

DDRB_ODT0
DDRB_CS1#

DDRB_ODT1

DDRB_DQ32

DDRB_DQ33

DDRB_DQS#4
DDRB_DQS4

DDRB_DQ39

DDRB_DQ38

DDRB_DQ41

DDRB_DQ40

DDRB_DQ47

DDRB_DQ43

DDRB_DQ53

DDRB_DQ48

DDRB_DQS#6
DDRB_DQS6

DDRB_DQ54

DDRB_DQ50

DDRB_DQ60

DDRB_DQ57

DDRB_DQ59

DDRB_DQ58

SMB_CLK_S3

+VDD_SPD

+VPP

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD25

RF@

1

2

33P_0402_50V8J

CD37

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

JDDR1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AS0-26001-1P60

ME@

@

1

1

1

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD118

CD6

1

2

10U_0603_6.3V6M

CD26

CD7

1

1

2

2

1U_0402_6.3V6K

CD27

CD28

2016/08/20

2016/08/20

2016/08/20

2

DM4_n/DBl4_n/NC

DM6_n/DBl6_n/NC

10U_0603_6.3V6M

1U_0402_6.3V6K

CD29

CD@

132

A2

134

EVENT_n

136

VDD_10

138

CK1_t

140

CK1_c

142

VDD_12

144

A0

146

A10/AP

148

VDD_14

150

BA0

152

RAS_n/A16

154

VDD_16

156

CAS_n/A15

158

A13

160

VDD_18

162

C0/CS2_n/NC

164

VREFCA

166

SA2

168

VSS_54

170

DQ36

172

VSS_56

174

DQ32

176

VSS_58

178

180

VSS_59

182

DQ39

184

VSS_61

186

DQ35

188

VSS_63

190

DQ45

192

VSS_65

194

DQ41

196

VSS_67

198

DQS5_c

200

DQS5_t

202

VSS_70

204

DQ47

206

VSS_72

208

DQ43

210

VSS_74

212

DQ53

214

VSS_76

216

DQ48

218

VSS_78

220

222

VSS_79

224

DQ54

226

VSS_81

228

DQ50

230

VSS_83

232

DQ60

234

VSS_85

236

DQ57

238

VSS_87

240

DQS7_c

242

DQS7_t

244

VSS_90

246

DQ63

248

VSS_92

250

DQ59

252

VSS_94

254

SDA

256

SA0

258

Vtt

260

SA1

262

GND_2

+2.5V_DDR+0.6VS

1

2

10U_0603_6.3V6M

CD8

CD@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD30

Title

Title

Title

Size

Size

Size

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

DDRB_MA2
DDRB_EVENT#

DDRB_CLK1
DDRB_CLK1#

DDRB_MA0

DDRB_MA10

DDRB_BS0#
DDRB_MA16_RAS#

DDRB_MA15_CAS#
DDRB_MA13

+VREF_CA_DIMM
DDRB_SA2

DDRB_DQ36

DDRB_DQ37

DDRB_DQ34

DDRB_DQ35

DDRB_DQ45

DDRB_DQ44

DDRB_DQS#5
DDRB_DQS5

DDRB_DQ46

DDRB_DQ42

DDRB_DQ52

DDRB_DQ49

DDRB_DQ55

DDRB_DQ51

DDRB_DQ56

DDRB_DQ61

DDRB_DQS#7
DDRB_DQS7

DDRB_DQ62

DDRB_DQ63

SMB_DATA_S3
DDRB_SA0

DDRB_SA1

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD9

CD10

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD31

CD32

DDR4 SO-DIMM

DDR4 SO-DIMM

DDR4 SO-DIMM

Document Number Rev

Document Number Rev

Document Number Rev

Thursday, July 14, 2016

Thursday, July 14, 2016

Thursday, July 14, 2016

1

2

CD11

CD@

1

2

CD33

CD@

+0.6VS

1U_0402_6.3V6K

CD12

1U_0402_6.3V6K

CD34

CG413

CG413

CG413

1

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

RD91

240_0402_1%

@

DDRB_MA2 6

DDRB_CLK1 6

DDRB_CLK1# 6

DDRB_MA0 6

DDRB_MA10 6

DDRB_BS0# 6
DDRB_MA16_RAS# 6

DDRB_MA15_CAS# 6

DDRB_MA13 6

@

1

1

2

2

0.1u_0201_10V6K

CD1

CD2

@

1

+

2

220U_6.3V_M

CD35

of

18 60

18 60

18 60

+1.2V

2.2U_0402_6.3V6M

1

2

1.0

1.0

1.0

C

B

A