Lenovo Ideapad 330-15AR Schematic

A

Vinafix.com

1 1

B

C

D

E

LCFC

NM_B681 M/B Schematics Document

2 2

AMD FP5 Raven Ridge SoC with DDRIV

AMD R17M-P1-50/R18M-M2-60

2017-09-6

REV:1.0

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

A

B

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USE D BYOR DISCLOSED TO ANYT HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAYBE USE D BYOR DISCLOSED TO ANYT HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAYBE USE D BYOR DISCLOSED TO ANYT HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

2013/08/15

2013/08/15

2013/08/15

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

D

Titl e

Titl e

Titl e

Cover Page

Cover Page

Cover Page

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

E

1 52

1 52

1 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

D D

C C

B B

PRT06

0_0402_5%

SD02800008J

PRT07

0_0402_5%

SD02800008J

PRT08

0_0402_5%

SD02800008J

PR609

NEC_UMA@

NEC_UMA@

NEC_UMA@

R18@

PRT06

540_0402NEW_30%

SL20000220J

PRT07

540_0402NEW_30%

SL20000220J

PRT08

540_0402NEW_30%

SL20000220J

NEC_R17@

NEC_R17@

NEC_R17@

PRT06

0_0402_5%

SD02800008J

PRT07

540_0402NEW_30%

SL20000220J

PRT08

540_0402NEW_30%

SL20000220J

NEC_R18@

NEC_R18@

NEC_R18@

R18 LL=1mohm,PR609=18.7K
R17 LL=0.6mohm,PR609=31.6K

18.7K_0402_1%

SD03418728J

A A

Title

Title

5

4

Title

Size

Size

Size

Dat e: Sheet o f

Dat e: Sheet o f

3

Dat e: Sheet o f

<Title>

<Title>

<Title>

Document Number R ev

Document Number R ev

Document Number R ev

<Doc> 1.0

A

<Doc> 1.0

A

<Doc> 1.0

A

1 1Friday, March 23, 2018

1 1Friday, March 23, 2018

2

1 1Friday, March 23, 2018

1

A

Vinafix.com

B

C

D

E

AMD: R17M-P1-50
R18M-M2-60
Package: S4a

1 1

VRAM 256*16

PCI-Express

8x Gen3

PEG 0~7

GDDR5*2 2G

HDMI x4 Lane Port1

Channel A

1.2V DDR4 2400MT/s

Memory BUS (DDR4)
Channel B

1.2V DDR4 2400MT/s

Memory BUS (DDR4)

DDR4-SO-DIMM X1

UP TO 8G x 1

DDR4 DRAM DOWN

4pcs x16

HDMI Conn.

eDP Conn

eDP x2 Lane port0

USB 3.0 1x
USB 2.0 1x

Int. Camera

USB 2.0 Port1

Int. DMIC Conn.

AMD FP5 APU

USB 3.0 1x
USB 2.0 1x

2 2

SATA HDD

SATA Port0

SATA Gen3

Raven Ridge TDP 15W

USB 3.0 1x

SATA ODD

NGFF Card
WLAN&BT
Key E

USB 2.0 Port

fingerprint

USB 2.0 Port

reserve

3 3

Touch Screen

USB 2.0 Port

USB 2.0 1x
USB 2.0 1x

USB 2.0 1x

USB HUB

GL850G

SATA Port1

PCIe Port1

USB 2.0 Port5

SATA Gen1

PCIe 1x

USB2.0 1x

USB2.0(480M) 1x

USB2.0 1x

HD Audio

BGA-1140P

35mm*25mm

USB 2.0 1x

PCIe 1x

SPI BUS

USB Left

USB 2.0 Port4
USB 3.0 Port4

USB Left

USB 2.0 Port2
USB 3.0 Port2

USB Repeater

Parade PS8713

USB 3.0 Port3
USB 2.0 Port3

LAN Realtek

RTL8111GUL

PCIe Port2

SPI ROM

8MB

USB 3.0 1x

CC logic&Mux

Realtek RTS5449

RJ45 Conn.

USB 3.0 2x

Type C Conn

USB 2.0 Port0

Codec&Card reader

Realtek_RTS5199

SPK Conn.

SD/MMC Conn.

LPC

TPM

reserve

EC

HP&Mic Combo Conn.

IT8586E-FX_LQFP128

Sub-board for 15&17

4 4

A

B

Int.KBDTouch Pad

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

Thermal Sensor
NCT7718W

C

reserve

2013/08/15

2013/08/15

2013/08/15

Thermistor

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2013/08/15

2013/08/15

2013/08/15

ODD BOARD

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 23, 2018

330ARR

330ARR

330ARR

E

2 52

2 52

2 52

1.0

1.0

1.0

A

Vinafix.com

Voltage Rails

1 1

2 2

plane

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

( O --> Means ON , X --> Means OFF )

B+
(+20VSB )

+3VL

+5VLP

O

O

O

O

X

+5VALW

+3VALW
(+3VALW _APU)

+1.8VAL W

+0.9VAL W

+1.2V

O

O

O

X

O

X X

X

X X X

+5VS

+3VS

+1.8VS

+0.9VSpower

+0.6VS

+2.5VS

+VDDC_V DD

+VDDCR_ SOC

+VDDC

+VDDCI

+3VGS

+1.8VGS

+1.35VG S

B

SOURCE

+3VALW

SIGNAL

SLP_S3# SLP _S5# +VALW +V +VS Clock

HIGH HIGH

LOW

LOW LOW

Device

Touch Pad

+3VS

Address

?

?

STATE

S0 (Full ON)

S1 (Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

OO

I2C Control Table

X

TP_I2C0 _SCL APU

TP_I2C0 _SDA

X

APU I2C address

Device

Elan：S A469 D- 22 HA 69x104x1. 0

Synaptics ：T M- P3255-00 8 69x104x 1. 0

HIGHHIGH

HIGHLOW

LOW

C

ON

ONONON ON

ON

ON

ON

ON

OFF

ON

OFF

Port List

HSIO Port

GPP

GFX

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

D

BOM Structure Table

E

BTO ItemBOM Structure

@

0

WLAN

1

LAN

2

N/A

3

N/A

4

N/A

5

N/A

6

HDD

7

ODD

0
1
2
3

GPU

4

Device

ME@
EMC @
EMC_NS@
RF@
RF_PXNS@
UMA @
PX@
R17M-P1@
R18M-M2@
TPM @
KBL @
HDT @
REDRV@
USB_HUB@

Not stuff

Connect or

EMC Part

EMC reserve Part

RF Part

RF GPU reserve part

UMA SKU ID part

Discrete GPU SKU part

R17M-P1-50 SKU part

R18M-M2-60 SKU part

TPM part

Keyboard backlight part

HDT Debug part

Redriver part

USB HUB part

5
6
7
0

SMBUS Control Table

SOURCE

3 3

EC_SMB_ CK1

EC_SMB_ DA1

EC_SMB_ CK2

EC_SMB_ DA2

EC_SMB_ CK3

EC_SMB_ DA3

APU_SCL K0
APU_SDA TA0

IT8586

+3VL

IT8586

+3VL

IT8586

+3VS

APU

+3VS

EC SM Bus1 address

Device

4 4

Battery

Charger

Address

?

0001 0010 b

GPU BATT SODIMM WLAN Thermal

X

X

X X

X

X

X

+3VS_VG A

V

X

XV

V VX X X X X

EC SM Bus2 address

Device

PMIC

Thermal Sensor

Address

0X34

1001_10 0xb(reserv e)

Sensor

APUIT8586

Charger

X X V

X

V

+3VS

X

V X X

X

EC SM Bus3 address

Device

GPU

APU SB-TSI

PMIC

X

VX

X

Address

0x41(defaul t)

releate to F3x1E4[SbiAddr] or
Address Select Pins setting

APU SM Bus address

Device

DDR4 SO-DIMM

WLAN

Address

?

RSVD

A

B

USB3.0

USB2.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

N/A

1

Type C

2

LEFT USB (3.0) lower

3

LEFT USB (3.0) upper

4

N/A

0

Card Reader

1

Type C

2

LEFT USB (3.0) lower

3

LEFT USB (3.0) upper

4

USB HUB(Camera,FP,Touch)

5

BT

LC Future Center Secret Data

LC Future Center Secret Data

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

VRAM

Deciphered Date

Deciphered Date

Deciphered Date

D

S2G @
M2G @
H2G @
HDMI@

2013/08/15

2013/08/15

2013/08/15

SAMSUNG 2G

MICRON 2G

HYNIX 2G

HDMI Logo

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330ARR

330ARR

330ARR

E

3 52

3 52

3 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

UC2B

PCIE_CRX_GTX_P017

D D

GPU

C C

WLAN

LAN

B B

HDD HDD

PCIE_CRX_GTX_N017

PCIE_CRX_GTX_P117
PCIE_CRX_GTX_N117

PCIE_CRX_GTX_P217
PCIE_CRX_GTX_N217

PCIE_CRX_GTX_P317
PCIE_CRX_GTX_N317

PCIE_CRX_GTX_P417
PCIE_CRX_GTX_N417

PCIE_CRX_GTX_P517
PCIE_CRX_GTX_N517

PCIE_CRX_GTX_P617
PCIE_CRX_GTX_N617

PCIE_CRX_GTX_P717
PCIE_CRX_GTX_N717

PCIE_PRX_DTX_P135
PCIE_PRX_DTX_N135

PCIE_PRX_DTX_P232
PCIE_PRX_DTX_N232

SATA_PRX_DTX_P038

SATA_PRX_DTX_N138

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2

SATA_PRX_DTX_P0
SATA_PRX_DTX_N0

SATA_PRX_DTX_P1
SATA_PRX_DTX_N1

P8

P_GFX_RXP0

P9

P_GFX_RXN0

N6

P_GFX_RXP1

N7

P_GFX_RXN1

M8

P_GFX_RXP2

M9

P_GFX_RXN2

L6

P_GFX_RXP3

L7

P_GFX_RXN3

K11

P_GFX_RXP4

J11

P_GFX_RXN4

H6

P_GFX_RXP5

H7

P_GFX_RXN5

G6

P_GFX_RXP6

F7

P_GFX_RXN6

G8

P_GFX_RXP7

F8

P_GFX_RXN7

N10

P_GPP_RXP0

N9

P_GPP_RXN0

L10

P_GPP_RXP1

L9

P_GPP_RXN1

L12

P_GPP_RXP2

M11

P_GPP_RXN2

P12

P_GPP_RXP3

P11

P_GPP_RXN3

V6

P_GPP_RXP4

V7

P_GPP_RXN4

T8

P_GPP_RXP5

T9

P_GPP_RXN5

R6

P_GPP_RXP6/SATA_RXP0

R7

P_GPP_RXN6/SATA_RXN0

R9

P_GPP_RXP7/SATA_RXP1

R10

P_GPP_RXN7/SATA_RXN1

@

PCIE

FP5 REV 0.90
PART 2 OF 13

P_GFX_TXP0
P_GFX_TXN0

P_GFX_TXP1
P_GFX_TXN1

P_GFX_TXP2
P_GFX_TXN2

P_GFX_TXP3
P_GFX_TXN3

P_GFX_TXP4
P_GFX_TXN4

P_GFX_TXP5
P_GFX_TXN5

P_GFX_TXP6
P_GFX_TXN6

P_GFX_TXP7
P_GFX_TXN7

P_GPP_TXP0
P_GPP_TXN0

P_GPP_TXP1
P_GPP_TXN1

P_GPP_TXP2
P_GPP_TXN2

P_GPP_TXP3
P_GPP_TXN3

P_GPP_TXP4
P_GPP_TXN4

P_GPP_TXP5
P_GPP_TXN5

P_GPP_TXP6/SATA_TXP0
P_GPP_TXN6/SATA_TXN0

P_GPP_TXP7/SATA_TXP1
P_GPP_TXN7/SATA_TXN1

AMD-RAVEN-FP5_BGA1140

PCIE_CTX_GRX_P0

N1

PCIE_CTX_GRX_N0

N3

PCIE_CTX_GRX_P1

M2

PCIE_CTX_GRX_N1

M4

PCIE_CTX_GRX_P2

L2

PCIE_CTX_GRX_N2

L4

PCIE_CTX_GRX_P3

L1

PCIE_CTX_GRX_N3

L3

PCIE_CTX_GRX_P4

K2

PCIE_CTX_GRX_N4

K4

PCIE_CTX_GRX_P5

J2

PCIE_CTX_GRX_N5

J4

PCIE_CTX_GRX_P6

H1

PCIE_CTX_GRX_N6

H3

PCIE_CTX_GRX_P7

H2

PCIE_CTX_GRX_N7

H4

PCIE_PTX_DRX_P1

N2

PCIE_PTX_DRX_N1

P3

PCIE_PTX_DRX_P2

P4

PCIE_PTX_DRX_N2

P2

R3
R1

T4
T2

W2
W4

W3
V2

SATA_PTX_DRX_P0

V1

SATA_PTX_DRX_N0

V3

SATA_PTX_DRX_P1

U2

SATA_PTX_DRX_N1

U4

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

SATA_PTX_DRX_P0 38

SATA_PTX_DRX_N0 38SATA_PRX_DTX_N038

SATA_PTX_DRX_P1 38SATA_PRX_D TX_P138
SATA_PTX_DRX_N1 38

CC50.22U_0201_6.3V6-K PX@
CC60.22U_0201_6.3V6-K PX@

CC70.22U_0201_6.3V6-K PX@
CC80.22U_0201_6.3V6-K PX@

CC90.22U_0201_6.3V6-K PX@
CC100.22U_0201_6.3V6-K PX@

CC110.22U_0201_6.3V6-K PX@
CC120.22U_0201_6.3V6-K PX@

CC180.22U_0201_6.3V6-K R5R7@
CC300.22U_0201_6.3V6-K R5R7@

CC310.22U_0201_6.3V6-K R5R7@
CC330.22U_0201_6.3V6-K R5R7@

CC320.22U_0201_6.3V6-K R5R7@
CC340.22U_0201_6.3V6-K R5R7@

CC350.22U_0201_6.3V6-K R5R7@
CC360.22U_0201_6.3V6-K R5R7@

CC10.1U_0201_6.3V6-K
CC20.1U_0201_6.3V6-K

CC30.1U_0201_6.3V6-K
CC40.1U_0201_6.3V6-K

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2

PCIE_CTX_C_GRX_P0 17
PCIE_CTX_C_GRX_N0 17

PCIE_CTX_C_GRX_P1 17
PCIE_CTX_C_GRX_N1 17

PCIE_CTX_C_GRX_P2 17
PCIE_CTX_C_GRX_N2 17

PCIE_CTX_C_GRX_P3 17
PCIE_CTX_C_GRX_N3 17

PCIE_CTX_C_GRX_P4 17
PCIE_CTX_C_GRX_N4 17

PCIE_CTX_C_GRX_P5 17
PCIE_CTX_C_GRX_N5 17

PCIE_CTX_C_GRX_P6 17
PCIE_CTX_C_GRX_N6 17

PCIE_CTX_C_GRX_P7 17
PCIE_CTX_C_GRX_N7 17

PCIE_PTX_C_DRX_P1 35
PCIE_PTX_C_DRX_N1 35

PCIE_PTX_C_DRX_P2 32
PCIE_PTX_C_DRX_N2 32

GPU

WLAN

LAN

ODDODD

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/15

2013/08/15

2013/08/15

2

Titl e

Titl e

Titl e

FP5 (PCIE SATA I/F)

FP5 (PCIE SATA I/F)

FP5 (PCIE SATA I/F)

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

4 5 2

4 5 2

4 5 2

1.0

1.0

1.0

5

Vinafix.com

UC2A

D D

C C

B B

MEM_MA_RST#14

DDRA_MA[13..0]14

DDRA_MA14_WE#14
DDRA_MA15_CAS#14
DDRA_MA16_RAS#14

DDRA_BA014
DDRA_BA114

DDRA_BG014
DDRA_BG114

DDRA_ACT#14

DDRA_DM[7..0]14

DDRA_CLK014
DDRA_CLK0#14
DDRA_CLK114
DDRA_CLK1#14

DDRA_CS0#14
DDRA_CS1#14

DDRA_CKE014
DDRA_CKE114

DDRA_ODT014
DDRA_ODT114

DDRA_ALERT#14

MEM_MA_EVENT#14

1 2

RC283 0_0402_5%@

+1.2V

1 2

RC284 1K_0402_5%

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12

DDRA_MA13
DDRA_MA14_WE#
DDRA_MA15_CAS#
DDRA_MA16_RAS#

DDRA_BA0

DDRA_BA1

DDRA_BG0

DDRA_BG1

DDRA_ACT#

DDRA_DM0

DDRA_DM1

DDRA_DM2

DDRA_DM3

DDRA_DM4

DDRA_DM5

DDRA_DM6

DDRA_DM7

DDRA_DQS0

DDRA_DQS#0

DDRA_DQS1

DDRA_DQS#1

DDRA_DQS2

DDRA_DQS#2

DDRA_DQS3

DDRA_DQS#3

DDRA_DQS4

DDRA_DQS#4

DDRA_DQS5

DDRA_DQS#5

DDRA_DQS6

DDRA_DQS#6

DDRA_DQS7

DDRA_DQS#7

DDRA_CLK0

DDRA_CLK0#

DDRA_CLK1

DDRA_CLK1#

DDRA_CS0#

DDRA_CS1#

DDRA_CKE0

DDRA_CKE1

DDRA_ODT0

DDRA_ODT1

DDRA_ALERT#

MEM_MA_EVENT#

MEM_MA_RST#_R

MEM_MA_EVENT#

AF25

MA_ADD0/MAB_CS0

AE23

MA_ADD1/RSVD

AD27

MA_ADD2/RSVD

AE21

MA_ADD3/RSVD

AC24

MA_ADD4/RSVD

AC26

MA_ADD5/RSVD

AD21

MA_ADD6/RSVD

AC27

MA_ADD7/MAA_CA3

AD22

MA_ADD8/MAA_CA4

AC21

MA_ADD9/MAA_CKE1

AF22

MA_ADD10/MAB_CKE0

AA24

MA_ADD11/MAA_CA5

AC23

MA_ADD12/MAA_CA2

AJ25

MA_ADD13_BANK2/RSVD

AG27

MA_WE_L_ADD14/MAB_CA2

AG23

MA_CAS_L_ADD15/MAB_CA4

AG26

MA_RAS_L_ADD16/MAB_CA3

AF21

MA_BANK0/MAB_CS1

AF27

MA_BANK1/MAB_CA0

AA21

MA_BG0/MAA_CS1

AA27

MA_BG1/MAA_CKE0

AA22

MA_ACT_L/MAA_CS0

F21

MA_DM0/MAA_DM1

G27

MA_DM1/MAA_DM0

N24

MA_DM2/MAA_DM2

N23

MA_DM3/MAA_DM3

AL24

MA_DM4/MAB_DM2

AN27

MA_DM5/MAB_DM3

AW25

MA_DM6/MAB_DM1

AT21

MA_DM7/MAB_DM0

T27

RSVD_36

F22

MA_DQS_H0/MAA_DQS_H1

G22

MA_DQS_L0/MAA_DQS_L1

H27

MA_DQS_H1/MAA_DQS_H0

H26

MA_DQS_L1/MAA_DQS_L0

N27

MA_DQS_H2/MAA_DQS_H2

N26

MA_DQS_L2/MAA_DQS_L2

R21

MA_DQS_H3/MAA_DQS_H3

P21

MA_DQS_L3/MAA_DQS_L3

AM26

MA_DQS_H4/MAB_DQS_H2

AM27

MA_DQS_L4/MAB_DQS_L2

AN24

MA_DQS_H5/MAB_DQS_H3

AN25

MA_DQS_L5/MAB_DQS_L3

AU23

MA_DQS_H6/MAB_DQS_H1

AT23

MA_DQS_L6/MAB_DQS_L1

AV20

MA_DQS_H7/MAB_DQS_H0

AW20

MA_DQS_L7/MAB_DQS_L0

V24

RSVD_41

V23

RSVD_40

AD25

MA_CLK_H0/MAA_CKT

AD24

MA_CLK_L0/MAA_CKC

AE26

MA_CLK_H1/MAB_CKT

AE27

MA_CLK_L1/MAB_CKC

AG21

MA_CS_L0/MAB_CKE1

AJ27

MA_CS_L1/RSVD

Y23

MA_CKE0/MAA_CA0

Y26

MA_CKE1/MAA_CA1

AG24

MA_ODT0/MAB_CA5

AJ22

MA_ODT1/RSVD

AA25

MA_ALERT_L/MA_TEST

AE24

MA_EVENT_L

Y24

MA_RESET_L

@

SO-DIMM

FP5 REV 0.90
PART 1 OF 13

MEMORY A

MA_DATA0/MAA_DATA8

MA_DATA1/MAA_DATA9
MA_DATA2/MAA_DATA13
MA_DATA3/MAA_DATA12
MA_DATA4/MAA_DATA11
MA_DATA5/MAA_DATA10
MA_DATA6/MAA_DATA15
MA_DATA7/MAA_DATA14

MA_DATA8/MAA_DATA0

MA_DATA9/MAA_DATA1
MA_DATA10/MAA_DATA5
MA_DATA11/MAA_DATA4
MA_DATA12/MAA_DATA7
MA_DATA13/MAA_DATA6
MA_DATA14/MAA_DATA2
MA_DATA15/MAA_DATA3

MA_DATA16/MAA_DATA17
MA_DATA17/MAA_DATA16
MA_DATA18/MAA_DATA23
MA_DATA19/MAA_DATA20
MA_DATA20/MAA_DATA19
MA_DATA21/MAA_DATA18
MA_DATA22/MAA_DATA21
MA_DATA23/MAA_DATA22

MA_DATA24/MAA_DATA30
MA_DATA25/MAA_DATA31
MA_DATA26/MAA_DATA26
MA_DATA27/MAA_DATA27
MA_DATA28/MAA_DATA28
MA_DATA29/MAA_DATA29
MA_DATA30/MAA_DATA24
MA_DATA31/MAA_DATA25

MA_DATA32/MAB_DATA16
MA_DATA33/MAB_DATA17
MA_DATA34/MAB_DATA22
MA_DATA35/MAB_DATA20
MA_DATA36/MAB_DATA19
MA_DATA37/MAB_DATA18
MA_DATA38/MAB_DATA23
MA_DATA39/MAB_DATA21

MA_DATA40/MAB_DATA30
MA_DATA41/MAB_DATA31
MA_DATA42/MAB_DATA26
MA_DATA43/MAB_DATA27
MA_DATA44/MAB_DATA28
MA_DATA45/MAB_DATA29
MA_DATA46/MAB_DATA24
MA_DATA47/MAB_DATA25

MA_DATA48/MAB_DATA11
MA_DATA49/MAB_DATA10
MA_DATA50/MAB_DATA15
MA_DATA51/MAB_DATA14
MA_DATA52/MAB_DATA12
MA_DATA53/MAB_DATA13

MA_DATA54/MAB_DATA9
MA_DATA55/MAB_DATA8

MA_DATA56/MAB_DATA5
MA_DATA57/MAB_DATA6
MA_DATA58/MAB_DATA2
MA_DATA59/MAB_DATA3
MA_DATA60/MAB_DATA7
MA_DATA61/MAB_DATA4
MA_DATA62/MAB_DATA1
MA_DATA63/MAB_DATA0

MA_PAROUT/MAB_CA1

AMD-RAVEN-FP5_BGA1140

RSVD_34
RSVD_35
RSVD_51
RSVD_52
RSVD_27
RSVD_28
RSVD_43
RSVD_42

4

DDRA_DQS[0..7]

DDRA_DQS#[0..7]

DDRA_DQ[63..0] 14

APU

DA32

DA33

DA34

DA35

DA36

DA37

DA38

DA39

DA40

DA41

DA42

DA43

DA44

DA45

DA46

DA47

DA48

DA49

DA50

DA51

DA52

DA53

DA54

DA55

DA56

DA57

DA58

DA59

DA60

DA61

DA62

DA63

DDRA_PAR 14

SO-DIMM

DQ39

DQ36

DQ35

DQ34

DQ37

DQ32

DQ38

DQ33

DQ45

DQ44

DQ47

DQ46

DQ40

DQ41

DQ43

DQ42

DQ55

DQ49

DQ54

DQ48

DQ53

DQ52

DQ50

DQ51

DQ61

DQ56

DQ63

DQ58

DQ60

DQ57

DQ59

DQ62

DRAM

UD3.1

UD3.6

UD3.2

UD3.7

UD3.5

UD3.3

UD3.4

UD3.0

UD3.15

UD3.9

UD3.14

UD3.8

UD3.13

UD3.11

UD3.12

UD3.10

UD4.0

UD4.3

UD4.2

UD4.7

UD4.5

UD4.1

UD4.6

UD4.4

UD4.14

UD4.10

UD4.11

UD4.12

UD4.13

UD4.9

UD4.15

UD4.8

J21
H21
F23
H23
G20
F20
J22
J23

G25
F26
L24
L26
L23
F25
K25
K27

M25
M27
P27
R24
L27
M24
P24
P25

M22
N21
T22
V21
L21
M20
R23
T21

AL27
AL25
AP26
AR27
AK26
AK24
AM24
AP27

AM23
AM21
AR25
AU27
AL22
AL21
AP24
AP23

AW26
AV25
AV22
AW22
AU26
AV27
AW23
AT22

AW21
AU21
AP21
AN20
AR22
AN22
AT20
AR20

T24
T25
W25
W27
R26
R27
V27
V26

AF24

DDRA_DQS[0..7]14

DDRA_DQS#[0..7]14

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7

DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15

DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23

DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39

DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47

DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55

DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

DDRA_PAR

3

DDRB_MA[13..0]15

DDRB_MA14_WE#15
DDRB_MA15_CAS#15
DDRB_MA16_RAS#15

DDRB_BA015
DDRB_BA115

DDRB_BG015

TC213 @

DDRB_ACT#15

DDRB_DM[7..0]15

DDRB_CLK015
DDRB_CLK0#15

DDRB_CS0#15

DDRB_CKE015

DDRB_ODT015

DDRB_ALERT#15

1 2

+1.2V

RC240 0_0402_5%@

1 2

RC9 1K_0 402_5%DRAM@

MEM_MB_RST#15

1

MEM_MB_EVENT#

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12

DDRB_MA13
DDRB_MA14_WE#
DDRB_MA15_CAS#
DDRB_MA16_RAS#

DDRB_BA0

DDRB_BA1

DDRB_BG0

DDRB_BG1

DDRB_ACT#

DDRB_DM0

DDRB_DM1

DDRB_DM2

DDRB_DM3

DDRB_DM4

DDRB_DM5

DDRB_DM6

DDRB_DM7

DDRB_DQS0

DDRB_DQS#0

DDRB_DQS1

DDRB_DQS#1

DDRB_DQS2

DDRB_DQS#2

DDRB_DQS3

DDRB_DQS#3

DDRB_DQS4

DDRB_DQS#4

DDRB_DQS5

DDRB_DQS#5

DDRB_DQS6

DDRB_DQS#6

DDRB_DQS7

DDRB_DQS#7

DDRB_CLK0

DDRB_CLK0#

DDRB_CS0#

DDRB_CKE0

DDRB_ODT0

DDRB_ALERT#

MEM_MB_EVENT#

MEM_MB_RST#_R

2

UC2I

AG30

MB_ADD0/MBB_CS0

AC32

MB_ADD1/RSVD

AC30

MB_ADD2/RSVD

AB29

MB_ADD3/RSVD

AB31

MB_ADD4/RSVD

AA30

MB_ADD5/RSVD

AA29

MB_ADD6/RSVD

Y30

MB_ADD7/MBA_CA3

AA31

MB_ADD8/MBA_CA4

W29

MB_ADD9/MBA_CKE1

AH29

MB_ADD10/MBB_CKE0

Y32

MB_ADD11/MBA_CA5

W31

MB_ADD12/MBA_CA2

AL30

MB_ADD13_BANK2/RSVD

AK30

MB_WE_L_ADD14/MBB_CA2

AK32

MB_CAS_L_ADD15/MBB_CA4

AJ30

MB_RAS_L_ADD16/MBB_CA3

AH31

MB_BANK0/MBB_CS1

AG32

MB_BANK1/MBB_CA0

V31

MB_BG0/MBA_CS1

V29

MB_BG1/MBA_CKE0

V30

MB_ACT_L/MBA_CS0

C21

MB_DM0/MBA_DM1

C25

MB_DM1/MBA_DM0

E32

MB_DM2/MBA_DM2

K30

MB_DM3/MBA_DM3

AP30

MB_DM4/MBB_DM2

AW31

MB_DM5/MBB_DM3

BB26

MB_DM6/MBB_DM1

BD22

MB_DM7/MBB_DM0

N32

RSVD_21

D22

MB_DQS_H0/MBA_DQS_H1

B22

MB_DQS_L0/MBA_DQS_L1

D25

MB_DQS_H1/MBA_DQS_H0

B25

MB_DQS_L1/MBA_DQS_L0

F29

MB_DQS_H2/MBA_DQS_H2

F30

MB_DQS_L2/MBA_DQS_L2

K31

MB_DQS_H3/MBA_DQS_H3

K29

MB_DQS_L3/MBA_DQS_L3

AR29

MB_DQS_H4/MBB_DQS_H2

AR31

MB_DQS_L4/MBB_DQS_L2

AW30

MB_DQS_H5/MBB_DQS_H3

AW29

MB_DQS_L5/MBB_DQS_L3

BC25

MB_DQS_H6/MBB_DQS_H1

BA25

MB_DQS_L6/MBB_DQS_L1

BC22

MB_DQS_H7/MBB_DQS_H0

BA22

MB_DQS_L7/MBB_DQS_L0

N31

RSVD_20

N29

RSVD_18

AC31

MB_CLK_H0/MBA_CKT

AD30

MB_CLK_L0/MBA_CKC

AD29

MB_CLK_H1/MBB_CKT

AD31

MB_CLK_L1/MBB_CKC

AE30

RSVD_89

AE32

RSVD_90

AF29

RSVD_91

AF31

RSVD_92

AJ31

MB_CS_L0/MBB_CKE1

AM31

MB_CS_L1/RSVD

AJ29

RSVD_95

AM29

RSVD_97

U29

MB_CKE0/MBA_CA0

T30

MB_CKE1/MBA_CA1

V32

RSVD_93

U31

RSVD_94

AL31

MB_ODT0/MBB_CA5

AM32

MB_ODT1/RSVD

AL29

RSVD_96

AM30

RSVD_98

W30

MB_ALERT_L/MB_TEST

AG29

MB_EVENT_L

T31

MB_RESET_L

@

Memory down

FP5 REV 0.90
PART 9 OF 13

MEMORY B

MB_DATA0/MBA_DATA8

MB_DATA1/MBA_DATA9
MB_DATA2/MBA_DATA13
MB_DATA3/MBA_DATA12
MB_DATA4/MBA_DATA11
MB_DATA5/MBA_DATA10
MB_DATA6/MBA_DATA15
MB_DATA7/MBA_DATA14

MB_DATA8/MBA_DATA0

MB_DATA9/MBA_DATA1
MB_DATA10/MBA_DATA5
MB_DATA11/MBA_DATA4
MB_DATA12/MBA_DATA7
MB_DATA13/MBA_DATA6
MB_DATA14/MBA_DATA2
MB_DATA15/MBA_DATA3

MB_DATA16/MBA_DATA19
MB_DATA17/MBA_DATA18
MB_DATA18/MBA_DATA22
MB_DATA19/MBA_DATA23
MB_DATA20/MBA_DATA20
MB_DATA21/MBA_DATA21
MB_DATA22/MBA_DATA17
MB_DATA23/MBA_DATA16

MB_DATA24/MBA_DATA30
MB_DATA25/MBA_DATA31
MB_DATA26/MBA_DATA26
MB_DATA27/MBA_DATA27
MB_DATA28/MBA_DATA28
MB_DATA29/MBA_DATA29
MB_DATA30/MBA_DATA25
MB_DATA31/MBA_DATA24

MB_DATA32/MBB_DATA16
MB_DATA33/MBB_DATA17
MB_DATA34/MBB_DATA21
MB_DATA35/MBB_DATA20
MB_DATA36/MBB_DATA19
MB_DATA37/MBB_DATA18
MB_DATA38/MBB_DATA23
MB_DATA39/MBB_DATA22

MB_DATA40/MBB_DATA24
MB_DATA41/MBB_DATA25
MB_DATA42/MBB_DATA29
MB_DATA43/MBB_DATA28
MB_DATA44/MBB_DATA31
MB_DATA45/MBB_DATA30
MB_DATA46/MBB_DATA26
MB_DATA47/MBB_DATA27

MB_DATA48/MBB_DATA11
MB_DATA49/MBB_DATA10
MB_DATA50/MBB_DATA14
MB_DATA51/MBB_DATA15
MB_DATA52/MBB_DATA12
MB_DATA53/MBB_DATA13

MB_DATA54/MBB_DATA9
MB_DATA55/MBB_DATA8

MB_DATA56/MBB_DATA6
MB_DATA57/MBB_DATA7
MB_DATA58/MBB_DATA2
MB_DATA59/MBB_DATA3
MB_DATA60/MBB_DATA4
MB_DATA61/MBB_DATA5
MB_DATA62/MBB_DATA1
MB_DATA63/MBB_DATA0

MB_PAROUT/MBB_CA1

AMD-RAVEN-FP5_BGA1140

1

DDRB_DQS[0..7]15

DDRB_DQS#[0..7]15

DQ bi t swapp ing is allowed in a b yte lane.

DDRB_DQ[63..0] 15

APU

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DA8

DA9

DA10

DA11

DA12

DA13

DA14

DA15

DA16

DA17

DA18

DA19

DA20

DA21

DA22

DA23

DA24

DA25

DA26

DA27

DA28

DA29

DA30

DA31

DDRB_PAR 15

SO-DIMM

DQ2 UD1.0

DQ7

DQ6

DQ0

DQ1

DQ5

DQ4

DQ3

DQ12

DQ13

DQ11

DQ10

DQ9

DQ8

DQ15

DQ14

DQ20

DQ16

DQ19

DQ18

DQ17

DQ21

DQ22

DQ23

DQ24

DQ28

DQ30

DQ26

DQ25

DQ29

DQ27

DQ31

RSVD_17
RSVD_19
RSVD_26
RSVD_29
RSVD_16
RSVD_15
RSVD_25
RSVD_24

B21
D21
B23
D23
A20
C20
A22
C22

D24
A25
D27
C27
C23
B24
C26
B27

C30
E29
H29
H31
A28
D28
F31
G30

J29
J31
L29
L31
H30
H32
L30
L32

AP29
AP32
AT29
AU32
AN30
AP31
AR30
AT31

AU29
AV30
BB30
BA28
AU30
AU31
AY32
AY29

BA27
BC27
BA24
BC24
BD28
BB27
BB25
BD25

BC23
BB22
BC21
BD20
BB23
BA23
BB21
BA21

M31
N30
P31
R32
M30
M29
P30
P29

AG31

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7

DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15

DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23

DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31

DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39

DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47

DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55

DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

DDRB_PAR

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

DRAM

UD1.3

UD1.4

UD1.5

UD1.2

UD1.7

UD1.1

UD1.6

UD1.11

UD1.9

UD1.12

UD1.14

UD1.13

UD1.15

UD1.8

UD1.10

UD2.7

UD2.3

UD2.4

UD2.1

UD2.0

UD2.2

UD2.6

UD2.5

UD2.9

UD2.11

UD2.12

UD2.8

UD2.13

UD2.15

UD2.14

UD2.10

A A

Titl e

Titl e

Titl e

FP5 (MEM)

FP5 (MEM)

FP5 (MEM)

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

330ARR

330ARR

330ARR

5 52

5 52

5 52

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

2

G

2

G

2

G

+3VALW_APU

+3VALW_APU

+3VALW_APU

+3VS_APU

+3VS_APU

RC71
10K_0402_5%

1 2

5

G

61

D

QC8A
DMN5L06DWK-7 2N SOT363-6

S

1 2

RC205 0_0402_5%@

+3VS_APU

RC73
10K_0402_5%

@

1 2

5

G

61

D

QC9A
DMN5L06DWK-7 2N SOT363-6

@

S

1 2

RC206 0_0402_5%@

+3VS_APU

RC75
10K_0402_5%

@

1 2

5

G

61

D

QC10A
DMN5L06DWK-7 2N SOT363-6

S

@

1 2

RC207 0_0402_5%@

2013/08/15

2013/08/15

2013/08/15

+1.8VS

RC2

39.2_0402_1%

@

1 2

APU_TEST31

APU_TEST31

M_TEST CONNECTION TBD

RC3131

39.2_0402_1%

@

1 2

12

RC70

4.7K_0402_5%

34

D

QC8B
DMN5L06DWK-7 2N SOT363-6

S

12

RC74

4.7K_0402_5%

@

34

D

QC9B
DMN5L06DWK-7 2N SOT363-6

@

S

RC77

2.2K_0402_5%

@

1 2

34

D

QC10B
DMN5L06DWK-7 2N SOT363-6

S

@

Title

Title

Title

FP5 (DP/JTAG/SIV2/MISC)

FP5 (DP/JTAG/SIV2/MISC)

FP5 (DP/JTAG/SIV2/MISC)

Size

Size

Size

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

PCH_ENBKL 26

Document Number R ev

Document Number R ev

Document Number R ev

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

+1.8VS

RC3101
1K_0402_5%

1 2

DP_STEREOSYNC

RC3102
1K_0402_5%

@

1 2

PCH_EDP_PWM 26

PCH_ENVDD 26

330ARR

330ARR

330ARR

1

6 52

6 52

6 52

APU_EDP_TX0+26

+1.8VS

12

RC18

D D

C C

B B

300_0402_5%

APU_RST#

PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC16
56P_0201_50V8-J

2

@

+1.8VS

12

RC19
300_0402_5%

APU_PWROK

PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC17
56P_0201_50V8-J

2

@

+3VS_APU

RPC8

1 4
2 3

1K_0404_4P2R_5%

RPC51

1 4
2 3

1K_0404_4P2R_5%

+3VS_APU

1 2

RC22 1K_0402_1%

1 2

CC1393 0.1U_0201_6.3V6-K

1 2

CC1394 0.1U_0201_6.3V6-K

APU_SIC
APU_SID

APU_PROCHOT#_R

ALERT#

APU_THERMTRIP#

@

@

APU_THERMTRIP#

APU_PROCHOT#_R

eDP

HDMI

EC_SMB_CK318,39
EC_SMB_DA318,39

APU_THERMTRIP#39

H_PROCHOT#39,49

APU_SVC52
APU_SVD52
APU_SVT52

1

2

@

APU_EDP_TX0-26

APU_EDP_TX1+26
APU_EDP_TX1-26 APU_EDP_AUX 26

APU_HDMI_TX2+27
APU_HDMI_TX2-27

APU_HDMI_TX1+27
APU_HDMI_TX1-27

APU_HDMI_TX0+27
APU_HDMI_TX0-27

APU_HDMI_CLK+27
APU_HDMI_CLK-27

APU_PWROK52

1 2

RC3129 0_0402_5%@

1 2

RC3130 0_0402_5%@

1 2

RC31 0_0402_5%@

1 2

RC213 0_0402_5%@

1 2

RC215 0_0402_5%@

1 2

RC279 0_0402_5%@

APU_SVC APU_SVD

CC1281
1000P_0201_50V7-K

1

CC1283
1000P_0201_50V7-K

2

@

APU_EDP_TX0+
APU_EDP_TX0-

APU_EDP_TX1+
APU_EDP_TX1-

APU_HDMI_TX2+
APU_HDMI_TX2-

APU_HDMI_TX1+
APU_HDMI_TX1-

APU_HDMI_TX0+
APU_HDMI_TX0-

APU_HDMI_CLK+
APU_HDMI_CLK-

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#

APU_RST#
APU_PWROK

APU_SIC
APU_SID

ALERT#
APU_THERMTRIP#

APU_PROCHOT#_R

APU_SVC_RA
APU_SVD_RA
APU_SVT_RA

APU_SVT

1

CC214
1000P_0201_50V7-K

2

@

AU2
AU4
AU1
AU3
AV3

AW3

AW4
AW2

H14

AP16

L19

F16
H16

C8
A8

D8
B8

B6
C7

C6
D6

E6
D5

E1
C1

F3
E4

F4
F2

J14
J15

J16

DP0_TXP0
DP0_TXN0

DP0_TXP1
DP0_TXN1

DP0_TXP2
DP0_TXN2

DP0_TXP3
DP0_TXN3

DP1_TXP0
DP1_TXN0

DP1_TXP1
DP1_TXN1

DP1_TXP2
DP1_TXN2

DP1_TXP3
DP1_TXN3

TDI
TDO
TCK
TMS
TRST_L
DBREQ_L

RESET_L
PWROK

SIC
SID
ALERT_L
THERMTRIP_L
PROCHOT_L

SVC0
SVD0
SVT0

@

DISPLAY/SVI2/JTAG/TEST

DP_STEREOSYNC

TEST31/RSVD

VDDP_SENSE

VDDCR_SOC_SENSE

VDDCR_SENSE

VSS_SENSE_A

FP5 REV 0.90

VSS_SENSE_B

PART 3 OF 13

AMD-RAVEN-FP5_BGA1140

DP_BLON

DP_DIGON

DP_VARY_BL

DP0_AUXP
DP0_AUXN

DP0_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP2_AUXP
DP2_AUXN

DP2_HPD

DP3_AUXP
DP3_AUXN

DP3_HPD

RSVD_4
RSVD_3

RSVD_2

TEST4
TEST5

TEST6

TEST14
TEST15
TEST16
TEST17

TEST41

TEST470
TEST471

SMU_ZVDD

CORETYPE

DP_ENBKL

G15

DP_ENVDD

F15

DP_EDP_PWM

L14

APU_EDP_AUX

D9

APU_EDP_AUX#

B9

APU_EDP_HPD

C10

APU_DDC_CLK

G11

APU_DDC_DATA

F11

APU_HDMI_HPD

G13

J12
H12
K13

J10
H10
K8

DP_STEREOSYNC

K15

F14
F12

F10

AP14

TEST4

AN14

TEST5

F13

APU_TEST14

G18

APU_TEST15

APU_TEST15

H19

APU_TEST16

F18

APU_TEST17

APU_TEST17

F19

APU_TEST31

W24

AR11

AJ21

TEST470

AK21

TEST471

SMU_ZVDDP

V4

AW11

CORETYPE

APU_VDDP_RUN_FB_H

AN11

VDDCR_SOC_VCC_SENSE

J19

VDDCR_VCC_SENSE

K18

VDDCR_VSS_SENSE

J18

VSS_SENSEB

AM11

+1.8VS

1 2

eDP

HDMI

12

VDDCR_SOC_VCC_SENSE
VDDCR_VCC_SENSE
VDDCR_VSS_SENSE

+0.9VS

+3VALW_APU

APU_EDP_AUX# 26
APU_EDP_HPD 26

APU_DDC_CLK 27
APU_DDC_DATA 27
APU_HDMI_HPD 27

1

TC34@

1

TC33@

1

TC32@

1

TC204@

1

TC205@

1

TC206@

RPC47

4 5
3 6
2 7
1 8

1

TC24@

10K_0804_8P4R_5%

1

1
1

@

TC23@

TC22@
TC21@

RC3 196_0402_1%

RC3113 1K_0402_5%@

1

TC35@

1

TC40@

UC2C

APU_DDC_CLK
APU_DDC_DATA

APU_EDP_HPD

VDDCR_SOC_VCC_SENSE 52
VDDCR_VCC_SENSE 52

VDDCR_VSS_SENSE 52

1
1
1

TC52@
TC207@
TC208@

With HDT+ Header

+1.8VALW

RC7
1K_0402_5%

1 2

APU_TRST#

A A

2

CC84

0.01U_0201_10V6K

1

1 2

RC76 33_0402_5%HDT@

1 8

2 7

RPC17
10K_0804_8P4R_5%

HDT@

3 6

4 5

APU_TRST#_R

JHDT1

@

1

1

3

3

5

5

7

7

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

SAMTE_ASP-136446-07-B

2

2

4

4

6

6

8

8

10

12

14

16

18

20

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWROK_BUF

APU_RST#_BUF

APU_DBRDY

1 2

RC273 33_0402_5%HDT@

APU_PLLTEST0

APU_PLLTEST1

APU_DBRDY 12

APU_DBREQ#

APU_PLLTEST0 12

APU_PLLTEST1 12

RPC5

1K_0804_8P4R_5%

2

CC213

0.01U_0201_10V6K

1

HDT@

+1.8VALW+1.8VALW

18
27
36
45

APU_PWROK

APU_RST#

APU_TDIAPU_DBREQ#

2

CC212

0.01U_0201_10V6K

1

@

CC25

0.1U_0201_6.3V6-K

HDT@

UC6

3

2A

2

GND

1

1A

5

4

3

+1.8VALW+1.8VALW

1

2

4

2Y

5

VCC

6

1Y

SN74LVC2G07YZPR_WCSP6HDT@

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

12

RC32
300_0402_5%

HDT@

12

RC36
300_0402_5%

HDT@

APU_PWROK_BUF

APU_RST#_BUF

2013/08/15

2013/08/15

2013/08/15

RPC18

1 4
2 3

2.2K_0404_4P2R_5%

1 2

RC35 100K_0402_5%

To EDP panel

PU FOR INTERNAL

PD FOR CUSTOMER

DP_EDP_PWM

12

RC11
100K_0402_5%

DP_ENVDD

12

RC13
100K_0402_5%

@

LCD Power IC can change for PCH_ENVDD for cost down

DP_ENBKL

12

RC14
100K_0402_5%

@

Deciphered Date

Deciphered Date

Deciphered Date

2

1.0

1.0

1.0

5

Vinafix.com

RC243 0_04 02_5%@

EC_RSMRST#39

D D

1 2

PLT_RST#17,32, 35

C C

Board_ID0

Board_ID1

Board_ID2

Board_ID
[3,4]

Description

0

1

0

1

000NONEC

1

01

10

11

+1.8VS

12

RC3234
2K_0402 _5%

@

0

1

0

1

+1.8VALW

B B

Board_ID5

Board_ID6

RC3202 33_0402 _5%

12

RC3201
100K_04 02_5%

@

R17

R18

Discrete GPU

UMA

NEC

Hynix 8Gb

Micron 8Gb

DIMM_ONLY

Samsung 8Gb

NON-TS

TS

Reserved

Reserved

+3VALW _APU

12

RC3231
2K_0402 _5%

R18@

12

1

CC1389
100P_02 01_25V8J

2

RC1609 RC1607

RC1609 RC1608

RC1615
2K_0402 _5%

@

Stuff RBoard ID

RC1616

RC3234

RC1614

RC1613

RC1612

RC1611

RC1607RC1610

RC1608RC1610

RC123

RC1606

RC3224

RC3225

PCIE_RST0#_R

RB751V-4 0_SOD323-2 @

PBTN_OUT#39

SYS_RESE T#13

PM_SLP_ S3#39
PM_SLP_ S5#13,39

AC_PRESE NT39

+3VS_AP U

DC1

1 2

4

12

+3VALW _APU

HDA_SDIN036

+1.8VALW

12

RC3198
10K_040 2_5%

RSMRST#_R

1

CC1316

0.1U_020 1_6.3V6-K

2

RC191 0_04 02_5%@

PM_SLP_ S3#

RC193 0_04 02_5%@

PM_SLP_ S5#

RC194 0_04 02_5%@

RC100 10K _0402_5%

RC201 0_04 02_5%@

1 2

1 2
1 2

1 2

1 2

+3VALW _APU

TC42 @
TC210 @

1

2

1
1

CC8783
10U_040 2_6.3V6M

EC_SYS_P WRGD39

PCIE_RST0# _R

PCIE_RST1#_R

RSMRST#_R

PWRBTN#_ RP BTN_OUT#
SYS_PW RGD_R
SYS_RESE T#
PCIE_W AKE#_RA

PM_SLP_ S3#_R
PM_SLP_ S5#_R

AC_PRESE NT

BATLOW#

HDA_BITCLK
HDA_SDIN0 _R
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT

BOARD_ID0

HDA_RST_AUD IO#36

HDA_SYNC_A UDIO36
HDA_BITCLK_ AUDIO36
HDA_SDOUT_ AUDIO36

3

1 2

RC3065 0_040 2_5%@

UC2D

BD5

PCIE_RST0_L/EGPIO26

BB6

PCIE_RST1_L/EGPIO27

AT16

RSMRST_L

AR15

PWR_BTN_L/AGPIO0

AV6

PWR_GOOD

AP10

SYS_RESET_L/AGPIO1

AV11

WAKE_L/AGPIO2

AV13

SLP_S3_L

AT14

SLP_S5_L

AR8

S0A3_GPIO/AGPIO10

AT10

AC_PRES/AGPIO23

AN6

LLB_L/AGPIO12

AW8

EGPIO42

AR2

AZ_BITCLK/TDM_BCLK_MIC

AP7

AZ_SDIN0/CODEC_GPI

AP1

AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK

AP4

AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK

AP3

AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC

AR4

AZ_SYNC/TDM_FRM_MIC

AR3

AZ_SDOUT/TDM_FRM_PLAYBACK

AT2

SW_MCLK/TDM_BCLK_BT

AT4

SW_DATA0/TDM_DOUT_BT

AR6

AGPIO7/FCH_ACP_I2S_SDIN_BT

AP6

AGPIO8/FCH_ACP_I2S_LRCLK_BT

@

ACPI/AUDIO/I2C/GPIO/MIS C

RPC4

1 8
2 7
3 6
4 5

33_0804 _8P4R_5%

+3VALW _APU

12

RC3199
10K_040 2_5%

@

SYS_PW RGD_R

1

CC1314

0.1U_020 1_6.3V6-K

2

EGPIO41/SFI_S5_EGPIO41
AGPIO39/SFI_S5_AGPIO39

I2C0_SCL/SFI0_I2C_SCL/EGPIO151

I2C0_SDA/SFI0_I2C_SDA/EGPIO152

I2C1_SCL/SFI1_I2C_SCL/EGPIO149

I2C1_SDA/SFI1_I2C_SDA/EGPIO150

I2C2_SCL/EGPIO113/SCL0

I2C2_SDA/EGPIO114/SDA0

I2C3_SCL/AGPIO19/SCL1
I2C3_SDA/AGPIO20/SDA1

AGPIO4/SATAE_IFDET

SATA_ACT_L/AGPIO130

FP5 REV 0.90

PART 4 OF 13

AMD-RAVEN-F P5_BGA114 0

RC260

1 2

1K_0402_5%

@

PSA_I2C_SCL

PSA_I2C_SDA

AGPIO3

AGPIO5/DEVSLP0
AGPIO6/DEVSLP1

AGPIO9
AGPIO40
AGPIO69
AGPIO86

INTRUDER_ALERT

SPKR/AGPIO91
BLINK/AGPIO11

GENINT1_L/AGPIO89
GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

RC262

RC261

1 2

1 2

1K_0402_5%

@

@

AW12
AU12

AR13
AT13

AN8
AN9

BC20
BA20

AM9
AM10

L16
M16

AT15
AW10

AP9
AU10
AV15

AU7
AU6
AW13
AW15

AU14
AU16
AV8

AW16
BD15

AR18
AT18

HDA_RST#
HDA_SYNC
HDA_BITCLK
HDA_SDOUT

1K_0402_5%

2

SYS_RESE T#

EGPIO15 1
EGPIO15 2

EGPIO14 9
EGPIO15 0

I2C2_SCL _APU
I2C2_SDA _APU

TP_I2C0_S CL_R
TP_I2C0_S DA_R

PSA_I2C_ SCL
PSA_I2C_ SDA

BOARD_ID2

AGPIO5

BOARD_ID6
PXS_PW REN_R1
BOARD_ID3

INTRUDER_AL ERT

BLINK

PCH_TP_INT#

RB751V-4 0_SOD323-2

1

CC38

0.1U_020 1_6.3V6-K

2

RC501 0_04 02_5%@
RC500 0_04 02_5%@

CRB connect to EC and PMIC

RC3240 0_040 2_5%PX@

EC_SMI# 39

RC3100 20M_0402_5%@

SUSP14,27,41

1 2

1 2
1 2

2

G

DC4

SYS_PW RGD_R

@

TP_I2C0_S CL_R 13 ,40
TP_I2C0_S DA_R 13 ,40

USBDEBUG 28

12

12

PCH_BEEP 36

PCH_TP_INT# 40

PXS_PW REN

RC3244
1K_0402 _5%

PX@

1 2

13

D

QC11
2N7002K W_SOT323-3

PX@

S

PCIE_W AKE#_RA

AGPIO5

APU_SMB_ CLK 14,35
APU_SMB_ DATA 14,35

Touch Pad

PXS_PW REN 8 ,50,51

VCCRTC

1 2

RC88 0_0402_ 5%@

2 1

EGPIO14 9
EGPIO15 0
EGPIO15 1
EGPIO15 2

12

DC3

@

RC92 0 _0402_5%@

SDM10U45 LP-7_DFN1006 -2-2

SO-DIMM,Mini Card

PSA_I2C_ SCL

RC3126 4.7K_0402_5%@

PSA_I2C_ SDA

RC3127 4.7K _0402_5%@

I2C2_SCL _APU
I2C2_SDA _APU

EC_SMI#
PCH_TP_INT#

TP_I2C0_S CL_R
TP_I2C0_S DA_R

PBTN_OUT#
PCIE_W AKE#_RA
AC_PRESE NT

Blink
PM_SLP_ S3#

PM_SLP_ S5#
PXS_PW REN_R1

PCH_TP_INT#
RSMRST#_R
SYS_PW RGD_R

PCIE_RST1# _R
PXS_PW REN_R1

RC3081 2.2K _0402_5%
RC3213 10K_0402_5%

RC3119 10K _0402_5%@
RC203 2.2K_0 402_5%@
RC208 2.2K_0 402_5%@
RC3241 10K _0402_5%PX @

RC248 10K _0402_5%@
RC87 100K_04 02_5%
RC89 100K_04 02_5%

RC3227 10K _0402_5%
RC3242 10K _0402_5%@

1

RPC55

1 8
2 7
3 6
4 5

10K_080 4_8P4R_5%

12
12

RPC21

23
14

2.2K_04 04_4P2R_5 %

1 2
1 2

RPC56

23
14

2.2K_04 04_4P2R_5 %

RPC15

1 8
2 7
3 6
4 5

10K_080 4_8P4R_5%

1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2

PCIE_W AKE# 32,35 ,39

+1.8VS

+3VS_AP U

+3VALW _APU

+3VALW _APU

12

RC1613
2K_0402 _5%

UMA@

BOARD_ID0

BOARD_ID19

A A

BOARD_ID49
BOARD_ID59

BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6

RC1616
10K_040 2_5%

R17@

1 2

RC1614
10K_040 2_5%

PX@

1 2

RC1611
10K_040 2_5%

NEC@

1 2

12

RC1612
2K_0402 _5%

NONEC@

5

12

RC1609
2K_0402 _5%

@

RC1610
10K_040 2_5%

@

1 2

1 2

1 2

4

RC1608
10K_040 2_5%

@

RC1607
10K_040 2_5%

@

RC1606
10K_040 2_5%

TS@

1 2

12

RC123
2K_0402 _5%

NOTS@

RC3225
10K_040 2_5%

@

1 2

RC3224
10K_040 2_5%

@

1 2

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Titl e

FP5 AZ/I2C/ACPI/GPIO

FP5 AZ/I2C/ACPI/GPIO

FP5 AZ/I2C/ACPI/GPIO

Size Document Num ber Re v

Size Document Num ber Re v

Size Document Num ber Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

7 52

7 52

7 52

1.0

1.0

1.0

5

Vinafix.com

D D

+3VS_AP U

+3VS_AP U

C C

1 2

RC3161 10K _0402_5%

1 2

RC3162 10K _0402_5%

1 2

RC3163 10K _0402_5%

1 2

RC3164 10K _0402_5%

1 2

RC3217 10K _0402_5%UMA @

1 2

12
12

RC10 150_040 2_1%@
RC6 150_040 2_1%@

RC3223 2K_ 0402_5%PX@

PCH_WL AN_OFF#
LAN_CLKR EQ#
WLAN_C LKREQ#
PCH_BT_OFF#
GPU_CLKR EQ#

XGBECLK 0
XGBECLK 1

GPU_CLKR EQ#

PCIE CL K1

WLAN

PCIE CL K2 LAN

PXS_PW REN7,50,51

CLK_PCIE _WLAN35

CLK_PCIE _WLAN#35

CLK_PCIE _LAN3 2

CLK_PCIE _LAN#3 2

CLK_PCIE _GPU1 7

CLK_PCIE _GPU#17

48MHz/10pF Crystal

1 2

B B

RC3204 1M_04 02_5%

YC1

1

OSC1

NC12OSC2

1

48MHZ_10 PF_7V4800 0017
CC1390
8P_0402 _50V8-B

2

NC2

4

WLAN_C LKREQ#35
LAN_CLKR EQ#32

PCH_BT_OFF#35

PCH_WL AN_OFF#35

12

RC119 0_04 02_5%@
RC120 0_04 02_5%@

RC121 0_04 02_5%@
RC122 0_04 02_5%@

RC117 0_04 02_5%@
RC118 0_04 02_5%@

CC21

10P_040 2_50V8J

RC1090_0402_ 5% @

1 2
1 2

1 2
1 2

1 2
1 2

SUSCLK35

GPU_CLKR EQ#18

CLK_PCIE _WLAN#

CLK_PCIE _LAN# CLK_PCIE_LAN#_ R

X48M_X1

X48M_X2

Kevin H: change YC2 PN change to SJ10000MQ00,manual modify PN to SJ10000MQ00

4

3

1

CC1391
8P_0402 _50V8-B

2

WLAN_C LKREQ#
LAN_CLKR EQ#
PCH_BT_OFF#
PCH_WL AN_OFF#
PXS_PW REN_R
GPU_CLKR EQ#

CLK_PCIE _WLAN_RCLK_PCIE _WLAN
CLK_PCIE _WLAN#_R

CLK_PCIE _LAN_RCLK_PCIE _LAN

CLK_PCIE _GPU_RCLK_PCIE _GPU
CLK_PCIE _GPU#_RCL K_PCIE_GP U#

48M_OSC

1

TC41 @

X48M_X1

X48M_X2

XGBECLK 0
XGBECLK 1

RC45

1 2

20M_040 2_5%

YC3

1 2

32.768K HZ_12.5PF_2 02740-PG1 4

1

2

X32K_X1

X32K_X2

1

CC22
12P_040 2_50V8-J

2

3

APU_LPC_ RST#13,34,39

CLK/LPC/EMMC/SD /SPI/e SPI/UAR T

AV18

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

AN19

CLK_REQ1_L/AGPIO115

AP19

CLK_REQ2_L/AGPIO116

AT19

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

AU19

CLK_REQ4_L/OSCIN/EGPIO132

AW18

CLK_REQ5_L/EGPIO120

AW19

CLK_REQ6_L/EGPIO121

AK1

GPP_CLK0P

AK3

GPP_CLK0N

AM2

GPP_CLK1P

AM4

GPP_CLK1N

AM1

GPP_CLK2P

AM3

GPP_CLK2N

AL2

GPP_CLK3P

AL4

GPP_CLK3N

AN2

GPP_CLK4P

AN4

GPP_CLK4N

AN3

GPP_CLK5P

AP2

GPP_CLK5N

AJ2

GPP_CLK6P

AJ4

GPP_CLK6N

AJ3

X48M_OSC

BB3

X48M_X1

BA5

X48M_X2

AF8

RSVD_76

AF9

RSVD_77

AW14

RTCCLK

AY1

X32K_X1

AY4

X32K_X2

@

PCH_SPI_ CS0#
PCH_SPI_ D1
PCH_SPI_ D2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

+1.8V_SP I

RC3235 10K _0402_5%
RC3236 10K _0402_5%
RC3237 10K _0402_5%@
RC3238 10K _0402_5%@

LPC_PD_L/SD_CMD/AGPIO21

LAD0/SD_DATA0/EGPIO104
LAD1/SD_DATA1/EGPIO105
LAD2/SD_DATA2/EGPIO106
LAD3/SD_DATA3/EGPIO107

LPC_CLKRUN_L/AGPIO88

LPC_RST_L/SD_WP_L/AGPIO32

LPC_PME_L/SD_PWR_CTRL/AGPIO22

SPI_ROM_REQ/EGPIO67
SPI_ROM_GNT/AGPIO76

ESPI_RESET_L/KBRST_L/AGPIO129
ESPI_ALERT_L/LDRQ0_L/EGPIO108

SPI_HOLD_L/ESPI_DAT3

SPI_CS2_L/ESPI_CS_L/AGPIO30

SPI_TPM_CS_L/AGPIO29

UART0_RTS_L/UART2_RXD/EGPIO137
UART0_CTS_L/UART2_TXD/EGPIO135

EGPIO142/UART1_RTS_L/UART3_RXD
EGPIO140/UART1_CTS_L/UART3_TXD

FP5 REV 0.90

PART 5 OF 13

AMD-RAVEN-F P5_BGA114 0

UC3

/HOLDor/RESET(IO3)

W25Q6 4FWSSIQ_ SO8

8MB(64Mb)

1 2
1 2
1 2
1 2

1 2

RC46 33_04 02_5%

1

CC1318
150P_04 02_50V8-J

2

UC2E

8
7
6
5

PCH_SPI_ CS0#
PCH_SPI_ D1
PCH_SPI_ D2
PCH_SPI_ D3

BD13
BB14
BB12
BC11
BB15
BC15
BA15
BC13
BB13
BC12
BA12

BD11
BA11
BA13

BC8
BB8

BB11
BC6

BB7
BA9
BB10
BA10
BC10
BC9
BA8
BA6
BD8

BA16
BB18
BC17
BA18
BD18

BC18
BA17
BC16
BB19
BB16

+1.8V_SP I
PCH_SPI_ D3
PCH_SPI_ CLK
PCH_SPI_ D0

EGPIO70/SD_CLK

LPCCLK0/EGPIO74

LPCCLK1/EGPIO75

SERIRQ/AGPIO87

LFRAME_L/EGPIO109

AGPIO68/SD_CD

SPI_CLK/ESPI_CLK
SPI_DI/ESPI_DAT1

SPI_DO/ESPI_DAT0

SPI_WP_L/ESPI_DAT2

SPI_CS1_L/EGPIO118

SPI_CS3_L/AGPIO31

UART0_RXD/EGPIO136
UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

EGPIO141/UART1_RXD
EGPIO143/UART1_TXD

AGPIO144/UART1_INTR

VCC

CLK

DI(IO0)

LPC_RST#_R

EGPIO70
LPCPD#
LAD0

RC3208 10_ 0402_5%

LAD1

RC3209 10_ 0402_5%

LAD2

RC3210 10_ 0402_5%

LAD3

RC3211 10_ 0402_5%

LPCCLK0

EGPIO75

LPC_RST#_R

KBRST#

RC3141 0_040 2_5%@

SPI_CLK

RC3083 10_ 0402_5%

SPI_D1

RC3084 0_040 2_5%@

SPI_D0

RC3085 0_040 2_5%@

SPI_D2

RC3087 0_040 2_5%@

SPI_D3

RC3088 0_040 2_5%@

SPI_CS0#

RC3089 0_040 2_5%@

AGPIO30

APU_UART0_ RXD
APU_UART0_ TXD
APU_UART0_ RTS#
APU_UART0_ CTS#
APU_UART0_ INTR

DGPU_PW ROK

PXS_RST#_ R

0.085 A

1 2
1 2
1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2
1 2

1

CC220

0.1U_020 1_6.3V6-K

2

2

1 2

RC3220 0_040 2_5%@

1 2

RC435 0_04 02_5%@

LDRQ0#

PCH_SPI_ CLK
PCH_SPI_ D1
PCH_SPI_ D0
PCH_SPI_ D2
PCH_SPI_ D3
PCH_SPI_ CS0#

LPCCLK0

LPCPD# 1 3

LPC_AD0 13,34,39
LPC_AD1 13,34,39
LPC_AD2 13,34,39
LPC_AD3 13,34,39

LPC_CLKR UN# 13,34

SERIRQ 13,34,39
LPC_FRAME # 13,34 ,39

EC_SCI# 39

KBRST# 39
LDRQ0# 1 3

PCH_SPI_ CLK 1 3

DGPU_PW ROK 1 7

PXS_RST# 1 7

+1.8VALW+1 .8V_SPI

LPCCLK0

RC126 3.3_0 402_1%
RC125 22_0 402_5%TPM@

RC3212

RC3138

RC3136

1 2

1 2

1 2

1K_0402_1%

1K_0402_1%

1K_0402_1%

@

@

@

@

PCH_SPI_ CLK

12

RC282
0_0201_ 5%

EMC_NS@

1

CC219
22P_020 1_25V8

EMC_NS@

2

EMC EMC

12
12

LPC_FRAME #

KBRST#

PXS_RST#_ R

PXS_PW REN_R

DGPU_PW ROK

EC_SCI#

+1.8VS

RC3139

RC3140

1 2

1 2

1K_0402_1%

1K_0402_1%

@

PXS_RST#

PXS_RST#_ R

EGPIO70

AGPIO30

EGPIO75

DGPU_PW ROK

1

RC139
10_0402 _5%

EMC_NS@

1 2

1

CC26
10P_020 1_25V8G

EMC_NS@

2

CLK_PCI_ EC 13,3 9

TPM_CLK 34

1 2

RC152 10K _0402_5%@

1 2

RC3063 10K _0402_5%

1 2

RC3226 10K _0402_5%@

1 2

RC3228 10K _0402_5%@

1 2

RC3229 1K_ 0402_5%@

PX@

12

+3VALW _APU

CC12590.01U_02 01_10V6K

RC322210K_ 0402_5% PX@

RC315710K_ 0402_5% @

RC315810K_ 0402_5%

RC316010K_ 0402_5%

RC155810K_ 0402_5% UMA@

1 2

RC3091 10K _0402_5%@

1 2

1 2

1 2

1 2

1 2

+3VS_AP U

A A

Titl e

Titl e

Titl e

FP5 CLK/LPC/SD/EMMC/UART

FP5 CLK/LPC/SD/EMMC/UART

FP5 CLK/LPC/SD/EMMC/UART

Size Document Num ber Re v

Size Document Num ber Re v

Size Document Num ber Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

8 52

8 52

8 52

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

AD2

USBC0_A2/USB_0_TXP0/DP3_TXP2

AD4

USBC0_A3/USB_0_TXN0/DP3_TXN2

AC2

USBC0_B11/USB_0_RXP0/DP3_TXP3

AC4

D D

USB30_TX_P329

Type C

LEFT USB (3.0) lower

LEFT USB (3.0) upper

C C

USB30_TX_N329

USB30_RX_P329

USB30_RX_N329

USB30_TX_P228
USB30_TX_N228

USB30_RX_P228

USB30_RX_N228

USB30_TX_P128
USB30_TX_N128

USB30_RX_P128

USB30_RX_N128

USB30_TX_P3
USB30_TX_N3

USB30_RX_P3
USB30_RX_N3

USB30_TX_P2
USB30_TX_N2

USB30_RX_P2
USB30_RX_N2

USB30_TX_P1
USB30_TX_N1

USB30_RX_P1
USB30_RX_N1

USBC0_B10/USB_0_RXN0/DP3_TXN3

AF4

USBC0_B2/DP3_TXP1

AF2

USBC0_B3/DP3_TXN1

AE3

USBC0_A11/DP3_TXP0

AE1

USBC0_A10/DP3_TXN0

AG3

USB_0_TXP1

AG1

USB_0_TXN1

AJ9

USB_0_RXP1

AJ8

USB_0_RXN1

AG4

USB_0_TXP2

AG2

USB_0_TXN2

AG7

USB_0_RXP2

AG6

USB_0_RXN2

AA2

USBC1_A2/USB_0_TXP3/DP2_TXP2

AA4

USBC1_A3/USB_0_TXN3/DP2_TXN2

Y1

USBC1_B11/USB_0_RXP3/DP2_TXP3

Y3

USBC1_B10/USB_0_RXN3/DP2_TXN3

AC1

USBC1_B2/DP2_TXP1

AC3

USBC1_B3/DP2_TXN1

AB2

USBC1_A11/DP2_TXP0

AB4

USBC1_A10/DP2_TXN0

AH4

USB_1_TXP0

AH2

USB_1_TXN0

AK7

USB_1_RXP0

AK6

USB_1_RXN0

@

USB

FP5 REV 0.90

PART 10 OF 13

USB_OC0_L/AGPIO16
USB_OC1_L/AGPIO17
USB_OC2_L/AGPIO18
USB_OC3_L/AGPIO24
AGPIO14/USB_OC4_L
AGPIO13/USB_OC5_L

AMD-RAVEN-FP 5_BGA1140

UC2J

USB_0_DP0
USB_0_DM0

USB_0_DP1
USB_0_DM1

USB_0_DP2
USB_0_DM2

USB_0_DP3
USB_0_DM3

USB_1_DP0
USB_1_DM0

USB_1_DP1
USB_1_DM1

USBC_I2C_SCL

USBC_I2C_SDA

USB20_P4

AE7

USB20_N4

AE6

USB20_P7

AG10

USB20_N7

AG9

USB20_P6

AF12

USB20_N6

AF11

USB20_P5

AE10

USB20_N5

AE9

USB20_P5_HUB

AJ12

USB20_N5_HUB

AJ11

USB20_P0

AD9

USB20_N0

AD8

USBC_I2C_SCL

AM6

USBC_I2C_SDA

AM7

BOARD_ID1

AK10
AK9

USB_OC2# USB_OC1#

AL9

USB_OC1#

AL8

BOARD_ID5

AW7

BOARD_ID4

AT12

USB20_P4 36
USB20_N4 36

USB20_P7 29
USB20_N7 29

USB20_P6 28
USB20_N6 28

USB20_P5 28
USB20_N5 28

USB20_P0 35
USB20_N0 35

1 2

RC3239 0_0402_5%@

1 2

RC3233 0_0402_5%@

USB20_P5_HUB 31
USB20_N5_HUB 31

BOARD_ID1 7

USB_OC1# 28
BOARD_ID5 7
BOARD_ID4 7

Card Reader

Type C

LEFT USB (3.0) lower

LEFT USB (3.0) upper

USB HUB(Camera,FP,Touch Screen)

BT

TYPE_C_OCP#USB_OC3#

USB_OC3#
USB_OC1#

USBC_I2C_SCL
USBC_I2C_SDA

TYPE_C_OCP# 29

1 2

RC3218 10K_0402_5%

1 2

RC3219 10K_0402_5%

1 2

RC270 4.7K_0402_5%

1 2

RC3232 4.7K_0402_5%

+1.8VALW

+3VALW_A PU

RSVD_62
RSVD_61
RSVD_65

RSVD_72

RSVD_67
RSVD_63

RSVD_33
RSVD_73

RSVD_53
RSVD_54

RSVD_45
RSVD_46

3

UC2L

AA9
AA8
AC6

AD11

AC9
AA11

T12
AD12

Y6
Y7

W8
W9

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Titl e

Titl e

Titl e

FP5 USB/WIFI

FP5 USB/WIFI

FP5 USB/WIFI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

9 52

9 52

9 52

1.0

1.0

1.0

T11

RSVD_32

AC7

W11
W12

AA12
AC10

RSVD_66

Y9

RSVD_55

Y10

RSVD_56

RSVD_47
RSVD_48

V9

RSVD_38

V10

RSVD_39

RSVD_64
RSVD_68

@

B B

A A

5

4

RSVD

FP5 REV 0.90
PART 12 OF 13

AMD-RAVEN-FP 5_BGA1140

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

5

Vinafix.com

D D

4

3

2

1

C C

B B

A18

CAM0_CSI2_CLOCKP

C18

CAM0_CSI2_CLOCKN

A15

CAM0_CSI2_DATAP0

C15

CAM0_CSI2_DATAN0

B16

CAM0_CSI2_DATAP1

C16

CAM0_CSI2_DATAN1

C19

CAM0_CSI2_DATAP2

B18

CAM0_CSI2_DATAN2

B17

CAM0_CSI2_DATAP3

D17

CAM0_CSI2_DATAN3

D12

CAM1_CSI2_CLOCKP

B12

CAM1_CSI2_CLOCKN

C13

CAM1_CSI2_DATAP0

A13

CAM1_CSI2_DATAN0

B11

CAM1_CSI2_DATAP1

C12

CAM1_CSI2_DATAN1

J13

RSVD_6

@

CAMERAS

FP5 REV 0.90

PART 13 OF 13

AMD-RAVEN-FP5_BGA1140

UC2M

CAM0_CLK

CAM0_I2C_SCL

CAM0_I2C_SDA

CAM0_SHUTDOWN

CAM1_CLK

CAM1_I2C_SCL

CAM1_I2C_SDA

CAM1_SHUTDOWN

CAM_PRIV_LED

CAM_IR_ILLU

B15

D15
C14

B13

B10

A11
C11

D11

D13
D10

A A

Titl e

Titl e

Titl e

FP5 CAM

FP5 CAM

FP5 CAM

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

10 52

10 52

10 52

1.0

1.0

1.0

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

5

Vinafix.com

4

3

2

1

+VDDCR_SOC

10A

M15

VDDCR_SOC_1

M18

VDDCR_SOC_2

M19

VDDCR_SOC_3

6A

0.2A

0.25A

2A

0.5A

1A

4A

N16

VDDCR_SOC_4

N18

VDDCR_SOC_5

N20

VDDCR_SOC_6

P17

VDDCR_SOC_7

P19

VDDCR_SOC_8

R18

VDDCR_SOC_9

R20

VDDCR_SOC_10

T19

VDDCR_SOC_11

U18

VDDCR_SOC_12

U20

VDDCR_SOC_13

V19

VDDCR_SOC_14

W18

VDDCR_SOC_15

W20

VDDCR_SOC_16

Y19

VDDCR_SOC_17

T32

VDDIO_MEM_S3_1

V28

VDDIO_MEM_S3_2

W28

VDDIO_MEM_S3_3

W32

VDDIO_MEM_S3_4

Y22

VDDIO_MEM_S3_5

Y25

VDDIO_MEM_S3_6

Y28

VDDIO_MEM_S3_7

AA20

VDDIO_MEM_S3_8

AA23

VDDIO_MEM_S3_9

AA26

VDDIO_MEM_S3_10

AA28

VDDIO_MEM_S3_11

AA32

VDDIO_MEM_S3_12

AC20

VDDIO_MEM_S3_13

AC22

VDDIO_MEM_S3_14

AC25

VDDIO_MEM_S3_15

AC28

VDDIO_MEM_S3_16

AD23

VDDIO_MEM_S3_17

AD26

VDDIO_MEM_S3_18

AD28

VDDIO_MEM_S3_19

AD32

VDDIO_MEM_S3_20

AE20

VDDIO_MEM_S3_21

AE22

VDDIO_MEM_S3_22

AE25

VDDIO_MEM_S3_23

AE28

VDDIO_MEM_S3_24

AF23

VDDIO_MEM_S3_25

AF26

VDDIO_MEM_S3_26

AF28

VDDIO_MEM_S3_27

AF32

VDDIO_MEM_S3_28

AG20

VDDIO_MEM_S3_29

AG22

VDDIO_MEM_S3_30

AG25

VDDIO_MEM_S3_31

AG28

VDDIO_MEM_S3_32

AJ20

VDDIO_MEM_S3_33

AJ23

VDDIO_MEM_S3_34

AJ26

VDDIO_MEM_S3_35

AJ28

VDDIO_MEM_S3_36

AJ32

VDDIO_MEM_S3_37

AK28

VDDIO_MEM_S3_38

AL28

VDDIO_MEM_S3_39

AL32

VDDIO_MEM_S3_40

AP12

VDDIO_AUDIO

AL18

VDD_33_1

AM17

VDD_33_2

AL20

VDD_18_1

AM19

VDD_18_2

AL19

VDD_18_S5_1

AM18

VDD_18_S5_2

AL17

VDD_33_S5_1

AM16

VDD_33_S5_2

AL14

VDDP_S5_1

AL15

VDDP_S5_2

AM14

VDDP_S5_3

AL13

VDDP_1

AM12

VDDP_2

AM13

VDDP_3

AN12

VDDP_4

AN13

VDDP_5

AT11

VDDBT_RTC_G

@

EC_RTCRST#_ON 39

D D

+1.2V

1

CC1337

2

1U_0402_6.3V6K

BOBUBU

1U_0402_6.3V6K

1U_0402_6.3V6K

+RTCBATT

1U_0402_6.3V6K

+3VS_APU

1

CC1338

2

1U_0402_6.3V6K

CD@

1

CC1324

CC1323

2

1U_0402_6.3V6K

+RTCBATT

RC3128 1K_0402_5%

1

JCMOS1

@

1

2

1U_0402_6.3V6K

BU

1 2

+1.8VS

1

CC1325

2

+RTCBATT_APU

12

13

D

S

1 2

1U_0402_6.3V6K

RC8
470_0603_5%

@

+1.8VALW

RC3154

RC3118
0_0402_5%

0_0402_5%

@

@

1 2

12

CC1385

BO

1

1

CC1327

CC1326

2

2

1U_0402_6.3V6K

1

CC1340

2

1U_0402_6.3V6K

BU

QC7

EC_RTCRST#_ON

2

G

2N7002KW_SOT323-3

@

CC1339

22U_0603_6.3V6-M

180P_0402_50V8-J

CC192

+VDD_AUD_ALW

1

2

1U_0402_6.3V6K

0.25A

0.1A

1

2

0.22U_0201_6.3V6-K

12

RC15
100K_0402_5%

@

+3VS+VDDC_VDD

1 2

+1.8VS

+1.8VALW

+3VALW_APU

+0.9VALW

+0.9VS

12

CC1381

22U_0603_6.3V6-M

BO(Bottom side outside SOC)

1

CC37

2

12

12

12

12

12

RC3112 0_0402_5%@

1

CC1335

CC1336

2

CC1376

1U_0402_6.3V6K

BO B U

22U_0603_6.3V6-M

CC1377

22U_0603_6.3V6-M

CC1378

22U_0603_6.3V6-M

CC1379

22U_0603_6.3V6-M

BO BU

CC1380

22U_0603_6.3V6-M

1U_0402_6.3V6K

CD@

1

CC1334

CC1333

2

1U_0402_6.3V6K

BO BU

CD@

1

CC1331

CC1332

2

1U_0402_6.3V6K

BO B U

CD@

1

CC1328

CC1329

2

1U_0402_6.3V6K

CD@

1

1

CC1319

CC1320

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

UC5

1

Vin

2

GND

AP2138N-1.5TRG1_SOT23-3

12

CC1375

22U_0603_6.3V6-M

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

1

CC1330

2

2

1U_0402_6.3V6K

CD@

1

1

CC1322

CC1321

2

2

1U_0402_6.3V6K

3

Vout

1

CC194

2

1

CC1382

2

180P_0402_50V8-J

+VDDCR_SOC

1

C C

B B

CC1372

10U_0402_6.3V6M

1

2

2

+1.2V

12

12

CC1341

CC1257

22U_0603_6.3V6-M

CD@

CD@

All BU(on bottom side under SOC)

+1.2V

1

CC168

2

@

CC1383
10U_0402_6.3V6M

12

12

CC1342

CC1343

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

1

CC169

CC170

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

CD@

DECOUPLING BETWEEN PROCESSOR AND DIMMs
ACROSS VDDIO AND VSS SPLIT

12

12

12

CC1345

CC1344

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

CC172

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

12

12

CC1346

CC1347

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CD@

1

1

CC179

CC176

2

2

180P_0402_50V8-J

@

1

1

1

CC1374

CC1384

CC1373

CC1348

22U_0603_6.3V6-M

180P_0402_50V8-J

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8-J

CD@

VCCRTC

1 2

RC231 10K_0402_5%

POWER

FP5 REV 0.90
PART 6 OF 13

AMD-RAVEN-FP5_BGA1140

UC2F

VDDCR_1
VDDCR_2
VDDCR_3
VDDCR_4
VDDCR_5
VDDCR_6
VDDCR_7
VDDCR_8

VDDCR_9
VDDCR_10
VDDCR_11
VDDCR_12
VDDCR_13
VDDCR_14
VDDCR_15
VDDCR_16
VDDCR_17
VDDCR_18
VDDCR_19
VDDCR_20
VDDCR_21
VDDCR_22
VDDCR_23
VDDCR_24
VDDCR_25
VDDCR_26
VDDCR_27
VDDCR_28
VDDCR_29
VDDCR_30
VDDCR_31
VDDCR_32
VDDCR_33
VDDCR_34
VDDCR_35
VDDCR_36
VDDCR_37
VDDCR_38
VDDCR_39
VDDCR_40
VDDCR_41
VDDCR_42
VDDCR_43
VDDCR_44
VDDCR_45
VDDCR_46
VDDCR_47
VDDCR_48
VDDCR_49
VDDCR_50
VDDCR_51
VDDCR_52
VDDCR_53
VDDCR_54
VDDCR_55
VDDCR_56
VDDCR_57
VDDCR_58
VDDCR_59
VDDCR_60
VDDCR_61
VDDCR_62
VDDCR_63
VDDCR_64
VDDCR_65
VDDCR_66
VDDCR_67
VDDCR_68
VDDCR_69
VDDCR_70
VDDCR_71
VDDCR_72
VDDCR_73
VDDCR_74
VDDCR_75
VDDCR_76
VDDCR_77
VDDCR_78
VDDCR_79
VDDCR_80
VDDCR_81
VDDCR_82
VDDCR_83

G7
G10
G12
G14
H8
H11
H15
K7
K12
K14
L8
M7
M10
N14
P7
P10
P13
P15
R8
R14
R16
T7
T10
T13
T15
T17
U14
U16
V13
V15
V17
W7
W10
W14
W16
Y8
Y13
Y15
Y17
AA7
AA10
AA14
AA16
AA18
AB13
AB15
AB17
AB19
AC14
AC16
AC18
AD7
AD10
AD13
AD15
AD17
AD19
AE8
AE14
AE16
AE18
AF7
AF10
AF13
AF15
AF17
AF19
AG14
AG16
AG18
AH13
AH15
AH17
AH19
AJ7
AJ10
AJ14
AJ16
AJ18
AK13
AK15
AK17
AK19

+VDDC_VDD

35A

A A

Title

Title

Title

FP5 POWER

FP5 POWER

FP5 POWER

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330ARR

330ARR

330ARR

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

11 52

11 52

11 52

5

4

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

1.0

1.0

1.0

5

Vinafix.com

D D

4

3

2

1

VSS_316

A3

VSS_1

A5

VSS_2

A7

VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

C3

VSS_13
VSS_14
VSS_15
VSS_16
VSS_17

E7

VSS_18

E8

VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35

F5

VSS_36
VSS_37

G1

VSS_38

G5

VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46

H5

VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53

K1

VSS_54

K5

VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

AMD-RAVEN-FP5_BGA1140

@

GND

FP5 REV 0.90

PART 7 OF 13

VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123

K32
L5
L13
L15
L18
L20
L25
L28
M1
M5
M12
M21
M23
M26
M28
M32
N4
N5
N8
N11
N13
N15
N17
N19
N22
N25
N28
P1
P5
P14
P16
P18
P20
P23
P26
P28
P32
R5
R11
R12
R13
R15
R17
R19
R22
R25
R28
R30
T1
T5
T14
T16
T18
T20
T23
T26
T28
U13
U15
U17
U19
V5

N12

A10
A12
A14
A16
A19
A21
A23
A26
A30

C32
D16
D18
D20

E10
E11
E12
E13
E14
E15

C C

B B

E16
E18
E19
E20
E21
E22
E23
E25
E26
E27

F28

G16
G19
G21
G23
G26
G28
G32

H13
H18
H20
H22
H25
H28

K16
K19
K21
K22
K26
K28

AA13
AA15
AA17
AA19
AB14
AB16
AB18
AB20

AC11
AC12
AC13
AC15
AC17
AC19

AD14
AD16
AD18
AD20

AE11
AE12
AE13
AE15
AE17
AE19

AF14
AF16
AF18
AF20

V8

VSS_124

V11

VSS_125

V12

VSS_126

V14

VSS_127

V16

VSS_128

V18

VSS_129

V20

VSS_130

V22

VSS_131

V25

VSS_132

W1

VSS_133

W5

VSS_134

W13

VSS_135

W15

VSS_136

W17

VSS_137

W19

VSS_138

W23

VSS_139

W26

VSS_140

Y5

VSS_141

Y11

VSS_142

Y12

VSS_143

Y14

VSS_144

Y16

VSS_145

Y18

VSS_146

Y20

VSS_147

AA1

VSS_148

AA5

VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157

AC5

VSS_158

AC8

VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165

AD1

VSS_166

AD5

VSS_167
VSS_168
VSS_169
VSS_170
VSS_171

AE5

VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178

AF1

VSS_179

AF5

VSS_180
VSS_181
VSS_182
VSS_183
VSS_184

AG5

VSS_185

@

UC2G

UC2H

GND

VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247

FP5 REV 0.90

PART 8 OF 13

AMD-RAVEN-FP5_BGA1140

AG8
AG11
AG12
AG13
AG15
AG17
AG19
AH14
AH16
AH18
AH20
AJ1
AJ5
AJ13
AJ15
AJ17
AJ19
AK5
AK8
AK11
AK12
AK14
AK16
AK18
AK20
AK22
AK25
AL1
AL5
AL7
AL10
AL12
AL16
AL23
AL26
AM5
AM8
AM15
AM20
AM22
AM25
AM28
AN1
AN5
AN7
AN10
AN15
AN18
AN21
AN23
AN26
AN28
AN32
AP5
AP8
AP13
AP15
AP18
AP20
AP25
AP28
AR1

AR12
AR14
AR16
AR19
AR21
AR26
AR28
AR32

AU11
AU13
AU15
AU18
AU20
AU22
AU25
AU28

AV10
AV12
AV14
AV16
AV19
AV21
AV23
AV26
AV28
AV32

AW5

AW28

AY10
AY11
AY12
AY13
AY14
AY15
AY16
AY18
AY19
AY20
AY21
AY22
AY23
AY25
AY26
AY27

BB20
BB32

BD10
BD12
BD14

AR5

VSS_248

AR7

VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257

AU5

VSS_258

AU8

VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267

AV1

VSS_268

AV5

VSS_269

AV7

VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282

AY6

VSS_283

AY7

VSS_284

AY8

VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301

BB1

VSS_302
VSS_303
VSS_304

BD3

VSS_305

BD7

VSS_306
VSS_307
VSS_308
VSS_309

@

UC2K

GND/RSVD

VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315

RSVD_1
RSVD_5
RSVD_7
RSVD_8

RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_22
RSVD_23
RSVD_30
RSVD_31
RSVD_37
RSVD_44
RSVD_49
RSVD_50
RSVD_57
RSVD_58
RSVD_59
RSVD_60
RSVD_69
RSVD_70
RSVD_71
RSVD_74
RSVD_75
RSVD_78
RSVD_79
RSVD_80
RSVD_81
RSVD_82
RSVD_83
RSVD_87
RSVD_88

RSVD_14
RSVD_84
RSVD_85
RSVD_86

FP5 REV 0.90

PART 11 OF 13

AMD-RAVEN-FP5_BGA1140

BD16
BD19
BD21
BD23
BD26
BD30

B20
G3
J20
K3
K6
K20
M3
M6
M13
P6
P22
T3
T6
T29
W6
W21
W22
Y21
Y27
AA3
AA6
AC29
AD3
AD6
AF3
AF6
AF30
AJ6
AJ24
AK23
AK27
AL3
AN29
AN31

UNNAMED_15_F P5_I216_RSVD14

M14

UNNAMED_15_F P5_I216_RSVD84

AL6

UNNAMED_15_F P5_I216_RSVD85

AL11

UNNAMED_15_F P5_I216_RSVD86

AN16

1 2

RC3103 0_0402_5%@

1 2

RC3104 0_0402_5%@

1 2

RC3105 0_0402_5%@

1 2

RC3106 0_0402_5%@

APU_PLLTEST0

APU_PLLTEST1
APU_DBRDY

+5VALW

APU_PLLTEST0 6

APU_PLLTEST1 6
APU_DBRDY 6

A A

Titl e

Titl e

Titl e

FP5 GND

FP5 GND

FP5 GND

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

12 52

12 52

12 52

1.0

1.0

1.0

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

5

Vinafix.com

D D

PCH_SPI_CLK8 SYS_RESET#7

PCH_SPI_CLK

4

+1.8VS +1.8VALW +3VALW_APU

RC3134
10K_0402_5%

@

12

RC3133
10K_0402_5%

12

RC159
2K_0402_5%

@

12

RC156
10K_0402_5%

12

RC163
2K_0402_5%

@

12

3

2

1

STRAP PINS

PCH_SPI_CLK

C C

SYS_RESET#

1:USE 48MHZ CRYSTAL CLOCK AND
GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
0:USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK AND
GENERATE INTERNAL CLOCKS ONLY

1:NORMAL RESET MODE(DEFAULT)

SYS_RESET#

0:SHORT RESET MODE

LPC ROM EMULATOR HEADER

LPC@

RC3146
0_0402_5%

1 2

LPC_RST#_H

2

1

+3VS_APU+3VALW_APU

LPC@

1 2

LPCRUNPWR

I2C2_SCL_LPC

2

1

RC3145
0_0402_5%

CD347

0.1U_0402_10V7K

LPC@

PIN4 should be removed as a Key

DAISY CHAIN ROUT ING FO R LPC SIGNALS

J601

1 2
3 4

UNNAMED_16_C ON20_I130_P6

5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20

HEADER_2X10

@

RC3142 0_0402_5%@

LPC_AD1

I2C2_SDA_LPC

SERIRQ
LPC_CLKRUN#

LDRQ0#

1 2

RC3153 0_0402_5%LPC@

1 2

PM_SLP_S5#

PM_SLP_S5# 7,39
LPC_AD2 8,34,39
LPC_AD1 8,34,39

TP_I2C0_SDA_R 7,40
SERIRQ 8,34,39
LPC_CLKRUN# 8,34

15P_0402_50V8J

CC1387

B B

CLK_PCI_EC8,39
LPC_FRAME#8,34,39

APU_LPC_RST#8,34,39

LPC_AD38,34,39

LPC_AD08,34,39

TP_I2C0_SCL_R7,40

LPCPD#8 LDRQ0# 8

@

CLK_PCI_EC
LPC_FRAME#
APU_LPC_RST#

LPC_AD3 LPC_AD2

LPC_AD0

LPCPD#

12

RC3147

UNNAMED_16_C AP_I116_B

1 2

@

1 2

RC3144 0_0402_5%LPC@

1 2

RC3152 0_0402_5%LPC@

33_0402_5%

CD345

0.1U_0402_10V7K

LPC@

RC3152 RC3153 s hould be put on APU s ide to reduce stub when MP

+3VS_APU

1 2

RC3214 10K_0402_5%LPC@

1 2

RC3215 10K_0402_5%@

1 2

A A

RC3216 100K_0402_5%LPC@

1 2

CC1392 150P_0402_50V8-J@

5

4

LPCPD#

LPC_CLKRUN#

APU_LPC_RST#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Titl e

Titl e

Titl e

FP5 Straps

FP5 Straps

FP5 Straps

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

13 52

13 52

13 52

1.0

1.0

1.0

5

Vinafix.com

JDDR1A

1

DDRA_DQ1

D D

C C

RD273 240_0402_1%@
RD274 240_0402_1%@

DDRA_CKE05

DDRA_BG15 DDRA_ACT# 5
DDRA_BG05

B B

A A

+1.2V

12

RD258
1K_0402_1%

@

DDRA_ALERT#

+3VS +3VS

12

RD26

10K_0402_5%

@

DDRA0_SA0 DDRA0_SA1 DDRA0_SA2

12

RD268
0_0402_5%

@

DDRA_DQ6

DDRA_DQS#0
DDRA_DQS0

DDRA_DQ7

DDRA_DQ3

DDRA_DQ8

DDRA_DQ9

DDRA_DM1

DDRA_DQ17

DDRA_DQ21

DDRA_DQS#2
DDRA_DQS2

DDRA_DQ22

DDRA_DQ19

DDRA_DQ25

DDRA_DQ29

DDRA_DM3

DDRA_DQ30

DDRA_DQ31

1 2
1 2

+3VS

12

12

+1.2V +1.2V+1.2V

DDRA_CKE0

DDRA_BG1
DDRA_BG0

DDRA_MA12
DDRA_MA9

DDRA_MA8
DDRA_MA6 DDRA_MA4

RD269

10K_0402_5%

@

RD28
0_0402_5%

@

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_ n/NC

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_ n/NC

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AS0-26001-1P60

ME@

RD11

1K_0402_1%

12

RD270

10K_0402_5%

@

12

RD29
0_0402_5%

@

DM0_n/DBIO_n/NC

DM2_n/DBl2_ n/NC

DM8_n/DBI8_n/NC

+1.2V

12

RD10
1K_0402_1%

1 2

CD262

1

2

15mil

0.1U_0201_6.3V6-K

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15

DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24
VSS_35
DQS3_c

DQS3_t

VSS_38

DQ31
VSS_40

DQ27
VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

CKE1

VDD_2
ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

CD116

DQ4

DQ0

DQ6

DQ2

DQ8

A11

1

2

A7

A5
A4

+VREF_CA

0.1U_0201_6.3V6-K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130

1

2

CD117

1000P_0201_50V7-K

4

DDRA_DQ4

DDRA_DQ5

DDRA_DM0

DDRA_DQ0

DDRA_DQ2

DDRA_DQ12

DDRA_DQ13

DDRA_DQS#1
DDRA_DQS1

DDRA_DQ10DDRA_DQ14

DDRA_DQ15DDRA_DQ11

DDRA_DQ16

DDRA_DQ20

DDRA_DM2

DDRA_DQ18

DDRA_DQ23

DDRA_DQ24

DDRA_DQ28

DDRA_DQS#3
DDRA_DQS3

DDRA_DQ26

DDRA_DQ27

MEM_MA_RST#
DDRA_CKE1

DDRA_ACT#
DDRA_ALERT#

DDRA_MA11
DDRA_MA7

DDRA_MA5

+2.5VS

for MEM_MB_RST# overshoot issue

DDRA_CKE1 5

DDRA_ALERT# 5

+3VS +VDDSPD

1 2

RD271 0_0402_5%@

1 2

RD272 0_0402_5%@

Layout Note: Place near JDDR1

+0.6VS

0.1U_0201_6.3V6-K

1

CD251

CD249

@

@

2

+2.5V

follow CRB 1pcs 1uf + 2pcs 0.1uf + 1pcs 180pf

1U_0402_6.3V6K

1

CD123

CD122

2

1

2

1

2

1

2

@

CD120

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CD250

CD124

MEM_MA_RST# 5

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

1

CD248

2

0.1U_0201_6.3V6-K

1

CC206

2

1

2

1

2

+VDDSPD

4.7U_0402_6.3V6M

180P_0402_50V8-J

3

+1.2V

JDDR1B

DDRA_MA3
DDRA_MA1

DDRA_CLK05
DDRA_CLK0#5

DDRA_PAR5

DDRA_BA15

DDRA_CS0#5

DDRA_MA14_WE#5

DDRA_ODT05

DDRA_CS1#5

DDRA_ODT15

APU_SMB_CLK7,35 APU_SMB_DATA 7,35

1

1

CD29

CD28

0.1U_0201_6.3V6-K

2

2

+1.2V

follow CRB 6pcs 0.1uffollow CRB 1pcs 4.7uf + 1pcs 0.1uf

0.1U_0201_6.3V6-K

1

CD16

2

+1.2V

1

CD261

@

2

10U_0603_6.3V6M

DDRA_CLK0 DDRA_CLK1
DDRA_CLK0#

DDRA_BA1

DDRA_CS0#
DDRA_MA14_WE#

DDRA_ODT0
DDRA_CS1#

DDRA_ODT1

DDRA_DQ33

DDRA_DQ32

DDRA_DQS#4
DDRA_DQS4

DDRA_DQ35

DDRA_DQ34

DDRA_DQ40

DDRA_DQ41

DDRA_DM5

DDRA_DQ46

DDRA_DQ47

DDRA_DQ49

DDRA_DQS#6
DDRA_DQS6

DDRA_DQ50

DDRA_DQ55

DDRA_DQ60

DDRA_DQ57

DDRA_DM7

DDRA_DQ63

APU_SMB_CLK APU_SMB_DATA

+2.5V

CD121

22P_0402_50V8-J

RF_NS@

RF

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

1

1

CD18

CD17

2

2

1

CD63

@

1

CD66

2

2

10U_0603_6.3V6M

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

DM4_n/DBl4_ n/NC

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_ n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

DM6_n/DBl6_ n/NC

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_ n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

261

0.1U_0201_6.3V6-K

1

CD21

2

1

2

22U_0603_6.3V6-M

VPP_2

GND_1

ARGOS_D4AS0-26001-1P60

ME@

0.1U_0201_6.3V6-K

1

CD22

2

1

CD19
22P_0402_50V8-J

RF@

2

1

2

CD20

CD67

22U_0603_6.3V6-M

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t
VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t
VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

0.1U_0201_6.3V6-K

1

2

132

A2

134
136
138
140
142
144

A0

146
148
150

BA0

152
154
156
158

A13

160
162
164
166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

Vtt

260

SA1

262

CD23

@

1

CD260
22P_0402_50V8-J

RF@

2

+1.2V

DDRA_MA2
MEM_MA_EVENT#

DDRA_CLK1#

DDRA_MA0

DDRA_MA10

DDRA_BA0
DDRA_MA16_RAS#

DDRA_MA15_CAS#
DDRA_MA13

DDRA0_SA2

DDRA_DQ37

DDRA_DQ36

DDRA_DM4

DDRA_DQ39

DDRA_DQ38

DDRA_DQ45

DDRA_DQ44

DDRA_DQS#5
DDRA_DQS5

DDRA_DQ42

DDRA_DQ43

DDRA_DQ53DDRA_DQ52

DDRA_DQ48

DDRA_DM6

DDRA_DQ54

DDRA_DQ51

DDRA_DQ56

DDRA_DQ61

DDRA_DQS#7
DDRA_DQS7

DDRA_DQ58

DDRA_DQ59DDRA_DQ62

DDRA0_SA0

DDRA0_SA1

LP2301ALT1G_SOT23-3

SUSP27,41

27P 25V J NPO 0201

0.1U_0201_6.3V6-K

1

1

CD58

EMC@

2

2

1

2

2

DDRA_DQ[0..63]

DDRA_DQS[0..7]

DDRA_DQS#[0..7]

DDRA_MA[0..13]

DDRA_DM[0..7]

QD1

CD59

@

CD12
22P_0402_50V8-J

RF@

D

S

13

G

2

@

0.1U_0201_6.3V6-K

1

CD60

EMC@

2

DDRA_DQ[0..63] 5

DDRA_DQS[0..7] 5

DDRA_DQS#[0..7] 5

DDRA_MA[0..13] 5

DDRA_DM[0..7] 5

MEM_MA_EVENT# 5

DDRA_CLK1 5
DDRA_CLK1# 5

DDRA_BA0 5

DDRA_MA16_RAS# 5

DDRA_MA15_CAS# 5

+VREF_CA

+0.6VS

+2.5VS+2.5V

27P 25V J NPO 0201

1

1

CD61

@

2

2

1

CD348
22P_0402_50V8-J

RF_NS@

2

0.1U_0201_6.3V6-K

CD62

@

1

2

0.1U_0201_6.3V6-K

1

CC211

2

CD349
22P_0402_50V8-J

RF_NS@

1

Swap Table

Net NamePin Name

DDRA_DQ6

DQ0

DDRA_DQ5

DQ1

DDRA_DQ2

DQ2

DDRA_DQ3

DQ3

DDRA_DQ4

DQ4

DDRA_DQ0

DQ5

DDRA_DQ1

DQ6

DDRA_DQ7

DQ7

DDRA_DQS#0

DQS#0

DDRA_DQS0

DQS0

DDRA_DQ13

DQ8

DDRA_DQ9

DQ9

DDRA_DQ14

DQ10

DDRA_DQ10

DQ11

DDRA_DQ12

DQ12

DDRA_DQ8

DQ13

DDRA_DQ15

DQ14

DDRA_DQ11

DQ15

DDRA_DQS#1

DQS#1

DDRA_DQS1

DQS1

DQ16

DDRA_DQ20

DQ17

DDRA_DQ21

DQ18

DDRA_DQ22

DQ19

DDRA_DQ19

DQ20

DDRA_DQ16

DQ21

DDRA_DQ17

DQ22

DDRA_DQ23

DQ23

DDRA_DQ18

DQS#2

DDRA_DQS#2

DQS2

DDRA_DQS2

DDRA_DQ28

DQ24

DDRA_DQ29

DQ25

DDRA_DQ31

DQ26

DDRA_DQ27

DQ27

DDRA_DQ24

DQ28

DDRA_DQ25

DQ29

DDRA_DQ30

DQ30

DDRA_DQ26

DQ31

DDRA_DQS#3

DQS#3

DDRA_DQS3

DQS3

DDRA_DQ33

DQ32

DDRA_DQ37

DQ33

DDRA_DQ34

DQ34

DDRA_DQ38

DQ35

DDRA_DQ32

DQ36

DDRA_DQ36

DQ37

DDRA_DQ35

DQ38

DDRA_DQ39

DQ39

DDRA_DQS#4

DQS#4

DDRA_DQS4

DQS4

DDRA_DQ44

DQ40

DDRA_DQ40

DQ41

DDRA_DQ47

DQ42

DDRA_DQ43

DQ43

DDRA_DQ41

DQ44

DDRA_DQ45

DQ45

DDRA_DQ46

DQ46

DDRA_DQ42

DQ47

DDRA_DQS#5

DQS#5

DDRA_DQS5

DQS5

DQ48

DDRA_DQ48

DQ49

DDRA_DQ49

DQ50

DDRA_DQ55

DQ51

DDRA_DQ50

DQ52

DDRA_DQ52

DQ53

DDRA_DQ53

DQ54

DDRA_DQ54

DQ55

DDRA_DQ51

DQS#6

DDRA_DQS#6

DQS6

180P_0402_50V8-J

1

2

RF

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS#7
DQS7

DDRA_DQS6

DDRA_DQ60
DDRA_DQ56
DDRA_DQ63
DDRA_DQ59
DDRA_DQ61
DDRA_DQ57
DDRA_DQ58
DDRA_DQ62
DDRA_DQS#7
DDRA_DQS7

SPD Address = A2H

5

4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Title

DDRIV SO-DIMM A

DDRIV SO-DIMM A

DDRIV SO-DIMM A

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date : She et o f

Date : She et o f

Date : She et o f

330ARR

330ARR

330ARR

1

14 52

14 52

14 52

1.0

1.0

1.0

5

Vinafix.com

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8

L2
M8
L8

K8
K7

K2

F3
G3
A7
B7

E2
E7

N2
N8

L3
L7
P9

M2

K3

T3

N9

P1

F1
H1
A2
D2
E3
A8
D8
E8
C9
H9

F9

12

RD116
240_04 02_1%

@

DRAM@

UD3

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD118

MT40A51 2M16HA08 3EA_F BGA96

240_04 02_1%

DRAM@

UD1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

WE_N/A14
CAS_N/A15
RAS_N/A16

CK_C
CK_T

CKE

LDQS_C
LDQS_T
UDQS_C

VDD10

UDQS_T

VDDQ1

NF/UDM_N/UDBI_N

VDDQ2

NF/LDM_N/LDBI_N

VDDQ3
VDDQ4

BA0

VDDQ5

BA1

VDDQ6
VDDQ7

ACT_N

VDDQ8

CS_N

VDDQ9

ALERT_N

VDDQ10

BG0

ODT

VREFCA

PAR

TEN

RESET_N

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ZQ

MT40A51 2M16HA08 3EA_F BGA96

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VPP1
VPP2

VREFCA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

@

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12

D D

RF

C C

B B

A A

DDRB_MA 14_WE #5
DDRB_MA 15_CAS #5
DDRB_MA 16_RAS #5

DDRB_C LK0#5
DDRB_C LK05

DDRB_C KE05

DDRB_B A05
DDRB_B A15

DDRB_A CT#5
DDRB_C S0#5
DDRB_A LERT#5

DDRB_B G05

DDRB_O DT05

DDRB_P AR5

1 2

MEM_MB_RST #5

1 2

DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_C LK0#
DDRB_C LK0

DDRB_C KE0

DDRB_D QS#0
DDRB_D QS0
DDRB_D QS#1
DDRB_D QS1

DDRB_D M1

DDRB_B A0
DDRB_B A1

DDRB_A CT#
DDRB_C S0#
DDRB_A LERT#

DDRB_B G0

DDRB_O DT0

DDRB_P AR

TEN1

RD25110K_04 02_5% D RAM@

MEM_MB_RST #

1

CD132

2

@

0.1U_0201_6.3V6-K

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_C LK0#
DDRB_C LK0

DDRB_C KE0

DDRB_D QS#4
DDRB_D QS4
DDRB_D QS#5
DDRB_D QS5

DDRB_D M5
DDRB_D M4

DDRB_B A0
DDRB_B A1

DDRB_A CT#
DDRB_C S0#
DDRB_A LERT#

DDRB_B G0

DDRB_O DT0

DDRB_P AR

RD25510K_04 02_5% D RAM@

TEN3

MEM_MB_RST #

1

CD161

2

@

0.1U_0201_6.3V6-K

DDRB_D Q3

G2

DDRB_D Q7

F7

DDRB_D Q2

H3

DDRB_D Q0

H7

DDRB_D Q6

H2

DDRB_D Q5

H8

DDRB_D Q1

J3

DDRB_D Q4

J7

DDRB_D Q11

A3

DDRB_D Q8

B8

DDRB_D Q15

C3

DDRB_D Q9

C7

DDRB_D Q10

C2

DDRB_D Q13

C8

DDRB_D Q14

D3

DDRB_D Q12

D7

+1.2V

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

NC

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

+1.2V

DRAM@

DDRB_D Q39
DDRB_D Q35
DDRB_D Q34
DDRB_D Q37
DDRB_D Q38
DDRB_D Q36
DDRB_D Q32
DDRB_D Q33
DDRB_D Q47
DDRB_D Q40
DDRB_D Q46
DDRB_D Q44
DDRB_D Q42
DDRB_D Q45
DDRB_D Q43
DDRB_D Q41

CD234

DRAM@

+VREF_C A

1

1

DRAM@

CD189

CD188

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

+VREF_C A

1

1

CD235

DRAM@

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

4

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7

M3

T2

M7

T8

L2

M8

L8

K8
K7

K2

F3
G3
A7
B7

E2
E7

N2
N8

L3
L7
P9

M2

K3

T3

N9

P1

F1
H1
A2
D2
E3
A8
D8
E8
C9
H9

F9

12

RD117
240_04 02_1%

DRAM@

UD4

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD119

MT40A51 2M16HA08 3EA_F BGA96

240_04 02_1%

@

DRAM@

UD2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

WE_N/A14
CAS_N/A15
RAS_N/A16

CK_C
CK_T

CKE

LDQS_C
LDQS_T
UDQS_C
UDQS_T

NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N

BA0
BA1

ACT_N
CS_N
ALERT_N

BG0

ODT

PAR

TEN

RESET_N

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ZQ

MT40A51 2M16HA08 3EA_F BGA96

@

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_C LK0#
DDRB_C LK0

DDRB_C KE0

DDRB_D QS#2
DDRB_D QS2
DDRB_D QS#3
DDRB_D QS3

DDRB_D M3
DDRB_D M2DDRB_D M0

DDRB_B A0
DDRB_B A1

DDRB_A CT#
DDRB_C S0#

+2.5V

1

1

CD203

CD202

2

2

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

+2.5V

1

1

CD237

CD236

2

2

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

1 2

1 2

DDRB_A LERT#

DDRB_B G0

DDRB_O DT0

DDRB_P AR

TEN2

RD25310K_04 02_5% DRAM@

MEM_MB_RST #

1

CD160

2

@

0.1U_0201_6.3V6-K

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_C LK0#
DDRB_C LK0

DDRB_C KE0

DDRB_D QS#7
DDRB_D QS7
DDRB_D QS#6
DDRB_D QS6

DDRB_D M6
DDRB_D M7

DDRB_B A0
DDRB_B A1

DDRB_A CT#
DDRB_C S0#
DDRB_A LERT#

DDRB_B G0

DDRB_O DT0

DDRB_P AR

TEN4

RD25710K_04 02_5% D RAM@

MEM_MB_RST #

1

CD162

2

@

0.1U_0201_6.3V6-K

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VREFCA

3

DDRB_D Q19

G2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VPP1
VPP2

VREFCA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDD10

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

DDRB_D Q23

F7

DDRB_D Q22

H3

DDRB_D Q17

H7

DDRB_D Q18

H2

DDRB_D Q21

H8

DDRB_D Q20

J3

DDRB_D Q16

J7

DDRB_D Q27

A3

DDRB_D Q29

B8

DDRB_D Q31

C3

DDRB_D Q25

C7

DDRB_D Q26

C2

DDRB_D Q28

C8

DDRB_D Q30

D3

DDRB_D Q24

D7

+1.2V

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

NC

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

+1.2V

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9

DRAM@

K9
M9

T7

DRAM@

DDRB_D Q59
DDRB_D Q57
DDRB_D Q58
DDRB_D Q61
DDRB_D Q63
DDRB_D Q56
DDRB_D Q62
DDRB_D Q60
DDRB_D Q50
DDRB_D Q52
DDRB_D Q55
DDRB_D Q48
DDRB_D Q54
DDRB_D Q49
DDRB_D Q51
DDRB_D Q53

CD238

+VREF_C A

1

1

CD230

CD231

2

2

DRAM@

1000P_0201_50V7-K

+1.2V

CD266

CD267

47P_0201_25V8-J

1

EMC_NS@

2

+VREF_C A

1

1

CD239

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

+2.5V

1

1

CD232

CD233

2

2

DRAM@

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CD268

CD269

CD270

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

1

1

1

EMC@

EMC@

2

CD240

DRAM@

1

EMC@

EMC@

2

2

2

+2.5V

1

1

CD241

DRAM@

2

2

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

2/22: change to K back for materil stock risk, and this change
has conf i r m t o A MD

CD273

CD274

CD272

CD271

27P 25V J NPO 0201

EMC@

47P_0201_25V8-J

27P 25V J NPO 0201

27P 25V J NPO 0201

1

1

1

1

EMC_NS@

EMC@

EMC@

2

2

2

2

2

DDRB_D Q[0..63]

DDRB_D QS[0..7]

DDRB_D QS#[0..7]

DDRB_MA [0..13]

DDRB_D M[0..7]

DDRB_D Q[0..63] 5

DDRB_D QS[0..7] 5

DDRB_D QS#[0..7] 5

DDRB_MA [0..13] 5

DDRB_D M[0..7] 5

CD163 change from K to J

DDRB_C LK0#
DDRB_C LK0

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_A CT#

DDRB_O DT0
DDRB_C S0#
DDRB_C KE0

DDRB_B A0
DDRB_B A1

DDRB_B G0
DDRB_P AR

DDRB_A LERT#

CD277

CD276

CD275

47P_0201_25V8-J

27P 25V J NPO 0201

47P_0201_25V8-J

1

1

EMC_NS@

EMC_NS@

2

2

Layout Note: Place near DRAM

27P 25V J NPO 0201

[email protected] V

1

EMC@

+1.2V

2

follow SCL 2 0pcs 0.22uf

0.22U_0201_6.3V6-K

1

CD155

CD154

2

DRAM@

[email protected] V

+1.2V

0.22U_0201_6.3V6-K

1

CD174

CD173

2

DRAM@

+1.2V

0.22U_0201_6.3V6-K

1

CD218

CD215

@

@

2

+0.6VS

follow SCL 1 0pcs 0.22uf

0.22U_0201_6.3V6-K

1

CD148

CD146

2

DRAM@

+0.6VS +0.6VS

0.22U_0201_6.3V6-K

1

CD259

CD252

@

@

2

DRAM@

DRAM@

DRAM@

0.22U_0201_6.3V6-K

1

CD142

2

0.22U_0201_6.3V6-K

1

CD169

2

0.22U_0201_6.3V6-K

1

CD212

@

2

0.22U_0201_6.3V6-K

1

CD139

2

0.22U_0201_6.3V6-K

1

2

DRAM@

DRAM@

DRAM@

1 2

RD122 39_0402 _5%DRAM@

1 2

RD123 39_0402 _5%DRAM@

1 2

RD148 39_0402 _5%DRAM@

1 2

RD149 39_0402 _5%DRAM@

1 2

RD124 39_0402 _5%DRAM@

1 2

RD125 39_0402 _5%DRAM@
RD126 39_0402 _5%DRAM@

1 2
1 2

RD127 39_0402 _5%DRAM@

1 2

RD128 39_0402 _5%DRAM@

1 2

RD129 39_0402 _5%DRAM@

1 2

RD130 39_0402 _5%DRAM@
RD131 39_0402 _5%DRAM@

1 2
1 2

RD132 39_0402 _5%DRAM@

1 2

RD133 39_0402 _5%DRAM@

1 2

RD134 39_0402 _5%DRAM@

1 2

RD135 39_0402 _5%DRAM@

1 2

RD138 39_0402 _5%DRAM@

1 2

RD139 39_0402 _5%DRAM@

1 2

RD140 39_0402 _5%DRAM@

RD144 39_0402 _5%DRAM@

1 2

1 2

RD147 39_0402 _5%DRAM@

1 2

RD145 39_0402 _5%DRAM@

1 2

RD141 39_0402 _5%DRAM@

1 2

RD142 39_0402 _5%DRAM@
RD143 39_0402 _5%DRAM@

1 2

1 2

RD146 39_0402 _5%DRAM@
RD275 39_0402 _5%DRAM@

1 2

1 2

RD86 1K_ 0402_ 1%DRA M@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD127

CD141

2

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD167

CD165

2

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD211

@

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD201

CD138

2

2

2

DRAM@

DRAM@

1

CD263
22P_04 02_50V 8-J

RF_NS@

2

0.22U_0201_6.3V6-K

CD152

0.22U_0201_6.3V6-K

CD172

+1.2V

0.22U_0201_6.3V6-K

CD245

1

CD264
22P_04 02_50V 8-J

RF_NS@

2

1

2

DRAM@

1

2

DRAM@

1

CD133
22P_04 02_50V 8-J

RF_NS@

2

1

2

DRAM@

+0.6VS

+1.2V

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD150

2

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD171

2

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD246

2

DRAM@

1

DRAM@

1 2

CD163 0.1 U_0402_ 10V7K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD158

CD143

CD137

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD166

CD168

CD175

2

2

DRAM@

DRAM@

1

CD153
22P_04 02_50V 8-J

RF_NS@

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD244

CC205

DRAM@

DRAM@

1

2

CD242

CD243

2

2

DRAM@

+2.5V

1

CD265
22P_04 02_50V 8-J

RF_NS@

2

180P_0402_50V8-J

DRAM@

DRAM@

DRAM@

+1.2V

0.22U_0201_6.3V6-K

1

2

0.22U_0201_6.3V6-K

1

2

0.22U_0201_6.3V6-K

1

2

Swap Table

Pin Name Net Name

DQ0

DDRB_DQ3

DQ1

DDRB_DQ6

DQ2

DDRB_DQ2

DQ3

DDRB_DQ0

DQ4

DDRB_DQ7

DQ5

DDRB_DQ5

DQ6

DDRB_DQ4

DQ7

DDRB_DQ1

DQS#0

DDRB_DQS#0

DQS0

DDRB_DQS0

UD1

DDRB_DQ9

DQ8

DDRB_DQ11

DQ9

DDRB_DQ12

DQ10

DDRB_DQ8

DQ11

DDRB_DQ15

DQ12

DDRB_DQ13

DQ13

DDRB_DQ14

DQ14

DDRB_DQ10

DQ15

DDRB_DQS#1

DQS#1

DDRB_DQS1

DQS1

UD1

DQ16

DDRB_DQ7

DQ17

DDRB_DQ3

DQ18

DDRB_DQ4

DQ19

DDRB_DQ0

DQ20

DDRB_DQ6

DQ21

DDRB_DQ5

DQ22

DDRB_DQ2

DQ23

DDRB_DQ1

DQS#2

DDRB_DQS#2

DQS2

DDRB_DQS2

UD2

DQ24

DDRB_DQ15

DQ25

DDRB_DQ11

DQ26

DDRB_DQ12

DQ27

DDRB_DQ8

DQ28

DDRB_DQ13

DQ29

DDRB_DQ9

DQ30

DDRB_DQ14

DQ31

DDRB_DQ10

DQS#3

DDRB_DQS#3

DQS3

DDRB_DQS3

UD2

DQ32

DDRB_DQ6

DQ33

DDRB_DQ7

DQ34

DDRB_DQ2

DQ35

DDRB_DQ1

DQ36

DDRB_DQ5

DQ37

DDRB_DQ3

DQ38

DDRB_DQ4

DQ39

DDRB_DQ0

DQS#4

DDRB_DQS#4

DQS4

DDRB_DQS4

UD3

DQ40

DDRB_DQ9

DQ41

DDRB_DQ15

DQ42

DDRB_DQ12

DQ43

DDRB_DQ14

DQ44

DDRB_DQ11

DQ45

DDRB_DQ13

DQ46

DDRB_DQ10

DQ47

DDRB_DQ8

DQS#5

DDRB_DQS#5

DQS5

DDRB_DQS5

UD3

DQ48

DDRB_DQ11

DQ49

DDRB_DQ13

DQ50

DDRB_DQ8

DQ51

DDRB_DQ14

DQ52

DDRB_DQ9

DQ53

DDRB_DQ15

DQ54

DDRB_DQ12

DQ55

DDRB_DQ10

DQS#6

DDRB_DQS#7

DQS6

DDRB_DQS7

UD4

DQ56

DDRB_DQ5

DQ57

DDRB_DQ1

DQ58

DDRB_DQ2

DQ59

DDRB_DQ0

DQ60

DDRB_DQ7

DQ61

DDRB_DQ3

DQ62

DDRB_DQ6

DQ63

DDRB_DQ4

DQS#7

DDRB_DQS#6

DQS7

DDRB_DQS6

UD4

5

4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

Title

DDRVI MD

DDRVI MD

DDRVI MD

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

330ARR

330ARR

330ARR

15 52

15 52

15 52

1.0

1.0

1.0

5

Vinafix.com

D D

4

3

2

1

Power-Up/Down Sequence

"Topaz" has the following requirements with regards to power-supply sequencing to
avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/μ s.
It is recommended that the 3.3-V rail ramp up first.
The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μ s
before VDDC, VDDCI, and VMEMIO start to ramp up.
The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μ s).
For power down, reversing the ramp-up sequence is recommended.

C C

0 ~ 20ms

VDDR3(+3VGS)

0 ~ 20ms

VRAM ID config

GPU

8Gb GDDR5

R17M-P1 -50

R18M-M2 -60

256M x 32

(UV3/UV 4)

8Gb GDDR5

256M x 32

(UV3/UV 4)

Memory Type

Samsung

K4G80325FB-HC28 [email protected]

Hynix

H5GC8H24MJR-R0C [email protected]

Micron

MT51J256M32HF-70:A [email protected]

Samsung

K4G80325FB-HC28 [email protected]

Hynix

H5GC8H24MJR-R0C [email protected]

Micron

MT51J256M32HF-70:A [email protected]

BOARD_CO NFIG[2: 0]

DBGDATA_ [5..3]

000

001

010

NA

NA

NA

VRAM ID

PS_3[3: 1]

NA

NA

NA

000

001

010

Stuff R

RV1307

RV1307 R V1297RV1304

RV1307 R V1298

RV1415( NC) RV1418(4 .75K)

RV1415(8 .45K) RV1 418(2K)

RV1415(4 .53K) RV1 418(2K)

RV1298RV1304

RV1303

VDD_CT(+1.8VGS)

PCIE_VDDC(+0.95VGS)

10us min.

B B

VDDR1(+1.35VGS)

VDDC/VDDCI(+VGA_CORE)

PERSTb(GPU_RST#)

100ms min.

100us min.

REFCLK(CLK_PCIE_VGA)

A A

Title

Title

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

16 52

16 52

16 52

1.0

1.0

1.0

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2016/08/16

2016/08/16

2016/08/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2017/08/15

2017/08/15

2017/08/15

5

Vinafix.com

4

3

2

1

PCIE_CTX_C_GRX_P[0..7]4

PCIE_CTX_C_GRX_N[0..7]4

D D

UV1B

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6

C C

CLK_PCIE_GPU8
CLK_PCIE_GPU#8

+3VALW

+3VGS

B B

1 2

RV1430 0_0402_5%@

1 2

RV1429 0_0402_5%@

PXS_RST#8

PLT_RST#7,32,35

+3V_GATE

PXS_RST#

PLT_RST#

1 2

RV1236 0_0402_5%@

+3V_GATE

5

UV5

1

VCC

IN1

2

OUT

IN2

GND

MC74VHC1G08DFT2G_SC 70-5

3

PX@

1

CV122

0.1U_0201_6.3V6-K

@

2

4

12

PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7 PCIE_CRX_C_GTX_P7
PCIE_CTX_C_GRX_N7

CLK_PCIE_GPU
CLK_PCIE_GPU#

GPU_RST#

RV1227
100K_0402_5%

PX@

AT41
AT40

AR41
AR40

AP41
AP40

AM41
AM40

AL41
AL40

AK41
AK40

AJ41
AJ40

AH41
AH40

AV33
AU33

symbol2

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_REFCLKP
PCIE_REFCLKN

REV 0.91

216-0905018-C3_FC BGA769

@

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PERSTB

PCIE_ZVSS

PX_EN

PCIE_CRX_C_GTX_P0

AV35

PCIE_CRX_C_GTX_N0

AU35

PCIE_CRX_C_GTX_P1

AU38

PCIE_CRX_C_GTX_N1

AU39

PCIE_CRX_C_GTX_P2

AR37

PCIE_CRX_C_GTX_N2

AR38

PCIE_CRX_C_GTX_P3

AN37

PCIE_CRX_C_GTX_N3

AN38

PCIE_CRX_C_GTX_P4

AL37

PCIE_CRX_C_GTX_N4

AL38

PCIE_CRX_C_GTX_P5

AJ37

PCIE_CRX_C_GTX_N5

AJ38

PCIE_CRX_C_GTX_P6

AG37

PCIE_CRX_C_GTX_N6 PCIE_CRX_GTX_N6

AG38

AE37

PCIE_CRX_C_GTX_N7

AE38

GPU_RST#

AV41

PX_EN

AC41

PX_EN: On/off regulator control signal for BACO mode, internal pull down.
High(3.3V)--switches the regulators off. (enter BACO mode)
Low(0V)--switches the regulators on. (Default)
Can be left unconnected if not used.

PCIE_ZVSS

AU41

VR_VGA_PWRGD51

GPU_RST# 18

1 2

RV1226 1K_0402_5%@

1 2

RV1228 200_0402_1%PX@

GPU_RST#

VR_VGA_PWRGD

VR_VGA_PWRGD

CV1 0.22U_020 1_6.3V6-KPX@
CV2 0.22U_020 1_6.3V6-KPX@

CV3 0.22U_020 1_6.3V6-KPX@
CV4 0.22U_020 1_6.3V6-KPX@

CV5 0.22U_020 1_6.3V6-KPX@
CV6 0.22U_020 1_6.3V6-KPX@

CV7 0.22U_020 1_6.3V6-KPX@
CV8 0.22U_020 1_6.3V6-KPX@

CV141 0 .22U_0201_6.3V6-KR5R7@
CV138 0 .22U_0201_6.3V6-KR5R7@

CV143 0 .22U_0201_6.3V6-KR5R7@
CV136 0 .22U_0201_6.3V6-KR5R7@

CV140 0 .22U_0201_6.3V6-KR5R7@
CV142 0 .22U_0201_6.3V6-KR5R7@

CV137 0 .22U_0201_6.3V6-KR5R7@
CV139 0 .22U_0201_6.3V6-KR5R7@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

2

3

RV1404 0_0402_5%@

DV6

LBAT54AWT1G_SOT 323-3

PX@

1 2

1

VGA_PWROK

PCIE_CRX_GTX_P[0..7] 4

PCIE_CRX_GTX_N[0..7] 4

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

VGA_PWROK 51

DGPU_PWROK 8

Need confirm if can NC UV5/RV1227

A A

and stuff RV1236--Brooks 0708

5

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

4

2016/08/16

2016/08/16

2016/08/16

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/08/15

2017/08/15

2017/08/15

2

Titl e

R17M-P1-50_PCIE

R17M-P1-50_PCIE

R17M-P1-50_PCIE

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Friday, March 23, 2018

Friday, March 23, 2018

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

17 52

17 52

17 52

1.0

1.0

1.0

5

Vinafix.com

+3VGS +3VGS

RV1251 0_0402_5%@

1 2

1

CV11
1U_0402_6.3V6K

PX@

2

D D

EC_SMB_CK3
EC_SMB_DA3

GPU_SVC51
GPU_SVD51
GPU_SVT51

C C

+1.8VGS

RV1428
0_0402_5%

1 2

1U_0402_6.3V6K

B B

+1.8VGS

RV1229 10K_0402_5%PX@
RV1230 10K_0402_5%PX@

RV1234 0_0402_5%@

RV1334 0_0402_5%@
RV1336 0_0402_5%@

RV1421 0_0402_5%@
RV1422 0_0402_5%@
RV1423 0_0402_5%@

+1.8VGS

1 2

RV1300 1K_0402_5%

1 2

RV1301 1K_0402_5%

@

AM13

1

J8

CV18

PX@

2

J7

N38

1 2
1 2

1 2

1 2
1 2

1 2
1 2
1 2

R17@

R17@

UV1J

TSVDD

TEMPIN0

TEMPINRETURN

TS_A

216-0905018-C3_FCBGA769

@

GPU_SMB_CLK
GPU_SMB_DATA

GPU_SVC_R
GPU_SVD_R
GPU_SVT_R

TEST_PG
TEST_PG_BACO

12

RV1410

10K_0402_5%

R18@

Reserve for
R18M-M2-60

symbol10

N35

DPLUS

N34

DMINUS

U38

GPIO_28_FDO

REV 0.91

Reserve for R18M-M2-60
to enable MLPS

UV1A

BP_0

AA38

BP_1

BP_0

AA37

BP_1

B2

TEST6 TESTEN

TEST6

216-0905018-C3_FCBGA769

@

Reserve

GPU_RST#

GPU_RST#17

A A

GPU_GPIO19

21

DV5

SDM10U45LP-7_DFN1006-2-2

1 2

RV1385

@

47K_0402_5%

@

+VDD_33

GPU_GPIO28_FDO

RV1343

10K_0402_5%

R18@

symbol1

JTAG_TDO

JTAG_TDI
JTAG_TMS
JTAG_TCK

TESTEN

JTAG_TRSTB

REV 0.91

RV1381

12

UV1E

symbol5

AM31

VDD_33

GPIO_5_REG_HOT_AC_ BATT

GPIO_10_ROMSCK

GPIO_16_8P_DETECT

GPIO_17_THERMAL_INT

AC35

SCL

AC34

AW40
AW41

AU17
AV17
AR17

AN34
AP31

BA13

RV1384
100K_0402_5%

@

GPIO_22_ROMCSB

SDA

SMBCLK
SMBDAT

GPIO_SVC
GPIO_SVD
GPIO_SVT

DDCVGACLK
DDCVGADATA

AY13

TEST_PG
TEST_PG_BACO

K41

RSVD#K41

R34

RSVD#R34

REV 0.91

216-0905018-C3_FCBGA769

@

GPU_SMB_CLK

12

GPU_SMB_DATA

Need confirm if can NC for
CNL-U GT0 --Brooks0710

GPU_JTAG_TDO

AF41

GPU_JTAG_TDI

AD40

GPU_JTAG_TMS

AD41

GPU_JTAG_TCK

AE41

AE40

GPU_JTAG_TRST#

AF40

1 2

@

2.2K_0402_5%

GPIO_0
GPIO_1
GPIO_2

GPIO_6_TACH

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_11
GPIO_12
GPIO_13

GPIO_14_HPD2

GPIO_15

GPIO_18_HPD3

GPIO_19_CTF

GPIO_20
GPIO_21

GPIO_29

GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD

GENERICE_HPD4

GENERICF_HPD5

GENERICG

CLKREQB

WAKEB

DIGON

BL_ENABLE

BL_PWM_DIM

HSYNC
VSYNC

SWAPLOCKA
SWAPLOCKB

GENLK_CLK

GENLK_VSYNC

RV1321

47K_0402_5%

PX@

1

1

1

1

2

B

@

1

2

0.1U_0201_6.3V6-K

CV120

W40
AA40
AA35

AA34
U35

AP25
AM25
AM27
W41
Y40
Y41
AU21
AA41
U34
R37
AV25
R38
AB40
AB41
AP27
W37
W38
BA38
AV29
AU31
AV31
AU25
AV23
AM29

AV21

HPD1

AV40
AU40

AC40

AC37
AC38

W34
W35

AG34
AE34
AR29
AP29

12

TV48 PAD@
TV49 PAD@
TV50 PAD@
TV51 PAD@

RV1380

C

QV7
MMBT3904WH_SOT323-3

@

E

3 1

12

Reserve for R18M-M2-60

GPU_GPIO0

RV1424 0_0402_5%R18@

GPU_GPIO2

DV1

GPU_GPIO5
GPU_GPIO6 GPU_GPIO6

RV1257 0_0402_5%R17@

GPU_GPIO8

RV1261 33_0402_5%@

GPU_GPIO9

RV1264 33_0402_5%@

GPU_GPIO10

RV1265 33_0402_5%@

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
GPU_EDP_HPD
GPU_GPIO15 GPU_GPIO15

GPU_GPIO18
GPU_GPIO19
GPU_GPIO20 GPU_GPIO20
GPU_GPIO21

1

GPU_GPIO22

RV1277 33_0402_5%@

GPU_GPIO29 GPU_GPIO29

1

GENERICA
PS_1

PS_2
PS_3
GENERICE_HPD4
GENERICF_HPD5
PS_0

GPU_HDMI_HPD GPU_HDMI_HPD

GPU_CLKREQ#_R
GPU_WAKE#

1

TV60 PAD@

RV20 0_0402_5%@

1

TV67 PAD@

1

TV68 PAD@

1

TV69 PAD@

GPU_HSYNC
GPU_VSYNC

RV1335

2

G

47K_0402_5%

PX@

S

61

QV1A

PX@

D

2N7002KDWH_SOT363-6

QV1B

2N7002KDWH_SOT363-6

+3VGS

12

12

RV1233

5.11K_0402_1%

@

12

12

RV1235

1K_0402_5%

PX@

1 2

@

WRST# 39

0_0402_5%

5

4

1 2

RB751V-40_SOD323-2

1 2

1 2
1 2
1 2

TV57 PAD@

1 2

TV59 PAD@

+3VGS

G

S

2N7002KW_SOT323-3

1 2

GPU_VR_HOT#

12

PX@

VGA_AC_DET 39

GPU_VR_HOT# 39,51

GPU_ROMSO
GPU_ROMSI
GPU_ROMSCK

GPU_ROMCS# GPU_GPIO22

2

QV2

@

13

D

GPU_CLKREQ# 8

RV1247 5.1K_0402_5%@

1 2

1 2

RV1281 5.1K_0402_5%@

RV1246 10K_0402_5%PX@

1 2
1 2

RV1405 10K_0402_5%R17@

1 2

RV1252 5.1K_0402_5%@

1 2

RV1254 5.1K_0402_5%@

1 2

RV1270 5.1K_0402_5%@

1 2

RV1272 5.1K_0402_5%@

1 2

RV1274 5.1K_0402_5%@

RV1287 5.1K_0402_5%@

1 2

RV1283 5.1K_0402_5%R17@

1 2

1 2

RV1258 5.1K_0402_5%@

1 2

RV1279 5.1K_0402_5%R17@

1 2

RV1302 10K_0402_5%@

HSYNC/VSYNC: If use dGPU for display output, this 2
pins need pull up to VDD_33 --Brooks 0718

1 2

RV1266 5.1K_0402_5%@

1 2

RV1268 5.1K_0402_5%@

Need confirm the BOM Structure --Brooks0727

GPU_GPIO0

GPU_GPIO2

GPU_GPIO5

GPU_GPIO8
GPU_GPIO9

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
GPU_EDP_HPD

GPU_GPIO18
GPU_GPIO19

GENERICE_HPD4
GENERICF_HPD5

GPU_CLKREQ#_R

GPU_HSYNC
GPU_VSYNC

Need confirm the BOM Structure --Brooks0726

+3VGS+3VGS +1.8VGS

34

D

PX@

EC_SMB_CK3 6,39

EC_SMB_DA3 6,39

UV1F

REV 0.91

216-0905018-C3_FCBGA769

@

4

symbol6

G

5

S

RV1238
10K_0402_5%

PX@

RV1239
10K_0402_5%

@

XTALIN

XTALOUT

PLLCHARZ_L

PLLCHARZ_H

ANALOGIO

UV1K

symbol11

DBGDATA_0
DBGDATA_1
DBGDATA_2
DBGDATA_3
DBGDATA_4
DBGDATA_5
DBGDATA_6
DBGDATA_7
DBGDATA_8

DBGDATA_9
DBGDATA_10
DBGDATA_11
DBGDATA_12
DBGDATA_13
DBGDATA_14
DBGDATA_15

REV 0.91

216-0905018-C3_FCBGA769

@

GPU_XTALIN

BA39

GPU_XTALOUT

AY39

PLLCHARZ_L

AV15

PLLCHARZ_H

AU15

AY38

ANALOGIO

L40
L41
M40
M41
N40
N41
P40
P41
R40
R41
T40
T41
U40
U41
V40
V41

1 2

RV1337

0_0402_5%

1
1

1 2

RV1344 16.2K_0402_1%@

DBGDATA_0
DBGDATA_1
DBGDATA_2
DBGDATA_3
DBGDATA_4
DBGDATA_5
DBGDATA_6
DBGDATA_7
DBGDATA_8
DBGDATA_9
DBGDATA_10
DBGDATA_11
DBGDATA_12
DBGDATA_13
DBGDATA_14
DBGDATA_15

R17@

SSON#_CLKGEN

CLK_100M_CLKGEN

TV42 PAD@
TV43 PAD@

1

TV24 PAD@

1

TV25 PAD@

1

TV26 PAD@

1

TV27 PAD@
TV28 PAD@

1
1

TV29 PAD@

1

TV30 PAD@

1

TV31 PAD@

3

RV1248 5.1K_0402_5%@

1 2

1 2

RV1282 5.1K_0402_5%@

1 2

RV1253 5.1K_0402_5%@

1 2

RV1255 5.1K_0402_5%@

1 2

RV1271 5.1K_0402_5%@

1 2

RV1273 5.1K_0402_5%@

1 2

RV1275 5.1K_0402_5%R17@

1 2

RV1312 10K_0201_5%R17@
RV1288 5.1K_0402_5%@

1 2

1 2

RV1316 10K_0201_5%R17@

1 2

RV1419 10K_0402_5%PX@
RV1284 5.1K_0402_5%@

1 2

1 2

RV1259 5.1K_0402_5%R17@

1 2

RV1280 5.1K_0402_5%@

1 2

RV1317 10K_0201_5%R17@
RV1318 10K_0201_5%R17@

1 2

1 2

RV1309 10K_0201_5%R17@

1 2

RV1313 10K_0402_5%@

1 2

RV1267 5.1K_0402_5%@

1 2

RV1269 5.1K_0402_5%@

+1.8VGS

1 2

RV1285 5.1K_0402_5%R17@

RV1289 5.1K_0402_5%R17@

1 2

1 2

RV1293 5.1K_0402_5%R17@

1 2

RV1297 5.1K_0402_5%@

1 2

RV1303 5.1K_0402_5%@

1 2

RV1306 5.1K_0402_5%@

RV1310 5.1K_0402_5%R17@

1 2

1 2

RV1314 5.1K_0402_5%@

UV10

6

VSS

5

SSCLK2/REFCLK_D/OE1/FSEL/SSEL/SSON#/PD#

4

SSCLK1/REFCLK/FSEL/SSEL/SSON#/OE2

SI51214-A1FAGMR_TDFN6_1P2X1P4

R17@

GPU_XTALIN

GPU_XTALOUT

1 2

RV1341
0_0402_5%

R18@

RV1342
0_0402_5%

R18@

1 2

3

2

0

1

0

0

0

1

0

1

00

111

01

1

Issued Date

Issued Date

Issued Date

GPU Default

0
(Internal pulldown)

1
(Internal pull-up)

0
(Internal pulldown)

0
(Internal pulldown)

101
(Internal pull-up
/pull-down)

0
(Internal pulldown)

0
(Internal pulldown)

1
(Internal pull-up)

0
(Internal pulldown)

0
(Internal pulldown)

0
(Internal pulldown)

0
(Internal pulldown)

0
(Internal pulldown)

SVC

0

0

1

1

R17@

2

CV16

0.1U_0201_6.3V6-K

Clock SS

SS Off

SS On0

RECOMMENDED SET TINGS
0 = PULL-DOWN TO GND
1 = PULL-UP TO POWER
X = DESIGN DEPENDENT
NA = NOT APPLICABLE

Recommended
Settings

productio n.

Must default to 0 for
productio n.

X
(Strap the address to
0x41 if no conflict)

SVD

Output Voltage

0 1.1 V

1

0

1

R17@

LV1

1 2

BLM15PD121SN1D_2P

1

CV17
10U_0603_6.3V6M

R17@

2

5.1K_0402_5%

SSON#_CLKGEN

5.1K_0402_5%

2

CONFIGURATION STRAPS R17M-P1-50

Any extern al circuit using these pins m ust no t conflict with the logic level
required by the strap after power up until PCIe reset gets de-asserted.

Pin NameStrap Name

GPIO_0TX_HALF_SW ING

BIF_GEN3 _EN_A

GPIO_2

GPIO_8

BIF_CLK_PM _EN

_ROMSO

GPIO_9

Reserv ed Must default to 0 for

_ROMSI

GPIO_13

ROM_CO NFIG

GPIO_12

[2:0]

GPIO_11

GPIO_20TX_DEEMPH_EN

GPIO_22

BIOS_ROM_ EN

_ROMCSB

GPIO_29BIF_VGA_ DIS

HSY NC

Special Usage [1]

VSYN C

Special Usage [0]

DBGDATA_ 2

AUD_POR T

DBGDATA_ 1

_CONN[ 2:0]

DBGDATA_ 0

DBGDATA_ 5

BOARD _CONFI G

DBGDATA_ 4

[2:0]

DBGDATA_ 3

SMBUS_A DDR

DBGDATA_ 7

[1:0]

DBGDATA_ 6

Note: To chan ge the straps from the default values, use pull-up or pull-down resistors of

5.1Kohm (5%) o n the PCB

DBGDATA_0

RV1286 5.1K_0402_5%@

DBGDATA_1

RV1290 5.1K_0402_5%@

DBGDATA_2

RV1294 5.1K_0402_5%@

DBGDATA_3

RV1298 5.1K_0402_5%@

DBGDATA_4

RV1304 5.1K_0402_5%@

DBGDATA_5

RV1307 5.1K_0402_5%@

DBGDATA_6

RV1311 5.1K_0402_5%@

DBGDATA_7

RV1315 5.1K_0402_5%@

VDD_CLKGEN

1

VDD

XTALIN_CLKGEN

2

XIN/CLKIN

XTALOUT_CLKGEN

3

XOUT

XTALIN

RV1340

1M_0402_5%

XTALOUT

@

CV20

2

1

YV1

PX@

12

OSC1

GND1

OSC23GND2

4

27MHZ_10PF_7V27000050

CV19

Description

Controls the transmitter full/half swing mode.
0: The transmitter fullswing is enabled.
1: The transmitter halfswing is enabled.
PCIe Gen3 capability.
1: P CIe Gen3 is supported.
0: P CIe Gen3 is not supported.
0: T he CLKREQB power management
capability is disabled.
1: T he CLKREQB power management
capability is enabled.

Reserv ed

If BIOS_ROM_EN = 1, defines the ROM type.
If BIOS_ROM_EN = 0, def ines the primary
memory aperture size.

Reserv edGPIO_ 15Rese rved

PCI E xpress transmitter de-emphasis enable
0: Tx de-emphasis disabled.
1: Tx de-emphasis enabled.
Enable external BIOS ROM device.
0: Disable external BIOS ROM device.
1: Enable external BIOS ROM device.
0: VGA Co ntroller capacity enabled.
1: The device will not be recognized as the
system's VGA controller(for headless designs)

Special usage

Determine the maximum number of digital
display audio endpoints that will be
presented to the OS and user.
111: No usable endpoints
110: One usable endpoint
101: Two usable endpoints
100: Three usable endpoints
011: Four usable endpoints
010: Five usable endpoints
001: Six usable endpoints
000: All endpoints are usable

Provides an option to specif y certain
board-level specifics to the VBIOS o r driver.

Provide a strap option to change the SMBUS
slave address o f the GPU.
00: 0x40
01: 0x41
10: 0x42
11: 0x43

1 2

12P_0201_25V8-J

1 2

12P_0201_25V8-J

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

PX@

PX@

RV1425

RV1426

000 = Samsung 8Gb
001 = Hynix 8Gb
010 = M icron 8Gb

1 2

R17@

0_0201_5%

1 2

R17@

0_0201_5%

001 = 256MB

XTALIN

XTALOUT

SSON#

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1.0 V

0.9 V

0.8 V1

0

X

1

X

1

X

X

X

X

X

+1.8VGS

+1.8VGS

RV1338

R17@

RV1339

@

2016/08/16

2016/08/16

2016/08/16

12

12

CONFIGURATION STRAPS R18M-M2-60

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE
GPIOS ARE USED, T HEY MUST NOT CONFLICT DURING RESET

PS_0[1]
PS_0[2]
PS_0[3]

PS_0[4] N/A

PS_0[5]

PS_1[1]

PS_1[2]

PS_1[3]

PS_1[4]

PS_1[5]

PS_2[1]

PS_2[2]

PS_2[3]

PS_2[4]

PS_2[5]

PS_3[1]
PS_3[2]
PS_3[3]

PS_3[4]

PS_3[5]

12

RV1325
10K_0402_5%

PX@

GPU_SVC
GPU_SVD

12

RV1329
10K_0402_5%

@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESIST OR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

Strap Name

ROM_CO NFIG[0 ]

Define the ROM type when STRAP_BIOS_ROM_EN = 1,

ROM_CO NFIG[1 ]

Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.

ROM_CO NFIG[2 ]

Reserved f or internal use only. Must be 1 at reset.

N/A

Reserv ed

1 = PCIe GEN3 is supported.

STRAP_BIF_GE N3_EN_ A

STRAP_BIF_CLK_ PM_EN

STRAP_TX_CFG_ DRV_
FULL_SW ING

STRAP_TX_DEEMPH_E N

STRAP_BIOS_RO M_EN

BOARD _CONFIG [0]
BOARD _CONFIG [1]
BOARD _CONFIG [2]

0 = PCIe GEN3 is not supported.

0 = The CLKREQB po wer management capability is disabled
1 = The CLKREQB po wer management capability is enabled

N/A

Reserved f or internal use only. Must be 0 at reset.

0 = The transmitter half-swing is enabled
1 = The transmitter f ull-swing is enabled

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

Reserv ed.

N/A

Reserv ed.

N/A

0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

N/A

Reserv ed

N/A Res erve d 1

Board configuration related strapping, such as for memory ID

N/A

Reserv ed

N/A

Reserv ed

For R18M-M2-60

12

RV1324
10K_0402_5%

@

12

RV1331
10K_0402_5%

PX@

RV1411

8.45K_0402_1%

R18@

PS_0 PS_1

RV1413

2K_0402_1%

R18@

RV1416

10K_0402_5%

PS_2

RV1417

4.75K_0402_1%

R18@

Reserve

+3VGS +3VGS

12

GPU_ROMCS#

RV1409

1K_0402_5%

GPU_ROMSO

@

GPU_ROMWP#

2017/08/15

2017/08/15

2017/08/15

DescriptionMLPS Bit

001 = 256MB

1= GEN3 is supported

1= Enable

0= Disable

000 = Samsung 8Gb
001 = Hynix 8Gb
010 = M icron 8Gb

+1.8VGS +1.8VGS

12

12

1

CV124
.01U_0402_16V7-K

@

2

+1.8VGS

12

@

12

1

CV126
.01U_0402_16V7-K

@

2

+3VGS

8

UV7

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

Title

Title

Title

R17M-P1-50_VRAM I/F

R17M-P1-50_VRAM I/F

R17M-P1-50_VRAM I/F

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Date: She et of

Date: She et of

Date: She et of

CV123

1 2

0.1U_0201_6.3V6-K

@

VCC

DI(IO0)

CLK

/HOLD(IO3)

GND

W25Q80DVSSIG_SO8

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

RV1412

8.45K_0402_1%

R18@

RV1414

2K_0402_1%

R18@

RV1415

8.45K_0402_1%

PS_3

RV1418

2K_0402_1%

@

5

6

7

330ARR

330ARR

330ARR

12

12

+1.8VGS

12

@

12

@

GPU_ROMSI

GPU_ROMSCK

GPU_ROMHOLD#

RECOMMENDED
SETT INGS

X

1

1

X

0

0

1

X

0

0

X

1

X

1

1

1

CV125
.01U_0402_16V7-K

@

2

1

CV127
.01U_0402_16V7-K

@

2

12

RV1407
1K_0402_5%

@

18 52

18 52

18 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

UV1G

D D

C C

B B

BA12

12

RV1345

150_0402_1%

PX@

symbol7

TX2P_DPB0P

TX2M_DPB0N

TX1P_DPB1P

TX1M_DPB1N

TX0P_DPB2P

TX0M_DPB2N

TXCBP_DPB3P

TXCBM_DPB3N

DDCAUX3P

DDCAUX3N

TX5P_DPA0P

TX5M_DPA0N

TX4P_DPA1P

TX4M_DPA1N

TX3P_DPA2P

TX3M_DPA2N

TXCAP_DPA3P

TXCAM_DPA3N

AUX_ZVSS

REV 0.91

216-0905018-C3_FC BGA769

@

DDCAUX4P

DDCAUX4N

AY32

BA32

AY31

BA31

AY30

BA30

AY28

BA28

AM21

AP21

AY36

BA36

AY35

BA35

AY34

BA34

AY33

BA33

AR23

AP23

1

TV64 PAD @

UV1H

symbol8

TX2P_DPD0P

TX2M_DPD0N

TX1P_DPD1P

TX1M_DPD1N

TX0P_DPD2P

TX0M_DPD2N

TXCDP_DPD3P

TXCDM_DPD3N

AUX1N

DDC1CLK

DDC1DATA

TX5P_DPC0P

TX5M_DPC0N

TX4P_DPC1P

TX4M_DPC1N

TX3P_DPC2P

TX3M_DPC2N

TXCCP_DPC3P

TXCCM_DPC3N

AUX2N

DDC2CLK

REV 0.91

216-0905018-C3_FC BGA769

@

DDC2DATA

AUX1P

AUX2P

AY22

BA22

AY21

BA21

AY20

BA20

AY19

BA19

AY11

BA11

AY10

BA10

AY27

BA27

AY26

BA26

AY25

BA25

AY24

BA24

AP19

AM19

AV19

AU19

RV1420

1

1 2

@

51K_0402_5%

1

1

TV63 PAD @

TV62 PAD @

TV61 PAD @

UV1O

symbol15

TX2P_DPE0P

TX2M_DPE0N

TX1P_DPE1P

TX1M_DPE1N

TX0P_DPE2P

TX0M_DPE2N

TXCEP_DPE3P

TXCEM_DPE3N

DDCAUX5P

DDCAUX5N

REV 0.91

216-0905018-C3_FC BGA769

@

AY18

BA18

AY16

BA16

AY15

BA15

AY14

BA14

AU27

AV27

1

1

TV65 PAD @

TV66 PAD @

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

2016/08/16

2016/08/16

2016/08/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2017/08/15

2017/08/15

Deciphered Date

Deciphered Date

Deciphered Date

3

2017/08/15

2

Titl e

R17M-P1-50_GPIO

R17M-P1-50_GPIO

R17M-P1-50_GPIO

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Friday, March 23, 2018

Friday, March 23, 2018

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

19 52

19 52

19 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

+VDDC

D D

Reserve 8pcs 22U_0603 capacitors
for PWR requirement --Brooks 0717

C C

+1.35VGS

B B

(1U_0402_6.3V) *7
(22U_0603_6.3V) *8

PX@

1

2

CV21

PX@

1

2

CV47

PX@

1

2

CV128

(1U_0402_6.3V) *10
(22U_0603_6.3V) *2

PX@

1

2

CV57

PX@

1

2

CV75

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV23

CV22

PX@

PX@

1

1

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CV49

CV48

@

PX@

1

1

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CV129

CV130

PX_CD@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV55

CV58

PX@

1

33P_0402_50V8J

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CV76

1U_0402_6.3V6K

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1U_0402_6.3V6K

CV501

RF_PXNS@

UV1I

N13

symbol9

VDDC#0

N15

VDDC#1

N21

VDDC#2

PX_CD@

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

CV24

CV25

PX@

PX@

1

1

2

2

22U_0603_6.3V6-M

CV51

CV50

PX@

PX@

1

1

2

2

22U_0603_6.3V6-M

CV131

CV132

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

CV59

CV56

1

2

PX_CD@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1U_0402_6.3V6K

1U_0402_6.3V6K

CV30

CV31

PX@

PX@

1

1

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CV53

CV52

@

@

1

1

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CV134

CV133

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV64

CV63

CV503

33P_0402_50V8J

RF_PXNS@

PX@

1

2

22U_0603_6.3V6-M

CV54

@

1

2

22U_0603_6.3V6-M

CV135

PX_CD@

1

2

1U_0402_6.3V6K

CV65

1

2

RF

PX_CD@

PX@

1

1

2

2

1U_0402_6.3V6K

CV66

CV67

RF

N23

VDDC#3

N29

VDDC#4

N31

VDDC#5

R13

VDDC#6

R15

VDDC#7

R21

VDDC#8

R23

VDDC#9

R29

VDDC#10

R31

VDDC#11

U13

VDDC#12

U15

VDDC#13

U21

VDDC#14

U23

VDDC#15

U29

VDDC#16

U31

VDDC#17

W13

VDDC#18

W15

VDDC#19

W21

VDDC#20

W23

VDDC#21

W29

VDDC#22

W31

VDDC#23

AA13

VDDC#24

AA15

VDDC#25

AA21

VDDC#26

AA23

VDDC#27

AA29

VDDC#28

AA31

VDDC#29

AC13

VDDC#30

AC15

VDDC#31

AC21

VDDC#32

AC23

VDDC#33

AC29

VDDC#34

AC31

VDDC#35

AE13

VDDC#36

AE15

VDDC#37

AE21

VDDC#38

AE23

VDDC#39

AE29

VDDC#40

AE31

VDDC#41

AG13

VDDC#42

AG15

VDDC#43

AG21

VDDC#44

AG23

VDDC#45

AG29

VDDC#46

AG31

VDDC#47

AJ13

VDDC#48

AJ15

VDDC#49

AJ17

VDDC#50

AJ19

VDDC#51

AJ21

VDDC#52

AJ23

VDDC#53

AJ25

VDDC#54

AJ27

VDDC#55

AJ29

VDDC#56

AJ31

VDDC#57

AL13

VDDC#58

AL15

VDDC#59

AL17

VDDC#60

AL19

VDDC#61

AL21

VDDC#62

AL23

VDDC#63

AL25

VDDC#64

AL27

VDDC#65

AL29

VDDC#66

AL31

VDDC#67

REV 0.91

216-0905018-C3_FCBGA769

@

UV1N

symbol14

K11

VMEMIO#0

K13

VMEMIO#1

K19

VMEMIO#2

K23

VMEMIO#3

K27

VMEMIO#4

K31

VMEMIO#5

L10

VMEMIO#6

N10

VMEMIO#7

W10

1U_0402_6.3V6K

VMEMIO#8

AC10

VMEMIO#9

AG10

VMEMIO#10

216-0905018-C3_FCBGA769

@

REV 0.91

VDDCI#0
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

FB_VMEMIO

FB_VDDCI

FB_VDDC

FB_VSS

VDD_18#0
VDD_18#1
VDD_18#2

VDD_08#0
VDD_08#1
VDD_08#2
VDD_08#3
VDD_08#4
VDD_08#5

VDD_08

VSS#227
VSS#228

L13
L17
L21
L25
L29
N11
U11
AA11
AE11

GPU_VMEMIO_SENSE

C3

GPU_VDDCI_SENSE

AV13

GPU_VDDC_SENSE

AR13

GPU_VSSC_SENSE

AU13

AM15
AP15
AR15

AC32
AG32
AG35
AJ32
AJ34
AL34

W32

AM23
AM17

PX_CD@

1

2

1U_0402_6.3V6K

CV26

(1U_0402_6.3V) *3

PX@

1

2

1U_0402_6.3V6K

CV60

(1U_0402_6.3V) *7

PX@

1

2

CV68

10U_0402_6.3V6M

(1U_0402_6.3V) *4
(22U_0603_6.3V) *2

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV27

CV35

GPU_VMEMIO_SENSE 50
GPU_VDDCI_SENSE 51
GPU_VDDC_SENSE 51
GPU_VSSC_SENSE 51

PX_CD@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV61

CV62

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

CV69

CV70

10U_0402_6.3V6M

PX@

1

2

1U_0402_6.3V6K

CV28

RV1427 0_0805_5%@

1

CV504

0.1U_0201_6.3V6-K

@

2

For EMC

PX@

1

2

1U_0402_6.3V6K

CV71

Change CV72~CV74 to 0201 size for
layout space limitation --Brooks 0719

1 2

PX@

1

2

CV72

1U_0201_6.3V6-M

+VDDCI

PX@

PX@

1

1

2

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CV29

CV36

+1.8VGS+1.8VGS_GPU

+VDD_08

PX@

PX@

1

1

2

2

CV74

CV73

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CV502

33P_0402_50V8J

RF_PXNS@

1

CV33

0.1U_0201_6.3V6-K

@

2

For EMC

1

2

RF

+3VALW TO +3VGS

+3VGS /10mA

MOS. AO3402 VGS
MAX is 12V

+1.8VALW TO +1.8VGS

+1.8VGS /1.0A Rdson<65mohm
Backup is AO3420

Discharge

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

2016/08/16

2016/08/16

2016/08/16

3

Deciphered Date

2017/08/15

2017/08/15

2017/08/15

2

Titl e

R17M-P1-50_DIGITAL OUT

R17M-P1-50_DIGITAL OUT

R17M-P1-50_DIGITAL OUT

Size

Size

Size

Document Number R e v

Document Number R e v

Document Number R e v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

20 52

20 52

20 52

1

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

UV1L

A2

VSS#0

A5

VSS#1

A9

D D

C C

B B

VSS#2

A13

VSS#3

A17

VSS#4

A21

VSS#5

A25

VSS#6

A29

VSS#7

A33

VSS#8

A37

VSS#9

A40

VSS#10

B1

VSS#11

B40

VSS#12

B41

VSS#13

C5

VSS#14

C7

VSS#15

C9

VSS#16

C11

VSS#17

C13

VSS#18

C15

VSS#19

C17

VSS#20

C19

VSS#21

C21

VSS#22

C23

VSS#23

C25

VSS#24

C27

VSS#25

C29

VSS#26

C31

VSS#27

C33

VSS#28

C35

VSS#29

C37

VSS#30

C39

VSS#31

E1

VSS#32

E3

VSS#33

E4

VSS#34

E9

VSS#35

E13

VSS#36

E17

VSS#37

E21

VSS#38

E25

VSS#39

E29

VSS#40

E39

VSS#41

E41

VSS#42

G3

VSS#43

G7

VSS#44

G11

VSS#45

G15

VSS#46

G19

VSS#47

G23

VSS#48

G27

VSS#49

G31

VSS#50

G35

VSS#51

G39

VSS#52

J1

VSS#53

J3

VSS#54

J5

VSS#55

J34

VSS#56

J37

VSS#57

216-0905018-C3_FCBG A769

@

symbol12

REV 0.91

VSS#58
VSS#59
VSS#60
VSS#61
VSS#62
VSS#63
VSS#64
VSS#65
VSS#66
VSS#67
VSS#68
VSS#69
VSS#70
VSS#71
VSS#72
VSS#73
VSS#74
VSS#75
VSS#76
VSS#77
VSS#78
VSS#79
VSS#80
VSS#81
VSS#82
VSS#83
VSS#84
VSS#85
VSS#86
VSS#87
VSS#88
VSS#89
VSS#90
VSS#91
VSS#92
VSS#93
VSS#94
VSS#95
VSS#96
VSS#97
VSS#98

VSS#99
VSS#100
VSS#101
VSS#102
VSS#103
VSS#104
VSS#105
VSS#106
VSS#107
VSS#108
VSS#109
VSS#110
VSS#111
VSS#112
VSS#113
VSS#114

J39
J40
J41
K21
K25
K29
K40
L3
L7
L11
L15
L19
L23
L27
L31
L35
L39
N1
N3
N5
N17
N19
N25
N27
N32
N37
N39
R3
R7
R11
R17
R19
R25
R27
R32
R35
R39
U1
U3
U5
U17
U19
U25
U27
U32
U37
U39
W3
W7
W11
W17
W19
W25
W27
W39
AA1
AA3

UV1M

AA5

VSS#115

AA10

VSS#116

AA17

VSS#117

AA19

VSS#118

AA25

VSS#119

AA27

VSS#120

AA32

VSS#121

AA39

VSS#122

AC3

VSS#123

AC7

VSS#124

AC11

VSS#125

AC17

VSS#126

AC19

VSS#127

AC25

VSS#128

AC27

VSS#129

AC39

VSS#130

AE1

VSS#131

AE3

VSS#132

AE5

VSS#133

AE10

VSS#134

AE17

VSS#135

AE19

VSS#136

AE25

VSS#137

AE27

VSS#138

AE32

VSS#139

AE35

VSS#140

AE39

VSS#141

AG3

VSS#142

AG7

VSS#143

AG11

VSS#144

AG17

VSS#145

AG19

VSS#146

AG25

VSS#147

AG27

VSS#148

AG39

VSS#149

AG40

VSS#150

AG41

VSS#151

AJ1

VSS#152

AJ3

VSS#153

AJ5

VSS#154

AJ10

VSS#155

AJ11

VSS#156

AJ35

VSS#157

AJ39

VSS#158

AL3

VSS#159

AL7

VSS#160

AL10

VSS#161

AL11

VSS#162

AL32

VSS#163

AL35

VSS#164

AL39

VSS#165

AN1

VSS#166

AN3

VSS#167

AN7

VSS#168

AN35

VSS#169

AN39

VSS#170

216-0905018-C3_FCBG A769

@

symbol13

REV 0.91

VSS#171
VSS#172
VSS#173
VSS#174
VSS#175
VSS#176
VSS#177
VSS#178
VSS#179
VSS#180
VSS#181
VSS#182
VSS#183
VSS#184
VSS#185
VSS#186
VSS#187
VSS#188
VSS#189
VSS#190
VSS#191
VSS#192
VSS#193
VSS#194
VSS#195
VSS#196
VSS#197
VSS#198
VSS#199
VSS#200
VSS#201
VSS#202
VSS#203
VSS#204
VSS#205
VSS#206
VSS#207
VSS#208
VSS#209
VSS#210
VSS#211
VSS#212
VSS#213
VSS#214
VSS#215
VSS#216
VSS#217
VSS#218
VSS#219
VSS#220
VSS#221
VSS#222
VSS#223
VSS#224
VSS#225
VSS#226

AN40
AN41
AP13
AP17
AR3
AR7
AR11
AR19
AR21
AR25
AR27
AR31
AR35
AR39
AU1
AU3
AU9
AU23
AU29
AW3
AW5
AW7
AW9
AW11
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW29
AW31
AW33
AW35
AW37
AW39
AY1
AY2
AY9
AY12
AY17
AY23
AY29
AY37
AY40
AY41
BA2
BA5
BA9
BA17
BA23
BA29
BA37
BA40

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

2016/08/16

2016/08/16

2016/08/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2017/08/15

2017/08/15

2017/08/15

2

Titl e

R17M-P1-50_PWR

R17M-P1-50_PWR

R17M-P1-50_PWR

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

21 52

21 52

21 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

UV1C

DQA0_[0..31]23

DQA1_[0..31]23

D D

MAA0_[0..8]23

MAA1_[0..8]23

C C

B B

DQA0_[0..31]

DQA1_[0..31]

MAA0_[0..8]

MAA1_[0..8]

WCKA0_023
WCKA0#_023

WCKA0_123
WCKA0#_123

EDCA0_023
EDCA0_123
EDCA0_223
EDCA0_323

DDBIA0_023
DDBIA0_123
DDBIA0_223
DDBIA0_323

CSA0#_023

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8

WCKA0_0
WCKA0#_0

WCKA0_1
WCKA0#_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

ADBIA0

CSA0#_0

G37
E38
E35
D35
H41
H40
G41
G40
E40
D41
D40
C41
C40
B39
A39
B38
B36
A36
B35
A35
B33
B32
A32
B31
A30
B29
B28
A28

G25
H25
E27
D27
D29
H27
H23
E23
D25
H29

D33
E33

A34
B34

G38
F41
B37
A31

F40
A38
B30

H21

H31

L34
L37
L38
J35

J38

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
DQA0_10
DQA0_11
DQA0_12
DQA0_13
DQA0_14
DQA0_15
DQA0_16
DQA0_17
DQA0_18
DQA0_19
DQA0_20
DQA0_21
DQA0_22
DQA0_23
DQA0_24
DQA0_25
DQA0_26
DQA0_27
DQA0_28
DQA0_29
DQA0_30
DQA0_31

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9

WCKA 0_0
WCKA 0B_0

WCKA 0_1
WCKA 0B_1

EDCA0_0
EDCA0_1
EDCA0_2
EDCA0_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

ADBIA0

CSA0B_0

symbol3

DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8

DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MAA1_0

MAA1_1

MAA1_2

MAA1_3

MAA1_4

MAA1_5

MAA1_6

MAA1_7

MAA1_8

MAA1_9

WCKA 1_0

WCKA 1B_0

WCKA 1_1

WCKA 1B_1

EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ADBIA1

CSA1B_0

B27
A27
B26
A26
A24
B23
A23
B22
B20
A20
B19
A19
B17
A16
B16
A15
B15
A14
B14
B13
A11
B11
A10
B10
B8
A7
B7
A6
A4
B4
A3
B3

E15
H15
G13
D13
H11
H13
H17
G17
D15
E11

A22
B21

A8
B9

B24
A18
B12
B6

B25
B18
A12
B5

H19

E7

DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31

MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MAA1_8

WCKA1_0
WCKA1#_0

WCKA1_1
WCKA1#_1

EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3

DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3

ADBIA1

CSA1#_0

WCKA1_0 23
WCKA1#_0 23

WCKA1_1 23
WCKA1#_1 23

EDCA1_0 23
EDCA1_1 23
EDCA1_2 23
EDCA1_3 23

DDBIA1_0 23
DDBIA1_1 23
DDBIA1_2 23
DDBIA1_3 23

ADBIA1 23ADBIA023

CSA1#_0 23

UV1D

C2

DQB0_0

C1

DQB0_1

D2

DQB0_2

D1

DQB0_3

F1

DQB0_4

G2

DQB0_5

G1

DQB0_6

H2

DQB0_7

K2

DQB0_8

K1

DQB0_9

L2

DQB0_10

L1

DQB0_11

N2

DQB0_12

P2

DQB0_13

P1

DQB0_14

R2

DQB0_15

R1

DQB0_16

T2

DQB0_17

T1

DQB0_18

U2

DQB0_19

W1

DQB0_20

W2

DQB0_21

Y1

DQB0_22

Y2

DQB0_23

AB2

DQB0_24

AC1

DQB0_25

AC2

DQB0_26

AD1

DQB0_27

AF1

DQB0_28

AF2

DQB0_29

AG1

DQB0_30

AG2

DQB0_31

R5

MAB0_0

R8

MAB0_1

N7

MAB0_2

N4

MAB0_3

L8

MAB0_4

N8

MAB0_5

U8

MAB0_6

U7

MAB0_7

R4

MAB0_8

L5

MAB0_9

H1

WCKB 0_0

J2

WCKB 0B_0

AB1

WCKB 0_1

AA2

WCKB 0B_1

F2

EDCB0_0

M2

EDCB0_1

V1

EDCB0_2

AD2

EDCB0_3

E2

DDBIB0_0

M1

DDBIB0_1

V2

DDBIB0_2

AE2

DDBIB0_3

W8

ADBIB0

CSB0B_0G5CSB1B_0

symbol4

DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8

DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31

MAB1_0

MAB1_1

MAB1_2

MAB1_3

MAB1_4

MAB1_5

MAB1_6

MAB1_7

MAB1_8

MAB1_9

WCKB 1_0

WCKB 1B_0

WCKB 1_1

WCKB 1B_1

EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3

DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3

ADBIB1

AH1
AH2
AJ2
AK1
AL2
AM1
AM2
AN2
AR1
AR2
AT1
AT2
AV2
AW1
AW2
AY3
BA3
AY4
BA4
AY5
BA7
AY7
AY8
BA8
AR4
AR5
AU4
AU7
AN8
AV11
AU11
AP11

AE7
AE8
AG5
AG4
AJ4
AG8
AC8
AC5
AE4
AJ8

AP1
AP2

AN4
AN5

AL1
AU2
BA6
AV7

AK2
AV1
AY6
AV9

AA8

AL8

D23

CASA0#23
RASA0#23
WEA0#23

CKEA023

CLKA023
CLKA0#23

1 2

RV1241

PX@

120_0402_1%

1 2

RV1242

DRAM_RST23

A A

PX@

49.9_0402_1%

120P_0402_50V8-J

CV10

PX@

RV1243

1

2

1 2

PX@

10_0402_1%

5

CASA0#
RASA0#
WEA0#

CKEA0

CLKA0
CLKA0#

MEM_CALRA

DRAM_RST_ADRAM_RST_R

12

RV1245

4.99K_0402_1%

PX@

4

CASA0B

D21

RASA0B

G29

WEA 0B

G21

CKEA0

E31

CLKA0

D31

CLKA0B

K15

MEM_CAL RA

L32

DRAM_RS TA

216-0905018-C3_FCBGA769

@

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

CASA1B
RASA1B

WEA 1B

CKEA1

CLKA1

CLKA1B

MVREFDA

REV 0.91

Issued Date

Issued Date

Issued Date

D17
D19
D11

E19

D7
D9

K17

CASA1#
RASA1#
WEA1#

CKEA1

CLKA1
CLKA1#

MVREFDA

CASA1# 23
RASA1# 23
WEA1# 23

CKEA1 23

CLKA1 23
CLKA1# 23

1

CV9
1U_0402_6.3V6K

PX@

2

2016/08/16

2016/08/16

2016/08/16

3

CASB0BU4CASB1B
RASB0BW4RASB1B

L4

+1.35VGS +1.35VGS

12

RV1240

40.2_0402_1%

PX@

12

RV1244
100_0402_1%

PX@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

WEB 0B

W5

CKEB0

G4

CLKB0

J4

CLKB0B

R10

MEM_CAL RB

AM11

DRAM_RS TB

216-0905018-C3_FCBGA769

@

2017/08/15

2017/08/15

2017/08/15

2

AC4
AA4

Reserve for R18M-M2-60

AJ7

WEB 1B

AA7

CKEB1

AL5

CLKB1

AL4

CLKB1B

U10

MVREFDB

REV 0.91

MVREFDB

1

CV121
1U_0402_6.3V6K

R18@

2

Titl e

Titl e

Titl e

R17M-P1-50_VSS

R17M-P1-50_VSS

R17M-P1-50_VSS

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

12

RV1387

40.2_0402_1%

R18@

12

RV1386
100_0402_1%

R18@

22 52

22 52

22 52

1.0

1.0

1.0

5

Vinafix.com

PX@

PX@

1

1

2

2

0.1U_0201_6.3V6-K
CV110

CV109

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

CV94

CV93

DQA0_[0. .31]

MAA0_[0. .8]

EDCA0_022
EDCA0_122
EDCA0_222
EDCA0_322

DDBIA0_022
DDBIA0_122
DDBIA0_222
DDBIA0_322

CLKA022
CLKA0#22
CKEA022

RV1360

ADBIA022
RASA0#2 2
CSA0#_02 2
CASA0#2 2
WEA0#22

WCKA0# _022
WCKA0_ 022

WCKA0# _122
WCKA0_ 122

DRAM_RST22

(0.1U_0201_6.3V) *8
(1U_0402_6.3V) *8
(10U_0603_6.3V) *3

PX@

PX@

PX@

1

1

1

2

2

0.1U_0201_6.3V6-K
CV111

PX@

1

2

1U_0402_6.3V6K

CV95

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CV112

CV113

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV96

CV97

1 2

120_040 2_1%

+1.35VGS

PX_CD@

1

2

0.1U_0201_6.3V6-K
CV114

PX_CD@

1

2

1U_0402_6.3V6K

CV98

PX@

MF=0 No Mirror MF=1 Mirror

UV3

EDCA0_0

C2

PX_CD@

1

2

0.1U_0201_6.3V6-K

CV116

PX_CD@

1

2

1U_0402_6.3V6K

CV100

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

H5GQ1H24 AFR-T2L_BGA1 70

@

EDCA0_1
EDCA0_2
EDCA0_3

DDBIA0_0
DDBIA0_1
DDBIA0_2
DDBIA0_3

CLKA0
CLKA0#
CKEA0

MAA0_2
MAA0_5
MAA0_4
MAA0_3

MAA0_7
MAA0_1
MAA0_0
MAA0_6
MAA0_8

ZQ_UV3

ADBIA0
RASA0#

CSA0#_0

CASA0#
WEA0#

WCKA0# _0
WCKA0_ 0

WCKA0# _1
WCKA0_ 1

VREFD1_A 0
VREFD2_A 0
VREFC_A0

DRAM_RST

PX_CD@

1

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CV115

PX_CD@

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV99

DQA0_[0. .31]22

MAA0_[0. .8]22

D D

+1.35VGS

12

RV1350

2.37K_0 402_1%

@

VREFD1_A 0

12

1

RV1352

5.49K_0 402_1%

@

+1.35VGS

C C

B B

A A

RV1354

2.37K_0 402_1%

RV1356

5.49K_0 402_1%

RV1364

2.37K_0 402_1%

RV1366

5.49K_0 402_1%

+1.35VGS

PX@

1

2

CV505

10U_0603_6.3V6M

PX@

PX@

PX@

CV506

@

@

+1.35VGS

1

2

CV77
1U_0402 _6.3V6K

@

2

12

VREFD2_A 0

12

1

CV79
1U_0402 _6.3V6K

@

2

12

VREFC_A0

12

1

CV81
1U_0402 _6.3V6K

PX@

2

+1.35VGS

PX@

1

2

CV92

10U_0603_6.3V6M

10U_0603_6.3V6M

5

4

MF=0 MF =1 MF=0MF=1

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9

4

DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

3

DQA1_[0. .31]22

+1.35VGS

1 2

RV1346 60.4 _0201_1%PX@

1 2

DQA0_1

A4

DQA0_2

A2

DQA0_7

B4

DQA0_5

B2

DQA0_6

E4

DQA0_4

E2

DQA0_3

F4

DQA0_0

F2

DQA0_8

A11

DQA0_9

A13

DQA0_10

B11

DQA0_11

B13

DQA0_14

E11

DQA0_12

E13

DQA0_15

F11

DQA0_13

F13

DQA0_22

U11

DQA0_20

U13

DQA0_23

T11

DQA0_21

T13

DQA0_19

N11

DQA0_18

N13

DQA0_16

M11

DQA0_17

M13

DQA0_27

U4

DQA0_28

U2

DQA0_26

T4

DQA0_29

T2

DQA0_25

N4

DQA0_30

N2

DQA0_24

M4

DQA0_31

M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

Byte 0

Byte 1

Byte 2

Byte 3

+1.35VGS

RV1347 60.4 _0201_1%PX@

RV1349 60.4 _0201_1%PX@
RV1348 60.4 _0201_1%PX@

+1.35VGS

PX@

1

2

CV507

3

10U_0603_6.3V6M

1 2
1 2

2.37K_0 402_1%

5.49K_0 402_1%

2.37K_0 402_1%

5.49K_0 402_1%

2.37K_0 402_1%

5.49K_0 402_1%

PX@

1

2

CV508

10U_0603_6.3V6M

MAA1_[0. .8]22

CLKA0
CLKA0#

CLKA1
CLKA1#

+1.35VGS

12

RV1351

@

VREFD1_A 1

12

RV1353

RV1355

RV1361

RV1365

PX@

RV1367

PX@

PX@

1

2

CV83

10U_0603_6.3V6M

1

CV78

@

+1.35VGS

@

@

+1.35VGS

1U_0402 _6.3V6K

@

2

12

VREFD2_A 1

12

1

CV80
1U_0402 _6.3V6K

@

2

12

VREFC_A1

12

1

CV82
1U_0402 _6.3V6K

PX@

2

+1.35VGS

PX@

PX@

1

1

2

2

0.1U_0201_6.3V6-K
CV102

CV101

PX@

PX@

1

1

2

2

1U_0402_6.3V6K

CV85

CV84

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

DQA1_[0. .31]

MAA1_[0. .8]

+1.35VGS

(0.1U_0201_6.3V) *8
(1U_0402_6.3V) *8
(10U_0603_6.3V) *3

PX@

PX@

PX@

1

1

1

2

2

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

CV103

CV104

CV105

PX@

PX@

PX@

1

1

1

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV86

CV87

CV88

PX_CD@

0.1U_0201_6.3V6-K
CV106

PX_CD@

1U_0402_6.3V6K

CV89

2016/08/16

2016/08/16

2016/08/16

1

2

1

2

2

EDCA1_1
EDCA1_0
EDCA1_2
EDCA1_3

DDBIA1_1
DDBIA1_0
DDBIA1_2
DDBIA1_3

CLKA1
CLKA1#
CKEA1

MAA1_4
MAA1_3
MAA1_2
MAA1_5

MAA1_0
MAA1_6
MAA1_7
MAA1_1
MAA1_8

ZQ_UV4

1 2

PX@

120_040 2_1%

ADBIA1
CASA1#
WEA1#
RASA1#

CSA1#_0

WCKA1# _0
WCKA1_ 0

WCKA1# _1
WCKA1_ 1

VREFD1_A 1
VREFD2_A 1
VREFC_A1

DRAM_RST

+1.35VGS

PX_CD@

1

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CV108

PX_CD@

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CV91

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

RV1363

0.1U_0201_6.3V6-K

1U_0402_6.3V6K

EDCA1_122
EDCA1_022
EDCA1_222
EDCA1_322

DDBIA1_122
DDBIA1_022
DDBIA1_222
DDBIA1_322

CLKA122
CLKA1#22
CKEA122

ADBIA122
CASA1#22
WEA1#2 2
RASA1#22
CSA1#_022

WCKA1# _022
WCKA1_ 02 2

WCKA1# _122
WCKA1_ 12 2

PX_CD@

1

2

CV107

PX_CD@

1

2

CV90

UV4

MF=0 MF= 1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

H5GQ1H24 AFR-T2L_BGA1 70

@

2017/08/15

2017/08/15

2017/08/15

1

DQA1_11

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2

B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14

A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14

DQA1_15
DQA1_10
DQA1_14
DQA1_9
DQA1_13
DQA1_8
DQA1_12
DQA1_1
DQA1_0
DQA1_2
DQA1_3
DQA1_4
DQA1_7
DQA1_5
DQA1_6
DQA1_22
DQA1_20
DQA1_23
DQA1_21
DQA1_18
DQA1_19
DQA1_17
DQA1_16
DQA1_27
DQA1_28
DQA1_26
DQA1_29
DQA1_25
DQA1_30
DQA1_24
DQA1_31

330ARR

330ARR

330ARR

1

+1.35VGS

Byte 1

Byte 0

Byte 2

Byte 3

23 52

23 52

23 52

DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31

Titl e

Titl e

Titl e

R17M-P1-50_GDDR5 VRAM1

R17M-P1-50_GDDR5 VRAM1

R17M-P1-50_GDDR5 VRAM1

Size Document Num ber Re v

Size Document Num ber Re v

Size Document Num ber Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

1.0

1.0

1.0

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

Title

Title

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2

2016/08/16

2016/08/16

2016/08/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2017/08/15

2017/08/15

2017/08/15

Title

R17M-P1-50_GDDR5 VRAM2

R17M-P1-50_GDDR5 VRAM2

R17M-P1-50_GDDR5 VRAM2

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

330ARR

330ARR

330ARR

24 52

24 52

24 52

1.0

1.0

1.0

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CON TAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

2016/08/16

2016/08/16

2016/08/16

3

Deciphered Date

2017/08/15

2017/08/15

2017/08/15

2

Titl e

R17M-P1-50_Sequence

R17M-P1-50_Sequence

R17M-P1-50_Sequence

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

25 52

25 52

25 52

1.0

1.0

1.0

5

Vinafix.com

+3VS

1

2

D D

PCH_ENVDD6

LCD POWER CIRCUIT

1U_0402_6.3V6K

C1

PCH_ENVDD

5

4

SY6288C20AAC_SOT23-5

PCH_ENVDD

U9

IN

EN

12

1

OUT

2

GND

3

OCB

R35
100K_0402_5%

+LCDVDD_CON

1

2

C2

W=60mi ls

@

1

2

4.7U_0402_6.3V6M

C122

0.1U_0201_6.3V6-K

APU output enable Voh min is 1.8V-0.45V=1.35V

PCH_EDP_PWM6

C C

PCH_EDP_PWM

1 2

R19 0_0402_5%@

INVT_PWM

12

R20
100K_0402_5%

@

Need Short

+3VS

R10

4.7K_0402_5%

@

1 2

BKOFF#39

B B

R12 0_0402_5%@

1 2

R14 0_0402_5%@

1 2

DISPOFF#

ENBKL

12

R16
100K_0402_5%

ENBKL 39PCH_ENBKL6

4

1

RF_NS@

2

33P_0402_50V8J

C123

For RF

CMOS Camera

CMOS_ON#39

DMIC_CLK

USB20_N1

USB20_P1

1

C11

2

EMC@

100P_0201_25V8J

C1323

0.1U_0201_6.3V6-K

@

1 2

R5

@

100K_0402_5%

L12

EMC_NS@

1

1

4

4

EXC24CH900U_4P

DISPOFF#

C12

+3VS

1

2

2

2

3

3

1

2

EMC_NS@

470P_0201_50V7-K

3

F3

J1

112

JUMP_43X39

LP2301ALT1G_SOT23-3

S

Q7

@

G

CMOS_ON#_R

USB20_N1_R

USB20_P1_R

INVT_PWM

0.5A_32V_ERBRD0R50XNEC@

21

@

2

D

13

2

1

C10

0.1U_0201_6.3V6-K

@

2

C1322

@

APU_EDP_TX0+6
APU_EDP_TX0-6

APU_EDP_TX1+6
APU_EDP_TX1-6

APU_EDP_AUX6
APU_EDP_AUX#6

Need Short

W=40 mils

1

C1321

2

@

0.01U_0402_25V7K

+3VS_CMOS

10U_0603_6.3V6M

1

C3

2

APU_EDP_TX1+ EDP_TX1+

APU_EDP_AUX EDP_AUX
APU_EDP_AUX# EDP_AUX#

AUX don't pull high and pull low for eDP panel

+3VS

1 2

R21

@

0_0402_5%

1

C13

1

2

470P_0201_50V7-K

C22
470P_0201_50V7-K

@

2

EMC_NS@

W=60mils

DMIC_DATA36

DMIC_CLK36

USB20_P131
USB20_N131

V20B+

1 2

0.1U_0201_6.3V6-K

1

2

+LEDVDD

C19 0.1U_0201_6.3V6-K
C16 0.1U_0201_6.3V6-K

C17 0.1U_0201_6.3V6-K
C18 0.1U_0201_6.3V6-K

C20 0.1U_0201_6.3V6-K
C21 0.1U_0201_6.3V6-K

APU_EDP_HPD6

+LCDVDD_CON

+3VS

R182 0_0402_5%@
R183 0_0402_5%@

+3VS_CMOS

.047U_0201_6.3V6K

2

B+ to +LEDVDD POWER

+LEDVDD

NONEC@

R22

0_0805_5%

F2

NEC@

21

3A_32V_ERBRD3R00X

12
12

12
12

12
12

1 2
1 2

C1320

EMC_NS@

1

2

2A 80 mil

4.7U_0805_25V6-K
C25

1

2

EDP_TX0+APU_EDP_TX0+
EDP_TX0-APU_EDP_TX0-

EDP_TX1-APU_EDP_TX1-

DISPOFF#

INVT_PWM

USB20_P1_R
USB20_N1_R

W=40mils

1

C23

0.1U_0402_25V6

C23 0.1u for G HSW panel blink issue

2

JEDP1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

G1

32

G2

DRAPH_FC5AF301-3181H

ME@

1

EMC

Touch Screen

USB20_N2 USB20_N2_CONN

USB20_P2 USB20_ P2_CONN

L33

1

1

4

4

EXC24CH900U_4P

EMC_NS@

For EMI

2

2

3

3

USB20_P2_CONN

+5VS_TS

USB20_N2_CONN

1

D42

1

2

AZ5725-01F.R7GR_DFN1006P2X2

2

EMC_NS@

For ESD

3

2

D41
AZC199-02S.R7G_SOT23-3

EMC_NS@

1

Touch Screen

TS_NEC@

1 2

TS_NONEC@

21

0.1U_0201_6.3V6-K

F4 0.5A_32V_ERBR D0R50X

+5VS

R4675 0_0402_5%

C2079

TS@

+5VS_TS

1

2

JTS1

ME@

1

1

2

1 2

EC_TS_ON39

USB20_N231
USB20_P231

R4677 0_0402_5%@

1 2

R4678 0_0402_5%@

1 2

R4676 0_0402_5%@

TS_RS

USB20_N2_CONN
USB20_P2_CONN

2

3

3

4

4

5

5

6

6

CVILU_CI1806M2HR0-NH

GND1

GND2

7

8

A A

Title

Title

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

2013/08/08

2013/08/08

2013/08/08

3

Deciphered Date

2013/08/05

2013/08/05

2013/08/05

2

Title

eDP/CMOS/TS

eDP/CMOS/TS

eDP/CMOS/TS

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

26 52

26 52

26 52

1.0

1.0

1.0

5

Vinafix.com

L2

HDMI_CLK-_C

HDMI_CLK+_C

D D

HDMI_TX0-_C

HDMI_TX0+_C

HDMI_TX1-_C

HDMI_TX1+_C

HDMI_TX2-_C

HDMI_TX2+_C

1

1

4

4

EXC24CH900U_4P

L3

1

1

4

4

EXC24CH900U_4P

L4

1

1

4

4

EXC24CH900U_4P

L5

1

1

4

4

EXC24CH900U_4P

EMC@

EMC@

EMC@

EMC@

2

3

2

3

2

3

2

3

HDMI_CLK-_CON

2

HDMI_CLK+_CON

3

HDMI_TX0-_CON

2

HDMI_TX0+_CON

3

HDMI_TX1-_CON

2

HDMI_TX1+_CON

3

HDMI_TX2-_CON

2

HDMI_TX2+_CON

3

1 2

EMC_NS@

C26 10P_0201_25V8G

1 2

EMC_NS@

C27 10P_0201_25V8G

1 2

EMC_NS@

C28 10P_0201_25V8G

1 2

EMC_NS@

C29 10P_0201_25V8G

1 2

EMC_NS@

C30 10P_0201_25V8G

1 2

EMC_NS@

C31 10P_0201_25V8G

1 2

EMC_NS@

C32 10P_0201_25V8G

1 2

EMC_NS@

C33 10P_0201_25V8G

EMC

C C

HDMI_CLK-_C

HDMI_CLK+_C

HDMI_TX0-_C

HDMI_TX0+_C

HDMI_TX1-_C

HDMI_TX1+_C

HDMI_TX2-_C

HDMI_TX2+_C

B B

1 2

R29 499_0402_1%

1 2

R30 499_0402_1%

1 2

R31 499_0402_1%

1 2

R32 499_0402_1%

1 2

R33 499_0402_1%

1 2

R34 499_0402_1%

1 2

R37 499_0402_1%

1 2

R38 499_0402_1%

+3VS

R42

2

G

1 2

@

100K_0402_5%

13

D

Q13

2N7002KW_SOT323-3

S

4

APU_DDC_CLK6

APU_DDC_DATA6

APU_DDC_CLK

APU_DDC_DATA

2N7002KDWH_SOT363-6

3

+3VS

5

Q1A

G

S

Q1B

2N7002KDWH_SOT363-6

2

61

D

G

S

HDMICLK_R

34

D

HDMIDAT_R

HDMI_DET HDMI_DET

HDMICLK_R HDMICLK_R

HDMIDAT_R HDMIDAT_R

+5VS_HDMI +5VS_HDMI

2

D3

1

2

4

5

3

AZ1045-04F_DFN2510P10E-10-9

1

2

4

5

3

8

EMC_NS@

10

9

7

6

1

9

8

7

6

EMC

+5VS_HDMI

2

3

+3VS

C

Q43

APU_HDMI_HPD6

3 1

12

Follow Zx05 and beema

2

R202 150K_0402_5%

B

E

MMBT3904WH_SOT323-3

R910
100K_0402_5%

APU_HDMI_TX0+6
APU_HDMI_TX0-6
APU_HDMI_TX1+6
APU_HDMI_TX1-6
APU_HDMI_TX2+6
APU_HDMI_TX2-6

APU_HDMI_CLK+6
APU_HDMI_CLK-6

1 2

100K_0402_5%

APU_HDMI_CLK-

12

R257

C38 0.1U_0201_6.3V6-K
C37 0.1U_0201_6.3V6-K
C40 0.1U_0201_6.3V6-K
C39 0.1U_0201_6.3V6-K
C42 0.1U_0201_6.3V6-K
C41 0.1U_0201_6.3V6-K

C36 0.1U_0201_6.3V6-K
C35 0.1U_0201_6.3V6-K

D4

BAT54S-7-F_SOT23-3

1

12
12
12
12
12
12

12
12

@

HDMI_DET

HDMI_TX0+_C HDMI_TX0+_CONAPU_HDMI_TX0+

HDMI_TX1+_C HDMI_TX1+_CONAPU_HDMI_TX1+
HDMI_TX1-_C HDMI_TX1-_CONAPU_HDMI_TX1­HDMI_TX2+_C HDMI_TX2+_CONAPU_HDMI_TX2+
HDMI_TX2-_C HDMI_TX2-_CONAPU_HDMI_TX2-

HDMI_CLK-_C HDMI_CLK-_CON

R46 0_0402_5%@
R45 0_0402_5%@
R48 0_0402_5%@
R47 0_0402_5%@
R50 0_0402_5%@
R49 0_0402_5%@

R44 0_0402_5%@
R43 0_0402_5%@

12
12
12
12
12
12

12
12

+5VS +5VS_HDMI_F +5VS_HDMI

SUSP14,41

HDMI_TX0-_CONHDMI_TX0-_CAPU_HDMI_TX0-

HDMI_CLK+_CONHDMI_CLK+_CAPU_HDMI_CLK+

LP2301ALT1G_SOT23-3

+5VS_HDMI

D5

2

@

3

RB491D_SOT23-3

1 3

D

S

G

2

18

7
9
4
6
1
3

8
5
2

11
10
12

1

1.1A_8V_1206L110THYR

Q22

JHDMI1

+5V_Power

TMDS_Data0+
TMDS_Data0­TMDS_Data1+
TMDS_Data1­TMDS_Data2+
TMDS_Data2-

TMDS_Data0_Shield
TMDS_Data1_Shield
TMDS_Data2_Shield

TMDS_Clock_Shield
TMDS_Clock+
TMDS_Clock-

ALLTO_C128S9-K1935-L

F1

21

C34

0.1U_0201_6.3V6-K

ME@

CEC

DDC/CEC_Ground

Hot_Plug_Detect

Utility

GND1
GND2
GND3
GND4

1

2

CC1279

10U_0402_6.3V6M

2

1

HDMICLK_R

15

SCL
SDA

HDMIDAT_R

16

13
17

HDMI_DET

19

14

20
21
22
23

14

23

@

RP2

2.2K_0404_4P2R_5%

D6

1

1

2

HDMI_TX0+_CON HDMI_TX0+_CON

A A

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10E-10-9

EMC_NS@

9

10

HDMI_CLK-_CONHDMI_CLK-_CON

8

9

7

7

HDMI_TX0-_CONHDMI_TX0-_CON HDMI_TX2+_CON

6

6

HDMI_TX1-_CONHDMI_CLK+_CON HDMI_CLK+_CON

HDMI_TX1+_CON

HDMI_TX2-_CON

5

D7

1

2

4

5

3

AZ1045-04F_DFN2510P10E-10-9

1

2

4

5

3

8

EMC_NS@

10

9

7

6

4

9

8

7

6

EMC

HDMI_TX1-_CON

HDMI_TX1+_CON

HDMI_TX2-_CON

HDMI_TX2+_CON

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Title

Title

Title

HDMI_CONN

HDMI_CONN

HDMI_CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330ARR

330ARR

330ARR

1

27 52

27 52

27 52

1.0

1.0

1.0

A

Vinafix.com

LEFT SIDE USB3.0 PORT x2

+5VALW +USB_ VCCA

1

C128
1U_0402_6.3 V6K

USB_ON#39

1 1

2

USB30_RX_C_N1 USB30_RX_R_N1

USB30_RX_C_P1 USB30_RX_R_ P1

USB30_TX_C_N1 USB30_TX_ R_N1

USB30_TX_C_P1 USB30 _TX_R_P1

USB20_P5

USB20_N5

5

4

Low Active 2A

L13

112

4

4

EXC24CH900U_4P

L16

112

4

4

EXC24CH900U_4P

L8

112

4

4

EXC24CH900U_4P

U2

1

OUT

IN

2

GND

3

OCB

ENB

SY6288D20AAC_SO T23-5

EMC@

2

3

3

EMC@

2

3

3

EMC@

2

3

3

USB20_P5_R

USB20_N5_R

EMC

USB_OC1#

1

C140
1000P_020 1_50V7-K

EMC_NS@

2

B

USB_OC1# 9

USB30_TX_P19

USB30_TX_N19

USB30_RX_P19

USB30_RX_N19

C

1 2

C126 0.22U_04 02_16V6-K

USB30_TX_N1 USB30_TX_C_N1 USB30_TX_R_N1

1 2

USB20_P59

USB20_N59

+USB_VCCA

1

D11

1

2

EMC@

2

AZ5725-01F.R7GR_DFN1006P2X2

C124 0.22U_04 02_16V6-K

USB30_RX_P1 USB30 _RX_R_P1

1 2

C8787 0.3 3U_0402_10V6-K

1 2

C8788 0.3 3U_0402_10V6-K

USB20_P5_R

USB20_N5_R

312

USB30_TX_C_P1 USB30_TX_R_P1USB30_TX_P1

USB30_RX_C_P1

USB30_RX_C_N1

D13
AZC199-02S.R7 G_SOT23-3

EMC@

EMC

1 2

R95 0_0402_ 5%@

1 2

R96 0_0402_ 5%@

1 2

R97 0_0402_ 5%@

1 2

R93 0_0402_ 5%@

1 2

R94 0_0402_ 5%@

1 2

R98 0_0402_ 5%@

D

USB30_RX_R_N1

USB30_RX_R_P1

USB30_TX_R_P1

+USB_VCCA

USB20_P5_RUSB20_P5

USB20_N5_RUSB20_N5

USB30_RX_R_N1USB30_RX_N1

D12

9

10

8

9

7

7

6

6

AZ1045-04F_ DFN2510P10E-1 0-9

EMC@

C55

C1117

C125

C127

9
1
8
3
7
2
6
4
5

1

2

4

5

3

8

+

1 2

220U_6.3V_M

1 2

47U_0805_6. 3V6-M@

1 2

1U_0402_10V6K@

1 2

1U_0402_10V6K@

JUSB1

StdA_SSTX+
VBUS
StdA_SSTX­D+
GND_DRAIN
D­StdA_SSRX+
GND_1
StdA_SSRX-

ALLTO_C190AG-1093 9-L

USB30_RX_R_N1

1

USB30_RX_R_P1

2

USB30_TX_R_N1USB3 0_TX_R_N1

4

USB30_TX_R_P1

5

3

GND_2
GND_3
GND_4
GND_5

E

ME@

10
11
12
13

2 2

L30

USB30_RX_C_N2 USB30_RX_R_N2

USB30_RX_C_P2 USB30_RX_R_ P2

USB30_TX_C_N2 USB30_TX_ R_N2

USB30_TX_C_P2 USB30 _TX_R_P2

USB20_P6_S

USB20_N6_S

112

4

4

EXC24CH900U_4P

L29

112

4

4

EXC24CH900U_4P

L17

112

4

4

EXC24CH900U_4P

EMC@

EMC@

EMC@

2

3

3

2

3

3

USB20_P6_R

2

USB20_N6_R

3

3

USB30_TX_P29

USB30_TX_N29

USB30_RX_P29

USB30_RX_N29

1 2

C2058 0.2 2U_0402_16V6-K

USB30_TX_N2 USB3 0_TX_C_N2 USB30_TX_R_N2

1 2

C2057 0.2 2U_0402_16V6-K

USB30_RX_P2

1 2

C8789 0.3 3U_0402_10V6-K

USB30_RX_N2

1 2

C8790 0.3 3U_0402_10V6-K

USB30_TX_C_P2 USB30_TX_R_ P2USB30_TX_P2

USB20_P6_S

USB20_N6_S
USB30_RX_C_P2

USB30_RX_C_N2

1 2

R3119 0_0402_5%@

1 2

R3116 0_0402_5%@

1 2

R3103 0_0402_5%@

1 2

R942 0_0402_5%@

1 2

R3117 0_0402_5%@

1 2

R3114 0_0402_5%@

12

R537

R538

0_0402_5%

100K_0402_5%

@

Debug@

1 2

For USB Debug Function

3 3

EC_TX35,39

EC_RX35 ,39

USB20_P69

USB20_N69

USBDEBUG

Kernel debug

Set input

Set input

Set output Low

ENABLE

4 4

UARTA_P80_ EN

Set input

Set output Low

H

SOE #

LXL

HL

POST 80

DISABLE

ENABLE

FUNCTIO N

DISABLE

D(+/-) to 1D(+/-)

D(+/-) to 2D(+/-)

A

R533 0_0402_5%Debug@

R536 0_0402_5%Debug@

USBDEBUG7

12

12

EC_TX_C

EC_RX_C

UARTA_P80_EN

R531 0_ 0402_5%

U129

1

1D+

2

1D-

3

2D+

4

2D-

5

GND1

11

GND2

NCT3958Y_DFN10_3 X3

Debug@

R539 0_0402_5%@

R541 0_0402_5%@

Debug@

NCY3958Y

Debug@

2

G

B

12

VCC

OE#

12

12

+3VALW

12

R547
10K_0402_ 5%

USB_UART_SEL

13

D

L2N7002KWT1 G_SOT323-3
Q56

S

Debug@

USB_UART_SEL

10

9

S

8

D+

7

D-

6

USB20_P6_SUSB20_P6

USB20_N6_SUSB20_N6

R10456 0_0402_5 %Debug@

USB_UART_SEL

USB20_P6_S

USB20_N6_S

USB20_P6_R

USB20_N6_R

12

+3VALW

312

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE C ENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE C ENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUT URE C ENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

Close to ConnectorFOR ESD

D43
AZC199-02S.R7 G_SOT23-3

EMC@

2016/08/16

2016/08/16

2016/08/16

+USB_VCCA

AZ5725-01F.R7GR_DFN1006P2X2

Deciphered Date

Deciphered Date

Deciphered Date

1

D34

1

EMC_NS@

2

2

D

+USB_VCCA

1 2

C2060

1U_0402_10V6K@

1 2

C2059

1U_0402_10V6K@

JUSB3

9

StdA_SSTX+

1

VBUS

USB20_P6_R
UARTA_P80_EN
USB20_N6_R
USB30_RX_R_P2

USB30_RX_R_N2

2017/08/15

2017/08/15

2017/08/15

8

StdA_SSTX-

3

D+

7

GND_DRAIN

2

D-

6

StdA_SSRX+

4

GND_1

5

StdA_SSRX-

ALLTO_C190AG-1093 9-L

D45

USB30_RX_R_N2

USB30_RX_R_P2

USB30_TX_R_P2 USB30_ TX_R_P2

EMC@

9

10

8

9

7

7

6

6

AZ1045-04F_ DFN2510P10E-1 0-9

Title

Title

Title

USB3.0 PORT (LEFT)

USB3.0 PORT (LEFT)

USB3.0 PORT (LEFT)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Shee t of

Date: Shee t of

Date: Shee t of

ME@

GND_2
GND_3
GND_4
GND_5

USB30_RX_R_N2

1

1

USB30_RX_R_P2

2

2

USB30_TX_R_N2USB3 0_TX_R_N2

4

4

5

5

3

3

8

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

10
11
12
13

330ARR

330ARR

330ARR

28 5 2

28 5 2

28 5 2

E

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

D D

+3VALW

R133 0_0402_5%@

1 2

+3VS

R134 0_0402_5%@

1 2

TYPE_C_OCP#
VBUS_EN

C C

C2068 0.1U_0402_10V7K

R3146
10K_0402_5%

@

VBUS_EN

R3141
10K_0402_5%

1 2

C2067 0.1U_0402_10V7K

1 2

C2065 0.1U_0402_10V7K

1 2

C2066 0.1U_0402_10V7K

1 2

R3142
10K_0402_5%@

1 2

R4674
10K_0402_5%

1 2

USB30_RX_N39

USB30_RX_P39

USB30_TX_N39
USB30_TX_P39

+3V_MUX +3V_MUX

R3139

B B

A A

10K_0402_5%

1 2

M1 M0

R3144
10K_0402_5%@

1 2

+3V_MUX

1 2

1 2

+3V_MUX

PH at CPU side 09/06 wei

R3147
10K_0402_5%@

1 2

TYPE_C_OCP#

R3140
10K_0402_5%@

1 2

VMON

USB30_RX_N3_M
USB30_RX_P3_M

USB30_TX_N3_M
USB30_TX_P3_M

M1
M0

R3150

6.2K_0402_1%

1 2

Rp configuration

Rp:1.5A (now)

For C_VBUS
power switch enable pin

Rp:900mA

Rp:1.5A

Rp:3.0A

M1 M0

1

1 1

Power switch enable pin

High Active

For C_VBUS
power switch OCP pin

Power switch OCP pin

High Active

+3V_MUX +5V_MUX

U26

16

OCP_DET

15

VBUS_EN

17

VMON

4

SSRX_1P/2N

5

SSRX_1N/2P

10Gbps 2:1 MUX

6

SSTX_1P/2N

7

SSTX_1N/2P

23

NC

21

RP_SEL_M1

22

RP_SEL_M0

18

REXT

10

R3144/R3142 mount

0

R3139/R3143 mount

R3139/R3142 mount

R3146 mountLow Active

R3141 mount

R3147 mountLow Active

R3140 mount

Note

Note

Realtek

RTS5449

Note

+5VALW

+5VS

C_TX2_1P/2N
C_TX2_1N/2P

C_RX2_1P/2N
C_RX2_1N/2P

C_TX1_1P/2N
C_TX1_1N/2P

C_RX1_1P/2N
C_RX1_1N/2P

RTS5449-GR_QFN24_4X4

5

4

Remove ty pe-c redriver

R173 0_0402_5%@

1 2

R174 0_0402_5%@

1 2

2

CC1271

220P_0201_25V7-K

1

12

CC1

14

CC2

MUX_TX2_N

11

MUX_TX2_P

10

24
1

MUX_TX1_N

8

MUX_TX1_P

9

2
3

13

VCON_IN

LDO_3V3

5V_IN

E-PAD

R171 0_0402_5%@

19

R172 0_0402_5%

20

25

2

CC1272
220P_0201_25V7-K

1

CC1

A5

CC2

B5

C2076 0.1U_0402_10V7K

1 2

C2075 0.1U_0402_10V7K

1 2

C2073 0.1U_0402_10V7K

1 2

C2074 0.1U_0402_10V7K

1 2

1 2

1 2

1

CC1273

2

4.7U_0402_6.3V6M

C_TX2_N
C_TX2_P

C_RX2_N
C_RX2_P

C_TX1_N
C_TX1_P

C_RX1_N
C_RX1_P

+5V_MUX

+3V_MUX

2

C2063

1

0.1U_0201_6.3V6-K

Close Pin13

C2077

2

C2064

1

0.1U_0201_6.3V6-K

Close Pin19

@

R943 0_0402_5%

1 2

USB20_P79

USB20_N79

C_TX2_N

C_TX2_P C_TX2_P_C

C_RX2_P

C_RX2_N

L23

112

4

4

EXC24CH900U_4P

@

R91 0_0402_5%

1 2

R944 0_0402_5%@

L24

334

2

2

EXC24CH900U_4P

R3107 0_04 02_5%@

R100 0_0402_5%@

L25

334

2

2

EXC24CH900U_4P

R101 0_0402_5%@

1

2

EMC@

EMC@

EMC@

10U_0402_6.3V6M

12

12

12

12

B3
B2

A10
A11

A3
A2

B10
B11

VBUS_P0

2

3

3

4

1

1

4

1

1

+5VALW

47U_0805_6.3V6-M

12

R3155
200K_0402_1%

R3149
10K_0402_1%

1 2

3

1.5A

1

1

+

C213

VMON

C_DP

C_DM

C_TX2_N_C

C_RX2_P_C

C_RX2_N_C

C1333
150U_B2_6.3VM_R35M

@

2

2

VBUS_EN TYPE_C_OCP#

High active

VBUS_P0

D38

1

1

EMC_NS@

2

2

SPHV24-01ETG-C_SOD882-2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

VBUS_P0

U6

1

5

OUT

IN

2

GND

3

4

OCB

EN

SY6288C20AAC_SOT23-5

1

1

C919

C918

1 2

C_RX1_N

C_RX1_P

C_TX1_P C_TX1_P_C

C_TX1_N C_TX1_N_C

C922

@

2

2

4.7U_0805_25V6-K

10U_0805_25V6K

0.47U_0402_25V6K

R3135 0_04 02_5%@

1 2

L31

4

4

112

EXC24CH900U_4P

R3137 0_04 02_5%@

1 2

R3136 0_04 02_5%@

1 2

L32

4

4

112

EXC24CH900U_4P

R3138 0_04 02_5%@

1 2

2016/08/16

2016/08/16

2016/08/16

1

C8791
1000P_0201_50V7- K

EMC_NS@

2

1

1

C921

C920

2

2

0.47U_0402_25V6K

0.47U_0402_25V6K

EMC@

3

3

2

EMC@

3

3

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

TYPE_C_OCP# 9

1

C1334

2

C_TX2_P_C

C_TX2_N_C

C_RX1_N_C

C_RX1_P_C

Deciphered Date

Deciphered Date

Deciphered Date

2

0.47U_0402_25V6K

C_RX1_N_C

C_RX1_P_C

D36

9

10

8

9

7

7

6

6

AZ1045-04F_DFN2510P10 E-10-9

EMC_NS@

C_TX2_N_C

C_TX2_P_C

1

1

2

2

4

4

5

5

3

3

8

2017/08/15

2017/08/15

2017/08/15

28

GND525GND626GND727GND8

GND929GND1030GND1131GND12

HIGHS_UB11246-15A0C-1H

32

C_RX1_P_C

C_RX1_N_C

C_DM

C_DP

CC2

24

Power_GND_B12

23

SSRXp1_B11

22

SSRXn1_B10

21

VBUS_B9

20

SBU2_B8

19

Dn2_B7

18

Dp2_B6

17

CC2_B5

16

VBUS_B4

15

SSTXn2_B3

14

SSTXp2_B2

13

GND_B1

JP1

09/02 Update Type-C Conn. DC021608291 wei

CC1
CC2

312

D47

EMC_NS@

AZC199-02S.R7G_SOT23-3

C_TX2_P_C

C_TX2_N_C

C_RX1_N_C

C_RX1_P_C

C_TX1_P_C

C_TX1_N_C

C_RX2_P_C

9

10

8

9

7

7

6

6

For ESD

Title

Title

Title

Type-C RTS5449

Type-C RTS5449

Type-C RTS5449

Size Document Numb er Re v

Size Document Numb er Re v

Size Document Numb er Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date: Shee t o f

Date: Shee t o f

Date: Shee t o f

VBUS_P0

3A

ME@

1

GND_A1

2

SSTXp1_A2

3

SSTXn1_A3

4

VBUS_A4

5

CC1_A5

6

Dp1_A6

7

Dn1_A7

8

SBU1_A8

9

VBUS_A9

10

SSRXn2_A10

11

SSRXp2_A11

12

GND_A12

C_DP
C_DM

312

D48

AZC199-02S.R7G_SOT23-3

D20

EMC_NS@

1

1

2

2

4

4

5

5

3

3

8

AZ1045-04F_DFN2510P10 E-10-9

330ARR

330ARR

330ARR

1

C_TX1_P_C

C_TX1_N_C

CC1

C_DP

C_DM

C_RX2_N_C

C_RX2_P_C

EMC_NS@

C_TX1_P_C

C_TX1_N_C

C_RX2_N_CC_RX2_N_C

C_RX2_P_C

29 52

29 52

29 52

1.0

1.0

1.0

5

Vinafix.com

D D

C C

4

3

2

1

B B

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

2016/08/16

2016/08/16

2016/08/16

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2017/08/15

2017/08/15

Deciphered Date

Deciphered Date

Deciphered Date

3

2017/08/15

2

Titl e

Blank

Blank

Blank

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Friday, March 23, 2018

Friday, March 23, 2018

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

30 52

30 52

30 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

for USB HUB update to OHY50, manual modify PN to GL850G-OHY50

+3VS

D D

USB20_N5_HUB_R
USB20_P5_HUB_R
USB20_N1_C
USB20_P1_C

+AVDD

USB20_N3
USB20_P3

RREF_HUB
+AVDD

XTAL12_IN

XTAL12_OUT
USB20_N2
USB20_P2

+AVDD

C C

B B

A A

10
11
12
13
14

29

USB_HUB@

UH1

1

DM0

2

DP0

3

DM1

4

DP1

5

AVDD

6

DM2

7

DP2

8

RREF

9

AVDD1
X1
X2
DM3
DP3
AVDD2

PAD

GL850G

GL850G-OHY50_QFN28_5X5

PORT1

PORT2

PORT3

USB20_N5_HUB
USB20_P5_HUB

USB20_P1
USB20_N1

USB20_P3
USB20_N3

USB20_P2
USB20_N2

USB20_P5_HUB

USB20_N5_HUB

USB20_N1_C

V33

V5

PWREN1#/SDA
OVCUR1#/SMC
OVCUR2#/SMD

QFN28

PGANG

PSELF

DVDD
OVCUR3#
OVCUR4#
TEST/SCL

RESET#

DP4

DM4

Camera

FP

Touch Screen

USB20_N5_HUB 9
USB20_P5_HUB 9

USB20_P1 26
USB20_N1 26

USB20_P3 40
USB20_N3 40

USB20_P2 26
USB20_N2 26

1 2

RH16 0_0201_ 5%NFPTS@

1 2

RH17 0_0201_5%NFPTS@

USB_HUB@

1 2

RH18 0_0201_5%

USB_HUB@

1 2

RH19 0_0201_5%

USB_HUB@

1 2

RH20 0_0201_5%

USB_HUB@

1 2

RH21 0_0201_5%

28

27
26
25
24
23

22

21
20
19
18
17

16

15

+VDD
V5

SDA_HUB

PGANG
PSELF

TEST/SCL
HUB_RESET#

Camera

Finger Print

Touch Screen

USB20_N1USB20_N5_HUB
USB20_P1

USB20_N5_HUB_R

USB20_P5_HUB_RUSB20_P5_HUB

USB20_N1

USB20_P1USB20_P1_C

1

TP271 @

RH4

1

TP270 @

1 2

@

0_0402_5%

+VDD

1

CH1

0.1U_0201_6.3V6-K

USB_HUB@

2

CH9
15P_0402_50V8J

USB_HUB@

YH1

1

XTAL12_IN

1

2

OSC1

2

GND1

12MHZ_10PF_7V12000008

USB_HUB@

As close to GL850G

+5VALW

RH8

10K_0402_5%

@

HUB_RESET#

CH11

1U_0402_6.3V6K

USB_HUB@

0604

0604

3

OSC2

4

GND2

+VDD

12

12

RH9
10K_0402_5%

USB_HUB@

12

1

RH12
47K_0402_5%

@

2

XTAL12_OUT

1

CH10
18P_0402_50V8J

2

USB_HUB@

10U_0603_6.3V6M

Vienna change to 619 ohm for Eye Diagram test

RREF_HUB

PGANG

PSELF

1 2

1 2

1 2

+3VALW

** External regulator mode
RH1 install，RH2 non-install,RH15 install
Internal regulator mode
RH1 non-install，RH2 install,RH15 non-install

+VDD

1 2

1

CH2

USB_HUB@

2

CH2 close to PIN28

RH11

680_0402_1%

USB_HUB@

RH13

100K_0402_5%

USB_HUB@

RH14

10K_0402_5%

USB_HUB@

+VDD

@

1 2

RH1 0_0603_5%

1 2

RH3 0_0603_5%@

+AVDD

RH6

@

0_0603_5%

1

CH3

0.1U_0201_6.3V6-K

USB_HUB@

2

Individual Mode

Self-power

+VDD

+VDD

+5VALW

@

1 2

RH15

1 2

@

RH2 0_0603_5%

0_0603_5%

V5

V5

：

：

+AVDD

CH5

USB_HUB@

CH4

1

2

.1U_0402_10V6-K

0.1U_0201_6.3V6-K

1

2

@

As close to GL850G

CH3 PIN5 CH4/CH5 PIN9 CH6/CH15 PIN14

CH6

1U_0402_6.3V6K

1

2

USB_HUB@

CH7

1

2

CD@

CH8

1U_0402_6.3V6K

.1U_0402_10V6-K

1

CD@

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

Titl e

Titl e

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2013/08/15

2013/08/15

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/15

2

Titl e

USB HUB

USB HUB

USB HUB

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Friday, March 23, 2018

Friday, March 23, 2018

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

31 52

31 52

31 52

1.0

1.0

1.0

5

+3VALW_LAN rising t i me ( 10 %~90 %):

Vinafix.com

4

3

2

1

+3VALW TO +3VALW_LAN

+3VALW +3VA LW_LAN

D D

LAN_PWR_ON#39

RL2

100K_0402_5%

@

+3VALW

12

RL3

1 2

@

47K_0402_5%

JL1

1

CL8

0.1U_0201_6.3V6-K

@

2

Need short

2

112

JUMP_43X79

LP2301ALT1G_SOT23-3

Q14

D

S

13

@

G

2

@

CL9

@

0. 5ms＜s p ec＜ 1 0 0ms

1

CL4

1

2

2

SIT1CD@

0.01U_0201_10V6K

width : 40 mils

1

CL5

2

4.7U_0402_6.3V6M

SIT1CD@

1

CL6

2

4.7U_0402_6.3V6M

1

CL7

2

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

Close to Pin11 Close to Pin32Close to Pin11 Close to Pin32

+3VALW_LAN +LAN_V DDREG

@

1 2

RL1 0_0603_5%

1

CL1

4.7U_0402_6.3V6M

2

SIT1CD@

1

CL2

0.1U_0201_6.3V6-K

2

SIT1CD@

+3VALW_LAN +3VS

+3VALW_LAN

RL5
10K_0402_5%

@

1 2

YL1

OSC1

GND2

GND12OSC2

PCIE_WAKE#_R

4

3

PLT_RST#7,17,35
PCIE_PRX_DTX_N24
PCIE_PRX_DTX_P24

LAN_XTALI

LAN_XTALO

1

CL13
12P_0402_50V8-J

2

1 2

RL8

2.49K_0402_1%

1 2

RL12

0_0402_5%

CL10 0.1U_0201_6.3V6-K
CL11 0.1U_0201_6.3V6-K

CL10 close to Pin18
CL11 close to Pin17

TL3 @

@

TL4 @

12
12

For RTL8111GUL/ RTL8106EUL (SWR mode)
For RTL8111H (LDO mode) RL19 stuf f

+LAN_REGOUT

Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil

+3VALW_LAN
RSET

+LAN_VDD10
LAN_XTALO
LAN_XTALI

1

LAN_DISABLE#LAN_PWR_ON#

1

+LAN_REGOUT

+LAN_VDDREG
+LAN_VDD10
PCIE_WAKE#_R

ISOLATE#

PLT_RST#
PCIE_PRX_C_DTX_N2
PCIE_PRX_C_DTX_P2

RL19 0_0805_5%

LL1

2.2UH_NLC252018T-2R2J-N_5%

1 2

RL7 0_0402_5%@
RL6 0_0402_5%@

1 2

@

0_0402_5%

CL12

10P_0402_50V8J

1 2

LAN_PWR_ON#

1

2

1

25MHZ_10PF_7V25000014

+3VS

12

ISOLATE#

12

PCIE_WAKE#7,35,39

LAN_WAKE#35,39

RL9
1K_0402_1%

RL11
15K_0402_5%

@

RL10

C C

B B

follow G CarrizoL 10pf

UL1

33

GND

32

AVDD33_2

31

RSET

30

AVDD10

29

CKXTAL2

28

CKXTAL1

27

LED0

26

LED1/GPIO

25

LED2

24

REGOUT

23

VDDREG

22

DVDD10

21

LANWAK EB

20

ISOLATEB

19

PERSTB

18

HSON

17

HSOP

RTL8111GUL-CG_QFN32_4X4

8111GUL@

8111H@

1 2

1 2

8111GUL@

4.7U_0402_6.3V6M

CL15

1

2

REFCLK_N
REFCLK_P

HSIN

HSIP
CLKREQB
AVDD33_1

MDIN3
MDIP3

AVDD10_2

MDIN2
MDIP2
MDIN1
MDIP1

AVDD10_1

MDIN0
MDIP0

1

CL16

0.1U_0201_6.3V6-K

2

CLK_PCIE_LAN#

16

CLK_PCIE_LAN

15

PCIE_PTX_C_DRX_N2

14

PCIE_PTX_C_DRX_P2

13

LAN_CLKREQ#_R

12

+3VALW_LAN

11

LAN_MDI3-

10

LAN_MDI3+

9

+LAN_VDD10

8

LAN_MDI2-

7

LAN_MDI2+

6

LAN_MDI1-

5

LAN_MDI1+

4

+LAN_VDD10

3

LAN_MDI0-

2

LAN_MDI0+

1

+LAN_VDD10

1

CL17

0.1U_0201_6.3V6-K

2

CLK_PCIE_LAN# 8
CLK_PCIE_LAN 8
PCIE_PTX_C_DRX_N2 4
PCIE_PTX_C_DRX_P2 4

LAN_MDI3- 33
LAN_MDI3+ 33

LAN_MDI2- 33
LAN_MDI2+ 33
LAN_MDI1- 33
LAN_MDI1+ 33

LAN_MDI0- 33
LAN_MDI0+ 33

1

CL18

0.1U_0201_6.3V6-K

2

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

LAN_CLKREQ#_R

1

CL19

0.1U_0201_6.3V6-K

2

RL4

10K_0402_5%

@

1 2

APU CLKREQ all both 3VS pow er plane

1

CL20

0.1U_0201_6.3V6-K

2

2

G

QL1

1 3

2N7002KW_SOT323-3

1 2

RL18 0_0402_5%@

2018/01/24: add AZ5815-01F.R7GR for
RTL8111H Lan Surge is sue

D

+LAN_VDD10

1

2

S

1

2

@

DL4

AZ5815-01F.R7GR_DFN1006P2E

EMC_8111H@

Change part number

1

CL21
1U_0402_6.3V6K

2

@

LAN_CLKREQ# 8

1

CL22

0.1U_0201_6.3V6-K

@

2

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

2013/08/08

2013/08/08

2013/08/08

3

Deciphered Date

2

2013/08/05

2013/08/05

2013/08/05

Titl e

LAN_RTL8111GUL

LAN_RTL8111GUL

LAN_RTL8111GUL

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Shee t o f

Date : Shee t o f

Date : Shee t o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

32 52

32 52

32 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

TL1

PJ5909

112

24

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19

MX2-

18

MCT3

17

MX3+

16

MX3-

15

MCT4

14

MX4+

13

MX4-

BOTH_GST5009 LF

8111GUL@

2

MX1+

3

MX1-

5

MX2+

6

MX2-

8

MX3+

9

MX3-

11

MX4+

12

MX4-

4

NC1

7

NC2

10

NC3

1

GND

@

2

CHASSIS1_GND

LAN_MDI0+

LAN_MDI0-

LAN_MDI1+

LAN_MDI1-

LAN_MDI2+

LAN_MDI2-

LAN_MDI3+

LAN_MDI3-

TCT

MCT

TCT

LAN_MDI0+

LAN_MDI0-

LAN_MDI1+

LAN_MDI1-

LAN_MDI2+

LAN_MDI2-

LAN_MDI3+

LAN_MDI3-

TL2

23

TD1+

22

TD1-

20

TD2+

19

TD2-

17

TD3+

16

TD3-

14

TD4+

13

TD4-

24

TCT1

21

TCT2

18

TCT3

15

TCT4

AJOHO_N-8660GR

8111H@

JUMP_43X39

LAN_MDI3+

D D

C C

B B

LAN_MDI3-

LAN_MDI1+

LAN_MDI1-

Place Close to TL1
Change part number

DL1

4

I/O3

5

VDD

6

I/O4

AZ1135-04S.R7G_SOT23 -6L-6

EMC_8111H@

DL2

4

I/O3

5

VDD

6

I/O4

AZ1135-04S.R7G_SOT23 -6L-6

EMC_8111H@

GND

GND

1 2

RL14 0_0603_5%

1 2

RL15 0_0603_5%

1 2

RL16 0_0603_5%

1 2

RL20 0_0603_5%

I/O2

I/O1

I/O2

I/O1

@

@

@

@

3

2

1

3

2

1

LAN_MDI2-

LAN_MDI2+

LAN_MDI0-

LAN_MDI0+

EMC

1

CL24

0.01U_0201_25V6-K

8111GUL@

2

EMC

LAN_MDI0+32

LAN_MDI0-32

LAN_MDI1+32

LAN_MDI1-32

LAN_MDI2+32

LAN_MDI2-32

LAN_MDI3+32

LAN_MDI3-32

EMC

TCT1

TD1+

TD1-

TCT2

TD2+

TD2-

TCT3

TD3+

TD3-

TCT4

TD4+

TD4-

LAN_MDO0+

LAN_MDO0-

LAN_MDO1+

LAN_MDO1-

LAN_MDO2+

LAN_MDO2-

LAN_MDO3+

LAN_MDO3-

MCT

1

2

3

4

5

6

7

8

9

10

11

12

MCT

LAN_MDO0+

LAN_MDO0-

MCT

LAN_MDO1+

LAN_MDO1-

MCT

LAN_MDO2+

LAN_MDO2-

MCT

LAN_MDO3+

LAN_MDO3-

0.022U_0603_50V7K

CL32

8111GUL@

LAN_MDO0+

LAN_MDO0-

LAN_MDO1+

LAN_MDO2+

LAN_MDO2-

LAN_MDO1-

LAN_MDO3+

LAN_MDO3-

12

8111GUL@

RL17
20_0603_5%

1

2

CHASSIS1_GND

JRJ1

1

TX_DA+

2

TX_DA-

3

RX_DB+

4

BI_DC+

5

BI_DC-

6

RX_DB-

7

BI_DD+

8

BI_DD-

ALLTO_C10235-108 39-L

1

CL25
1000P_1206_2KV7-K

8111GUL@

2

EMC

ME@

GND_4

GND_3

GND_2

GND_1

1

DL3

1

BS4200N-C-LV_SMB-F2

8111GUL@

2

EMC

2

12

11

10

9

CHASSIS1_GND

CHASSIS1_GND

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/05

2013/08/05

2013/08/05

2

Titl e

LAN_Transformer

LAN_Transformer

LAN_Transformer

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

33 52

33 52

33 52

1.0

1.0

1.0

5

Vinafix.com

Close to U1

2200P_0402_25V7-K

D D

C44

@

1

2

REMOTE+_R

REMOTE-_R

REMOTE+_R

REMOTE-_R

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

SMSC thermal sensor
placed near DIMM

+3VS

1

C47

0.1U_0201_6.3V6-K

@

2

+3VS

C C

+5VLP

REMOTE+_R

REMOTE-_R

R51

10K_0402_5%

1

C4

0.1U_0201_6.3V6-K

@

2

@

over temperature threshold:
RSET=3*RTMH
92+/-30C

B B

Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

F5

NEC@

NONEC@

C2081

0.1u_0201_10V6K

@

21

1

2

+5VS

A A

1A_32V_ERBRD1R00X

1 2

R4682 0_0603_5%

1

C2080
10U_0603_6.3V6M

2

U1

1

VDD

2

D+

3

12

D-

4

T_CRIT#

NCT7718W_MSOP8

Address 1001_101xb

HW thermal sensor

@

U4

1

VCC

2

GND

3

OT1

4

OT2

G718TM1U_SOT23-8

EC_FAN_SPEED39
EC_FAN_PWM39

2

CC1280
10U_0402_6.3V6M

@

1

TMSNS1

RHYST1

TMSNS2

RHYST2

8

7

6

5

SCL

SDA

ALERT#

GND

TMSNS1

PHYST1

TMSNS2

PHYST2

+5VS_FAN

4

1 2

R175 0_0402_5%@

1 2

R176 0_0402_5%@

1 2

R177 0_0402_5%@

1 2

R178 0_0402_5%@

THERMAL_SMB_CK2

8

THERMAL_SMB_DA2

7

6

5

@

1 2

R6 10K_0402_5%@

1 2

R7 10K_0402_5%@

FAN Conn

JFAN1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_85205-04001

ME@

R252

21.5K_0402_1%

@

REMOTE1+

REMOTE2+

REMOTE2-

REMOTE1-

THERMAL_SMB_CK2 39

THERMAL_SMB_DA2 39

+5VLP +5VLP

R253

21.5K_0402_1%

@

1 2

1 2

R196 0_0402_5%@

R197 0_0402_5%@

+3VALW

+3VS

1 2

1 2

RTPM13 0_0402_5%@

RTPM14 0_0603_5%@

RTPM15 0_0603_5%@

+3VS

1 2

1 2

1 2

3

REMOTE1+

100P_0201_25V8J

REMOTE1-

NTC_V1

NTC_V2

+3VALW

RTPM12 0_0603_5%@

RTPM1 0_0603_5%TPM@

20mA

1

C45

@

2

NTC_V1

1 2

1 2

11
18

12
13
14

Near GPU&VRAM

C

2

Q15

B

MMBT3904WH_SOT323-3

E

@

3 1

+3VALW

12

12

1 2

EC_AGND

NTC_V1 39

NTC_V2 39EC_ON_R48

TPM

UTPM1

1

NC_1

2

NC_2

3

NC_3

7

PP

6

NC_4

9

NC_7

4

GND_1
GND_2
GND_3

5

NC_5

8

NC_6
NC_8
NC_9
NC_10

Z32H320TC_TSSOP28

2

R17

13.7K_0402_1%

PX@

PH2
100K_0402_1%_NCP15WF104F03RC

PX@

R184
0_0402_5%

@

CLK_RUN#

R185
0_0402_5%

@

1 2

THERMAL_SMB_CK2

THERMAL_SMB_DA2

1

CTPM1
10U_0603_6.3V6M

2

@

TPM@

24

VDD3

10

VDD1

28

LPCPD#

27

SERIRQ

26

LAD0

23

LAD1

22

LFRAME#

20

LAD2

17

LAD3

25

GND_4

21

LCLK

19

VDD2

15

16

LRESET#

14

23

R4689

R4690

SERIRQ_TPM
LPC_AD0_TPM
LPC_AD1_TPM
LPC_FRAME#_TPM
LPC_AD2_TPM
LPC_AD3_TPM

REMOTE2+

100P_0201_25V8J

REMOTE2-

R4688

2.2K_0404_4P2R_5%

@

1 2

@

0_0402_5%

0_0402_5%

RTPM2 10K_0402_5%TPM@

RTPM11 0_0402_5%TPM@
RTPM16 0_0402_5%TPM@

1 2

@

1 2

1 2
1 2

2N7002KDWH_SOT363-6

+3VS_TPM

1

2

RTPM5 0_0402_5%TPM@
RTPM6 0_0402_5%TPM@
RTPM7 0_0402_5%TPM@
RTPM8 0_0402_5%TPM@
RTPM9 0_0402_5%TPM@
RTPM10 0_0402_5%TPM@

1

C46

NTC_V2

G

S

CTPM3

0.1U_0201_6.3V6-K

TPM@

1 2
1 2
1 2
1 2
1 2
1 2

APU_LPC_RST# 8,13,39

2

B

@

2

+3VALW

12

12

1 2

+3VS+3VS

2

Q160A

61

@

D

G

S

2N7002KDWH_SOT363-6

+3VS_TPM

E

EC_AGND

5

1

Near CPU core

C

Q16

MMBT3904WH_SOT323-3

@

3 1

Near CPU

R25

13.7K_0402_1%

PH3
100K_0402_1%_NCP15WF104F03RC

R191
0_0402_5%

@

Q160B

34

@

D

R192
0_0402_5%

@

1 2

EC_SMB_CK2 39,49

EC_SMB_DA2 39,49

SERIRQ 8,13,39

LPC_AD0 8,13,39
LPC_AD1 8,13,39
LPC_FRAME# 8,13,39
LPC_AD2 8,13,39
LPC_AD3 8,13,39

TPM_CLK 8

LPC_CLKRUN# 8,13

+3VS_TPM

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

4

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/05

2013/08/05

2013/08/05

Titl e

Titl e

Titl e

Thermal sensor/FAN CONN/TPM

Thermal sensor/FAN CONN/TPM

Thermal sensor/FAN CONN/TPM

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Dat e: Sheet of

Dat e: Sheet of

2

Dat e: Sheet of

Friday, March 23, 2018

330ARR

330ARR

330ARR

34 52

34 52

34 52

1

1.0

1.0

1.0

A

Vinafix.com

B

C

D

E

Mini-Express Card(WLAN/WiMAX)

1 1

+3VS_WLA N

PCIE_PTX_C_DRX_P14
PCIE_PTX_C_DRX_N14

PCIE_PRX_DTX_P14
PCIE_PRX_DTX_N14

CLK_PCIE_W LAN8
CLK_PCIE_W LAN#8

1

C53

0.1U_0201_6.3V6-K

@

2

USB20_P09
USB20_N09

WLAN_C LKREQ_Q#
PCIE_WAK E#_WLAN

JWLA N1

1

GND1

3

USB_D+

5

USB_D-

7

GND2

9

SDIO_CLK

11

SDIO_CMD

13

SDIO_DATA0

15

SDIO_DATA1

17

SDIO_DATA2

19

SDIO_DATA3

21

SDIO_WAKE#

23

SDIO_RESET#

25
27
29
31

33

GND3

35

PETP0

37

PETN0

39

GND4

41

PERP0

43

PERN0

45

GND5

47

REFCLKP0

49

REFCLKN0

51

GND6

53

CLKREQ0#

55

PEWAKE0#

57

GND7

59

RSRVD/PETP1

61

RSRVD/PETN1

63

GND8

65

RSRVD/PERP1

67

RERVD/PERN1

69

GND9

71

RSRVD/REFCLKP1

73

RSRVD/REFCLKN1

75

GND10

77

GND15

ARGOS_NASE0-S67 01-TS40

ME@

3.3VAUX1

3.3VAUX2
LED1#

PCM_CLK/I2S_SCK

PCM_SYNC/I2S_WS

PCM_IN/I2S_SD_IN

PCM_OUT/I2S_SD_OUT

KEY E
PIN24~PIN31 NC PIN

UIM_POWER_SNK/CLKREQ1#

UIM_POWER_SRC/GPIO1/PEWAKE1#

LED#2

GND11

UART_WAKE#

UART_RXD

UART_TXD
UART_CTS

UART_RTS
VENDOR_DEFINED1
VENDOR_DEFINED2
VENDOR_DEFINED3

COEX3
COEX2
COEX1

SUSCLK

PERST0#
W_DISABLE2#
W_DISABLE1#

I2C_DATA

I2C_CLK

ALERT#

RSRVD

UIM_SWP/PERST1#

3.3VAUX3

3.3VAUX4

GND14

+3VS_WLA N

2
4
6
8
10
12
14
16
18
20
22

24
26
28
30

32
34
36
38
40
42
44
46
48
50
52
54
56

58
60
62
64
66
68
70
72
74

76

1

T7@

1

T6@

SUSCLK_R
PLT_RST#
BT_OFF#
WLAN_O FF#

APU_SMB_DATA_R
APU_SMB_CLK_R

EC_TX_R

+3VS_WLA N

1 2

R88 0_040 2_5%@

1 2

R55 0_040 2_5%

1 2

R53 1K_0402_5%

1 2

R56 0_040 2_5%@

1 2

R58 0_0402_5%@

1 2

R59 0_0402_5%@

1 2

R89 0_040 2_5%@

12

R186
100K_0402_5%

+3VS

EC_RX 28,39

SUSCLK 8
PLT_RST# 7,17,32

PCH_BT_OFF# 8

PCH_W LAN_OFF# 8

APU_SMB_DATA 7,14
APU_SMB_CLK 7,14

EC_TX 28,39

PCIE_WAK E#7,32 ,39
LAN_WA KE#32,39

Need short

@

J2

112

JUMP_43X79

2

R61 0_0402_5%@
R262 0_0402_5%@
R57 0_0402_5 %@

1 2
1 2
1 2

+3VS

2 2

WLAN_C LKREQ#8

3 3

1

C8793

0.1U_0201_6.3V6-K

@

2

SUSCLK_R

M74VHC1GT125DF2G_SC 70-5

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

B

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

2013/08/08

2013/08/08

2013/08/08

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/05

2013/08/05

2013/08/05

D

U130

5

Vcc

4

OUT_Y

@

Titl e

Titl e

Titl e

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

1

OE

2

IN_A

3

GND

NGFF WLAN

NGFF WLAN

NGFF WLAN

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

SUSCLK

330ARR

330ARR

330ARR

E

35 52

35 52

35 52

1.0

1.0

1.0

5

Vinafix.com

+3VALW

1 2

RA213 0_0402_5%@

+3VS

1 2

RA216 0_0402_5%@

+1.8VS

RA227 0_0402_5%@

+1.8VALW

D D

Analog power for mixers, & IO ports

C C

RA228 0_0402_5%@

+5VS +5VA

@

1 2

RA7 0_0603_5%

2

CA42

0.1U_0201_6.3V6-K

@

1

+3VALW

+3VS +3VS_CARD

1U_0402_6.3V6K

1

ABR USB leakage issue, card reader power need 3VALW

C2062

2

+3VL

RA203 0_0402_5%@

To solve the background noise while combojack c onnecting to an
active speaker and system entry into S3/S4/S5 without analog power.

Digital power for HDA link

12

12

2

1

12

Power supply for full-bridge left/Right channel

+5VS +5VD

EMC_NS@

1 2

LA25 BLM15PD600SN1D_2P

@

1 2

RA10 0_0603_5%

CA20

1U_0402_6.3V6K

1 2

RA220 0_0402_5%@

1 2

RA219 0_0402_5%@

Power for combo jack depop circuit at system
shutdown mode

VDD_STB

DVDD_IO

2

CA2

0.1U_0201_6.3V6-K

1

Close to Pin7

CA178 10U_0603_6.3V6M

1

2

CA19 0.1U_0201_6.3V6-K

CA18 0.1U_0201_6.3V6-K

2

2

1

1

4

+1.8VS +1.8V_AUDIO

RA225 0_0402_5%@

12

8/29 Ad d +1.8VS Circuit for Audio wei

DMIC_DATA
DMIC_CLK

HDA_SDIN0 SD ATA_IN

+3VS

PLUG_IN

SD_CMD_R
SD_D3_R
SD_D2_R

USB20_N4 USB20_N4_R
USB20_P4 USB20_P4_R

CW18

4.7U_0402_6.3V6M

DA1

2

1

3

LBAT54CWT1G_SOT323-3

MICBIASB

HDA_SDOUT_AUDIO7
HDA_BITCLK_AUDIO7

HDA_SDIN07

HDA_SYNC_AUDIO7

RING2_CONN
RING3_CONN

1 2

RA38 2.2K_0402_5%

1 2

RA37 2.2K_0402_5%

USB20_N49
USB20_P49

EC_MUTE#39

BEEP#39

PCH_BEEP7

DMIC_DATA26

DMIC_CLK26

SD_CMD_R37
SD_D3_R37
SD_D2_R37

+3VS_CARD

12

RA19 0_0402_5%@

12

RA18 0_0402_5%@

1 2

CA1 2.2U_0402_6.3V6M

1 2

RA16 33_0402_5%

DVDD_IO

1 2

RA205 100K_0402_1%

1 2

RA204 200K_0402_1%

1 2

CA41 2.2U_0402_6.3V6M

1 2

CW1 1U_0402_6.3V6K

1 2

CW2 1U_0402_6.3V6K

1 2

RW11 6.2K_0402_1%

12

RW12 0_0402_5%@

12

RW13 0_0402_5%@

1

2

RA35 0_0402_5%@

CARD_3V3

1

CW19

0.1U_0201_6.3V6-K

2

DA4

1 2

@

LRB751V-40T1G_SOD323-2

12

12

RA211 0_0402_5%@

3

DMIC_DATA_R
DMIC_CLK_R
HDA_SDOUT_AUDIO
HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO
PC_BEEP

JSENSE

VDD_STB

LINE1_R
LINE1_L

RREF

SPKR_MUTE#EC_MUTE#

12

RA43
10K_0402_5%

1 2

CA40

12

RA14
10K_0402_5%

UA1

1

HD-GPIO0/D MIC-DATA

2

HD-GPIO1/D MIC-CLK

3

HD-SDATA-OUT

4

HD-BCLK

5

HD-LDO3-CAP

6

HD-SDATA-IN

7

HD-DVDD-IO

8

HD-SYNC

9

HD-PCBEEP

10

HD-JD1(HP/LIN E1)

11

HD-MIC2-L(RING )

12

HD-MIC2-R(SLE EVE)

13

HD-3V5V-STB

14

HD-MIC2-CAP

15

HD-LINE1-R

16

HD-LINE1-L

17

HD-LINE2-R

18

HD-LINE2-L

19

CR-SD-CMD

20

CR-SD-DAT[3]

21

CR-SD-DAT[2]

22

CR-SDREG

23

CR-TEST1

24

CR-V18-CAP

25

CR-RREF

26

CR-DM

27

CR-DP

28

CR-3V3-IN

29

CR-SD-3V3

RTS5199-CG_QFN56_7X7

0.1U_0201_6.3V6-K

2

30

CR-GPIO

CR-SD-CD

CR-SD-WP
CR-SD-DAT[1]
CR-SD-DAT[0]

CR-SD-CLK

HD-AVDD1

HD-LDO1-CAP

HD-VREF

HD-MIC2-VREF O

HD-LINE1-VRE FO-L

HD-HPOUT-L

HD-HPOUT-R

HD-CPVEE

HD-CPVDD

HD-LDO2-CAP

HD-AVDD2

HD-PVDD1

HD-SPKOUT-LP
HD-SPKOUT-LN

HD-SPKOUT-RN

HD-SPKOUT-RP

HD-PVDD2

HD-DVDD

GNDPAD

PC_BEEPPC_BEEP1

SD_CD#

31

SD_WP

32

SD_D1_R

33

SD_D0_R

34

SD_CLK_R

35
36

+5VA
LDO1_CAP

37
38
39

MICBIASB
LINE1_VREF_L

40

HPOUT_L

41

HPOUT_R

42
43
44

HD-CBN

45
46

HD-CBP

HD_LDO2

47
48
49

+5VD
SPK_L+

50

SPK_L-

51

SPK_R-

52

SPK_R+

53
54

+5VD
SPKR_MUTE#

55

HD-PDB

56

57

LINE1_L

CA45 1U_0402_6.3V6K

LINE1_VREF_L

RA41 4.7K_0402_5%

HPOUT_L A_HP_OUTL_R

LINE1_VREF_L

RA42 4.7K_0402_5%

LINE1_R

CA46 1U_0402_6.3V6K

1 2

CA43 2.2U_0402_6.3V6M

1 2

CA44 1U_0402_6.3V6K

1 2

CA47 1U_0402_6.3V6K

1 2

CA185 10U_0603_6.3V6M

1 2

1 2

1 2

1 2

SD_CD# 37
SD_WP 37
SD_D1_R 37
SD_D0_R 37
SD_CLK_R 37

+1.8V_AUDIO

+3VS

Analog power for DACs, ADCs

Digital power for digital I/O circuit

2

2

0.1U_0201_6.3V6-K

1U_0402_6.3V6K

CA180

CA179

1

1

1 2

RA21 51_0402_1%

1 2

RA20 51_0402_1%

1 2

CA48 1U_0402_6.3V6K

12

CA44.7U_0603_6.3V6K

@

A_HP_OUTR_RHPOUT_R

+1.8V_AUDIO

1

2

1

CC257
10U_0603_6.3V6M

1 2

HDA_RST_AUDIO#7

B B

RING3_CONN
RING2_CONN
A_HP_OUTL_R
A_HP_OUTR_R
PLUG_IN

1

C185

EMC_NS@

A A

2

RA217 0_0402_5%@

1 2

RA1 0_0402_5%

EMC_NS@

1 2

RA4 0_0402_5%

EMC_NS@

RA9 0_0402_5%@

1 2

RA12 0_0402_5%

EMC_NS@

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

1

1

DA5

1

EMC_NS@

2

47P_0201_25V8-J

2

1

DA6

1

1

EMC_NS@

2

2

2

2

1

TC203@

JSPK1

470P_0201_50V7-K

ME@

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_88231-04001

JHP1

3

G/M

1

L

5

5

6

6

2

R

4

M/G

7

MS

SINGA_2SJ3095-140111F

ME@

1 2

RA223 15_0402_5%CD@

1 2

RA224 15_0402_5%CD@

1 2

RA32 15_0402_5%CD@

1 2

RA33 15_0402_5%CD@

LW2

USB20_N4 USB20_N4_R

12

GNDAGND

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

DA7

EMC_NS@

1

1

1

2

2

DA9

DA8

1

EMC_NS@

EMC_NS@

2

2

1

CA38

2

EMC_NS@

100P_0201_25V8J

USB20_P4

FOR EMI

1

CA39

2

100P_0201_25V8J

EMC_NS@

1

4

EXC24CH900U_4P

EMC_NS@

1

4

DMIC_CLK

DMIC_DATA

2

2

USB20_P4_R

3

3

CA23

1

2

22P_0201_258J

22P_0201_258J

EMC_NS@

2

2

CA183

CA184

1

1

220P_0201_25V7-K

220P_0201_25V7-K

CD@

CD@

EMC_NS@

1 2

RA27 27_0402_5%

CA24

CA25

1

2

EMC_NS@

CA26

1

1

2

2

EMC_NS@

33P_0201_50V8-J

33P_0201_50V8-J

EMC_NS@

220P_0201_25V7-K

CD@

CA29

2

1

220P_0201_25V7-K

CD@

2

CA30

1

HDA_SYNC_AUDIO
HDA_SDOUT_AUDIO
HDA_BITCLK_AUDIO
HDA_SDIN0

For EMI

SPK_R+
SPK_R­SPK_L+
SPK_L-

R3124

R3123

RA222 0_0402_5%@
RA221 0_0402_5%@
RA30 0_0402_5%@
RA34 0_0402_5%@

1 2

@

0_0402_5%

1 2

@

0_0402_5%

12
12
12
12

1 2

C232

1 2

C184

SPK_R+_CONN
SPK_R-_CONN
SPK_L+_CONN
SPK_L-_CONN

CA31

1

EMC@

2

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K

CA182

CA181

CA32

1

1

EMC@

EMC@

EMC@

2

2

8/16 Upd ate Audio Jack P/N SP011509163 wei

Audio Jack

RING2_CONN
A_HP_OUTL_R

470P_0201_50V7-K@

PLUG_IN

A_HP_OUTR_R

470P_0201_50V7-K@

RING3_CONN

1

1

C182

C183

EMC@

EMC@

2

2

100P_0201_25V8J

100P_0201_25V8J

1

2

8/16 Upd ate Audio Jack P/N DC021608101 wei

Titl e

Titl e

Titl e

Codec & CR_RTS5199

Codec & CR_RTS5199

Codec & CR_RTS5199

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

330ARR

330ARR

330ARR

36 52

36 52

36 52

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2016/08/16

2016/08/16

2016/08/16

LC Future Center Sec ret Data

LC Future Center Sec ret Data

LC Future Center Sec ret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2017/08/15

2017/08/15

2017/08/15

1.0

1.0

1.0

5

Vinafix.com

D D

4

3

CARD_3V3

2

1

SD / MMC

SD_CD#36
SD_WP36

CARD_3V3

1

1

2

2

1

CW17

0.1U_0201_6.3V6-K

2

DW1

AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@

FOR ESD

SD_D3
SD_CMD

SD_CLK

SD_D0
SD_D1
SD_D2

SD_CD#
SD_WP

JREAD1

1

CD/DAT3

2

CMD

3

VSS1

4

VDD

5

CLK

6

VSS2

7

DAT0

8

DAT1

9

DAT2

10

CARDDET ECT

11

WRITE PROTECT

T-SOL_5-251301001000-6_NR

ME@

SH1
SH2
SH3
SH4

8/16 Update Conn. P/N SP07000WG00 wei

12
13
14
15

SD_D0_R36

SD_D1_R36

C C

B B

SD_D2_R36

SD_D3_R36

SD_CMD_R36

SD_CLK_R36

SD_D0_R

SD_D1_R

SD_D2_R

SD_D3_R

RW3 0_0402_5%@

RW4 0_0402_5%@

RW5 0_0402_5%@

RW6 0_0402_5%@

RW7 0_0402_5%@

RW8 0_0402_5%@

12

12

12

12

12

12

1 2

CW5 5.6P_0402_50V8-D

EMC@

1 2

CW6 5.6P_0402_50V8-D

EMC@

1 2

CW7 5.6P_0402_50V8-D

EMC@

1 2

CW8 5.6P_0402_50V8-D

EMC@

1 2

CW11 5.6P_0402_50V8-D

EMC@

1 2

CW12 5.6P_0402_50V8-D

EMC@

SD_D0

SD_D1

SD_D2

SD_D3

SD_CMDSD_CMD_R

SD_CLKSD_CLK_R

1

CW9

@

2

4.7U_0402_6.3V6M

Close to Connector

Close to Connector

A A

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

2016/08/16

2016/08/16

2016/08/16

3

Deciphered Date

2017/08/15

2017/08/15

2017/08/15

2

Titl e

Cardreader

Cardreader

Cardreader

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

37 52

37 52

37 52

1

1.0

1.0

1.0

A

Vinafix.com

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD1

10

SATA_PTX_DRX_P04

1 1

SATA_PTX_DRX_N04

SATA_PRX_DTX_N04

SATA_PRX_DTX_P04

+5VS_HDD

1

C74
1000P_0201_50V7-K

EMC_NS@

2

SATA_PTX_DRX_P0 SATA_PTX_C_DRX_P0
SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0 SATA_PRX_C_DTX_N0
SATA_PRX_DTX_P0 SATA_PRX_C_DTX_P0

1

C75

0.1U_0201_6.3V6-K

2

1 2

C66 0.01U_0201_10V6K

1 2

C67 0.01U_0201_10V6K

1 2

C68 0.01U_0201_10V6K

1 2

C69 0.01U_0201_10V6K

Need short

+5VS

2A_32V_ERBRD2R00X

1

C76
33P_0402_50V8J

RF@

2

1

C77
10U_0603_6.3V6M

2

J3

@

112

JUMP_43X79

F6

NEC@

2

21

+5VS_HDD

1

C78
33P_0402_50V8J

RF@

2

10

9

9

8

8

7

7

GND2

6

6

5

5

4

4

3

3

GND1

2

2

1

1

ELCO_006809610010846

ME@

12

11

FOR 15"

SATA ODD FFC Conn

2 2

EMC

SATA 15 ODD P/N pin assgin is different from G SKL

JODD2

1

+5VS to +5V_ODD

+5VS +5V_ODD

3 3

4 4

Need short

J4

@

2

112

JUMP_43X79

F7

NEC@

2A_32V_ERBRD2R00X

21

10U_0603_6.3V6M

1

C85

1

C86

2

0.1U_0201_6.3V6-K

2

1

C1324
33P_0402_50V8J

RF@

2

1

2

C8792
22P_0402_50V8-J

RF_NS@

SATA_PTX_DRX_N14
SATA_PTX_DRX_P14

SATA_PRX_DTX_P14

SATA_PRX_DTX_N14

SATA_PTX_DRX_N1 SATA_PTX_C_DRX_N1_15

1 2

C198 0.01U_0201_10V6K

1 2

C197 0.01U_0201_10V6K

1 2

C200 0.01U_0201_10V6K

1 2

C199 0.01U_0201_10V6K

SATA_PTX_C_DRX_P1_15SATA_PTX_DRX_P1

SATA_PRX_C_DTX_P1_15SATA_PRX_DTX_P1
SATA_PRX_C_DTX_N1_15SATA_PRX_DTX_N1

+5V_ODD

ME@

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND1

10

GND2

HIGHS_FC5AF081-2931H

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

B

C

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

D

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

E

F

2013/08/05

2013/08/05

2013/08/05

Titl e

Titl e

Titl e

HDD/ODD CONN

HDD/ODD CONN

HDD/ODD CONN

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

G

330ARR

330ARR

330ARR

38 52

38 52

38 52

H

1.0

1.0

1.0

5

Vinafix.com

D D

WRST#18

+3VL_EC

1 2

DE1

@

RB751V-40_SOD323-2

1 2

RE8 100K_0402_5%

+3VS

C C

14

23

RPE3

2.2K_0404_4P2R_5%

@

EC_SMB_CK3
EC_SMB_DA3

+3VL_EC

23

14

RPE2

2.2K_0404_4P2R_5%

EC_SMB_CK1
EC_SMB_DA1

1

CE12
1U_0402_6.3V6K

2

EC_SCI# in APU internal pull high to 3VALW

KSI[0..7]40

KSO[0..17]40

LPC_FRAME#8,13,34

CLK_PCI_EC8,13

APU_LPC_RST#8,13,34

KSI[0..7]

KSO[0..17]

KBRST#8
SERIRQ8,13,34

LPC_AD38,13,34
LPC_AD28,13,34
LPC_AD18,13,34
LPC_AD08,13,34

EC_SMI#7

EC_RX28,35

EC_TX28,35

EC_SCI#8

IT13

AMD request SIC/SID（ EC_SMB3 ） pul l hig h 1 K

+3VL_EC +3VALW

B B

RE74
0_0402_5%

@

1 2

14

23

RPE5

2.2K_0404_4P2R_5%

EC_SMB_CK2
EC_SMB_DA2

12

RE73

0_0402_5%

@

Mirror Core strap

GPG2

when mirror, GPG2 pull high
when no mirror, GPG2 pull low

A A

Reserve Factory EC flash, need confirm with ITE

EC_SMB_CK1
EC_SMB_DA1

KSI7
KSI6
WRST#

12

RE98 10K_0402_5%@

12

RE97 10K_0402_5%

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

5

SMBus 1:Char ger/Ba ttery
SMBus 2:PMIC /therm alsens or
SMBus 3:APU/ GPU

SYSON

+3VL_EC

IT1
IT2
IT3
IT4
IT5

IT6
IT7
IT8

EC_ON

1 2

RE104 0_0402_5%@

EC_SMB_CK146,47
EC_SMB_DA146,47
EC_SMB_CK234,49
EC_SMB_DA234,49
EC_SMB_CK36,18

+3VL

@

1 2

DE4 RB751V-40_SOD323-2

1 2

RE99 0_0402_5%@

@

1 2

DE5 RB751V-40_SOD323-2

1 2

RE100 1K_0402_5%@

1 2

RE27 0_0402_5%@

EC_SMB_DA36,18

LAN_WAKE#32,35

PCH_CMOSP41

EC_RSMRST#7

PCIE_WAKE#7,32,35
AC_PRESENT7

for VR_APU_PWRGD undershoot issue

ON/OFF40

USB_ON#28

4

Change RE6 to 0ohm jump

CLK_PCI_EC

WRST#

EC_RX
EC_TX
APU_LPC_RST#
EC_SCI#

1

GATEA20

PAD@

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

ON/OFF

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK3
EC_SMB_DA3

LAN_WAKE#

USB_ON#

EC_RSMRST#

1_2VEN 49

2_5VEN

1

CE25

0.1U_0402_25V6

@

2

2_5VEN 49

4

Close EC

1 2

CE3

0.1U_0201_6.3V6-K

RE6 0_0402_5%@

126

110
111
115
116
117
118

112
125

128

VR_APU_PWRGDAPUALW_PWRGD

10
13
14
15
16
17
22
23

58
59
60
61
62
63
64
65
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
56
57

94
95

33
35
93

VCOREVCC

12

12

3

UE1

VBAT

4

KBRST#/GPB6

5

SERIRQ/GPM6

6

LFRAME#/GPM5

7

LAD3/GPM3

8

LAD2/GPM2

9

LAD1/GPM1
LAD0/GPM0
LPCCLK/GPM4
WRST#
ECSMI#/GPD4
PWUREQ#/BBO/SMCLK2ALT/GPC7
LPCPD#/GPE6
LPCRST#/GPD2
ECSCI#/GPD3
GA20/GPB5

KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7
KSO0/PD0

Int. K/B

KSO1/PD1

Matrix

KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15
KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5

PWRSW#
XLP_OUT
SMCLK1/GPC1
SMDAT1/GPC2
SMCLK2/PECI/GPF6
SMDAT2/PECIRQT#/GPF7
CRX1/SIN1/SMCLK3/GPH1/ID1
CTX1/SOUT1/GPH2/SMDAT3/ID2

VSTBY0
GPE4

GINT/CTS0#/GPD5
RTS1#/GPE5
CLKRUN#/GPH0/ID0

2

CK32KE/GPJ7
CK32K/GPJ6

IT8586E-AX_LQFP128_14X14

1

CE24

0.01U_0201_10V6K

2

Clock

RE1 0_0603_5%

RE3 0_0603_5%@

+3VS

11

VCORE

+3VL_EC_R

127

50

92

114

121

VCC

VSTBY2

VSTBY3

VSTBY4

VSTBY126VSTBY5

VSTBY(PLL)

LPC

IT8586E/AX
LQFP-128L

EXTERNAL SERIAL FLASH

SPI Flash ROM

SM Bus

WAKE UP

GPIO

VSS1

VSS2

VSS4

VSS349VSS6

1

27

91

113

2N7002KW_SOT323-3 @

@

1 2

1 2

+3VL_EC

All capacitors close to EC

1

CD@

2

0.1u_0201_10V6K

CE6

minimum trace width 12 mil

74

AVCC

PWM0/GPA0
PWM1/GPA1
PWM2/GPA2

PWM6/SSCK/GPA6

PWM7/RIG1#/GPA7

ADC

ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6

ADC7/CTS1#/GPI7

DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3

DAC

DAC4/DCD0#/GPJ4

DAC5/RIG0#/GPJ5

PS2CLK0/TMB0/CEC/GPF0

PS2DAT0/TMB1/GPF1

PS2

UART

GPIO

DTR1#/SBUSY/GPG1/ID7

CTX0/TMA0/GPB2

TACH1A/TMA1/GPD7

L80HLAT/BAO/GPE0

AVSS

75

EC_AGND

+3VL

12

ACIN#

13

D

S

PWM3/GPA3
PWM4/GPA4
PWM5/GPA5

TMRI0/GPC4
TMRI1/GPC6

ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3
ADC4/GPI4

PS2CLK2/GPF4
PS2DAT2/GPF5

GPH3/ID3
GPH4/ID4
GPH5/ID5
GPH6/ID6

LID_SW#

EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3

SSCE0#/GPG2
SSCE1#/GPG0

DSR0#/GPG6

CRX0/GPC0

RI1#/GPD0
RI2#/GPD1

TACH2/GPJ0

TACH0A/GPD6

L80LLAT/GPE7

RE102
100K_0402_5%

RE101 0_0402_5%@

QE7

G

PWM

VSS5

122

+3VL

+3VALW

CE7

GPF2
GPF3

NC1
NC2
NC3
NC4

AC_IN#

GPJ1

1 2

2

3

+3VL_EC +3VL_EC

1

2

CE10

0.1U_0201_6.3V6-K

1

1

1

RE34 0_0402_5%@

RE82 0_0402_5%@

@

1

2

CE11

0.1u_0201_10V6K

PWR_LED# 40
BATT_CHG_LED# 40
BATT_LOW_LED# 40

VGA_AC_DET 18
LED_KB_PWM 40
EC_FAN_PWM 34
BEEP# 36

EC_APU_ALWEN 49

IT14

SUSP# 41,48,49

NTC_V1 34

NTC_V2 34

BATT_TEMP 46,47

ENBKL 26

ADP_I 47

VR_APU_PWRGD 52

EC_RTCRST#_ON 11

EC_ON 48,49

PBTN_OUT# 7

EC_LID_OUT# 40

CAPS_LED# 40

EC_VR_ON 52

LAN_PWR_ON# 32
EC_SYS_PWRGD 7

LID_SW# 40

EC_MUTE# 36

APUALW_PWRGD 49
CMOS_ON# 26

PM_SLP_S5# 7,13

OTP_RESET 48

BKOFF# 26

PM_SLP_S3# 7

IT16

NOVO# 40

EC_TS_ON 26

EC_FAN_SPEED 34

IT18

NUM_LED# 4 0

1 2

1 2

2

2N7002KW_SOT323-3

RE286 0_0402_5%@

RE85 0_0402_5%@

RE280 0_0402_5%@

QE1

G

@

1 2

RE278 0_0402_5%@

RE276 0_0402_5%@
RE71 0_0402_5%@

1 2

RE26 1K_0402_5%@

RE283 0_0402_5%@
RE284 0_0402_5%@
RE90 0_0402_5%@

2N7002KW_SOT323-3

13

D

S

1

2

0.1U_0201_6.3V6-K

24
25
28
29
30
31
32
34
120
124

66
67
68
69
70
71
72
73

78
79
80
81

85
86
87
88
89
90

96
97
98
99

101
102
103
105

108
109

82
83
84

77
100
106
104
107
119
123
18
21
76
48
47
19
20

2

CE8

0.1U_0201_6.3V6-K

EC_FAN_PWM

EC_APU_ALWEN
HVB_EN

SUSP#

ENBKL

MAINPWON1_EC
H_PROCHOT#_EC

EC_ON

EC_SMB_CK4
EC_SMB_DA4
GPU_EC_HOT#
EC_LID_OUT#

EC_VR_ON

ACIN#
LID_SW#

APUALW_PWRGD

GPG2

BKOFF#

VDDGFX_PD

EC_FAN_SPEED
PCH_PWRBT#

H_PROCHOT#

VR_HOT#47,52

H_PROCHOT#_EC

1

2

0.1u_0201_10V6K

CE9

ACIN 47

PAD @

PAD @

PAD @

@

1

2

@

1 2

LE1 0_0603_5%

CE4

0.1U_0201_6.3V6-K

@

1 2

LE2 0_0603_5%

12
12

12
12
12

13

D

QE8

2

G

S

@

12

12

SYSON

12

H_PROCHOT# 6,49

1

CE14
47P_0201_25V8-J

@

2

CLK_PCI_EC

1

2

EC_AGND

EC_AGND

IDCHG 47

PSYS 47

2_5VEN

MAINPWON 48

THERMAL_SMB_CK2 34
THERMAL_SMB_DA2 34

1

2

0.9V_PWRGD 49

APU_THERMTRIP# 6

RE103 10_0402_5%

+3VL_EC_R

1

CE5
1000P_0201_50V7-K

2

CE33
47P_0201_25V8-J

@

1 2

EMC_NS@

GPU_VR_HOT# 18, 51

APU_LPC_RST#

SYSON

BATT_TEMP

ACIN#

ON/OFF

EC_FAN_SPEED
EC_FAN_PWM

ENBKL
SERIRQ

EC_LID_OUT#

USB_ON#

SUSP#
LAN_WAKE#

EC_ON

LID_SW#

EC_VR_ON
2_5VEN
EC_APU_ALWEN

SUSP#
SYSON
BKOFF#

EC_ON

CE29 10P_0201_25V8GEMC_NS@

CE27 220P_0201_25V7-KEMC_NS@

CE31 0.1U_0201_6.3V6-KEMC_NS@

CE28 100P_0201_25V8JEMC_NS@

CE26 100P_0201_25V8JEMC_NS@

CE30 0.1U_0402_10V7KEMC@

1 2

1 2

1 2

1 2

1 2

1 2

1

1 2

RE10 10K_0402_5%

1 2

RE11 10K_0402_5%@

1 2

RE9 100K_0402_5%@

1 2

RE81 10K_0402_5%@

1 2

RE93 10K_0402_5%@

1 2

RE15 10K_0402_5%

1 2

RE18 100K_0402_5%@

1 2

RE5 10K_0402_5%

1 2

RE72 10K_0402_5%@

1 2

RE38 100K_0402_5%

1 2

RE282 100K_0402_5%

1 2

RE279 100K_0402_5%

1 2

RE66 100K_0402_5%

1 2

RE19 100K_0402_5%

1 2

RE21 100K_0402_5%

1 2

RE40 10K_0402_5%

1 2

RE285 100K_0402_5%

+3VS

+3VS

+5VALW

+3VL_EC

+3VL

2

CE32

0.1U_0201_6.3V6-K

1

EMC_NS@

EMC

Title

Title

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2016/08/16

2016/08/16

2016/08/16

2

Deciphered Date

Deciphered Date

Deciphered Date

2017/08/15

2017/08/15

2017/08/15

Title

EC ITE8586LQFP

EC ITE8586LQFP

EC ITE8586LQFP

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330ARR

330ARR

330ARR

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

39 52

39 52

39 52

1.0

1.0

1.0

5

Vinafix.com

ON/OFF switch Novo button

100K_0402_5%

NOVO#

NOVO#39

ON/OFF

D D

1 2

J5

SHORT PADS

1 2

J6

SHORT PADS

+3VALW

+3VL

R83

R82

100K_0402_5%

@

1 2

1 2

12

R85 0_0402_5%@

12

R119 0_0402_5%@

@

@

R261 0_0402_5%@

2

D15

3

BAT54CW_SOT323-3

+3VALW

R111
100K_0402_5%

@

1 2

ON/OFFON/OFFBTN#

12

@

4

NOVO_BTN#

1

+3VL

R114
100K_0402_5%

1 2

ON/OFF 39

ON/OFFBTN#

1

D25

1

2

EMC@
2

AZ5123-01F.R7GR_DFN1006P2X2

3

SW2

NTC325-EKJ-A160T_3P

123

2

NOVO_BTN#

4

5

1

D24

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2

2

1

LID switch

1

C1105

0.01U_0201_10V6K

2

12

R264 0_0402_5%@

+3VL

+VCC_LID

OUTPUT

2

VCC

AH9247-W-7_SC59-3

U14

1

GND

1

C1104
100P_0201_25V8J

2

LID_SW#

3

LID_SW# 39

K/B Connector

PWR_CAPS_LED

CAPS_LED#

NUM_LED#_R

C C

EMC_NS@

1 2

C133 100P_0201_25V8J

EMC@
1 2

C117 100P_0201_25V8J

1 2

C118 100P_0201_25V8J

EMC@

CAPS_LED#_R NUM_LED#_R

1

D22

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2

2

1

1

2

2

D23
AZ5123-01F.R7GR_DFN1006P2X2

EMC@

Finger Print Connector

+3VS

R3120 0_0402_5%@

0.5A_32V_ERBRD0R50X

USB20_N3_CONN

B B

A A

USB20_P3_CONN

312

AZC199-02S.R7G_SOT23-3

BATT_LOW_LED#39

BATT_CHG_LED#39

BATT_LOW_LED#

1

1

2

2

BATT_CHG_LED#

1

1

2

2

PWR_LED#39

PWR_LED#

PWR_LED Change to M/B (310->320) 08/17

5

KSI[0..7]

KSO[0..17]

For EMC

FP_PWR

12

F9

@

21

1

2

DT2

FP_EMC@

1 2

LED2

L-C192JFCT-LCFC_SUPER_AMBER

D18
AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

1 2

LED3

L-C192WDT-LCFC_WHITE

D19
AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

1 2

LED4

L-C192WDT-LCFC_WHITE

KSI[0..7] 39

KSO[0..17] 39

PWR_LED#_R

1

D46

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2

2

USB20_N3

USB20_N331
USB20_P331

C2061

0.1U_0201_6.3V6-K

FP@

R3122 0_0402_5%@

USB20_P3 USB20_P3_CONN

R3121 0_0402_5%@

1 2

R143 470_0402_5%

1 2

R144 1.5K_0402_5%

1 2

R4672 1.5K_0402_5%

R274 200_0402_1%

PWR_LED# PWR_LED#_R

NUM_LED#39

CAPS_LED#39

+3VALW

1 2

1 2

R279 200_0402_1%

1 2

KSO17

R281 0_0402_5%@

1 2

KSO16

R280 0_0402_5%@

R275 200_0402_1%

1 2
1 2

NONEC@

R84

F8

NEC@

0.5A_32V_ERBRD0R50X

To be confirm Pin define

USB20_N3_CONN

12
12

+3VALW

+5VALW

+5VALW

4

1
2
3
4
5
6
7
8

9

10

HIGHS_FC5AF081-2931H

1

1

2

2

0_0402_5%

21

JFP1

1
2
3
4
5
6
7
8

GND1
GND2

ME@

PWR_LED#

D16
AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

ON/OFFBTN#

NUM_LED#_R
KSO17_R
KSO16_R

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

CAPS_LED#_R
PWR_CAPS_LED

JKB1

32

32

31

31

30

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

CVILU_CF32321D0RONH

ME@

3

KB Ba cklight Connector

33

GND1

34

GND2

R265

10K_0402_5%

KBL@

LED_KB_PWM39

0.1U_0201_6.3V6-K

C1109

KBL@

LED_KB_PWM

1

2

R4685
10K_0402_5%

@

1 2

2

G

TP/B Co nnector

TP_PWR+3VS

NONEC@

1 2

R141

0_0402_5%

F10

NEC@

21

0.5A_32V_ERBRD0R50X

TP_I2C0_SCL
TP_I2C0_SDA

312

DT1

EMC_NS@

For EMC

TP_I2C0_SDA_R7,13

TP_I2C0_SCL_R7,13

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

AZC199-02S.R7G_SOT23-3

TP_I2C0_SDA_R TP_I2C0_SDA

R4686 0_0402_5%@

TP_I2C0_SCL_R

R4687 0_0402_5%@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

2016/08/16

2016/08/16

2016/08/16

Deciphered Date

2

+5VS

+5VALW

12

R266

1 2

100K_0402_5%

KBL@

13

D

Q32
2N7002KW_SOT323-3

KBL@

S

1

C114

0.1U_0201_6.3V6-K

2

TP_I2C0_SDA_R TP_I2C0_SDA

1 2

1 2

Q31
LP2301ALT1G_SOT23-3

KBL@

D

S

13

G

2

1

C1108

0.01U_0201_10V6K

KBL@

2

1 2

R4681 0_0402_5%@

1 2

R4680 0_0402_5%@

2017/08/15

2017/08/15

2017/08/15

R4684 0_0402_5%@
R4683 0_0402_5%@

1

2

C115

2

6 1

D

Q159A
2N7002KDWH_SOT363-6

EC_LID_OUT#39

PCH_TP_INT#7

@

21

F11 0.5A_32V_ERBRD0R50X

1 2

R267 0_0402_5%@

10U_0603_6.3V6M

+VCC_KB_LED

C1110

0.1u_0201_10V6K

@

1 2
1 2

TP_PWR

1

2

EMC_NS@

EMC_NS@

C116

100P_0201_25V8J

100P_0201_25V8J

TP_PWR

5

G

3 4

S

D

Q159B
2N7002KDWH_SOT363-6

G

S

Title

Title

Title

KBD/PWR/IO/LED/TP Conn.

KBD/PWR/IO/LED/TP Conn.

KBD/PWR/IO/LED/TP Conn.

Size

Size

Size

Document N umber Rev

Document N umber Rev

Document N umber Rev

Custom

Custom

Custom

Date: Shee t o f

Date: Shee t o f

Date: Shee t o f

C1106

KBL@

1

2

EC_LID_OUT#_R
TP_INT#

TP_I2C0_SCLTP_I2C0_SCL_R

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

2

CVILU_CF50041D0RN-10-NH

TP_PWR

14

23

RPC20

2.2K_0404_4P2R_5%

TP_I2C0_SCL

+VCC_KB_LED

1

C8786

0.1U_0201_6.3V6-K

KBL@

2

To be confirm Pin define

JKBL1

ME@

1

1

2

2

3

6

3

GND2

5

4

GND1

4

JTP1

1

1

2

2

3

3

4

4

5

5

6

6

ELCO_04-6809-606-110-846-+

330ARR

330ARR

330ARR

1

ME@

GND1

GND2

40 52

40 52

40 52

7

8

1.0

1.0

1.0

A

Vinafix.com

+5VALW+5VLP

R156
100K_0402_5%

Q6

2

G

12

R157
100K_0402_5%

@

13

D

S

2N7002KW_SOT323- 3

12

1 1

SUSP14,27

SUSP#39,48,49

SUSP

B

C

D

E

+1.8VALW to +1.8VS

C143

Q39

4

1.8VS_GATE_R

1

2

1
2
3

C1326 0.01U_0201_10V6K

1

2

+1.8VALW

1

C1325

0.1U_0201_6.3V6-K

@

2

0.01U_0201_25V6-K

AON6414AL_DFN8-5

5

+/- 2%

2 2

C141

10U_0603_6.3V6M

@

+/- 5% 1.5A

+1.8VS

1

@

2

R211

1M_0402_5%

1

C2082
10U_0603_6.3V6M

2

12

0_0402_5%@

12

R212

R194

@

0_0402_5%

1

C142
1U_0402_6.3V6K

2

1.8VS_GATE

12

D

S

13

Q45

2N7002KW_SOT323- 3

AON6 414A L
VDS=30V VGS=20V, ID=50A,
Rds=8mohm @ VGS=10V
VGS(th)=2.5V Max

V20B+

R214

12

130K_0402_5%

2

SUSP

G

+0.9V to +0.9VS

+/- 1.5%

12

R213
470_0603_5%

@

13

D

2

G

Q46
2N7002KW_SOT323- 3

@

S

C146

10U_0603_6.3V6M

@

+0.9V

1

2

0.01U_0201_25V6-K

AON6414AL_DFN8-5

5

1

C1327

0.1U_0201_6.3V6-K

@

2

J602

112

JUMP_43X118

C144

@

@

2

Q41

1
2
3

@

4

1.05VS_GATE_R

1

2

+/-5% 3.6A

+0.9VS

1

C145
10U_0603_6.3V6M

2

1

C1328 0.01U_0201_10V6K

@

2

R193

12

0_0402_5%

@

R187

820K_0402_5%

@

AON6 414A L
VDS=30V VGS=20V, ID=50A,
Rds=8mohm @ VGS=10V
VGS(th)=2.5V Max

1

C147
1U_0402_6.3V6K

2

R206

1.8VS_GATE

12

0_0402_5%

@

1.05VS_GATE

1 2

R190
0_0402_5%

@

12

R189

470K_0402_5%

@

13

D

Q37

2

G

S

2N7002KW_SOT323- 3

@

V20B+

12

SUSP

+0.9V

12

R188
470_0603_5%

13

D

2

G

Q40
2N7002KW_SOT323- 3

@

S

J603

112

JUMP_43X118

@

+0.9VALW

@

2

20VSB will change to 6V in DC mode, careful the Res divide voltage

+3VALW to +3VALW_APU

3 3

1 2

PCH_CMOSP39

4 4

R158 0_0402_5%@

12

R164
100K_0402_5%

@

+3VALW +3VALW_APU

1

2

LP2301ALT1G_SOT23-3

@

Q29

C129

0.1U_0201_6.3V6-K

@

Need Short

J7

@

2

112

JUMP_43X79

Id=3.2 A

D

S

13

G

2

1

C131

0.1U_0201_6.3V6-K

@

2

C130

1

@

2

2N7002KW_SOT323- 3 @

0.01U_0201_10V6K

+0.6VS

12

R159
47_0603_5%

@

13

D

Q8

2

SUSP

G

S

+0.9V +0.9V +0.9V +0.9V

1

C2083

2200P_0402_25V7-K

EMC_NS@

2

2N7002KW_SOT323- 3 @

1

C2084

2200P_0402_25V7-K

EMC_NS@

2

reserve to cut off APU 3VALW when clear CMOS

A

B

For DisCharge

+2.5V +3VS

C2086

2200P_0402_25V7-K

EMC_NS@

2013/08/15

2013/08/15

2013/08/15

12

13

D

S

R940
47_0603_5%

@

Q158

2

G

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

R935
47_0603_5%

@

13

D

Q156

2

SUSP SUSP

G

S

1

C2085

2200P_0402_25V7-K

EMC_NS@

2

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISION OF R&D
DEPARTMENT EX CEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOS ED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF L C FUTURE CENTER.

MAY BE USED BY OR DISCLOS ED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF L C FUTURE CENTER.

MAY BE USED BY OR DISCLOS ED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF L C FUTURE CENTER.

C

Issued Date

Issued Date

Issued Date

2N7002KW_SOT323- 3 @

1

2

CS31

1 2

0.1U_0201_6.3V6-K

+3VS +3VS+5VS +5VS

D

+3VALW+5VALW +3VALW+ 3VS

1

CS28

0.1U_0402_10V7K

2

1

CS43

0.1U_0402_10V7K

2

2013/08/15

2013/08/15

2013/08/15

1

CS24

0.1U_0402_10V7K

2

1

CS42
10U_0603_6.3V6M

2

CS34

1 2

0.1U_0201_6.3V6-K

1

CS27

0.1U_0402_10V7K

2

+1.2V

1

CS44

0.1U_0201_6.3V6-K

2

Title

Title

Title

DC V TO VS INTERFACE

DC V TO VS INTERFACE

DC V TO VS INTERFACE

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Date : Sheet of

Date : Sheet of

Date : Sheet of

Friday, March 23, 2018

1

CS25

0.1U_0402_10V7K

2

+5VS+3VS+3VALW

1

CS26

0.1U_0402_10V7K

2

330ARR

330ARR

330ARR

E

41 52

41 52

41 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

CPU Thermal Holex3 GPU Thermal Holex2

H11

D D

HOLEA

1

pad_c6p0d4p0

H12
HOLEA

1

pad_c6p0d4p0

H13
HOLEA

1

pad_c6p0d4p0

H8
HOLEA

1

pad_c8p0d3p3

H9
HOLEA

1

pad_c8p0d3p3

H4
HOLEA

1

CHASSIS1_GND

pad_ct7p0b8p0d3p0

Close to Audio jackClose to RJ45

H3
HOLEA

1

pad_ct7p0b8p0d3p0

PCB Fedical Mark PAD

FD1

FD2

1

1

FD3

FD4

1

1

FD5

FD6

1

1

WLAN Standoff

H15
H5
HOLEA

C C

pad_o2p6x2p9d2p6x2p9n

B B

1

H17
HOLEA

1

pad_d2p5

SH1

ME@

1

1

SPRING_FINGER_6.2X1.64

SH4

ME@

1

1

SPRING_FINGER_6.2X1.64

H6
HOLEA

1

PAD_CB5P5D2P5

H18
HOLEA

1

PAD_C2P5D2P5N

SH2

1

1

SH5

1

1

H7
HOLEA

1

pad_c2p5d2p5n

ME@

SPRING_FINGER_6.2X1.64

ME@

SPRING_FINGER_6.2X1.64

H10
HOLEA

1

pad_c8p0d3p3

SH3

ME@

1

1

SPRING_FINGER_6.2X1.64

SH6

ME@

1

1

SPRING_FINGER_6.2X1.64

H14
HOLEA

1

pad_c3p3d3p3n

SH12

1

1

SH13

1

1

HOLEA

1

PAD_CT7P0D3P0

ME@

SPRING_FINGER_6.2X1.64

ME@

SPRING_FINGER_6.2X1.64

USB3.0 Shielding

A A

H16
HOLEA

1

pad_d2p5

SH7

ME@

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH9

ME@

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH8

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH10

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

DDR4 Shielding

ME@

ME@

SH11

ME@

1

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC F UTURE CENTER.

2013/08/08

2013/08/08

2013/08/08

Titl e

Titl e

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2013/08/05

2013/08/05

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/05

2

Titl e

Hole

Hole

Hole

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

B

B

B

Friday, March 23, 2018

Friday, March 23, 2018

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

42 52

42 52

42 52

1.0

1.0

1.0

5

Vinafix.com

UL1

8111H@

UC2

4

UC2

UC2

3

UV1

R17@

2

UV1

R18@

ZZZ3

HDMI@

1

RTL8111H-CG

SA000074W00

D D

ZZZ9

Samsung

X7645A12004

UD1

K4A8G165WC-BCTD

SA00008PE00

C C

UD1

H5AN8G6NAFR-UHC

SA00007X200

UD1

MT40A512M16LY-075:E

SA00008F930

LAN Chip

DRAM_S4G@

MD_S8Gb@

MD_H8Gb@

MD_M8Gb@

UD2

K4A8G165WC-BCTD

SA00008PE00

UD2

H5AN8G6NAFR-UHC

SA00007X200

UD2

MT40A512M16LY-075:E

SA00008F930

RAVEN RIDGE YM2700C4T4MFBA

R7@
SA00008QB10

ZZZ2

DRAM_M4G@

Micron

X7645A12006

MD_S8Gb@

MD_H8Gb@

MD_M8Gb@

ZZZ7

Hynix

X7645A12005

UD3

MD_S8Gb@

K4A8G165WC-BCTD

SA00008PE00

UD3

MD_H8Gb@

H5AN8G6NAFR-UHC

SA00007X200

UD3

MD_M8Gb@

MT40A512M16LY-075:E

SA00008F930

DRAM_H4G@

UD4

K4A8G165WC-BCTD

SA00008PE00

UD4

H5AN8G6NAFR-UHC

SA00007X200

UD4

MT40A512M16LY-075:E

SA00008F930

RAVEN RIDGE YM2500C4T4MFBA

R5@
SA00008QA10

MD_S8Gb@

MD_H8Gb@

MD_M8Gb@

DRAM X76 BOM

RAVEN RIDGE YM2200C4T2OFB

R3@
SA00008UR10

RC1608

MD_S8Gb@

10K_0402_5%

SD02810028J

RC1610

MD_H8Gb@

10K_0402_5%

SD02810028J

RC1610

MD_M8Gb@

10K_0402_5%

SD02810028J

RC1609

DIMM_ONLY@

RC1609

2K_0402_5%

SD02820018J

RC1607

10K_0402_5%

SD02810028J

RC1608

10K_0402_5%

SD02810028J

RC1607

MD_S8Gb@

MD_H8Gb@

MD_M8Gb@

DIMM_ONLY@

APU type

DRAM_Samsung 4G

DRAM_Hynix 4G

DRAM_Micron 4G

216-0905018-C3_FCBGA769

SA00008DT20

ZZZ5

S8GX2@

Samsung

X7645A12002

UV3

S8G_VR@

K4G80325FB-HC28

SA000081C00

UV3

H8G_VR@

H5GC8H24MJR-R0C

SA000081600

UV3

M8G_VR@

MT51J256M32HF-70:A

SA000081700

UV3

S8G_VRR18@

ZZZ8

H8GX2@

Hynix

X7645A12001

UV4

S8G_VR@

K4G80325FB-HC28

SA000081C00

UV4

H8G_VR@

H5GC8H24MJR-R0C

SA000081600

UV4

M8G_VR@

MT51J256M32HF-70:A

SA000081700

UV4

S8G_VRR18@

216-0915006_FCBGA769

SA00008XC00

ZZZ12

M8GX2@

Micron

X7645A12003

RV1307

5.1K_0402_5%

SD02851018J

RV1307

5.1K_0402_5%

SD02851018J

RV1307

5.1K_0402_5%

SD02851018J

GPU

S8G_VR@

H8G_VR@

M8G_VR@

ZZZ4

Samsung

X7645A12009

HDMI PN

RO00000040J

S8GX2R18@

RV1304

S8G_VR@

5.1K_0402_5%

SD02851018J

RV1304

H8G_VR@

5.1K_0402_5%

SD02851018J

RV1303

M8G_VR@

5.1K_0402_5%

SD02851018J

HDMI Royalty

ZZZ6

Hynix

X7645A12007

H8GX2R18@

RV1298

S8G_VR@

5.1K_0402_5%

SD02851018J

RV1297

H8G_VR@

5.1K_0402_5%

SD02851018J

RV1298

M8G_VR@

5.1K_0402_5%

SD02851018J

RV1418

ZZZ10

M8GX2R18@

Micron

X7645A12008

VRAM X76 BOM

VRAM_Samsung 8GX2

VRAM_Hynix 8GX2

VRAM_Micron 8GX2

S8G_VRR18@

B B

A A

2K_0402_5%

SD02820018J

5

4

10K_0402_5%

SD02810028J

ZZZ13

PCB PN

DAZ18700100

DIMM ONLY

PCB_MB

3

K4G80325FB-HC28

SA000081C00

UV3

H8G_VRR18@

H5GC8H24MJR-R0C

SA000081600

UV3

M8G_VRR18@

MT51J256M32HF-70:A

SA000081700

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

K4G80325FB-HC28

SA000081C00

UV4

H8G_VRR18@

H5GC8H24MJR-R0C

SA000081600

UV4

M8G_VRR18@

MT51J256M32HF-70:A

SA000081700

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/05

2013/08/05

2013/08/05

RV1415

8.45K_0402_1%

SD000011R00

H8G_VRR18@

RV1415

M8G_VRR18@

4.53K_0402_1%

SD03445318J

4.75K_0402_1%

SD03447518J

VRAM_Samsung 8GX2 R18

RV1418

H8G_VRR18@

2K_0402_1%

SD03420018J

VRAM_Hynix 8GX2 R18

RV1418

M8G_VRR18@

2K_0402_1%

SD03420018J

VRAM_Micron 8GX2 R18

Title

Title

Title

Virtual symbol

Virtual symbol

Virtual symbol

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date : She et o f

Date : She et o f

Date : She et o f

330ARR

330ARR

330ARR

1

43 52

43 52

43 52

1.0

1.0

1.0

5

Vinafix.com

D D

C C

B B

4

3

2

1

A A

Title

Title

Title

Power sequence Block

Power sequence Block

Power sequence Block

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

330G-ARR

330G-ARR

330G-ARR

44 52

44 52

44 52

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

1.0

1.0

1.0

5

Vinafix.com

B+

Adaptor

D D

EC_ON

4

EN

EN

Richtek

LV5083AGQUF

PMIC

FOR 3/5VALW

PGOOD

PGOODEC_ON

+5VLP/ 100mA

+5VA LW/8A

ALW_PW RGD

+3VLP/ 100mA

+3VA LW/6A

+3VALW _PG

3

2

1

POK_VD DQ

PGOODEC_APU _ALWEN

+1.2 V/6 A

+0.6 VS/1A

+0.9 V/6 A

APUALW _PWRGDPGOOD

+1.8 VALW /3A

APUALW _PWRGDEN

+0.9 VALW /1A

LCFC

LV5075B

1.2VEN

TI

BQ24780SRUYR

Battery Charger

Switch Mode

C C

SMBus

SUSP#

+5VALW

EC_APU _ALWEN EN

+3VALW

+1.8 VAL W

APUALW _PWRGD EN

S5

S3

PMIC

FOR SYS

+3.3 VAL W

Battery

EN2.5VEN

+2.5 V/1 A

Li-ion

2S1P

Richtek

LV5095BGQUF

PMIC

B B

FOR 1.35VGS

ENPXS_PWREN PG OOD

Richtek

RT3662ACGQW

controller

PXS_PW REN

FOR VGA_CORE

EN

PGOOD

+1.35VGS /8A

+VDD C/28A

+VDD CI1/8A

VR_VGA _PWRGD

APL5930KAI
LDO

PXS_PW REN EN

A A

APU_SV ID

EC_VR_ ON

FOR VDD_08_1
(R18M)

Richtek

RT3662ACGQW

controller

VIDs

FOR CPU CORE&NB

EN

5

4

+VDD _08_ 1/2 A

VDDC _VDD /35 A

VDDC R_SOC/1 0A

PGOOD

VR_APU _PWRGD

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret D ata

LC Future Center Secret D ata

LC Future Center Secret D ata

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Title

Power Diagram

Power Diagram

Power Diagram

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

330G-ARR

330G-ARR

330G-ARR

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

45 53

45 53

45 53

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

12

0.01U_0402_25V7K

A/D

BATT+VMB

PC107

EMC@

PL101

EMC@

HCB2012KF-121T50_0805

1 2

D D

JDCIN1

1

APDIN APDIN1

1

2

GND1

3

GND2

4

GND3

5

GND4

6

GND5

7

GND6

HIGHS_PJSS0026-8B01H

ME@

C C

PF101

7A_24VDC_429007.WRML

21

12

12

EMC@

PC102

PC101

1000P_0402_50V7K

HCB2012KF-121T50_0805

1 2

JUMP_43X79

EMC@

100P_0402_50V8J

PL102

PJ101

112

EMC_NS@

@

2

VIN

16

GND4

15

GND3

14

GND2

13

GND1

12

12

11

11

10

10

9

9

8

8

7

7

6

6

JBATT1

ME@

5

5

4

4

3

3

2

2

1

1

12

12

EMC@

EMC@

100P_0402_50V8J

PC104

PC103

1000P_0402_50V7K

SUYIN_125022HB012M200ZL

EC_SMCA
EC_SMDA

AZC199-02S.R7G_SOT23-3

12

PR106

100_0402_1%

BATT_TEMP_IN

PD103

3

1

100K_0402_1%

PR107

1 2

1 2

PR108

10K_0402_1%

2

12

EMC_NS@

12

PR105

100_0402_1%

PL103

HCB2012KF-121T50_0805

1 2

PL104

HCB2012KF-121T50_0805

1 2

PC106
1000P_0402_50V7K

EMC@

EC_SMB_CK1 39,48

EC_SMB_DA1 39,48

+3VALW

BATT_TEMP 39,48

EMC@

EMC@

B B

VCCRTC

2

@

PC105

1

1U_0402_10V6K

A A

+3VL

PD101

2

1

3

LBAT54CWT1G_SOT323-3

PR104

1K_0603_1%

12

5

RTC_VCC

4

JRTC1

1

1

2

2

3

GND1

4

GND2

HIGHS_WS33020-S0351-HF

ME@

GC02001YB00-35mm cable , delete when layout

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PRTC1

BATT CR2032 3V 220MAH

RTC@

2013/08/15

2013/08/15

2013/08/15

2

Titl e

Titl e

Titl e

DCIN / RTC

DCIN / RTC

DCIN / RTC

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330G-ARR

330G-ARR

330G-ARR

1

46 53

46 53

46 53

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

PC340

0.01U_0402_50V6-K

EMC_NS@

1 2

10U_0805_25V6K

780s_SRP_R

780s_SRN_R

780s_BATDRV

PC212

10U_0805_25V6K

V20B+

12

5

4

12

PC208

PR203

499K_0402_1%

0.01U_0402_25V7K

PR213

0.01_1206_1%

1

4

3

2

1 2

PC228

0.1U_0402_25V6

12

PC223

0.1U_0402_25V6

PQ203
AON6324_DFN8-5

321

12

12

12

PC224

0.1U_0402_25V6

c ha r ge ：
current=5A
volatge=2S 595490
fsw=800K/REG0x12[9:8] = 01

12

PC217

PC221

PC230

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

BATT+

D D

VIN

C C

ACIN39

EC_SMB_DA139,47

EC_SMB_CK139,47

ADP_I39

IDCHG39

B B

PSYS39

VR_HOT#39,53

PQ201

AON6414AL_DFN8-5

5

12

PC201

470P_0402_50V7K

P2 P3

1
2
3

4
12

PR202

4.7_0603_5%

780s_ACDRV_R

12

1
2
3

PC202

0.022U_0402_25V7K

PQ202
AON7408L_DFN8-5

S1
S2
S3

G

4

2

5

D

12

PC203

10U_0603_25V6-M

VIN VIN

12

ACOK_10k pull high +3VL of open drain output at EC

SMBUS_10k pull high +3VL_EC of open drain output at EC

12

1 2

VR_HOT_10k pull high +3VS_APU of open drain output at APU

12

PC213

1 2

2

PD201

LBAT54CWT1G_SOT323-3

@

PR2150_0402_5%

@

PR2170_0402_5%

@

PR2180_0402_5%

780s_ILIM_R

12

PR206

PC225

100P_0402_50V8J

PR207

4.02K_0603_1%

4.02K_0603_1%

12

PR208

43K_0402_1%

PR210

PC215

1 2

1 2

1 2

1 2

1 2

7.15K_0402_1%

PR2190_0402_5%

PR2200_0402_5%

PR2210_0402_5%

0.01U_0402_25V7K

12

12

PC226

PC227

100P_0402_50V8J

100P_0402_50V8J

@

PR2320_0402_5%

+3VALW

@

@

@

PR231

20K_0402_1%

1 2

PR227

143K_0402_1%

1U_0603_25V6K

1 2

1 2

1 2

12

PJ201

JUMP_43X79

EMC_NS@

BATT+

3

1

12

PR209
10_1206_5%

PC229

0.1U_0402_25V6

@

112

780s_VCC

780s_ACDET

780s_CMSRC

780s_ACDRV

780s_ACOK

780s_SDA

780s_SCL

780s_IADP

780s_IDCHG

780s_PMON

780s_VR_HOT

1 2

12

12

780s_ILIM

PR226
0_0402_5%

@

PR230

12

100K_0402_1%

PR201

0.01_1206_1%

1

4

3

PC204

10U_0603_25V6-M

EMC_NS@

PC206

0.1U_0402_25V6

28

VCC

6

ACDET

3

CMSRC

4

ACDRV

5

ACOK

11

SDA

12

SCL

7

IADP

8

IDCHG

9

PMON

10

PROCHOT#

13

CMPIN

14

CMPOUT

21

ILIM

1 2

32.4K_0402_1%

2

0.1U_0402_25V6

PR228

ACP

2

1 2

PC205

ACP

ACN

1

ACN

PU201

BQ24780SRUYR_QFN28_4X4

TB_STAT#

16

15

780s_TB#

12

12

12

12

PC330

PC329

470P_0402_50V7K

220P_0402_50V7K

EMC_NS@

EMC_NS@

12

PC207

0.1U_0402_25V6

12

PC331

PC332

680P_0402_50V7K

4700P_0402_50V7-K

EMC_NS@

EMC_NS@

BQ24780S_VDD

2.2U_0603_10V6-K
PC214

2.2_0603_5%

1 2

PR211

780s_BATDRV

1 2

0.047U_0603_16V7K

PC216

10_0603_5%

1 2

1 2

10_0603_5%

1 2

10_0603_5%

PR222

PR224

PR225

24

REGN

780s_BS

25

BTST

780s_HG

26

HIDRV

780s_LX

27

PHASE

780s_LG

23

LODRV

22

GND

29

PAD

18

BATDRV

780s_BATSRC 780s_BATSRC_R

17

BATSRC

780s_SRP

20

SRP

780s_SRN

19

SRN

BATPRES#

Charge current limit 7A, discharge current 10A limit during turbo

12

12

PC333

PC334

6800P_0402_25V7-K

EMC_NS@

EMC_NS@

12

PC335

220P_0402_50V7K

0.01U_0402_50V6-K

EMC_NS@

12

12

PC336

470P_0402_50V7K

EMC_NS@

12

12

PC338

PC337

EMC_NS@

PC339

680P_0402_50V7K

4700P_0402_50V7-K

6800P_0402_25V7-K

EMC_NS@

EMC_NS@

V20B+

12

PC209

PC211

1 2

EMC_NS@

PQ205

AON6380_DFN8-5

12

PQ206

12

AON6380_DFN8-5

0.1U_0402_25V6

c ho ck ：
DCR=7mohm
Idc=12A
Isat=18A

PL201

1 2

2.2UH_PCMB063T-2R2MS_8A_20%

PR216

4.7_0805_5%

EMC_NS@

PC222
1000P_0402_50V9-J

EMC_NS@

5

12

4

321

5

4

321

BATT_TEMP 39,47

A A

Titl e

Titl e

Titl e

CHARGER

CHARGER

CHARGER

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330G-ARR

330G-ARR

330G-ARR

1

48 53

48 53

48 53

1.0

1.0

1.0

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/05

2013/08/05

2013/08/05

5

Vinafix.com

PJ3501

@

2

V20B+

EC_ON pull high reserve at EC

no need mirror code--enable=3.3V normal mode

D D

0_0402_5%

@

PR5996

EC_ON39,50

MAINPWON39

EC_ON_R34

+3VALW

1 2

1 2

@

PD3501

LRB751V-40T1G_SOD323-2

0_0402_5%

PR3507

1 2

1 2

PR3510

0_0402_5%

，

@

+3VALW_EN

+5VALW_EN

@

V20B+

@

@

PR3513

1 2

C C

PR3514

1 2

100K_0402_5%

100K_0402_5%

+3VALW_PG

ALW_PWRGD

JUMP_43X79

PJ3503

2

JUMP_43X79

112

+3VALW_EN

@

112

+5VALW_EN

+3VALW

SUSP#39,41,50

+5VALW

@

12

12

PC3565

SUSP#

PC3531

22U_0603_6.3V6-M

1U_0402_6.3V6K

4

12

PC3535

0.1U_0402_25V6

12

PC3537

0.1U_0402_25V6

12

PC3546

0.1U_0402_25V6

12

PC3549

0.1U_0402_25V6

0_0402_5%

PR3517

1 2

@

PC3569 1U_0402_6.3V6K

0_0402_5%

PR3518

1 2

@

PC3570 1U_0402_6.3V6K

12

EMC@

@

12

EMC@

@

@

12

@

12

@

12

PC3534

PC3547

PC3566

22U_0603_6.3V6-M

+3VALW_VIN

12

10U_0805_25V6K

+3VALW_PG

+5VALW_VIN

12

10U_0805_25V6K

ALW_PWRGD

12

+3VS_EN

+5VS_EN

PC3536

10U_0805_25V6K

PC3538

1 2

1U_0402_6.3V6K

PC3548

10U_0805_25V6K

PC3550

1 2

1U_0402_6.3V6K

PC3530

1U_0402_6.3V6K

3

+5VLP

PU3501

11

VIN1

10

EN1

9

PGOOD1

7

VCC1

14

VIN2

15

EN2

16

PGOOD2

18

VCC2

33

VINSW1

30

ENSW1

34

VINSW2

27

ENSW2

25

VDDSW

LV5083AGQUF_UQFN36_5X4

13

AGND_217PGND_112PGND_2

BOOT1

LX1_1
LX1_2
LX1_3

VOUT1

VBYP3

LDO3

BOOT2

LX2_1
LX2_2
LX2_3

VOUT2

VBYP5

LDO5

VOUTSW1

VOUTSW2

AGND_3

8

32

3

1
2
35

6

4

5

22

23
24
36

19

21

20

29

31

SS1

28

26

SS2

AGND_1

+3VALW_BS

+3VALW_LX

+3VALW_P

100 mA

+5VALW_BS

+5VALW_LX

+5VALW_P

100 mA

+3VS_SW

3VS_SS

1 2

PC3562

2200P_0402_25V7-K

+5VS_SW

5VS_SS

1 2

PC3561

2200P_0402_25V7-K

10_0603_5%

PR3511

1 2

+3VLP

10_0603_5%

PR3512

1 2

0.1U_0603_25V7K
PC3541

1 2

PC3545 4.7U_0603_6.3V6K

PC3554 0.1U_0603_25V7K

+5VLP

4.7U_0603_6.3V6K

1 2

1 2

PC3559

1 2

12

+3VALW

+5VALW

@

PC3568

1U_0402_6.3V6K

2

PL3501

1 2

1.5UH_PCMB063T-1R5MS_10A_20%

PJ3505

@

2

112

JUMP_43X39

PL3502

1 2

1.5UH_PCMB063T-1R5MS_10A_20%

PJ3506

@

2

112

JUMP_43X79

PJ3507

@

2

112

JUMP_43X79

+3VL

+3VS

+5VS

3VALW:
TDC=6A
OCP=8A
OVP=120%
Fsw=500KHz
5VALW:
TDC=8A
OCP=10A
OVP=120%
Fsw=500KHz

12

12

12

PC3539

PC3544

22U_0603_6.3V6-M

22U_0603_6.3V6-M

12

12

PC3555

PC3552

22U_0603_6.3V6-M

+3VALW_LX

12

+3VALW_SN

12

12

PC3542

PC3543

22U_0603_6.3V6-M

12

12

PC3553

22U_0603_6.3V6-M

22U_0603_6.3V6-M

PR3508

2.2_0805_5%

EMC_NS@

PC3532

1000P_0402_50V7K

EMC_NS@

22U_0603_6.3V6-M

PC3551

+5VALW_P

22U_0603_6.3V6-M

+5VALW_LX

12

+5VALW_SN

12

+3VALW_P

1

+

2

PR3509

2.2_0805_5%

EMC_NS@

1000P_0402_50V7K

1

PJ3502

2

112

JUMP_43X79

PJ3504

2

112

JUMP_43X79

PC3572
150U_B2_6.3VM_R35M

@

PC3533

EMC_NS@

@

@

+3VALW

+5VALW

B B

PR3522
750K_0402_5%

1 2

NEC@

2

G

PQ3503
2N7002WT1G

PD3503 1SS355VMT E-17

1 2

NEC@

1 2

PD3504 1SS355VMT E-17

NEC@

OTP_RESET 42

GPU_VDDC PHASE2

PRT08 NEC_R17 R18 part on PTC,NEC_UMA part on 0ohm
PRT07:NEC_R17 R18 part on PTC,NEC_UMA part in 0ohm
PRT06:NEC_R17part on PTC,NEC_R18 UMA part on 0ohm

3

VIN

V20B+

VDDQ_1.2 V

540_0402NEW_30%

PRT01

NEC@

PRT08

540_0402NEW_30%

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

540_0402NEW_30%

12

540_0402NEW_30%

12

GPU_VDDC PHASE1

Charger

PRT02

NEC@

PRT07

@

2015/08/20

2015/08/20

2015/08/20

PD3502

0_0402_5%

PR3519

EC_ON49,57

A A

1 2

@

1SS355VMTE-17

NEC@

PMBT3904

PQ3502

PR3520

100K_0402_1%

12

1 2

NEC@

13

C

2

B

E

NEC@

2

B

NEC@

NEC@

10K_0402_1%

31

E

PQ3501
PMBT3906

C

1 2

PR3521

1 2

NEC@

PC3571

1U_0603_25V7K

NEC@

13

D

S

5

4

PTC
(DC/DC FET protection)

APU_VDD PHASE1

540_0402NEW_30%

PRT03

12

12

NEC@

PRT06

540_0402NEW_30%

12

12

GPU_VDDC I A PU_SOC

@

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

APU_VDD PHASE2

540_0402NEW_30%

PRT04

12

NEC@

PRT05

540_0402NEW_30%

12

NEC@

2016/08/20

2016/08/20

2016/08/20

Titl e

Titl e

Titl e

PWR_3VALW/5VALW

PWR_3VALW/5VALW

PWR_3VALW/5VALW

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330G-ARR

330G-ARR

330G-ARR

1

49 53

49 53

49 53

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

LV5075_VCC

PC1910

22U_0603_6.3V6-M

PC1918

22U_0603_6.3V6-M

12

PC1911

12

PC1919

1 2

33K_0402_1%

PR1917

10_0603_5%

PR1907

1 2

12

PC1902

2.2U_0603_6.3V6K

PR1909

1 2

10_0402_5%

1 2

1U_0402_25V6-K

LV5075_0.9ALW_EN

LV5075_2.5V_EN

LV5075_0.9VS_EN

LV5075_1P8VA_EN

LV5075_VDDQ_EN

LV5075_VTT_EN

0.1U_0402_25V6

EMC_NS@

EMC_NS@

0.1U_0402_25V6

@

LV5075_CS

PC1901

PU1901

29

1

11

16

31

36

7
8

19

38

39

40

30

5

4

EN_LDO1

EN_LDO2

EN_V1P0A

EN_V1P8A

EN_VDDQ

EN_VTT

VIN_V1P0A_7
VIN_V1P0A_8

VIN_V1P8A_19

VIN_VTT

VTT

VSNS_VTT

CS_VDDQ

VIN_LDO1

VIN_LDO2

@

1 2

PR1901 0_0402_5%

1 2

@

PC1903

0.1U_0402_10V6-K

LV5075_VSYS

LV5075_PMIC_EN

9

28

41

27

VSYS

VCC

PMIC_EN

LV5075BGQV_VQFN40_5X5

UGATE_VDDQ

PHASE_VDDQ

T_ALERT_B

POK_V1P0A

POK_V1P8A

POK_VDDQ

LX_V1P0A_12
LX_V1P0A_13
LX_V1P0A_14
LX_V1P0A_15

LX_V1P8A_17
LX_V1P8A_18

VO_V1P8A_20

BOOT_VDDQ

LGATE_VDDQ

VSNS_VDDQ

GND

VO_V1P0A

LDO1

LDO2

FB_LDO2

SDA

SCL

LV5075_EC_SMB_DA2

25

LV5075_EC_SMB_CK2

26

LV5075_ALERT#

24

0.9V_PWRGD

22

APUALW_PWRGD

21

23

LV5075_LX_0.9VS

12
13
14
15

10

LV5075_LX_1P8

17
18

20

LV5075_UG_1.2V

33

LV5075_BST_1.2V

32

LV5075_LX_1.2V

34

LV5075_LG_1.2V

35

+1.2V_P

37

+0.9VALW_P

6

+2.5V_P

3

2

+2.5V_FB

12

12

EC_ON 39,49

1 2

PR1925 0_0402_5%

1 2

PR1926 0_0402_5%

1 2

PR1912 0_0402_5%

@

PR1915 100K_0402_5%

@

PR1927 100K_0402_5%

1 2

0.47UH_CMMB062D-R47MS_15A_20%

1 2

1UH_PH041H-1R0MS_3.8A_20%

PR1916

1 2

0_0603_5%

JUMP_43X39

PJ1907

112

1 2

PC1928

10U_0603_6.3V6M

PJ1910

112

JUMP_43X39

1 2

PC1935

PR1920

10U_0603_6.3V6M

24.9K_0402_1%

PR1921

10.5K_0402_1%

@

@

12

12

PL1901

PL1902

PC1925

1 2

0.1U_0603_25V7K

@

2

@

2

1A

+3VALW

+3VALW

+0.9VALW

0.9V:
VDDP_S5= 1A

LV5075_UG_1.2V

+2.5V

2.5V:
ICCMAX=240m A

LV5075_LG_1.2V

LV5075_LX_1P8

LV5075_LX_0.9VS

1 2

1 2

PR1918

PR1919

4.7_0603_5%

4.7_0603_5%

EMC_NS@

EC_SMB_DA2 34,39

EC_SMB_CK2 34,39

H_PROCHOT# 6,39

0.9V_PWRGD 39

APUALW_PWRGD 39

12

12

12

12

12

PC1915

PC1913

PC1914

PC1912

22U_0603_6.3V6-M

22U_0603_6.3V6-M

12

12

PC1921

PC1920

22U_0603_6.3V6-M

22U_0603_6.3V6-M

5

D

4

G

3

5

4

321

22U_0603_6.3V6-M

22U_0603_6.3V6-M

12

12

EMC_NS@

PQ1901

S11S22S3

0.47UH_CMMB062D-R47MS_15A_20%

AON7408L_DFN8-5

1 2

PQ1902

12

AON7506_DFN8-5

@

@

+0.9VS_P

12

PC1916

PC1917

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

+1.8VA_P

12

PC1922

PC1923

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

+1.2V_B+

12

PC1932

PC1929

0.1U_0402_25V6
10U_0805_25V6K

PL1903

1 2

PR1922

4.7_0805_5%

EMC_NS@

PC1943
680P_0402_50V7K

EMC_NS@

12

PC1930

12

@

PC1933

10U_0805_25V6K

12

EMC_NS@

12

PC1931

EMC_NS@

EMC_NS@

680P_0402_50V7K

680P_0402_50V7K

PJ1902

@

2

112

JUMP_43X79

PJ1904

@

2

112

JUMP_43X79

1.8VALW:
APU_VDD18+GPU_VDD18=2A +1A=3A(T DC)
TDC=3A
OCP=6A
OVP=12 0%
Fsw=1M

PJ1908

@

2

112

JUMP_43X39

12

12

PC1938

PC1937

22U_0603_6.3V6-M

22U_0603_6.3V6-M

0.9V:

0.9VS/VDDP =4A
TDC=6A
OCP=10 A
OVP=12 0%
Fsw=1M

+0.9V

+1.8VALW

V20B+

+1.2V_PLV5075_LX_1.2V

12

12

PC1941

PC1940

PC1939

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

@

1.2V:
VDDIO_MEM_S3=6A DRAM=7A
TDC=10A
OCP=20 A
OVP=12 0%
Fsw=1M

12

PJ1911

2

JUMP_43X79

PC1942

22U_0603_6.3V6-M

@

112

+1.2V

@

1 2

1_2VEN39

SYSON-1_2VEN

D D

C C

B B

SUSP#39,41,49,50

SUSP#39,41,49,50

EC_APU_ALWEN39,50

EC_APU_ALWEN39,50

APUALW_PWRGD

APUALW_PWRGD need delay to EC after 0.9VALW power up

EC Push,no pull high,not support 1.8V SPI mirror code

2_5VEN39

EC-2_5VEN

PR1902 0_0402_5%

12

PC1909 0.1U_0402_10V6-K

@

@

1 2

PR1904 0_0402_5%

12

PC1908 0.1U_0402_10V6-K

@

@

1 2

PR1906 0_0402_5%

1 2

PR1913 0_0402_5%

@

12

PC1907 0.1U_0402_10V6-K

@

@

1 2

PR1908 0_0402_5%

12

PC1906 0.1U_0402_10V6-K

@

@

1 2

PR1910 0_0402_5%

12

PC1905 0.1U_0402_10V6-K

@

@

1 2

PR1911 0_0402_5%

12

PC1904 0.1U_0402_10V6-K

@

LV5075_VDDQ_EN

LV5075_VTT_EN

LV5075_0.9VS_EN

LV5075_1P8VA_EN

LV5075_0.9ALW_EN

LV5075_2.5V_EN

+5VALW

+3VALW

+1.2V_P

+0.6VS

+1.8VALW

+3VALW

PJ1901

112

JUMP_43X39

PJ1903

112

JUMP_43X39

PJ1905

2

JUMP_43X39

JUMP_43X39

PJ1906

112

JUMP_43X39

PJ1909

112

112

@

2

@

LV5075_V1P8_VIN

2

+0.6VSP

@

@

2

@

2

+5VLP

+1.2V_B+

LV5075_0.9VS_VIN

1 2

PC1924
10U_0603_6.3V6M

12

22U_0603_6.3V6-M
PC1926

LV5075_0.9VALW_VIN

12

PC1927
10U_0603_6.3V6M

LV5075_2.5V_VIN

12

PC1934
10U_0603_6.3V6M

12

12

A A

Title

Title

Title

System PMIC

System PMIC

System PMIC

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

A2

A2

A2

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330G-ARR

330G-ARR

330G-ARR

1

50 53

50 53

50 53

5

4

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2014/02/20

2014/02/20

2014/02/20

2

Deciphered Date

Deciphered Date

Deciphered Date

2014/02/20

2014/02/20

2014/02/20

1.0

1.0

1.0

A

Vinafix.com

1 1

modify symbol PN：SA00008WM00, S IC LV5095BGQUF UQFN 29P PMIC，need updat e new SYMBOL

PJ3601

@

2

V20B+

PXS_PWREN7,52

+5VALW

PXS_PWREN +3VGS_EN

2 2

+3VALW

+1.8VALW

Lo adc ap aci ty ：
rail1=0.5A,Rdson=36mohm
rail2=1A,Rdson=18mohm
rail3=3.5A,Rdson=5mohm

112

JUMP_43X39

PX@

1 2

PR3602 200K_0402_1%

PX@

1 2

PC3604 0.1U_0402_25V6

PC3616 1U_0402_6.3V6KPX@

1 2

PC3614 0.1U_0402_25V6PX@

1 2

PR3604 0_0402_5%

PC3615 1U_0402_6.3V6KPX@

1 2

PR3608 20K_0402_1%PX@

1 2

PC3621 0.1U_0402_25V6PX@

PC3622

1U_0402_6.3V6K

12

12

PX@

PX@

PC3602

PC3601

10U_0805_25V6K

10U_0805_25V6K

12

+1.35V_VIN

+1.35V_EN

@

12

12

PX@

B

10_0603_5%

+1.35V_BST

5

18

12

VIN4

AGND

16

EN4

25

NC_3

22

NC_1

24

VCC_SW

19

EN2

21

VIN2

+1.8VGS_ENPXS_PWREN

28

EN3

1

VIN3_1

2

VIN3_2

29

VIN3_3

14

PR3611

100K_0402_1%

@

1 2

PC3629

1U_0402_6.3V6K

VBOOT

PX@

VCC

TH_ALT

17

12

PX@

PR3615

1 2

PX@

PU3601

+1.35V_LX +1.35V_P

3

SW_1

4

SW_2

15

FB

23

NC_2

6

PGND_1

7

PGND_2

8

PGND_3

9

PGND_4

10

PGND_5

11

PGND_6

20

VOUT2

26

VOUT3_1

27

VOUT3_2

PGOOD

13

PR3610
100K_0402_1%

@

1 2

12

PX@

PC3603

0.1U_0603_25V7K

12

PR3603

2.2_0603_5%

EMC_NS@

12

PC3619

1000P_0402_50V7K

EMC_NS@

0.68UH_PCMB063T-R68MN_16A_20%

PL3601

1 2

PX@

12

PC3620

560P_0402_50V7-K

C

1K_0402_1%

PR3606

1 2

PX@

PX@

+1.35V_FB

D

+1.35VGS:
VMEMIO=2A/8A memory=6A
FB=0.6V

TDC=10A
OCP=13A
OVP=130%

12

PC3607

PX@

Fsw=500Khz

12

12

PC3612

PC3609

22U_0603_6.3V6-M

22U_0603_6.3V6-M

PX@

@

12

PC3610

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

+3VGS

+3VGS:

VDD_33=10mA

+1.35VGS

@

PJ3602

2

112

12

PR3613

12

PR3607

12

PR3609

PX@

10_0402_1%

PX@

42.2K_0402_1%

PX@

32.4K_0402_1%

12

PC3611

PX@

12

PR3614
0_0402_5%

@

GPU_VMEMIO_SENSE

12

12

12

PC3606

22U_0603_6.3V6-M

22U_0603_6.3V6-M

PX@

@

12

PX@

@

PC3617

PC3618

1U_0402_6.3V6K

10U_0603_6.3V6M

JUMP_43X79

12

PC3608

PC3613

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

23

+1.8VGS

12

12

PX@

@

PC3623

PC3624

10U_0603_6.3V6M

1U_0402_6.3V6K

+1.8VGS:

VDD_18=1A

3 3

4 4

Title

Title

Title

PWR_1.35VGS

PWR_1.35VGS

PWR_1.35VGS

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

A2

A2

A2

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330G-ARR

330G-ARR

330G-ARR

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

D

51 53

51 53

51 53

A

B

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2013/08/15

2013/08/15

2013/08/15

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

V20B+

12

12

EMC_PX@

PX@

PC604

0.1U_0402_25V6
10U_0805_25V6K

PL601

PX@

0.22UH_PCME064T-R22MS0R985_28A_20%

1 2

@

PJ601
JUMPER

1 2

12

PR612

2.94K_0603_1%

PX@

PR628

2.94K_0603_1%

PX@

1 2

PC616

12

0.1U_0402_25V7-K

PX@

12

12

PC619

EMC_PX@

0.1U_0402_25V6

PX@

PL602

0.22UH_PCME064T-R22MS0R985_28A_20%

1 2

@

PJ603

JUMPER

JUMPER

1 2

12

PR644

2.94K_0603_1%

PX@

PR627

2.94K_0603_1%

1 2

PX@

0.1U_0402_25V7-K
PC638

12

PR652

1 2

5.9K_0402_1% PX@

R17@

PC645

10U_0805_25V6K

0.36UH_PDME064TR36MS1_24A_20%

1 2

12

1 2

PX@

PC605

10U_0805_25V6K

@

PJ602
JUMPER

1 2

PC607

PX@

PX@

12

PC620

PC623

10U_0805_25V6K

10U_0805_25V6K

@

PJ604

1 2

PX@

V20B+

L=0.3 6uH
DCR=1.4m ohm
Irms= 24A
Isat= 24A
Si ze：6. 8 *7 .3 * 4

R17@

PL603

1 2

@

PJ605
JUMPER

PR659

1.65K_0603_1%

R17@

PR662

1.65K_0603_1%

R17@

PC652

12

0.1U_0402_25V7-K

R17@

L=0.2 2uH
DCR=0.98m ohm
Irms= 34A
Isat= 35A
Si ze：6. 8 *7 .6 * 4

1

1

12

+

PC608

2

330U_D2_2V_Y

R18@

V20B+

1

+

PC627

2

330U_D2_2V_Y

R18@

@

PJ606
JUMPER

1 2

12

+

PC609

2

@

330U_D2_2V_Y

PX@

22U_0603_6.3V6-M

R17-P1-50-18W:+ VDDC
LL=0.6m
TDC=20A
EDC=50A
OCP=80A
DC tolerance=VID-VDDCX0.6 +/- 20m V
AC tolerance: overshoot 120mV, undershoot 90mV

R18-M2-60-18W:+VDDC merger VDDCI
LL=1.0m
TDC=25A
EDC=60A
OCP=80A
DC tolerance=VID-VDDCX1.0 +/- 15m V
AC tolerance: overshoot TDB, undershoot TDB

1

12

12

+

PC628

PC631

PC630

2

PX@

22U_0603_6.3V6-M

330U_D2_2V_Y

R18@

1

12

+

PC647

2

R17@

330U_D2_2V_Y

330U change PN from SGA00008Q00 to SGA20331E1J 7/24

+VDDC

12

12

12

PC610

PC4363

PC4362

PC654

@

22U_0603_6.3V6-M

0.1U_0402_25V6

@

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

EMC_PX@

12

12

2

JUMP_43X79

2

JUMP_43X79

+VDDC

PC632

0.1U_0402_25V6

EMC_PX@

+VDDCI1

PC650

0.1U_0402_25V6

EMC_R17@

@

PJ2404

112

+VDDCI

@

PJ2406

112

+VDD_08

12

12

PC4364

PC4365

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

@

R18@

R17-P1-50:+VDDCI m erger +VDD_08

0.875V
TDC=8A
EDC=12A
OCP=14A
DC tolerance: +/-3%
AC tolerance: +/-3%

12

R17@

R17@

PC648

PC649

22U_0603_6.3V6-M

22U_0603_6.3V6-M

+VDDCI1

+VDDCI1

R17M-P1-50 -PJ2404 PJ2406short

1 2

1 2

PR648

1 2

1 2

EMC_NS@

PR636

4.7_0603_5%

EMC_NS@

1_0402_1%PX@

EMC_NS@

PR604

4.7_0603_5%

EMC_NS@

PC613
680P_0402_50V7K

1_0402_1%

1 2

5.9K_0402_1%

1 2

PC634
680P_0402_50V7K

12

VDDCI_PHASE

12

PC602

PR618

PX@

PR621

PX@

12

12

R17@

PC642

0.1U_0402_25V6

EMC_R17@

PC644

10U_0805_25V6K

EMC_NS@

PR658

4.7_0603_5%

1 2

EMC_NS@

PC651
680P_0402_50V7K

1 2

5

PQ601

VDDC_ISEN2P

VDDC_ISEN1N

VDDC_ISEN1P

AON6380_DFN8-5

4

321

PX@

VDDC_PHASE1

5

PQ602
AON6324_DFN8-5

4

321

PX@

VDDC_ISEN1P

VDDC_ISEN1N

VDDC_ISEN2P

5

PQ603
AON6380_DFN8-5

4

321

PX@

VDDC_PHASE2

5

PQ604
AON6324_DFN8-5

4

321

PX@

1 2

5

D

PQ605

4

AON7408L_DFN8-5

G

R17@

S11S22S3

3

5

PQ606

4

AON7506_DFN

R17@

321

VDDCI_ISEN1P

VDDCI_ISEN1N

VDDC_UGATE1

PR601

PX@

0_0402_5%

+VDDC

PX@

+VDDCI

0.47U_0402_25V6K
PC640

12

+1.8VGS

PX@

+3VGS

12

PR617

4.7K_0402_1%

VDDCI_ISEN1N

VDDCI_ISEN1P

1 2

100_0402_1%

1 2

100_0402_1%

1 2

0_0402_5%

1 2

@

PR603

PX@

PR606

PX@

PR607

PX@

330P_0201_25V7-K

@

1 2

PR661 0_04 02_5%

3.9_0402_1%
PR647

PX@

12

@

1 2

PR623

0_0402_5%

2.2_0402_1%
PR632

1 2

12

PC633

1U_0402_6.3V6K

12

PR660
0_0402_5%

R18@

100_0402_1%

PR640

R17@

1 2

1 2

PR641

R17@

0_0402_5%

1 2

PC614

GPU_POK_R

PX@

PX@

@

VDDC_TSEN

3662_SET1

VDDC_IMON

3662_VREF

VDDCI_IMON

VDDCI_FB_R

330P_0402_50V8J

PC611

PX@

1 2

1 2

PR608

PX@

10K_0402_1%

@

1 2

PR611 0_04 02_5%

12

PC618

PX@

0.1U_0402_25V6

11

VRHOT_L

12

TSEN

13

SET1

14

IMON

15

VREF_PINSET

16

IMON_NB

18

PWROK

19

SVC

20

SVD

21

SVT

0.1U_0402_25V6

330P_0402_50V8J

PC636

R17@

1 2

1 2

PR642

R17@

10K_0402_1%

12

PC639

@

330P_0201_25V7-K

PC612

68P_0402_50V8J

1 2

PR609

1 2

31.6K_0402_1%

VDDC_VSEN

VDDC_ISEN1N

8

9

10

VSEN

ISEN1P

ISEN1N

PU601
RT3662ACGQW_WQFN40_5X5

VDDIO22TSEN_NB23ISENN_NB24ISENP_NB25FB_NB26COMP_NB27VIN28EN29BOOT_NB

GND

41

3662_VDDIO VDDC_ISEN1P

VDDCI_TSEN

PC653

R17@

12

68P_0402_50V8J

1 2

1 2

71.5K_0402_1%

PX@

R18 LL=1mohm,PR609=18.7K

R17@

R17 LL=0.6mohm,PR609=31.6K

VR_VGA_PWRGD

VDDC_BOOT2

VDDC_UGATE2

VDDC_FB

VDDC_COMP

VR_VGA_PWRGD

3662_RGND

VDDC_ISEN2P

6

4

5

2

7

3

1

FB

RGND

COMP

PHASE2

BOOT2

ISEN2P

PGOOD

UGATE2

LGATE2

UGATE1

PHASE1

R17@

R17@

LGATE1

LGATE_NB

PHASE_NB

UGATE_NB

30

VDDCI_COMP

VDDCI_BOOT

VDDCI_EN_1

3662_VIN

VDDCI_FB

PX@

PC637

PR643

BOOT1

PVCC

10K_0402_1%

PR610

1 2

VCC

VDDC_PHASE1

PR602

PC606

2.2_0603_5%

VDDC_BOOT1

VDDC_LGATE1

17

PX@

40

39

38

37

36

35

34

17

33

32

31

VDDC_PHASE2

VDDC_LGATE2

VDDC_BOOT1

VDDC_UGATE1

VDDC_PHASE1

VDDC_LGATE1

3662_PVCC

3662_VCC

VDDCI_LGATE

VDDCI_PHASE

VDDCI_UGATE

1 2

PR638

100K_0402_1%

1 2

PC4360

0.1U_0402_25V6

1 2

PR639

4.7_0402_5%

1 2

PC635

0.1U_0402_25V6

+3VGS

+5VALW

VDDC_UGATE2

VDDC_PHASE2

VDDC_BOOT2

VDDC_LGATE2

VDDCI_UGATE

VDDCI_PHASE

VDDCI_BOOT

VDDCI_LGATE

@

1 2

PR622 0_0 603_5%

1 2

PR624

PX@

4.7_0402_5%

1

1

PC624

PC625

2

2

PX@

PX@

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

7,51,52

PX@

PX@

PX@

PX@

PXS_PWREN

V20B+

1 2

PX@

PR633

2.2_0603_5%

1 2

PX@

PR657

2.2_0603_5%

1 2

R17@

1 2

0.1U_0603_25V7K

PX@

PC626

0.1U_0603_25V7K

1 2

PX@

1 2

PC646

0.1U_0603_25V7K

R17@

GPU_VSSC_SENSE20

D D

GPU_VDDC_SENSE20

3662_VREF

12

PR614
665K_0402_1%

PX@

C C

12

PR637
16K_0402_1%

PX@

12

12

12

12

PR615

64.9K_0402_1%

PX@

PR619

1.43K_0402_1%

PX@

PR630

33.2K_0402_1%

PX@

PR634
402_0402_1%

PX@

12

12

VDDC_TSEN_R

VDDCI_TSEN_R

12

PR631

24.3K_0402_1%

R17@

PR635
100_0402_1%

R17@

1 2

PR616
255K_0402_1%

R17@

PR620

4.53K_0402_1%

R17@

100K_0402_1%_NCP15WF104F03RC

PH601

PX@

1 2

1 2

PR626

PX@

60.4K_0402_1%

60.4K_0402_1%
PR629

R17@

1 2

1 2

PH602

R17@

100K_0402_1%_NCP15WF104F03RC

VDDC_TSEN

3662_SET1

VDDCI_TSEN

GPU_VR_HOT#18 ,39

VGA_PWROK17

GPU_VR_HOT#

GPU_VR_HOT# pull high to +3VGS at GPU

1 2

PR4396 4.7K_0402_1%

+1.8VGS

VGA_PWROK

GPU_SVC18

GPU_SVD18

GPU_SVT18

VBOOT Pull high/ low portion

3662_VREF

10.5K_0402_1%
PR646

PX@

1 2

1 2

1 2

15.8K_0402_1%

R17@

11.8K_0402_1%

PR649

1 2

PR654

PX@

R17@

1 2

PR650

1.33K_0402_1%

1 2

PR655

8.87K_0402_1%

PX@

R17@

PH603

PX@

100K_0402_1%_NCP15WF104F03RC

14.7K_0402_1%

1 2

PR653

VDDCI_IMON_R

1 2

PH604

R17@

100K_0402_1%_NCP15WF104F03RC

B B

1 2

PR651

0_0402_5%

1 2

PR656
0_0402_5%

R17@

VDDC_IMONVDDC_IMON_R

PX@

VDDCI_IMON

PR4377

VDDCI_ISEN1P

10K_0402_1%

R18@

12

+5VALW

R18M-M2-60 -disable VDDCI

GPU_VDDCI_SENSE20

1U_0402_10V6K

+5VALW

PC701

R18@

+1.2V

A A

PXS_PWREN7,51,52

+1.2V

R18@

R18@

R18@

12

12

12

PC6083

PC6084

PC6082

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

PC702

1 2

PR701

40.2K_0402_1%

R18@

12

R18@

12

add 3pcs 22*uf capacity for 1.2V current add with R18 M2 60 GPU

5

4

3

R18@

PU701 APL59 30CKAI-TRG_SO8

6

7

VCNTL

POK

5

VIN

3

VOUT1

+VDD_08_1_EN

12

@

PC703

0.1U_0402_25V7-J

2

4

VOUT2

8
9

Security Classificat ion

Security Classificat ion

Security Classificat ion

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

EN
EPAD

Issued Date

Issued Date

Issued Date

+VDD_08_1_FB

2

2017/06/24

2017/06/24

2017/06/24

12

R18@

PR703

4.53K_0402_1%

12

R18@

PR702

24K_0402_1%

LC Future Center Sec ret Data

LC Future Center Sec ret Data

LC Future Center Sec ret Data

FB

GND

1

@

12

PC704

220P_0402_50V7K

Deciphered Date

Deciphered Date

Deciphered Date

R18@

12

PC705

22U_0603_6.3V6-M

0.95V for R18M-M2-60 +VDD_08_1

0.95V
TDC:2A
Max: 3A

+VDDC

R18@

R18@

12

12

PC706

22U_0603_6.3V6-M

+VDD_08_1

PC707

22U_0603_6.3V6-M

R18M-M2-60 -PJ2403 PJ2405short

Title

Title

2018/06/23

2018/06/23

2018/06/23

Title

PWR-GPU_CORE_AMD

PWR-GPU_CORE_AMD

PWR-GPU_CORE_AMD

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sh eet o f

Date: Sh eet o f

Date: Sh eet o f

1

PJ2403

2

JUMP_43X79

PJ2405

2

JUMP_43X79

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

@

112

@

112

330G-ARR

330G-ARR

330G-ARR

+VDDCI

+VDD_08_1

+VDD_08

52 53

52 53

52 53

1.0

1.0

1.0

5

Vinafix.com

PR5902 close to APU side

D D

VDDCR_VSS_SENSE6

Kelvin routing

VDDCR_VCC_SENSE6

+VDDC_VDD

PR5903 close to APU side

APU_VREF

12

12

VR-HOT indicator,close to VDDCR_VDD choc k

100K_0402_1%_NCP15WF 104F03RC

1 2

PR5921

PR5919

PR5920

1 2

261K_0402_1%

261K_0402_1%

26.7K_0402_1%

C C

1 2

PR5935

620_0402_1%

APU_VREF

B B

+1.8VS

PR5981

PR5986

10K_0402_1%

1 2

@

PR5982
10K_0402_1%

1 2

@

A A

PR5985

10K_0402_1%

10K_0402_1%

1 2

1 2

@

@

PR5984

PR5983

10K_0402_1%

10K_0402_1%

1 2

1 2

@

@

PH5901

1 2

PR5929

60.4K_0402_1%

60.4K_0402_1%
PR5934

1 2

PH5902

1 2

12

100K_0402_1%_NCP15WF 104F03RC

VR-HOT indicator,close to VDDCR_SOC chock

PR5936

1 2

PR5937

24K_0402_1%

24.3K_0402_1%

10.5K_0402_1%
PR5942

1 2

PR5947

PH5903

1 2

1 2

15.8K_0402_1%

100K_0402_1%_NCP15WF 104F03RC

19.6K_0402_1%
PR5951

1 2

PH5904

PR5952

1 2

1 2

100K_0402_1%_NCP15WF 104F03RC

6.98K_0402_1%

APU_SVC

APU_SVD

12

APU_SVT

PC6079

@

@

0.1U_0402_25V7- J

VDDCR_TSEN

APU_SET1

SOC_TSEN

1.5K_0402_1%

PR5948

VDDCR_IMON

1 2

21.5K_0402_1%

PR5953

SOC_IMON

1 2

12

12

PC6081

PC6080

@

0.1U_0402_25V7- J

0.1U_0402_25V7- J

VR_HOT#39,48

fixed 0.8V output reference output voltage

delete PWROK pull high EEside pull high

APU_PWROK6

APU_SVC6

APU_SVD6

APU_SVT6

APU_SVC

APU_SVD

APU_SVT

+VDDCR_SOC

VDDCR_SOC_VCC_SENSE6

Kelvin routing

+1.8VS

PR5941 close to APU side

5

PR5902

20_0402_1%

1 2

PR5901

10_0402_1%

PR5904

10_0402_1%

1 2

PR5903

20_0402_1%

+3VS

12

PR5995

4.7K_0402_1%

@

0.47U_0402_25V6K

PC5954

12

4

12

follow richtek suggestion

12

@

1 2

PR5956 0_0402_5%

3.9_0402_1%

PR5943

1 2

@

1 2

PR5926 0_0402_5%

2.2_0603_5%
PR5938

12

PC5937

12

1U_0402_6.3V6K

1 2

PR5941

100_0402_1%

12

PR5944
10_0402_1%

4

PC6076

1 2

680P_0402_50V7K

PC5909

1 2

330P_0402_50V7K

@

VDDCR_ISEN1P

VDDCR_ISEN1N

VDDCR_ISEN2P

@

APU_VR_HOT_L

VDDCR_TSEN

APU_SET1

VDDCR_IMON

APU_VREF

SOC_IMON

APU_POK_R

SOC_FB_R

PR5991

@

12

100_0402_5%

1 2

PC5906

220P_0402_50V7K

1 2

PR5905

10K_0402_1%

1 2

PR5993 0_0402_5%

0.1U_0402_25V6

11

12

13

14

15

16

18

19

20

21

SOC_ISEN1N

SOC_ISEN1P

220P_0402_50V7K

1 2

10K_0402_1%

reserved

PC5947
330P_0402_50V7K

1 2

@

@

PC5927

1 2

10

ISEN1N

VRHOT_L

TSEN

SET1

IMON

VREF_PINSET

IMON_NB

PWROK

SVC

SVD

SVT

GND

41

PC5938

1 2

0.1U_0402_25V6

1 2

PC5944

PR5945

12

@

12

@

PC5907

1 2

56P_0402_50V8-J

PR5906

1 2

31.6K_0402_1%

VDDCR_VSEN

VDDCR_FB

VDDCR_COMP

APU_PGOOD

APU_RGND

3

7

9

5

8

6

FB

VSEN

RGND4COMP

ISEN2P

ISEN1P

PGOOD

VDDIO22TSEN_NB23ISENN_NB24ISENP_NB25FB_NB26COMP_NB27VIN28EN29BOOT_NB

SOC_COMP

SOCI_FB

SOC_TSEN

APU_VDDIO

APUPWR_EN_R

APU_VIN

PC5945

1 2

56P_0402_50V8-J

1 2

PR5946

35.7K_0402_1%

PR5992
100_0402_5%

follow richtek suggestion

PC6077
680P_0402_50V7K

+3VS

12

PR5971

10K_0402_1%

@

1 2

PR5916 0_0402_5%

VDDCR_BOOT2

VDDCR_UGATE2

PU5901

1

2

RT3662ACGQW_WQF N40_5X5

40

BOOT2

PHASE2

UGATE2

39

LGATE2

38

BOOT1

37

UGATE1

36

PHASE1

35

LGATE1

34

PVCC

17

VCC

33

LGATE_NB

32

PHASE_NB

31

UGATE_NB

30

SOC_BOOT

PR5975 0_0402_5%

0.1U_0402_25V6

0.1U_0402_25V6

1 2

PC6071

1 2

4.7_0603_5%
PR5939

1 2

PC5940

1 2

@

VDDCR_PHASE2

VDDCR_LGATE2

VDDCR_BOOT1

VDDCR_UGATE1

VDDCR_PHASE1

VDDCR_LGATE1

APU_PVCC

APU_VCC

SOC_LGATE

SOC_PHASE

SOC_UGATE

VR_APU_PWRGD 39

1 2

PR5925 0_0603_5%

1 2

PR5927

2.2_0603_5%

1

1

PC5934

PC5935

2

2

2.2U_0402_6.3V6 -K

2.2U_0402_6.3V6 -K

EC_VR_ON

V20B+

+5VALW

@

39

3

VDDCR_UGATE2

VDDCR_PHASE2

PR5907

VDDCR_BOOT2_RVDDCR_BOO T2

1 2

2.2_0603_5%

VDDCR_LGATE2

VDDCR_UGATE1

VDDCR_PHASE1

PR5974

VDDCR_BOOT1 VDDCR_BOOT1_R

1 2

2.2_0603_5%

VDDCR_LGATE1

SOC_UGATE

SOC_PHASE

SOC_BOOT SOC_BOOT_R

1 2

PR5949

2.2_0603_5%

SOC_LGATE

3

1 2

0.22U_0603_25V7K

PC5946

1 2

0.22U_0603_25V7K

PC5908

PC5994

1 2

0.22U_0603_25V7K

2

V20B+

6A

1

PR5908

2

10U_0805_25V6- K

PC5919

EMC_NS@

EMC_NS@

SOC_PHASE

1

+

+

PC5986

PC5904

PC5987

2

2

22U_25V_M

@

EMC_NS@

4.7_0805_5%

EMC_NS@

VDDCR_ISEN2P

1000P_0402_50V7 K

VDDCR_ISEN1N

VDDCR_ISEN1P

VDDCR_ISEN1P

PR5933

VDDCR_ISEN1N

1 2

1_0402_1%

VDDCR_ISEN2P

1A

SOC_ISEN1P

SOC_ISEN1N

1 2

PR5977 0_0402_5%

L=0.24 uH
DCR=1.14m ohm

68U_25V_M

Irms=3 5A
Isat=3 2A
Si ze：7. 4* 6. 8* 3

PL5901

0.24UH_PCME063T-R24MS1R145_ 35A_20%

1 2

@

@

PJ5903

PJ5904

JUMPER

JUMPER

1 2

1 2

12

PR5909

Kelvin routing

2.74K_0603_1%

12

PR5958

2.74K_0603_1%

PC5920

1 2

0.1U_0402_25V7-K

PR5913

1 2

1_0402_1%

PR5959

1 2

5.49K_0402_1%

PL5902

0.24UH_PCME063T-R24MS1R145_ 35A_20%

1 2

@

PJ5905
JUMPER

1 2
12

PR5932

Kelvin routing

2.74K_0603_1%

12

PR5960

2.74K_0603_1%

PC5918

1 2

0.1U_0402_25V7-K

PR5961

1 2

5.49K_0402_1%

12

@

PC515

PJ5906
JUMPER

1 2

12

PC519

PC520

22U_0603_6.3V6- M

22U_0603_6.3V6- M

@

V20B+

PL5903

0.24UH_PCME063T-R24MS1R145_ 35A_20%

1 2

@

@

PJ5907

PJ5908

JUMPER

JUMPER

1 2

1 2

12

PR5957

Kelvin routing

2.74K_0603_1%

12

PR5955

2.74K_0603_1%

PC5939

1 2

0.1U_0402_25V7-K

PR5940

12

5.49K_0402_1%

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

2017/03/14

2017/03/14

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2017/03/14

1

+

PC5911

2

330U_D2_2V_Y

12

12

PC5923

PC5921

PC5925

22U_0603_6.3V6- M

22U_0603_6.3V6- M

12

12

12

PC516

PC517

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

12

12

12

PC521

PC522

22U_0603_6.3V6- M

22U_0603_6.3V6- M

@

@

@

10A

1

1

+

PC6070

2

2

330U_D2_2V_Y

12

12

PC6095

10U_0402_6.3V6M

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

+

PC5912

2

330U_D2_2V_Y

12

PC5973

22U_0603_6.3V6- M

12

PC518

22U_0603_6.3V6- M

12

PC523

22U_0603_6.3V6- M

@

+

PC5964

330U_D2_2V_Y

PC6096

10U_0402_6.3V6M

12

12

5

4

321

5

4

PQ5902

AON6324_DFN8-5

321

12

PQ5901

AON6380_DFN8-5

5

4

PQ5903

AON6324_DFN8-5

321

12

EMC@

EMC@

PC5905

PC6069

2200P_0402_25V7 -K

PC5903

0.1U_0402_25V6
10U_0805_25V6- K

VDDCR_PHASE2

12

VDDCR_SN2

12

V20B+

12

12

12

12

EMC_NS@

5

4

PQ5904

321

5

4

PQ5905

AON6324_DFN8-5

321

12

5

PC5941

4

4

10U_0805_25V6- K

PQ5907

AON6380_DFN8-5

321

5

PQ5908

AON6324_DFN8-5

321

EMC_NS@

PC5932

PC5990

AON6380_DFN8-5

5

4

PQ5906

AON6324_DFN8-5

321

12

12

12

PC5942

PC5992

PC5943

EMC@

0.1U_0402_25V6
2200P_0402_25V7 -K

10U_0805_25V6- K

PC5931

PC5930

2200P_0402_25V7 -K

0.1U_0402_25V6
10U_0805_25V6- K

10U_0805_25V6- K

VDDCR_PHASE1

12

PR5924

4.7_0805_5%

VDDCR_SN1

12

PC5936

1000P_0402_50V7 K

EMC@

12

PR5950

4.7_0805_5%

EMC_NS@

SOC_SN1

12

PC5955

EMC_NS@

680P_0402_50V7K

1

+VDDC_VDD

35A

1

1

+

+

PC5956

PC5957

2

2

330U_D2_2V_Y

330U_D2_2V_Y

12

12

12

PC5974

PC5975

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

PC5977

22U_0603_6.3V6- M

12

PC5978

22U_0603_6.3V6- M

12

12

PC5979

PC5980

22U_0603_6.3V6- M

22U_0603_6.3V6- M

APU_VD DCR
FSW=400KHz

Slew rate:12.5mv/us
TDC=35A EDC=45A
OCP=67.5A
OVP=VID+ 300 mV
Load Line=0.7mohm
Ripple:+/ -20mv
MAX AC: VID_VDDC +95mv
MIN AC: VID_VDDC -80mv

12

12

PC5959

PC5963

22U_0603_6.3V6- M

22U_0603_6.3V6- M

+VDDC_VDD

12

12

PC514

22U_0603_6.3V6- M

@

12

12

PC5962

PC5976

10U_0402_6.3V6M

10U_0402_6.3V6M

12

PC6086

PC6085

22U_0603_6.3V6- M

22U_0603_6.3V6- M

@

@

12

12

12

PC5961

PC5958

PC5960

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

12

12

12

PC6088

PC6087

PC6089

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

@

@

@

VDDCR_ SOC
FSW=300KHz

Slew rate :12.5mv/us
TDC=10A EDC=13A
OCP= 20A
OVP=VID+ 300 mA
Ripple:+/ -20mv
MAX AC: VID_VDDCR_SOC +70mv
MIN AC: VID_VDDCR_SOC -40mv

12

12

12

12

PC5922

PC5924

10U_0402_6.3V6M

10U_0402_6.3V6M

12

12

PC6090

22U_0603_6.3V6- M

@

12

12

PC6091

PC6094

PC5926

PC6093

PC6092

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

+VDDCR_SOC

12

12

12

PC5951

22U_0603_6.3V6- M

12

12

12

12

PC524

PC5972

PC5966

PC5968

PC5953

PC5971

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

+VDDCR_SOC

12

2017/03/01

2017/03/01

2017/03/01

12

PC526

PC525

22U_0603_6.3V6- M

22U_0603_6.3V6- M

@

@

1

12

12

12

12

PC530

PC528

PC529

PC527

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

22U_0603_6.3V6- M

@

@

@

@

Title

Title

Title

PWR-VDDCR/SOC

PWR-VDDCR/SOC

PWR-VDDCR/SOC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

330G-ARR

330G-ARR

330G-ARR

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date: Shee t o f

Date: Shee t o f

Date: Shee t o f

53 53

53 53

53 53

1.0

1.0

1.0