Lenovo Ideapad 330-15AR Schematic

A

Vinafix.com

1 1

B

C

D

E

LCFC

NM_B681 M/B Schematics Document

2 2

AMD FP5 Raven Ridge SoC with DDRIV

AMD R17M-P1-50/R18M-M2-60

2017-09-6

REV:1.0

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D

A

B

AND TRADE SECRET INFORMATION. THIS SHEET MAYNOT BE TR ANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USE D BYOR DISCLOSED TO ANYT HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAYBE USE D BYOR DISCLOSED TO ANYT HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

MAYBE USE D BYOR DISCLOSED TO ANYT HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CEN TER.

2013/08/15

2013/08/15

2013/08/15

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

D

Titl e

Titl e

Titl e

Cover Page

Cover Page

Cover Page

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

E

1 52

1 52

1 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

D D

C C

B B

PRT06

0_0402_5%

SD02800008J

PRT07

0_0402_5%

SD02800008J

PRT08

0_0402_5%

SD02800008J

PR609

NEC_UMA@

NEC_UMA@

NEC_UMA@

R18@

PRT06

540_0402NEW_30%

SL20000220J

PRT07

540_0402NEW_30%

SL20000220J

PRT08

540_0402NEW_30%

SL20000220J

NEC_R17@

NEC_R17@

NEC_R17@

PRT06

0_0402_5%

SD02800008J

PRT07

540_0402NEW_30%

SL20000220J

PRT08

540_0402NEW_30%

SL20000220J

NEC_R18@

NEC_R18@

NEC_R18@

R18 LL=1mohm,PR609=18.7K
R17 LL=0.6mohm,PR609=31.6K

18.7K_0402_1%

SD03418728J

A A

Title

Title

5

4

Title

Size

Size

Size

Dat e: Sheet o f

Dat e: Sheet o f

3

Dat e: Sheet o f

<Title>

<Title>

<Title>

Document Number R ev

Document Number R ev

Document Number R ev

<Doc> 1.0

A

<Doc> 1.0

A

<Doc> 1.0

A

1 1Friday, March 23, 2018

1 1Friday, March 23, 2018

2

1 1Friday, March 23, 2018

1

A

Vinafix.com

B

C

D

E

AMD: R17M-P1-50
R18M-M2-60
Package: S4a

1 1

VRAM 256*16

PCI-Express

8x Gen3

PEG 0~7

GDDR5*2 2G

HDMI x4 Lane Port1

Channel A

1.2V DDR4 2400MT/s

Memory BUS (DDR4)
Channel B

1.2V DDR4 2400MT/s

Memory BUS (DDR4)

DDR4-SO-DIMM X1

UP TO 8G x 1

DDR4 DRAM DOWN

4pcs x16

HDMI Conn.

eDP Conn

eDP x2 Lane port0

USB 3.0 1x
USB 2.0 1x

Int. Camera

USB 2.0 Port1

Int. DMIC Conn.

AMD FP5 APU

USB 3.0 1x
USB 2.0 1x

2 2

SATA HDD

SATA Port0

SATA Gen3

Raven Ridge TDP 15W

USB 3.0 1x

SATA ODD

NGFF Card
WLAN&BT
Key E

USB 2.0 Port

fingerprint

USB 2.0 Port

reserve

3 3

Touch Screen

USB 2.0 Port

USB 2.0 1x
USB 2.0 1x

USB 2.0 1x

USB HUB

GL850G

SATA Port1

PCIe Port1

USB 2.0 Port5

SATA Gen1

PCIe 1x

USB2.0 1x

USB2.0(480M) 1x

USB2.0 1x

HD Audio

BGA-1140P

35mm*25mm

USB 2.0 1x

PCIe 1x

SPI BUS

USB Left

USB 2.0 Port4
USB 3.0 Port4

USB Left

USB 2.0 Port2
USB 3.0 Port2

USB Repeater

Parade PS8713

USB 3.0 Port3
USB 2.0 Port3

LAN Realtek

RTL8111GUL

PCIe Port2

SPI ROM

8MB

USB 3.0 1x

CC logic&Mux

Realtek RTS5449

RJ45 Conn.

USB 3.0 2x

Type C Conn

USB 2.0 Port0

Codec&Card reader

Realtek_RTS5199

SPK Conn.

SD/MMC Conn.

LPC

TPM

reserve

EC

HP&Mic Combo Conn.

IT8586E-FX_LQFP128

Sub-board for 15&17

4 4

A

B

Int.KBDTouch Pad

Security Cl assification

Security Cl assification

Security Cl assification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

Thermal Sensor
NCT7718W

C

reserve

2013/08/15

2013/08/15

2013/08/15

Thermistor

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2013/08/15

2013/08/15

2013/08/15

ODD BOARD

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 23, 2018

330ARR

330ARR

330ARR

E

2 52

2 52

2 52

1.0

1.0

1.0

A

Vinafix.com

Voltage Rails

1 1

2 2

plane

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

( O --> Means ON , X --> Means OFF )

B+
(+20VSB )

+3VL

+5VLP

O

O

O

O

X

+5VALW

+3VALW
(+3VALW _APU)

+1.8VAL W

+0.9VAL W

+1.2V

O

O

O

X

O

X X

X

X X X

+5VS

+3VS

+1.8VS

+0.9VSpower

+0.6VS

+2.5VS

+VDDC_V DD

+VDDCR_ SOC

+VDDC

+VDDCI

+3VGS

+1.8VGS

+1.35VG S

B

SOURCE

+3VALW

SIGNAL

SLP_S3# SLP _S5# +VALW +V +VS Clock

HIGH HIGH

LOW

LOW LOW

Device

Touch Pad

+3VS

Address

?

?

STATE

S0 (Full ON)

S1 (Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

OO

I2C Control Table

X

TP_I2C0 _SCL APU

TP_I2C0 _SDA

X

APU I2C address

Device

Elan：S A469 D- 22 HA 69x104x1. 0

Synaptics ：T M- P3255-00 8 69x104x 1. 0

HIGHHIGH

HIGHLOW

LOW

C

ON

ONONON ON

ON

ON

ON

ON

OFF

ON

OFF

Port List

HSIO Port

GPP

GFX

ON

OFF

OFF

OFF

LOW

OFF

OFF

OFF

D

BOM Structure Table

E

BTO ItemBOM Structure

@

0

WLAN

1

LAN

2

N/A

3

N/A

4

N/A

5

N/A

6

HDD

7

ODD

0
1
2
3

GPU

4

Device

ME@
EMC @
EMC_NS@
RF@
RF_PXNS@
UMA @
PX@
R17M-P1@
R18M-M2@
TPM @
KBL @
HDT @
REDRV@
USB_HUB@

Not stuff

Connect or

EMC Part

EMC reserve Part

RF Part

RF GPU reserve part

UMA SKU ID part

Discrete GPU SKU part

R17M-P1-50 SKU part

R18M-M2-60 SKU part

TPM part

Keyboard backlight part

HDT Debug part

Redriver part

USB HUB part

5
6
7
0

SMBUS Control Table

SOURCE

3 3

EC_SMB_ CK1

EC_SMB_ DA1

EC_SMB_ CK2

EC_SMB_ DA2

EC_SMB_ CK3

EC_SMB_ DA3

APU_SCL K0
APU_SDA TA0

IT8586

+3VL

IT8586

+3VL

IT8586

+3VS

APU

+3VS

EC SM Bus1 address

Device

4 4

Battery

Charger

Address

?

0001 0010 b

GPU BATT SODIMM WLAN Thermal

X

X

X X

X

X

X

+3VS_VG A

V

X

XV

V VX X X X X

EC SM Bus2 address

Device

PMIC

Thermal Sensor

Address

0X34

1001_10 0xb(reserv e)

Sensor

APUIT8586

Charger

X X V

X

V

+3VS

X

V X X

X

EC SM Bus3 address

Device

GPU

APU SB-TSI

PMIC

X

VX

X

Address

0x41(defaul t)

releate to F3x1E4[SbiAddr] or
Address Select Pins setting

APU SM Bus address

Device

DDR4 SO-DIMM

WLAN

Address

?

RSVD

A

B

USB3.0

USB2.0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

N/A

1

Type C

2

LEFT USB (3.0) lower

3

LEFT USB (3.0) upper

4

N/A

0

Card Reader

1

Type C

2

LEFT USB (3.0) lower

3

LEFT USB (3.0) upper

4

USB HUB(Camera,FP,Touch)

5

BT

LC Future Center Secret Data

LC Future Center Secret Data

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

VRAM

Deciphered Date

Deciphered Date

Deciphered Date

D

S2G @
M2G @
H2G @
HDMI@

2013/08/15

2013/08/15

2013/08/15

SAMSUNG 2G

MICRON 2G

HYNIX 2G

HDMI Logo

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330ARR

330ARR

330ARR

E

3 52

3 52

3 52

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

UC2B

PCIE_CRX_GTX_P017

D D

GPU

C C

WLAN

LAN

B B

HDD HDD

PCIE_CRX_GTX_N017

PCIE_CRX_GTX_P117
PCIE_CRX_GTX_N117

PCIE_CRX_GTX_P217
PCIE_CRX_GTX_N217

PCIE_CRX_GTX_P317
PCIE_CRX_GTX_N317

PCIE_CRX_GTX_P417
PCIE_CRX_GTX_N417

PCIE_CRX_GTX_P517
PCIE_CRX_GTX_N517

PCIE_CRX_GTX_P617
PCIE_CRX_GTX_N617

PCIE_CRX_GTX_P717
PCIE_CRX_GTX_N717

PCIE_PRX_DTX_P135
PCIE_PRX_DTX_N135

PCIE_PRX_DTX_P232
PCIE_PRX_DTX_N232

SATA_PRX_DTX_P038

SATA_PRX_DTX_N138

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2

SATA_PRX_DTX_P0
SATA_PRX_DTX_N0

SATA_PRX_DTX_P1
SATA_PRX_DTX_N1

P8

P_GFX_RXP0

P9

P_GFX_RXN0

N6

P_GFX_RXP1

N7

P_GFX_RXN1

M8

P_GFX_RXP2

M9

P_GFX_RXN2

L6

P_GFX_RXP3

L7

P_GFX_RXN3

K11

P_GFX_RXP4

J11

P_GFX_RXN4

H6

P_GFX_RXP5

H7

P_GFX_RXN5

G6

P_GFX_RXP6

F7

P_GFX_RXN6

G8

P_GFX_RXP7

F8

P_GFX_RXN7

N10

P_GPP_RXP0

N9

P_GPP_RXN0

L10

P_GPP_RXP1

L9

P_GPP_RXN1

L12

P_GPP_RXP2

M11

P_GPP_RXN2

P12

P_GPP_RXP3

P11

P_GPP_RXN3

V6

P_GPP_RXP4

V7

P_GPP_RXN4

T8

P_GPP_RXP5

T9

P_GPP_RXN5

R6

P_GPP_RXP6/SATA_RXP0

R7

P_GPP_RXN6/SATA_RXN0

R9

P_GPP_RXP7/SATA_RXP1

R10

P_GPP_RXN7/SATA_RXN1

@

PCIE

FP5 REV 0.90
PART 2 OF 13

P_GFX_TXP0
P_GFX_TXN0

P_GFX_TXP1
P_GFX_TXN1

P_GFX_TXP2
P_GFX_TXN2

P_GFX_TXP3
P_GFX_TXN3

P_GFX_TXP4
P_GFX_TXN4

P_GFX_TXP5
P_GFX_TXN5

P_GFX_TXP6
P_GFX_TXN6

P_GFX_TXP7
P_GFX_TXN7

P_GPP_TXP0
P_GPP_TXN0

P_GPP_TXP1
P_GPP_TXN1

P_GPP_TXP2
P_GPP_TXN2

P_GPP_TXP3
P_GPP_TXN3

P_GPP_TXP4
P_GPP_TXN4

P_GPP_TXP5
P_GPP_TXN5

P_GPP_TXP6/SATA_TXP0
P_GPP_TXN6/SATA_TXN0

P_GPP_TXP7/SATA_TXP1
P_GPP_TXN7/SATA_TXN1

AMD-RAVEN-FP5_BGA1140

PCIE_CTX_GRX_P0

N1

PCIE_CTX_GRX_N0

N3

PCIE_CTX_GRX_P1

M2

PCIE_CTX_GRX_N1

M4

PCIE_CTX_GRX_P2

L2

PCIE_CTX_GRX_N2

L4

PCIE_CTX_GRX_P3

L1

PCIE_CTX_GRX_N3

L3

PCIE_CTX_GRX_P4

K2

PCIE_CTX_GRX_N4

K4

PCIE_CTX_GRX_P5

J2

PCIE_CTX_GRX_N5

J4

PCIE_CTX_GRX_P6

H1

PCIE_CTX_GRX_N6

H3

PCIE_CTX_GRX_P7

H2

PCIE_CTX_GRX_N7

H4

PCIE_PTX_DRX_P1

N2

PCIE_PTX_DRX_N1

P3

PCIE_PTX_DRX_P2

P4

PCIE_PTX_DRX_N2

P2

R3
R1

T4
T2

W2
W4

W3
V2

SATA_PTX_DRX_P0

V1

SATA_PTX_DRX_N0

V3

SATA_PTX_DRX_P1

U2

SATA_PTX_DRX_N1

U4

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

SATA_PTX_DRX_P0 38

SATA_PTX_DRX_N0 38SATA_PRX_DTX_N038

SATA_PTX_DRX_P1 38SATA_PRX_D TX_P138
SATA_PTX_DRX_N1 38

CC50.22U_0201_6.3V6-K PX@
CC60.22U_0201_6.3V6-K PX@

CC70.22U_0201_6.3V6-K PX@
CC80.22U_0201_6.3V6-K PX@

CC90.22U_0201_6.3V6-K PX@
CC100.22U_0201_6.3V6-K PX@

CC110.22U_0201_6.3V6-K PX@
CC120.22U_0201_6.3V6-K PX@

CC180.22U_0201_6.3V6-K R5R7@
CC300.22U_0201_6.3V6-K R5R7@

CC310.22U_0201_6.3V6-K R5R7@
CC330.22U_0201_6.3V6-K R5R7@

CC320.22U_0201_6.3V6-K R5R7@
CC340.22U_0201_6.3V6-K R5R7@

CC350.22U_0201_6.3V6-K R5R7@
CC360.22U_0201_6.3V6-K R5R7@

CC10.1U_0201_6.3V6-K
CC20.1U_0201_6.3V6-K

CC30.1U_0201_6.3V6-K
CC40.1U_0201_6.3V6-K

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2

PCIE_CTX_C_GRX_P0 17
PCIE_CTX_C_GRX_N0 17

PCIE_CTX_C_GRX_P1 17
PCIE_CTX_C_GRX_N1 17

PCIE_CTX_C_GRX_P2 17
PCIE_CTX_C_GRX_N2 17

PCIE_CTX_C_GRX_P3 17
PCIE_CTX_C_GRX_N3 17

PCIE_CTX_C_GRX_P4 17
PCIE_CTX_C_GRX_N4 17

PCIE_CTX_C_GRX_P5 17
PCIE_CTX_C_GRX_N5 17

PCIE_CTX_C_GRX_P6 17
PCIE_CTX_C_GRX_N6 17

PCIE_CTX_C_GRX_P7 17
PCIE_CTX_C_GRX_N7 17

PCIE_PTX_C_DRX_P1 35
PCIE_PTX_C_DRX_N1 35

PCIE_PTX_C_DRX_P2 32
PCIE_PTX_C_DRX_N2 32

GPU

WLAN

LAN

ODDODD

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/15

2013/08/15

2013/08/15

2

Titl e

Titl e

Titl e

FP5 (PCIE SATA I/F)

FP5 (PCIE SATA I/F)

FP5 (PCIE SATA I/F)

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Dat e: Sheet o f

Dat e: Sheet o f

Dat e: Sheet o f

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

4 5 2

4 5 2

4 5 2

1.0

1.0

1.0

5

Vinafix.com

UC2A

D D

C C

B B

MEM_MA_RST#14

DDRA_MA[13..0]14

DDRA_MA14_WE#14
DDRA_MA15_CAS#14
DDRA_MA16_RAS#14

DDRA_BA014
DDRA_BA114

DDRA_BG014
DDRA_BG114

DDRA_ACT#14

DDRA_DM[7..0]14

DDRA_CLK014
DDRA_CLK0#14
DDRA_CLK114
DDRA_CLK1#14

DDRA_CS0#14
DDRA_CS1#14

DDRA_CKE014
DDRA_CKE114

DDRA_ODT014
DDRA_ODT114

DDRA_ALERT#14

MEM_MA_EVENT#14

1 2

RC283 0_0402_5%@

+1.2V

1 2

RC284 1K_0402_5%

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12

DDRA_MA13
DDRA_MA14_WE#
DDRA_MA15_CAS#
DDRA_MA16_RAS#

DDRA_BA0

DDRA_BA1

DDRA_BG0

DDRA_BG1

DDRA_ACT#

DDRA_DM0

DDRA_DM1

DDRA_DM2

DDRA_DM3

DDRA_DM4

DDRA_DM5

DDRA_DM6

DDRA_DM7

DDRA_DQS0

DDRA_DQS#0

DDRA_DQS1

DDRA_DQS#1

DDRA_DQS2

DDRA_DQS#2

DDRA_DQS3

DDRA_DQS#3

DDRA_DQS4

DDRA_DQS#4

DDRA_DQS5

DDRA_DQS#5

DDRA_DQS6

DDRA_DQS#6

DDRA_DQS7

DDRA_DQS#7

DDRA_CLK0

DDRA_CLK0#

DDRA_CLK1

DDRA_CLK1#

DDRA_CS0#

DDRA_CS1#

DDRA_CKE0

DDRA_CKE1

DDRA_ODT0

DDRA_ODT1

DDRA_ALERT#

MEM_MA_EVENT#

MEM_MA_RST#_R

MEM_MA_EVENT#

AF25

MA_ADD0/MAB_CS0

AE23

MA_ADD1/RSVD

AD27

MA_ADD2/RSVD

AE21

MA_ADD3/RSVD

AC24

MA_ADD4/RSVD

AC26

MA_ADD5/RSVD

AD21

MA_ADD6/RSVD

AC27

MA_ADD7/MAA_CA3

AD22

MA_ADD8/MAA_CA4

AC21

MA_ADD9/MAA_CKE1

AF22

MA_ADD10/MAB_CKE0

AA24

MA_ADD11/MAA_CA5

AC23

MA_ADD12/MAA_CA2

AJ25

MA_ADD13_BANK2/RSVD

AG27

MA_WE_L_ADD14/MAB_CA2

AG23

MA_CAS_L_ADD15/MAB_CA4

AG26

MA_RAS_L_ADD16/MAB_CA3

AF21

MA_BANK0/MAB_CS1

AF27

MA_BANK1/MAB_CA0

AA21

MA_BG0/MAA_CS1

AA27

MA_BG1/MAA_CKE0

AA22

MA_ACT_L/MAA_CS0

F21

MA_DM0/MAA_DM1

G27

MA_DM1/MAA_DM0

N24

MA_DM2/MAA_DM2

N23

MA_DM3/MAA_DM3

AL24

MA_DM4/MAB_DM2

AN27

MA_DM5/MAB_DM3

AW25

MA_DM6/MAB_DM1

AT21

MA_DM7/MAB_DM0

T27

RSVD_36

F22

MA_DQS_H0/MAA_DQS_H1

G22

MA_DQS_L0/MAA_DQS_L1

H27

MA_DQS_H1/MAA_DQS_H0

H26

MA_DQS_L1/MAA_DQS_L0

N27

MA_DQS_H2/MAA_DQS_H2

N26

MA_DQS_L2/MAA_DQS_L2

R21

MA_DQS_H3/MAA_DQS_H3

P21

MA_DQS_L3/MAA_DQS_L3

AM26

MA_DQS_H4/MAB_DQS_H2

AM27

MA_DQS_L4/MAB_DQS_L2

AN24

MA_DQS_H5/MAB_DQS_H3

AN25

MA_DQS_L5/MAB_DQS_L3

AU23

MA_DQS_H6/MAB_DQS_H1

AT23

MA_DQS_L6/MAB_DQS_L1

AV20

MA_DQS_H7/MAB_DQS_H0

AW20

MA_DQS_L7/MAB_DQS_L0

V24

RSVD_41

V23

RSVD_40

AD25

MA_CLK_H0/MAA_CKT

AD24

MA_CLK_L0/MAA_CKC

AE26

MA_CLK_H1/MAB_CKT

AE27

MA_CLK_L1/MAB_CKC

AG21

MA_CS_L0/MAB_CKE1

AJ27

MA_CS_L1/RSVD

Y23

MA_CKE0/MAA_CA0

Y26

MA_CKE1/MAA_CA1

AG24

MA_ODT0/MAB_CA5

AJ22

MA_ODT1/RSVD

AA25

MA_ALERT_L/MA_TEST

AE24

MA_EVENT_L

Y24

MA_RESET_L

@

SO-DIMM

FP5 REV 0.90
PART 1 OF 13

MEMORY A

MA_DATA0/MAA_DATA8

MA_DATA1/MAA_DATA9
MA_DATA2/MAA_DATA13
MA_DATA3/MAA_DATA12
MA_DATA4/MAA_DATA11
MA_DATA5/MAA_DATA10
MA_DATA6/MAA_DATA15
MA_DATA7/MAA_DATA14

MA_DATA8/MAA_DATA0

MA_DATA9/MAA_DATA1
MA_DATA10/MAA_DATA5
MA_DATA11/MAA_DATA4
MA_DATA12/MAA_DATA7
MA_DATA13/MAA_DATA6
MA_DATA14/MAA_DATA2
MA_DATA15/MAA_DATA3

MA_DATA16/MAA_DATA17
MA_DATA17/MAA_DATA16
MA_DATA18/MAA_DATA23
MA_DATA19/MAA_DATA20
MA_DATA20/MAA_DATA19
MA_DATA21/MAA_DATA18
MA_DATA22/MAA_DATA21
MA_DATA23/MAA_DATA22

MA_DATA24/MAA_DATA30
MA_DATA25/MAA_DATA31
MA_DATA26/MAA_DATA26
MA_DATA27/MAA_DATA27
MA_DATA28/MAA_DATA28
MA_DATA29/MAA_DATA29
MA_DATA30/MAA_DATA24
MA_DATA31/MAA_DATA25

MA_DATA32/MAB_DATA16
MA_DATA33/MAB_DATA17
MA_DATA34/MAB_DATA22
MA_DATA35/MAB_DATA20
MA_DATA36/MAB_DATA19
MA_DATA37/MAB_DATA18
MA_DATA38/MAB_DATA23
MA_DATA39/MAB_DATA21

MA_DATA40/MAB_DATA30
MA_DATA41/MAB_DATA31
MA_DATA42/MAB_DATA26
MA_DATA43/MAB_DATA27
MA_DATA44/MAB_DATA28
MA_DATA45/MAB_DATA29
MA_DATA46/MAB_DATA24
MA_DATA47/MAB_DATA25

MA_DATA48/MAB_DATA11
MA_DATA49/MAB_DATA10
MA_DATA50/MAB_DATA15
MA_DATA51/MAB_DATA14
MA_DATA52/MAB_DATA12
MA_DATA53/MAB_DATA13

MA_DATA54/MAB_DATA9
MA_DATA55/MAB_DATA8

MA_DATA56/MAB_DATA5
MA_DATA57/MAB_DATA6
MA_DATA58/MAB_DATA2
MA_DATA59/MAB_DATA3
MA_DATA60/MAB_DATA7
MA_DATA61/MAB_DATA4
MA_DATA62/MAB_DATA1
MA_DATA63/MAB_DATA0

MA_PAROUT/MAB_CA1

AMD-RAVEN-FP5_BGA1140

RSVD_34
RSVD_35
RSVD_51
RSVD_52
RSVD_27
RSVD_28
RSVD_43
RSVD_42

4

DDRA_DQS[0..7]

DDRA_DQS#[0..7]

DDRA_DQ[63..0] 14

APU

DA32

DA33

DA34

DA35

DA36

DA37

DA38

DA39

DA40

DA41

DA42

DA43

DA44

DA45

DA46

DA47

DA48

DA49

DA50

DA51

DA52

DA53

DA54

DA55

DA56

DA57

DA58

DA59

DA60

DA61

DA62

DA63

DDRA_PAR 14

SO-DIMM

DQ39

DQ36

DQ35

DQ34

DQ37

DQ32

DQ38

DQ33

DQ45

DQ44

DQ47

DQ46

DQ40

DQ41

DQ43

DQ42

DQ55

DQ49

DQ54

DQ48

DQ53

DQ52

DQ50

DQ51

DQ61

DQ56

DQ63

DQ58

DQ60

DQ57

DQ59

DQ62

DRAM

UD3.1

UD3.6

UD3.2

UD3.7

UD3.5

UD3.3

UD3.4

UD3.0

UD3.15

UD3.9

UD3.14

UD3.8

UD3.13

UD3.11

UD3.12

UD3.10

UD4.0

UD4.3

UD4.2

UD4.7

UD4.5

UD4.1

UD4.6

UD4.4

UD4.14

UD4.10

UD4.11

UD4.12

UD4.13

UD4.9

UD4.15

UD4.8

J21
H21
F23
H23
G20
F20
J22
J23

G25
F26
L24
L26
L23
F25
K25
K27

M25
M27
P27
R24
L27
M24
P24
P25

M22
N21
T22
V21
L21
M20
R23
T21

AL27
AL25
AP26
AR27
AK26
AK24
AM24
AP27

AM23
AM21
AR25
AU27
AL22
AL21
AP24
AP23

AW26
AV25
AV22
AW22
AU26
AV27
AW23
AT22

AW21
AU21
AP21
AN20
AR22
AN22
AT20
AR20

T24
T25
W25
W27
R26
R27
V27
V26

AF24

DDRA_DQS[0..7]14

DDRA_DQS#[0..7]14

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7

DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15

DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23

DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39

DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47

DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55

DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

DDRA_PAR

3

DDRB_MA[13..0]15

DDRB_MA14_WE#15
DDRB_MA15_CAS#15
DDRB_MA16_RAS#15

DDRB_BA015
DDRB_BA115

DDRB_BG015

TC213 @

DDRB_ACT#15

DDRB_DM[7..0]15

DDRB_CLK015
DDRB_CLK0#15

DDRB_CS0#15

DDRB_CKE015

DDRB_ODT015

DDRB_ALERT#15

1 2

+1.2V

RC240 0_0402_5%@

1 2

RC9 1K_0 402_5%DRAM@

MEM_MB_RST#15

1

MEM_MB_EVENT#

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12

DDRB_MA13
DDRB_MA14_WE#
DDRB_MA15_CAS#
DDRB_MA16_RAS#

DDRB_BA0

DDRB_BA1

DDRB_BG0

DDRB_BG1

DDRB_ACT#

DDRB_DM0

DDRB_DM1

DDRB_DM2

DDRB_DM3

DDRB_DM4

DDRB_DM5

DDRB_DM6

DDRB_DM7

DDRB_DQS0

DDRB_DQS#0

DDRB_DQS1

DDRB_DQS#1

DDRB_DQS2

DDRB_DQS#2

DDRB_DQS3

DDRB_DQS#3

DDRB_DQS4

DDRB_DQS#4

DDRB_DQS5

DDRB_DQS#5

DDRB_DQS6

DDRB_DQS#6

DDRB_DQS7

DDRB_DQS#7

DDRB_CLK0

DDRB_CLK0#

DDRB_CS0#

DDRB_CKE0

DDRB_ODT0

DDRB_ALERT#

MEM_MB_EVENT#

MEM_MB_RST#_R

2

UC2I

AG30

MB_ADD0/MBB_CS0

AC32

MB_ADD1/RSVD

AC30

MB_ADD2/RSVD

AB29

MB_ADD3/RSVD

AB31

MB_ADD4/RSVD

AA30

MB_ADD5/RSVD

AA29

MB_ADD6/RSVD

Y30

MB_ADD7/MBA_CA3

AA31

MB_ADD8/MBA_CA4

W29

MB_ADD9/MBA_CKE1

AH29

MB_ADD10/MBB_CKE0

Y32

MB_ADD11/MBA_CA5

W31

MB_ADD12/MBA_CA2

AL30

MB_ADD13_BANK2/RSVD

AK30

MB_WE_L_ADD14/MBB_CA2

AK32

MB_CAS_L_ADD15/MBB_CA4

AJ30

MB_RAS_L_ADD16/MBB_CA3

AH31

MB_BANK0/MBB_CS1

AG32

MB_BANK1/MBB_CA0

V31

MB_BG0/MBA_CS1

V29

MB_BG1/MBA_CKE0

V30

MB_ACT_L/MBA_CS0

C21

MB_DM0/MBA_DM1

C25

MB_DM1/MBA_DM0

E32

MB_DM2/MBA_DM2

K30

MB_DM3/MBA_DM3

AP30

MB_DM4/MBB_DM2

AW31

MB_DM5/MBB_DM3

BB26

MB_DM6/MBB_DM1

BD22

MB_DM7/MBB_DM0

N32

RSVD_21

D22

MB_DQS_H0/MBA_DQS_H1

B22

MB_DQS_L0/MBA_DQS_L1

D25

MB_DQS_H1/MBA_DQS_H0

B25

MB_DQS_L1/MBA_DQS_L0

F29

MB_DQS_H2/MBA_DQS_H2

F30

MB_DQS_L2/MBA_DQS_L2

K31

MB_DQS_H3/MBA_DQS_H3

K29

MB_DQS_L3/MBA_DQS_L3

AR29

MB_DQS_H4/MBB_DQS_H2

AR31

MB_DQS_L4/MBB_DQS_L2

AW30

MB_DQS_H5/MBB_DQS_H3

AW29

MB_DQS_L5/MBB_DQS_L3

BC25

MB_DQS_H6/MBB_DQS_H1

BA25

MB_DQS_L6/MBB_DQS_L1

BC22

MB_DQS_H7/MBB_DQS_H0

BA22

MB_DQS_L7/MBB_DQS_L0

N31

RSVD_20

N29

RSVD_18

AC31

MB_CLK_H0/MBA_CKT

AD30

MB_CLK_L0/MBA_CKC

AD29

MB_CLK_H1/MBB_CKT

AD31

MB_CLK_L1/MBB_CKC

AE30

RSVD_89

AE32

RSVD_90

AF29

RSVD_91

AF31

RSVD_92

AJ31

MB_CS_L0/MBB_CKE1

AM31

MB_CS_L1/RSVD

AJ29

RSVD_95

AM29

RSVD_97

U29

MB_CKE0/MBA_CA0

T30

MB_CKE1/MBA_CA1

V32

RSVD_93

U31

RSVD_94

AL31

MB_ODT0/MBB_CA5

AM32

MB_ODT1/RSVD

AL29

RSVD_96

AM30

RSVD_98

W30

MB_ALERT_L/MB_TEST

AG29

MB_EVENT_L

T31

MB_RESET_L

@

Memory down

FP5 REV 0.90
PART 9 OF 13

MEMORY B

MB_DATA0/MBA_DATA8

MB_DATA1/MBA_DATA9
MB_DATA2/MBA_DATA13
MB_DATA3/MBA_DATA12
MB_DATA4/MBA_DATA11
MB_DATA5/MBA_DATA10
MB_DATA6/MBA_DATA15
MB_DATA7/MBA_DATA14

MB_DATA8/MBA_DATA0

MB_DATA9/MBA_DATA1
MB_DATA10/MBA_DATA5
MB_DATA11/MBA_DATA4
MB_DATA12/MBA_DATA7
MB_DATA13/MBA_DATA6
MB_DATA14/MBA_DATA2
MB_DATA15/MBA_DATA3

MB_DATA16/MBA_DATA19
MB_DATA17/MBA_DATA18
MB_DATA18/MBA_DATA22
MB_DATA19/MBA_DATA23
MB_DATA20/MBA_DATA20
MB_DATA21/MBA_DATA21
MB_DATA22/MBA_DATA17
MB_DATA23/MBA_DATA16

MB_DATA24/MBA_DATA30
MB_DATA25/MBA_DATA31
MB_DATA26/MBA_DATA26
MB_DATA27/MBA_DATA27
MB_DATA28/MBA_DATA28
MB_DATA29/MBA_DATA29
MB_DATA30/MBA_DATA25
MB_DATA31/MBA_DATA24

MB_DATA32/MBB_DATA16
MB_DATA33/MBB_DATA17
MB_DATA34/MBB_DATA21
MB_DATA35/MBB_DATA20
MB_DATA36/MBB_DATA19
MB_DATA37/MBB_DATA18
MB_DATA38/MBB_DATA23
MB_DATA39/MBB_DATA22

MB_DATA40/MBB_DATA24
MB_DATA41/MBB_DATA25
MB_DATA42/MBB_DATA29
MB_DATA43/MBB_DATA28
MB_DATA44/MBB_DATA31
MB_DATA45/MBB_DATA30
MB_DATA46/MBB_DATA26
MB_DATA47/MBB_DATA27

MB_DATA48/MBB_DATA11
MB_DATA49/MBB_DATA10
MB_DATA50/MBB_DATA14
MB_DATA51/MBB_DATA15
MB_DATA52/MBB_DATA12
MB_DATA53/MBB_DATA13

MB_DATA54/MBB_DATA9
MB_DATA55/MBB_DATA8

MB_DATA56/MBB_DATA6
MB_DATA57/MBB_DATA7
MB_DATA58/MBB_DATA2
MB_DATA59/MBB_DATA3
MB_DATA60/MBB_DATA4
MB_DATA61/MBB_DATA5
MB_DATA62/MBB_DATA1
MB_DATA63/MBB_DATA0

MB_PAROUT/MBB_CA1

AMD-RAVEN-FP5_BGA1140

1

DDRB_DQS[0..7]15

DDRB_DQS#[0..7]15

DQ bi t swapp ing is allowed in a b yte lane.

DDRB_DQ[63..0] 15

APU

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DA8

DA9

DA10

DA11

DA12

DA13

DA14

DA15

DA16

DA17

DA18

DA19

DA20

DA21

DA22

DA23

DA24

DA25

DA26

DA27

DA28

DA29

DA30

DA31

DDRB_PAR 15

SO-DIMM

DQ2 UD1.0

DQ7

DQ6

DQ0

DQ1

DQ5

DQ4

DQ3

DQ12

DQ13

DQ11

DQ10

DQ9

DQ8

DQ15

DQ14

DQ20

DQ16

DQ19

DQ18

DQ17

DQ21

DQ22

DQ23

DQ24

DQ28

DQ30

DQ26

DQ25

DQ29

DQ27

DQ31

RSVD_17
RSVD_19
RSVD_26
RSVD_29
RSVD_16
RSVD_15
RSVD_25
RSVD_24

B21
D21
B23
D23
A20
C20
A22
C22

D24
A25
D27
C27
C23
B24
C26
B27

C30
E29
H29
H31
A28
D28
F31
G30

J29
J31
L29
L31
H30
H32
L30
L32

AP29
AP32
AT29
AU32
AN30
AP31
AR30
AT31

AU29
AV30
BB30
BA28
AU30
AU31
AY32
AY29

BA27
BC27
BA24
BC24
BD28
BB27
BB25
BD25

BC23
BB22
BC21
BD20
BB23
BA23
BB21
BA21

M31
N30
P31
R32
M30
M29
P30
P29

AG31

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7

DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15

DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23

DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31

DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39

DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47

DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55

DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

DDRB_PAR

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

DRAM

UD1.3

UD1.4

UD1.5

UD1.2

UD1.7

UD1.1

UD1.6

UD1.11

UD1.9

UD1.12

UD1.14

UD1.13

UD1.15

UD1.8

UD1.10

UD2.7

UD2.3

UD2.4

UD2.1

UD2.0

UD2.2

UD2.6

UD2.5

UD2.9

UD2.11

UD2.12

UD2.8

UD2.13

UD2.15

UD2.14

UD2.10

A A

Titl e

Titl e

Titl e

FP5 (MEM)

FP5 (MEM)

FP5 (MEM)

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

330ARR

330ARR

330ARR

5 52

5 52

5 52

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE P ROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET M AY NOT BE TRANS FERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CEN TER NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER .

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

2

G

2

G

2

G

+3VALW_APU

+3VALW_APU

+3VALW_APU

+3VS_APU

+3VS_APU

RC71
10K_0402_5%

1 2

5

G

61

D

QC8A
DMN5L06DWK-7 2N SOT363-6

S

1 2

RC205 0_0402_5%@

+3VS_APU

RC73
10K_0402_5%

@

1 2

5

G

61

D

QC9A
DMN5L06DWK-7 2N SOT363-6

@

S

1 2

RC206 0_0402_5%@

+3VS_APU

RC75
10K_0402_5%

@

1 2

5

G

61

D

QC10A
DMN5L06DWK-7 2N SOT363-6

S

@

1 2

RC207 0_0402_5%@

2013/08/15

2013/08/15

2013/08/15

+1.8VS

RC2

39.2_0402_1%

@

1 2

APU_TEST31

APU_TEST31

M_TEST CONNECTION TBD

RC3131

39.2_0402_1%

@

1 2

12

RC70

4.7K_0402_5%

34

D

QC8B
DMN5L06DWK-7 2N SOT363-6

S

12

RC74

4.7K_0402_5%

@

34

D

QC9B
DMN5L06DWK-7 2N SOT363-6

@

S

RC77

2.2K_0402_5%

@

1 2

34

D

QC10B
DMN5L06DWK-7 2N SOT363-6

S

@

Title

Title

Title

FP5 (DP/JTAG/SIV2/MISC)

FP5 (DP/JTAG/SIV2/MISC)

FP5 (DP/JTAG/SIV2/MISC)

Size

Size

Size

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

PCH_ENBKL 26

Document Number R ev

Document Number R ev

Document Number R ev

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

+1.8VS

RC3101
1K_0402_5%

1 2

DP_STEREOSYNC

RC3102
1K_0402_5%

@

1 2

PCH_EDP_PWM 26

PCH_ENVDD 26

330ARR

330ARR

330ARR

1

6 52

6 52

6 52

APU_EDP_TX0+26

+1.8VS

12

RC18

D D

C C

B B

300_0402_5%

APU_RST#

PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC16
56P_0201_50V8-J

2

@

+1.8VS

12

RC19
300_0402_5%

APU_PWROK

PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf

1

CC17
56P_0201_50V8-J

2

@

+3VS_APU

RPC8

1 4
2 3

1K_0404_4P2R_5%

RPC51

1 4
2 3

1K_0404_4P2R_5%

+3VS_APU

1 2

RC22 1K_0402_1%

1 2

CC1393 0.1U_0201_6.3V6-K

1 2

CC1394 0.1U_0201_6.3V6-K

APU_SIC
APU_SID

APU_PROCHOT#_R

ALERT#

APU_THERMTRIP#

@

@

APU_THERMTRIP#

APU_PROCHOT#_R

eDP

HDMI

EC_SMB_CK318,39
EC_SMB_DA318,39

APU_THERMTRIP#39

H_PROCHOT#39,49

APU_SVC52
APU_SVD52
APU_SVT52

1

2

@

APU_EDP_TX0-26

APU_EDP_TX1+26
APU_EDP_TX1-26 APU_EDP_AUX 26

APU_HDMI_TX2+27
APU_HDMI_TX2-27

APU_HDMI_TX1+27
APU_HDMI_TX1-27

APU_HDMI_TX0+27
APU_HDMI_TX0-27

APU_HDMI_CLK+27
APU_HDMI_CLK-27

APU_PWROK52

1 2

RC3129 0_0402_5%@

1 2

RC3130 0_0402_5%@

1 2

RC31 0_0402_5%@

1 2

RC213 0_0402_5%@

1 2

RC215 0_0402_5%@

1 2

RC279 0_0402_5%@

APU_SVC APU_SVD

CC1281
1000P_0201_50V7-K

1

CC1283
1000P_0201_50V7-K

2

@

APU_EDP_TX0+
APU_EDP_TX0-

APU_EDP_TX1+
APU_EDP_TX1-

APU_HDMI_TX2+
APU_HDMI_TX2-

APU_HDMI_TX1+
APU_HDMI_TX1-

APU_HDMI_TX0+
APU_HDMI_TX0-

APU_HDMI_CLK+
APU_HDMI_CLK-

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#

APU_RST#
APU_PWROK

APU_SIC
APU_SID

ALERT#
APU_THERMTRIP#

APU_PROCHOT#_R

APU_SVC_RA
APU_SVD_RA
APU_SVT_RA

APU_SVT

1

CC214
1000P_0201_50V7-K

2

@

AU2
AU4
AU1
AU3
AV3

AW3

AW4
AW2

H14

AP16

L19

F16
H16

C8
A8

D8
B8

B6
C7

C6
D6

E6
D5

E1
C1

F3
E4

F4
F2

J14
J15

J16

DP0_TXP0
DP0_TXN0

DP0_TXP1
DP0_TXN1

DP0_TXP2
DP0_TXN2

DP0_TXP3
DP0_TXN3

DP1_TXP0
DP1_TXN0

DP1_TXP1
DP1_TXN1

DP1_TXP2
DP1_TXN2

DP1_TXP3
DP1_TXN3

TDI
TDO
TCK
TMS
TRST_L
DBREQ_L

RESET_L
PWROK

SIC
SID
ALERT_L
THERMTRIP_L
PROCHOT_L

SVC0
SVD0
SVT0

@

DISPLAY/SVI2/JTAG/TEST

DP_STEREOSYNC

TEST31/RSVD

VDDP_SENSE

VDDCR_SOC_SENSE

VDDCR_SENSE

VSS_SENSE_A

FP5 REV 0.90

VSS_SENSE_B

PART 3 OF 13

AMD-RAVEN-FP5_BGA1140

DP_BLON

DP_DIGON

DP_VARY_BL

DP0_AUXP
DP0_AUXN

DP0_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP2_AUXP
DP2_AUXN

DP2_HPD

DP3_AUXP
DP3_AUXN

DP3_HPD

RSVD_4
RSVD_3

RSVD_2

TEST4
TEST5

TEST6

TEST14
TEST15
TEST16
TEST17

TEST41

TEST470
TEST471

SMU_ZVDD

CORETYPE

DP_ENBKL

G15

DP_ENVDD

F15

DP_EDP_PWM

L14

APU_EDP_AUX

D9

APU_EDP_AUX#

B9

APU_EDP_HPD

C10

APU_DDC_CLK

G11

APU_DDC_DATA

F11

APU_HDMI_HPD

G13

J12
H12
K13

J10
H10
K8

DP_STEREOSYNC

K15

F14
F12

F10

AP14

TEST4

AN14

TEST5

F13

APU_TEST14

G18

APU_TEST15

APU_TEST15

H19

APU_TEST16

F18

APU_TEST17

APU_TEST17

F19

APU_TEST31

W24

AR11

AJ21

TEST470

AK21

TEST471

SMU_ZVDDP

V4

AW11

CORETYPE

APU_VDDP_RUN_FB_H

AN11

VDDCR_SOC_VCC_SENSE

J19

VDDCR_VCC_SENSE

K18

VDDCR_VSS_SENSE

J18

VSS_SENSEB

AM11

+1.8VS

1 2

eDP

HDMI

12

VDDCR_SOC_VCC_SENSE
VDDCR_VCC_SENSE
VDDCR_VSS_SENSE

+0.9VS

+3VALW_APU

APU_EDP_AUX# 26
APU_EDP_HPD 26

APU_DDC_CLK 27
APU_DDC_DATA 27
APU_HDMI_HPD 27

1

TC34@

1

TC33@

1

TC32@

1

TC204@

1

TC205@

1

TC206@

RPC47

4 5
3 6
2 7
1 8

1

TC24@

10K_0804_8P4R_5%

1

1
1

@

TC23@

TC22@
TC21@

RC3 196_0402_1%

RC3113 1K_0402_5%@

1

TC35@

1

TC40@

UC2C

APU_DDC_CLK
APU_DDC_DATA

APU_EDP_HPD

VDDCR_SOC_VCC_SENSE 52
VDDCR_VCC_SENSE 52

VDDCR_VSS_SENSE 52

1
1
1

TC52@
TC207@
TC208@

With HDT+ Header

+1.8VALW

RC7
1K_0402_5%

1 2

APU_TRST#

A A

2

CC84

0.01U_0201_10V6K

1

1 2

RC76 33_0402_5%HDT@

1 8

2 7

RPC17
10K_0804_8P4R_5%

HDT@

3 6

4 5

APU_TRST#_R

JHDT1

@

1

1

3

3

5

5

7

7

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

SAMTE_ASP-136446-07-B

2

2

4

4

6

6

8

8

10

12

14

16

18

20

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWROK_BUF

APU_RST#_BUF

APU_DBRDY

1 2

RC273 33_0402_5%HDT@

APU_PLLTEST0

APU_PLLTEST1

APU_DBRDY 12

APU_DBREQ#

APU_PLLTEST0 12

APU_PLLTEST1 12

RPC5

1K_0804_8P4R_5%

2

CC213

0.01U_0201_10V6K

1

HDT@

+1.8VALW+1.8VALW

18
27
36
45

APU_PWROK

APU_RST#

APU_TDIAPU_DBREQ#

2

CC212

0.01U_0201_10V6K

1

@

CC25

0.1U_0201_6.3V6-K

HDT@

UC6

3

2A

2

GND

1

1A

5

4

3

+1.8VALW+1.8VALW

1

2

4

2Y

5

VCC

6

1Y

SN74LVC2G07YZPR_WCSP6HDT@

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

12

RC32
300_0402_5%

HDT@

12

RC36
300_0402_5%

HDT@

APU_PWROK_BUF

APU_RST#_BUF

2013/08/15

2013/08/15

2013/08/15

RPC18

1 4
2 3

2.2K_0404_4P2R_5%

1 2

RC35 100K_0402_5%

To EDP panel

PU FOR INTERNAL

PD FOR CUSTOMER

DP_EDP_PWM

12

RC11
100K_0402_5%

DP_ENVDD

12

RC13
100K_0402_5%

@

LCD Power IC can change for PCH_ENVDD for cost down

DP_ENBKL

12

RC14
100K_0402_5%

@

Deciphered Date

Deciphered Date

Deciphered Date

2

1.0

1.0

1.0

5

Vinafix.com

RC243 0_04 02_5%@

EC_RSMRST#39

D D

1 2

PLT_RST#17,32, 35

C C

Board_ID0

Board_ID1

Board_ID2

Board_ID
[3,4]

Description

0

1

0

1

000NONEC

1

01

10

11

+1.8VS

12

RC3234
2K_0402 _5%

@

0

1

0

1

+1.8VALW

B B

Board_ID5

Board_ID6

RC3202 33_0402 _5%

12

RC3201
100K_04 02_5%

@

R17

R18

Discrete GPU

UMA

NEC

Hynix 8Gb

Micron 8Gb

DIMM_ONLY

Samsung 8Gb

NON-TS

TS

Reserved

Reserved

+3VALW _APU

12

RC3231
2K_0402 _5%

R18@

12

1

CC1389
100P_02 01_25V8J

2

RC1609 RC1607

RC1609 RC1608

RC1615
2K_0402 _5%

@

Stuff RBoard ID

RC1616

RC3234

RC1614

RC1613

RC1612

RC1611

RC1607RC1610

RC1608RC1610

RC123

RC1606

RC3224

RC3225

PCIE_RST0#_R

RB751V-4 0_SOD323-2 @

PBTN_OUT#39

SYS_RESE T#13

PM_SLP_ S3#39
PM_SLP_ S5#13,39

AC_PRESE NT39

+3VS_AP U

DC1

1 2

4

12

+3VALW _APU

HDA_SDIN036

+1.8VALW

12

RC3198
10K_040 2_5%

RSMRST#_R

1

CC1316

0.1U_020 1_6.3V6-K

2

RC191 0_04 02_5%@

PM_SLP_ S3#

RC193 0_04 02_5%@

PM_SLP_ S5#

RC194 0_04 02_5%@

RC100 10K _0402_5%

RC201 0_04 02_5%@

1 2

1 2
1 2

1 2

1 2

+3VALW _APU

TC42 @
TC210 @

1

2

1
1

CC8783
10U_040 2_6.3V6M

EC_SYS_P WRGD39

PCIE_RST0# _R

PCIE_RST1#_R

RSMRST#_R

PWRBTN#_ RP BTN_OUT#
SYS_PW RGD_R
SYS_RESE T#
PCIE_W AKE#_RA

PM_SLP_ S3#_R
PM_SLP_ S5#_R

AC_PRESE NT

BATLOW#

HDA_BITCLK
HDA_SDIN0 _R
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT

BOARD_ID0

HDA_RST_AUD IO#36

HDA_SYNC_A UDIO36
HDA_BITCLK_ AUDIO36
HDA_SDOUT_ AUDIO36

3

1 2

RC3065 0_040 2_5%@

UC2D

BD5

PCIE_RST0_L/EGPIO26

BB6

PCIE_RST1_L/EGPIO27

AT16

RSMRST_L

AR15

PWR_BTN_L/AGPIO0

AV6

PWR_GOOD

AP10

SYS_RESET_L/AGPIO1

AV11

WAKE_L/AGPIO2

AV13

SLP_S3_L

AT14

SLP_S5_L

AR8

S0A3_GPIO/AGPIO10

AT10

AC_PRES/AGPIO23

AN6

LLB_L/AGPIO12

AW8

EGPIO42

AR2

AZ_BITCLK/TDM_BCLK_MIC

AP7

AZ_SDIN0/CODEC_GPI

AP1

AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK

AP4

AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK

AP3

AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC

AR4

AZ_SYNC/TDM_FRM_MIC

AR3

AZ_SDOUT/TDM_FRM_PLAYBACK

AT2

SW_MCLK/TDM_BCLK_BT

AT4

SW_DATA0/TDM_DOUT_BT

AR6

AGPIO7/FCH_ACP_I2S_SDIN_BT

AP6

AGPIO8/FCH_ACP_I2S_LRCLK_BT

@

ACPI/AUDIO/I2C/GPIO/MIS C

RPC4

1 8
2 7
3 6
4 5

33_0804 _8P4R_5%

+3VALW _APU

12

RC3199
10K_040 2_5%

@

SYS_PW RGD_R

1

CC1314

0.1U_020 1_6.3V6-K

2

EGPIO41/SFI_S5_EGPIO41
AGPIO39/SFI_S5_AGPIO39

I2C0_SCL/SFI0_I2C_SCL/EGPIO151

I2C0_SDA/SFI0_I2C_SDA/EGPIO152

I2C1_SCL/SFI1_I2C_SCL/EGPIO149

I2C1_SDA/SFI1_I2C_SDA/EGPIO150

I2C2_SCL/EGPIO113/SCL0

I2C2_SDA/EGPIO114/SDA0

I2C3_SCL/AGPIO19/SCL1
I2C3_SDA/AGPIO20/SDA1

AGPIO4/SATAE_IFDET

SATA_ACT_L/AGPIO130

FP5 REV 0.90

PART 4 OF 13

AMD-RAVEN-F P5_BGA114 0

RC260

1 2

1K_0402_5%

@

PSA_I2C_SCL

PSA_I2C_SDA

AGPIO3

AGPIO5/DEVSLP0
AGPIO6/DEVSLP1

AGPIO9
AGPIO40
AGPIO69
AGPIO86

INTRUDER_ALERT

SPKR/AGPIO91
BLINK/AGPIO11

GENINT1_L/AGPIO89
GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

RC262

RC261

1 2

1 2

1K_0402_5%

@

@

AW12
AU12

AR13
AT13

AN8
AN9

BC20
BA20

AM9
AM10

L16
M16

AT15
AW10

AP9
AU10
AV15

AU7
AU6
AW13
AW15

AU14
AU16
AV8

AW16
BD15

AR18
AT18

HDA_RST#
HDA_SYNC
HDA_BITCLK
HDA_SDOUT

1K_0402_5%

2

SYS_RESE T#

EGPIO15 1
EGPIO15 2

EGPIO14 9
EGPIO15 0

I2C2_SCL _APU
I2C2_SDA _APU

TP_I2C0_S CL_R
TP_I2C0_S DA_R

PSA_I2C_ SCL
PSA_I2C_ SDA

BOARD_ID2

AGPIO5

BOARD_ID6
PXS_PW REN_R1
BOARD_ID3

INTRUDER_AL ERT

BLINK

PCH_TP_INT#

RB751V-4 0_SOD323-2

1

CC38

0.1U_020 1_6.3V6-K

2

RC501 0_04 02_5%@
RC500 0_04 02_5%@

CRB connect to EC and PMIC

RC3240 0_040 2_5%PX@

EC_SMI# 39

RC3100 20M_0402_5%@

SUSP14,27,41

1 2

1 2
1 2

2

G

DC4

SYS_PW RGD_R

@

TP_I2C0_S CL_R 13 ,40
TP_I2C0_S DA_R 13 ,40

USBDEBUG 28

12

12

PCH_BEEP 36

PCH_TP_INT# 40

PXS_PW REN

RC3244
1K_0402 _5%

PX@

1 2

13

D

QC11
2N7002K W_SOT323-3

PX@

S

PCIE_W AKE#_RA

AGPIO5

APU_SMB_ CLK 14,35
APU_SMB_ DATA 14,35

Touch Pad

PXS_PW REN 8 ,50,51

VCCRTC

1 2

RC88 0_0402_ 5%@

2 1

EGPIO14 9
EGPIO15 0
EGPIO15 1
EGPIO15 2

12

DC3

@

RC92 0 _0402_5%@

SDM10U45 LP-7_DFN1006 -2-2

SO-DIMM,Mini Card

PSA_I2C_ SCL

RC3126 4.7K_0402_5%@

PSA_I2C_ SDA

RC3127 4.7K _0402_5%@

I2C2_SCL _APU
I2C2_SDA _APU

EC_SMI#
PCH_TP_INT#

TP_I2C0_S CL_R
TP_I2C0_S DA_R

PBTN_OUT#
PCIE_W AKE#_RA
AC_PRESE NT

Blink
PM_SLP_ S3#

PM_SLP_ S5#
PXS_PW REN_R1

PCH_TP_INT#
RSMRST#_R
SYS_PW RGD_R

PCIE_RST1# _R
PXS_PW REN_R1

RC3081 2.2K _0402_5%
RC3213 10K_0402_5%

RC3119 10K _0402_5%@
RC203 2.2K_0 402_5%@
RC208 2.2K_0 402_5%@
RC3241 10K _0402_5%PX @

RC248 10K _0402_5%@
RC87 100K_04 02_5%
RC89 100K_04 02_5%

RC3227 10K _0402_5%
RC3242 10K _0402_5%@

1

RPC55

1 8
2 7
3 6
4 5

10K_080 4_8P4R_5%

12
12

RPC21

23
14

2.2K_04 04_4P2R_5 %

1 2
1 2

RPC56

23
14

2.2K_04 04_4P2R_5 %

RPC15

1 8
2 7
3 6
4 5

10K_080 4_8P4R_5%

1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2

PCIE_W AKE# 32,35 ,39

+1.8VS

+3VS_AP U

+3VALW _APU

+3VALW _APU

12

RC1613
2K_0402 _5%

UMA@

BOARD_ID0

BOARD_ID19

A A

BOARD_ID49
BOARD_ID59

BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6

RC1616
10K_040 2_5%

R17@

1 2

RC1614
10K_040 2_5%

PX@

1 2

RC1611
10K_040 2_5%

NEC@

1 2

12

RC1612
2K_0402 _5%

NONEC@

5

12

RC1609
2K_0402 _5%

@

RC1610
10K_040 2_5%

@

1 2

1 2

1 2

4

RC1608
10K_040 2_5%

@

RC1607
10K_040 2_5%

@

RC1606
10K_040 2_5%

TS@

1 2

12

RC123
2K_0402 _5%

NOTS@

RC3225
10K_040 2_5%

@

1 2

RC3224
10K_040 2_5%

@

1 2

Titl e

Titl e

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Titl e

FP5 AZ/I2C/ACPI/GPIO

FP5 AZ/I2C/ACPI/GPIO

FP5 AZ/I2C/ACPI/GPIO

Size Document Num ber Re v

Size Document Num ber Re v

Size Document Num ber Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

7 52

7 52

7 52

1.0

1.0

1.0

5

Vinafix.com

D D

+3VS_AP U

+3VS_AP U

C C

1 2

RC3161 10K _0402_5%

1 2

RC3162 10K _0402_5%

1 2

RC3163 10K _0402_5%

1 2

RC3164 10K _0402_5%

1 2

RC3217 10K _0402_5%UMA @

1 2

12
12

RC10 150_040 2_1%@
RC6 150_040 2_1%@

RC3223 2K_ 0402_5%PX@

PCH_WL AN_OFF#
LAN_CLKR EQ#
WLAN_C LKREQ#
PCH_BT_OFF#
GPU_CLKR EQ#

XGBECLK 0
XGBECLK 1

GPU_CLKR EQ#

PCIE CL K1

WLAN

PCIE CL K2 LAN

PXS_PW REN7,50,51

CLK_PCIE _WLAN35

CLK_PCIE _WLAN#35

CLK_PCIE _LAN3 2

CLK_PCIE _LAN#3 2

CLK_PCIE _GPU1 7

CLK_PCIE _GPU#17

48MHz/10pF Crystal

1 2

B B

RC3204 1M_04 02_5%

YC1

1

OSC1

NC12OSC2

1

48MHZ_10 PF_7V4800 0017
CC1390
8P_0402 _50V8-B

2

NC2

4

WLAN_C LKREQ#35
LAN_CLKR EQ#32

PCH_BT_OFF#35

PCH_WL AN_OFF#35

12

RC119 0_04 02_5%@
RC120 0_04 02_5%@

RC121 0_04 02_5%@
RC122 0_04 02_5%@

RC117 0_04 02_5%@
RC118 0_04 02_5%@

CC21

10P_040 2_50V8J

RC1090_0402_ 5% @

1 2
1 2

1 2
1 2

1 2
1 2

SUSCLK35

GPU_CLKR EQ#18

CLK_PCIE _WLAN#

CLK_PCIE _LAN# CLK_PCIE_LAN#_ R

X48M_X1

X48M_X2

Kevin H: change YC2 PN change to SJ10000MQ00,manual modify PN to SJ10000MQ00

4

3

1

CC1391
8P_0402 _50V8-B

2

WLAN_C LKREQ#
LAN_CLKR EQ#
PCH_BT_OFF#
PCH_WL AN_OFF#
PXS_PW REN_R
GPU_CLKR EQ#

CLK_PCIE _WLAN_RCLK_PCIE _WLAN
CLK_PCIE _WLAN#_R

CLK_PCIE _LAN_RCLK_PCIE _LAN

CLK_PCIE _GPU_RCLK_PCIE _GPU
CLK_PCIE _GPU#_RCL K_PCIE_GP U#

48M_OSC

1

TC41 @

X48M_X1

X48M_X2

XGBECLK 0
XGBECLK 1

RC45

1 2

20M_040 2_5%

YC3

1 2

32.768K HZ_12.5PF_2 02740-PG1 4

1

2

X32K_X1

X32K_X2

1

CC22
12P_040 2_50V8-J

2

3

APU_LPC_ RST#13,34,39

CLK/LPC/EMMC/SD /SPI/e SPI/UAR T

AV18

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

AN19

CLK_REQ1_L/AGPIO115

AP19

CLK_REQ2_L/AGPIO116

AT19

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

AU19

CLK_REQ4_L/OSCIN/EGPIO132

AW18

CLK_REQ5_L/EGPIO120

AW19

CLK_REQ6_L/EGPIO121

AK1

GPP_CLK0P

AK3

GPP_CLK0N

AM2

GPP_CLK1P

AM4

GPP_CLK1N

AM1

GPP_CLK2P

AM3

GPP_CLK2N

AL2

GPP_CLK3P

AL4

GPP_CLK3N

AN2

GPP_CLK4P

AN4

GPP_CLK4N

AN3

GPP_CLK5P

AP2

GPP_CLK5N

AJ2

GPP_CLK6P

AJ4

GPP_CLK6N

AJ3

X48M_OSC

BB3

X48M_X1

BA5

X48M_X2

AF8

RSVD_76

AF9

RSVD_77

AW14

RTCCLK

AY1

X32K_X1

AY4

X32K_X2

@

PCH_SPI_ CS0#
PCH_SPI_ D1
PCH_SPI_ D2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

+1.8V_SP I

RC3235 10K _0402_5%
RC3236 10K _0402_5%
RC3237 10K _0402_5%@
RC3238 10K _0402_5%@

LPC_PD_L/SD_CMD/AGPIO21

LAD0/SD_DATA0/EGPIO104
LAD1/SD_DATA1/EGPIO105
LAD2/SD_DATA2/EGPIO106
LAD3/SD_DATA3/EGPIO107

LPC_CLKRUN_L/AGPIO88

LPC_RST_L/SD_WP_L/AGPIO32

LPC_PME_L/SD_PWR_CTRL/AGPIO22

SPI_ROM_REQ/EGPIO67
SPI_ROM_GNT/AGPIO76

ESPI_RESET_L/KBRST_L/AGPIO129
ESPI_ALERT_L/LDRQ0_L/EGPIO108

SPI_HOLD_L/ESPI_DAT3

SPI_CS2_L/ESPI_CS_L/AGPIO30

SPI_TPM_CS_L/AGPIO29

UART0_RTS_L/UART2_RXD/EGPIO137
UART0_CTS_L/UART2_TXD/EGPIO135

EGPIO142/UART1_RTS_L/UART3_RXD
EGPIO140/UART1_CTS_L/UART3_TXD

FP5 REV 0.90

PART 5 OF 13

AMD-RAVEN-F P5_BGA114 0

UC3

/HOLDor/RESET(IO3)

W25Q6 4FWSSIQ_ SO8

8MB(64Mb)

1 2
1 2
1 2
1 2

1 2

RC46 33_04 02_5%

1

CC1318
150P_04 02_50V8-J

2

UC2E

8
7
6
5

PCH_SPI_ CS0#
PCH_SPI_ D1
PCH_SPI_ D2
PCH_SPI_ D3

BD13
BB14
BB12
BC11
BB15
BC15
BA15
BC13
BB13
BC12
BA12

BD11
BA11
BA13

BC8
BB8

BB11
BC6

BB7
BA9
BB10
BA10
BC10
BC9
BA8
BA6
BD8

BA16
BB18
BC17
BA18
BD18

BC18
BA17
BC16
BB19
BB16

+1.8V_SP I
PCH_SPI_ D3
PCH_SPI_ CLK
PCH_SPI_ D0

EGPIO70/SD_CLK

LPCCLK0/EGPIO74

LPCCLK1/EGPIO75

SERIRQ/AGPIO87

LFRAME_L/EGPIO109

AGPIO68/SD_CD

SPI_CLK/ESPI_CLK
SPI_DI/ESPI_DAT1

SPI_DO/ESPI_DAT0

SPI_WP_L/ESPI_DAT2

SPI_CS1_L/EGPIO118

SPI_CS3_L/AGPIO31

UART0_RXD/EGPIO136
UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

EGPIO141/UART1_RXD
EGPIO143/UART1_TXD

AGPIO144/UART1_INTR

VCC

CLK

DI(IO0)

LPC_RST#_R

EGPIO70
LPCPD#
LAD0

RC3208 10_ 0402_5%

LAD1

RC3209 10_ 0402_5%

LAD2

RC3210 10_ 0402_5%

LAD3

RC3211 10_ 0402_5%

LPCCLK0

EGPIO75

LPC_RST#_R

KBRST#

RC3141 0_040 2_5%@

SPI_CLK

RC3083 10_ 0402_5%

SPI_D1

RC3084 0_040 2_5%@

SPI_D0

RC3085 0_040 2_5%@

SPI_D2

RC3087 0_040 2_5%@

SPI_D3

RC3088 0_040 2_5%@

SPI_CS0#

RC3089 0_040 2_5%@

AGPIO30

APU_UART0_ RXD
APU_UART0_ TXD
APU_UART0_ RTS#
APU_UART0_ CTS#
APU_UART0_ INTR

DGPU_PW ROK

PXS_RST#_ R

0.085 A

1 2
1 2
1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2
1 2

1

CC220

0.1U_020 1_6.3V6-K

2

2

1 2

RC3220 0_040 2_5%@

1 2

RC435 0_04 02_5%@

LDRQ0#

PCH_SPI_ CLK
PCH_SPI_ D1
PCH_SPI_ D0
PCH_SPI_ D2
PCH_SPI_ D3
PCH_SPI_ CS0#

LPCCLK0

LPCPD# 1 3

LPC_AD0 13,34,39
LPC_AD1 13,34,39
LPC_AD2 13,34,39
LPC_AD3 13,34,39

LPC_CLKR UN# 13,34

SERIRQ 13,34,39
LPC_FRAME # 13,34 ,39

EC_SCI# 39

KBRST# 39
LDRQ0# 1 3

PCH_SPI_ CLK 1 3

DGPU_PW ROK 1 7

PXS_RST# 1 7

+1.8VALW+1 .8V_SPI

LPCCLK0

RC126 3.3_0 402_1%
RC125 22_0 402_5%TPM@

RC3212

RC3138

RC3136

1 2

1 2

1 2

1K_0402_1%

1K_0402_1%

1K_0402_1%

@

@

@

@

PCH_SPI_ CLK

12

RC282
0_0201_ 5%

EMC_NS@

1

CC219
22P_020 1_25V8

EMC_NS@

2

EMC EMC

12
12

LPC_FRAME #

KBRST#

PXS_RST#_ R

PXS_PW REN_R

DGPU_PW ROK

EC_SCI#

+1.8VS

RC3139

RC3140

1 2

1 2

1K_0402_1%

1K_0402_1%

@

PXS_RST#

PXS_RST#_ R

EGPIO70

AGPIO30

EGPIO75

DGPU_PW ROK

1

RC139
10_0402 _5%

EMC_NS@

1 2

1

CC26
10P_020 1_25V8G

EMC_NS@

2

CLK_PCI_ EC 13,3 9

TPM_CLK 34

1 2

RC152 10K _0402_5%@

1 2

RC3063 10K _0402_5%

1 2

RC3226 10K _0402_5%@

1 2

RC3228 10K _0402_5%@

1 2

RC3229 1K_ 0402_5%@

PX@

12

+3VALW _APU

CC12590.01U_02 01_10V6K

RC322210K_ 0402_5% PX@

RC315710K_ 0402_5% @

RC315810K_ 0402_5%

RC316010K_ 0402_5%

RC155810K_ 0402_5% UMA@

1 2

RC3091 10K _0402_5%@

1 2

1 2

1 2

1 2

1 2

+3VS_AP U

A A

Titl e

Titl e

Titl e

FP5 CLK/LPC/SD/EMMC/UART

FP5 CLK/LPC/SD/EMMC/UART

FP5 CLK/LPC/SD/EMMC/UART

Size Document Num ber Re v

Size Document Num ber Re v

Size Document Num ber Re v

Custom

Custom

Custom

Date : Sheet of

Date : Sheet of

Date : Sheet of

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

8 52

8 52

8 52

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

1.0

1.0

1.0

5

Vinafix.com

4

3

2

1

AD2

USBC0_A2/USB_0_TXP0/DP3_TXP2

AD4

USBC0_A3/USB_0_TXN0/DP3_TXN2

AC2

USBC0_B11/USB_0_RXP0/DP3_TXP3

AC4

D D

USB30_TX_P329

Type C

LEFT USB (3.0) lower

LEFT USB (3.0) upper

C C

USB30_TX_N329

USB30_RX_P329

USB30_RX_N329

USB30_TX_P228
USB30_TX_N228

USB30_RX_P228

USB30_RX_N228

USB30_TX_P128
USB30_TX_N128

USB30_RX_P128

USB30_RX_N128

USB30_TX_P3
USB30_TX_N3

USB30_RX_P3
USB30_RX_N3

USB30_TX_P2
USB30_TX_N2

USB30_RX_P2
USB30_RX_N2

USB30_TX_P1
USB30_TX_N1

USB30_RX_P1
USB30_RX_N1

USBC0_B10/USB_0_RXN0/DP3_TXN3

AF4

USBC0_B2/DP3_TXP1

AF2

USBC0_B3/DP3_TXN1

AE3

USBC0_A11/DP3_TXP0

AE1

USBC0_A10/DP3_TXN0

AG3

USB_0_TXP1

AG1

USB_0_TXN1

AJ9

USB_0_RXP1

AJ8

USB_0_RXN1

AG4

USB_0_TXP2

AG2

USB_0_TXN2

AG7

USB_0_RXP2

AG6

USB_0_RXN2

AA2

USBC1_A2/USB_0_TXP3/DP2_TXP2

AA4

USBC1_A3/USB_0_TXN3/DP2_TXN2

Y1

USBC1_B11/USB_0_RXP3/DP2_TXP3

Y3

USBC1_B10/USB_0_RXN3/DP2_TXN3

AC1

USBC1_B2/DP2_TXP1

AC3

USBC1_B3/DP2_TXN1

AB2

USBC1_A11/DP2_TXP0

AB4

USBC1_A10/DP2_TXN0

AH4

USB_1_TXP0

AH2

USB_1_TXN0

AK7

USB_1_RXP0

AK6

USB_1_RXN0

@

USB

FP5 REV 0.90

PART 10 OF 13

USB_OC0_L/AGPIO16
USB_OC1_L/AGPIO17
USB_OC2_L/AGPIO18
USB_OC3_L/AGPIO24
AGPIO14/USB_OC4_L
AGPIO13/USB_OC5_L

AMD-RAVEN-FP 5_BGA1140

UC2J

USB_0_DP0
USB_0_DM0

USB_0_DP1
USB_0_DM1

USB_0_DP2
USB_0_DM2

USB_0_DP3
USB_0_DM3

USB_1_DP0
USB_1_DM0

USB_1_DP1
USB_1_DM1

USBC_I2C_SCL

USBC_I2C_SDA

USB20_P4

AE7

USB20_N4

AE6

USB20_P7

AG10

USB20_N7

AG9

USB20_P6

AF12

USB20_N6

AF11

USB20_P5

AE10

USB20_N5

AE9

USB20_P5_HUB

AJ12

USB20_N5_HUB

AJ11

USB20_P0

AD9

USB20_N0

AD8

USBC_I2C_SCL

AM6

USBC_I2C_SDA

AM7

BOARD_ID1

AK10
AK9

USB_OC2# USB_OC1#

AL9

USB_OC1#

AL8

BOARD_ID5

AW7

BOARD_ID4

AT12

USB20_P4 36
USB20_N4 36

USB20_P7 29
USB20_N7 29

USB20_P6 28
USB20_N6 28

USB20_P5 28
USB20_N5 28

USB20_P0 35
USB20_N0 35

1 2

RC3239 0_0402_5%@

1 2

RC3233 0_0402_5%@

USB20_P5_HUB 31
USB20_N5_HUB 31

BOARD_ID1 7

USB_OC1# 28
BOARD_ID5 7
BOARD_ID4 7

Card Reader

Type C

LEFT USB (3.0) lower

LEFT USB (3.0) upper

USB HUB(Camera,FP,Touch Screen)

BT

TYPE_C_OCP#USB_OC3#

USB_OC3#
USB_OC1#

USBC_I2C_SCL
USBC_I2C_SDA

TYPE_C_OCP# 29

1 2

RC3218 10K_0402_5%

1 2

RC3219 10K_0402_5%

1 2

RC270 4.7K_0402_5%

1 2

RC3232 4.7K_0402_5%

+1.8VALW

+3VALW_A PU

RSVD_62
RSVD_61
RSVD_65

RSVD_72

RSVD_67
RSVD_63

RSVD_33
RSVD_73

RSVD_53
RSVD_54

RSVD_45
RSVD_46

3

UC2L

AA9
AA8
AC6

AD11

AC9
AA11

T12
AD12

Y6
Y7

W8
W9

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Titl e

Titl e

Titl e

FP5 USB/WIFI

FP5 USB/WIFI

FP5 USB/WIFI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

9 52

9 52

9 52

1.0

1.0

1.0

T11

RSVD_32

AC7

W11
W12

AA12
AC10

RSVD_66

Y9

RSVD_55

Y10

RSVD_56

RSVD_47
RSVD_48

V9

RSVD_38

V10

RSVD_39

RSVD_64
RSVD_68

@

B B

A A

5

4

RSVD

FP5 REV 0.90
PART 12 OF 13

AMD-RAVEN-FP 5_BGA1140

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF LC FUTURE CENTER.

5

Vinafix.com

D D

4

3

2

1

C C

B B

A18

CAM0_CSI2_CLOCKP

C18

CAM0_CSI2_CLOCKN

A15

CAM0_CSI2_DATAP0

C15

CAM0_CSI2_DATAN0

B16

CAM0_CSI2_DATAP1

C16

CAM0_CSI2_DATAN1

C19

CAM0_CSI2_DATAP2

B18

CAM0_CSI2_DATAN2

B17

CAM0_CSI2_DATAP3

D17

CAM0_CSI2_DATAN3

D12

CAM1_CSI2_CLOCKP

B12

CAM1_CSI2_CLOCKN

C13

CAM1_CSI2_DATAP0

A13

CAM1_CSI2_DATAN0

B11

CAM1_CSI2_DATAP1

C12

CAM1_CSI2_DATAN1

J13

RSVD_6

@

CAMERAS

FP5 REV 0.90

PART 13 OF 13

AMD-RAVEN-FP5_BGA1140

UC2M

CAM0_CLK

CAM0_I2C_SCL

CAM0_I2C_SDA

CAM0_SHUTDOWN

CAM1_CLK

CAM1_I2C_SCL

CAM1_I2C_SDA

CAM1_SHUTDOWN

CAM_PRIV_LED

CAM_IR_ILLU

B15

D15
C14

B13

B10

A11
C11

D11

D13
D10

A A

Titl e

Titl e

Titl e

FP5 CAM

FP5 CAM

FP5 CAM

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

10 52

10 52

10 52

1.0

1.0

1.0

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

5

Vinafix.com

4

3

2

1

+VDDCR_SOC

10A

M15

VDDCR_SOC_1

M18

VDDCR_SOC_2

M19

VDDCR_SOC_3

6A

0.2A

0.25A

2A

0.5A

1A

4A

N16

VDDCR_SOC_4

N18

VDDCR_SOC_5

N20

VDDCR_SOC_6

P17

VDDCR_SOC_7

P19

VDDCR_SOC_8

R18

VDDCR_SOC_9

R20

VDDCR_SOC_10

T19

VDDCR_SOC_11

U18

VDDCR_SOC_12

U20

VDDCR_SOC_13

V19

VDDCR_SOC_14

W18

VDDCR_SOC_15

W20

VDDCR_SOC_16

Y19

VDDCR_SOC_17

T32

VDDIO_MEM_S3_1

V28

VDDIO_MEM_S3_2

W28

VDDIO_MEM_S3_3

W32

VDDIO_MEM_S3_4

Y22

VDDIO_MEM_S3_5

Y25

VDDIO_MEM_S3_6

Y28

VDDIO_MEM_S3_7

AA20

VDDIO_MEM_S3_8

AA23

VDDIO_MEM_S3_9

AA26

VDDIO_MEM_S3_10

AA28

VDDIO_MEM_S3_11

AA32

VDDIO_MEM_S3_12

AC20

VDDIO_MEM_S3_13

AC22

VDDIO_MEM_S3_14

AC25

VDDIO_MEM_S3_15

AC28

VDDIO_MEM_S3_16

AD23

VDDIO_MEM_S3_17

AD26

VDDIO_MEM_S3_18

AD28

VDDIO_MEM_S3_19

AD32

VDDIO_MEM_S3_20

AE20

VDDIO_MEM_S3_21

AE22

VDDIO_MEM_S3_22

AE25

VDDIO_MEM_S3_23

AE28

VDDIO_MEM_S3_24

AF23

VDDIO_MEM_S3_25

AF26

VDDIO_MEM_S3_26

AF28

VDDIO_MEM_S3_27

AF32

VDDIO_MEM_S3_28

AG20

VDDIO_MEM_S3_29

AG22

VDDIO_MEM_S3_30

AG25

VDDIO_MEM_S3_31

AG28

VDDIO_MEM_S3_32

AJ20

VDDIO_MEM_S3_33

AJ23

VDDIO_MEM_S3_34

AJ26

VDDIO_MEM_S3_35

AJ28

VDDIO_MEM_S3_36

AJ32

VDDIO_MEM_S3_37

AK28

VDDIO_MEM_S3_38

AL28

VDDIO_MEM_S3_39

AL32

VDDIO_MEM_S3_40

AP12

VDDIO_AUDIO

AL18

VDD_33_1

AM17

VDD_33_2

AL20

VDD_18_1

AM19

VDD_18_2

AL19

VDD_18_S5_1

AM18

VDD_18_S5_2

AL17

VDD_33_S5_1

AM16

VDD_33_S5_2

AL14

VDDP_S5_1

AL15

VDDP_S5_2

AM14

VDDP_S5_3

AL13

VDDP_1

AM12

VDDP_2

AM13

VDDP_3

AN12

VDDP_4

AN13

VDDP_5

AT11

VDDBT_RTC_G

@

EC_RTCRST#_ON 39

D D

+1.2V

1

CC1337

2

1U_0402_6.3V6K

BOBUBU

1U_0402_6.3V6K

1U_0402_6.3V6K

+RTCBATT

1U_0402_6.3V6K

+3VS_APU

1

CC1338

2

1U_0402_6.3V6K

CD@

1

CC1324

CC1323

2

1U_0402_6.3V6K

+RTCBATT

RC3128 1K_0402_5%

1

JCMOS1

@

1

2

1U_0402_6.3V6K

BU

1 2

+1.8VS

1

CC1325

2

+RTCBATT_APU

12

13

D

S

1 2

1U_0402_6.3V6K

RC8
470_0603_5%

@

+1.8VALW

RC3154

RC3118
0_0402_5%

0_0402_5%

@

@

1 2

12

CC1385

BO

1

1

CC1327

CC1326

2

2

1U_0402_6.3V6K

1

CC1340

2

1U_0402_6.3V6K

BU

QC7

EC_RTCRST#_ON

2

G

2N7002KW_SOT323-3

@

CC1339

22U_0603_6.3V6-M

180P_0402_50V8-J

CC192

+VDD_AUD_ALW

1

2

1U_0402_6.3V6K

0.25A

0.1A

1

2

0.22U_0201_6.3V6-K

12

RC15
100K_0402_5%

@

+3VS+VDDC_VDD

1 2

+1.8VS

+1.8VALW

+3VALW_APU

+0.9VALW

+0.9VS

12

CC1381

22U_0603_6.3V6-M

BO(Bottom side outside SOC)

1

CC37

2

12

12

12

12

12

RC3112 0_0402_5%@

1

CC1335

CC1336

2

CC1376

1U_0402_6.3V6K

BO B U

22U_0603_6.3V6-M

CC1377

22U_0603_6.3V6-M

CC1378

22U_0603_6.3V6-M

CC1379

22U_0603_6.3V6-M

BO BU

CC1380

22U_0603_6.3V6-M

1U_0402_6.3V6K

CD@

1

CC1334

CC1333

2

1U_0402_6.3V6K

BO BU

CD@

1

CC1331

CC1332

2

1U_0402_6.3V6K

BO B U

CD@

1

CC1328

CC1329

2

1U_0402_6.3V6K

CD@

1

1

CC1319

CC1320

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

UC5

1

Vin

2

GND

AP2138N-1.5TRG1_SOT23-3

12

CC1375

22U_0603_6.3V6-M

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

1

CC1330

2

2

1U_0402_6.3V6K

CD@

1

1

CC1322

CC1321

2

2

1U_0402_6.3V6K

3

Vout

1

CC194

2

1

CC1382

2

180P_0402_50V8-J

+VDDCR_SOC

1

C C

B B

CC1372

10U_0402_6.3V6M

1

2

2

+1.2V

12

12

CC1341

CC1257

22U_0603_6.3V6-M

CD@

CD@

All BU(on bottom side under SOC)

+1.2V

1

CC168

2

@

CC1383
10U_0402_6.3V6M

12

12

CC1342

CC1343

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

1

CC169

CC170

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

CD@

DECOUPLING BETWEEN PROCESSOR AND DIMMs
ACROSS VDDIO AND VSS SPLIT

12

12

12

CC1345

CC1344

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

CC172

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

12

12

CC1346

CC1347

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CD@

1

1

CC179

CC176

2

2

180P_0402_50V8-J

@

1

1

1

CC1374

CC1384

CC1373

CC1348

22U_0603_6.3V6-M

180P_0402_50V8-J

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8-J

CD@

VCCRTC

1 2

RC231 10K_0402_5%

POWER

FP5 REV 0.90
PART 6 OF 13

AMD-RAVEN-FP5_BGA1140

UC2F

VDDCR_1
VDDCR_2
VDDCR_3
VDDCR_4
VDDCR_5
VDDCR_6
VDDCR_7
VDDCR_8

VDDCR_9
VDDCR_10
VDDCR_11
VDDCR_12
VDDCR_13
VDDCR_14
VDDCR_15
VDDCR_16
VDDCR_17
VDDCR_18
VDDCR_19
VDDCR_20
VDDCR_21
VDDCR_22
VDDCR_23
VDDCR_24
VDDCR_25
VDDCR_26
VDDCR_27
VDDCR_28
VDDCR_29
VDDCR_30
VDDCR_31
VDDCR_32
VDDCR_33
VDDCR_34
VDDCR_35
VDDCR_36
VDDCR_37
VDDCR_38
VDDCR_39
VDDCR_40
VDDCR_41
VDDCR_42
VDDCR_43
VDDCR_44
VDDCR_45
VDDCR_46
VDDCR_47
VDDCR_48
VDDCR_49
VDDCR_50
VDDCR_51
VDDCR_52
VDDCR_53
VDDCR_54
VDDCR_55
VDDCR_56
VDDCR_57
VDDCR_58
VDDCR_59
VDDCR_60
VDDCR_61
VDDCR_62
VDDCR_63
VDDCR_64
VDDCR_65
VDDCR_66
VDDCR_67
VDDCR_68
VDDCR_69
VDDCR_70
VDDCR_71
VDDCR_72
VDDCR_73
VDDCR_74
VDDCR_75
VDDCR_76
VDDCR_77
VDDCR_78
VDDCR_79
VDDCR_80
VDDCR_81
VDDCR_82
VDDCR_83

G7
G10
G12
G14
H8
H11
H15
K7
K12
K14
L8
M7
M10
N14
P7
P10
P13
P15
R8
R14
R16
T7
T10
T13
T15
T17
U14
U16
V13
V15
V17
W7
W10
W14
W16
Y8
Y13
Y15
Y17
AA7
AA10
AA14
AA16
AA18
AB13
AB15
AB17
AB19
AC14
AC16
AC18
AD7
AD10
AD13
AD15
AD17
AD19
AE8
AE14
AE16
AE18
AF7
AF10
AF13
AF15
AF17
AF19
AG14
AG16
AG18
AH13
AH15
AH17
AH19
AJ7
AJ10
AJ14
AJ16
AJ18
AK13
AK15
AK17
AK19

+VDDC_VDD

35A

A A

Title

Title

Title

FP5 POWER

FP5 POWER

FP5 POWER

Size

Size

Size

Document Number R ev

Document Number R ev

Document Number R ev

Custom

Custom

Custom

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

330ARR

330ARR

330ARR

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

11 52

11 52

11 52

5

4

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Security Classification LC Future Center Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

1.0

1.0

1.0

5

Vinafix.com

D D

4

3

2

1

VSS_316

A3

VSS_1

A5

VSS_2

A7

VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

C3

VSS_13
VSS_14
VSS_15
VSS_16
VSS_17

E7

VSS_18

E8

VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35

F5

VSS_36
VSS_37

G1

VSS_38

G5

VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46

H5

VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53

K1

VSS_54

K5

VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61

AMD-RAVEN-FP5_BGA1140

@

GND

FP5 REV 0.90

PART 7 OF 13

VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123

K32
L5
L13
L15
L18
L20
L25
L28
M1
M5
M12
M21
M23
M26
M28
M32
N4
N5
N8
N11
N13
N15
N17
N19
N22
N25
N28
P1
P5
P14
P16
P18
P20
P23
P26
P28
P32
R5
R11
R12
R13
R15
R17
R19
R22
R25
R28
R30
T1
T5
T14
T16
T18
T20
T23
T26
T28
U13
U15
U17
U19
V5

N12

A10
A12
A14
A16
A19
A21
A23
A26
A30

C32
D16
D18
D20

E10
E11
E12
E13
E14
E15

C C

B B

E16
E18
E19
E20
E21
E22
E23
E25
E26
E27

F28

G16
G19
G21
G23
G26
G28
G32

H13
H18
H20
H22
H25
H28

K16
K19
K21
K22
K26
K28

AA13
AA15
AA17
AA19
AB14
AB16
AB18
AB20

AC11
AC12
AC13
AC15
AC17
AC19

AD14
AD16
AD18
AD20

AE11
AE12
AE13
AE15
AE17
AE19

AF14
AF16
AF18
AF20

V8

VSS_124

V11

VSS_125

V12

VSS_126

V14

VSS_127

V16

VSS_128

V18

VSS_129

V20

VSS_130

V22

VSS_131

V25

VSS_132

W1

VSS_133

W5

VSS_134

W13

VSS_135

W15

VSS_136

W17

VSS_137

W19

VSS_138

W23

VSS_139

W26

VSS_140

Y5

VSS_141

Y11

VSS_142

Y12

VSS_143

Y14

VSS_144

Y16

VSS_145

Y18

VSS_146

Y20

VSS_147

AA1

VSS_148

AA5

VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157

AC5

VSS_158

AC8

VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165

AD1

VSS_166

AD5

VSS_167
VSS_168
VSS_169
VSS_170
VSS_171

AE5

VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178

AF1

VSS_179

AF5

VSS_180
VSS_181
VSS_182
VSS_183
VSS_184

AG5

VSS_185

@

UC2G

UC2H

GND

VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247

FP5 REV 0.90

PART 8 OF 13

AMD-RAVEN-FP5_BGA1140

AG8
AG11
AG12
AG13
AG15
AG17
AG19
AH14
AH16
AH18
AH20
AJ1
AJ5
AJ13
AJ15
AJ17
AJ19
AK5
AK8
AK11
AK12
AK14
AK16
AK18
AK20
AK22
AK25
AL1
AL5
AL7
AL10
AL12
AL16
AL23
AL26
AM5
AM8
AM15
AM20
AM22
AM25
AM28
AN1
AN5
AN7
AN10
AN15
AN18
AN21
AN23
AN26
AN28
AN32
AP5
AP8
AP13
AP15
AP18
AP20
AP25
AP28
AR1

AR12
AR14
AR16
AR19
AR21
AR26
AR28
AR32

AU11
AU13
AU15
AU18
AU20
AU22
AU25
AU28

AV10
AV12
AV14
AV16
AV19
AV21
AV23
AV26
AV28
AV32

AW5

AW28

AY10
AY11
AY12
AY13
AY14
AY15
AY16
AY18
AY19
AY20
AY21
AY22
AY23
AY25
AY26
AY27

BB20
BB32

BD10
BD12
BD14

AR5

VSS_248

AR7

VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257

AU5

VSS_258

AU8

VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267

AV1

VSS_268

AV5

VSS_269

AV7

VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282

AY6

VSS_283

AY7

VSS_284

AY8

VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301

BB1

VSS_302
VSS_303
VSS_304

BD3

VSS_305

BD7

VSS_306
VSS_307
VSS_308
VSS_309

@

UC2K

GND/RSVD

VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315

RSVD_1
RSVD_5
RSVD_7
RSVD_8

RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_22
RSVD_23
RSVD_30
RSVD_31
RSVD_37
RSVD_44
RSVD_49
RSVD_50
RSVD_57
RSVD_58
RSVD_59
RSVD_60
RSVD_69
RSVD_70
RSVD_71
RSVD_74
RSVD_75
RSVD_78
RSVD_79
RSVD_80
RSVD_81
RSVD_82
RSVD_83
RSVD_87
RSVD_88

RSVD_14
RSVD_84
RSVD_85
RSVD_86

FP5 REV 0.90

PART 11 OF 13

AMD-RAVEN-FP5_BGA1140

BD16
BD19
BD21
BD23
BD26
BD30

B20
G3
J20
K3
K6
K20
M3
M6
M13
P6
P22
T3
T6
T29
W6
W21
W22
Y21
Y27
AA3
AA6
AC29
AD3
AD6
AF3
AF6
AF30
AJ6
AJ24
AK23
AK27
AL3
AN29
AN31

UNNAMED_15_F P5_I216_RSVD14

M14

UNNAMED_15_F P5_I216_RSVD84

AL6

UNNAMED_15_F P5_I216_RSVD85

AL11

UNNAMED_15_F P5_I216_RSVD86

AN16

1 2

RC3103 0_0402_5%@

1 2

RC3104 0_0402_5%@

1 2

RC3105 0_0402_5%@

1 2

RC3106 0_0402_5%@

APU_PLLTEST0

APU_PLLTEST1
APU_DBRDY

+5VALW

APU_PLLTEST0 6

APU_PLLTEST1 6
APU_DBRDY 6

A A

Titl e

Titl e

Titl e

FP5 GND

FP5 GND

FP5 GND

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

12 52

12 52

12 52

1.0

1.0

1.0

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

5

Vinafix.com

D D

PCH_SPI_CLK8 SYS_RESET#7

PCH_SPI_CLK

4

+1.8VS +1.8VALW +3VALW_APU

RC3134
10K_0402_5%

@

12

RC3133
10K_0402_5%

12

RC159
2K_0402_5%

@

12

RC156
10K_0402_5%

12

RC163
2K_0402_5%

@

12

3

2

1

STRAP PINS

PCH_SPI_CLK

C C

SYS_RESET#

1:USE 48MHZ CRYSTAL CLOCK AND
GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
0:USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK AND
GENERATE INTERNAL CLOCKS ONLY

1:NORMAL RESET MODE(DEFAULT)

SYS_RESET#

0:SHORT RESET MODE

LPC ROM EMULATOR HEADER

LPC@

RC3146
0_0402_5%

1 2

LPC_RST#_H

2

1

+3VS_APU+3VALW_APU

LPC@

1 2

LPCRUNPWR

I2C2_SCL_LPC

2

1

RC3145
0_0402_5%

CD347

0.1U_0402_10V7K

LPC@

PIN4 should be removed as a Key

DAISY CHAIN ROUT ING FO R LPC SIGNALS

J601

1 2
3 4

UNNAMED_16_C ON20_I130_P6

5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20

HEADER_2X10

@

RC3142 0_0402_5%@

LPC_AD1

I2C2_SDA_LPC

SERIRQ
LPC_CLKRUN#

LDRQ0#

1 2

RC3153 0_0402_5%LPC@

1 2

PM_SLP_S5#

PM_SLP_S5# 7,39
LPC_AD2 8,34,39
LPC_AD1 8,34,39

TP_I2C0_SDA_R 7,40
SERIRQ 8,34,39
LPC_CLKRUN# 8,34

15P_0402_50V8J

CC1387

B B

CLK_PCI_EC8,39
LPC_FRAME#8,34,39

APU_LPC_RST#8,34,39

LPC_AD38,34,39

LPC_AD08,34,39

TP_I2C0_SCL_R7,40

LPCPD#8 LDRQ0# 8

@

CLK_PCI_EC
LPC_FRAME#
APU_LPC_RST#

LPC_AD3 LPC_AD2

LPC_AD0

LPCPD#

12

RC3147

UNNAMED_16_C AP_I116_B

1 2

@

1 2

RC3144 0_0402_5%LPC@

1 2

RC3152 0_0402_5%LPC@

33_0402_5%

CD345

0.1U_0402_10V7K

LPC@

RC3152 RC3153 s hould be put on APU s ide to reduce stub when MP

+3VS_APU

1 2

RC3214 10K_0402_5%LPC@

1 2

RC3215 10K_0402_5%@

1 2

A A

RC3216 100K_0402_5%LPC@

1 2

CC1392 150P_0402_50V8-J@

5

4

LPCPD#

LPC_CLKRUN#

APU_LPC_RST#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Titl e

Titl e

Titl e

FP5 Straps

FP5 Straps

FP5 Straps

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

330ARR

330ARR

330ARR

1

13 52

13 52

13 52

1.0

1.0

1.0

5

Vinafix.com

JDDR1A

1

DDRA_DQ1

D D

C C

RD273 240_0402_1%@
RD274 240_0402_1%@

DDRA_CKE05

DDRA_BG15 DDRA_ACT# 5
DDRA_BG05

B B

A A

+1.2V

12

RD258
1K_0402_1%

@

DDRA_ALERT#

+3VS +3VS

12

RD26

10K_0402_5%

@

DDRA0_SA0 DDRA0_SA1 DDRA0_SA2

12

RD268
0_0402_5%

@

DDRA_DQ6

DDRA_DQS#0
DDRA_DQS0

DDRA_DQ7

DDRA_DQ3

DDRA_DQ8

DDRA_DQ9

DDRA_DM1

DDRA_DQ17

DDRA_DQ21

DDRA_DQS#2
DDRA_DQS2

DDRA_DQ22

DDRA_DQ19

DDRA_DQ25

DDRA_DQ29

DDRA_DM3

DDRA_DQ30

DDRA_DQ31

1 2
1 2

+3VS

12

12

+1.2V +1.2V+1.2V

DDRA_CKE0

DDRA_BG1
DDRA_BG0

DDRA_MA12
DDRA_MA9

DDRA_MA8
DDRA_MA6 DDRA_MA4

RD269

10K_0402_5%

@

RD28
0_0402_5%

@

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_ n/NC

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_ n/NC

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AS0-26001-1P60

ME@

RD11

1K_0402_1%

12

RD270

10K_0402_5%

@

12

RD29
0_0402_5%

@

DM0_n/DBIO_n/NC

DM2_n/DBl2_ n/NC

DM8_n/DBI8_n/NC

+1.2V

12

RD10
1K_0402_1%

1 2

CD262

1

2

15mil

0.1U_0201_6.3V6-K

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

VSS_11

DQ12

VSS_13

VSS_15

DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26

VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24
VSS_35
DQS3_c

DQS3_t

VSS_38

DQ31
VSS_40

DQ27
VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

CKE1

VDD_2
ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

CD116

DQ4

DQ0

DQ6

DQ2

DQ8

A11

1

2

A7

A5
A4

+VREF_CA

0.1U_0201_6.3V6-K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130

1

2

CD117

1000P_0201_50V7-K

4

DDRA_DQ4

DDRA_DQ5

DDRA_DM0

DDRA_DQ0

DDRA_DQ2

DDRA_DQ12

DDRA_DQ13

DDRA_DQS#1
DDRA_DQS1

DDRA_DQ10DDRA_DQ14

DDRA_DQ15DDRA_DQ11

DDRA_DQ16

DDRA_DQ20

DDRA_DM2

DDRA_DQ18

DDRA_DQ23

DDRA_DQ24

DDRA_DQ28

DDRA_DQS#3
DDRA_DQS3

DDRA_DQ26

DDRA_DQ27

MEM_MA_RST#
DDRA_CKE1

DDRA_ACT#
DDRA_ALERT#

DDRA_MA11
DDRA_MA7

DDRA_MA5

+2.5VS

for MEM_MB_RST# overshoot issue

DDRA_CKE1 5

DDRA_ALERT# 5

+3VS +VDDSPD

1 2

RD271 0_0402_5%@

1 2

RD272 0_0402_5%@

Layout Note: Place near JDDR1

+0.6VS

0.1U_0201_6.3V6-K

1

CD251

CD249

@

@

2

+2.5V

follow CRB 1pcs 1uf + 2pcs 0.1uf + 1pcs 180pf

1U_0402_6.3V6K

1

CD123

CD122

2

1

2

1

2

1

2

@

CD120

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CD250

CD124

MEM_MA_RST# 5

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

1

CD248

2

0.1U_0201_6.3V6-K

1

CC206

2

1

2

1

2

+VDDSPD

4.7U_0402_6.3V6M

180P_0402_50V8-J

3

+1.2V

JDDR1B

DDRA_MA3
DDRA_MA1

DDRA_CLK05
DDRA_CLK0#5

DDRA_PAR5

DDRA_BA15

DDRA_CS0#5

DDRA_MA14_WE#5

DDRA_ODT05

DDRA_CS1#5

DDRA_ODT15

APU_SMB_CLK7,35 APU_SMB_DATA 7,35

1

1

CD29

CD28

0.1U_0201_6.3V6-K

2

2

+1.2V

follow CRB 6pcs 0.1uffollow CRB 1pcs 4.7uf + 1pcs 0.1uf

0.1U_0201_6.3V6-K

1

CD16

2

+1.2V

1

CD261

@

2

10U_0603_6.3V6M

DDRA_CLK0 DDRA_CLK1
DDRA_CLK0#

DDRA_BA1

DDRA_CS0#
DDRA_MA14_WE#

DDRA_ODT0
DDRA_CS1#

DDRA_ODT1

DDRA_DQ33

DDRA_DQ32

DDRA_DQS#4
DDRA_DQS4

DDRA_DQ35

DDRA_DQ34

DDRA_DQ40

DDRA_DQ41

DDRA_DM5

DDRA_DQ46

DDRA_DQ47

DDRA_DQ49

DDRA_DQS#6
DDRA_DQS6

DDRA_DQ50

DDRA_DQ55

DDRA_DQ60

DDRA_DQ57

DDRA_DM7

DDRA_DQ63

APU_SMB_CLK APU_SMB_DATA

+2.5V

CD121

22P_0402_50V8-J

RF_NS@

RF

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

1

1

CD18

CD17

2

2

1

CD63

@

1

CD66

2

2

10U_0603_6.3V6M

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

DM4_n/DBl4_ n/NC

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_ n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

DM6_n/DBl6_ n/NC

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_ n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

261

0.1U_0201_6.3V6-K

1

CD21

2

1

2

22U_0603_6.3V6-M

VPP_2

GND_1

ARGOS_D4AS0-26001-1P60

ME@

0.1U_0201_6.3V6-K

1

CD22

2

1

CD19
22P_0402_50V8-J

RF@

2

1

2

CD20

CD67

22U_0603_6.3V6-M

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t
VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t
VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

0.1U_0201_6.3V6-K

1

2

132

A2

134
136
138
140
142
144

A0

146
148
150

BA0

152
154
156
158

A13

160
162
164
166

SA2

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254

SDA

256

SA0

258

Vtt

260

SA1

262

CD23

@

1

CD260
22P_0402_50V8-J

RF@

2

+1.2V

DDRA_MA2
MEM_MA_EVENT#

DDRA_CLK1#

DDRA_MA0

DDRA_MA10

DDRA_BA0
DDRA_MA16_RAS#

DDRA_MA15_CAS#
DDRA_MA13

DDRA0_SA2

DDRA_DQ37

DDRA_DQ36

DDRA_DM4

DDRA_DQ39

DDRA_DQ38

DDRA_DQ45

DDRA_DQ44

DDRA_DQS#5
DDRA_DQS5

DDRA_DQ42

DDRA_DQ43

DDRA_DQ53DDRA_DQ52

DDRA_DQ48

DDRA_DM6

DDRA_DQ54

DDRA_DQ51

DDRA_DQ56

DDRA_DQ61

DDRA_DQS#7
DDRA_DQS7

DDRA_DQ58

DDRA_DQ59DDRA_DQ62

DDRA0_SA0

DDRA0_SA1

LP2301ALT1G_SOT23-3

SUSP27,41

27P 25V J NPO 0201

0.1U_0201_6.3V6-K

1

1

CD58

EMC@

2

2

1

2

2

DDRA_DQ[0..63]

DDRA_DQS[0..7]

DDRA_DQS#[0..7]

DDRA_MA[0..13]

DDRA_DM[0..7]

QD1

CD59

@

CD12
22P_0402_50V8-J

RF@

D

S

13

G

2

@

0.1U_0201_6.3V6-K

1

CD60

EMC@

2

DDRA_DQ[0..63] 5

DDRA_DQS[0..7] 5

DDRA_DQS#[0..7] 5

DDRA_MA[0..13] 5

DDRA_DM[0..7] 5

MEM_MA_EVENT# 5

DDRA_CLK1 5
DDRA_CLK1# 5

DDRA_BA0 5

DDRA_MA16_RAS# 5

DDRA_MA15_CAS# 5

+VREF_CA

+0.6VS

+2.5VS+2.5V

27P 25V J NPO 0201

1

1

CD61

@

2

2

1

CD348
22P_0402_50V8-J

RF_NS@

2

0.1U_0201_6.3V6-K

CD62

@

1

2

0.1U_0201_6.3V6-K

1

CC211

2

CD349
22P_0402_50V8-J

RF_NS@

1

Swap Table

Net NamePin Name

DDRA_DQ6

DQ0

DDRA_DQ5

DQ1

DDRA_DQ2

DQ2

DDRA_DQ3

DQ3

DDRA_DQ4

DQ4

DDRA_DQ0

DQ5

DDRA_DQ1

DQ6

DDRA_DQ7

DQ7

DDRA_DQS#0

DQS#0

DDRA_DQS0

DQS0

DDRA_DQ13

DQ8

DDRA_DQ9

DQ9

DDRA_DQ14

DQ10

DDRA_DQ10

DQ11

DDRA_DQ12

DQ12

DDRA_DQ8

DQ13

DDRA_DQ15

DQ14

DDRA_DQ11

DQ15

DDRA_DQS#1

DQS#1

DDRA_DQS1

DQS1

DQ16

DDRA_DQ20

DQ17

DDRA_DQ21

DQ18

DDRA_DQ22

DQ19

DDRA_DQ19

DQ20

DDRA_DQ16

DQ21

DDRA_DQ17

DQ22

DDRA_DQ23

DQ23

DDRA_DQ18

DQS#2

DDRA_DQS#2

DQS2

DDRA_DQS2

DDRA_DQ28

DQ24

DDRA_DQ29

DQ25

DDRA_DQ31

DQ26

DDRA_DQ27

DQ27

DDRA_DQ24

DQ28

DDRA_DQ25

DQ29

DDRA_DQ30

DQ30

DDRA_DQ26

DQ31

DDRA_DQS#3

DQS#3

DDRA_DQS3

DQS3

DDRA_DQ33

DQ32

DDRA_DQ37

DQ33

DDRA_DQ34

DQ34

DDRA_DQ38

DQ35

DDRA_DQ32

DQ36

DDRA_DQ36

DQ37

DDRA_DQ35

DQ38

DDRA_DQ39

DQ39

DDRA_DQS#4

DQS#4

DDRA_DQS4

DQS4

DDRA_DQ44

DQ40

DDRA_DQ40

DQ41

DDRA_DQ47

DQ42

DDRA_DQ43

DQ43

DDRA_DQ41

DQ44

DDRA_DQ45

DQ45

DDRA_DQ46

DQ46

DDRA_DQ42

DQ47

DDRA_DQS#5

DQS#5

DDRA_DQS5

DQS5

DQ48

DDRA_DQ48

DQ49

DDRA_DQ49

DQ50

DDRA_DQ55

DQ51

DDRA_DQ50

DQ52

DDRA_DQ52

DQ53

DDRA_DQ53

DQ54

DDRA_DQ54

DQ55

DDRA_DQ51

DQS#6

DDRA_DQS#6

DQS6

180P_0402_50V8-J

1

2

RF

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS#7
DQS7

DDRA_DQS6

DDRA_DQ60
DDRA_DQ56
DDRA_DQ63
DDRA_DQ59
DDRA_DQ61
DDRA_DQ57
DDRA_DQ58
DDRA_DQ62
DDRA_DQS#7
DDRA_DQS7

SPD Address = A2H

5

4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Title

DDRIV SO-DIMM A

DDRIV SO-DIMM A

DDRIV SO-DIMM A

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

Date : She et o f

Date : She et o f

Date : She et o f

330ARR

330ARR

330ARR

1

14 52

14 52

14 52

1.0

1.0

1.0

5

Vinafix.com

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8

L2
M8
L8

K8
K7

K2

F3
G3
A7
B7

E2
E7

N2
N8

L3
L7
P9

M2

K3

T3

N9

P1

F1
H1
A2
D2
E3
A8
D8
E8
C9
H9

F9

12

RD116
240_04 02_1%

@

DRAM@

UD3

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD118

MT40A51 2M16HA08 3EA_F BGA96

240_04 02_1%

DRAM@

UD1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

WE_N/A14
CAS_N/A15
RAS_N/A16

CK_C
CK_T

CKE

LDQS_C
LDQS_T
UDQS_C

VDD10

UDQS_T

VDDQ1

NF/UDM_N/UDBI_N

VDDQ2

NF/LDM_N/LDBI_N

VDDQ3
VDDQ4

BA0

VDDQ5

BA1

VDDQ6
VDDQ7

ACT_N

VDDQ8

CS_N

VDDQ9

ALERT_N

VDDQ10

BG0

ODT

VREFCA

PAR

TEN

RESET_N

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ZQ

MT40A51 2M16HA08 3EA_F BGA96

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VPP1
VPP2

VREFCA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

@

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12

D D

RF

C C

B B

A A

DDRB_MA 14_WE #5
DDRB_MA 15_CAS #5
DDRB_MA 16_RAS #5

DDRB_C LK0#5
DDRB_C LK05

DDRB_C KE05

DDRB_B A05
DDRB_B A15

DDRB_A CT#5
DDRB_C S0#5
DDRB_A LERT#5

DDRB_B G05

DDRB_O DT05

DDRB_P AR5

1 2

MEM_MB_RST #5

1 2

DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_C LK0#
DDRB_C LK0

DDRB_C KE0

DDRB_D QS#0
DDRB_D QS0
DDRB_D QS#1
DDRB_D QS1

DDRB_D M1

DDRB_B A0
DDRB_B A1

DDRB_A CT#
DDRB_C S0#
DDRB_A LERT#

DDRB_B G0

DDRB_O DT0

DDRB_P AR

TEN1

RD25110K_04 02_5% D RAM@

MEM_MB_RST #

1

CD132

2

@

0.1U_0201_6.3V6-K

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_C LK0#
DDRB_C LK0

DDRB_C KE0

DDRB_D QS#4
DDRB_D QS4
DDRB_D QS#5
DDRB_D QS5

DDRB_D M5
DDRB_D M4

DDRB_B A0
DDRB_B A1

DDRB_A CT#
DDRB_C S0#
DDRB_A LERT#

DDRB_B G0

DDRB_O DT0

DDRB_P AR

RD25510K_04 02_5% D RAM@

TEN3

MEM_MB_RST #

1

CD161

2

@

0.1U_0201_6.3V6-K

DDRB_D Q3

G2

DDRB_D Q7

F7

DDRB_D Q2

H3

DDRB_D Q0

H7

DDRB_D Q6

H2

DDRB_D Q5

H8

DDRB_D Q1

J3

DDRB_D Q4

J7

DDRB_D Q11

A3

DDRB_D Q8

B8

DDRB_D Q15

C3

DDRB_D Q9

C7

DDRB_D Q10

C2

DDRB_D Q13

C8

DDRB_D Q14

D3

DDRB_D Q12

D7

+1.2V

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

NC

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

+1.2V

DRAM@

DDRB_D Q39
DDRB_D Q35
DDRB_D Q34
DDRB_D Q37
DDRB_D Q38
DDRB_D Q36
DDRB_D Q32
DDRB_D Q33
DDRB_D Q47
DDRB_D Q40
DDRB_D Q46
DDRB_D Q44
DDRB_D Q42
DDRB_D Q45
DDRB_D Q43
DDRB_D Q41

CD234

DRAM@

+VREF_C A

1

1

DRAM@

CD189

CD188

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

+VREF_C A

1

1

CD235

DRAM@

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

4

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7

M3

T2

M7

T8

L2

M8

L8

K8
K7

K2

F3
G3
A7
B7

E2
E7

N2
N8

L3
L7
P9

M2

K3

T3

N9

P1

F1
H1
A2
D2
E3
A8
D8
E8
C9
H9

F9

12

RD117
240_04 02_1%

DRAM@

UD4

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

12

RD119

MT40A51 2M16HA08 3EA_F BGA96

240_04 02_1%

@

DRAM@

UD2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13

WE_N/A14
CAS_N/A15
RAS_N/A16

CK_C
CK_T

CKE

LDQS_C
LDQS_T
UDQS_C
UDQS_T

NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N

BA0
BA1

ACT_N
CS_N
ALERT_N

BG0

ODT

PAR

TEN

RESET_N

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

ZQ

MT40A51 2M16HA08 3EA_F BGA96

@

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_C LK0#
DDRB_C LK0

DDRB_C KE0

DDRB_D QS#2
DDRB_D QS2
DDRB_D QS#3
DDRB_D QS3

DDRB_D M3
DDRB_D M2DDRB_D M0

DDRB_B A0
DDRB_B A1

DDRB_A CT#
DDRB_C S0#

+2.5V

1

1

CD203

CD202

2

2

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

+2.5V

1

1

CD237

CD236

2

2

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

1 2

1 2

DDRB_A LERT#

DDRB_B G0

DDRB_O DT0

DDRB_P AR

TEN2

RD25310K_04 02_5% DRAM@

MEM_MB_RST #

1

CD160

2

@

0.1U_0201_6.3V6-K

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_C LK0#
DDRB_C LK0

DDRB_C KE0

DDRB_D QS#7
DDRB_D QS7
DDRB_D QS#6
DDRB_D QS6

DDRB_D M6
DDRB_D M7

DDRB_B A0
DDRB_B A1

DDRB_A CT#
DDRB_C S0#
DDRB_A LERT#

DDRB_B G0

DDRB_O DT0

DDRB_P AR

TEN4

RD25710K_04 02_5% D RAM@

MEM_MB_RST #

1

CD162

2

@

0.1U_0201_6.3V6-K

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VREFCA

3

DDRB_D Q19

G2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDD10

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VPP1
VPP2

VREFCA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDD10

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

NC

DDRB_D Q23

F7

DDRB_D Q22

H3

DDRB_D Q17

H7

DDRB_D Q18

H2

DDRB_D Q21

H8

DDRB_D Q20

J3

DDRB_D Q16

J7

DDRB_D Q27

A3

DDRB_D Q29

B8

DDRB_D Q31

C3

DDRB_D Q25

C7

DDRB_D Q26

C2

DDRB_D Q28

C8

DDRB_D Q30

D3

DDRB_D Q24

D7

+1.2V

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9
K9
M9

T7

NC

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

+1.2V

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1

E1
K1
N1
T1
B2
G8
E9

DRAM@

K9
M9

T7

DRAM@

DDRB_D Q59
DDRB_D Q57
DDRB_D Q58
DDRB_D Q61
DDRB_D Q63
DDRB_D Q56
DDRB_D Q62
DDRB_D Q60
DDRB_D Q50
DDRB_D Q52
DDRB_D Q55
DDRB_D Q48
DDRB_D Q54
DDRB_D Q49
DDRB_D Q51
DDRB_D Q53

CD238

+VREF_C A

1

1

CD230

CD231

2

2

DRAM@

1000P_0201_50V7-K

+1.2V

CD266

CD267

47P_0201_25V8-J

1

EMC_NS@

2

+VREF_C A

1

1

CD239

2

2

DRAM@

0.1U_0201_6.3V6-K

1000P_0201_50V7-K

+2.5V

1

1

CD232

CD233

2

2

DRAM@

DRAM@

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

CD268

CD269

CD270

27P 25V J NPO 0201

27P 25V J NPO 0201

27P 25V J NPO 0201

1

1

1

EMC@

EMC@

2

CD240

DRAM@

1

EMC@

EMC@

2

2

2

+2.5V

1

1

CD241

DRAM@

2

2

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

2/22: change to K back for materil stock risk, and this change
has conf i r m t o A MD

CD273

CD274

CD272

CD271

27P 25V J NPO 0201

EMC@

47P_0201_25V8-J

27P 25V J NPO 0201

27P 25V J NPO 0201

1

1

1

1

EMC_NS@

EMC@

EMC@

2

2

2

2

2

DDRB_D Q[0..63]

DDRB_D QS[0..7]

DDRB_D QS#[0..7]

DDRB_MA [0..13]

DDRB_D M[0..7]

DDRB_D Q[0..63] 5

DDRB_D QS[0..7] 5

DDRB_D QS#[0..7] 5

DDRB_MA [0..13] 5

DDRB_D M[0..7] 5

CD163 change from K to J

DDRB_C LK0#
DDRB_C LK0

DDRB_MA 0
DDRB_MA 1
DDRB_MA 2
DDRB_MA 3
DDRB_MA 4
DDRB_MA 5
DDRB_MA 6
DDRB_MA 7
DDRB_MA 8
DDRB_MA 9
DDRB_MA 10
DDRB_MA 11
DDRB_MA 12
DDRB_MA 13

DDRB_MA 14_WE #
DDRB_MA 15_CAS #
DDRB_MA 16_RAS #

DDRB_A CT#

DDRB_O DT0
DDRB_C S0#
DDRB_C KE0

DDRB_B A0
DDRB_B A1

DDRB_B G0
DDRB_P AR

DDRB_A LERT#

CD277

CD276

CD275

47P_0201_25V8-J

27P 25V J NPO 0201

47P_0201_25V8-J

1

1

EMC_NS@

EMC_NS@

2

2

Layout Note: Place near DRAM

27P 25V J NPO 0201

3A@1.5 V

1

EMC@

+1.2V

2

follow SCL 2 0pcs 0.22uf

0.22U_0201_6.3V6-K

1

CD155

CD154

2

DRAM@

3A@1.5 V

+1.2V

0.22U_0201_6.3V6-K

1

CD174

CD173

2

DRAM@

+1.2V

0.22U_0201_6.3V6-K

1

CD218

CD215

@

@

2

+0.6VS

follow SCL 1 0pcs 0.22uf

0.22U_0201_6.3V6-K

1

CD148

CD146

2

DRAM@

+0.6VS +0.6VS

0.22U_0201_6.3V6-K

1

CD259

CD252

@

@

2

DRAM@

DRAM@

DRAM@

0.22U_0201_6.3V6-K

1

CD142

2

0.22U_0201_6.3V6-K

1

CD169

2

0.22U_0201_6.3V6-K

1

CD212

@

2

0.22U_0201_6.3V6-K

1

CD139

2

0.22U_0201_6.3V6-K

1

2

DRAM@

DRAM@

DRAM@

1 2

RD122 39_0402 _5%DRAM@

1 2

RD123 39_0402 _5%DRAM@

1 2

RD148 39_0402 _5%DRAM@

1 2

RD149 39_0402 _5%DRAM@

1 2

RD124 39_0402 _5%DRAM@

1 2

RD125 39_0402 _5%DRAM@
RD126 39_0402 _5%DRAM@

1 2
1 2

RD127 39_0402 _5%DRAM@

1 2

RD128 39_0402 _5%DRAM@

1 2

RD129 39_0402 _5%DRAM@

1 2

RD130 39_0402 _5%DRAM@
RD131 39_0402 _5%DRAM@

1 2
1 2

RD132 39_0402 _5%DRAM@

1 2

RD133 39_0402 _5%DRAM@

1 2

RD134 39_0402 _5%DRAM@

1 2

RD135 39_0402 _5%DRAM@

1 2

RD138 39_0402 _5%DRAM@

1 2

RD139 39_0402 _5%DRAM@

1 2

RD140 39_0402 _5%DRAM@

RD144 39_0402 _5%DRAM@

1 2

1 2

RD147 39_0402 _5%DRAM@

1 2

RD145 39_0402 _5%DRAM@

1 2

RD141 39_0402 _5%DRAM@

1 2

RD142 39_0402 _5%DRAM@
RD143 39_0402 _5%DRAM@

1 2

1 2

RD146 39_0402 _5%DRAM@
RD275 39_0402 _5%DRAM@

1 2

1 2

RD86 1K_ 0402_ 1%DRA M@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD127

CD141

2

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD167

CD165

2

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD211

@

2

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

1

CD201

CD138

2

2

2

DRAM@

DRAM@

1

CD263
22P_04 02_50V 8-J

RF_NS@

2

0.22U_0201_6.3V6-K

CD152

0.22U_0201_6.3V6-K

CD172

+1.2V

0.22U_0201_6.3V6-K

CD245

1

CD264
22P_04 02_50V 8-J

RF_NS@

2

1

2

DRAM@

1

2

DRAM@

1

CD133
22P_04 02_50V 8-J

RF_NS@

2

1

2

DRAM@

+0.6VS

+1.2V

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD150

2

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD171

2

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

CD246

2

DRAM@

1

DRAM@

1 2

CD163 0.1 U_0402_ 10V7K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD158

CD143

CD137

2

2

DRAM@

DRAM@

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD166

CD168

CD175

2

2

DRAM@

DRAM@

1

CD153
22P_04 02_50V 8-J

RF_NS@

2

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

1

1

CD244

CC205

DRAM@

DRAM@

1

2

CD242

CD243

2

2

DRAM@

+2.5V

1

CD265
22P_04 02_50V 8-J

RF_NS@

2

180P_0402_50V8-J

DRAM@

DRAM@

DRAM@

+1.2V

0.22U_0201_6.3V6-K

1

2

0.22U_0201_6.3V6-K

1

2

0.22U_0201_6.3V6-K

1

2

Swap Table

Pin Name Net Name

DQ0

DDRB_DQ3

DQ1

DDRB_DQ6

DQ2

DDRB_DQ2

DQ3

DDRB_DQ0

DQ4

DDRB_DQ7

DQ5

DDRB_DQ5

DQ6

DDRB_DQ4

DQ7

DDRB_DQ1

DQS#0

DDRB_DQS#0

DQS0

DDRB_DQS0

UD1

DDRB_DQ9

DQ8

DDRB_DQ11

DQ9

DDRB_DQ12

DQ10

DDRB_DQ8

DQ11

DDRB_DQ15

DQ12

DDRB_DQ13

DQ13

DDRB_DQ14

DQ14

DDRB_DQ10

DQ15

DDRB_DQS#1

DQS#1

DDRB_DQS1

DQS1

UD1

DQ16

DDRB_DQ7

DQ17

DDRB_DQ3

DQ18

DDRB_DQ4

DQ19

DDRB_DQ0

DQ20

DDRB_DQ6

DQ21

DDRB_DQ5

DQ22

DDRB_DQ2

DQ23

DDRB_DQ1

DQS#2

DDRB_DQS#2

DQS2

DDRB_DQS2

UD2

DQ24

DDRB_DQ15

DQ25

DDRB_DQ11

DQ26

DDRB_DQ12

DQ27

DDRB_DQ8

DQ28

DDRB_DQ13

DQ29

DDRB_DQ9

DQ30

DDRB_DQ14

DQ31

DDRB_DQ10

DQS#3

DDRB_DQS#3

DQS3

DDRB_DQS3

UD2

DQ32

DDRB_DQ6

DQ33

DDRB_DQ7

DQ34

DDRB_DQ2

DQ35

DDRB_DQ1

DQ36

DDRB_DQ5

DQ37

DDRB_DQ3

DQ38

DDRB_DQ4

DQ39

DDRB_DQ0

DQS#4

DDRB_DQS#4

DQS4

DDRB_DQS4

UD3

DQ40

DDRB_DQ9

DQ41

DDRB_DQ15

DQ42

DDRB_DQ12

DQ43

DDRB_DQ14

DQ44

DDRB_DQ11

DQ45

DDRB_DQ13

DQ46

DDRB_DQ10

DQ47

DDRB_DQ8

DQS#5

DDRB_DQS#5

DQS5

DDRB_DQS5

UD3

DQ48

DDRB_DQ11

DQ49

DDRB_DQ13

DQ50

DDRB_DQ8

DQ51

DDRB_DQ14

DQ52

DDRB_DQ9

DQ53

DDRB_DQ15

DQ54

DDRB_DQ12

DQ55

DDRB_DQ10

DQS#6

DDRB_DQS#7

DQS6

DDRB_DQS7

UD4

DQ56

DDRB_DQ5

DQ57

DDRB_DQ1

DQ58

DDRB_DQ2

DQ59

DDRB_DQ0

DQ60

DDRB_DQ7

DQ61

DDRB_DQ3

DQ62

DDRB_DQ6

DQ63

DDRB_DQ4

DQS#7

DDRB_DQS#6

DQS7

DDRB_DQS6

UD4

5

4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

Title

DDRVI MD

DDRVI MD

DDRVI MD

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date : Sheet o f

Date : Sheet o f

Date : Sheet o f

Friday, March 23, 2018

Friday, March 23, 2018

Friday, March 23, 2018

1

330ARR

330ARR

330ARR

15 52

15 52

15 52

1.0

1.0

1.0