Lenovo IdeaPad 330-14IGM Schematic

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B

C

D

E

LCFC Confidential

330-IGM M/B EG431/EG532 Schematics Document

Intel Geminilake M-Processor with DDR4 + AMD LV2-R17M-M1-70 GPU

2 2

2018-03-02

REV:1.0

3 3

4 4

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/01/21

2014/01/21

2014/01/21

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

EG431/EG532

EG431/EG532

EG431/EG532

E

1 60

1 60

1 60

1.0

1.0

1.0

Vinafix.com

A

B

C

D

E

LCFC confidential

File Name : TURING 4D&5D
Board Number : NM-B661

PN : DA600013W00

1 1

2 2

3 3

AMD LV2-R17M-M1-70

AMD: Level2
Package: S3

Page 19~25

VRAM: 256*32
GDDR5*2: 2GB

Page 26

eDP Conn

Int. Camera

USB 2.0 Port6

Int. MIC Conn.

Page 28

SATA HDD

Page 42

RJ45 Conn.

Page 37

SD/MMC Conn.

Page 35

SPK Conn.

Page 34

HP&Mic Combo Conn.

Page 34

HDMI Conn.

Page 32

SATA Port0

Page 42

LAN Realtek

RTL8106E/RTL8107E

Page 36

PCIe Port 1~4

SATA Port1

PCIe Port4

Codec & C/R

Realtek RTS5119

USB2.0 Port5

Page 34

PCI-Express

4x Gen2

HDMI

eDP x2 Lane

SATA Gen3

SATA Gen1SATA ODD

PCIe 1x

USB2.0 x1

HD Audio

Geminilake-M

BGA-1090
24mm*25mm

TDP 6W

Page 4~15

I2C

EC
ITE IT8986E/BX-LQFP

Page 44

LPC BUS

Memory BUS (DDR4)
Single Channel

1.2V DDR4 2133 MT/s
(platform support up to 2400MT/s)

USB 3.0 1x
USB 2.0 1x

USB 2.0 1x

USB3.0 1x
USB2.0 1x Parade PS8713

USB2.0 1x

USB2.0 1x

USB2.0 1x

USB3.0 Redriver

Page 29

Touch Screen

Page 28

Fingerprint

Page 45

PCIe 1x

SPI ROM

Page 6

Int. Camera

Page 28

8MB

USB2.0 1x

FSPI BUS

TPM

Z32H320TC

Page 38

Reserve

DDR4-SO-DIMM

Page 17

UP TO 8G

Type-C IC

Realtek RTS5449

Page 29

Reserve

Reserve

Page 39

USB 2.0 Port4

Mirror Code

SPI Port

NGFF Card
WLAN&BT

PCIe Port5
USB 2.0 Port7

EC

USB 3.0 Conn

Page 31

USB 2.0 Conn

Page 31

Type-C Conn

Page 29

USB 3.0 Port1
USB 2.0 Port0

USB 2.0 Port3

Reserve

Touch Pad Int.KBD

Page 45 Page 45

4 4

A

B

Thermal Sensor
NCT7718W

Page 38

C

Reserve

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/01/21

2014/01/21

2014/01/21

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

EG431/EG532

EG431/EG532

EG431/EG532

E

2 60

2 60

2 60

1.0

1.0

1.0

Vinafix.com

Voltage Rails

A

( O --> Means ON

, X --> Means OFF )

Power Plane

V20B+

+3VALW

+3VL

State

1 1

S0

+5VALW

+5VL

O

S3

S5 S4/AC Only

S5 S4
Battery only

S5 S4
AC & Battery

don't exist

2 2

O
O

+3VALW_SOC
+1.24VALW
+1.8VALW

O O O

O X X

XX

+1.2V

O
O

OO O X
O

X
X

XX

X

SMBUS Control Table

SOURCE

EC_SMB_CK0
EC_SMB_DA0

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SMB_CLK
PCH_SMB_DATA

3 3

EC SM Bus0 address

Device

PMIC

EC

+3VL

EC

+3VL

EC

+3VS

PCH

+3VALW_SOC

0x68

VGA BATT SODIMM

X X X X X X X X

X

V

+3VGS

X

IT8986HE

V

V

V

+3VL

V

X

+3VS

X

X

EC SM Bus1 address

Device

Smart Battery 0x16

AddressAddress

WLAN
WiMAX

X

V

V V

+3VS +3VS

I2C4/I2C7 Bus address (Touch Pad)

Device Address

Slave
Descriptor

RCOMP RESISTOR REQUIREMENT

Memory
USB2

USB3/PCIe/SATA PCIE2_USB3_SATA3_RCOMP_P/N

4 4

SMBUS/GPIO/EMMC for all 1.8V
only and 1.8V mode operation of

1.8/3.3V CFIO interfaces

0x15
0x0001

PIN NAMEINTERFACE

MEM_CH0_RCOMP
MEM_CH1_RCOMP

PCIE_REF_CLK_RCOMPPCIe Refclk 56 +/-1%
EDP_RCOMP_P/NDP/eDP*/HDMI*

EMMC_RCOMP

A

B

+5VS
+3VS
+1.8VS
+1.05VS
+0.6VS
+CPU_CORE
+VNN

X
X

Thermal
Sensor

EC SM Bus2 address

Device

Thermal Sensor 0x98(reserve)

RC1
RC2
RC64
RC63
RC62
RC79
RC78
RC48

RC20

PCH

X X

V

X

+3VALW_PCH

VALUE(ohm)LOCATION

110 +/-1%
110 +/-1%
113 +/-1%USB2_RCOMP
100 +/-1%

100 +/-1%
150 +/-1%MDSI_RCOMPMDSI
150 +/-1%CNV_WT_RCOMPCNVi

200 +/-1%

B

X

STATE

Full ON

S0IX(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S0# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS/VTT Clock

USB Port Table

XHCI Port device

USB 3.0

USB 2.0

TP

Charger

Module

Port Port

0
1
0
1
2

3
4
5
6
7

PMIC

V

XXXX

X

X

X

V

X

X

X

X

PCH SM Bus address

Device AddressAddress

DDR SO-DIMM
Wlan

C

HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW

LOW

HIGHHIGH

HIGH

LOWLOWLOW

USB3.0

Type C(RSVD)
Type C( USB 2.0)(RSVD)

USB3.0 (2.0)

Touch Screen(RSVD)

USB2.0

Finger Print(RSVD)

CARD READER
CAMERA

BT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

0xA0
RsvdCharger 0x12

HIGH

HIGH

HIGH

HIGH

LOW

ON

ON

ON

ON

ON

ON

OFF

ON

ON

OFF

DDI PORT LIST

DDI0
DDI1

eDP

2013/08/08

2013/08/08

2013/08/08

D

ON ON

OFFON

OFF

OFF

OFF

OFF

OFF

OFF

Device

HDMI
NC
eDP

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

E

PCIE PORT LIST

Port Device

0
1
2
3
4
5

BIOS Device ID Map

dGPU

PCIe1(Func0):Root Port#3

LAN

PCIe0(Func0):Root Port#1

WLAN

PCIe0(Func1):Root Port#2

BOM Structure Table

EMC@ For EMC part
EMC_NS@ For EMC un-stuff part
EMC_15@
EMC_14@
EMC_USB@ EMC USB TVS part
1284_EMC@ 1284 LAN Transformer EMC part
CD@ Cost Down part

RF@ For RF part
RF_NS@ For RF un-stuff part
RF_PXNS@ For RF GPU un-stuff part

14@
15@

8106E@
8107E@

1284@
8400M@

PX@ Discrete GPU SKU part
TOPAZ@ TOPAZ dGPU SKU part

UMA@ UMA SKU ID part

TMSEN@ Thermal Sensor part
TMSEN_PX@ dGPU Thermal Sensor part
TMSEN_UMA@ UMA Thermal Sensor part

TPM@ TPM part
NUVOTON@ NOVOTON TPM part
NATIONZ@ NATIONZ TPM part

TS@
FP@ Finger Print part
KBL@ KB Backlight part

UART@ UART debug part
RTCRST@ Clear RTCRST# function part

ME@ ME part

HDMI@ HDMI Logo part

N4100@ GLK N4100 CPU part
N4000@
N5000@

M8G@
S8G@
H8G@
PCB@ MB PCB part
ODD@ ODD PCB part

2014/01/21

2014/01/21

2014/01/21

EMC 15" part
EMC 14" part

For 14" part
For 15" part

8106E LAN SKU part@
8107E LAN SKU part@
1284 LAN Transformer part
8400M LAN Transformer part

R16M-M1-30 dGPU SKU partEXO@

Touch Screen part

un-stuff part@

GLK N4000 CPU part
GLK N5000 CPU part

Micron 8GbX2 VRAM X76 SKUM8GX2@
Samsung 8GbX2 VRAM X76 SKUS8GX2@
Hynix 8GbX2 VRAM X76 SKUH8GX2@
Micron 8GbX2 VRAM
Samsung 8GbX2 VRAM
Hynix 8GbX2 VRAM

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

BTO ItemBOM Structure

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

E

CLK REQ

CLKREQ0

CLKREQ1
CLKREQ2

3 60

3 60

3 60

1.0

1.0

1.0

Vinafix.com

5

DDRA_DQ[63:0] 17
DDRA_DQS[7:0] 17
DDRA_DQS#[7:0] 17

4

3

2

1

DDRA_DQ40
DDRA_DQ41
DDRA_DQ42

D D

C C

DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31

UC1A

BJ36

MEM_CH0_DQ40

BK37

MEM_CH0_DQ41

BJ35

MEM_CH0_DQ42

BL36

MEM_CH0_DQ43

BJ39

MEM_CH0_DQ44

BL40

MEM_CH0_DQ45

BJ40

MEM_CH0_DQ46

BK41

MEM_CH0_DQ47

BA35

MEM_CH0_DQ32

AY33

MEM_CH0_DQ33

BA33

MEM_CH0_DQ34

AY35

MEM_CH0_DQ35

BA37

MEM_CH0_DQ36

AY37

MEM_CH0_DQ37

AY39

MEM_CH0_DQ38

BA39

MEM_CH0_DQ39

BL34

MEM_CH0_DQ56

BL30

MEM_CH0_DQ57

BJ29

MEM_CH0_DQ58

BK29

MEM_CH0_DQ59

BJ33

MEM_CH0_DQ60

BK33

MEM_CH0_DQ61

BJ34

MEM_CH0_DQ62

BJ30

MEM_CH0_DQ63

BD29

MEM_CH0_DQ48

BF29

MEM_CH0_DQ49

BH29

MEM_CH0_DQ50

BF33

MEM_CH0_DQ51

BC29

MEM_CH0_DQ52

BD33

MEM_CH0_DQ53

BF35

MEM_CH0_DQ54

BH35

MEM_CH0_DQ55

AR53

MEM_CH0_DQ0

AP55

MEM_CH0_DQ1

AP53

MEM_CH0_DQ2

AN54

MEM_CH0_DQ3

AU54

MEM_CH0_DQ4

AV53

MEM_CH0_DQ5

AV55

MEM_CH0_DQ6

AW53

MEM_CH0_DQ7

AU51

MEM_CH0_DQ8

AU48

MEM_CH0_DQ9

AU49

MEM_CH0_DQ10

BA46

MEM_CH0_DQ11

BA48

MEM_CH0_DQ12

BA49

MEM_CH0_DQ13

BA51

MEM_CH0_DQ14

AR51

MEM_CH0_DQ15

AY55

MEM_CH0_DQ16

BA54

MEM_CH0_DQ17

BA53

MEM_CH0_DQ18

AY53

MEM_CH0_DQ19

BC53

MEM_CH0_DQ20

BD55

MEM_CH0_DQ21

BE54

MEM_CH0_DQ22

BD53

MEM_CH0_DQ23

AN43

MEM_CH0_DQ24

AN44

MEM_CH0_DQ25

AR48

MEM_CH0_DQ26

AU41

MEM_CH0_DQ27

AU43

MEM_CH0_DQ28

AN41

MEM_CH0_DQ29

AN39

MEM_CH0_DQ30

AU44

MEM_CH0_DQ31

GEMINILAKE_FCBGA1090

@

DDR0

1 OF 13

DDR4_LP3_LP4DDR4_LP3_LP4

MEM_CH0_DQS0_P
MEM_CH0_DQS0_N

MEM_CH0_DQS1_P
MEM_CH0_DQS1_N

MEM_CH0_DQS2_P
MEM_CH0_DQS2_N

MEM_CH0_DQS3_P
MEM_CH0_DQS3_N

MEM_CH0_DQS4_P
MEM_CH0_DQS4_N

MEM_CH0_DQS5_P
MEM_CH0_DQS5_N

MEM_CH0_DQS6_P
MEM_CH0_DQS6_N

MEM_CH0_DQS7_P
MEM_CH0_DQS7_N

MEM_CH0_ODT1

MEM_CH0_CS1_N

MEM_CH0_ODT0

MEM_CH0_CS0_N

MEM_CH0_CKE1
MEM_CH0_CKE0

MEM_CH0_CLK0_P
MEM_CH0_CLK0_N

MEM_CH0_CLK1_P
MEM_CH0_CLK1_N

MEM_CH0_MA0
MEM_CH0_MA1

MEM_CH0_MA2
MEM_CH0_MA10
MEM_CH0_MA13
MEM_CH0_MA16

MEM_CH0_BA1

MEM_CH0_BA0

MEM_CH0_BG1

MEM_CH0_ACT_N

MEM_CH0_MA3

MEM_CH0_MA4

MEM_CH0_MA5

MEM_CH0_MA6

MEM_CH0_MA7

MEM_CH0_MA8

MEM_CH0_MA9
MEM_CH0_MA11
MEM_CH0_MA12
MEM_CH0_MA14
MEM_CH0_MA15

MEM_CH0_BG0

MEM_CH0_VREFDQ

MEM_CH0_VREFCA

NCTF1
NCTF2
NCTF3

NCTF4

AT53
AT55

AW49
AW48

BC54
BB53

AR41
AR43

AV37
AV35

BL38
BJ38

BF31
BD31

BJ32
BK31

BG54
BH54
BJ42
BF39
BK43

BL44
BD39
BJ43
BF54
BF55

BE49
BE51

BC49
BC48

BD45
BH50
BH47
BF45
BH43
BD41
BH51
BD43
BF43
BF41
BG52

BK45
BJ46
BJ44
BJ47
BJ45
BK47
BJ51
BJ52
BJ48
BJ50
BL50

TP_DDRA_VREFDQ

AY31
AV29

DDRA_DQS0
DDRA_DQS#0

DDRA_DQS1
DDRA_DQS#1

DDRA_DQS2
DDRA_DQS#2

DDRA_DQS3
DDRA_DQS#3

DDRA_DQS4
DDRA_DQS#4

DDRA_DQS5
DDRA_DQS#5

DDRA_DQS6
DDRA_DQS#6

DDRA_DQS7
DDRA_DQS#7

DDRA_CLK0
DDRA_CLK0#

DDRA_CLK1
DDRA_CLK1#

DDRA_ODT1 17
DDRA_CS1# 17

DDRA_ODT0 17
DDRA_CS0# 17
DDRA_CKE1 17
DDRA_CKE0 17

DDRA_CLK0 17
DDRA_CLK0# 17

DDRA_CLK1 17
DDRA_CLK1# 17

DDRA_MA0 17
DDRA_MA1 17
DDRA_MA2 17
DDRA_MA10 17
DDRA_MA13 17
DDRA_MA16_RAS# 17
DDRA_BS1# 17
DDRA_BS0# 17
DDRA_BG1 17
DDRA_ACT# 17
DDRA_MA3 17

DDRA_MA4 17
DDRA_MA5 17
DDRA_MA6 17
DDRA_MA7 17
DDRA_MA8 17
DDRA_MA9 17
DDRA_MA11 17
DDRA_MA12 17
DDRA_MA14_WE# 17
DDRA_MA15_CAS# 17
DDRA_BG0 17

1

TC208 @

DDRA_VREFCA 17

VREF_DQ NOT APPLICABLE FOR DDR4

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/03/26

2013/03/26

2013/03/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/01/21

2014/01/21

2014/01/21

Title

SOC (DDR4 CHA)

SOC (DDR4 CHA)

SOC (DDR4 CHA)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

1

of

4 60

4 60

4 60

1.0

1.0

1.0

Vinafix.com

5

4

3

2

1

UC1B

AY3

MEM_CH1_DQ40

BD3

MEM_CH1_DQ41

BD1

MEM_CH1_DQ42

BC3

MEM_CH1_DQ43

AY1

MEM_CH1_DQ44

BA3

MEM_CH1_DQ45

D D

C C

B B

BA2

MEM_CH1_DQ46

BE2

MEM_CH1_DQ47

AR8

MEM_CH1_DQ32

AN15

MEM_CH1_DQ33

AN17

MEM_CH1_DQ34

AU12

MEM_CH1_DQ35

AN12

MEM_CH1_DQ36

AN13

MEM_CH1_DQ37

AU13

MEM_CH1_DQ38

AU15

MEM_CH1_DQ39

AP3

MEM_CH1_DQ56

AU2

MEM_CH1_DQ57

AV3

MEM_CH1_DQ58

AW3

MEM_CH1_DQ59

AN2

MEM_CH1_DQ60

AP1

MEM_CH1_DQ61

AR3

MEM_CH1_DQ62

AV1

MEM_CH1_DQ63

AR5

MEM_CH1_DQ48

BA8

MEM_CH1_DQ49

AU7

MEM_CH1_DQ50

AU5

MEM_CH1_DQ51

BA5

MEM_CH1_DQ52

BA7

MEM_CH1_DQ53

AU8

MEM_CH1_DQ54

BA10

MEM_CH1_DQ55

BJ26

MEM_CH1_DQ0

BL26

MEM_CH1_DQ1

BJ27

MEM_CH1_DQ2

BK27

MEM_CH1_DQ3

BJ23

MEM_CH1_DQ4

BK23

MEM_CH1_DQ5

BJ22

MEM_CH1_DQ6

BL22

MEM_CH1_DQ7

BD27

MEM_CH1_DQ8

BF27

MEM_CH1_DQ9

BH27

MEM_CH1_DQ10

BC27

MEM_CH1_DQ11

BH21

MEM_CH1_DQ12

BF23

MEM_CH1_DQ13

BD23

MEM_CH1_DQ14

BF21

MEM_CH1_DQ15

BK19

MEM_CH1_DQ16

BJ20

MEM_CH1_DQ17

BL20

MEM_CH1_DQ18

BJ21

MEM_CH1_DQ19

BJ17

MEM_CH1_DQ20

BJ16

MEM_CH1_DQ21

BK15

MEM_CH1_DQ22

BL16

MEM_CH1_DQ23

BA21

MEM_CH1_DQ24

AY23

MEM_CH1_DQ25

BA23

MEM_CH1_DQ26

BA17

MEM_CH1_DQ27

AY21

MEM_CH1_DQ28

AY17

MEM_CH1_DQ29

AY19

MEM_CH1_DQ30

BA19

MEM_CH1_DQ31

GEMINILAKE_FCBGA1090

@

Follow CRB&PDG v1.2

DDR1

2 OF 13

DDR4_LP3_LP4DDR4_LP3_LP4

MEM_CH1_DQS0_P
MEM_CH1_DQS0_N

MEM_CH1_DQS1_P
MEM_CH1_DQS1_N

MEM_CH1_DQS2_P
MEM_CH1_DQS2_N

MEM_CH1_DQS3_P
MEM_CH1_DQS3_N

MEM_CH1_DQS4_P
MEM_CH1_DQS4_N

MEM_CH1_DQS5_P
MEM_CH1_DQS5_N

MEM_CH1_DQS6_P
MEM_CH1_DQS6_N

MEM_CH1_DQS7_P
MEM_CH1_DQS7_N

MEM_CH1_MA0
MEM_CH1_MA1
MEM_CH1_MA2

MEM_CH1_MA3
MEM_CH1_MA10
MEM_CH1_MA13
MEM_CH1_MA16

MEM_CH1_BA0
MEM_CH1_BA1

MEM_CH1_BG1

MEM_CH1_ACT_N

MEM_CH1_MA11
MEM_CH1_MA12
MEM_CH1_MA14
MEM_CH1_MA15

MEM_CH1_BG0

MEM_CH1_MA4

MEM_CH1_MA5

MEM_CH1_MA6

MEM_CH1_MA7

MEM_CH1_MA8

MEM_CH1_MA9

MEM_CH1_CLK0_P
MEM_CH1_CLK0_N

MEM_CH1_CLK1_P
MEM_CH1_CLK1_N

MEM_CH1_CS1_N

MEM_CH1_ODT1

MEM_CH1_CS0_N

MEM_CH1_ODT0
MEM_CH1_CKE0

MEM_CH1_CKE1

MEM_CH0_RCOMP

MEM_CH1_RESET_N

MEM_CH1_RCOMP

MEM_CH1_VREFCA
MEM_CH1_VREFDQ

MEM_CH0_RESET_N

NCTF7
NCTF8
NCTF5

NCTF6

BJ24
BK25

BD25
BF25

BL18
BJ18

AV19
AV21

AR13
AR15

BB3
BC2

AW7
AW8

AT1
AT3

BH9
BC13
BD11
BD13
BF11
BE5
BH5
BH6
BF13
BG4
BE7

BK11
BJ12
BK9
BJ11
BJ10
BJ4
BL6
BJ5
BJ9
BJ6
BJ8

BF17
BD17

BF15
BH15

BJ13
BL12
BF1
BF2
BC7

BH2
BC8
BG2
BK13
BJ14

AY29
BC15

AY27
AV27

AY25
BC43

DDRA_RCOMP
DDRB_DRAMRST#

DDRB_RCOMP

DDRA_DRAMRST#

1 2

RC1 110_0402_1%

1

TP53@

1 2

RC2 110_0402_1%

+1.2V

12

RC3
1K_0402_1%

DDRA_DRAMRST# DDRA_DRAMRST#_R

A A

5

4

1 2

RC4 0_0402_5%@

Different with APL CRB(1K damping resistor)

DDRA_DRAMRST#_R 17

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/03/26

2013/03/26

2013/03/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/01/21

2014/01/21

2014/01/21

Title

Title

Title

SOC (DDR3L CHB)

SOC (DDR3L CHB)

SOC (DDR3L CHB)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

1

5 60

5 60

5 60

1.0

1.0

1.0

Vinafix.com

5

GPIO_15915

D D

HDA_BITCLK_AUDIO34
HDA_SYNC_AUDIO34

HDA_SDIN0_GPIO_16815,34

HDA_SDOUT_AUDIO34
HDA_RST_AUDIO#34

For unused EMMC interface, refer PDG. NC for all signals, except the
EMMC_RCOMP, which requires PD termination. -------intel schematic check list

C C

Need double check if EMMC_RST#&EMMC_PWR_EN# signal can left NC

RC20 200_0402_1%

GPIO_16315
GPIO_16415

1 2

RC5 33_0402_5%

1 2

RC7 33_0402_5%

1 2

RC8 33_0402_5%

1 2

RC10 33_0402_5%@

GPIO_17215
GPIO_17415

GPIO_17515

12

HDA_BITCLK_AUDIO_R
HDA_SYNC_AUDIO_R

HDA_SDOUT_AUDIO_R
HDA_RST_AUDIO#_R

EMMC_RCOMP

UC1G

C26

AVS_I2S0_MCLK

B25

AVS_I2S0_BCLK

C25

AVS_I2S0_WS_SYNC

C24

AVS_I2S0_SDI

B23

AVS_I2S0_SDO

M23

AVS_I2S1_MCLK

L21

AVS_I2S1_BCLK

J21

AVS_I2S1_WS_SYNC

M21

AVS_I2S1_SDI

P23

AVS_I2S1_SDO

A22

AVS_HDA_BCLK

C23

AVS_HDA_WS_SYNC

B21

AVS_HDA_SDI

C22

AVS_HDA_SDO

C21

AVS_HDA_RST_N

B19

AVS_DMIC_CLK_A1

C20

AVS_DMIC_CLK_B1

C19

AVS_DMIC_DATA_1

C18

AVS_DMIC_CLK_AB2

A18

AVS_DMIC_DATA_2

J13

EMMC_CLK

L15

EMMC_RCLK

M19

EMMC_D0

H19

EMMC_D1

J19

EMMC_D2

P17

EMMC_D3

P19

EMMC_D4

J15

EMMC_D5

L17

EMMC_D6

M17

EMMC_D7

M13

EMMC_CMD

U44

EMMC_RST_N

G51

EMMC_PWR_EN_N

L13

EMMC_RCOMP

GEMINILAKE_FCBGA1090

@

4

AUDIO-AVS

eMMC

7 OF 13

RSVD

LPC/eSPI

FAST_SPI

3

L29

RSVD6

M29

RSVD5

P29

RSVD7

M27

RSVD8

P27

RSVD9

L27

RSVD3

L25

RSVD4

P25

RSVD2

L23

RSVD10

J25

RSVD1

C37

LPC_CLKOUT0

A38

LPC_CLKOUT1

A34

LPC_AD0

C34

LPC_AD1

B35

LPC_AD2

C35

LPC_AD3

LPC_FRAME_N

LPC_SERIRQ

FST_SPI_CLK

FST_SPI_IO2
FST_SPI_IO3

C33
B33
B37

B29
B31

C30
A30
C29

C31
C32

LPC_CLKRUN_N

FST_SPI_MOSI_IO0
FST_SPI_MISO_IO1

FST_SPI_CS0_N
FST_SPI_CS1_N

SPI ROM

2

SD Card I/F, Intel have changed to RSVD

LPC BUS I/O Voltage is controlled by Hardware Strap(GPIO_83)
Need BIOS soft strap to 3.3V

LPC Can Set 3.3/1.8 by Soft Strap
Need discuss with EC/BIOS if can set LPC to 1.8V
TPM is 3.3V level, if change to 1.8V, can't support TPM

CLK_PCI_EC_R
CLK_PCI_TPM_R

LPC_AD0_R
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R

LPC_CLKRUN#_R
LPC_FRAME#_R
LPC_SERIRQ_R

PCH_SPI_CLK_R
PCH_SPI_D0_R

PCH_SPI_D1_R
PCH_SPI_D2_R
PCH_SPI_D3_R

PCH_SPI_CS0#_R

EC_SPI_CLK_R44

EC_SPI_CS0#_R44

EC_SPI_D0_R44

EC_SPI_D1_R44

RC11 33_0402_5%
RC9 33_0402_5%TPM@

RC12 20_0402_5%
RC13 20_0402_5%
RC14 20_0402_5%
RC15 20_0402_5%
RC16 0_0402_5%@
RC17 0_0402_5%TPM@
RC18 0_0402_5%@
RC19 0_0402_5%@

12
12

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PCH_SPI_CLK_R

PCH_SPI_CS0#_R

PCH_SPI_D0_R

PCH_SPI_D1_R

Near place RC210&RC41; RC22&42; RC23&RC43; RC24&RC44

PCH_SPI_D2_R
PCH_SPI_D3_R

CLK_PCI_EC 44
CLK_PCI_TPM 38

LPC_AD0 38,44
LPC_AD1 38,44
LPC_AD2 38,44
LPC_AD3 38,44
LPC_CLKRUN#_EC 44
LPC_CLKRUN# 38
LPC_FRAME# 38,44
LPC_SERIRQ 38,44

RC21 33_0402_5%

1 2

RC41 0_0402_5%@

1 2

RC22 0_0402_5%@

1 2

RC42 0_0402_5%@

1 2

RC23 0_0402_5%@

1 2

RC43 0_0402_5%@

1 2

RC24 0_0402_5%@

1 2

RC44 0_0402_5%@

1 2

RC25 0_0402_5%@

1 2

RC26 0_0402_5%@

LPC_CLKRUN#_R

12

1

RC6 10K_0402_5%@

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_D0

PCH_SPI_D1

PCH_SPI_D2
PCH_SPI_D3

+3VALW_SOC

12

Place all damping resisor near SPI ROM for minimum SPI Stub

Ball Name Signal Name

FST_SPI_CS0_N PCH_SPI_CS0#

+1.8VALW

1 2

RC31 0_0402_5%@

B B

+VCC_SPI

1 2

RC32 100K_0402_5%@

1 2

RC33 3.3K_0402_5%

1 2

RC34 3.3K_0402_5%

Follow CRB: set WP# and HOLD# PU

+VCC_SPI

PCH_SPI_CS0#
PCH_SPI_D2

PCH_SPI_D3

FST_SPI_MOSI_IO0 PCH_SPI_D0

FST_SPI_IO3
FST_SPI_CLK

PCH_SPI_CS0#
PCH_SPI_D1 PCH_SPI_D3
PCH_SPI_D2

PCH_SPI_D1FST_SPI_MISO_IO1
PCH_SPI_D2FST_SPI_IO2

UC2

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FWSSIQ_SO8

/HOLDor/RESET(IO3)

1.8V SPI ROM

I/O Voltage Default Term Buffer Type

1.8V Native HSMV

DI(IO0)

1.8V

1.8V

1.8V

1.8VPCH_SPI_D3

1.8VPCH_SPI_CLK

8

VCC

7

PCH_SPI_CLK

6

CLK

PCH_SPI_D0

5

Native HSMV
Native HSMV
Native HSMV
Native HSMV
Native HSMV

+VCC_SPI

50mA

1

CC258

0.1U_0201_6.3V6-K

2

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/03/26

2013/03/26

2013/03/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/01/21

2014/01/21

2014/01/21

Title

SOC (Audio,eMMC,LPC,SPI)

SOC (Audio,eMMC,LPC,SPI)

SOC (Audio,eMMC,LPC,SPI)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

1

6 60

6 60

6 60

1.0

1.0

1.0

Vinafix.com

5

+1.8VALW

D D

+3VALW_SOC

SMBus Alert is open drain, and it has 20 KΩ internal pull-up.

C C

RPC21

1 4
2 3

2.2K_0404_4P2R_5%

@

1 2

RC45 1K_0402_5%@

Need Confirm PU is Stuff or Not, CRB v1.2 Reserve

DBG_I2C3_SCL
DBG_I2C3_SDA

PCH_SMB_ALERT#

cnvi disable guide follow PDG chapter 17.5

RC267 10K_0402_5%@

for use debug

Reserve For TouchPad

PCH_SMB_CLK_GPIO_17715

Need check CNVi disable guide
Can't find in PDG/SCH CKL

CLKIN_XTAL_LCP suggest reserve a pull down.

1 2

XTAL_CLKREQ_GPIO_19615

CNVI_BRI_DT_GPIO_19115
CNVI_BRI_RSP_GPIO_19215

CNVI_RGI_DT_GPIO_19315
CNVI_RGI_RSP_GPIO_19415
CNVI_RF_RST#_GPIO_19515

RC48 150_0402_1%

Intel recommends Max routing length shorter than 1000mils,
spacing with other signals larger than 15mils.

CLKIN_XTAL_LCP

1 2

PCH_SMB_ALERT#
PCH_SMB_CLK_GPIO_177
PCH_SMB_DATA

DBG_I2C3_SCL
DBG_I2C3_SDA

TP_I2C4_SCL
TP_I2C4_SDA

TP_I2C7_SCL
TP_I2C7_SDA

CNVI_WT_RCOMP

4

U49
U51

U46
U48

AA39
AA41

R44
R43

R49
R51

C50
A50

C48
C47

B47
C46

A26
B27
C27

H29
H31

M31
P31

D29
F29

F35
D35

J35

H35
L31

J31
J29

F19

H17

J17
D19
D17
F17

F33

UC1F

SIO_I2C0_SCL
SIO_I2C0_SDA

SIO_I2C1_SCL
SIO_I2C1_SDA

SIO_I2C2_SCL
SIO_I2C2_SDA

SIO_I2C3_SCL
SIO_I2C3_SDA

SIO_I2C4_SCL
SIO_I2C4_SDA

SIO_I2C5_SCL
SIO_I2C5_SDA

SIO_I2C6_SCL
SIO_I2C6_SDA

SIO_I2C7_SCL
SIO_I2C7_SDA

SMB_ALERT_N
SMB_CLK
SMB_DATA

CNV_WGR_CLK_P
CNV_WGR_CLK_N

CNV_WGR_D0_P
CNV_WGR_D0_N

CNV_WGR_D1_P
CNV_WGR_D1_N

CNV_WT_CLK_P
CNV_WT_CLK_N

CNV_WT_D0_P
CNV_WT_D0_N

CNV_WT_D1_P
CNV_WT_D1_N

CLKIN_XTAL_LCP
XTAL_CLKREQ

CNV_BRI_DT
CNV_BRI_RSP
CNV_RGI_DT
CNV_RGI_RSP
CNV_RF_RESET_N

CNV_WT_RCOMP

GEMINILAKE_FCBGA1090

@

LPSS_I2C

LPSS SMBus

3

LPSS_SPI

LPSS_UART

CNVI

6 OF 13

SIO_SPI_0_CLK
SIO_SPI_0_TXD

SIO_SPI_0_RXD
SIO_SPI_0_FS0
SIO_SPI_0_FS1

SIO_SPI_2_CLK
SIO_SPI_2_TXD

SIO_SPI_2_RXD
SIO_SPI_2_FS0
SIO_SPI_2_FS1
SIO_SPI_2_FS2

SIO_UART0_TXD

SIO_UART0_RXD
SIO_UART0_RTS_N
SIO_UART0_CTS_N

SIO_UART2_TXD

SIO_UART2_RXD
SIO_UART2_RTS_N
SIO_UART2_CTS_N

2

M39
J37

L39
L37
J39

M37
M33

P35
P33
P37
L35

N54
P53
N53
M55

L54
M53
K53
L53

GPIO_79 15
GPIO_83 15
GPIO_80 15

GPIO_81 15
GPIO_84 15
GPIO_89 15
GPIO_85 15

GPIO_86 15
GPIO_87 15

GPIO_61 15
GPIO_62 15

SOC_UART_TXD_GPIO_65 15,39
SOC_UART_RXD 39
GPIO_66 15

Only UART2 supports debug functionality

1

+1.8VALW

14

23

RP16

1K_0404_4P2R_5%

@

TP_I2C4_SDA TP_I2C4_SDA_M

TP_I2C4_SCL

QC1B

DMN5L06DWK-7_SOT363-6

+1.8VALW

QC1A

S1

DMN5L06DWK-7_SOT363-6

@

G2

G

D2S2

S

D

DMN5L06DWK-7[Vgs(th)max=1.0V]

SCH GLK request MOSFET output capacitance less than 10pF

@

I2C7 I/O Voltage is 3.3V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

@

S

12

RC50

0_0402_5%

@

1

@

2

CC260

.1U_0402_10V6-K

@

SMB_CLK_S3
SMB_DATA_S3

+3VS+3VALW

12

RC52

@

2

@

1

CC261

14

23

RPC4

2.2K_0404_4P2R_5%

0_0402_5%

RC56 10K_0402_5%@

1

@

2

CC262

.1U_0402_10V6-K

SMB_DATA_S3

TP_I2C4_SDA_R

10U_0603_6.3V6M

4

12

SMB_CLK_S3 17,39

SMB_DATA_S3 17,39

TP_I2C4_SDA_R 45
TP_I2C4_SCL_R 45

+1.8VALW

+1.8VALW

12

RC51
0_0402_5%

@

UC3

1

TP_I2C4_SDA
TP_I2C4_SCL TP_I2C4_SCL_R

B B

1

2

CC259

@

SMBus

14

23

RPC3

2.2K_0404_4P2R_5%

@

PCH_SMB_CLK_GPIO_177 SMB_CLK_S3

A A

PCH_SMB_DATA

PCH_SMB_CLK_GPIO_177
PCH_SMB_DATA

SMB_CLK&SMB_DATA is OD(PDG v1.2 P309), Reserve MOS LS, Keep +3VS PU, CRB w/o PU, need BIOS check if have internal PU
I/O Voltage is controlled by Hardware Strap(GPIO_163: PD) & Soft Strap 3.3(default)(SMIP v0.82 P84)

SMBUS I/O Voltage is controlled by Hardware Strap(GPIO_163)

L2N7002KDW1T1G_SOT363-6

5

VCCA

2

A1

3

A2
GND4OE

TXS0102DQER_X2SON8_1X1P4

@

.1U_0402_10V6-K

+3VS +3VS+3VALW_SOC

2

6 1

D

@

QC3A

L2N7002KDW1T1G_SOT363-6

1 2

RC60 0_0402_5%@

1 2

RC61 0_0402_5%@

8

VCCB

7

B1

6

B2

5

G

S

5

G

3 4

D

QC3B

+3VALW +3VS

RPC1

2.2K_0404_4P2R_5%

1 4

G1

SGD

2 3

D1

2

2013/03/26

2013/03/26

2013/03/26

TP_I2C4_SCL_M TP_I2C4_SCL_R

TP_I2C7_SDA

RC58 0_0402_5%@

TP_I2C7_SCL

RC59 0_0402_5%@

Need Confirm I2C7 PU Power Rail with Intel
Maybe Can Connect to TP_I2C4_SDA_R

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

L2N7002KDW1T1G_SOT363-6

1 2
1 2

2

6 1

D

2014/01/21

2014/01/21

2014/01/21

L2N7002KDW1T1G_SOT363-6

G

QC2A

S

TP_I2C4_SDA_M
TP_I2C4_SCL_M

+3VS

14

23

RPC2

5

G

QC2B

3 4

S

D

12

RC550_0402_5% @

The I2C signals are open drain, and it has internal pull-up.
A 1 k!" 5% for external pull-up resistor is recommended.

12

RC570_0402_5% @

Reserve Touch Pad I2C LS(MOS and IC) Lewis 2016/10/21

Title

Title

Title

SOC (I2C,SMBus,CNVi,UART)

SOC (I2C,SMBus,CNVi,UART)

SOC (I2C,SMBus,CNVi,UART)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

2.2K_0404_4P2R_5%

TP_I2C4_SDA_R

EG431/EG532

EG431/EG532

EG431/EG532

1

7 60

7 60

7 60

1.0

1.0

1.0

Vinafix.com

5

RC62 56_0402_1%

1 2

CLK_PCIE_GPU20
CLK_PCIE_GPU#20

CLK_PCIE_LAN36
CLK_PCIE_LAN#36

CLK_PCIE_WLAN39
CLK_PCIE_WLAN#39

PCIE_PTX_C_GRX_P0
PCIE_PTX_C_GRX_N0

PCIE_PTX_C_GRX_P1
PCIE_PTX_C_GRX_N1

PCIE_PTX_C_GRX_P2
PCIE_PTX_C_GRX_N2

dGPU

PCIE_PTX_C_GRX_P020
PCIE_PTX_C_GRX_N020

PCIE_PRX_GTX_P020
PCIE_PRX_GTX_N020

PCIE_PTX_C_GRX_P120
PCIE_PTX_C_GRX_N120

PCIE_PRX_GTX_P120
PCIE_PRX_GTX_N120

PCIE_PTX_C_GRX_P220
PCIE_PTX_C_GRX_N220

PCIE_PRX_GTX_P220
PCIE_PRX_GTX_N220

D D

C C

CC263 0.1U_0201_6.3V6-K
CC264 0.1U_0201_6.3V6-K

CC267 0.1U_0201_6.3V6-K
CC268 0.1U_0201_6.3V6-K

CC271 0.1U_0201_6.3V6-K
CC272 0.1U_0201_6.3V6-K

HDD

1 2
1 2

1 2
1 2

1 2
1 2

SATA_PTX_DRX_P042
SATA_PTX_DRX_N042

SATA_PRX_DTX_P042
SATA_PRX_DTX_N042

PX@
PX@

PX@
PX@

PX@
PX@

PCIE Configuration

Port

P0
P1
P2
P3
P4
P5

CLOCK REQUEST

B B

+1.8V_3.3V_PU

Remove level shift, due to LAN chip page already have level shift

LAN_CLKREQ#_Q

Both RTL8111GUL&RTL8111H CLKREQ# are OD,Can pull high to 1.8V

LAN_CLKREQ# need BIOS soft strap to 3.3V

WLAN_CLKREQ#_Q

L2N7002KDW1T1G_SOT363-6

A A

Device

Config Name:Dev:Fun:DID:Root Port

X4

dGPU

PCIe1(Func0):19:0:0x31D8:2

X1

LAN

X1

RPC6

10K_0804_8P4R_5%

L2N7002KDW1T1G_SOT363-6

PCIe0(Func0):20:0:0x31D6:0
PCIe0(Func1):20:1:0x31D7:1WLAN

WLAN_CLKREQ#_Q

45

PCIE_CLKREQ_3#

36
27

LAN_CLKREQ#_Q

18

RC70 0_0402_5%@

1 2

+3VS

RC72

@

10K_0402_5%

1 2

34

D

QC4B

5

G

S

61

D

@

QC4A

G

S

@

Need Check
CLKREQ can be set 1.8V/3.3V by soft strap
CLKREQ0/2/4 default 3.3V
CLKREQ1 default 1.8V

PCIE_CLKREQ[3:0]_N I/O Voltage is controlled by Soft Straps

LAN_CLKREQ# 36

2

WLAN_CLKREQ# 39

GPU do NOT use CLKREQ#, Set level shifter as NC
GPU_CLKREQ# control by BOM structure(Follow CG412)

4

PCIE_REF_CLK_RCOMP

CLK_PCIE_GPU
CLK_PCIE_GPU#

CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_PCIE_WLAN
CLK_PCIE_WLAN#

PCIE_PTX_GRX_P0
PCIE_PTX_GRX_N0

PCIE_PRX_GTX_P0
PCIE_PRX_GTX_N0

PCIE_PTX_GRX_P1
PCIE_PTX_GRX_N1

PCIE_PRX_GTX_P1
PCIE_PRX_GTX_N1

PCIE_PTX_GRX_P2
PCIE_PTX_GRX_N2

PCIE_PRX_GTX_P2
PCIE_PRX_GTX_N2

GPU_CLKREQ#_Q
LAN_CLKREQ#_Q
WLAN_CLKREQ#_Q
PCIE_CLKREQ_3#

PCIE_WAKE0#
PCIE_WAKE1#
PCIE_WAKE2#
PCIE_WAKE3#

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_P0
SATA_PRX_DTX_N0

GPU_CLKREQ#_Q

L2N7002KDW1T1G_SOT363-6

L2N7002KDW1T1G_SOT363-6

GPU_CLKREQ#_Q
GPU_CLKREQ#_Q

UC1D

L10

PCIE_REF_CLK_RCOMP

R12

PCIE_CLKOUT0P

R10

PCIE_CLKOUT0N

N7

PCIE_CLKOUT1P

N5

PCIE_CLKOUT1N

R7

PCIE_CLKOUT2P

R5

PCIE_CLKOUT2N

N8

PCIE_CLKOUT3P

N10

PCIE_CLKOUT3N

E2

PCIE_P0_TXP

F2

PCIE_P0_TXN

G7

PCIE_P0_RXP

H6

PCIE_P0_RXN

A7

PCIE_P1_TXP

C7

PCIE_P1_TXN

D4

PCIE_P1_RXP

E5

PCIE_P1_RXN

C9

PCIE_P2_TXP

B9

PCIE_P2_TXN

E7

PCIE_P2_RXP

F6

PCIE_P2_RXN

A46

PCIE_CLKREQ0_N

C45

PCIE_CLKREQ1_N

B45

PCIE_CLKREQ2_N

C44

PCIE_CLKREQ3_N

F47

PCIE_WAKE0_N

D47

PCIE_WAKE1_N

F45

PCIE_WAKE2_N

D50

PCIE_WAKE3_N

J3

SATA_P0_TXP

J2

SATA_P0_TXN

J7

SATA_P0_RXP

J5

SATA_P0_RXN

GEMINILAKE_FCBGA1090

@

34

D

QC5B

G

S

@

+3VS

RC71
10K_0402_5%

@

1 2

5

61

D

QC5A

S

@

GPU_CLKREQ#

RC76 10K_0402_5%UMA@
RC77 2K_0402_5%PX@

1 2

3

SATA_PTX_DRX_P1

USB3_P0_TXP
USB3_P0_TXN

USB3_P0_RXP
USB3_P0_RXN

USB3_P1_TXP
USB3_P1_TXN

USB3_P1_RXP
USB3_P1_RXN

USB2_DP0
USB2_DN0

USB2_DP1
USB2_DN1

USB2_DP2
USB2_DN2

USB2_DP3
USB2_DN3

USB2_DP4
USB2_DN4

USB2_DP5
USB2_DN5

USB2_DP6
USB2_DN6

USB2_DP7
USB2_DN7

USB2_RCOMP

USB2_DUALROLE

USB2_VBUS_SNS

USB2_OC0_N
USB2_OC1_N

H1

SATA_PTX_DRX_N1

H2

SATA_PRX_DTX_P1

H4

SATA_PRX_DTX_N1

G5

USB30_TX_P0

B15

USB30_TX_N0

C15

USB30_RX_P0

F15

USB30_RX_N0

D15

USB30_TX_P1

C14

USB30_TX_N1

A14

USB30_RX_P1

J11

USB30_RX_N1

H11

PCIE_PTX_GRX_P3 PCIE_PTX_C_GRX_P3

C10

PCIE_PTX_GRX_N3

A10

PCIE_PRX_GTX_P3

H9

PCIE_PRX_GTX_N3

F9

PCIE_PTX_DRX_P4 PCIE_PTX_C_DRX_P4

C11

PCIE_PTX_DRX_N4

B11

PCIE_PRX_DTX_P4

D11

PCIE_PRX_DTX_N4

F11

PCIE_PTX_DRX_P5

B13

PCIE_PTX_DRX_N5

C13

PCIE_PRX_DTX_P5

F13

PCIE_PRX_DTX_N5

D13

PCIE_USB3_SATA_RCOMP_DN

C5

PCIE_USB3_SATA_RCOMP_DP

C6

AA10

NC1

AA8

NC2

W13

NC3

W12

NC4

U15

NC5

USB20_P0

U7

USB20_N0

U5

USB20_P1

N2

USB20_N1

N3

USB20_P2

L2

USB20_N2

L3

USB20_P3

R13

USB20_N3

R15

USB20_P4

M1

USB20_N4

M3

USB20_P5

R2

USB20_N5

R3

USB20_P6

P1

USB20_N6

P3

USB20_P7

U8

USB20_N7

U10

USB2_RCOMP

U12

USB_OTG_ID

V1

USB_VBUSSNS

V3

USB_OC0#_GPIO_44

U54

USB_OC1#_GPIO_45

U53

SATA_P1_USB3_P5_TXP

SATA/USB3

PCIe

USB3

PCIe/USB3

SSIC

SATA

USB2

4 OF 13

SATA_P1_USB3_P5_TXN
SATA_P1_USB3_P5_RXP

SATA_P1_USB3_P5_RXN

PCIE_P3_USB3_P4_TXP
PCIE_P3_USB3_P4_TXN

PCIE_P3_USB3_P4_RXP
PCIE_P3_USB3_P4_RXN

PCIE_P4_USB3_P3_TXP
PCIE_P4_USB3_P3_TXN

PCIE_P4_USB3_P3_RXP
PCIE_P4_USB3_P3_RXN

PCIE_P5_USB3_P2_TXP
PCIE_P5_USB3_P2_TXN

PCIE_P5_USB3_P2_RXP
PCIE_P5_USB3_P2_RXN

PCIE2_USB3_SATA3_RCOMP_N
PCIE2_USB3_SATA3_RCOMP_P

LAN WAKE

+1.8V_3.3V_PU

PCIE_WAKE[3:0]_N I/O Voltage is controlled by Soft Straps

RPC7

PCIE_WAKE3#

18

PCIE_WAKE2#

27

PCIE_WAKE1#

36

PCIE_WAKE0#

45

10K_0804_8P4R_5%

PCIE_WAKE 1.8/3.3 Can be Set by Soft Straps
Need Confirm if Can Use PCIE_WAKE0 1.8/3.3(Default) for LAN_WAKE
or SW set PCIE_WAKE1# to 3.3V

+1.8VALW

2

GPU_CLKREQ# 21

G

+3VS

RC75

10K_0402_5%

@

1 2

+1.8V_3.3V_PU

12

PCIE_WAKE1# PCIE_WAKE#

QC6

LSI1012XT1G_SC-89-3

PCIE_WAKE1# PCIE_WAKE#

WAKE0/2/3 default 3.3V
WAKE1 default 1.8V
WAKE1 need BIOS soft strap to 3.3V

+3VALW

RC73

@

10K_0402_5%

1 2

123

@

PJQ1900[Vgs(th)<1.0V], 01/15

RC252 0_0402_5%@

1 2

2

SATA_PTX_DRX_P1 42
SATA_PTX_DRX_N1 42

SATA_PRX_DTX_P1 42
SATA_PRX_DTX_N1 42

USB30_TX_P0 31
USB30_TX_N0 31

USB30_RX_P0 31
USB30_RX_N0 31

USB30_TX_P1 29
USB30_TX_N1 29

USB30_RX_P1 29
USB30_RX_N1 29

CC265 0.1U_0201_6.3V6-K

1 2

CC266 0.1U_0201_6.3V6-K

1 2

CC269 0.1U_0201_6.3V6-K

1 2

CC270 0.1U_0201_6.3V6-K

1 2

CC273 0.1U_0201_6.3V6-K

1 2

CC274 0.1U_0201_6.3V6-K

1 2

USB20_P0 29
USB20_N0 29

USB20_P1 31
USB20_N1 31

USB20_P2 28
USB20_N2 28

USB20_P3 31
USB20_N3 31

USB20_P4 45
USB20_N4 45

USB20_P5 34
USB20_N5 34

USB20_P6 28
USB20_N6 28

USB20_P7 39
USB20_N7 39

RC64 113_0402_1%

1 2

Intel recommends to add a VSS shield at least 4Mmils
wide to shield between USB2_RCOMP and adjacent I/O.

USB_OC0#_GPIO_44 15
USB_OC1#_GPIO_45 15,31

ODD

USB (3.0)

Type C

PX@

PX@

PCIE_PTX_C_GRX_N3

PCIE_PTX_C_DRX_N4

PCIE_PTX_C_DRX_P5
PCIE_PTX_C_DRX_N5

Type C USB 2.0
USB 2.0( for standard USB 3.0 port)
Touch Screen

USB2.0(for standard USB2.0 port)

Finger Print
CARD READER
CAMERA

BT

USB OCP

PCIE_WAKE# 36,39,44

1

PCIE_PTX_C_GRX_P3 20
PCIE_PTX_C_GRX_N3 20

PCIE_PRX_GTX_P3 20
PCIE_PRX_GTX_N3 20

PCIE_PTX_C_DRX_P4 36
PCIE_PTX_C_DRX_N4 36

PCIE_PRX_DTX_P4 36
PCIE_PRX_DTX_N4 36

PCIE_PTX_C_DRX_P5 39
PCIE_PTX_C_DRX_N5 39

PCIE_PRX_DTX_P5 39
PCIE_PRX_DTX_N5 39

dGPU

LAN

WLAN

PCIE_USB3_SATA_RCOMP_DP

PCIE_USB3_SATA_RCOMP_DN

Intel recommends to add a VSS shield at least 4Mmils
wide to shield between PCIE2_USB3_SATA3_RCOMP_P /
PCIE2_USB3_SATA3_RCOMP_N trace and adjacent I/O.

12

RC63
100_0402_1%

USB DUAL ROLE

USB_OTG_ID

USB_VBUSSNS

+3VALW

10K_0402_5%

USB_OC0#_GPIO_44

USB_OC0#_GPIO_44 TYPE_C_OCP#

Reserve TYPE_C_OCP# to CPU USB_OC0# Lewis

Reserve LS for USB OCP Lewis 2016/10/13

34

D

QC7B

5

G

S

L2N7002KDW1T1G_SOT363-6

@

RC74 0_0402_5%@

1 2

61

D

S

@

1 2

RC65 10K_0402_5%@

12

RC66 0_0402_5%@

1 2

RC67 10K_0402_5%@

12

RC68 0_0402_5%@

Follow PDG v1.2 P195 USB2.0 Disabling and Termination Guidelines
When the platform does not use the USB2_OTG_ID, USB2_VBUS_SNS, and
USB2_OC0/1_N pins:
USB2_OTG_ID and USB2_OC[x]_N pins can be left unconnected.
USB2_VBUS_SNS needs to be connected to GND.

USB_OC0#_GPIO_44
USB_OC1#_GPIO_45

RC69

@

QC7A

G

L2N7002KDW1T1G_SOT363-6

1 2

Follow CRB un-stuff OC# PU resistor

TYPE_C_OCP#

2

RPC5

2 3
1 4

10K_0404_4P2R_5%

@

TYPE_C_OCP# 29

+1.8VALW

+1.8VALW

+1.8VALW

WLAN_CLKREQ#_Q WLAN_CLKREQ#

RC253 0_0402_5%@

1 2

CLKREQ can be set 1.8V/3.3V by soft strap

5

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/03/26

2013/03/26

2013/03/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/01/21

2014/01/21

2014/01/21

Title

SOC (PCIE&GPIO&SPI)

SOC (PCIE&GPIO&SPI)

SOC (PCIE&GPIO&SPI)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

1

8 60

8 60

8 60

1.0

1.0

1.0

Vinafix.com

5

4

3

2

1

HDMI D2

HDMI D1

HDMI D0

D D

+1.8V_3.3V_PU

+3VS

12

12

RC282

0_0402_5% @

RC281
0_0402_5%

@

RPC8

DDPB_CLK

23

DDPB_DATA

14

10K_0404_4P2R_5%

DDC Signals Can Be Set to 1.8/3.3(Default) by Soft Straps

HDMI CLK

eDP

C C

eDP RCOMP is used for DDI0/DDI1 ports of HDMI/DP
as well as the eDP interface. DDI0_RCOMP removed for GLK

EDP_RCOMP_P

12

RC79
100_0402_1%

EDP_RCOMP_N

HDMI_TX2+32
HDMI_TX2-32

HDMI_TX1+32
HDMI_TX1-32

HDMI_TX0+32
HDMI_TX0-32

HDMI_CLK+32
HDMI_CLK-32

DDC Signals Can Be Set to 1.8/3.3(Default) by Soft Straps

HDMI_HPD#32

DDPB_CLK32
DDPB_DATA32

CPU_EDP_TX0+28
CPU_EDP_TX0-28

CPU_EDP_TX1+28
CPU_EDP_TX1-28

CPU_EDP_AUX28
CPU_EDP_AUX#28

HDMI_TX2+
HDMI_TX2-

HDMI_TX1+
HDMI_TX1-

HDMI_TX0+
HDMI_TX0-

HDMI_CLK+
HDMI_CLK-

DDPB_CLK
DDPB_DATA

CPU_EDP_TX0+
CPU_EDP_TX0-

CPU_EDP_TX1+
CPU_EDP_TX1-

CPU_EDP_AUX
CPU_EDP_AUX#

EDP_HPD#
PCH_BKLT_CTRL_Q

PCH_ENBKL
PCH_LCD_VDDEN_Q

EDP_RCOMP_P
EDP_RCOMP_N

UC1C

AH1

DDI0_TXP_0

AH3

DDI0_TXN_0

AE2

DDI0_TXP_1

AE3

DDI0_TXN_1

AJ2

DDI0_TXP_2

AJ3

DDI0_TXN_2

AG2

DDI0_TXP_3

AG3

DDI0_TXN_3

AC12

DDI0_AUXP

AC10

DDI0_AUXN

C39

DDI0_HPD

B43

DDI0_DDC_SCL

C43

DDI0_DDC_SDA

AA2

DDI1_TXP_0

AA3

DDI1_TXN_0

Y3

DDI1_TXP_1

Y1

DDI1_TXN_1

AD1

DDI1_TXP_2

AD3

DDI1_TXN_2

AC2

DDI1_TXP_3

AC3

DDI1_TXN_3

AC7

DDI1_AUXP

AC5

DDI1_AUXN

C42

DDI1_DDC_SCL

A42

DDI1_DDC_SDA

C38

DDI1_HPD

AE12

EDP_TXP_0

AE13

EDP_TXN_0

AC15

EDP_TXP_1

AC17

EDP_TXN_1

AE10

EDP_TXP_2

AE8

EDP_TXN_2

AE5

EDP_TXP_3

AE7

EDP_TXN_3

W17

EDP_AUXP

W15

EDP_AUXN

B39

EDP_HPD

B41

PNL0_BKLCTL

C40

PNL0_BKLTEN

C41

PNL0_VDDEN

AA5

EDP_RCOMP_P

AA7

EDP_RCOMP_N

GEMINILAKE_FCBGA1090

@

eDP/DDI_A

DDI0/DDI_B

DDI1/DDI_C

3 OF 13

AL2

MDSI_A_CLKP

AM3

MDSI_A_CLKN

AG13

MDSI_C_CLKP

AG12

MDSI_C_CLKN

AN5

MDSI_A_DP_0

AN7

MDSI_A_DN_0

AJ15

MDSI_A_DP_1

AJ17

MDSI

MDSI_A_DN_1
MDSI_A_DP_2

MDSI_A_DN_2
MDSI_A_DP_3

MDSI_A_DN_3
MDSI_C_DP_0

MDSI_C_DN_0

MDSI_C_DP_1

MDSI_C_DN_1

MDSI_C_DP_2

MDSI_C_DN_2

MDSI_C_DP_3

MDSI_C_DN_3

MIPI_I2C_SCL
MIPI_I2C_SDA

MDSI_C_TE
MDSI_A_TE

MDSI_RCOMP

AJ7
AJ5

AJ10
AJ12

AG15
AG17

AG8
AG10

AG7
AG5

AE15
AE17

R53
R54

T53
T55

MDSI_RCOMP

AL5

Reference to VSS, recommend to add a VSS shieldat
at least 12 mils wide placed between RCOMP and
adjacent I/O

GPIO_43 15
GPIO_42 15

1 2

RC78 150_0402_1%

DDI PORT LIST

Port

DDI0
DDI1
EDP

Device

HDMI

eDP

HPD Net

HDMI_HPD#

N/AN/A

EDP_HPD#

HPD Pin

C39
C38
B39

EDP_HPD

B B

A A

+1.8V_3.3V_PU

Follow CRB v1.2, PDG v1.2 Use 10K PU

EDP_HPD# can set 1.8(default)/3.3 by soft strap

RC80

1 2

100K_0402_5%

EDP_HPD#

13

D

QC8

2

G

S

L2N7002KWT1G_SOT323-3

EDP_HPD# CPU_EDP_HPD

1 2

RC82 0_0402_5%@

12

RC81

CPU_EDP_HPD 28

100K_0402_5%

EDP_HPD# need BIOS soft strap to 3.3V

5

4

PNL0_BKLCTL/PNL0_BKLTEN/PNL0_VDDEN Can be Set 1.8V/3.3V by Soft Strap

@

1 4

2 3

PCH_BKLT_CTRL_Q

2

@

6

D1

G1

S1

QC9A

1

PJT138K_SOT363-6

+3VS+3VALW +3VS+3VALW

RPC9
10K_0404_4P2R_5%

5

@

3

D2

G2

S2

QC9B

4

PJT138K_SOT363-6

PCH_EDP_PWM

PCH_LCD_VDDEN_Q

PJT138K[Vgs(th)<1.5V]

PNL0_BKLCTL default 1.8V
PNL0_BKLTEN default 1.8V
PNL0_VDDEN default 1.8V

PCH_ENBKL can direct connect to EC for costdown

Reserve 0ohm directly connect to PCH_EDP_PWM for setting 3.3V by soft straps

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/03/26

2013/03/26

2013/03/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

RPC10
10K_0404_4P2R_5%

@

1 4

2 3

3

5

G2

6

D1

2

G1

S1

QC10A

1

PJT138K_SOT363-6@

QC10B

4

PJT138K_SOT363-6@

PJT138K[Vgs(th)<1.5V]

PCH_LCD_VDDEN_Q

PCH_LCD_VDDEN_Q VOH min is ???, need check 1.8V DC Specification
SY6288C20 VIH min is 1.35V, do NOT use level shift
(Follow BMWC1)

PCH_ENBKL

PCH_BKLT_CTRL_Q PCH_EDP_PWM

1 2

RC83 0_0402_5%@

1.8V DC Specification :VOH=1.35V;VOL=0.45V

RC84 0_0402_5%@

PCH_ENBKL 28

1 2

D2

S2

PCH_ENVDD

PCH_ENVDD

GPIO Name

PNL0_VDDEN
PNL0_BKLTEN
PNL0_BKLTCTL

I/O Voltage

3.3V/1.8V

3.3V/1.8V

3.3V/1.8V

PCH_ENVDD 28

PCH_EDP_PWM 28

PCH_BKLT_CTRL_Q need BIOS soft strap to 3.3V

Title

Title

2014/01/21

2014/01/21

2014/01/21

Title

SOC (DDI,EDP,HDMI,MDSI)

SOC (DDI,EDP,HDMI,MDSI)

SOC (DDI,EDP,HDMI,MDSI)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

1

Default Term Buffer Type

CMOS

20K PD

CMOS

20K PD

CMOS

20K PD

9 60

9 60

9 60

1.0

1.0

1.0

Vinafix.com

5

+3VALW_SOC

Intel suggest PM_PLTRST# pu up to +3VALW,CRB PM_PLTRST# reserve pu up

RC85

@

RC86

1 2

RC88 100K_0402_5%@

1 2

RC90 100K_0402_5%

PM_PLTRST# & PM_RSTBTN# & SUSPWRDNACK is 3.3V level
set by GPIO_168 or Soft Stap?
SUSPWRDNACK Follow CRB v1.2, Reserve 100K PU to +3VALW
CRB PM_BATLOW# Reserve 100K PU to +3VALW

RC91 100K_0402_5%@

1 2

RC92 10K_0402_5%@

Check if need reserve SUS_CLK PD(CRB/PDG/CKL/EDS w/o)

D D

+1.2VALW

1 2

RC96 0_0402_5%@
RC97 49.9_0402_1%@1 2

+1.2VALW

1 2

RC98 0_0402_5%@

1 2

RC99 49.9_0402_1%@

intel reply OK for NC but reserve pull up to be safe

Follow CRB v1.2, need check with Intel

C C

PM_PLTRST#

2

PM_PLTRST#

10K_0402_5%

12

PM_RSTBTN#

10K_0402_5%

SUSPWRDNACK_R

12

PM_BATLOW#

intel reply 3.3V level set by GPIO168

PM_PLTRST#

12

PM_SUSCLK

DEBUG_PORT_A0

DEBUG_PORT_A1

RPC11
10K_0404_4P2R_5%

1 4

2 3

@

5

G2

6

D1

G1

S1

QC11A

1

PJT138K_SOT363-6@

PM_RSTBTN# follow CRB use 10k pull up resistor;shcematic check list show
use a 1k pull up resistor to 3P3A

Need confirm with PMIC if need connect S0IX

EC feedback no need this function

Follow I+A, need check with EC

+3VS+3VALW

PLT_RST#

3

2

D2

CC376

EMC@

220P_0201_25V7-K

1

S2

QC11B

4

PJT138K_SOT363-6@

PLT_RST# 20,36,38,39,44

2

CC375

1

@

0.1u_0201_10V6K

PJT138[Vgs(th)<1.5V]

PM_PLTRST# PLT_RST#

RC108 0_0402_5%@1 2

PM_PLTRST# by GPIO_168 hard strap

RC374 0_0402_5%@

13

D

QC37

S

+5VALW_PG_GATE

5

G

1 2

2

G

+1.05VS

RC260 84.5_0402_1%@

RC111 169_0402_1%@1 2
RC113 68_0402_5%@

RC273

L2N7002KWT1G_SOT323-3

D

12

61

CPU_SVID disable can NC---INTEL

1 2
1 2

Follow LPDD4+PMIC CRB

SYS_PWROK_R

RC280 0_0402_5%@
RC279 0_0402_5%@

RC274

1 2

100K_0402_5%

100K_0402_5%

@

RC271 0_0402_5%@1 2

QC27A

2

1 2

RC272 0_0402_5%@

G

S

L2N7002KDW1T1G_SOT363-6

CPU_SVID_CLK
CPU_SVID_DAT
CPU_SVID_ALRT#

1 2
1 2

+3VALW_PG 54
+5VALW_PG 54

SVID Disable

RSMRST# sequence control circuit

B B

EC_RSMRST#_R

0_0402_5%

RC276

1 2

@

34

D

S

QC27B

L2N7002KDW1T1G_SOT363-6

+3VL
+3VALW

4

PMC_I2C_SCL
PMC_I2C_SDA

PM_PLTRST#
PBTN_OUT#_R
PM_SLP_S0#_R
PM_SLP_S3#_R
PM_SLP_S4#_R
SUSPWRDNACK_R
PM_BATLOW#
PM_RSTBTN#
PM_SUSCLK
SUS_STAT#

1

@

TP64

CPU_SVID_CLK
CPU_SVID_DAT
CPU_SVID_ALRT#

DEBUG_PORT_A0
DEBUG_PORT_A1

PM_SUSCLK

SUSPWRDNACK_R

UC1H

R46

PMC_I2C_SCL

R48

PMC_I2C_SDA

L48

PMC_SPI_CLK

N48

PMC_SPI_FS0

N44

PMC_SPI_FS1

L49

PMC_SPI_FS2

L51

PMC_SPI_RXD

N49

PMC_SPI_TXD

D54

PMU_PLTRST_N

E54

PMU_PWRBTN_N

C52

PMU_SLP_S0_N

D51

PMU_SLP_S3_N

J49

PMU_SLP_S4_N

F54

SUSPWRDNACK

J48

PMU_BATLOW_N

C51

PMU_RSTBTN_N

G49

PMU_SUSCLK

E52

SUS_STAT_N

F55

SVID0_CLK

G53

SVID0_DATA

G54

SVID0_ALERT_N

D1

DEBUG_PORT_A0

D2

DEBUG_PORT_A1

A54

NC6

C54

NC7

GEMINILAKE_FCBGA1090

@

Connect SUSCLK to NGFF Conn.
Connect SUSCLK to EC in CRB

Change LBSS138[Vgs(th)<1.5V] to PJQ1900[Vgs(th)<0.9V]

+1.8VALW

12

RC100

2.2K_0402_5%

2

@

QC12

1

3

@

LSI1012XT1G_SC-89-3

1 2

RC105 0_0402_5%@

PM_SUSCLK is 3.3V level set by GPIO_168 or Soft Strap

1 2

RC254 0_0402_5%@

+3VALW

1 2

SUSPWRDNACK by GPIO_168 hard strap

PMC

PMU

SVID

Misc

RC101
10K_0402_5%

@

RTC

Thermal

Spare

8 OF 13

SUSCLK 39

SUSPWRDNACK 44

3

OSC_CLK_OUT0

B17

OSCIN

OSCOUT

RTC_X1
RTC_X2

INTRUDER

SKTOCC_N

NC8

NC9
NC10
NC11

NC12
NC13

NC14
NC15
NC16
NC17
NC18
NC19
NC20

OSC_CLK_OUT1

C17

XTAL19_IN

U2

XTAL19_OUT

T1

RTC_X1

D23

RTC_X2

F23

BVCCRTC_EXTPAD

J23

RTC_INTRUDER

H25

SYS_PWROK_R

D25
F27

RTC_TEST#

F25

RTC_RST#

D27

H_THERMTRIP#_R

J53

H_PROCHOT#

J54
AG43
H53
AG44
H55

A4
BH1

CPU_SKTPCC#

A53
F37
BL2
BL3
BL53
C2
C3
R41

1 2

RC106 0_0402_5%@

OSC_CLK_OUT_0
OSC_CLK_OUT_1

iCLK

VCC_RTC_EXTPAD

SOC_PWROK

RSM_RST_N

RTC_TEST_N

RTC_RST_N

THERMTRIP_N

PROCHOT_N

PBTN_OUT#_R

PBTN_OUT# is 3.3V level set by GPIO_168

PMU_BATLOW_N,PMU_PLTRST_N,PMU_PWRBTN_N,
PMU_RSTBTN_N,PMU_SLP_S0_N,PMU_SLP_S3_N,
PMU_SLP_S4_N, PMU_SUSCLK,SUSCLK[1/2],SUS_STAT_N,SUSPWRDNACK,
SOC_PWROKset by GPIO168

2

TP61 @1

1

TP62 @

1 2

CC275 0.1u_0201_10V6K

RTC_TEST# 44
RTC_RST# 44

1 2

RC95 0_0402_5%@

H_PROCHOT# 44

1

TP65 @

Follow CRB v1.2 left as TP

+1.8V_3.3V_PU

RC102
10K_0402_5%

@

1 2

10K_0404_4P2R_5%

PM_SLP_S3#_R
PM_SLP_S4#_R

PM_SLP_S3#,PM_SLP_S4# is 3.3V level set by GPIO_168

PBTN_OUT# 44

H_THERMTRIP#_REC_RSMRST#_R

Add 10K PU for THERMTRIP#(20K Internal PU, 10K may cost down)

H_PROCHOT#

H_THERMTRIP# 44,57

+1.8V_3.3V_PU

RPC12

@

1 4

2 3

PM_SLP_S0#_R

RC93 10K_0402_5%1 2

1 2

RC94 1K_0402_5%

THERMTRIP_N signals is 1.8V tolerant.

PM_SLP_S4#_R

RC371 0_0402_5%@

PM_SLP_S3#_R

RC372 0_0402_5%@

RC104 0_0402_5%@1 2

1 2

RC107 0_0402_5%@

+1.8V_3.3V_PU

RC261
10K_0402_5%

@

1 2

1 2

RC262 0_0402_5%@

Reserve for PMIC

1 2
1 2

1

+1.8VALW

PM_SLP_S3# 44
PM_SLP_S4# 44

SYSON 44,55,57
SUSP# 44,46,54,57

PM_SLP_S0# 44

PM_SLP_S0#_R by GPIO_168 hard strap

PMIC I2C

PMC_I2C_SCL

PMC_I2C_SDA

+1.8VALW

14

23

RPC23

2.2K_0404_4P2R_5%

@

QC26A
PJT138K_SOT363-6

@

PMC_I2C_SCL

RC256 0_0402_5%@

PMC_I2C_SDA

RC255 0_0402_5%@

CRB connect I2C to PMIC directly

+1.8VALW

2

G1
D1 6S11

1 2
1 2

G2 5
D2 3

4

S2

QC26B
PJT138K_SOT363-6

@

+3VALW

14

PMIC_I2C_SCL
PMIC_I2C_SDA

23

RPC22

2.2K_0404_4P2R_5%

@

PMIC_I2C_SCL

PMIC_I2C_SDA

PMIC_I2C_SCL 57

PMIC_I2C_SDA 57

SYS_PWROK_R

1 2

RC110 1K_0402_1%

SYS_PWROK_R connector EC, EC

RC269 0_0402_5%@

RC114

1 2

100K_0402_5%

1 2

Follow Intel request to add 100Kohm PD to avoid this leakage.

EC_RSMRST#_R

CC276

EMC@

RC109 1K_0402_1%1 2

12

2

RC112

1

0.01U_0201_25V6-K

RSM_RST_N is 3.3V

1 2

RC375 0_0402_5%@

100K_0402_5%

Follow SCH CKL add PD resistor, delete PU for EC is Push&Pull

CC278 0.01U_0201_25V6-K

EMC@

DC2

12

LRB751V-40T1G_SOD323-2

DC1

12

LRB751V-40T1G_SOD323-2

SYS_PWROK is 3.3V

SYS_PWROK_EC 44

12

SYS_PWROK 44,57

EC_RSMRST# 44

ALW_PGOOD 44,57

32.768kHz CRYSTAL--EPSON SJ10000IX00

1 2

RC119 10M_0402_5%

YC1

1 2

32.768KHZ_9PF_X1A0001410002

1

CC281
10P_0402_50V8J

2

1. Space 15MIL

2. No trace under crystal

A A

3. Place on oppsosit side of MCP for temp influence

4. EDS request X'TAL ESR=50Kohm; +/-20ppm; X1,X2 pin capacitance=15pF

RTC_X1_R

RTC_X2_R

1

CC282
9P_0402_50V8-B

2

Need Check ESR and CL with Intel

Intel reply ESR max 50k

5

1 2

RC116 0_0402_5%@

1 2

RC120 0_0402_5%@

RTC_X1

RTC_X2

RTCRST#/SRTCRST#

RTC_TEST#

RTC_RST#

4

1U_0402_6.3V6K

CC279

1

12

JCMOS1
SHORT PADS

@

2

JCMOS1

Place under Bottom Big Door

1 2

RC118 20K_0402_1%

1 2

RC123 20K_0402_1%

1U_0402_6.3V6K

1

CC280

2

RTCRST#

Space 15Mil

RTC_INTRUDER

Follow CRB v1.2 & PDG v1.2 use 330K PU Resistor

1 2

RC124 330K_0402_5%

3

VCCRTC

VCCRTC

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

19.2MHz CRYSTAL--TXC SJ10000LN00

RC121 200K_0402_5%

1

1

19.2MHZ_12PF_7V19200001
CC283
15P_0201_50V8-J

2

1. Space 15MIL

2. No trace under crystal

3. Place on oppsosit side of MCP for temp influence

4. PDG&EDS request X'TAL Max ESR=80ohm; +/-30ppm; Typical CL=12pF; Max PD=100uW

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

2013/08/08

2013/08/08

2013/08/08

Deciphered Date

2

1 2

YC2

OSC1
NC12OSC2

XTAL19_IN_R XTAL19_IN

XTAL19_OUT_R

4

NC2

3

1

CC284
15P_0201_50V8-J

2

Title

Title

2014/01/21

2014/01/21

2014/01/21

Title

SOC (RTC&RCOMP&JTAG)

SOC (RTC&RCOMP&JTAG)

SOC (RTC&RCOMP&JTAG)

Size

Size

Size

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

RC117 0_0402_5%@

1 2

RC122 0_0402_5%@

Document Number Rev

Document Number Rev

Document Number Rev

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

XTAL19_OUT

EG431/EG532

EG431/EG532

EG431/EG532

1

10 60

10 60

10 60

1.0

1.0

1.0

Vinafix.com

5

+1.8VALW

+1.8VALW

D D

PDG v1.2 P385:JTAGX is Unused Pin in GLK leave as No connect

1 2

RC125 51_0402_5%@

1 2

RC126 51_0402_5%@

1 2

RC127 150_0402_5%@

1 2

RC128 51_0402_5%@

1 2

RC131 51_0402_5%@

Need confirm with Intel if need stuff

intel reply can NC

1 2

RC129 150_0402_5%@

1 2

RC130 51_0402_5%@

PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TRST#

PCH_JTAG_PRDY#

AH53
AM53
AJ54
AL53
AL54
AK53

AH55
AJ53

4

UC1E

JTAGX
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

JTAG_PRDY_N
JTAG_PREQ_N

3

DBG_PTI_CLK0

AG53

DBG_PTI_DATA0

JTAG

ITP

GPIO

GPIO_8

GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16

GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25

GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34

GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41

GPIO_105
GPIO_134
GPIO_135
GPIO_136
GPIO_137
GPIO_138
GPIO_139
GPIO_140
GPIO_141
GPIO_142
GPIO_143
GPIO_144
GPIO_145
GPIO_146
GPIO_210
GPIO_212
GPIO_213
GPIO_214

AG54
AE54
AE53
AD55
AD53
AC54
AC53
AB53

AA49
AC48
AC46
AE51
AE49
AC51
AC49
AA51
AA46

AE41
AE39
AE46
AE44
AC41
AC39
AC44
AC43
AA44

AA54
AA53
Y55
Y53
W54
W53
V53

L46
H45
H47
L43
M43
H37
H43
J43
D43
F43
H41
F39
L41
F41
H27
U43
U41
U39

DBG_PTI_DATA1
DBG_PTI_DATA2
DBG_PTI_DATA3
DBG_PTI_DATA4
DBG_PTI_DATA5
DBG_PTI_DATA6
DBG_PTI_DATA7

SOC_CS_WAKE
TP_INT#_GPIO_18
PMIC_IRQ#_R
SOC_CODEC_IRQ
CNVI_MFUART2_RXD
CNVI_MFUART2_TXD
CNVI_GNSS_PA_BLANKING

GPIO_28
SOC_KBRST#

SOC_RUNTIME_SCI#
SOC_WAKE_SCI#

GLK_IERR#
SOC_EXTSMI#

SOC_ACIN
PXS_PWREN#_SOC

PXS_RST#_SOC
SATA_GP0
SATA_GP1
SATA_DEVSLP0
SATA_DEVSLP1
SATA_LED#
VGA_PWRGD_SOC

TP_INT#_GPIO_145
PXS_PWREN_GPIO_146
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3

2

1

@

TP72

1

@

TP66

1

@

TP67

1

@

TP73

1

@

TP68

1

@

TP69

1

@

TP74

1

@

TP70

1

@

TP71

1

Need Check

follow CRB

TC205 @

1

Need Check

follow CRB

TC204 @

1

Connect to CNVi WiFi though 33ohm

TC206 @

1

Connect to CNVi WiFi though 33ohm

TC207 @

1

Connect to CNVi WiFi though 33ohm

TC209 @

GPIO_27 15
GPIO_28 15

PCH_BEEP 34

1 2

RC132 1K_0402_5%@

Follow CRB v1.2, Need Confirm with Intel PU stuff or not

GPIO_105 can set 1.8V/3.3V(default) by soft strap
Follow CRB v1.2

1 2

Follow CRB v1.2

R9430 41.2K_0402_1%

1 2

RC270 10K_0402_5%

1 2

RC268 10K_0402_5%

1 2

RC134 8.2K_0402_5%

+1.8VALW

intel feedback it can be no connector.

+1.8VALW

100K_0402_5%

RC133

1 2

1.8/3.3(default) set by Soft straps
Need Confirm PU Power Rail

GPIO_146 need BIOS soft strp to 3.3V

Follow CRB v1.2, 1.8(Default)/3.3 Set by Soft Straps,
Need Confirm with Intel PU stuff or not

+3VALW_SOC

GPIO_142 default 3.3V

+3VALW_SOC

Intel suggest follow CRB

GPIO_140/GPIO_141 are OD Pin

1.8/3.3(default) set by Soft straps
Need Confirm PU or Not and PU Power Rail

1

GEMINILAKE_FCBGA1090

C C

10K_0404_4P2R_5%

TP_INT#

34

D

S

L2N7002KDW1T1G_SOT363-6

RC135 0_0402_5%@

TP_INT# IS Output, PU at Touch Pad Conn Side
Follow CRB Connect to GPIO_18

TP_INT#_GPIO_18
TP_INT#_GPIO_145

B B

GPIO_145
0 = PAD VCCIO is 3.3V
1 = PAD VCCIO is 1.8V (default)
GPIO_18=1.8V

GPIO_145 need BIOS soft strp to 3.3V

PXS_PWREN#_SOC

GPIO_134 Can be Set 3.3(default)/1.8 by Soft Straps[SMIP v0.82 P81], Maybe Can Change LBSS138 to L2N7002

VGA_GATE#44

A A

PXS_PWREN#_SOC need BIOS soft strp to 3.3V

+1.8VALW

RPC16

1 4

2 3

QC13B

5

G

61

D

S

L2N7002KDW1T1G_SOT363-6

1 2

1 2

RC278 0_0402_5%@

1 2

RC277 0_0402_5%@

RC143
10K_0402_5%

PX@

1 2

13

D

2

L2N7002KWT1G_SOT323-3

G

QC17

S

PX@

1 2

RC147 0_0402_5%

PX@

.1U_0402_10V6-K

+3VS

QC13A

2

PCH_TP_INT# 45

G

PCH_TP_INT#TP_INT#

TP_INT#

1 2

RC373 0_0402_5%@

2

G

1

CC285

PX@

@

2

5

RC144
100K_0402_5%

@

1 2

13

D

L2N7002KWT1G_SOT323-3
QC18

S

PCH_BT_OFF#

GPIO_28 PCH_BT_OFF#

PXS_PWREN_GPIO_146

PXS_PWREN 56,58,59

+1.8VALW

1 4

2 3

6

D1

2

G1

S1

QC14A

1

PJT138K_SOT363-6@

1 2

RC136 0_0402_5%@

Reserve BT_OFF# from PCH, EC connect to WLAN

PXS_RST#_SOC

@

1 2

GPIO_134
GPIO_137 20K PD

@

+3VS

RPC13
10K_0404_4P2R_5%

@

RC146
10K_0402_5%

GPIO_137 Can be Set 3.3(default)/1.8 by Soft Straps[SMIP v0.82 P80], Reserve MOS LS

Signal NameBall Name

PXS_PWREN#_SOC
PXS_RST#_SOC

BT_OFF# 39,44

3

D2

5

G2

S2

QC14B

4

PJT138K_SOT363-6@

+3VALW +3VS+3VS

RPC17
10K_0404_4P2R_5%

@

1 4

2 3

3

D2

5

G2

S2

6

QC19B

4

PJT138K_SOT363-6

D1

2

G1

PXS_RST#_SOC PXS_RST#

@

S1

QC19A

1

PJT138K_SOT363-6

@

1 2

RC149 0_0402_5%PX@

I/O Voltage

1.8/3.3(Default)

1.8/3.3(Default) HSHV

4

SOC_RUNTIME_SCI#

If EC_SCI#_Q default term is PU, EC is OD for EC_SCI#, can use 0ohm short

SOC_WAKE_SCI#

RC145
100K_0402_5%

@

1 2

Buffer TypeDefault Term

5 OF 13

+1.8VALW +3VL_EC

RPC14

10K_0404_4P2R_5%

34

D

QC15B

5

G

S

@

L2N7002KDW1T1G_SOT363-6

+1.8VALW

RC137
1K_0402_5%

1 2

1 2

RC138 0_0402_5%@

+1.8VALW

RC141
1K_0402_5%

@

1 2

1 2

RC142 0_0402_5%@

VGA_PWRGD_SOC

PXS_RST# 20

HSHV20K PD

@

1 4

2 3

61

D

QC15A

2

EC_SCI# 44

G

S

@

L2N7002KDW1T1G_SOT363-6

EC_SCI#SOC_RUNTIME_SCI#

Reserve for MS-Windows RS1

EC_WAKE_SCI# 44

+1.8VALW +3VALW

RPC18

10K_0404_4P2R_5%

34

D

S

@

L2N7002KDW1T1G_SOT363-6

VGA_PWRGD_SOC VR_VGA_PWRGD

1.8/3.3(default) set by Soft straps, Reserve MOS LS

VGA_PWRGD_SOC
VR_VGA_PWRGD

QC20B

5

G

RC148 0_0402_5%PX@

RC150 2K_0402_5%UMA@
RC151 100K_0402_5%@

3

1 4

2 3

61

D

S

L2N7002KDW1T1G_SOT363-6

1 2

1 2
1 2

@

QC20A

2

VR_VGA_PWRGD 20,56 KBRST# 44

G

@

+1.8VALW +3VL_EC

RPC15

10K_0404_4P2R_5%

SOC_EXTSMI#

34

D

QC16B

S

@

L2N7002KDW1T1G_SOT363-6

+1.8VALW

RC139
10K_0402_5%

1 2

SOC_EXTSMI# EC_SMI#

RC140 0_0402_5%@

If SOC_EXTSMI# default term is PU
EC is OD for EC_SMI#, can use 0ohm short

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

G

1 2

Issued Date

Issued Date

Issued Date

5

L2N7002KDW1T1G_SOT363-6

@

1 4

2 3

61

D

QC16A

EC_SMI#

2

G

S

@

+1.8VALW +3VL_EC

RPC20

10K_0404_4P2R_5%

SOC_KBRST#

34

D

QC22B

5

G

S

@

L2N7002KDW1T1G_SOT363-6

+1.8VALW

RC239
1K_0402_5%

1 2

SOC_KBRST#

RC240 0_0402_5%@

If KBRST#_Q default term is PU
EC is OD for KBRST#, can use 0ohm short

2013/08/08

2013/08/08

2013/08/08

2

EC_SMI# 44

@

1 4

2 3

61

D

QC22A

2

G

S

@

L2N7002KDW1T1G_SOT363-6

intel feedback pick any general 1.8V GPIO
in table EDS 2-28

1 2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

intel feedback AC_PRESENT can pick any general GPIO

SOC_ACIN

RC243
10K_0402_5%

@

1 2

SOC_ACIN

RC241 0_0402_5%@

+1.8VALW

@

1 2

GPIO_105 by GPIO_168 hard strap

+1.8VALW

RC258
100K_0402_5%

1 2

PMIC_IRQ#_R

RC258 follow RVP2 LPDDR4 CRB design

KBRST#

2014/01/21

2014/01/21

2014/01/21

QC25

LSI1012XT1G_SC-89-3

1 2

RC257 0_0402_5%@

BOARD ID

intel feedback BOARD ID can pick any general GPIO

Title

Title

Title

SOC (GPIO,JTAG,ITP)

SOC (GPIO,JTAG,ITP)

SOC (GPIO,JTAG,ITP)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

RC242

2.2K_0402_5%

@

1 2

QC24

LSI1012XT1G_SC-89-3

Change LBSS138[Vgs(th)<1.5V] to PJQ1900[Vgs(th)<0.9V]

13

D

QC23

2

G

S

L2N7002KWT1G_SOT323-3

AC_PRESENT

+3VALW

RC259
10K_0402_5%

@

1 2

123

@

123

@

AC_PRESENT 44

PMIC_IRQ# 57

AC_PRESENT

ACIN# 44

+1.8VALW

1 2

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3

ID0

ID2 ID3

ID1

0
1 GPU SKU

RSVD

0
1 15" Panel

EG431/EG532

EG431/EG532

EG431/EG532

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

1

1 2

RC244 2.2K_0402_5%PX@

RC245 2.2K_0402_5%15@

1 2

1 2

RC248 2.2K_0402_5%14@

RC249 2.2K_0402_5%UMA@

Description

UMA SKU

RSVD

14" Panel

11 60

11 60

11 60

1 2

1 2

RC247 2.2K_0402_5%@

RC246 2.2K_0402_5%@

1 2

1 2

RC250 2.2K_0402_5%@

RC251 2.2K_0402_5%@

1.0

1.0

1.0

Vinafix.com

5

+1.2V

IccMAX=3.0A

1

2

CC286

D D

Place near UC1.AP36,AT36,AP38,
AT38,AT35,AT18,AP18,AP21,AT20,
AT21,BA43,BA41,BA31,BA13,BA15,BA25

+1.05VS +VCCIOA

RC153 0_0805_5%@1 2

+1.8VALW

C C

B B

RC158 0_0805_5%@

IccMAX=2.0A

RC160 0_0603_5%@

RC162 0_0805_5%@

1

2

CC287

1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

1 2

1 2

2 x 0402_1uF; 4 x 0201_0.1uF
[6 x 0805_22uF on Power Side]

1

1

1

2

2

2

CC288

CC289

CC290

EMC@

EMC@

EMC@

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

Note:Place CAPs Near MLCCNote:Place CAPs Back of CPU

0.1U_0201_6.3V6-K

IccMAX=1.19A

1

1

2

2

CC301

CC302

22U_0603_6.3V6-M

22U_0603_6.3V6-M

@

+VCC1P8

IccMAX=0.4A

1

2

CC307

22U_0603_6.3V6-M

+VDD2_1P2_MPHY+1.2VALW

IccMAX=0.55A

1

1

2

2

CC364

CC365

22U_0603_6.3V6-M

22U_0603_6.3V6-M

+VDD2_1P2_AUD_ISH

IccMAX=0.22A

1

2

CC291

EMC@

0.1U_0201_6.3V6-K

2 x 0603_22uF; 3 x 0402_1uF; 1 x 0402_2.2uF

1

1

1

2

2

2

CC304

CC303

CC305

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

1 x 0603_22uF; 5 x 0402_1uF

1

2

CC308

1U_0402_6.3V6K

CRB: 2 x 0805_47uF; 1 x 0603_22uF; 3 x 0402_1uF

DFC: 5 x 0603_22uF; 3 x 0402_1uF

1

1

2

2

CC366

CC367

22U_0603_6.3V6-M

@

@

1

1

1

1

2

2

2

2

CC311

CC309

CC310

CC312

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

@

1

1

2

2

CC323

CC322

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1U_0402_6.3V6K

1

2

CC306

2.2U_0402_6.3V6M

1U_0402_6.3V6K

+VDD2_1P2_USB2

1

1

2

2

CC325

CC324

1U_0402_6.3V6K

1U_0402_6.3V6K

@

+1.2VALW +VDD2_1P2_GLM

1 2

RC163 0_0603_5%@

+VDD2_1P2_DSI

1 2

A A

RC164 0_0603_5%@

1

2

CC329

5

IccMAX=0.11A

22U_0603_6.3V6-M

1 2

RC165 0_0603_5%@

4

+VDD2_1P2_DSI

+VDD2_1P2_GLM

+VDD2_1P2_PLL

+VDD2_1P2_VNNAON

2 x 0603_22uF; 1 x 0402_1uF

1

2

CC326

CC327

22U_0603_6.3V6-M

@

+VDD2_1P2_PLL

1 x 0603_22uF; 2 x 0402_1uF 1 x 0402_1uF

1

2

CC330

22U_0603_6.3V6-M

4

+VCCIOA

+VCC1P8

+VDD2_1P2_MPHY

+VDD2_1P2_AUD_ISH

IccMAX=0.44A

1

1

2

2

CC328

22U_0603_6.3V6-M

1U_0402_6.3V6K

IccMAX=0.22A

1

1

2

2

@

CC331

CC332

1U_0402_6.3V6K

1U_0402_6.3V6K

3

+1.2V

UC1J

AP18

VDDQ1

AP21

VDDQ2

AP36

VDDQ3

AP38

VDDQ4

AT18

VDDQ5

AT20

VDDQ6

AT21

VDDQ7

AT35

VDDQ8

AT36

VDDQ9

AT38

VDDQ10

BA13

VDDQ11

BA15

VDDQ12

BA25

VDDQ13

BA31

VDDQ14

BA41

VDDQ15

BA43

VDDQ16

AP25

VCCIOA1

AP31

VCCIOA2

AT25

VCCIOA3

AT27

VCCIOA4

AT28

VCCIOA5

AT29

VCCIOA6

AT31

VCCIOA7

T21

VCC_1P8V_A3

T23

VCC_1P8V_A4

T25

VCC_1P8V_A5

V21

VCC_1P8V_A6

V23

VCC_1P8V_A7

V25

VCC_1P8V_A8

AJ23

VCC_1P8V_A2

AG23

VCC_1P8V_A1

AC21

VDD2_1P2_MPHY1

AE20

VDD2_1P2_MPHY2

AE21

VDD2_1P2_MPHY3

AF20

VDD2_1P2_MPHY4

AF21

VDD2_1P2_MPHY5

AC18

VDD2_1P2_AUD_ISH1

AC20

VDD2_1P2_AUD_ISH2

AW12

VDD2_1P2_DSI_CSI

AL36

VDD2_1P2_GLM1

AL38

VDD2_1P2_GLM2

AP20

VDD2_1P2_GLM4

AM20

VDD2_1P2_GLM3

AL18

VDD2_1P2_PLL1

AM18

VDD2_1P2_PLL2

AA18

VDD2_1P2_VNNAON1

AA20

VDD2_1P2_VNNAON2

AG18

VDD2_1P2_USB2

AJ20

VDD2_1P2_USB3

GEMINILAKE_FCBGA1090

@

VCCRAM(1.05V)

RTC

VDD1(1.8V)

VDD3(3.3V)

VDD2(1.2V)

10 OF 13

+1.2VALW +VDD2_1P2_VNNAON

RC161 0_0603_5%@1 2

IccMAX=0.22A

+VDD2_1P2_USB2

1 2

RC166 0_0603_5%@

IccMAX=0.22A

1

2

CC333

1U_0402_6.3V6K

3

VCCRAM_1P05_3
VCCRAM_1P05_4
VCCRAM_1P05_7
VCCRAM_1P05_8

VCCRAM_1P05_9
VCCRAM_1P05_10
VCCRAM_1P05_11
VCCRAM_1P05_12
VCCRAM_1P05_13
VCCRAM_1P05_14

VCC_1P05_INT2
VCC_1P05_INT1

VCC_1P05_INT3

VCCRAM_1P05_1

VCCRAM_1P05_2

VCCRAM_1P05_5

VCCRAM_1P05_6
VCCRAM_1P05_15
VCCRAM_1P05_16

VCCRTC_3P3V

VCC_3P3V_A2
VCC_3P3V_A5

VCC_3P3V_A1
VCC_3P3V_A3
VCC_3P3V_A4
VCC_3P3V_A6
VCC_3P3V_A7
VCC_3P3V_A8
VCC_3P3V_A9

+VCCRAM_1P05

AC33
AC35
AE33
AE35
AE36
AE38
AF27
AF28
AF36
AF38

AG51
AG49

AJ51
AA36

AA38
AC36
AC38
Y36
Y38

P15

AJ21
U17

AG21
T18
T20
V18
V20
Y18
Y20

2

+1.05VS total IccMAX=4.5A

+1.05VS +VCCRAM_1P05

J23

2

JUMP_43X39

112

@

+VCCRAM_1P05_FHV0_FHV1_FUSE

+VCCRAM_1P05

+1.05VS

VCCRTC

RC154 0_0603_5%@1 2

+VDD3_3P3

VCCRTC

CC313

+3VALW_SOC +VDD3_3P3

1

1

2

2

@

CC314

1U_0402_6.3V6K

1U_0402_6.3V6K

Reserve for VDD2_1P2 and VDDQ Merged

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/03/26

2013/03/26

2013/03/26

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/02/01

2013/02/01

2013/02/01

CC292

IccMAX=0.51A

1 2

RC159 0_0603_5%@

1

1

2

CC293

22U_0603_6.3V6-M

22U_0603_6.3V6-M

3 x 0603_22uF; 7 x 0402_1uF

1

1

@

CC294

2

2

10U_0402_6.3V6M

CC368

22U_0603_6.3V6-M

1

1

@

@

CC295

2

2

10U_0402_6.3V6M

CC297

CC296

1U_0402_6.3V6K

IccMAX=2.72A

1

2

+VCCRAM_1P05_FHV0_FHV1_FUSE

IccMAX=0.15A

1

1

2

CC315

22U_0603_6.3V6-M

Need Open

J22

2

112

JUMP_43X39

@

Title

Title

Title

SOC (Power)

SOC (Power)

SOC (Power)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

@

2

2

CC316

CC317

1U_0402_6.3V6K

+1.2VALW+1.2V

EG431/EG532

EG431/EG532

EG431/EG532

1

Follow Intel CRB

1

1

1

@

CC299

2

2

2

CC298

1U_0402_6.3V6K

1U_0402_6.3V6K

Follow Intel CRB

1

1

@

@

2

2

CC318

CC319

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12 60

12 60

12 60

1

@

2

10U_0402_6.3V6M

CC300

1U_0402_6.3V6K

1.0

1.0

1.0

Vinafix.com

5

4

3

2

1

IccMAX=25.0A IccMAX=4.0A

1

1

2

2

CC341

D D

CC334

1U_0402_6.3V6K

16 x 0402_1uF

1

1

1

2

2

CC335

1U_0402_6.3V6K

2

CC336

CC337

1U_0402_6.3V6K

CC338

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

2

2

2

CC340

CC339

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

Follow Intel CRB

+CPU_CORE+CPU_CORE

1

1

1

1

1

1

2

2

CC348

CC350

CC349

1U_0402_6.3V6K

1U_0402_6.3V6K

@

2

2

CC352

CC351

1U_0402_6.3V6K

1U_0402_6.3V6K

1

@

2

CC353

1U_0402_6.3V6K

1

@

@

2

2

2

CC354

CC355

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+CPU_CORE

1

1

2

2

CC357

CC358

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

EMC@

EMC@

C C

Follow CRB, Need EMC Team Confirmation

UC1I

AA28

VCC_VCG1

AA29

VCC_VCG2

AA31

VCC_VCG3

AA33

VCC_VCG4

AC28

VCC_VCG5

AC31

VCC_VCG6

AE28

VCC_VCG7

AE29

VCC_VCG8

AE31

VCC_VCG9

AF31

VCC_VCG10

AF33

VCC_VCG11

AG31

VCC_VCG12

AG33

VCC_VCG13

AJ31

VCC_VCG14

AJ33

VCC_VCG15

AJ35

VCC_VCG16

AL31

VCC_VCG17

AL33

VCC_VCG18

AL35

VCC_VCG19

AM33

VCC_VCG20

AM35

VCC_VCG21

AM36

VCC_VCG22

D31

VCC_VCG23

D33

VCC_VCG24

D37

VCC_VCG25

D39

VCC_VCG26

P39

VCC_VCG27

P41

VCC_VCG28

T28

VCC_VCG29

T29

VCC_VCG30

T31

VCC_VCG31

T33

VCC_VCG32

T35

VCC_VCG33

T36

VCC_VCG34

V28

VCC_VCG35

V29

VCC_VCG36

V31

VCC_VCG37

V33

VCC_VCG38

V35

VCC_VCG39

V36

VCC_VCG40

Y28

VCC_VCG41

Y29

VCC_VCG42

Y33

VCC_VCG43

Y35

VCC_VCG44

GEMINILAKE_FCBGA1090

@

9 OF 13

VCC_VCG_SENSE

VSS_VCG_SENSE

VNN_SENSE

VNN_VSS_SENSE

+VNN +VNN

AF35

VNN1

AG27

VNN2

AG28

VNN3

AG36

VNN4

AG46

VNN5

AG48

VNN6

AJ27

VNN7

AJ28

VNN8

AJ46

VNN9

AJ48

VNN10

AL27

VNN11

AL28

VNN12

AL48

VNN13

AL49

VNN14

AM27

VNN15

AM28

VNN16

AJ49

NC21

AW44

NC22

BH55

NC23

NC24

AG41
AG39

AJ41
AJ43

BL54

CPU_VCC_SENSE
CPU_VSS_SENSE

VNN_VCC_SENSE
VNN_VSS_SENSE

1

2

CC342

CPU_VCC_SENSE 57
CPU_VSS_SENSE 57

VNN_VCC_SENSE 57
VNN_VSS_SENSE 57

1

1

1

2

CC343

CC344

1U_0402_6.3V6K

10U_0402_6.3V6M

1

1

2

2

2

2

CC345

10U_0402_6.3V6M

10U_0402_6.3V6M

@

@

CC347

CC346

1U_0402_6.3V6K

1U_0402_6.3V6K

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/03/26

2013/03/26

2013/03/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/02/01

2013/02/01

2013/02/01

Title

SOC (Power2)

SOC (Power2)

SOC (Power2)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

1

13 60

13 60

13 60

1.0

1.0

1.0

Vinafix.com

5

4

3

2

1

UC1K

A3

VSS_6

A6

VSS_13

A12

VSS_1

A16

VSS_2

A20

VSS_3

A24

VSS_4

D D

C C

A28

VSS_5

A32

VSS_7

A36

VSS_8

A40

VSS_9

A44

VSS_10

A48

VSS_11

A51

VSS_12

AA12

VSS_14

AA13

VSS_15

AA15

VSS_16

AA17

VSS_17

AA21

VSS_18

AA23

VSS_19

AA25

VSS_20

AA27

VSS_21

AA35

VSS_22

AA43

VSS_23

AA48

VSS_24

AB1

VSS_25

AB3

VSS_26

AB55

VSS_27

AC8

VSS_33

AC13

VSS_28

AC23

VSS_29

AC25

VSS_30

AC27

VSS_31

AC29

VSS_32

AE18

VSS_34

AE23

VSS_35

AE25

VSS_36

AE27

VSS_37

AE43

VSS_38

AE48

VSS_39

AF1

VSS_40

AF3

VSS_49

AF4

VSS_50

AF6

VSS_61

AF8

VSS_62

AF9

VSS_63

AF11

VSS_41

AF12

VSS_42

AF14

VSS_43

AF16

VSS_44

AF18

VSS_45

AF23

VSS_46

AF25

VSS_47

AF29

VSS_48

AF40

VSS_51

AF42

VSS_52

GEMINILAKE_FCBGA1090

@

11 OF 13

VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_64
VSS_87
VSS_65
VSS_66
VSS_67
VSS_68
VSS_77
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_78
VSS_79
VSS_80
VSS_90
VSS_97
VSS_98
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_88
VSS_89
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_108
VSS_110
VSS_107
VSS_109

AF44
AF45
AF47
AF48
AF50
AF52
AF53
AF55
AG20
AL21
AG25
AG29
AG35
AG38
AJ8
AJ13
AJ18
AJ25
AJ29
AJ36
AJ38
AJ39
AJ44
AK1
AK3
AK55
AL3
AL7
AL8
AL10
AL12
AL13
AL15
AL17
AL20
AL25
AL29
AL39
AL41
AL43
AL44
AL46
AL51
AM1
AM21
AM23
AM25
AM29
AM31
AM38
AM55
AN3
AN8
AN10
AN46

UC1L

AN48

VSS_111

AN49

VSS_112

AN51

VSS_113

AN53

VSS_114

AP23

VSS_115

AP27

VSS_116

AP28

VSS_117

AP29

VSS_118

AP33

VSS_119

AP35

VSS_120

AR2

VSS_124

AR7

VSS_130

AR10

VSS_121

AR12

VSS_122

AR17

VSS_123

AR39

VSS_125

AR44

VSS_126

AR46

VSS_127

AR49

VSS_128

AR54

VSS_129

AT23

VSS_131

AT33

VSS_132

AU3

VSS_135

AU10

VSS_133

AU28

VSS_134

AU46

VSS_136

AU53

VSS_137

AV15

VSS_138

AV17

VSS_139

AV23

VSS_140

AV25

VSS_141

AV31

VSS_142

AV33

VSS_143

AV39

VSS_144

AV41

VSS_145

AW2

VSS_147

AW5

VSS_150

AW10

VSS_146

AW28

VSS_148

AW46

VSS_149

AW51

VSS_151

AW54

VSS_152

AY13

VSS_153

AY15

VSS_154

AY28

VSS_155

AY41

VSS_156

AY43

VSS_157

B2

VSS_158

B55

VSS_159

BA27

VSS_160

BA29

VSS_161

BB1

VSS_162

BB28

VSS_163

BB55

VSS_164

BC5

VSS_178

GEMINILAKE_FCBGA1090

@

12 OF 13

VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_179
VSS_187
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_189
VSS_188
VSS_190
VSS_194
VSS_191
VSS_192
VSS_193
VSS_195
VSS_199
VSS_196
VSS_197
VSS_198
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_215
VSS_213
VSS_214
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220

BC11
BC17
BC19
BC21
BC23
BC25
BC31
BC33
BC35
BC37
BC39
BC41
BC45
BC51
BD9
BD15
BD19
BD21
BD28
BD35
BD37
BD47
BE3
BE28
BE53
BF9
BF19
BF37
BF47
BG1
BG6
BG28
BG50
BG55
BH11
BH13
BH17
BH19
BH23
BH25
BH28
BH31
BH33
BH37
BH39
BH41
BH45
BJ2
BJ15
BJ19
BJ25
BJ28
BJ31
BJ37
BJ41

UC1M

AL23

VSS_221

BJ54

VSS_222

BK1

VSS_223

BK17

VSS_224

BK21

VSS_225

BK35

VSS_226

BK39

VSS_227

BK55

VSS_228

BL5

VSS_229

BL8

VSS_230

BL10

VSS_231

BL14

VSS_232

BL24

VSS_233

BL28

VSS_234

BL32

VSS_235

BL42

VSS_236

BL46

VSS_237

BL48

VSS_238

BL51

VSS_239

C1

VSS_240

C12

VSS_241

C16

VSS_242

C28

VSS_243

C36

VSS_244

D6

VSS_245

D9

VSS_246

D21

VSS_247

D28

VSS_248

D41

VSS_249

D45

VSS_250

D55

VSS_251

E28

VSS_252

E50

VSS_253

E55

VSS_254

F1

VSS_255

F4

VSS_256

F21

VSS_257

F31

VSS_258

G28

VSS_259

H13

VSS_260

H15

VSS_261

H21

VSS_262

H23

VSS_263

H28

VSS_264

H33

VSS_265

H39

VSS_266

J8

VSS_267

J27

VSS_268

J33

VSS_269

J41

VSS_270

J45

VSS_271

GEMINILAKE_FCBGA1090

@

13 OF 13

VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321

J51
K1
K3
K28
K55
L5
L7
L8
L19
L33
M15
M25
M28
M35
M41
N12
N28
N46
N51
P21
P55
R8
R28
T27
T38
U13
V27
V38
V55
W2
W3
W5
W7
W8
W10
W39
W41
W43
W44
W46
W48
W49
W51
Y21
Y23
Y25
Y27
Y31
T3
U3

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/03/26

2013/03/26

2013/03/26

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/02/01

2013/02/01

2013/02/01

Title

SOC (VSS)

SOC (VSS)

SOC (VSS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

1

14 60

14 60

14 60

1.0

1.0

1.0

Vinafix.com

5

Hardware STRAPS(Follow up CRB)

+1.8VALW

12

12

12

12

12

12

12

12

@

@

@

D D

RC173 4.7K_0402_5%

RC171 10K_0402_5%

RC172 10K_0402_5%

12

12

12

@

@

RC187 4.7K_0402_5%

RC189 10K_0402_5%

RC188 4.7K_0402_5%

C C

+1.8VALW +1.8VALW

12

12

12

@

@

@

RC204 4.7K_0402_5%

RC205 4.7K_0402_5%

RC203 4.7K_0402_5%

12

12

12

B B

@

@

@

RC222 10K_0402_5%

RC221 10K_0402_5%

RC220 10K_0402_5%

@

@

RC174 10K_0402_5%

12

12

@

@

RC190 4.7K_0402_5%

12

12

@

@

RC206 4.7K_0402_5%

12

12

@

RC223 10K_0402_5%

@

@

RC175 4.7K_0402_5%

RC176 4.7K_0402_5%

12

@

@

RC192 10K_0402_5%

RC191 10K_0402_5%

12

@

@

RC208 4.7K_0402_5%

RC207 10K_0402_5%

12

@

RC224 4.7K_0402_5%

RC225 10K_0402_5%

@

RC178 4.7K_0402_5%

RC177 4.7K_0402_5%

12

12

@

RC193 10K_0402_5%

RC194 10K_0402_5%

12

12

@

RC209 10K_0402_5%

RC210 4.7K_0402_5%

12

12

@

RC227 10K_0402_5%

RC266 4.7K_0402_5%

GPIO_42

Allow eMMC as a Boot Source
Allow SPI as a Boot Source
Flash Descriptor Override
RSVD
RSVD
Top Swap Override
Enable TXE ROM Bypass
RSVD

RSVD
RSVD
RSVD
RSVD

SMBus 1.8V/3.3V Mode Select

RSVD

PMU 1.8V/3.3V Mode Select

SMBus No Re-Boot

GPIO_27 11
GPIO_28 11
GPIO_42 9
GPIO_43 9
USB_OC0#_GPIO_44 8
USB_OC1#_GPIO_45 8,31
GPIO_61 7
GPIO_62 7

GPIO_86 7
GPIO_87 7
GPIO_89 7
GPIO_159 6
GPIO_163 6
GPIO_164 6
HDA_SDIN0_GPIO_168 6,34
GPIO_172 6

+1.8VALW

12

12

@

@

RC180 4.7K_0402_5%

RC179 4.7K_0402_5%

12

12

@

@

RC195 10K_0402_5%

RC196 10K_0402_5%

12

12

@

@

RC211 4.7K_0402_5%

RC212 4.7K_0402_5%

12

12

@

@

RC229 10K_0402_5%

RC228 10K_0402_5%

12

@

@

RC181 4.7K_0402_5%

12

@

@

RC197 10K_0402_5%

12

@

@

RC213 4.7K_0402_5%

12

@

@

RC230 10K_0402_5%

4

12

12

@

RC183 4.7K_0402_5%

RC182 4.7K_0402_5%

12

12

@

RC198 10K_0402_5%

RC199 1K_0402_5%

12

12

@

@

RC215 4.7K_0402_5%

RC214 4.7K_0402_5%

12

12

@

@

RC232 10K_0402_5%

RC231 10K_0402_5%

12

12

@

@

RC184 10K_0402_5%

RC185 10K_0402_5%

12

12

@

RC201 4.7K_0402_5%

RC200 4.7K_0402_5%

12

12

@

@

RC217 4.7K_0402_5%

RC216 10K_0402_5%

12

12

@

@

RC233 4.7K_0402_5%

RC234 10K_0402_5%

12

RC186 4.7K_0402_5%

12

RC202 10K_0402_5%

12

12

@

RC218 4.7K_0402_5%

RC219 4.7K_0402_5%

12

12

@

RC236 10K_0402_5%

RC235 10K_0402_5%

Force DNX FW Load
LPC boot BIOS Strap
RSVD
RSVD
RSVD

LPC 1.8V/3.3V Mode Select

Allow SPI as a Boot Source
RSVD

VDD2 1.24V vs. 1.20V select
eSPI vs. LPC Select
RSVD
eSPI Flash Sharing Mode
RSVD
RSVD
RSVD
RSVD
RSVD

3

SOC_UART_TXD_GPIO_65 7,39
GPIO_66 7
GPIO_79 7
GPIO_80 7
GPIO_81 7
GPIO_83 7
GPIO_84 7
GPIO_85 7

GPIO_174 6
GPIO_175 6
PCH_SMB_CLK_GPIO_177 7
CNVI_BRI_DT_GPIO_191 7
CNVI_BRI_RSP_GPIO_192 7
CNVI_RGI_DT_GPIO_193 7
CNVI_RGI_RSP_GPIO_194 7
CNVI_RF_RST#_GPIO_195 7
XTAL_CLKREQ_GPIO_196 7

2

Purpose

Internal
Termination

GPIO#

Allow eMMC as a

Boot Source

GPIO_27

Allow SPI as a

Boot Source

GPIO_28

Flash Descriptor

GPIO_42

Override 20K PD Floating

GPIO_43 RSVD

GPIO_44 RSVD 20K PD Floating

Top swap
override

GPIO_45

Enable TXE ROM

GPIO_61

Bypass 20K PD Floating

GPIO_62 RSVD 20K PD Floating

Force DNX FW
Load

GPIO_65

LPC boot BIOS
strap

GPIO_66

GPIO_79 RSVD 20K PD Floating

GPIO_80 RSVD 20K PD Floating

GPIO_81 RSVD 20K PU

LPC 1.8V/3.3V

mode select

GPIO_83

Allow SPI as a
boot source

GPIO_84 Follow CRB(v1.2 P58); EDS(v1.2 P40)

GPIO_85 RSVD 20K PD Floating

GPIO_86 RSVD 20K PD

RSVD

GPIO_87 20K PD Floating

GPIO_89

GPIO_159 Follow CRB(v1.2 P57); EDS(v1.2 P40)20K PDRSVD

SMBus 1.8V/3.3V

mode select

GPIO_163

GPIO_164 RSVD 20K PD

PMU 1.8V/3.3V

mode select

GPIO_168

SMBus No Re-

Boot

GPIO_172

VDD2 1.24V vs.

1.20V select

GPIO_174

GPIO_175

eSPI vs. LPC 20K PD Floating

GPIO_177

RSVD 20K PD Floating
eSPI Flash

GPIO_191

Sharing Mode 20K PD

GPIO_192

GPIO_193

RSVD

GPIO_194

RSVD

GPIO_195

RSVD

GPIO_196

RSVD

Schematics
Setting

20K PU

4.7K PD

20K PU Floating Follow CRB(v1.2 P58); EDS(v1.2 P39); PDG(v1.2 P469)

20K PU Floating

20K PD Floating

20K PD Floating

20K PD Floating Follow CRB(v1.2 P57); EDS(v1.2 P40)

20K PD 4.7K PD

20K PU 4.7K PD

Floating

FloatingRSVD 20K PD

Floating

20K PD 4.7K PD

20K PD 4.7K PD

20K PD Floating

FloatingRSVD 20K PD

20K PU Floating

20K PD

Floating

20K PD

Floating

20K PD

Floating

Pin Usage Remark

1 = Enable(Default); 0 = Disable[# ]

If platform is using SPI as the boot device, then
provide a pull-down for this strap to disable eMMC

1 = Enable(Default)[# ]; 0 = Disable
If platform is using eMMC as boot device, then
provide a pull down for this strap to disable SPI
1 = Override; 0 = No Override(Normal Operation)[# ]
This strap enables the platform to override security
features in the SPI
Ensure that this strap is pulled HIGH when RSM_RST_N
de-asserts for normal platform operation

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

1 = Enable; 0 = Disable(Default)[# ]
This strap enables platform to change where the core

will look for BIOS code for a SPI boot only

1 = Enable Bypass; 0 = Disable Bypass(Default)[# ]
This strap tells TXE 3.0 to bypass Read-Only Memory
(ROM) that it has on SoC
Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P39)

1 = Force; 0 = Do Not Force(Default)[# ]
This strap is a recovery strap for corrupted FW image,
will force TXE3.0 to execute a DnX flow

1 = Boot From LPC; 0 = Do Not(Default)[# ]
The board should strap this low and do not use
otherwise
Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation Follow CRB(v1.2 P58); EDS(v1.2 P40)

Ensure that this strap is pulled HIGH when RSM_RST_N
de-asserts for normal platform operation Follow CRB(v1.2 P58); EDS(v1.2 P40)4.7K PU

1=buffers set to 1.8V mode
0=buffers set to 3.3V mode (default)[# ]

1=disable
0=enable (default)[# ]

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation Follow CRB(v1.2 P58); EDS(v1.2 P40)

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P40)

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

1=buffers set to 1.8V mode
0=buffers set to 3.3V mode (default)[# ]

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P40)Floating

1=buffers set to 1.8V mode
0=buffers set to 3.3V mode (default)[# ]

1 = Enable ; 0 = Disable (default)[# ]
Note: Platforms should strap this LOW. Functionality is
handled by the PMC.

1=VDD2 is 1.24V;
0=VDD2 is 1.20V (default) Need Check

1=eSPI mode; 0=LPC mode (default)
Note: The default for A0 will be eSPI due to a bug on
LPC.

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P41)

eSPI Flash Sharing Mode:
1=slave attached flash sharing (SAFS);
0=master attached $lash sharing (MAFS; default)[# ]
Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

Ensure that this strap is pulled HIGH when RSM_RST_N
de-asserts for normal platform operation

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

Ensure that this strap is pulled LOW when RSM_RST_N
de-asserts for normal platform operation

Follow CRB(v1.2 P58); EDS(v1.2 P39); PDG(v1.2 P469)

Follow CRB(v1.2 P58); EDS(v1.2 P39); PDG(v1.2 P380)

Follow CRB(v1.2 P57); EDS(v1.2 P39)

Follow CRB(v1.2 P57); EDS(v1.2 P39)

Follow CRB(v1.2 P57); EDS(v1.2 P39)

Follow CRB(v1.2 P58); EDS(v1.2 P39); PDG(v1.2 P380)

Follow CRB(v1.2 P58); EDS(v1.2 P40); PDG(v1.2 P471)

Follow CRB(v1.2 P57); EDS(v1.2 P40)

Follow CRB(v1.2 P57); EDS(v1.2 P40)

Follow CRB(v1.2 P58); EDS(v1.2 P40)

Follow CRB(v1.2 P57); EDS(v1.2 P40)

Follow CRB(v1.2 P57); EDS(v1.2 P40)

Follow CRB(v1.2 P57); EDS(v1.2 P40)

Follow CRB(v1.2 P57); EDS(v1.2 P40)20K PD Floating

Follow CRB(v1.2 P57); EDS(v1.2 P40)

Follow CRB(v1.2 P57); EDS(v1.2 P41)

Follow CRB(v1.2 P57); EDS(v1.2 P41)Floating

Follow CRB(v1.2 P57); EDS(v1.2 P41)

Follow CRB(v1.2 P57); EDS(v1.2 P41)

Follow CRB(v1.2 P57); EDS(v1.2 P41)

Follow CRB(v1.2 P57); EDS(v1.2 P41)

Follow CRB(v1.2 P57); EDS(v1.2 P41)

1

ME_PROTECT Circuit

A A

GPIO_42

EC_ME_PROTECT GPIO_42 TXE Flash Descriptor Override

Low

High

1 2

@

ME3
SHORT PADS

High

Low

+1.8VALW

RC237

2.2K_0402_5%

1 2

S

QC21

G

2

D

DMG1013UW-7_SOT-323-3

1 3

No Override (Normal Operation)

5

12

RC238
100K_0402_5%

Override

EC_ME_PROTECT 44

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/01/21

2014/01/21

2014/01/21

Title

SOC (STRAPS & OTHERS)

SOC (STRAPS & OTHERS)

SOC (STRAPS & OTHERS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

EG431/EG532

EG431/EG532

EG431/EG532

1

15 60

15 60

15 60

1.0

1.0

1.0

Vinafix.com

5

D D

C C

4

3

2

1

B B

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/01/21

2014/01/21

2014/01/21

Title

P12-SOC (GPIO&HDA)

P12-SOC (GPIO&HDA)

P12-SOC (GPIO&HDA)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

Date: Sheet of

Date: Sheet of

Date: Sheet of

EG431/EG532

EG431/EG532

EG431/EG532

1

16 60

16 60

16 60

1.0

1.0

1.0

Vinafix.com

5

4

3

2

1

DDR4 Swap Mapping table

DDR4 SO-DIMMDDR4 NET DDR4 NET DDR4 SO-DIMM

DDRA_DQ0---DQ
DDRA_DQ1---DQ
DDRA_DQ2---DQ
DDRA_DQ3---DQ
DDRA_DQ4---DQ
DDRA_DQ5---DQ
DDRA_DQ6---DQ
DDRA_DQ7---DQ

DDRA_DQ8 ---DQ

D D

DDRA_DQ9 ---DQ
DDRA_DQ10---DQ
DDRA_DQ11---DQ
DDRA_DQ12---DQ
DDRA_DQ13---DQ
DDRA_DQ14---DQ
DDRA_DQ15---DQ

DDRA_DQ16---DQ
DDRA_DQ17---DQ
DDRA_DQ18---DQ
DDRA_DQ19---DQ
DDRA_DQ20---DQ
DDRA_DQ21---DQ
DDRA_DQ22---DQ
DDRA_DQ23---DQ

DDRA_DQ24---DQ
DDRA_DQ25---DQ
DDRA_DQ26---DQ
DDRA_DQ27---DQ
DDRA_DQ28---DQ
DDRA_DQ29---DQ
DDRA_DQ30---DQ
DDRA_DQ31---DQ

DDRA_DQ32---DQ
DDRA_DQ33---DQ
DDRA_DQ34---DQ
DDRA_DQ35---DQ
DDRA_DQ36---DQ
DDRA_DQ37---DQ
DDRA_DQ38---DQ
DDRA_DQ39---DQ

DDRA_DQ40---DQ
DDRA_DQ41---DQ
DDRA_DQ42---DQ
DDRA_DQ43---DQ
DDRA_DQ44---DQ
DDRA_DQ45---DQ

C C

DDRA_DQ46---DQ
DDRA_DQ47---DQ

DDRA_DQ48---DQ
DDRA_DQ49---DQ
DDRA_DQ50---DQ
DDRA_DQ51---DQ
DDRA_DQ52---DQ
DDRA_DQ53---DQ
DDRA_DQ54---DQ
DDRA_DQ55---DQ

DDRA_DQ56---DQ
DDRA_DQ57---DQ
DDRA_DQ58---DQ
DDRA_DQ59---DQ
DDRA_DQ60---DQ
DDRA_DQ61---DQ
DDRA_DQ62---DQ
DDRA_DQ63---DQ

B B

A A

DQ0
DQ5
DQ1
DQ4
DQ6
DQ2
DQ3
DQ7

DQ12
DQ9
DQ8
DQ11
DQ14
DQ10
DQ15
DQ13

DQ24
DQ29
DQ25
DQ28
DQ31
DQ30
DQ27
DQ26

DQ21
DQ20
DQ16
DQ18
DQ19
DQ17
DQ23
DQ22

DQ34
DQ35
DQ38
DQ39
DQ36
DQ32
DQ37
DQ33

DQ43
DQ47
DQ42
DQ46
DQ44
DQ40
DQ41
DQ45

DQ62
DQ63
DQ59
DQ56
DQ58
DQ61
DQ57
DQ60

DQ53
DQ50
DQ51
DQ55
DQ48
DQ49
DQ52
DQ54

DDRA_DQS0 ---DQS
DDRA_DQS0#---DQS#

DDRA_DQS1 ---DQS
DDRA_DQS1#---DQS#

DDRA_DQS2 ---DQS
DDRA_DQS2#---DQS#

DDRA_DQS3 ---DQS
DDRA_DQS3#---DQS#

DDRA_DQS4 ---DQS
DDRA_DQS4#---DQS#

DDRA_DQS5 ---DQS
DDRA_DQS5#---DQS#

DDRA_DQS6 ---DQS
DDRA_DQS6#---DQS#

DDRA_DQS7 ---DQS
DDRA_DQS7#---DQS#

Follow CRB v1.2

CD119

0.1u_0201_10V6K

+VREF_CA_DIMM

1

CD14

0.1u_0201_10V6K

2

DQS0_c
DQS0_t

DQS1_c
DQS1_t

DQS3_c
DQS3_t

DQS2_c
DQS2_t

+1.2V

RD93

RD92 240_0402_1%

DQS4_c
DQS4_t

DQS5_c
DQS5_t

DQS7_c
DQS7_t

DQS6_c
DQS6_t

+1.2V

1

12

2

RD96

3.65K_0402_1%

12

RD100

3.65K_0402_1%

Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket

RD98

+3VS

12

RD7
0_0402_5%

@

DDRA_SA0

12

RD10

@

0_0402_5%

1 2

2_0402_5%

12

DDRA_CKE04
DDRA_BG14

DDRA_BG04
DDRA_MA124

DDRA_MA94
DDRA_MA84

DDRA_MA64

12

DDRA_VREFCA_R

12

+3VS

12

RD8
0_0402_5%

@

12

@

+1.2V +1.2V +1.2V+1.2V+1.2V +1.2V +1.2V +1.2V

DDRA_DQ1
DDRA_DQ2
DDRA_DQS#0

DDRA_DQS0
DDRA_DQ7
DDRA_DQ6
DDRA_DQ15
DDRA_DQ9

DDRA_DQ14
DDRA_DQ13
DDRA_DQ24
DDRA_DQ29
DDRA_DQS#3

DDRA_DQS3
DDRA_DQ30
DDRA_DQ28
DDRA_DQ17
DDRA_DQ18

DDRA_DQ21
DDRA_DQ23

240_0402_1%

DDRA_DQS#8
DDRA_DQS8

RD97 0_0402_5%@
RD99 0_0402_5%

1

CD120

0.022U_0201_6.3V6-K

2

RD101

24.9_0402_1%

DDRA_SA1

RD11
0_0402_5%

DDR4 SO-DIMM

SHOULD CHECK SO-DIMM CONNECTOR WITH ME

JDDR1A

1 2
1 2

@

+3VS

12

12

@

RD9
0_0402_5%

@

RD12
0_0402_5%

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129

DDRA_SA2

VSS_1
DQ5
VSS_3
DQ1
VSS_5
DQS0_C
DQS0_t
VSS_8
DQ7
VSS_10
DQ3
VSS_12
DQ13
VSS_14
DQ9
VSS_16
DM1_n/DBl1_n/NC
VSS_17
DQ15
VSS_19
DQ10
VSS_21
DQ21
VSS_23
DQ17
VSS_25
DQS2_c
DQS2_t
VSS_28
DQ23
VSS_30
DQ19
VSS_32
DQ29
VSS_34
DQ25
VSS_36
DM3_n/DBl3_n/NC
VSS_37
DQ30
VSS_39
DQ26
VSS_41
CB5/NC
VSS_43
CB1/NC
VSS_45
DQS8_c
DQS8_t
VSS_48
CB2/NC
VSS_50
CB3/NC
VSS_52
CKE0
VDD_1
BG1
BG0
VDD_3
A12
A9
VDD_5
A8
A6
VDD_7

ARGOS_D4AS0-26001-1P60

ME@

DDRA_VREFCA_TP

DM0_n/DBIO_n/NC

VSS_11
VSS_13
VSS_15

DQS1_c
DQS1_t
VSS_18

VSS_20
VSS_22
VSS_24
VSS_26

DM2_n/DBl2_n/NC

VSS_27
VSS_29
VSS_31
VSS_33
VSS_35

DQS3_c
DQS3_t
VSS_38

VSS_40
VSS_42

CB4/NC
VSS_44
CB0/NC
VSS_46

DM8_n/DBI8_n/NC

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

VDD_2
ACT_n

ALERT_n

VDD_4

VDD_6

VDD_8

VSS_2
VSS_4
VSS_6
VSS_7
VSS_9

DQ12

DQ14
DQ11
DQ20
DQ16

DQ22
DQ18
DQ28
DQ24

DQ31
DQ27

CKE1

DQ4
DQ0

DQ6
DQ2

DQ8

A11

A7
A5

A4

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130

TP78

DDRA_VREFCA 4

@

DDRA_DQ3
DDRA_DQ0

DDRA_DQ4
DDRA_DQ5
DDRA_DQ8
DDRA_DQ10
DDRA_DQS#1

DDRA_DQS1
DDRA_DQ12
DDRA_DQ11
DDRA_DQ25
DDRA_DQ26

DDRA_DQ31
DDRA_DQ27
DDRA_DQ19
DDRA_DQ16
DDRA_DQS#2

DDRA_DQS2
DDRA_DQ20
DDRA_DQ22

DDRA_ALERT#

DDRA_CKE1 4
DDRA_ACT# 4

DDRA_MA11 4
DDRA_MA7 4

DDRA_MA5 4
DDRA_MA4 4

DDRA_DQ[0..63]
DDRA_DQS#[0..7]
DDRA_DQS[0..7]

DDRA_DQ[0..63] 4
DDRA_DQS#[0..7] 4
DDRA_DQS[0..7] 4

DDRA_DRAMRST#_R 5

1

CD3

0.1u_0201_10V6K

@

2

RD1 0_0603_5%@

+3VS

RD2 0_0603_5%@

+2.5V_DDR

Layout Note:
Place near DIMM

+1.2V

8 x 0603_10uF; 8 x 0402_1uF

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD19

CD20

CD@

+1.2V

2 x 0402_4.7uF; 2 x 0201_0.1uF; 2 x 0402_33pF

1

1

EMC_NS@

EMC_NS@

2

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

CD15

CD16

1 2

2.2U_0402_6.3V6M

1 2

1

2

10U_0603_6.3V6M

CD21

1

EMC_NS@

2

0.1u_0201_10V6K

CD17

DDRA_MA34
DDRA_MA14

DDRA_CLK04
DDRA_CLK0#4

DDRA_BS1#4
DDRA_CS0#4

DDRA_MA14_WE#4
DDRA_ODT04

DDRA_CS1#4
DDRA_ODT14

1

2

10U_0603_6.3V6M

CD22

1

EMC_NS@

2

0.1u_0201_10V6K

CD18

For EMC

SHOULD CHECK SO-DIMM CONNECTOR WITH ME

DDRA_CLK0
DDRA_CLK0#

DDRA_PAR

DDRA_DQ38
DDRA_DQ39
DDRA_DQS#4

DDRA_DQS4
DDRA_DQ34
DDRA_DQ32
DDRA_DQ44
DDRA_DQ45

DDRA_DQ43
DDRA_DQ42
DDRA_DQ62
DDRA_DQ61
DDRA_DQS#7

DDRA_DQS7
DDRA_DQ59
DDRA_DQ58
DDRA_DQ53
DDRA_DQ51

DDRA_DQ48
DDRA_DQ52

SMB_CLK_S37,39 SMB_DATA_S3 7,39

CD@

CD4

SMB_CLK_S3
+VDD_SPD

1

1

CD5

0.1u_0201_10V6K

2

2

+VPP

+VTT

2 x 0603_10uF; 4 x 0402_1uF 2 x 0603_10uF; 2 x 0402_1uF

1

2

CD6

cost down 1x 330uF from CRB

1

2

10U_0603_6.3V6M
CD23

CD@

RF@

1

2

CD36

1U_0402_6.3V6K

1

2

CD24

33P_0402_50V8J

1

2

1U_0402_6.3V6K

CD118

Follow CRB add 2*0402_1uF

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD25

RF@

1

2

33P_0402_50V8J

CD37

1

2

1U_0402_6.3V6K

CD121

1

2

CD26

CD@

CD122

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

JDDR1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AS0-26001-1P60

ME@

1

@

2

10U_0603_6.3V6M

CD7

1

2

1U_0402_6.3V6K

CD27

CD28

CD@

CD@

1

2

DM4_n/DBl4_n/NC

DM6_n/DBl6_n/NC

1

2

10U_0603_6.3V6M

CD8

1U_0402_6.3V6K

CD29

RAS_n/A16
CAS_n/A15

C0/CS2_n/NC

1

2

1U_0402_6.3V6K

CD@

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

VDD_16

VDD_18
VREFCA

VSS_54
VSS_56
VSS_58
VSS_59
VSS_61
VSS_63
VSS_65
VSS_67

DQS5_c

DQS5_t
VSS_70

VSS_72
VSS_74
VSS_76
VSS_78
VSS_79
VSS_81
VSS_83
VSS_85
VSS_87

DQS7_c

DQS7_t
VSS_90

VSS_92
VSS_94

GND_2

132
134
136
138
140
142
144

146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260

262

+2.5V_DDR

CD@

DDRA_EVENT#
DDRA_CLK1

DDRA_CLK1#

+VREF_CA_DIMM
DDRA_SA2

DDRA_DQ36
DDRA_DQ37

DDRA_DQ35
DDRA_DQ33
DDRA_DQ47
DDRA_DQ46
DDRA_DQS#5

DDRA_DQS5
DDRA_DQ41
DDRA_DQ40
DDRA_DQ56
DDRA_DQ60

DDRA_DQ63
DDRA_DQ57
DDRA_DQ55
DDRA_DQ54
DDRA_DQS#6

DDRA_DQS6
DDRA_DQ49
DDRA_DQ50
SMB_DATA_S3

DDRA_SA0
DDRA_SA1

1

1

CD@

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD9

CD10

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD32

CD31

A2

A0

BA0

A13

SA2
DQ36
DQ32

DQ39
DQ35
DQ45
DQ41

DQ47
DQ43
DQ53
DQ48

DQ54
DQ50
DQ60
DQ57

DQ63
DQ59

SDA

SA0

Vtt

SA1

1

2

1U_0402_6.3V6K

CD30

DDRA_MA2 4

DDRA_CLK1 4
DDRA_CLK1# 4

DDRA_MA0 4

DDRA_MA10 4
DDRA_BS0# 4

DDRA_MA16_RAS# 4
DDRA_MA15_CAS# 4

DDRA_MA13 4

1

2

0.1u_0201_10V6K

CD1

+VTT

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD12

CD11

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CD34

CD33

CD@

Near JDDRL1

@

1

2

CD2

2.2U_0402_6.3V6M

Follow CRB v1.2, mount RD91(KBL NC)

DDRA_EVENT#

RD91 240_0402_1%

DDRA_ALERT#

RD94 240_0402_1%

DDRA_PAR

RD95 240_0402_1%

1 2
1 2
1 2

+1.2V

CRB v1.2 P64 Use 10K PD

SPD Address = A0H

5

4

3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/08

2013/08/08

2013/08/08

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/01/21

2014/01/21

2014/01/21

Title

Title

Title

DDRIII SO-DIMM A

DDRIII SO-DIMM A

DDRIII SO-DIMM A

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

1

EG431/EG532

EG431/EG532

EG431/EG532

17 60

17 60

17 60

1.0

1.0

1.0

Vinafix.com

5

D D

C C

4

3

2

1

B B

A A

0.65A@0.75V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2013/08/08

2013/08/08

2013/08/08

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/05

2013/08/05

2013/08/05

Title

Title

Title

Blank

Blank

Blank

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Friday, March 02, 2018

Friday, March 02, 2018

Friday, March 02, 2018

1

EG431/EG532

EG431/EG532

EG431/EG532

18 60

18 60

18 60

1.0

1.0

1.0