Lenovo Ideapad 330 Schematic

A

1 1

B

C

D

E

LCFC Confidential

EG521/EG522 MB Schematics Document

Kabylake-U42 with DDR4 + Nvidia N17S-G1

2 2

2017-04-20

REV:0.2

3 3

4 4

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

C

2015/08/20

LC Future Center Secret Data

Deciphered Date

D

2016/08/20

Title

Cover Page

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

EG521

1 60

E

1 60

0.2

A

LCFC confidential

B

C

D

E

NV: N17S-G1 Package: GB2C-64

AMD: Level2 Package: S3

Page 19~24

1 1

VRAM: 512/256*16

GDDR5*4: 4GB/2GB

Page 25~29

PCIe Port 1~4

HDMI Conn.

Page 34

eDP Conn

Int. Camera Conn.

USB2.0 Port4

Int. MIC Conn.

2 2

Page 33

SATA HDD

Page 42

SATA ODD

Page 42

SSD/Optane memory (Optional)

Page 40

PCIe Port 9~12

SATA Port0

SATA Port1A

PCI-Express

4x Gen3

HDMI (DDI 1)

eDP x2 Lane

USB2.0 x1

SATA Gen3 x1

SATA Gen1 x1

Intel MCP

KBL-U22 15W

BGA-1356 42mm*24mm

Memory Bus (Dual Channel)

1.2V DDR4 2133MT/s

USB3.0 x1 USB2.0 x1

USB2.0 x1

PCIe Gen1 x1 USB2.0 x1

PCIe Gen1 x1

USB3.0 Left Conn

USB3.0 Port1 USB2.0 Port1

USB3.0 Left Conn

USB3.0 Port3 USB2.0 Port3

USB3.0 Redriver

Parade PS8713

Touch Screen (Optional)

USB2.0 Port6

Finger Print (Optional)

USB2.0 Port7

NGFF WLAN&BT

PCIe Port6

USB2.0 Port7

LAN Chip

Realtek_RTL8111GUL

PCIe Port5

DDR4 SO-DIMM x1

DDR4 Memory Down

4pcs x16

Page 41

Type-C IC

Page 43

Page 33

Page 45

Page 40

Page 37

Realtek RTS5449

Type-C Conn

RJ45 Conn.

Page 38

Page 18

Page 17

Page 43

SD/MMC Conn.

3 3

Page 31

SPK Conn.

Page 30

HP&Mic Combo Conn.

Page 30

Codec & C/R

Realtek RTS5119

USB2.0 Port5

Page 30

USB2.0 x1

HD Audio

Page 3~16

LPC

EC

ITE IT8586E-LQFP

Page 44

SPI

I2C

TPM (Reserved)

Z32H320TC

SPI ROM (16MB)

W25Q128FVSIQ

Touch Pad

Page 45

Page 32

Page 07

Sub-board( for 15" 17")

Int.KBD Thermal Sensor (Reserved)

Page 45

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

NCT7718W

2015/08/20

Page 39

LC Future Center Secret Data

Deciphered Date

D

ODD BOARD

2016/08/20

Title

Block Diagram

Size Document Number Re v

Custom

Date : Sheet of

EG521

Tuesday, April 25, 2017

2 60

E

0.2

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

Battery only

S5 S4 AC Only

S5 S4 Battery only

S5 S4 AC & Battery don't exist

SMBUS Control Table

3 3

EC_SMB_DA 1

EC_SMB_CK 2

EC_SMB_DA 2

EC_SMB_CK 3

EC_SMB_DA 3

( O --> Means ON , X --> Means OFF )

+3VALW

+5VALW

V20B+

+3VALW_PCH

+1.8VALW

+1.0VALW

O

O X

O

X X

SOURCE

IT8586EEC_SMB_CK 1

+3VL_EC

IT8586E

+3VL_EC

+3VS

BATT

V

X

ChargerVDGPU

X

V

+3VG_AON

IT8586E

+3VL_EC

+3VS

+3VL_EC

+1.2V

+2.5V_DDR

+VCCST

Memory Down

V

+5VS

+3VS

+VCCIO

+VCCSTG

+VCCSA

+VCC_GT

+CPU_CORE

+0.6VS

O

X

PCH

X

V

X

PMIC

X

X X

+3VALW_PC H

SODIMM

Thermal Sensor

X

VX X X X X X X

STATE

Full ON

S3 (Suspen d to RAM)

S4 (Suspen d to Disk)

S5 (Soft OFF)

HSIO PORT

1

2

USB3 .0

USB2 .0

PCIE

WLAN WiMAX

X

SATA

V

X

3

4

5

6

1

2

3

4

5

6

7

8

9

10

1~4

X4 PCIE

5

6

7

8

9~12

X4 PCIE

0

1A

1B

2

SIGNAL

Functio n

USB3.0 Con n Left

USB Typ e-C

USB3.0 Con n Left

NC

USB3.0 Con n Left

USB Typ e-C

USB3.0 Con n Left

Finger Print

Cardreade r

Touch P anel

Bluetooth

Camera

NC

DGPU

LAN

WLAN

SATA HDD

SATA ODD

Optane Memory

HDD

ODD

used as PCIE

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON ON ON

ON

OFF

OFFLOW LOW LOW

OFF

HIGH HIGH HIGH

LOW

HIGH

LOWLOW

LOW

BTO ItemBOM Structure

@ 14@ 15@ 14or15@ 14or17@

Cannonlake@ CD@ DUALMIC @ EMC@ EMC_15@ EMC_NS@ EMC_PX@ EMC_PXNS@ ES@ EXO@

ME@ NTS@

DIS@ OPT@ PX@ RANK A@ RANK B@ Realtek_SD@ SINGLEMIC@ SINGLERANK@ DUALRANK@ TS@ TPM@ UMA@

Not stuff

For 14" part

For 15" part

For 14" or 15" part

For 14" or 17" part

For Can nonlake part

For C cost down

For Dual MIC part

For EMC part

For EMC 15" part

For EMC nu-stuff part

For EMC PX part

For EMC PX nu-stu ff part

For ES CPU

For EXO GPU

For ME part

For nu-tou ch part

For GPU part

For NV GPU part

For AMD GPU part

For VRAM r ank A part

For VRAM r ank B part

For Realte k SD part

For single MIC part

For single VRAN rank part

For dual VRAN ran k part

For touch screen part

For TPM part

For UMA part

X

PCH_SMB_CL K

PCH_SMB_DA TA

EC SMBus1 address

Device

Smart Battery

4 4

Charger

PCH

+3VALW_PC H

need to update

0001 0010 b

X

X X

EC SMBus2 address

Device

Thermal Sensor(NCT7718W )

PCH

DGPU

A

1001_100xb

need to update

V

+3VALW_PC H

EC SMBus3 address

Device AddressAddress

PMIC

B

V

+3VS

need to update

X

V

+3VS

PCH SM Bus address

Device AddressAddress

DDR4 SODIMM

Wlan

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

need to update

Rese rve d

2015/08/20

LC Future Center Secret Data

Deciphered Date

D

2016/08/20

Titl e

Notes List

Size Document Number Re v

Custom

Date : Sheet of

Date : Sheet o f

EG521

Tuesday, April 25, 2017

3 60

E

3 60

0.2

5

HDMI D2

D D

HDMI D1

HDMI D0

HDMI CLK

+VCCIO

C C

+VCCSTG

12

RC19

check PROCHOT# circuit with PWR

H_PROCHOT#44,55

check H_THRMTRIP# if need to connector to EC

B B

1K_0402_5%

RC20 499 +-1% 0402

12

RC143 1K_0402_5%

+VCCST_CPU

1 2

HDMI_TX2-34 HDMI_TX2+34 HDMI_TX1-34 HDMI_TX1+34 HDMI_TX0-34 HDMI_TX0+34 HDMI_CLK-34 HDMI_CLK+34

DDPB_CLK34 DDPB_DATA34

RC4 24.9_0402_1%

12

+VCCIO&EDP_COMP : Trace Width: 20mil Isolation Spa cing: 25mil Max length: 100mil

1 2

RC155 49.9_0402_1%

1 2

RC156 49.9_0402_1%

1 2

RC157 49.9_0402_1%U23E@

1 2

RC170 49.9_0402_1%U23E@

4

?

HDMI_TX2HDMI_TX2+ HDMI_TX1HDMI_TX1+ HDMI_TX0HDMI_TX0+ HDMI_CLKHDMI_CLK+

DDPB_CLK DDPB_DATA

DDPC_CLK DDPC_DATA

EDP_COMP PCH_ENVDD

+VCCST_CPU

12

RC1625

49.9_0402_1%

@

CATERR#

TC11PAD @ TC12PAD @ TC13PAD @ TC14PAD @

TC162@PAD

H_PECI H_PROCHOT#_R H_THRMTRIP#

XDP_BPM0#

1

XDP_BPM1#

1

XDP_BPM2#

1

XDP_BPM3#

1

GPP_E3

1

PROC_OPI_RCOMP PCH_OPI_RCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

H_PECI44

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

REV = 1

@

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U_BGA1356

REV = 1 @

UC1D

SKL_ ULT

DDI

DISPLAY SIDEBANDS

SKL_ ULT

CPU MISC

?

1 OF 20

3

EDP

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

JTAGX

?

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52

G50 F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

?

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST#

JTAGX

1 1 1 1 1

1 1 1 1 1 1

CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+

CPU_EDP_AUX# CPU_EDP_AUX

HDMI_HPD

GPP_E15

CPU_EDP_HPD

PCH_ENBKL PCH_EDP_PWM

PAD @

TC15

PAD @

TC16

PAD @

TC17

PAD @

TC18

PAD @

TC27

PAD @

TC29

PAD @

TC31

PAD @

TC35

PAD @

TC36

PAD @

TC42

PAD @

TC43

2

CPU_EDP_TX0- 33 CPU_EDP_TX0+ 33 CPU_EDP_TX1- 33 CPU_EDP_TX1+ 33

CPU_EDP_AUX# 33 CPU_EDP_AUX 33

HDMI_HPD 34

1 2

RC181 0_0402_5%

PCH_ENBKL 33 PCH_EDP_PWM 33 PCH_ENVDD 33

XDP_TCK

XDP_TDO

1 2

RC1546 0_0402_5%

1 2

RC1547 0_0402_5%

XDP_TDI PCH_JTAG_TDI

GPP_E15

RC1601 10K_0402_5%@

12

RC13 100K_0402_5%

JTAGX

PCH_JTAG_TDO

1 2

RC1548 0_0402_5%

1 2

RC1549 0_0402_5%

1 2

RC1550 0_0402_5%

check JTAG circuit?

1 2

+3VS

EC_SCI# 44

CPU_EDP_HPD 33

1 2

RC1551 51_0402_5%

1 2

RC1543 51_0402_5%

PCH_JTAG_TMSXDP_TMS

PCH_JTAG_TRST#XDP_TRST#

1

+VCCSTG

+3VS

DDP*_CTRLDATA strapping sam pled on the rising edge of PWROK

Port

Strap Enable Disable

Port 1

DDPB_CTRLDATA

Port 2

DDPC_CTRLDATA

A A

5

Pull up to 3.3 V with 2.2Kohm

4

NC

check DDPC_CLK pull high or not?

3

RPC26

1 4 2 3

2.2K_0404_4P2R_5%

RPC27

1 4 2 3

2.2K_0404_4P2R_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

DDPC_CLK

@

Disable DDI2 G320 SDV wei

DDPC_DATA

DDPB_CLK DDPB_DATA

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Title

MCP (DDI,EDP)

Size Document Number Re v

Custom

Date: Sheet o f

Tuesday, April 25, 2017

EG521

1

4 60

0.2

5

DDRA_DQ[0..63]17

D D

C C

B B

4

?

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR CH - A

+3VALW

12

RC30 100K_0402 _5%

1 OF 20

DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63

UC1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

REV = 1

@

3

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1]

DDR0_DQSP[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

2

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

DDRA_DQS#0

AM70

DDRA_DQS0

AM69

DDRA_DQS#1

AT69

DDRA_DQS1

AT70

DDRA_DQS#2

BA64

DDRA_DQS2

AY64

DDRA_DQS#3

AY60

DDRA_DQS3

BA60

DDRA_DQS#4

BA38

DDRA_DQS4

AY38

DDRA_DQS#5

AY34

DDRA_DQS5

BA34

DDRA_DQS#6

BA30

DDRA_DQS6

AY30

DDRA_DQS#7

AY26

DDRA_DQS7

BA26

AW50 AT52

AY67 AY68 BA67

DDR_VTT_C NTL

AW67

?

DDRA_CLK0# 17 DDRA_CLK0 17

DDRA_CKE0 17

DDRA_CS0# 17

DDRA_ODT0 17

DDRA_MA5 17 DDRA_MA9 17 DDRA_MA6 17 DDRA_MA8 17 DDRA_MA7 17 DDRA_BG0 17 DDRA_MA12 17 DDRA_MA11 17 DDRA_ACT# 17

DDRA_MA13 17 DDRA_MA15_CAS# 17 DDRA_MA14_W E# 17 DDRA_MA16_RAS# 17 DDRA_BS0# 17 DDRA_MA2 17 DDRA_BS1# 17 DDRA_MA10 17 DDRA_MA1 17 DDRA_MA0 17 DDRA_MA3 17 DDRA_MA4 17

DDRA_ALERT# 17 DDRA_PAR 1 7

DDR_SA_VREFCA 17

DDR_SB_VREFCA 18

DDRA_DQS#[0..7]

DDRA_DQS[0..7]

DDRA_DQS#[0..7] 17

DDRA_DQS[0..7] 17

SMVREF

WIDTH:20MI L SPACING: 20MIL

1

+1.2V

1 2

RC3

1K_0402_5 %

DDR_VTT_C NTL

A A

5

4

2

B

RC29

10K_0402_ 5%

C

QC18

E

3 1

MMBT3904W H_SOT323-3

@

1 2

CPU_DRAMPG_C NTL 55

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE C ENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

MCP (DDR4)

Size Document Number Rev

Custom

Date : Sheet of

Tuesday, April 25, 2017

EG521

1

5 60

0.2

5

DDRB_DQ[0..63]18

D D

C C

B B

4

DDRB_DQ0 DDRB_DQ1 DDRB_DQ2 DDRB_DQ3 DDRB_DQ4 DDRB_DQ5 DDRB_DQ6 DDRB_DQ7 DDRB_DQ8 DDRB_DQ9 DDRB_DQ10 DDRB_DQ11 DDRB_DQ12 DDRB_DQ13 DDRB_DQ14 DDRB_DQ15 DDRB_DQ16 DDRB_DQ17 DDRB_DQ18 DDRB_DQ19 DDRB_DQ20 DDRB_DQ21 DDRB_DQ22 DDRB_DQ23 DDRB_DQ24 DDRB_DQ25 DDRB_DQ26 DDRB_DQ27 DDRB_DQ28 DDRB_DQ29 DDRB_DQ30 DDRB_DQ31 DDRB_DQ32 DDRB_DQ33 DDRB_DQ34 DDRB_DQ35 DDRB_DQ36 DDRB_DQ37 DDRB_DQ38 DDRB_DQ39 DDRB_DQ40 DDRB_DQ41 DDRB_DQ42 DDRB_DQ43 DDRB_DQ44 DDRB_DQ45 DDRB_DQ46 DDRB_DQ47 DDRB_DQ48 DDRB_DQ49 DDRB_DQ50 DDRB_DQ51 DDRB_DQ52 DDRB_DQ53 DDRB_DQ54 DDRB_DQ55 DDRB_DQ56 DDRB_DQ57 DDRB_DQ58 DDRB_DQ59 DDRB_DQ60 DDRB_DQ61 DDRB_DQ62 DDRB_DQ63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U_BGA1356

REV = 1 @

3

?

SKL_U LT

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_M A[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_M A[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_M A[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_M A[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_M A[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_M A[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_M A[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_AC T# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_M A[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1 _MA[15]

DDR1_WE#/DDR1_C AB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1 _MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_M A[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_M A[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_M A[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_M A[0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

1 OF 20

DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

DDR1_PAR

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

?

DDRB_DQS#0 DDRB_DQS0 DDRB_DQS#1 DDRB_DQS1 DDRB_DQS#2 DDRB_DQS2 DDRB_DQS#3 DDRB_DQS3 DDRB_DQS#4 DDRB_DQS4 DDRB_DQS#5 DDRB_DQS5 DDRB_DQS#6 DDRB_DQS6 DDRB_DQS#7 DDRB_DQS7

CPU_DRAMRST#_R SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

2

DDRB_CLK0# 18 DDRB_CLK1# 18 DDRB_CLK0 18 DDRB_CLK1 18

DDRB_CKE0 18 DDRB_CKE1 18

DDRB_CS0# 18 DDRB_CS1# 18 DDRB_ODT0 18 DDRB_ODT1 18

DDRB_MA5 18 DDRB_MA9 18 DDRB_MA6 18 DDRB_MA8 18 DDRB_MA7 18 DDRB_BG0 18 DDRB_MA12 18 DDRB_MA11 18 DDRB_ACT# 18 DDRB_BG1 18

DDRB_MA13 18 DDRB_MA15_CAS# 18 DDRB_MA14_WE # 18 DDRB_MA16_RAS# 18 DDRB_BS0# 18 DDRB_MA2 18 DDRB_BS1# 18 DDRB_MA10 18 DDRB_MA1 18 DDRB_MA0 18 DDRB_MA3 18 DDRB_MA4 18

DDRB_DQS#[0..7]

DDRB_DQS[0..7]

DDRB_ALERT# 18

DDRB_PAR 18

1 2

RC24 121_0402_1%

1 2

RC25 80.6_0402_1%

1 2

RC26 100_0402_1%

1

DDRB_DQS#[0..7] 18

DDRB_DQS[0..7] 18

+1.2V

12

RC22 470_0402_5%

2015/08/20

CPU_DRAMRST#_R

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Title

MCP (DDR4)

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

EG521

6 60

1

6 60

0.2

1 2

CPU_DRAMRST#17,18

A A

5

4

RC23 0_0402_5%

1

CC1

0.01U_0201_25V6-K

EMC_NS@

2

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

5

4

3

2

1

?

UC1E

AW13

AW3

AW2

AY11

AV2

AV3

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2 M1

G3 G2 G1

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKYLAKE-U_BGA1356

REV = 1

@

2.2K_0404_4P2R_5%

PCH_SML1_CLK

PCH_SML1_DAT

D D

C C

B B

SPI_CLK44

SPI_SO44

SPI_SI44

SPI_CS0#44

Check with BIOS, SPI is Dual mode or quad mode

SPI_CLK SPI_CLK_R

SPI_SO

SPI_SI

SPI_CS0# SPI_CS0#_R

+3VS

+3V_SPI

1. If support DS3, connect to +3VS and don't support EC mirror code;

2. If don't support DS3, connect to +3VALW_PCH and support EC mirror c ode.

*

SPI_WP#_R

RC54 15_0402_5%@

SPI_HOLD#_R

RC55 15_0402_5%@

SPI_CS0#

SPI_SO

SPI_WP#

1 2

RC1539 15_0402_5%

1 2

RC53 15_0402_5%

1 2

RC52 15_0402_5%

1 2

RC51 0_0402_5%

+3VALW_PCH

RC171 0_0402_5%

RC172 0_0402_5%@

1 2

UC3

1

/CS

2

DO (IO1)

3

IO2

GND4DI (IO0)

W25Q64JVSSIQ_SO8

1 2

1K_0402_5%

VCC

IO3

CLK

SPI_SO_R

SPI_SI_R

+3V_SPI

12

RC61

RC60

1K_0402_5%

8

SPI_HOLD#

7

SPI_CLK

6

SPI_SI

5

SPI_WP#

SPI_HOLD#

+3V_SPI

BOARD_ID48

KBRST#44

SERIRQ32,44

1

CC8

0.1u_0201_10V6K

2

SPI_CLK_R SPI_SO_R SPI_SI_R SPI_WP#_R SPI_HOLD#_R SPI_CS0#_R

BOARD_ID4

KBRST#

SERIRQ

SKL_U LT

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

LPC

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

1 OF 20

check CLKRUN# / SUS_STAT# signal if need to connect

PM_CLKRUN#

SERIRQ

KBRST#

+3VALW_PCH +3VS

RPC25

1 4

2 3

1 2

RC11 8.2K_0402_5%

1 2

RC12 10K_0402_5%

1 2

RC10 10K_0402_5%

1 2

CC1255 1000P_0201_50V7-K

EMC_NS@

2

G

6 1

QC10A

2N7002KDWH_SOT363-6

D

QC10B

S

2N7002KDWH_SOT363-6

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

@

5

G

3 4

@

S

D

+3VS

PCH_SMB_CLK

R7

PCH_SMB_DATA

R8

SMB_ALERT#

R10

SML0_CLK

R9

SML0_DATA

W2

SML0_ALERT#

W1

PCH_SML1_CLK

W3

PCH_SML1_DAT

V3

SML1_ALERT#

AM7

AY13 BA13 BB13 AY12 BA12

SUS_STAT#

BA11

CLK_PCI_EC_R

AW9

CLK_PCI_TPM_R

AY9

PM_CLKRUN#

AW11

?

DIMM, NGFF

GPU, EC, Thermal Sensor

RC173 22_0402_5% RC1541 22_0402_5%TPM@

EC_SMB_CK2 26,39,44

EC_SMB_DA2 26,39,44

LPC_AD0 32,44 LPC_AD1 32,44 LPC_AD2 32,44 LPC_AD3 32,44 LPC_FRAME# 32,44

12 12

1

TC81@

To enable Direct Connect Interface (DCI), a 150K pull up resist or will need to be added to PCHHOT# pin. This pin must be low during the ris ing edge of RSMRST#. (Refer to WW 52_MOW)

+3VALW_PCH +3VS +3VS

RPC20

2.2K_0404_4P2R_5%

PCH_SMB_CLK

PCH_SMB_DATA

CLK_PCI_EC 44 CLK_PCI_TPM 32 PM_CLKRUN# 32

SMB_ALERT#

SML0_CLK SML0_DATA

SML0_ALERT#

This signal has a weak internal pull-down. 0 = LPC Is selected for EC. (Default) 1 = eSPI Is selected for EC. Notes:

1. The internal pull-down is disabled after RSMRST# de-assert s.

2. This signal is in the primary wel Rising edge of RSMRST#

SML1_ALERT#

1 4

2 3

2.2K_0404_4P2R_5%

RC1564 2.2K_0402_5%@

1 2

RC1569 150K_0402_5%@

1 2

RC1655 150K_0402_5%

QC2A

2N7002KDWH_SOT363-6

12

2.2K_0402_5%

RPC23

14 23

12

2

6 1

D

QC2B

RC1562

G

S

5

G

3 4

D

2N7002KDWH_SOT363-6

+3VALW_PCH

S

RPC24

2.2K_0404_4P2R_5%

1 4

2 3

+3VS

SMB_CLK_S3 18,40

SMB_DATA_S3 18,40

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

MCP (MISC,JTAG,SPI,LPC,SMB)

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

7 60

0.2

5

@DIS For NV and AMD GPU SKU @OPT&GC6 Only for NV GPU SKU @UMA SKU

+3VS

PXS_PWREN_R

PXS_RST#_R

Reserve for GPU sequence

PXS_RST#_R

PXS_RST#

DGPU_PWROK 23,58

PCH_I2C_SDA0 PCH_I2C_SCL0

PCH_TP_INT#

RPC28

1 2

DIS@

DGPU_PWROK

12

RC1559 10K_0402_5%DIS@

RC1641 10K_0402_5%@

RC1557 10K_0402_5%DIS@

D D

CC1259 0.01U _0201_10V6K

+3VS

1 4 2 3

2.2K_0404_4P2R_5%

RC1658 10K_0402_5%

12

RC71K_0402_5% DIS@

12

RC80_0402_5% DIS@

1 2

RC1561 2.2K_0402_5%@

+3VS

PCH_CMOS_ON#33

UART_RX_DEBUG40 UART_TX_DEBUG40

1 2

RC1563 2.2K_0402_5%@

10/25 SIT For I2C T/P Function wei

+3VS

1 2

HDA_SYNC_AUDIO30 HDA_BITCLK_AUDIO30

HDA_SDIN030

HDA_RST_AUDIO#30

PCH_BEEP30

Default Value

*

RC1656 0_0402_5%

1 2

RC1657 0_0402_5%

When Sampled

0*Rising edge

of PCH_PWROK

Rising edge

0

of PCH_PWROK

Rising edge

0

of PCH_PWROK

TP_I2C_SDA045

1 2

PCH_CMOS_ON# PCH_WLAN_OFF# PCH_BT_OFF#

HDA_SDIN0

1 2

RC45 33_0402_5%

1 2

RC46 0_0402_5%

PCH_BEEP

Internal PD 0 = Disable “ Top Swap” mode. (Default) 1 = Enable “ Top Swap” mode.

Internal PD 0 = Disable “ No Reboot” mode. (Default) 1 = Enable “ No Reboot” mode

Internal PD 0 = SPI (Default) 1 = LPC

RC1595 10K_0402_5%@ RC1596 10K_0402_5%

C C

B B

RC1597 10K_0402_5%

+3VALW_PCH

*

HDA_SDO This signal has a weak internal pull-down. 0 = Enable security measures defined in the Flash Descriptor. 1 = Disable Flash Descriptor Security(override). This strap should only be asserted high during external pull-up in manufacturing/debug environments ONLY.

+3VS

12 12 12

double check if need the pull up resisor

+3VS

RC1600 1K_0402_5%@

RC47 1K_0402_5%@

For EMI

1

CC7 10P_0201_50V8F

EMC_NS@

2

HDA_SDOUT_AUDIO30 ME_FLASH44

1 2

RC14 2.2K_0402_5%@

Pin Name Strap Description Configurat ion

SPKR /

Top Swap

GPP_B14

Override

GSPI0_MOSI

No Reboot

A A

/GPP_B18

GSPI1_MOSI /GPP_B22

Boot BIOS Strap Bit BBS

HDA_SDOUT

TP_I2C_SCL045

PCH_WLAN_OFF#40 PCH_BT_OFF#40

HDA_SDOUT

*

4

PXS_PWREN 23

PXS_RST# 26

GPP_B18

GPP_B22

PXS_PWREN_R

1

TC206 @ TC207 @ TC208 @ TC204 @

1 2

RC43 33_0402_5%

1 2

RC42 33_0402_5%

1 2

RC44 33_0402_5%

1 1 1

PCH_I2C_SDA0 PCH_I2C_SCL0

PCH_WLAN_OFF# PCH_BT_OFF#

PXS_RST#_R DGPU_PWROK FB_GC6_EN_R

+3VS

RC1629 10K_0402_5%GC6@

RC1630 10K_0402_5%GC6@

RC1637 10K_0402_5%@

RC1638 10K_0402_5%@

HDA_SYNC HDA_BCLK HDA_SDOUT HDA_SDIN0

HDA_RST#

BOARD_ID10 BOARD_ID9

PCH_BEEP

1 2

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKYLAKE-U_BGA1356

REV = 1 @

3

FB_GC6_EN_R

GPU_EVENT#

FB_GC6_EN_R

GPU_EVENT#

LPSS ISH

UC1G

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKYLAKE-U_BGA1356

REV = 1 @

AUDIO

BA22 AY22 BB22 BA21 AY21

AW22

AY20

AW20

AK10

AW5

FB_GC6_EN_R 26

GPU_EVENT# 26

?

SKL_U LT

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

1 OF 20

?

SKL_U LT

1 OF 20

1 2

RC1558 10K_0402_5%UMA@

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

?

SD_RCOMP

GPP_F23

2

DGPU_PWROK

@

RC1615

1 2

BOARD_ID0 BOARD_ID1

BOARD_ID29

BOARD_ID47

BOARD_ID0

P2

BOARD_ID1

P3 P4

BOARD_ID3

P1

BOARD_ID6

M4

BOARD_ID5PCH_CMOS_ON#

N3

BOARD_ID7

N1

BOARD_ID8

N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2

GPU_EVENT#

12

RC49 200_0402_1%

1

TC205@

PCH_TP_INT# 45

AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

?

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

SD_RCOMP

AB7

AF13

BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5

DIMM_ONLY@

BOARD_ID6 BOARD_ID7 BOARD_ID8 BOARD_ID9 BOARD_ID10

10K_0402_5%

RC1616

1 2

10K_0402_5%

Board ID Descri ption

Board_ID[0:1 ]

Board_ID2

Board_ID3

Board_ID4

Board_ID5

DIMM_ONLY@

12

RC1631

10K_0402_5%

@

12

RC1634

10K_0402_5%

Board_ID [6,7]

15@

14@

DescriptionBoard ID

00

01

10

@

RC1613

1 2

10K_0402_5%

@

RC1614

1 2

10K_0402_5%

00

01

10

11

0

1

0

1

0

1

0

1

12

RC1632

10K_0402_5%

@

12

RC1635

10K_0402_5%

Samsung 8Gb

2400 MT/s

Hynix 8Gb

2400 MT/s

Micron 8Gb

2400 MT/s

RC1611

1 2

RC1612

1 2

14"

15"

17"

Reserved

UMA

DIS

NV GPU

AMD GPU

Reserved

520Z@

320G@

11 SO-DIMM Only

Board_ID8

Board_ID9

Board_ID10

01320G RC 1636

520Z

01Reserved

Reserved

0

Reserved

1

DIS@

1 2

10K_0402_5%

UMA@

RC1610

1 2

10K_0402_5%

12

RC1633

10K_0402_5%

12

RC1636

10K_0402_5%

Stuff R

RC1634 RC1635

RC1631

RC1633

RC1640

RC1639

RC1652

RC1651

1

PX@

RC1609

RC1608

1 2

10K_0402_5%

OPT@

RC1607

1 2

10K_0402_5%

Stuff R

RC1616

RC1614

RC1616 RC1613

RC1615

RC1614

RC1615 RC1613

RC1612

RC1611

RC1610

RC1609

RC1607

RC1608

RC123

RC1606

@

12

RC1639

10K_0402_5%

@

12

RC1640

10K_0402_5%

RC1632RC1634

RC1635

RC1632

@

+3VS

@

+3VS

RC1606

1 2

10K_0402_5%

RC123

10K_0402_5%

1 2

12

RC1651

10K_0402_5%

12

RC1652

10K_0402_5%

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

MCP (LPSS,ISH,AUDIO,SDIO)

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

8 60

0.2

5

4

3

2

1

@DIS For NV and AMD GPU SKU

D D

DGPU

C C

LAN

WLAN

SATA HDD

SATA ODD

Optane Memory

B B

A A

5

PCIE_CRX_GTX_N[0..3]20

PCIE_CRX_GTX_P[0..3]20

PCIE_CTX_C_GRX_N[0..3]20

PCIE_CTX_C_GRX_P[0..3]20

PCIE_CRX_GTX_N0

PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P0

PCIE_CTX_C_GRX_N1 PCIE_CTX_GRX_N1 PCIE_CTX_C_GRX_P1

PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 PCIE_CTX_GRX_P2

PCIE_CTX_C_GRX_N3 PCIE_CTX_GRX_N3 PCIE_CTX_C_GRX_P3 PCIE_CTX_GRX_P3

PCIE_PRX_DTX_N537

PCIE_PRX_DTX_P537 PCIE_PTX_C_DRX_N537 PCIE_PTX_C_DRX_P537

PCIE_PRX_DTX_N640

PCIE_PRX_DTX_P640 PCIE_PTX_C_DRX_N640 PCIE_PTX_C_DRX_P640

SATA_PRX_DTX_N042

SATA_PRX_DTX_P042

SATA_PTX_DRX_N042

SATA_PTX_DRX_P042

SATA_PRX_DTX_N142 SATA_PRX_DTX_P142

SATA_PTX_DRX_N142 SATA_PTX_DRX_P142

PCIE_PRX_DTX_N940

PCIE_PRX_DTX_P940 PCIE_PTX_C_DRX_N940 PCIE_PTX_C_DRX_P940

PCIE_PRX_DTX_N1040

PCIE_PRX_DTX_P1040 PCIE_PTX_C_DRX_N1040 PCIE_PTX_C_DRX_P1040

PCIE_RCOMPN and PCIE_RCOMPP Trace Width: 12-15mil Differential between RCOMPP/RCOMPN

PCIE_PRX_DTX_N1140

PCIE_PRX_DTX_P1140 PCIE_PTX_C_DRX_N1140 PCIE_PTX_C_DRX_P1140

PCIE_PRX_DTX_N1240

PCIE_PRX_DTX_P1240 PCIE_PTX_C_DRX_N1240 PCIE_PTX_C_DRX_P1240

+3VS

SATA2GP

CC1262 0.1u_0201_ 10V6K CC1261 0.1u_0201_ 10V6K

CC1264 0.1u_0201_ 10V6K CC1263 0.1u_0201_ 10V6K

CC22 0.22U_ 0201_6.3V6-K CC23 0.22U_ 0201_6.3V6-K

CC1266 0.22U_0 201_6.3V6-K CC1265 0.22U_0 201_6.3V6-K

1 2

RC119 100_0402_1%

CC1267 0.22U_0 201_6.3V6-K CC1268 0.22U_0 201_6.3V6-K

CC1269 0.22U_0 201_6.3V6-K CC1270 0.22U_0 201_6.3V6-K

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

1 2 1 2

TC20PAD @ TC19PAD @

1 2 1 2

RPC2

RC189 0_0402_5%

ODD_DETECT# SATA0GP

SATA2GP PIRQA#

1 2

CC160.22U_0201_6.3V6-K DIS@ CC140.22U_0201_6.3V6-K DIS@

CC150.22U_0201_6.3V6-K DIS@ CC170.22U_0201_6.3V6-K DIS@

CC180.22U_0201_6.3V6-K DIS@ CC190.22U_0201_6.3V6-K DIS@

CC200.22U_0201_6.3V6-K DIS@ CC210.22U_0201_6.3V6-K DIS@

1 1

PCIE_CRX_GTX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P0

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1

PCIE_CTX_GRX_P1

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2

PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3

PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9

PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10

PCIE_RCOMPN PCIE_RCOMPP

XDP_PRDY# XDP_PREQ#

PIRQA#

PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12 PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12

Add SSD_DET# for Optane memory wei

4

H13 G13 B17 A17

G11 F11 D16 C16

H16 G16 D17 C17

G15 F15 B19 A19

F16 E16 C19 D19

G18 F18 D20 C20

F20 E20 B21 A21

G21 F21 D21 C21

E22 E23 B23 A23

F25 E25 D23 C23

F5

E5

D56 D61

BB11

E28 E27 D24 C24 E30 F30 A25 B25

SSD_DET# 40

UC1H

PCIE/U SB3/SATA

PCIE1_RXN/USB3_5_RXN PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP

PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP

PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP

PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP

PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP

PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP

PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_TXN PCIE7_TXP/SATA0_TXP

PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

PCIE_RCOMPN PCIE_RCOMPP

PROC_PRDY# PROC_PREQ# GPP_A7/PIRQA#

PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_TXN PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

REV = 1 @

USB_OC0# USB_OC1# USB_OC3# USB_OC2#

?

SKL_U LT

SSIC / USB3

USB2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

1 OF 20

RPC17

18 27 36

10K_0804_8P4R_5%

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

45

2015/08/20

USB3_1_RXN

USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN

USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN

USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1 USB2P_1

USB2N_2 USB2P_2

USB2N_3 USB2P_3

USB2N_4 USB2P_4

USB2N_5 USB2P_5

USB2N_6 USB2P_6

USB2N_7 USB2P_7

USB2N_8 USB2P_8

USB2N_9 USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

?

+3VALW_PCH

LC Future Center Secret Data

USB30_RX_N1

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

USB30_RX_P1 USB30_TX_N1 USB30_TX_P1

USB30_RX_N2 USB30_RX_P2 USB30_TX_N2 USB30_TX_P2

USB30_RX_N3 USB30_RX_P3 USB30_TX_N3 USB30_TX_P3

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N4 USB20_P4

USB20_N5 USB20_P5

USB20_N6 USB20_P6

USB20_N7 USB20_P7

USB20_N8 USB20_P8

USB2_COMP USB2_ID USB2_VBUSSENSE

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

GPP_E4 GPP_E5

SATA0GP ODD_DETECT#

SATA2GP

BOARD_ID2

GPP_E4

USB_OC2#

USB30_RX_N1 41 USB30_RX_P1 41 USB30_TX_N1 41

USB30_TX_P1 41

USB30_RX_N2 43 USB30_RX_P2 43 USB30_TX_N2 43 USB30_TX_P2 43

USB30_RX_N3 41 USB30_RX_P3 41 USB30_TX_N3 41 USB30_TX_P3 41

USB20_N1 41 USB20_P1 41

USB20_N2 43 USB20_P2 43

USB20_N3 41 USB20_P3 41

USB20_N4 45 USB20_P4 45

USB20_N5 30 USB20_P5 30

USB20_N6 33 USB20_P6 33

USB20_N7 40 USB20_P7 40

USB20_N8 33 USB20_P8 33

RC118 113_0402_1%

1 2

RC1626 0_0402_5%

1 2

RC1627 1K_0402_5%

USB_OC1# 41

1

TC202PAD@

BOARD_ID2 8

RC1617 10K_0402_5%@

1 2

RC1654 0_0402_5%

8/24 Reserve TYPE_C_OCP# to CPU USB_OC2# wei

2016/08/20

Deciphered Date

2016/08/20

2

LEFT USB3.0

Type-C

LEFT USB3.0

Type-C

LEFT USB3.0

Finger Print

Card reader

Touch panel

BT

Camera

12

1 2

RC1628 0_0402_5%

2016/05/03: Implement as Power Button function for Windows RedStone support

+3VS

12

TYPE_C_OCP# 43

Title

MCP (PCIE,SATA,USB3,USB2)

Size Document Number Re v

Custom

Date: Sheet of

USBRBIAS

Width 20Mil Space 15Mil Length 500Mil

EG521

Tuesday, April 25, 2017

EG521

EC_SMI# 44

1

9 60

0.2

5

D D

C C

B B

check the Pull up resistor

+3VS

RPC4

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

LAN_CLKREQ# WLAN_CLKREQ# SSD_PCIE_CLKREQ# GPU_CLKREQ#

@DIS For NV and AMD GPU SKU

PCIE CLK0 DGPU

Optane memory

PCIE CLK5 WLAN

PCIE CLK4

LAN

CLK_PCIE_GPU#20 CLK_PCIE_GPU20 GPU_CLKREQ#20

CLK_PCIE_SSD#40 CLK_PCIE_SSD40

SSD_PCIE_CLKREQ#40

CLK_PCIE_WLAN#40 CLK_PCIE_WLAN40 WLAN_CLKREQ#40

CLK_PCIE_LAN#37 CLK_PCIE_LAN37 LAN_CLKREQ#37

4

CLK_PCIE_GPU# CLK_PCIE_GPU GPU_CLKREQ#

CLK_PCIE_SSD# CLK_PCIE_SSD SSD_PCIE_CLKREQ#

CLK_PCIE_WLAN# CLK_PCIE_WLAN WLAN_CLKREQ#

CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ#

A36 B36 C38 D38 C36 D36 A38 B38

C31 D31 C33 D33 A31 B31 A33 B33

A29 B29 C28 D28 A27 B27 C27 D27

SKYLAKE-U_BGA1356

REV = 1 @

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

REV = 1 @

UC1I

CSI-2

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

SKL_U LT

CLOCK SIGNALS

?

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

1 OF 20

?

1 OF 20

3

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC_RCOMP

?

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XCLK_BIASREF

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

XTAL24_IN

XTAL24_OUT

RTCX1 RTCX2

SRTCRST#

RTCRST#

?

CSI2_COMP

EMMC_RCOMP

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

1 2

RC73 100_0402_1%

1 2

RC50 200_0402_1%

CLK_PCIE_XDP# CLK_PCIE_XDP

SUSCLK

DIFFCLK_BIASREF

RTC_X1 RTC_X2

SRTC_RST# RTC_RST#

1 1

RC72 2.7K_0402_1%

VCCRTC

RC33 20K_0402_1% RC34 20K_0402_1%

TC85 @ TC87 @

SUSCLK 40

1 2

1 2 1 2

2

1U_0402_6.3V6K

SUSCLK

DIFFCLK_BIASREF

+VCCCLK5

1

CC3

2

1

CC6

2

1 2

RC95 1K_0402_5%@

1 2

RC1555 60.4_0402_1%

Cannonlake@

SRTC_RST# RTC_RST#

12

JCMOS1 SHORT PADS

@

RC1624

1 2

@

0_0402_5%

1

EC_RTC_RST# 44

RTC_X1

RTC_X2

2

CC5 7P_0402_50V8J

1

LC Future Center Secret Data

when single end external clock generator used, this pin should be grounded

Deciphered Date

2

2016/08/20

Title

MCP (CSI2,EMMC,CLOCK)

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

EG521

10 60

1

10 60

0.2

YC1

1 2

12

2015/08/20

RC32 10M_0402_5%

32.768KHZ_9PF_X1A0001410002

2

CC4 7P_0402_50V8J

1

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

5

D D

+3VALW

C C

PLT_RST#26,32,37,40,44

EC_RSMRST#44

SYS_PWROK44 PCH_PWROK44

SUSWARN#44

SUSACK#44

PCIE_WAKE#37,40,44

1 2

RC74 10K_0402_5%

1 2

RC75 8.2K_0402_5%

RC76 1K_0402_5%

RC90 10K_0402_5%

12

1 2

VCCST_PWRGD_R

AC_PRESENT_R

BATLOW#

WAKE#

PCH_LAN_WAKE#

TC21PAD@

Reserve for DS3

Follow CRB change to 1kohm

4

1 2

RC84 0_0402_5%

1 2

RC85 0_0402_5%

1

1 2

RC93 60.4_0402_1%

1 2

RC139 0_0402_5%

1 2

RC126 0_0402_5%

1 2

RC86 0_0402_5%@

1 2

RC79 0_0402_5%@

1 2

RC91 0_0402_5%@

PLT_RST#_R SYS_RESET# PCH_RSMRST#_R

CPU_PROCPWRGD VCCST_PWRGD

SYS_PWROK_R PCH_PWROK_R PCH_DPWROK_R

SUSWARN#_R SUSACK#_R

WAKE# PCH_LAN_WAKE#

UC1K

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWR OK

AR13

GPP_A13/SUSWARN#/SUS PWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKYLAKE-U_BGA1356

REV = 1 @

3

SKL_U LT

?

1 OF 20

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B11/EXT_PWR_GATE#

INTRUDER#

GPP_B2/VRALERT#

?

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

PM_SLP_S3#_R PM_SLP_S4#_R

PM_SLP_SUS#_R

PBTN_OUT#_R AC_PRESENT_R

BATLOW#

PME# INTVRMEN

AC_PRESENT44

2

1 2

RC96 0_0402_5%@

1 2

RC97 0_0402_5%@

1 2

RC89 0_0402_5%@

Reserve for DS3

1 2

RC87 0_0402_5%@

1

TC89@

RC41 330K_0402_5%

RC88 0_0402_5%@

12

1 2

ACIN#44

2

G

PM_SLP_S3# 13,44 PM_SLP_S4# 44

PM_SLP_SUS# 44

PBTN_OUT# 44

VCCRTC

AC_PRESENT_R

13

D

QC8 2N7002KW_SOT323-3

@

S

1

+3VALW_PCH

1 2

RC78 10K_0402_5%@

+3VS

1 2

RC80 10K_0402_5%

1 2

B B

1 2

Add to fix Reset&PWRGD test fail issue

RPC21

1 8 2 7 3 6 4 5

10K_0804_8P4R_5%

A A

1 2

@

10/25 SIT Add to fix PLT_RST# glitch issue wei

5

SUSWARN#_R

SYS_RESET#

PCH_RSMRST#_R

CC12541000P_0201_50V7-K

EMC_NS@

Stuff to fix Reset&PWRGD test fail issue

PCH_PWROK

CC1040.01U_0201_10V6K

PCH_DPWROK_R

CC1031000P_0201_50V7-K

EMC_NS@

SYS_PWROK

CC10147P_0201_25V8-J

EC_RSMRST#

CC12600.01U_0201_10V6K

PCH_RSMRST#_R PCH_PWROK SYS_PWROK

PLT_RST#_R

12

RC92100K_0402_5%

PCH_DPWROK_R

12

RC94100K_0402_1% @

PLT_RST#

CC1294100P_0201_25V8J

1 2

EC_VCCST_PWR GD44

4

RC138 0_0402_5%@

PM_SLP_S3#

1

CC46

0.01U_0201_25V6-K

EMC_NS@

2

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

+3VALW +VCCST_CPU +VCCSTG

5

G

Deciphered Date

RC137 1K_0402_5%

1 2

34

D

QC6B 2N7002KDWH_SOT363-6

@

S

RC136 10K_0402_5%

@

1 2

61

D

2

RC1599 0_0402_5%

DC4

RB751V-40_SOD323-2

G

1 2

QC6A 2N7002KDWH_SOT363-6

@

S

@

2015/08/20

LC Future Center Secret Data

VCCST_PWRGD_R

PCH_DPWROK_R

2

RC1554 1K_0402_5%

@

1 2

RC182 0_0402_5%

RC81 0_0402_5%@

2016/08/20

2

CC140 1000P_0201_50V7-K

EMC_NS@

1

1 2

Reserve for DS3

Title

Size Document Number Re v

Custom

Date: Sheet of

EC_RSMRST#

DPWROK_EC 44

MCP (SYSTEM PWR MANAGEMENT)

EG521

Tuesday, April 25, 2017

EG521

1

11 60

0.2

5

+CPU_CORE +CPU_CORE +VCC_GT

32000mA

D D

1

TC90@

+CPU_CORE

C C

12x10uF 0402, SIT update to 0603 package

1

CC1085

CC1086

2

10U_0402_6.3V6M

1

CC1296

CC1295

2

10U_0402_6.3V6M

1

2

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40 AM32 AM33 AM35 AM37 AM38

G30

K32

AK32

AB62

P62

V62

H63

G61

AC63 AE63

AE62 AG62

AL63

AJ62

CC1080

10U_0603_6.3V6M

UC1L

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO_AE62 VCCEOPIO_AG62

VCCEOPIO_SENSE VSSEOPIO_SENSE

SKYLAKE-U _BGA1356

REV = 1 @

1

CC1236

2

10U_0603_6.3V6M

1

CC1237

2

?

SKL_ULT

CPU POWER 1 OF 4

1

CC1093

2

10U_0603_6.3V6M

1 OF 20

10U_0603_6.3V6M

1

2

VCC_SENSE VSS_SENSE

VCCSTG_G20

CC1092

10U_0603_6.3V6M

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VIDALERT#

VIDSCK

VIDSOUT

1

CC1091

2

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

?

1

CC1089

2

10U_0603_6.3V6M

VCORE_VC C_SEN VCORE_VS S_SEN

CPU_SVID_ ALERT#_R CPU_SVID_ CLK_R CPU_SVID_ DAT_R

1

CC1238

2

10U_0603_6.3V6M

4

VCORE_VC C_SEN

VCORE_VS S_SEN VCCGT_VSS _SEN

VCORE_VC C_SEN 59 VCORE_VS S_SEN 5 9

+VCCSTG

1

CC1097

CC1305

2

10U_0402_6.3V6M

1

CC1299

CC1104

2

10U_0402_6.3V6M

1 2

RC77 100 _0402_1%

1 2

RC82 100 _0402_1%

VR_SVID_ ALRT#5 9

VR_SVID_ CLK59

VR_SVID_ DAT59

+VCC_GT

Backside Cap 8x10uF 0402, SIT update

1

CC1124

CC1240

CC1119

2

10U_0402_6.3V6M

@

3

+CPU_CORE +VCC_GT

SVID

1 2

VCCGT_VCC_ SEN

+VCCST_CPU

12

RC131

56_0402_5%

RC132

RC1544

100_0402_1%

@

100_0402_1%

RC133 220_0 402_1%

RC134 0_040 2_5%

RC1545 0_04 02_5%

1 2

RC83 100 _0402_1%

1 2

RC98 100 _0402_1%

1

CC42

0.1u_02 01_10V6K

@

2

1 2

CPU_SVID_ ALERT#_R

CPU_SVID_ CLK_R

CPU_SVID_ DAT_R

1, Alert# Route Between CLK and Data

1

CC1125

2

10U_0402_6.3V6M

1

CC1126

2

10U_0402_6.3V6M

1

CC1128

CC1127

2

10U_0402_6.3V6M

@

1

CC1129

2

10U_0402_6.3V6M

1

CC1312

CC1311

CC1313

2

10U_0402_6.3V6M

2

+VCC_GT

31000m A

+CPU_CORE

VCCGT_VCC_ SEN59 VCCGT_VSS _SEN59

VCCGT_VCC_ SEN VCCGT_VSS _SEN

UC1M

A48

VCCGT_A48

A53

VCCGT_A53

A58

VCCGT_A58

A62

VCCGT_A62

A66

VCCGT_A66

AA63

VCCGT_AA63

AA64

VCCGT_AA64

AA66

VCCGT_AA66

AA67

VCCGT_AA67

AA69

VCCGT_AA69

AA70

VCCGT_AA70

AA71

VCCGT_AA71

AC64

VCCGT_AC64

AC65

VCCGT_AC65

AC66

VCCGT_AC66

AC67

VCCGT_AC67

AC68

VCCGT_AC68

AC69

VCCGT_AC69

AC70

VCCGT_AC70

AC71

VCCGT_AC71

J43

VCCGT_J43

J45

VCCGT_J45

J46

VCCGT_J46

J48

VCCGT_J48

J50

VCCGT_J50

J52

VCCGT_J52

J53

VCCGT_J53

J55

VCCGT_J55

J56

VCCGT_J56

J58

VCCGT_J58

J60

VCCGT_J60

K48

VCCGT_K48

K50

VCCGT_K50

K52

VCCGT_K52

K53

VCCGT_K53

K55

VCCGT_K55

K56

VCCGT_K56

K58

VCCGT_K58

K60

VCCGT_K60

L62

VCCGT_L62

L63

VCCGT_L63

L64

VCCGT_L64

L65

VCCGT_L65

L66

VCCGT_L66

L67

VCCGT_L67

L68

VCCGT_L68

L69

VCCGT_L69

L70

VCCGT_L70

L71

VCCGT_L71

M62

VCCGT_M62

N63

VCCGT_N63

N64

VCCGT_N64

N66

VCCGT_N66

N67

VCCGT_N67

N69

VCCGT_N69

J70

VCCGT_SENSE

J69

VSSGT_SENSE

SKYLAKE-U _BGA1356

REV = 1 @

SKL_ULT

CPU POWER 2 OF 4

?

VCCGTX_SENSE

VSSGTX_SENSE

1 OF 20

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71 VCCGT_T62 VCCGT_U65 VCCGT_U68

VCCGT_U71 VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71

VCCGT_Y62

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

?

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

1

+CPU_CORE

VCCGTX_SE NSE VSSGTX_S ENSE

1

TC133 @

1

TC134 @

+CPU_CORE

15x1uF 0201, SIT update to 0402 package

1

CC1096

CC1095

2

1U_0402_6.3V6K

B B

+CPU_CORE

1

CC1308

CC1298

2

1U_0402_6.3V6K

@

1

CC1098

2

1

2

CC1099

2

1U_0402_6.3V6K

@

1

CC1301

CC1302

2

1U_0402_6.3V6K

1

CC1100

2

1U_0402_6.3V6K

@

1

CC1303

2

1U_0402_6.3V6K

1

CC1101

CC1102

2

1U_0402_6.3V6K

@

1

CC1304

2

1U_0402_6.3V6K

1

CC1105

2

1U_0402_6.3V6K

@

1

CC1306

2

1U_0402_6.3V6K

@

1

CC1307

2

1U_0402_6.3V6K

@

1

CC1309

CC1310

2

1U_0402_6.3V6K

@

1

CC1109

CC1108

2

1U_0201_6.3V6-M

@

1

CC1300

CC1297

2

1U_0201_6.3V6-M

@

+VCC_GT

Backside Cap 12x1uF 0201, SIT update

1

CC1111

2

1U_0402_6.3V6K

1

CC1115

CC1114

2

1U_0402_6.3V6K

1

CC1116

2

1U_0402_6.3V6K

1

CC1118

CC1122

2

1U_0402_6.3V6K

@

1

CC1241

CC1123

2

1U_0402_6.3V6K

@

1

CC1314

2

1U_0402_6.3V6K

@

SDV Add for U42 wei 02/21

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2016/12/14

LC Future Center Secret Data

Deciphered Date

2

2017/12/13

Titl e

MCP (CPU PWR1)

Size Document Number Re v

Custom

Date : Sheet o f

Tuesday, April 25, 2017

EG521

1

12 60

0.2

5

+1.2V

D D

CD@

C C

2A , 3x22uF, 6x10uF, 4x1uF, SIT update

1

CC1257

+1.2V

CC1258

2

22U_0603_6.3V6-M

1

CC1168

2

10U_0603_6.3V6M

CD@

1 2

RC1497 0_04 02_5%

1 2

RC104 0_040 2_5%

1

CC1256

2

22U_0603_6.3V6-M

1

CC1171

CC1169

2

10U_0402_6.3V6M

1

CC1222

CC1223

2

10U_0603_6.3V6M

+VDDQ_CPU_ CLK

1

CC1229

2

@

1U_0201_6.3V6-M

+VCCSFR_OC

1

CC1244

CC1243

2

10U_0402_6.3V6M

CD@

@

1

CC1228

2

10U_0402_6.3V6M

1

CC85

2

1U_0201_6.3V6-M

1

CC1224

CC1226

CC1225

2

1U_0201_6.3V6-M

CD@

@

+VCCIO

+VCCST_CPU

Reserved for VCCST/VCCSTG /VCCPLL power optimi zed

+VCCST_CPU

4

1

CC1227

2

1U_0201_6.3V6-M

@

RC103 0_040 2_5%

RC1604 0_04 02_5%@

+VDDQ_CPU_ CLK

1 2

RC105 0_040 2_5%

+VCCST_CPU

+VCCSTG

+VCCSFR_OC

+VCCPLL_C PU

+VCCSTG

3

3100mA

5100mA

VCCIO_SE NSE VSSIO_S ENSE

VCCSA_VS S_SEN VCCSA_VC C_SEN

+VCCIO

+VCCSA

1

TC136 @

1

TC137 @

VCCSA_VS S_SEN 5 9 VCCSA_VC C_SEN 59

VCCSA_VC C_SEN

VCCSA_VS S_SEN

RC101 100_0 402_1%

RC102 100_0 402_1%

+1.2V

2800mA

130mA

+VCCST_CPU

120mA

1

2

CC87

1U_0402_6.3V6K

2

+VCCPLL_C PU

CC86

1U_0402_6.3V6K

UC1N

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKYLAKE-U _BGA1356

REV = 1 @

SKL_ULT

CPU POWER 3 OF 4

1 OF 20

VCCIO_AK28 VCCIO_AK30 VCCIO_AL30 VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

VCCSA_AK23 VCCSA_AK25

VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28

VCCSA_J22 VCCSA_J23

VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

VCCIO_SENSE VSSIO_SENSE

VSSSA_SENSE VCCSA_SENSE

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

?

2

+VCCIO

3.1A 2x10uF, 4x1uF

+VCCSA

1

CC1152

2

10U_0402_6.3V6M

1

CC1153

CC1159

CC1158

2

1U_0201_6.3V6-M

10U_0402_6.3V6M

@

4.5A 10x10uF, 7x1uF, SIT update

1

2

CC1132

10U_0603_6.3V6M

1 2

1

2

1

CC1135

CC1133

CC1134

2

10U_0603_6.3V6M

10U_0402_6.3V6M

@

+VCCSA

1

CC1230

1U_0402_6.3V6K

CC1251

10U_0603_6.3V6M

@

1

CC1231

2

1U_0402_6.3V6K

@

1

CC1252

2

10U_0402_6.3V6M

@

RC1605 0_040 2_5%@

CC1232

1U_0402_6.3V6K

CC1253

10U_0402_6.3V6M

1 2

1

CC1139

2

1U_0402_6.3V6K

CD@

1

CC1140

2

1U_0402_6.3V6K

1

CC1145

CC1142

2

1U_0402_6.3V6K

CD@

1

CC1141

CC1144

CC1143

2

1U_0201_6.3V6-M

CD@

1

CC1161

CC1160

2

@

1

CC1136

2

CC1218

2

1U_0402_6.3V6K

1U_0201_6.3V6-M

@

1

2

10U_0603_6.3V6M

1

CC1137

2

10U_0603_6.3V6M

+1.0VALW +VCCST_CPU

Reserved for VCCST/VCCSTG/VCCPLL power optimized

120mA

1

CC84

CC1249

2

1U_0402_6.3V6K

0.1u_0201_10V6K

CC1250

1

2

+VCCIO

1

C1102

2

@

10U_0603_6.3V6M

+VCCST_CPU

1

CC80

2

@

2016/08/20

22U_0603_6.3V6-M

10U_0603_6.3V6M

Titl e

MCP (CPU PWR2)

Size Document Number Re v

Custom

Date : Sheet o f

Tuesday, April 25, 2017

EG521

1

13 60

0.2

+1.0VALW

1 2

B B

A A

5

EC_VCCIO_ EN44

PM_SLP_ S3#11,44

EC_VCCST_E N44

RC128 0_0 402_5%

1 2

DC1

RB751V-4 0_SOD323-2

1 2

RC142 0_0 402_5%

VCCIO_EN

@

1

0.01U_02 01_6.3V7 -K CC77

2

@

VCCST_EN

1

0.01U_02 01_6.3V7 -K CC81

2

@

4

+1.0VALW

CC79

10U_0603_6.3V6M

1

CC72

CC71

2

@

10U_0603_6.3V6M

22U_0603_6.3V6-M

+5VALW

VCCIO_EN

VCCST_EN

1

UC4

1

OUT1_2

IN1_1

2

OUT1_1

IN1_2

3

EN1

4

VBIAS

5

EN2

6

IN2_1

OUT2_2

7

IN2_2

OUT2_1

G5016KD 1U_TDFN14_2X3

14 13

12

CC1293 1000P _0201_50V 7-K

CT1

11

GND

10

CC1292 1000P _0201_50V 7-K

CT2

9 8

15

GPAD

1 2

2

Follow DG470 change to Dual Switch 8/24 wei

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

5

1 2

RC1503 0_0603_5%

+1.0VALW +VCCAMPHY

+1.0VALW +VCCAPLL_1P0

D D

+3VALW_PCH

1 2

RC1504 0_0402_5%

1 2

RC1586 0_0402_5%

+VCCHDA

4

3

1 2

RC1622 0_0402_5%

2

+VCCPGPPG+3VALW_PCH

1

+1.0VALW

1 2

RC1620 0_0402_5%@

VCCMPHYON_1P0_L1

1

CC144

2

1U_0402_6.3V6K

+3VALW_PCH

1

CC156

CC164

CC172

2

@

1U_0402_6.3V6K

+1.8VALW

+1.0VALW

+VCCCLK4

+VCCCLK5

2

1U_0402_6.3V6K

Near Y15

CC173

2

@

20mA

AK15

4mA

AG15

6mA

Y16

8mA

Y15

6mA

T16

161mA

AF16

61mA

AD15

V19

T1

6mA

AA1

1mA

AK17

AK19 BB14

BB10

VCCRTCEXT

35mA

A14

29mA

K19

24mA

L21

33mA

N20

4mA

L19

10mA

A10

AN11 AN13

?

1U_0402_6.3V6K

1mA

+VCCPGPPG

CC174

2

@

1U_0402_6.3V6K

1

CC175

2

@

1U_0402_6.3V6K

1

2

+1.0VALW

1

CC57

2

1U_0402_6.3V6K

1 2

RC15880_0603_5%

1

C1099

2

@

22U_0603_6.3V6-M

1 2

RC15890_0603_5%

1

C1100

2

@

22U_0603_6.3V6-M

+3VALW_PCH

1

CC176

2

@

1U_0402_6.3V6K

1 2

1

CC56

C1098

2

@

1U_0402_6.3V6K

22U_0603_6.3V6-M

+1.0VALW+VCCCLK4

+1.0VALW+VCCCLK5

+1.8VALW

1

CC142

2

RC15870_0603_5%

1U_0402_6.3V6K

+1.0VALW

1

CC149

2

0.1u_0201_10V6K

1

CC55

2

0.1u_0201_10V6K

+3VALW_PCH

1

CC143

2

1U_0402_6.3V6K

1

CC146

2

VCCRTC

1

CC1242

2

1U_0402_6.3V6K

0.1u_0201_10V6K

1

CC158

2

CC153

VCCMPHYON_1P0_L1

11mA

+1.0VALW

Near AB19

1U_0402_6.3V6K

0.696A

1

CC141

2

@

1U_0402_6.3V6K

33mA

1

2

AB19 AB20

P18

AF18 AF19

V20 V21

AL1

K17

L1

N15 N16 N17 P15 P16

K15

L15

V15

AB17

Y18

AD17 AD18

AJ17

AJ19

AJ16

AF20 AF21

T19 T20

AJ21

AK20

N18

CC169

1U_0402_6.3V6K

UC1O

VCCPRIM_1 P0_AB19 VCCPRIM_1 P0_AB20 VCCPRIM_1 P0_P18

VCCPRIM_CO RE_AF18 VCCPRIM_CO RE_AF19 VCCPRIM_CO RE_V20 VCCPRIM_CO RE_V21

DCPDSW_ 1P0

VCCMPHYAON_ 1P0_K17 VCCMPHYAON_ 1P0_L1

VCCMPHYGT_1P 0_N15 VCCMPHYGT_1P 0_N16 VCCMPHYGT_1P 0_N17 VCCMPHYGT_1P 0_P15 VCCMPHYGT_1P 0_P16

VCCAMPHYPL L_1P0_K1 5 VCCAMPHYPL L_1P0_L1 5

VCCAPLL_ 1P0

VCCPRIM_1 P0_AB17 VCCPRIM_1 P0_Y18

VCCDSW_ 3P3_AD17 VCCDSW_ 3P3_AD18 VCCDSW_ 3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1 P0_AF20 VCCSRAM_1 P0_AF21 VCCSRAM_1 P0_T19 VCCSRAM_1 P0_T20

VCCPRIM_3 P3_AJ21

VCCPRIM_1 P0_AK20

VCCAPLLE BB

SKYLAKE-U_BGA1356

REV = 1 @

SKL_ULT

CPU POWER 4 OF 4

?

1 OF 20

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3 P3_V19

VCCPRIM_1 P0_T1

VCCATS_1P 8

VCCRTCPRIM_3 P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

GPP_B0/ CORE_VID0 GPP_B1/ CORE_VID1

+1.0VALW

+VCCDSW_1P0

1

CC171

2

1U_0402_6.3V6K

CD@

+1.0VALW

PCH Internal VRM

1

CC165

2

0.1u_0201_10V6K

75mA

+1.0VALW

C C

Near N15

+VCCAMPHY

+VCCAPLL_1P0

B B

+1.0VALW

1

C1096

2

@

22U_0603_6.3V6-M

1

C1097

2

0.1u_0201_10V6K

1.5A

1

C2084

CC148

CC147

2

@

88mA

1U_0201_6.3V6-M

@

22U_0603_6.3V6-M

1

CC151

2

Near K15

1U_0402_6.3V6K

22mA

1

+1.0VALW

CC154

2

1U_0402_6.3V6K

0.642A

Near AF20

1

CC159

+3VALW_PCH

2

CD@

1U_0402_6.3V6K

+VCCHDA

1

2

CC145

1U_0402_6.3V6K

68mA

+3VALW_PCH

+3VALW

2.574A22mA

1

2

@

Near AF18

22U_0603_6.3V6-M

0.118A

Near A18

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

LC Future Center Se cret Data

Deciphered Date

2

2016/08/20

Titl e

MCP (PCH PWR)

Size Document Number Re v

Custom

Date: Sheet o f

EG521

Tuesday, April 25, 2017

1

14 60

0.2

5

?

SKL_U LT

D D

C C

B B

UC1P

A5

VSS_A5

A67

VSS_A67

A70

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD13

AD16

VSS_AD16

AD19

VSS_AD19

AD20

VSS_AD20

AD21

VSS_AD21

AD62

VSS_AD62

AD8

VSS_AD8

AE64

VSS_AE64

AE65

VSS_AE65

AE66

VSS_AE66

AE67

VSS_AE67

AE68

VSS_AE68

AE69

VSS_AE69

AF1

VSS_AF1

AF10

VSS_AF10

AF15

VSS_AF15

AF17

VSS_AF17

AF2

VSS_AF2

AF4

VSS_AF4

AF63

VSS_AF63

AG16

VSS_AG16

AG17

VSS_AG17

AG18

VSS_AG18

AG19

VSS_AG19

AG20

VSS_AG20

AG21

VSS_AG21

AG71

VSS_AG71

AH13

VSS_AH13

AH6

VSS_AH6

AH63

VSS_AH63

AH64

VSS_AH64

AH67

VSS_AH67

AJ15

VSS_AJ15

AJ18

VSS_AJ18

AJ20

VSS_AJ20

AJ4

VSS_AJ4

AK11

VSS_AK11

AK16

VSS_AK16

AK18

VSS_AK18

AK21

VSS_AK21

AK22

VSS_AK22

AK27

VSS_AK27

AK63

VSS_AK63

AK68

VSS_AK68

AK69

VSS_AK69

AK8

VSS_AK8

AL2

VSS_AL2

AL28

VSS_AL28

AL32

VSS_AL32

AL35

VSS_AL35

AL38

VSS_AL38

AL4

VSS_AL4

AL45

VSS_AL45

AL48

VSS_AL48

AL52

VSS_AL52

AL55

VSS_AL55

AL58

VSS_AL58

AL64

VSS_AL64

SKYLAKE-U_BGA1356

REV = 1 @

GND 1 OF 3

1 OF 20

VSS_AL65

VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71

VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63 VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68 VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48

VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63

VSS_AR8

VSS_AT2 VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35

VSS_AT4 VSS_AT42 VSS_AT56 VSS_AT58

4

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

?

UC1Q

AT63

VSS_AT63

AT68

VSS_AT68

AT71

VSS_AT71

AU10

VSS_AU10

AU15

VSS_AU15

AU20

VSS_AU20

AU32

VSS_AU32

AU38

VSS_AU38

AV1

VSS_AV1

AV68

VSS_AV68

AV69

VSS_AV69

AV70

VSS_AV70

AV71

VSS_AV71

AW10

VSS_AW10

AW12

VSS_AW12

AW14

VSS_AW14

AW16

VSS_AW16

AW18

VSS_AW18

AW21

VSS_AW21

AW23

VSS_AW23

AW26

VSS_AW26

AW28

VSS_AW28

AW30

VSS_AW30

AW32

VSS_AW32

AW34

VSS_AW34

AW36

VSS_AW36

AW38

VSS_AW38

AW41

VSS_AW41

AW43

VSS_AW43

AW45

VSS_AW45

AW47

VSS_AW47

AW49

VSS_AW49

AW51

VSS_AW51

AW53

VSS_AW53

AW55

VSS_AW55

AW57

VSS_AW57

AW6

VSS_AW6

AW60

VSS_AW60

AW62

VSS_AW62

AW64

VSS_AW64

AW66

VSS_AW66

AW8

VSS_AW8

AY66

VSS_AY66

B10

VSS_B10

B14

VSS_B14

B18

VSS_B18

B22

VSS_B22

B30

VSS_B30

B34

VSS_B34

B39

VSS_B39

B44

VSS_B44

B48

VSS_B48

B53

VSS_B53

B58

VSS_B58

B62

VSS_B62

B66

VSS_B66

B71

VSS_B71

BA1

VSS_BA1

BA10

VSS_BA10

BA14

VSS_BA14

BA18

VSS_BA18

BA2

VSS_BA2

BA23

VSS_BA23

BA28

VSS_BA28

BA32

VSS_BA32

BA36

VSS_BA36

F68

VSS_F68

BA45

VSS_BA45

SKYLAKE-U_BGA1356

REV = 1 @

3

SKL_U LT

GND 2 OF 3

?

1 OF 20

VSS_BA49 VSS_BA53 VSS_BA57

VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55

VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70

VSS_C1

VSS_C25

VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58

VSS_D6 VSS_D62 VSS_D66 VSS_D69 VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56

VSS_E6 VSS_E65 VSS_E71

VSS_F1 VSS_F13

VSS_F2 VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38

VSS_F4 VSS_F40 VSS_F42

VSS_BA41

2

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

?

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

VSS_K63

K64

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

SKYLAKE-U_BGA1356

REV = 1 @

SKL_U LT

UC1R

GND 3 OF 3

?

1 OF 20

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21

VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13

VSS_R6 VSS_T15 VSS_T17 VSS_T18

VSS_T2 VSS_T21

VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18

VSS_W13

VSS_W6

VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

?

1

A A

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Title

MCP (VSS)

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

EG521

15 60

1

15 60

0.2

5

CPU_CFG0

*

CPU_CFG1

1

CPU_CFG2

1

XDP_CPU_CFG3

1

CPU_CFG4 CPU_CFG5

1

CPU_CFG6

1

CPU_CFG7

1

CPU_CFG8

1

CPU_CFG9

1

CPU_CFG10

1

CPU_CFG11

1

CPU_CFG12

1

CPU_CFG13

1

CPU_CFG14

1

CPU_CFG15

1

CPU_CFG16

1

CPU_CFG17

1

CPU_CFG18

1

CPU_CFG19

1

CFG_RCOMP

XDP_ITP_PMODE

1

1 1

Default Value

1

D D

RC1618 1K_0402_5%

@

1 2

C C

B B

RC106 1K_0402_5%

1 2

RC162

49.9_0402_1%

1 2

TC142PAD @ TC143PAD @ TC144PAD @

TC146PAD @ TC147PAD @ TC148PAD @ TC153PAD @ TC150PAD @ TC151PAD @ TC152PAD @ TC157PAD @ TC154PAD @ TC155PAD @ TC156PAD @

TC159PAD @ TC158PAD @

TC161PAD @ TC160PAD @

TC166PAD @

TC169PAD @ TC170PAD @

Pin Name Strap Description Configura tion

A A

CFG[4] Display Port

Presence strap

— 1 = eDP Disabled — 0 = eDP Enabled

5

AL25 AL27

BA70 BA68

E68 B67 D65 D67 E70 C68 D68 C67

F71

G69

F70 G68 H70 G71 H69 G70

E63

F63

E66

F66

E60

E8

AY2 AY1

D1 D3

K46 K45

C71 B70

F60

A52

J71

J68

F65 G65

F61 E61

4

UC1S

RESERVED SIGNALS-1

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2 RSVD_AY1

RSVD_D1 RSVD_D3

RSVD_K46 RSVD_K45

RSVD_AL25 RSVD_AL27

RSVD_C71 RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70 RSVD_TP_BA68

RSVD_J71 RSVD_J68

VSS_F65 VSS_G65

RSVD_F61 RSVD_E61

SKYLAKE-U_BGA1356

REV = 1 @

4

SKL_ ULT

?

1 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW 1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW 71 RSVD_TP_AW 70

MSM#

PROC_SELECT#

3

BB68 BB69

AK13 AK12

BB2 BA3

AU5

TP5

AT5

TP6

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

TP4

A69 B69

RSVD_AY3

AY3

D71 C70

C54 D54

AY4

TP1

BB3

TP2

?

VSS_AY71

AY71 AR56

AW71 AW70

AP56

PROC_SELECT#

C64

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

TC167 P AD@

1

TC177 P AD@

1

TC178 P AD@

1

TC168 P AD@

1 2

2015/08/20

3

+1.8VALW

Cannonlake@

RC1582 0_0402_5% RC1583 0_0402_5%

Cannonlake@

XTAL24_IN

need to check with Intel

+VCCST_CPU

R22100K_0402_5% C annonlake@

LC Future Center Secret Data

RC241 0_0201_5%

Deciphered Date

2

?

SKL_ ULT

UC1T

SPAR E

RSVD_AW 69 RSVD_AW 68 RSVD_AU56 RSVD_AW 48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKYLAKE-U_BGA1356

REV = 1 @

1 OF 20

YC2

GND12OSC2

OSC1

GND2

12

RC71 1M_0402_5%

1

24MHZ_6PF_7V24000032

12 12

1 2

XTAL24_OUT RSVD_U12 RSVD_U11

CC12

3.3P_0402_50V8-C

AW69 AW68

AU56

AW48

C7 U12 U11 H11

1

2

need to use 38.4MHz (30ohm) for Cannonlake-u

RC107 0_0402_5%

1 2

RC108 0_0402_5%

1 2

Titl e

2016/08/20

2

MCP (CFG,RESERVED)

Size Document Number Re v

Custom

Date : Shee t o f

F6

RSVD_F6

E3

RSVD_E3

C11

RSVD_C11

B11

RSVD_B11

A11

RSVD_A11

D12

RSVD_D12

C12

RSVD_C12

F52

RSVD_F52

?

3

4

Tuesday, April 25, 2017

1

+VCCST_CPU

1 2

1

12

RC1619 150_0402_5%

@

XTAL24_IN

RSVD_F52

RC240 0_0201_5%

1

CC11

2.7P_0402_50V9-B

2

EG521

XTAL24_OUT

16 60

0.2

5

12

RD39

MD@

240_0402_1%

P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3

T2

M7

T8

L2

M8

L8

K8 K7

K2

F3 G3 A7 B7

E2 E7

N2 N8

L3 L7

P9

M2

K3

T3

N9

P1

F1 H1 A2 D2 E3 A8 D8 E8 C9 H9

F9

12

RD43

MD@

240_0402_1%

UD1

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

F9

ZQ

MT40A512M16HA083EA_FBGA96

UD3

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13

WE_N/A14 CAS_N/A15 RAS_N/A16

CK_C CK_T

CKE

LDQS_C LDQS_T UDQS_C UDQS_T

NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N

BA0 BA1

ACT_N CS_N ALERT_N

BG0

ODT

PAR

TEN

RESET_N

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

ZQ

MT40A512M16HA083EA_FBGA96

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13

D D

C C

B B

A A

DDRA_MA14_WE#5 DDRA_MA15_CAS#5 DDRA_MA16_RAS#5

DDRA_CLK0#5 DDRA_CLK05

DDRA_CKE05

+1.2V +1.2V

1 2

RD65 0_0402_5%@

1 2

RD68 0_0402_5%@

DDRA_BS0#5 DDRA_BS1#5

DDRA_ACT#5 DDRA_CS0#5 DDRA_ALERT#5

DDRA_BG05

DDRA_ODT05

DDRA_PAR5

1 2

RD94 10K_0402_5%MD@

CPU_DRAMRST#6,18

+1.2V

1 2

RD87 0_0402_5%@

1 2

RD88 0_0402_5%@

1 2

RD96 10K_0402_5%MD@

DDRA_MA14_WE# DDRA_MA15_CAS# DDRA_MA16_RAS#

DDRA_CLK0# DDRA_CLK0

DDRA_CKE0

DDRA_DQS#0 DDRA_DQS0 DDRA_DQS#1 DDRA_DQS1

DDRA_DM1 DDRA_DM0

DDRA_BS0# DDRA_BS1#

DDRA_ACT# DDRA_CS0# DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD1 TEN_UD2

CPU_DRAMRST#

@

1

2

CD47

0.1u_0201_10V6K

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13

DDRA_MA14_WE# DDRA_MA15_CAS# DDRA_MA14_WE# DDRA_MA16_RAS#

DDRA_CLK0# DDRA_CLK0

DDRA_CKE0

DDRA_DQS#5 DDRA_DQS5 DDRA_DQS#4 DDRA_DQS4

DDRA_DM4 DDRA_DM5 DDRA_DM6

DDRA_BS0# DDRA_BS1#

DDRA_ACT# DDRA_CS0# DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD3

CPU_DRAMRST#

@

1

2

0.1u_0201_10V6K

CD107

VDDQ10

VREFCA

VDD10

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VREFCA

@

DDRA_DQ2

G2

DDRA_DQ3

DQ0

F7

DDRA_DQ6

DQ1

H3

DDRA_DQ1

DQ2

H7

DDRA_DQ7

DQ3

H2

DDRA_DQ0

DQ4

H8

DDRA_DQ4

DQ5

J3

DDRA_DQ5

DQ6

J7

DDRA_DQ11

DQ7

A3

DDRA_DQ8

DQ8

B8

DDRA_DQ14

DQ9

C3

DDRA_DQ13

DQ10

C7

DDRA_DQ15

DQ11

C2

DDRA_DQ12

DQ12

C8

DDRA_DQ10

DQ13

D3

DDRA_DQ9

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

L9

VDD9

T9

VDD10

A1

VDDQ1

C1

VDDQ2

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

B1

VPP1

R9

VPP2

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

NC

@

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VPP1 VPP2

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

NC

+VREF_CA_MD

M1

E1 K1 N1 T1 B2 G8 E9 K9 M9

T7

G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7

D1 J1 L1 R1 B3 G7 B9 J9 L9 T9

A1 C1 G1 F2 J2 F8 J8 A9 D9 G9

B1 R9

M1

E1 K1 N1 T1 B2 G8 E9 K9 M9

T7

DDRA_DQ47 DDRA_DQ41 DDRA_DQ43 DDRA_DQ40 DDRA_DQ46 DDRA_DQ44 DDRA_DQ42 DDRA_DQ45 DDRA_DQ34 DDRA_DQ37 DDRA_DQ35 DDRA_DQ32 DDRA_DQ39 DDRA_DQ33 DDRA_DQ38 DDRA_DQ36

+1.2V

+VREF_CA_MD

1

MD@

2

.047U_0201_6.3V6K

CD113

1

MD@

2

.047U_0201_6.3V6K

CD115

4

DDRA_MA0

P3

DDRA_MA1

P7

DDRA_MA2

R3

DDRA_MA3

N7

DDRA_MA4

N3

DDRA_MA5

P8

DDRA_MA6

P2

DDRA_MA7

R8

DDRA_MA8

R2

DDRA_MA9

R7

DDRA_MA10

M3

DDRA_MA11 DDRA_MA12

M7

DDRA_MA13

DDRA_MA14_WE# DDRA_MA15_CAS#

M8

DDRA_MA16_RAS#

DDRA_CLK0#

K8

DDRA_CLK0

K7

DDRA_CKE0

K2

DDRA_DQS#2 DDRA_DQS2

G3

DDRA_DQS#3 DDRA_DQS3

B7

DDRA_DM3

1 2

RD66 0_0402_5%@

1 2

RD69 0_0402_5%@

+2.5V_DDR

1

CD@

MD@

1

MD@

2

0.1u_0201_10V6K

CD120

1

2

0.1u_0201_10V6K

CD149

2

1U_0402_6.3V6K

CD123

CD121

+2.5V_DDR

1

CD@

2

1U_0402_6.3V6K

CD@

CD151

CD150

1 2

RD95 10K_0402_5%MD@

@

1

2

CD48

0.1u_0201_10V6K

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3 DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7 DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11 DDRA_MA12 DDRA_MA13

DDRA_MA15_CAS# DDRA_MA16_RAS#

DDRA_CLK0# DDRA_CLK0

DDRA_CKE0

DDRA_DQS#7 DDRA_DQS7 DDRA_DQS#6

+1.2V

1 2

RD89 0_0402_5%@

1 2

RD90 0_0402_5%@

1 2

RD97 10K_0402_5%MD@

DDRA_DQS6

DDRA_DM7

DDRA_BS0# DDRA_BS1#

DDRA_ACT# DDRA_CS0# DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

TEN_UD4

CPU_DRAMRST#

@

1

2

0.1u_0201_10V6K

CD108

DDRA_DM2

DDRA_BS0# DDRA_BS1#

DDRA_ACT# DDRA_CS0# DDRA_ALERT#

DDRA_BG0

DDRA_ODT0

DDRA_PAR

CPU_DRAMRST#

MD@

E2 E7

N2 N8

P9

M2

K3

N9

P1

H1

D2 E3

D8 E8 C9 H9

12

RD40

MD@

240_0402_1%

UD4

P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8

L2 M8 L8

K8 K7

K2

F3 G3 A7 B7

E2 E7

N2 N8

L3 L7 P9

M2

K3

T3

N9

P1

F1 H1 A2 D2 E3 A8 D8 E8 C9 H9

F9

12

MT40A512M16HA083EA_FBGA96

RD44 240_0402_1%

UD2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP

T2

A11 A12/BC_N

T8

A13

L2

WE_N/A14 CAS_N/A15

L8

RAS_N/A16

CK_C CK_T

CKE

F3

LDQS_C LDQS_T

A7

UDQS_C UDQS_T

NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N

BA0 BA1

L3

ACT_N

L7

CS_N ALERT_N

BG0

ODT

T3

PAR

TEN

RESET_N

F1

VSSQ1 VSSQ2

A2

VSSQ3 VSSQ4 VSSQ5

A8

VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

F9

ZQ

MT40A512M16HA083EA_FBGA96

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13

WE_N/A14 CAS_N/A15 RAS_N/A16

CK_C CK_T

CKE

LDQS_C LDQS_T UDQS_C UDQS_T

NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N

BA0 BA1

ACT_N CS_N ALERT_N

BG0

ODT

PAR

TEN

RESET_N

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10

ZQ

VDD10

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9

VDDQ10

VREFCA

3

@

DDRA_DQ18

G2

DDRA_DQ19

DQ0

F7

DDRA_DQ22

DQ1

H3

DDRA_DQ21

DQ2

H7

DDRA_DQ23

DQ3

H2

DDRA_DQ17

DQ4

H8

DDRA_DQ16

DQ5

J3

DDRA_DQ20

DQ6

J7

DDRA_DQ30

DQ7

A3

DDRA_DQ28

DQ8

B8

DDRA_DQ26

DQ9

C3

DDRA_DQ25

DQ10

C7

DDRA_DQ31

DQ11

C2

DDRA_DQ24

DQ12

C8

DDRA_DQ27

DQ13

D3

DDRA_DQ29

DQ14

D7

DQ15

+1.2V

D1

VDD1

J1

VDD2

L1

VDD3

R1

VDD4

B3

VDD5

G7

VDD6

B9

VDD7

J9

VDD8

L9

VDD9

T9

VDD10

A1

VDDQ1

C1

VDDQ2

G1

VDDQ3

F2

VDDQ4

J2

VDDQ5

F8

VDDQ6

J8

VDDQ7

A9

VDDQ8

D9

VDDQ9

G9

VDDQ10

B1

VPP1

R9

VPP2

VREFCA

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

NC

@

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VPP1 VPP2

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

NC

+VREF_CA_MD

M1

E1 K1 N1 T1 B2 G8 E9 K9 M9

T7

G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7

D1 J1 L1 R1 B3 G7 B9 J9 L9 T9

A1 C1 G1 F2 J2 F8 J8 A9 D9 G9

B1 R9

M1

E1 K1 N1 T1 B2 G8 E9 K9 M9

T7

DDRA_DQ59 DDRA_DQ60 DDRA_DQ63 DDRA_DQ56 DDRA_DQ62 DDRA_DQ61 DDRA_DQ58 DDRA_DQ57 DDRA_DQ54 DDRA_DQ53 DDRA_DQ51 DDRA_DQ49 DDRA_DQ50 DDRA_DQ52 DDRA_DQ55 DDRA_DQ48

+1.2V

+VREF_CA_MD

1

MD@

2

0.1u_0201_10V6K

.047U_0201_6.3V6K

CD114

CD122

1

MD@

2

0.1u_0201_10V6K

.047U_0201_6.3V6K

CD153

CD116

DDR_SA_VREFCA5

CD111

0.022U_0201_6.3V6-K

24.9_0402_1% MD@

+2.5V_DDR

1

MD@

2

1U_0402_6.3V6K

CD124

CD125

+2.5V_DDR

1

MD@

2

1U_0402_6.3V6K

CD@

CD154

CD155

2

+1.2V

1

12

MD@

RD45

CD119

2

1 2

MD@

2.7_0402_1%

(1uF_0402_6.3V) *16 Place 4 near each DRAM

1

MD@

2

1U_0402_6.3V6K

CD@

CD126

CD127

(1OuF_0603_6.3V) *5 Place around the DRAMs

1

CD@

2

10U_0603_6.3V6M

CD143

CD142

(1OuF_0603_6.3V) *3 Place around the DRAMs

1

MD@

2

10U_0603_6.3V6M

CD156

CD152

(1uF_0402_6.3V) *8 Place 2 near each DRAM

1

MD@

2

1U_0402_6.3V6K

CD158

CD159

12

1

2

CD128

10U_0603_6.3V6M

1

2

CD@

CD160

1.8K_0402_1%

RD47

1.8K_0402_1%MD@

1

MD@

2

1U_0402_6.3V6K

CD129

1

MD@

2

CD144

1

CD@

2

CD147

1

CD@

2

1U_0402_6.3V6K

CD161

+VREF_CA_MD

1

MD@

CD112

0.1u_0201_10V6K

2

1

CD@

2

1U_0402_6.3V6K

CD@

CD130

CD131

CD132

1

MD@

2

10U_0603_6.3V6M

CD@

CD145

CD146

10U_0603_6.3V6M

1

MD@

CD@

1U_0402_6.3V6K

MD@

2

1U_0402_6.3V6K

CD@

CD163

CD164

CD162

0.1u_0201_10V6K

RD46

1

MD@

2

12

RD48

+1.2V

MD@

+1.2V

CD@

+2.5V_DDR

MD@

+0.6VS

MD@

1

MD@

2

1U_0402_6.3V6K

CD134

CD133

(1OuF_0603_6.3V) *2 Place around the DRAMs

1

MD@

2

1U_0402_6.3V6K

10U_0603_6.3V6M

CD@

CD166

CD165

DDRA_DQ[0..63]

DDRA_DQS#[0..7]

DDRA_DQS[0..7]

DDRA_MA[0..13]

1

MD@

2

1U_0402_6.3V6K

CD135

+1.2V

1

2

+2.5V_DDR

1

2

1

2

10U_0603_6.3V6M

CD167

1

MD@

2

1U_0402_6.3V6K

CD136

CD109 22P_0402_50V8-J

RF@

CD157 22P_0402_50V8-J

RF@

DDRA_CLK0# DDRA_CLK0

DDRA_CS0# DDRA_ODT0

DDRA_CKE0

DDRA_MA0 DDRA_MA1 DDRA_MA2 DDRA_MA3

DDRA_MA4 DDRA_MA5 DDRA_MA6 DDRA_MA7

DDRA_MA8 DDRA_MA9 DDRA_MA10 DDRA_MA11

DDRA_MA12 DDRA_MA13 DDRA_MA14_WE# DDRA_MA15_CAS#

DDRA_MA16_RAS# DDRA_BG0 DDRA_BS0# DDRA_BS1#

DDRA_ACT# DDRA_PAR

DDRA_ALERT#

1

2

1U_0402_6.3V6K

CD@

CD137

DDRA_DQ[0..63] 5

DDRA_DQS#[0..7] 5

DDRA_DQS[0..7] 5

DDRA_MA[0..13] 5

MD@

RD49 36_0402_1%MD@ RD50 36_0402_1%MD@

RD51 34.8_0402_1%MD@ RD52 34.8_0402_1%MD@

RD53 34.8_0402_1%MD@

RD54 34.8_0402_1%MD@ RD55 34.8_0402_1%MD@ RD56 34.8_0402_1%MD@ RD57 34.8_0402_1%MD@

RD58 34.8_0402_1%MD@ RD59 34.8_0402_1%MD@ RD60 34.8_0402_1%MD@ RD61 34.8_0402_1%MD@

RD62 34.8_0402_1%MD@ RD63 34.8_0402_1%MD@ RD64 34.8_0402_1%MD@ RD67 34.8_0402_1%MD@

RD70 34.8_0402_1%MD@ RD71 34.8_0402_1%MD@ RD72 34.8_0402_1%MD@ RD73 34.8_0402_1%MD@

RD74 34.8_0402_1%MD@ RD75 34.8_0402_1%MD@ RD76 34.8_0402_1%MD@ RD77 34.8_0402_1%MD@

RD78 34.8_0402_1%MD@ RD79 34.8_0402_1%MD@

RD86 49.9_0402_1%MD@

1

2

1U_0402_6.3V6K

CD138

1

CD110 22P_0402_50V8-J

RF@

2

1

CD148 22P_0402_50V8-J

RF@

2

+0.6VS

1 2 1 2

1 2

1 2 1 2 1 2 1 2

1 2 1 2

1 2

1

2

1U_0402_6.3V6K

CD@

CD139

1

CD168 22P_0402_50V8-J

RF@

2

1

+0.6VS

+1.2V

1

MD@

2

1U_0402_6.3V6K

CD140

CD141

1

CD169 22P_0402_50V8-J

RF@

2

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

2

2016/12/14

LC Future Center Secret Data

Deciphered Date

2017/12/13

Title

DDR4 Memory Down

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

1

EG523

17 60

0.2

5

DDR4 SO-DIMM

+1.2V +1.2V +1.2V+1.2V+1.2V +1.2V +1.2V +1.2V

DDRB_DQ12

DDRB_DQ13

DDRB_DQS#1 DDRB_DQS1

12

RD93 240_0402_1%

DDRB_DQ10

DDRB_DQ14

DDRB_DQ0

DDRB_DQ6

DDRB_DQ7

DDRB_DQ3

DDRB_DQ18

DDRB_DQ16

DDRB_DQS#2 DDRB_DQS2

DDRB_DQ22

DDRB_DQ23

DDRB_DQ27

DDRB_DQ28

DDRB_DQ25

DDRB_DQ30

DDRB_DQS#8 DDRB_DQS8

DDRB_CKE0

DDRB_BG1 DDRB_BG0

DDRB_MA12 DDRB_MA9

DDRB_MA8 DDRB_MA6

1

CD13

0.022U_0201_6.3V6-K

2

12

RD6

24.9_0402_1%

0.1u_0201_10V6K

D D

+1.2V

RD92

240_0402_1%

C C

DDRB_CKE06

DDRB_BG16 DDRB_BG06

DDRB_MA126 DDRB_MA96

DDRB_MA86 DDRB_MA66

B B

DDR_SB_VREFCA5

RD4

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129

CD117

1 2

2_0402_5%

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99

1

2

JDDR1A

VSS_1 DQ5 VSS_3 DQ1 VSS_5 DQS0_C

DM0_n/DBIO_n/NC DQS0_t VSS_8 DQ7 VSS_10 DQ3 VSS_12 DQ13 VSS_14 DQ9 VSS_16 DM1_n/DBl1_n/NC VSS_17 DQ15 VSS_19 DQ10 VSS_21 DQ21 VSS_23 DQ17 VSS_25 DQS2_c DQS2_t VSS_28 DQ23 VSS_30 DQ19 VSS_32 DQ29 VSS_34 DQ25 VSS_36 DM3_n/DBl3_n/NC VSS_37 DQ30 VSS_39 DQ26 VSS_41 CB5/NC VSS_43 CB1/NC VSS_45 DQS8_c DQS8_t VSS_48 CB2/NC VSS_50 CB3/NC VSS_52 CKE0 VDD_1 BG1 BG0 VDD_3 A12 A9 VDD_5 A8 A6 VDD_7

ARGOS_D4AS0-26001-1P60

ME@

DM2_n/DBl2_n/NC

DM8_n/DBI8_n/NC

+1.2V

12

RD3 1K_0402_1%

12

RD5 1K_0402_1%

VSS_11

VSS_13

VSS_15

DQS1_c

DQS1_t VSS_18

VSS_20

VSS_22

VSS_24

VSS_26

VSS_27

VSS_29

VSS_31

VSS_33

VSS_35

DQS3_c

DQS3_t VSS_38

VSS_40

VSS_42 CB4/NC VSS_44 CB0/NC VSS_46

VSS_47 CB6/NC VSS_49 CB7/NC VSS_51

RESET_n

ALERT_n

VSS_2

VSS_4

VSS_6

VSS_7

VSS_9

DQ12

DQ14

DQ11

DQ20

DQ16

DQ22

DQ18

DQ28

DQ24

DQ31

DQ27

CKE1 VDD_2 ACT_n

VDD_4

VDD_6

VDD_8

DQ4

DQ0

DQ6

DQ2

DQ8

A11

A7

A5 A4

4

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

Note: VREF trace width:20 mils at least

Spacing:20mils to other signal/planes Place near DIMM scoket

+VREF_CA_DIMM

1

CD14

0.1u_0201_10V6K

2

DDRB_DQ9

DDRB_DQ8

DDRB_DQ11

DDRB_DQ15

DDRB_DQ5

DDRB_DQ4

DDRB_DQS#0 DDRB_DQS0

DDRB_DQ1

DDRB_DQ2

DDRB_DQ20

DDRB_DQ21

DDRB_DQ17

DDRB_DQ19

DDRB_DQ24

DDRB_DQ29

DDRB_DQS#3 DDRB_DQS3

DDRB_DQ26

DDRB_DQ31

CPU_DRAMRST# DDRB_CKE1

DDRB_ACT# DDRB_ALERT#

DDRB_MA11 DDRB_MA7

DDRB_MA5 DDRB_MA4

DDRB_DQ[0..63]

DDRB_DQS#[0..7]

DDRB_DQS[0..7]

DDRB_CKE1 6

DDRB_ACT# 6 DDRB_ALERT# 6

DDRB_MA11 6 DDRB_MA7 6

DDRB_MA5 6 DDRB_MA4 6

1

CD3

0.1u_0201_10V6K

@

2

+1.2V

3

DDRB_DQ[0..63] 6

DDRB_DQS#[0..7] 6

DDRB_DQS[0..7] 6

CPU_DRAMRST# 6,17

RD1

+3VS

RD2

+2.5V_DDR

2

1

2

CD6

1U_0402_6.3V6K

CD118

JDDR1B

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

VPP_1

259

VPP_2

261

GND_1

ARGOS_D4AS0-26001-1P60

ME@

@

1

2

1U_0402_6.3V6K

10U_0603_6.3V6M

CD7

EVENT_n

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

RAS_n/A16

VDD_16

CAS_n/A15

VDD_18

C0/CS2_n/NC

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58

DM4_n/DBl4_n/NC

VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41

VSS_67

DQS5_c

DQS5_t VSS_70

DQ47

VSS_72

DQ43

VSS_74

DQ53

VSS_76

DQ48

VSS_78

DM6_n/DBl6_n/NC

VSS_79

DQ54

VSS_81

DQ50

VSS_83

DQ60

VSS_85

DQ57

VSS_87

DQS7_c

DQS7_t VSS_90

DQ63

VSS_92

DQ59

VSS_94

GND_2

1

2

10U_0603_6.3V6M

CD8

CD@

132

A2

134 136 138 140 142 144

A0

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254

SDA

256

SA0

258

Vtt

260

SA1

262

+2.5V_DDR+0.6VS

CD@

DDRB_MA2 DDRB_EVENT#

DDRB_CLK1 DDRB_CLK1#

DDRB_MA0

DDRB_MA10

DDRB_BS0# DDRB_MA16_RAS#

DDRB_MA15_CAS# DDRB_MA13

+VREF_CA_DIMM DDRB_SA2

DDRB_DQ36

DDRB_DQ37

DDRB_DQ34

DDRB_DQ35

DDRB_DQ45

DDRB_DQ44

DDRB_DQS#5 DDRB_DQS5

DDRB_DQ46

DDRB_DQ42

DDRB_DQ52

DDRB_DQ49

DDRB_DQ55

DDRB_DQ51

DDRB_DQ56

DDRB_DQ61

DDRB_DQS#7 DDRB_DQS7

DDRB_DQ62

DDRB_DQ63

SMB_DATA_S3 DDRB_SA0

DDRB_SA1

1

2

10U_0603_6.3V6M

CD9

CD11

CD10

CD@

1

2

1

CD5

0.1u_0201_10V6K

2

DDRB_MA3 DDRB_MA1

DDRB_CLK0 DDRB_CLK0#

DDRB_PAR

DDRB_BS1#

DDRB_CS0# DDRB_MA14_WE#

DDRB_ODT0 DDRB_CS1#

DDRB_ODT1

DDRB_DQ32

DDRB_DQ33

DDRB_DQS#4 DDRB_DQS4

DDRB_DQ39

DDRB_DQ38

DDRB_DQ41

DDRB_DQ40

DDRB_DQ47

DDRB_DQ43

DDRB_DQ53

DDRB_DQ48

DDRB_DQS#6 DDRB_DQS6

DDRB_DQ54

DDRB_DQ50

DDRB_DQ60

DDRB_DQ57

DDRB_DQ59

DDRB_DQ58

SMB_CLK_S3 +VDD_SPD

+VPP

DDRB_MA36 DDRB_MA16

DDRB_CLK06 DDRB_CLK0#6

DDRB_PAR6

DDRB_BS1#6

DDRB_CS0#6 DDRB_MA14_WE#6

DDRB_ODT06 DDRB_CS1#6

DDRB_ODT16

SMB_CLK_S37, 40 SMB_DATA_S3 7,40

1 2

0_0603_5%

CD4

2.2U_0402_6.3V6M

1 2

0_0603_5%

Layout Note: Place near DIMM

1

+1.2V

12

RD91

240_0402_1%

@

DDRB_MA2 6

DDRB_CLK1 6 DDRB_CLK1# 6

DDRB_MA0 6

DDRB_MA10 6

DDRB_BS0# 6 DDRB_MA16_RAS# 6

DDRB_MA15_CAS# 6 DDRB_MA13 6

@

1

2

0.1u_0201_10V6K

CD1

CD2

2.2U_0402_6.3V6M

+0.6VS

1

2

1U_0402_6.3V6K

CD12

1

2

10U_0603_6.3V6M

CD20

CD19

+3VS +3VS +3VS

12

RD7 0_0402_5%

@

A A

DDRB_SA0 DDRB_SA1 DDRB_SA2

12

RD10 0_0402_5%

12

RD8 0_0402_5%

12

RD11 0_0402_5%

@

12

RD9 0_0402_5%

@

12

RD12 0_0402_5%

SPD Address = 2H

5

4

CD@

+1.2V

1

EMC_NS@

2

4.7U_0402_6.3V6M

CD15

CD16

For EMC

Security Classification LC Future Center Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

2

10U_0603_6.3V6M

CD21

1

EMC_NS@

2

0.1u_0201_10V6K

4.7U_0402_6.3V6M CD17

10U_0603_6.3V6M

CD23

CD22

CD@

RF@

1

EMC_NS@

2

0.1u_0201_10V6K CD36

CD18

Near JDDRL1

2015/08/20

3

1

2

10U_0603_6.3V6M

CD25

CD24

RF@

1

2

33P_0402_50V8J

CD37

Deciphered Date

1

2

10U_0603_6.3V6M

CD27

CD26

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

CD28

2016/08/20

1

2

1U_0402_6.3V6K

CD29

CD@

1

2

CD30

1

2

CD33

CD@

2

1U_0402_6.3V6K

CD34

EG521

1U_0402_6.3V6K

1

1U_0402_6.3V6K

Custom

Date: Sheet of

1U_0402_6.3V6K

CD31

CD32

Title

DDR4 SO-DIMM

Size

Document Number Re v

Tuesday, April 25, 2017

18 60

0.2

5

4

3

2

1

N16x GPIO

GPIO I/O

GPIO0

GPIO1

D D

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

C C

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

OVERT

ACTIVE Function Description

-

OUT

IN

OUT

I/O

I/O N/A

OUT

IN

OUT

IN

GPU Core VDD PWM control signal

FB Enable for GC6 2.0

N/A

GPU power sequencin g---3V3_MAIN_EN

N/A

-

GPU wake signal for GC6 2.0

N/A

-

System side PCIe reset Monitor

2.2K Pull-up

FBVREF_ALTV for GD DR5

-

AC Power Detect Input

-

Phase Shedding

N/A

IN

N/A

IN

N/A

IN

N/A

OUT

GPU PCIe self-reset con trol

Active Low Thermal Catastrophic Over Temperature

(10K pull High)

Performance Mode P0 TDP and EDP-Continuous current (GDDR5)

FBVDDQ

Mem

(W)(W)

Min Core Clk

849

(V)

TBD

NVVDD

(A)

191.616

GPU

Products

N16S-GMR

N16S-GT R

18 1.7 967 26.5 2 4.2 8 00 60

FBVDD

(GPU+Mem )

(1.35V) (1.35V)

(A)

(W)

TBD TBD

2

(W)

TBD

(A)

4.2

TBD

(1.05V) (6)

(mA)

800 6 0

Other

(3.3V)

(mA)(MHz)

(W)(W)

N16x Multi-level Straps

Physical Strapping pin

ROM_SCLK

ROM_SI

ROM_SO PCIE_CF G

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

Power Rail

+3VGS

Logical Strapping Bit3

SOR3_EXPOSE D

DEVID_SE L

Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)

Reserved(keep pull-up and pull-down footprint and not stuff by default)

Logical Strapping Bit2

SOR2_EXPOSE D SOR1_EXPOSE D SOR0_EXPOSED

Logical Strapping Bit1

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

(W)

TBD

Logical Strapping Bit0

RAM_CFG[0]

VGA_DEVI CESMB_ALT_ ADDR

N15V-GM Power Sequence

B B

+3VG_AON

+VGA_COR E

+1.05VS_ VGA

+1.35VGS

Other Power rail

A A

+3VG_AON

5

tNVVDD >0

tPEX_VDD >0

1. all power rail ramp up time should be larger than 40us~4ms

Tpower-off <10ms

1.all GPU power rails should be turned off within 10ms

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

VGA Notes List

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

19 60

0.2

5

4

3

2

1

1/14 PCI_EXPRESS

PLT_RST_VGA#26

D D

C C

B B

0.1u_0201_10V6K

GPU_CLKREQ#10

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_N3 PCIE_C RX_C_GTX_N3

PCIE_CRX_GTX_N[0..3]9

PCIE_CRX_GTX_P[0..3]9

PCIE_CTX_C_GRX_N[0..3]9

PCIE_CTX_C_GRX_P[0..3]9

+1.8VGS

RV40 0_0402_5%

OPT@

1 2

1

CV23

@

2

G

1 3

D

S

QV5 LBSS139WT1G_SC70-3

OPT@

1 2

RV48

@

0_0402_5%

CLK_PCIE_GPU10 CLK_PCIE_GPU#10

1 2

CV10 0.22U_0201_6.3V6-KOPT@

1 2

CV13 0.22U_0201_6.3V6-KOPT@

1 2

CV8 0.22U_0201_6.3V6-KOPT@

1 2

CV9 0.22U_0201_6.3V6-KOPT@

1 2

CV6 0.22U_0201_6.3V6-KOPT@

1 2

CV7 0.22U_0201_6.3V6-KOPT@

1 2

CV4 0.22U_0201_6.3V6-KOPT@

1 2

CV5 0.22U_0201_6.3V6-KOPT@

+1.8VG_AON

RV44 10K_0402_5%

OPT@

1 2

RV46 10K_0402_5%

@

1 2

CLK_REQ_GPU#

PLT_RST_VGA#

CLK_REQ_GPU#

CLK_PCIE_GPU CLK_PCIE_GPU#

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0

PCIE_CRX_C_GTX_N1PCIE_CRX_GTX_N1

PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1

PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2

PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2

PCIE_CRX_C_GTX_P3PCIE_CRX_GTX_P3

PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

AC7

PEX_RST_N

AC6

PEX_CLKREQ_N

AE8

PEX_REFCLK

AD8

PEX_REFCLK_N

AC9

PEX_TX0

AB9

PEX_TX0_N

AG6

PEX_RX0

AG7

PEX_RX0_N

AB10

PEX_TX1

AC10

PEX_TX1_N

AF7

PEX_RX1

AE7

PEX_RX1_N

AD11

PEX_TX2

AC11

PEX_TX2_N

AE9

PEX_RX2

AF9

PEX_RX2_N

AC12

PEX_TX3

AB12

PEX_TX3_N

AG9

PEX_RX3

AG10

PEX_RX3_N

AB13

PEX_TX4

AC13

PEX_TX4_N

AF10

PEX_RX4

AE10

PEX_RX4_N

AD14

PEX_TX5

AC14

PEX_TX5_N

AE12

PEX_RX5

AF12

PEX_RX5_N

AC15

PEX_TX6

AB15

PEX_TX6_N

AG12

PEX_RX6

AG13

PEX_RX6_N

AB16

PEX_TX7

AC16

PEX_TX7_N

AF13

PEX_RX7

AE13

PEX_RX7_N

AD17

PEX_TX8

AC17

PEX_TX8_N

AE15

PEX_RX8

AF15

PEX_RX8_N

AC18

PEX_TX9

AB18

PEX_TX9_N

AG15

PEX_RX9

AG16

PEX_RX9_N

AB19

PEX_TX10

AC19

PEX_TX10_N

AF16

PEX_RX10

AE16

PEX_RX10_N

AD20

PEX_TX11

AC20

PEX_TX11_N

AE18

PEX_RX11

AF18

PEX_RX11_N

AC21

PEX_TX12

AB21

PEX_TX12_N

AG18

PEX_RX12

AG19

PEX_RX12_N

AD23

PEX_TX13

AE23

PEX_TX13_N

AF19

PEX_RX13

AE19

PEX_RX13_N

AF24

PEX_TX14

AE24

PEX_TX14_N

AE21

PEX_RX14

AF21

PEX_RX14_N

AG24

PEX_TX15

AG25

PEX_TX15_N

AG21

PEX_RX15

AG22

PEX_RX15_N

N17S-G1-A1_GB2C-64-595 @

COMMON? INS28344821UV1A

NearUnder GPU and PS

AA22

PEX_DVDD_1

AB23

PEX_DVDD_2

AC24

PEX_DVDD_3

AD25

PEX_DVDD_4

AE26

PEX_DVDD_5

AE27

PEX_DVDD_6

2000mA

AA10

PEX_HVDD_1

AA12

PEX_HVDD_2

AA13

PEX_HVDD_3

AA16

PEX_HVDD_4

AA18

PEX_HVDD_5

AA19

PEX_HVDD_6

AA20

PEX_HVDD_7

AA21

PEX_HVDD_8

AB22

PEX_HVDD_9

AC23

PEX_HVDD_10

AD24

PEX_HVDD_11

AE25

PEX_HVDD_12

AF26

PEX_HVDD_13

AF27

PEX_HVDD_14

PEX_PLL_HVDD_1 PEX_PLL_HVDD_2

AA8 AA9

PEX LANES 15 - 4 ARE DEFEATURED

PEX_TERMP

AF25

PEX_TERMP

1

OPT@

2

CV48

1U_0402_6.3V6K

Under GPU (below 150mils)

1

OPT@

2

1U_0402_6.3V6K

CV33

CV672

1

OPT@

2

CV49

CV668

4.7U_0402_6.3V6M

1

OPT@

2

1U_0402_6.3V6K

CV673

CV674

Under GPU(below 150mils)

1

OPT@

2

CV55

0.1u_0201_10V6K

12

1

OPT@

2

CV669

RV352.49K_0402_1% OPT@

4.7U_0402_6.3V6M

Near GPU

1

OPT@

2

CV675

2

OPT@

1

CV670

1

OPT@

2

CV37

4.7U_0402_6.3V6M

RV227 0_0402_5%OPT@

2

OPT@

1

10U_0603_6.3V6M

CV671

1 2

1

OPT@

2

CV43

10U_0603_6.3V6M

GPU and PS

2

OPT@

1

CV676

10U_0603_6.3V6M

+1.0VGS

22U_0603_6.3V6-M

+1.8VGS

2

OPT@

1

CV39

For RF

1

RF@

OPT@

2

10U_0603_6.3V6M

CV677

CV215

22U_0603_6.3V6-M

33P_0402_50V8J

PEX_DVDD/Q Decouling

MLCC

1.0uF

4.7uF

10uF

22uF

Q'ty

1

3

2

1

PEX_HVDD/Q Decouling

MLCC

1.0uF

4.7uF

10uF

Q'ty

2

22uF 1

+1.8VGS

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

N17S_PCIE Interface

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

20 60

0.2

5

4

3

2

1

2/14 FBA

FBA_D0

E18

FBA_D0

FBA_D1

F18

FBA_D1

FBA_D2

FBA_D[0..63]27,28

FBA_CMD[31..0]27, 28

FBA_EDC[7..0]27,28

FBA_DBI[7..0]27,28

D D

C C

B B

E16

FBA_D2

FBA_D3

F17

FBA_D3

FBA_D4

D20

FBA_D4

FBA_D5

D21

FBA_D5

FBA_D6

F20

FBA_D6

FBA_D7

E21

FBA_D7

FBA_D8

E15

FBA_D8

FBA_D9

D15

FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3 FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

FBA_D9

F15

FBA_D10

F13

FBA_D11

C13

FBA_D12

B13

FBA_D13

E13

FBA_D14

D13

FBA_D15

B15

FBA_D16

C16

FBA_D17

A13

FBA_D18

A15

FBA_D19

B18

FBA_D20

A18

FBA_D21

A19

FBA_D22

C19

FBA_D23

B24

FBA_D24

C23

FBA_D25

A25

FBA_D26

A24

FBA_D27

A21

FBA_D28

B21

FBA_D29

C20

FBA_D30

C21

FBA_D31

R22

FBA_D32

R24

FBA_D33

T22

FBA_D34

R23

FBA_D35

N25

FBA_D36

N26

FBA_D37

N23

FBA_D38

N24

FBA_D39

V23

FBA_D40

V22

FBA_D41

T23

FBA_D42

U22

FBA_D43

Y24

FBA_D44

AA24

FBA_D45

Y22

FBA_D46

AA23

FBA_D47

AD27

FBA_D48

AB25

FBA_D49

AD26

FBA_D50

AC25

FBA_D51

AA27

FBA_D52

AA26

FBA_D53

W26

FBA_D54

Y25

FBA_D55

R26

FBA_D56

T25

FBA_D57

N27

FBA_D58

R27

FBA_D59

V26

FBA_D60

V27

FBA_D61

W27

FBA_D62

W25

FBA_D63

D19

FBA_DQM0

D14

FBA_DQM1

C17

FBA_DQM2

C22

FBA_DQM3

P24

FBA_DQM4

W24

FBA_DQM5

AA25

FBA_DQM6

U25

FBA_DQM7

E19

FBA_DQS_WP0

C15

FBA_DQS_WP1

B16

FBA_DQS_WP2

B22

FBA_DQS_WP3

R25

FBA_DQS_WP4

W23

FBA_DQS_WP5

AB26

FBA_DQS_WP6

T26

FBA_DQS_WP7

F19

FBA_DQS_RN0

C14

FBA_DQS_RN1

A16

FBA_DQS_RN2

A22

FBA_DQS_RN3

P25

FBA_DQS_RN4

W22

FBA_DQS_RN5

AB27

FBA_DQS_RN6

T27

FBA_DQS_RN7

D23

FB_VREF

N17S-G1-A1_GB2C-64-595 @

COMMON? INS28351000UV1B

FB_PLL_AVDD_1

FB_PLL_AVDD_2

FB_REFPLL_AVDD

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 FBA_CMD32 FBA_CMD34 FBA_CMD35

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_CMD0

C27

FBA_CMD1

C26

FBA_CMD2

E24

FBA_CMD3

F24

FBA_CMD4

D27

FBA_CMD5

D26

FBA_CMD6

F25

FBA_CMD7

F26

FBA_CMD8

F23

FBA_CMD9

G22

FBA_CMD10

G23

FBA_CMD11

G24

FBA_CMD12

F27

FBA_CMD13

G25

FBA_CMD14

G27

FBA_CMD15

G26

FBA_CMD16

M24

FBA_CMD17

M23

FBA_CMD18

K24

FBA_CMD19

K23

FBA_CMD20

M27

FBA_CMD21

M26

FBA_CMD22

M25

FBA_CMD23

K26

FBA_CMD24

K22

FBA_CMD25

J23

FBA_CMD26

J25

FBA_CMD27

J24

FBA_CMD28

K27

FBA_CMD29

K25

FBA_CMD30

J27

FBA_CMD31

J26 B19 F22

RV121 60.4_0402_1%@

J22

RV122 60.4_0402_1%@

FBA_CLK0

D24

FBA_CLK0#

D25

FBA_CLK1

N22

FBA_CLK1#

M22

FBA_WCLK01

D18

FBA_WCLK01#

C18

FBA_WCLK23

D17

FBA_WCLK23#

D16

FBA_WCLK45

T24

FBA_WCLK45#

U24

FBA_WCLK67

V24

FBA_WCLK67#

V25

F16

P22

Place close to ball

H22

+1.35VGS

12

OPT@

RV209 10K_0402_1%

12

RV211 10K_0402_1%

+FB_PLLAVDD+1.8VGS

200mA

+FB_PLLAVDD

1

OPT@

2

CV111

22U_0603_6.3V6-M

RV210

10K_0402_1%

FBA_CMD14

FBA_CMD30

FBA_CMD13

FBA_CMD29

RV212

10K_0402_1%

+1.35VGS

12 12

FBA_CLK0 27 FBA_CLK0# 27 FBA_CLK1 28 FBA_CLK1# 28

FBA_WCLK01 27 FBA_WCLK01# 27 FBA_WCLK23 27 FBA_WCLK23# 27 FBA_WCLK45 28 FBA_WCLK45# 28 FBA_WCLK67 28 FBA_WCLK67# 28

N17S update to 1.8VGS

30ohms (ESR=0.01) Bead

1 2

LV4

SBK160808T-300Y-N

Place close to BGA

Under GPU Near GPU

@

1

OPT@

+FB_PLLAVDD

2

OPT@

1

0.1u_0201_10V6K

CV115

1

OPT@

2

CV59

CV58

0.1u_0201_10V6K

2

0.1u_0201_10V6K

CV710

OPT@

2

0.1u_0201_10V6K

CV711

0.1u_0201_10V6K

CV112

CV113

N17S Add 2x0.1u

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

N17S_MEM Interface

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

21 60

0.2

5

COMMON? INS28353114UV1C

11/14 NVVDD

K10

VDD_001

K12

VDD_002

K14

VDD_003

K16

VDD_004

K18

VDD_005

L13

VDD_006

L15

VDD_007

M10

VDD_008

M12

VDD_009

M16

VDD_010

M18

VDD_011

N11

VDD_012

D D

C C

N13

VDD_013

N15

VDD_014

N17

VDD_015

P14

VDD_016

R11

VDD_017

R13

VDD_018

R15

VDD_019

R17

VDD_020

T10

VDD_021

T12

VDD_022

T16

VDD_023

T18

VDD_024

U13

VDD_025

U15

VDD_026

V10

VDD_027

V12

VDD_028

V14

VDD_029

V16

VDD_030

V18

VDD_031

VDD_SENSE

GND_SENSE

N17S-G1-A1_GB2C-64-595

@

NVVDD_VCC_SENSE NVVDD_VSS_SENSE

trace width: 16mils differential voltage sensing. differential signal routing.

+VGA_CORE

NVVDD_VCC_SENSE

F2

NVVDD_VSS_SENSE

F1

NVVDD_VCC_SENSE 58 NVVDD_VSS_SENSE 58

7/14 VDDS

L11

VDDS_1

L17

VDDS_2

M14

VDDS_3

P10

VDDS_4

P12

VDDS_5

P16

VDDS_6

P18

VDDS_7

T14

VDDS_8

U11

VDDS_9

U17

VDDS_10

N17S-G1-A1_GB2C-64-595

@

COMMON? INS28353814UV1F

VDDS_SENSE GNDS_SENSE

F4

@

F3

@

4

+VGA_CORE

UV1G INS28355855? C OMMON

6/14 XVDD

G1

XVDD_1

G2

XVDD_2

G3

XVDD_3

G4

XVDD_4

G5

XVDD_5

G6

XVDD_6

G7

XVDD_7

H3

XVDD_8

H4

XVDD_9

H6

XVDD_10

J1

XVDD_11

J2

XVDD_12

J3

1

TV6

1

TV7

XVDD_13

J4

XVDD_14

J5

XVDD_15

J6

XVDD_16

J7

XVDD_17

K1

XVDD_18

K2

XVDD_19

K3

XVDD_20

K4

XVDD_21

K5

XVDD_22

K6

XVDD_23

K7

XVDD_24

L3

XVDD_25

L4

XVDD_26

M1

XVDD_27

M2

XVDD_28

M3

XVDD_29

M4

XVDD_30

M5

XVDD_31

M7

XVDD_32

N1

XVDD_33

N2

XVDD_34

N3

XVDD_35

N17S-G1-A1_GB2C-64-595

@

XVDD_36 XVDD_37 XVDD_38 XVDD_39 XVDD_40 XVDD_41 XVDD_42 XVDD_43 XVDD_44 XVDD_45 XVDD_46 XVDD_47 XVDD_48 XVDD_49 XVDD_50 XVDD_51 XVDD_52 XVDD_53 XVDD_54 XVDD_55 XVDD_56 XVDD_57 XVDD_58 XVDD_59 XVDD_60 XVDD_61 XVDD_62 XVDD_63 XVDD_64 XVDD_65 XVDD_66 XVDD_67 XVDD_68 XVDD_69

N4 N5 N7 P3 P4 P6 R1 R2 R3 R4 R5 R6 R7 T1 T2 T3 T4 T5 T6 T7 U3 U4 U6 V1 V2 V3 V4 V5 V6 V7 W1 W2 W3 W4

3

+VGA_CORE+VGA_CORE

OPT@

1

2

1U_0402_6.3V6K

CV89

CV90

OPT@

1

2

1U_0402_6.3V6K

CV92

CV91

Near GPU 4x4.7uF 11x10uF 4x22uF

1

OPT@

2

CV93

1

OPT@

2

CV94

CV95

4.7U_0402_6.3V6M

1

OPT@

2

CV97

CV96

4.7U_0402_6.3V6M

2

Under GPU

OPT@

1

2

1U_0402_6.3V6K

CV688

1

OPT@

2

CV76

CV77

4.7U_0402_6.3V6M

1

OPT@

2

CV78

4.7U_0402_6.3V6M

12x4.7uF 5x1uF

1

OPT@

2

CV80

CV79

4.7U_0402_6.3V6M

1

OPT@

2

CV81

CV82

4.7U_0402_6.3V6M

1

OPT@

2

CV83

4.7U_0402_6.3V6M

1

OPT@

2

CV84

CV85

4.7U_0402_6.3V6M

1

@

1

2

CV87

CV86

4.7U_0402_6.3V6M

For RF

@

RF@

1

2

33P_0402_50V8J

CV88

CV213

4.7U_0402_6.3V6M

Near VRAM

RF@

OPT@

1

OPT@

2

CV98

10U_0402_6.3V6M

1

OPT@

2

CV99

10U_0402_6.3V6M

CV100

10U_0402_6.3V6M

1

OPT@

2

CV102

10U_0402_6.3V6M

CV101

10U_0402_6.3V6M

1

OPT@

2

CV693

10U_0402_6.3V6M

CV694

10U_0402_6.3V6M

1

OPT@

2

10U_0402_6.3V6M

CV696

10U_0402_6.3V6M

CV695

10U_0402_6.3V6M

OPT@

1

OPT@

2

CV697

10U_0402_6.3V6M

1

2

CV104

CV103

22U_0603_6.3V6-M

OPT@

1

2

CV704

CV105

22U_0603_6.3V6-M

1

2

33P_0402_50V8J

CV214

For RF

2

OPT@

1

CV705

10U_0603_6.3V6M

CV706

10U_0603_6.3V6M

+1.35VGS

B B

C25

G13 G14 G15 G16 G18 G19 G20 G21

M21 N21 R21

W21 H24 H26

B26

E23 E26 F14 F21

L22 L24 L26

T21 V21

J21 K21

12/14 FBVDDQ

FBVDDQ_01 FBVDDQ_02 FBVDDQ_03 FBVDDQ_04 FBVDDQ_05 FBVDDQ_06 FBVDDQ_07 FBVDDQ_08 FBVDDQ_09 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18

COMMON? INS28353624UV1D

+1.35VGS

Under GPU(below 150mils)

OPT@

2

1

10U_0603_6.3V6M

CV26

CV686

8x10uF 2x10uF

OPT@

10U_0603_6.3V6M

CV29

OPT@

1

2

1U_0402_6.3V6K

CV30

CV683

OPT@

1

2

1U_0402_6.3V6K

CV681

CV682

OPT@

1

2

1U_0402_6.3V6K

CV680

OPT@

1

2

1

2

1U_0402_6.3V6K

CV679

CV678

1

OPT@

2

22U_0603_6.3V6-M

CV687

1x10uF 3x22uF

Near GPU

1

OPT@

2

22U_0603_6.3V6-M

CV25

CV684

OPT@

2

1

10U_0603_6.3V6M

CV685

FBVDD/Q Decouling

MLCC

1.0uF

4.7uF

10uF

Q'ty

8

0

3

22uF 3

+1.35VGS

D22

1 2

FB_CAL_PD_VDDQ

A A

FB_CAL_PU_GND

FB_CAL_TERM_GND

N17S-G1-A1_GB2C-64-595

@

5

RV55 40.2_0402_1%OPT@

C24

1 2

RV56 40.2_0402_1%OPT@

B25

1 2

RV57 60.4_0402_1%OPT@

Place near balls

4

CALIBRATION PIN

GDDR5

FB_CAL_x_PD_VDDQ 40.2Ohm

FB_CAL_x_PU_GND

40.2Ohm

FB_CAL_xTERM_GND 60.4Ohm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

N17S_+VGA_CORE,FBVDDQ

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

22 60

0.2

5

Near balls (Under GPU)

COMMON? INS28356407UV1E

14/14 VDD18

D D

N17S-G1-A1_GB2C-64-595

VDD18_1

VDD18_2 1V8_AON_1 1V8_AON_2

@

+VDD18

G8 G9 G10 G12

+1V8_AON

1

OPT@

2

CV50

CV51

0.1u_0201_10V6K

Near balls (Under GPU)

1

OPT@

2

0.1u_0201_10V6K CV714

CV716

0.1u_0201_10V6K

Near GPU

0.1u_0201_10V6K

RV54 0_0402_5%OPT@

1

OPT@

2

1U_0402_6.3V6K

CV53

CV52

4.7U_0402_6.3V6M

RV220 0_0402_5%OPT@

1

OPT@

2

1U_0402_6.3V6K

CV715

CV717

4.7U_0402_6.3V6M

1 2

4

+1.8VGS

12

RV69

47K_0402_5%

+1.8VG_AON

FBVDDQ_PWR_EN23,57

@

61

D

2

G

S

@

QV27A LBSS138DW1T1G_SOT363-6

+1.35VGS

5

G

3

12

34

@

RV67 470_0603_5%

@

D

QV27B LBSS138DW1T1G_SOT363-6

S

PXS_PWREN

2

G

+5VALW+5VALW

RV9 47K_0402_5%

@

1 2

61

D

QV35A 2N7002KDWH_SOT363-6

S

2

+1.8VG_AON

12

RV7 470_0603_5%

@

34

5

G

D

QV35B 2N7002KDWH_SOT363-6

S

NVVDD_EN

PXS_PWREN#FBVDDQ_PWR_EN#

2

+5VALW

1 2

61

G

RV239 47K_0402_5%

@

D

QV36A LBSS138DW1T1G_SOT363-6

S

NVVDD_EN#

1

+VGA_CORE

5

G

12

RV240 470_0603_5%

@

34

D

QV36B LBSS138DW1T1G_SOT363-6

S

Discharge

PXE_VDD & 1V8_AON

RV213

@

1

@

PXS_PWR_EN_R

12

+3VS

RV62 10K_0402_5%

OPT@

1 2

PXE_VDD_EN

12

RV64 10K_0402_5%

@

OPT@

PXE_VDD_EN_R

12

RV630_0402_5%

@

1

2

0.1u_0201_10V6K

CV726

1 2

PXS_PWREN

DGPU_PWROK

RV214 0_0402_5%OPT@

1.8VGS_PWR_EN

LRB751V-40T1G_SOD323-2

100K_0402_5%

DV3

1 2

DV7

2

3

LBAT54AWT1G_SOT323-3

OPT@

PXS_PWREN8,23

C C

DGPU_PWROK8,23,58

+1.8VG_AON TO +1.8VGS

1 2

RV243

+1.8VALW

RV244

+1.8VG_AON

47K_0402_5%

DGPU_PWR_EN#

12

1.8VGS_PWR_EN

5

+5VALW

RV71

GC6@

2

G

PXS_PWREN

12

61

D

QV29A

S

LBSS138DW1T1G_SOT363-6

RV51 0_0402_5%@

RV117 0_0402_5%@

4.7K_0402_5%

B B

1.8VGS_PWR_EN26

RV74

100K_0402_5%

GC6@

A A

PXS_PWREN8,23

+1.8VGS

RV73

GC6@

5

G

1 2

OPT@

V20B+

12

@

120K_0402_5% RV202

1 2

RV21 1K_0402_5%GC6@

34

D

QV29B

S

LBSS138DW1T1G_SOT363-6

RV1160_0402_5%

0_0603_5%

1 2

0_0603_5%

0.1u_0201_10V6K

150K_0402_5%

2

3

1 2

RV235 0_0402_5%OPT@

GC6@

@

RV171

1

CV72

@

2

12

RV245

0.1u_0201_10V6K

@

DV8

LBAT54AWT1G_SOT323-3

@

NVVDD_EN

1

4

1 2

0_0603_5%

QV16 AO3402_SOT-23-3

D1S

G

GC6@

2

1

CV75

GC6@

2

+3VS

@

3

12

+1.8VGS

1

CV73

0.01U_0201_10V6K

GC6@

2

DGPU_PWR_EN#

RV114 82K_0402_1%

@

RV115 100K_0402_1%

@

+1.0VALW

+5VALW

+1.8VALW

2

G

2

OPT@

1

CV718

10U_0603_6.3V6M

2

OPT@

1

CV719

10U_0603_6.3V6M

12

13

D

S

NVVDD_EN 58

PXE_VDD_EN_R

PXS_PWR_EN_R

RV72 470_0603_5%

@

QV20 2N7002KW_SOT323-3

@

+1.0VGS

2

OPT@

UV15

1

IN1_1

2

IN1_2

3

EN1

4

VBIAS

5

EN2

6

IN2_1

7

IN2_2

G5016KD1U_TDFN14_2X3

1

CV74 10U_0603_6.3V6M

GC6@

2

3

14

OUT1_2

13

OUT1_1

12

1 2

CV708 1000P_0201_50V7-K

CT1

11

GND

10

1 2

CV709 1000P_0201_50V7-K

CT2

9

OUT2_2

8

OUT2_1

15

GPAD

+1.0VGS +3VALW +3VS

10K_0402_5% @

12

RV238

@

1K_0402_5%

1

CV755

0.1u_0201_10V6K

@

2

FB_GC6_EN26

DGPU_PWROK8,23,58

PEX_PWROK23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

2015/08/20

1

CV720

10U_0603_6.3V6M

+1.8VG_AON

2

OPT@

1

CV721

10U_0603_6.3V6M

12

RV236

C

2

QV32

MMBT3904WH_SOT323-3

1 2

10K_0402_5%

1 2

0_0402_5%

Deciphered Date

1

CV756

2

0.1u_0201_10V6K

GC6@

0.1u_0201_10V6K

2

B

E

3 1

@

RV123 0_0402_5%

RV233

RV234

LC Future Center Secret Data

PXE_VDD_EN_R

@

OPT@

@

CV754

OPT@

RV237

10K_0402_5% @

2

G

GC6_ENFB_GC6_EN

RV126

1

2

+5VALW

12

13

D

2

G

S

12

1 2

RV232 0_0402_5%@

13

D

QV31 LBSS139WT1G_SC70-3

@

S

DV4 GC6@

2

3

BAV70W-7-F_SOT323-3

1 2

0_0402_5%

2016/08/20

RV100 47K_0402_5%

OPT@

+1.0VGS_PWR_EN#

QV17 2N7002KW_SOT323-3

OPT@

1

NGC6@

+1.0VGS

12

RV102

5.11_0805_1%

PEX_PWROK

12

RV125 200K_0402_5%

GC6@

Titl e

Size

C

Date: Sheet of

RV109

5.11_0805_1%

OPT@

1

D

2

QV15

G

AO3402_SOT-23-3

OPT@

S

3

PEX_PWROK 23

FBVDDQ_PWR_EN 23,57

N17S_AON/MAIN PWR

Document Number Rev

Tuesday, April 25, 2017

EG521

13

D

2

G

S

1

QV34 2N7002KW_SOT323-3

@

23 60

0.2

5

D D

C C

4

13/14 GND

A2

GND_001

AB17

GND_005

AB20

GND_006

AB24

GND_007

AC2

GND_008

AC22

GND_009

AC26

GND_010

AC5

GND_011

AC8

GND_012

AD12

GND_013

AD13

GND_014

A26

GND_002

AD15

GND_015

AD16

GND_016

AD18

GND_017

AD19

GND_018

AD21

GND_019

AD22

GND_020

AE11

GND_021

AE14

GND_022

AE17

GND_023

AE20

GND_024

AB11

GND_003

AF1

GND_025

AF11

GND_026

AF14

GND_027

AF17

GND_028

AF20

GND_029

AF23

GND_030

AF5

GND_031

AF8

GND_032

AG2

GND_033

AG26

GND_034

AB14

GND_004

B1

GND_035

B11

GND_036

B14

GND_037

B17

GND_038

B20

GND_039

B23

GND_040

B27

GND_041

B5

GND_042

B8

GND_043

E11

GND_044

E14

GND_045

E17

GND_046

E2

GND_047

E20

GND_048

E22

GND_049

E25

GND_050

E5

GND_051

E8

GND_052

3

COMMON? INS28356885UV1H

K11

GND_057

K13

GND_058

K15

GND_059

K17

GND_060

L10

GND_061

L12

GND_062

L14

GND_063

L16

GND_064

L18

GND_065

L5

GND_069

M11

GND_070

M13

GND_071

M15

GND_072

M17

GND_073

N10

GND_074

N12

GND_075

N14

GND_076

N16

GND_077

N18

GND_078

P11

GND_079

P13

GND_080

P15

GND_081

P17

GND_082

P23

GND_084

P26

GND_085

R10

GND_087

R12

GND_088

R14

GND_089

R16

GND_090

R18

GND_091

T11

GND_092

T13

GND_093

T15

GND_094

T17

GND_095

U10

GND_096

U12

GND_097

U14

GND_098

U16

GND_099

U18

GND_100

U23

GND_102

U26

GND_103

V11

GND_105

V13

GND_106

V15

GND_107

V17

GND_108

Y2

GND_109

Y23

GND_110

Y26

GND_111

Y5

GND_112

AA7

GND_F

AB7

GND_H

2

1

H2

GND_053

H5

GND_056

L2

GND_066

H23

GND_054

H25

GND_055

N17S-G1-A1_GB2C-64-595

B B

A A

5

4

@

P2

GND_083

P5

GND_086

U2

GND_101

U5

GND_104

L23

GND_067

L25

GND_068

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

N17S_GND

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

24 60

0.2C

0.2

5

4

3

2

1

4/14 IFPAB

5/14 NC

AA14

NC_1

AA15

NC_2

AB6

NC_3

AB8

NC_4

D D

1 2

200_0402_1%

PEX_TSTCLK_OUT

RV32

@

PEX_TSTCLK_OUT#

Differential signal

AD10

NC_5

AD7

NC_6

AE22

NC_7

AE3

NC_8

AE4

NC_9

AF2

NC_10

AF22

NC_11

AF3

NC_12

AF4

NC_13

AG3

NC_14

D10

NC_15

E10

NC_16

F10

NC_17

F5

NC_18

F6

NC_19

W5

NC_20

N17S-G1-A1_GB2C-64-595

@

COMMON? INS28357344UV1I

AA6

IFPAB_RSET

W7

IFPAB_PLLVDD

W6

IFP_IOVDD_1

Y6

IFP_IOVDD_2

IFPA B

1

N17S-G1-A1_GB2C-64-595

@

TV5

12

10P_0201_25V8G

ROM_SI 29 ROM_SO 29 ROM_SCLK 29

1

CV19

OPT@

2

XTALOUT

XTALSSIN XTALOUT

XTAL_IN

C C

10/14 MISC2

D1

STRAP029 STRAP129 STRAP229 STRAP329 STRAP429 STRAP529

+1.8VGS

OPT@

SBK160808T-300Y-N

30ohms (ESR=0.05) Bead

B B

+CORE_PLLVDD

12

LV2

1

OPT@

2

CV728

CV727

4.7U_0402_6.3V6M

1 2

LV5 0_0402_5%OPT@

22U_0603_6.3V6-M

LV1 0_0402_5%OPT@

Under GPU(below 150mils)

1 2

180ohms (ESR=0.2) Bead

1 2

LV7 0_0402_5%OPT@

Under GPUNear GPU

1

OPT@

2

CV21

0.1u_0201_10V6K

CV667

1

OPT@

2

CV15

0.1u_0201_10V6K

@

1

2

CV16

0.1u_0201_10V6K

@

1

2

CV712

+SP_PLLVDD

0.1u_0201_10V6K

VID_PLLVDD

GPCPLL_AVDD

STRAP0

D2

STRAP1

E4

STRAP2

E3

STRAP3

D3

STRAP4

C1

STRAP5

N17S-G1-A1_GB2C-64-595

@

+SP_PLLVDD

GPCPLL_AVDD VID_PLLVDD

XTALSSIN XTALOUT

L6

M6

F11

N6

150mA

A10

C11

N17S-G1-A1_GB2C-64-595

9/14 XTAL_PLL

XS_PLLVDD SP_PLLVDD GPCPLL_AVDD VID_PLLVDD

XTAL_SSIN

XTAL_IN

@

COMMON? INS28357601UV1L

COMMON? INS28357491UV1K

ROM_CS_N

ROM_SI

ROM_SO

ROM_SCLK

BUFRST_N

XTAL_OUTBUFF

XTAL_OUT

C10

B10

D12

B12 A12 C12

D11

XTAL_OUTXTAL_IN

@

ROM_SI ROM_SO ROM_SCLK

RV50 10K_0402_5%@

COMMON? INS28357414UV1J

DVI HDMI DP

SL/DL

TXC/TXC

TXD0/0

TXD1/1

TXD2/2

TXC

TXD0/3

TXD1/4

TXD2/5

(DEFEATURED 0N GM108)

1 2

1 2 1 2

1 2

RV38 10M_0402_5%OPT@

YV1

1

OSC1

GND12OSC2

27MHZ_10PF_7V27000050

OPT@

IFPA_L3_N

IFPA_L2_N

IFPA_L1_N

IFPA_L0_N

IFPA_AUX_SDA_N

IFPA_AUX_SCL

IFPB_L3_N

IFPB_L2_N

IFPB_L1_N

IFPB_L0_N

IFPB_AUX_SDA_N

IFPB_AUX_SCL

RV33 10K_0402_5%@

RV34 10K_0402_5%OPT@ RV36 10K_0402_5%OPT@

4

GND2

3

IFPA_L3

IFPA_L2

IFPA_L1

IFPA_L0

IFPB_L3

IFPB_L2

IFPB_L1

IFPB_L0

XTAL_OUT

AC4 AC3

Y3 Y4

AA2 AA3

AA1 AB1

AA5 AA4

AB4 AB5

AB2 AB3

AD2 AD3

AD1 AE1

AD5 AD4

+1.8VG_AON

1

CV20 10P_0201_25V8G

OPT@

2

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

N17S_STRAP/DP/HDMI

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

25 60

0.2

5

4

3

2

1

2.2K_0402_5%

PLT_RST_VGA#

FB_GC6_EN

10K_0402_5%

+1.8VG_AON

RV3

1 2

0.01U_0201_10V6K

RV47

GC6@

1 2

RV5

2.2K_0402_5%

1 2

RV174

OVERT#

CV221

2

G

8/14 MISC1

OVERT#

1

D D

CV707

0.1u_0201_10V6K

@

2

N17S update

C C

TV1 TV2 TV3 TV4

12

RV5310K_0402_5% OPT@

12

TESTMODE

RV5210K_0402_5% OPT@

A6

OVERT

AE2

TS_VREF

E12

THERMDN

F12

THERMDP

N17S-G1-A1_GB2C-64-595

@

3/14 JTAG

AE5

1

@

JTAG_TCK

AE6

1

@

JTAG_TDI

AF6

1

@

JTAG_TDO

AD6

1

@

JTAG_TMS

AG4

JTAG_TRST_N

AD9

NVJTAG_SEL

N17S-G1-A1_GB2C-64-595

@

COMMON? INS28357869UV1M

VGA_SMB_CK2

D9

I2CS_SCL

VGA_SMB_DA2

D8

I2CS_SDA

I2CC_SCL

A9

I2CC_SCL

I2CC_SDA

B9

I2CC_SDA

I2CB_SCL

C9

I2CB_SCL

I2CB_SDA

C8

I2CB_SDA

NVVDD_PWM_VID

C6

GPIO0

FB_GC6_EN

B2

GPIO1

GPU_EVENT#_R

D6

GPIO2

C7

GPIO3

1.8VGS_PWR_EN

F9

GPIO4

A3

GPIO5

PSI_VGA_R

A4

GPIO6

B6

GPIO7

MEM_VDD_CTL

E9

GPIO8

VGA_ALERT#

F8

GPIO9

GPIO10_FBVREF_ALTV

C5

GPIO10

E7

GPIO11

VGA_AC_DET_R

D7

GPIO12

B4

GPIO13

B3

GPIO14

C3

GPIO15

SYS_PEX_RST_MON#

D5

GPIO16

D4

GPIO17

C2

GPIO18

F7

GPIO19

E6

GPIO20

GPU_PEX_RST_HOLD#

C4

GPIO21

VGA_CRT_DATA

A7

GPIO22

VGA_CRT_CLK

B7

GPIO23

COMMON? INS28358016UV1N

1 2

RV6 0_0402_5%

OPT@

12

OPT@

DV1 RB751V-40_SOD323-2

NVVDD_PWM_VID 58

FB_GC6_EN 23

1.8VGS_PWR_EN 23

PSI_VGA 58

GPIO10_FBVREF_ALTV 27

VGA_AC_DET 44

VGA_SMB_CK2

VGA_SMB_DA2

G

5

QV1B

34

D

S

LBSS138DW1T1G_SOT363-6

1 2

56_0402_5%

1

@

2

+3VALW

RV45 10K_0402_5%

GC6@

1 2

61

D

QV33A LBSS138DW1T1G_SOT363-6

GC6@

S

+1.8VG_AON

G

2

QV1A

61

D

S

LBSS138DW1T1G_SOT363-6

@

G

2

13

D

S

QV24

@

LBSS139WT1G_SC70-3

+3VS

RV41 10K_0402_5%

GC6@

1 2

34

D

5

G

GC6@

S

GPU Address 0x9E

PU AT EC SIDE, +3VS AND 4.7K

1

CV218 220P_0201_25V7-K

@

2

WRST# 44

FB_GC6_EN_R

QV33B LBSS138DW1T1G_SOT363-6

EC_SMB_CK2 7,39,44

EC_SMB_DA2 7,39,44

FB_GC6_EN_R 8

+1.8VG_AON +1.8VG_AON

RV13

10K_0402_5%

GC6@

1 2

RV15 0_0402_5%@

1 2

RV17 2.2K_0402_5%@

1 2

RV19 2.2K_0402_5%@

1 2

RV22 2.2K_0402_5%@

1 2

RV25 2.2K_0402_5%@

1 2

RV28 2.2K_0402_5%@

1 2

RV30 2.2K_0402_5%@

1 2

RV241 10K_0402_5%@

1 2

RV224 10K_0402_5%@

2016/08/20

1

CV12

0.1u_0201_10V6K

@

2

G

5

34

D

S

QV25B

GC6@

LBSS138DW1T1G_SOT363-6

1 2

+1.8VG_AON +1.8VG_AON

GPU_EVENT#GPU_EVENT#_R

1.8VGS_PWR_EN

OVERT#

VGA_ALERT#

VGA_AC_DET_R

PSI_VGA

GPU_PEX_RST_HOLD#

Titl e

N17S_GPIO/JTAG

Size

Document Number Rev

C

Tuesday, April 25, 2017

Date: Sheet of

GPU_EVENT# 8

RV18 10K_0402_5%OPT@

1 2

RV20 10K_0402_5%OPT@

1 2

RV23 10K_0402_5%OPT@

1 2

RV26 100K_0402_5%OPT@

1 2

RV29 10K_0402_5%OPT@

1 2

RV31 10K_0402_5%OPT@

EG521

1

12

26 60

0.2

RV16 100K_0402_5%

OPT@

+3VS

RV12

@

0_0402_5%

1 2

+1.8VGARST

5

UV2

1

P

B

4

Y

2

A

G

MC74VHC1G09DFT2G_SC70-5

3

OPT@

RV14 100K_0402_5%

1

CV11

0.1u_0201_10V6K

OPT@

2

OPT@

RV180

+1.8VGS

@

SYS_PEX_RST_MON#SYS_PEX_RST#

+1.8VG_AON

RV37 10K_0402_5%

OPT@

1 2

PLT_RST_VGA#

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

Issued Date

PLT_RST_VGA# 20

2015/08/20

VGA_CRT_DATA

VGA_CRT_CLK

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

SYS_PEX_RST_MON#

MEM_VDD_CTL

LC Future Center Secret Data

Deciphered Date

2

1 2

RV242 0_0402_5%@

SYS_PEX_RST#

12

GPU_PEX_RST_HOLD#

SYS_PEX_RST#

RV39 0_0402_5%OPT@

4

2.2K_0402_5%

DV6

2

3

BAT54AW_SOT323-3

@

1 2

1

B B

PLT_RST#11,32,37,40,44

PXS_RST#8

A A

PLT_RST#

12

5

4

3

2

1

Lower 32 bits

FBA_D[0..63]21,28

FBA_CMD[31..0]21,28

FBA_EDC[7..0]21,28

FBA_DBI[7..0]21,28

D D

RV192 549_0402_1%

FBA_VREFC

RV191

1.33K_0402_1%

FBA_CLK0 FBA_CLK0#

RV194

40.2_0402_1%

12

RV193

40.2_0402_1%

1

CV228

0.01U_0201_10V6K

2

OPT@

RV182 1K_0402_1% RV183 1K_0402_1% RV185 121_0402_1%

FBA_WCLK01#21,27

FBA_WCLK0121,27

FBA_WCLK23#21,27

FBA_WCLK2321,27

RV190

OPT@

13

D

LBSS139WT1G_SC70-3

2

QV26

G

S

12

RV208 100K_0402_5%

1 2 1 2 1 2

931_0402_1%

FBA_CLK021

FBA_CLK0#21

C C

+1.35VGS

12

B B

GPIO10_FBVREF_ALTV26

A A

FBA_EDC0

FBA_EDC2

FBA_DBI0

FBA_DBI2

FBA_CLK0 FBA_CLK0# FBA_CMD14

FBA_CMD2 FBA_CMD4 FBA_CMD3 FBA_CMD1

FBA_CMD6 FBA_CMD11 FBA_CMD10 FBA_CMD7 FBA_CMD9

FBA_SEN0 FBA_SEN0

FBA_CMD8 FBA_CMD12 FBA_CMD0 FBA_CMD15 FBA_CMD5

FBA_WCLK01# FBA_WCLK01

FBA_WCLK23# FBA_WCLK23

FBA_VREFC FBA_VREFC

1

FBA_CMD13

CV224

2

820P_0402_25V7

+1.35VGS +1.35VGS

FBA_VREFC

12

MF=0 No Mir ror

UV5

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170VRAM@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19 VSSQ20 VSSQ21 VSSQ22 VSSQ23 VSSQ24 VSSQ25 VSSQ26 VSSQ27 VSSQ28 VSSQ29 VSSQ30 VSSQ31 VSSQ32 VSSQ33 VSSQ34 VSSQ35 VSSQ36

MF=1 Mirror

UV6

FBA_D0

A4

FBA_D1

A2

FBA_D2

B4

FBA_D3

B2

FBA_D4

E4

FBA_D5

E2

FBA_D6

F4

FBA_D7

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D16

U11

FBA_D17

U13

FBA_D18

T11

FBA_D19

T13

FBA_D20

N11

FBA_D21

N13

FBA_D22

M11

FBA_D23

M13 U4 U2 T4 T2 N4 N2 M4 M2

+1.35VGS +1.35VGS

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_VREFC

+1.35VGS

1 2

RV184 1K_0402_1%

1 2

RV186 121_0402_1%

FBA_WCLK23#21,27

FBA_WCLK2321,27

FBA_WCLK01#21,27

FBA_WCLK0121,27

FBA_EDC3

FBA_EDC1

FBA_DBI3

FBA_DBI1

FBA_CLK0 FBA_CLK0# FBA_CMD14

FBA_CMD3 FBA_CMD1 FBA_CMD2 FBA_CMD4

FBA_CMD10 FBA_CMD7 FBA_CMD6 FBA_CMD11 FBA_CMD9

FBA_CMD8 FBA_CMD15 FBA_CMD5 FBA_CMD12 FBA_CMD0

FBA_WCLK23# FBA_WCLK23

FBA_WCLK01# FBA_WCLK01

1

FBA_CMD13

CV226

2

820P_0402_25V7

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

H5GQ1H24AFR-T2L_BGA170VRAM@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19 VSSQ20 VSSQ21 VSSQ22 VSSQ23 VSSQ24 VSSQ25 VSSQ26 VSSQ27 VSSQ28 VSSQ29 VSSQ30 VSSQ31 VSSQ32 VSSQ33 VSSQ34 VSSQ35 VSSQ36

FBA_D24

A4

FBA_D25

A2

FBA_D26

B4

FBA_D27

B2

FBA_D28

E4

FBA_D29

E2

FBA_D30

F4

FBA_D31

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D8

U11

FBA_D9

U13

FBA_D10

T11

FBA_D11

T13

FBA_D12

N11

FBA_D13

N13

FBA_D14

M11

FBA_D15

M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VGS

Close to DRAM

CV743

CV741

10U_0402_6.3V6M

1

OPT@

2

CV744

10U_0402_6.3V6M

1

OPT@

2

CV745

CV742

10U_0402_6.3V6M

1

OPT@

2

CV746

10U_0402_6.3V6M

1

OPT@

2

CV621

CV623

1U_0402_6.3V6K

1

OPT@

2

CV627

CV628

1U_0402_6.3V6K

1

OPT@

2

CV625

CV622

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

OPT@

2

CV629

CV630

1U_0402_6.3V6K

1

OPT@

2

Around DRAM

CV747

CV748

10U_0402_6.3V6M

1

OPT@

2

CV749

CV750

10U_0402_6.3V6M

OPT@

CV751

CV752

CV753

1

2

1

OPT@

@

2

22U_0603_6.3V6-M

1

@

2

22U_0603_6.3V6-M

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

N17S_GDDR5_Rank0_[31:0]

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

27 60

0.2

5

4

3

2

1

upper 32 bits

FBA_D[0..63]21,27

FBA_CMD[31..0]21, 27

FBA_EDC[7..0]21,27

FBA_DBI[7..0]21,27

D D

FBA_EDC7

FBA_EDC5

FBA_CLK121

FBA_CLK1#21

C C

B B

A A

FBA_CLK1 FBA_CLK1#

RV196

40.2_0402_1%

12

RV195

40.2_0402_1%

1

CV649

0.01U_0201_10V6K

2

OPT@

+1.35VGS

1 2

RV199 1K_0402_1%

1 2

RV198 1K_0402_1%

1 2

RV200 121_0402_1%

FBA_WCLK67#21

FBA_WCLK6721

FBA_WCLK45#21

FBA_WCLK4521

FBA_DBI7

FBA_DBI5

FBA_CLK1 FBA_CLK1# FBA_CLK1# FBA_CMD30

FBA_CMD19 FBA_CMD17 FBA_CMD18 FBA_CMD20

FBA_CMD26 FBA_CMD23 FBA_CMD22 FBA_CMD27 FBA_CMD25

FBA_SEN1

FBA_CMD24 FBA_CMD31 FBA_CMD21 FBA_CMD28 FBA_CMD16

FBA_WCLK67# FBA_WCLK67

FBA_WCLK45# FBA_WCLK45

FBA_VREFC

1

FBA_CMD29

CV662

2

820P_0402_25V7

+1.35VGS

UV13

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

VRAM@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9 DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19 VSSQ20 VSSQ21 VSSQ22 VSSQ23 VSSQ24 VSSQ25 VSSQ26 VSSQ27 VSSQ28 VSSQ29 VSSQ30 VSSQ31 VSSQ32 VSSQ33 VSSQ34 VSSQ35 VSSQ36

H5GQ1H24AFR-T2L_BGA170

FBA_VREFC

1

CV665

2

820P_0402_25V7

FBA_EDC4

FBA_EDC6

FBA_DBI4

FBA_DBI6

FBA_CLK1

FBA_CMD30

FBA_CMD18 FBA_CMD20 FBA_CMD19 FBA_CMD17

FBA_CMD22 FBA_CMD27 FBA_CMD26 FBA_CMD23 FBA_CMD25

FBA_SEN1

FBA_CMD24 FBA_CMD28 FBA_CMD16 FBA_CMD31 FBA_CMD21

FBA_WCLK45# FBA_WCLK45

FBA_WCLK67# FBA_WCLK67

FBA_CMD29

+1.35VGS

FBA_D56

A4

FBA_D57

A2

FBA_D58

B4

FBA_D59

B2

FBA_D60

E4

FBA_D61

E2

FBA_D62

F4

FBA_D63

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D40

U11

FBA_D41

U13

FBA_D42

T11

FBA_D43

T13

FBA_D44

N11

FBA_D45

N13

FBA_D46 FBA_D55

M11

FBA_D47

M13 U4 U2 T4 T2 N4 N2 M4 M2

+1.35VGS

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_VREFC

1 2

RV197 1K_0402_1%

1 2

RV201 121_0402_1%

MF=0 No Mir rorMF=1 Mirror

UV14

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC1

U5

VPP/NC2

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD1

U10

VREFD2

J14

VREFC

J2

RESET#

H1

VSS1

K1

VSS2

B5

VSS3

G5

VSS4

L5

VSS5

T5

VSS6

B10

VSS7

D10

VSS8

G10

VSS9

L10

VSS10

P10

VSS11

T10

VSS12

H14

VSS13

K14

VSS14

G1

VDD1

L1

VDD2

G4

VDD3

L4

VDD4

C5

VDD5

R5

VDD6

C10

VDD7

R10

VDD8

D11

VDD9

G11

VDD10

L11

VDD11

P11

VDD12

G14

VDD13

L14

VDD14

170-BALL

SGRAM GDDR5

VRAM@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19 VSSQ20 VSSQ21 VSSQ22 VSSQ23 VSSQ24 VSSQ25 VSSQ26 VSSQ27 VSSQ28 VSSQ29 VSSQ30 VSSQ31 VSSQ32 VSSQ33 VSSQ34 VSSQ35 VSSQ36

H5GQ1H24AFR-T2L_BGA170

FBA_D32

A4

FBA_D33

A2

FBA_D34

B4

FBA_D35

B2

FBA_D36

E4

FBA_D37

E2

FBA_D38

F4

FBA_D39

F2 A11 A13 B11 B13 E11 E13 F11 F13

FBA_D48

U11

FBA_D49

U13

FBA_D50

T11

FBA_D51

T13

FBA_D52

N11

FBA_D53

N13

FBA_D54

M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

+1.35VGS

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.35VGS

OPT@

CV654

CV731

OPT@

1

2

1

2

CV734

10U_0402_6.3V6M

OPT@

10U_0402_6.3V6M

OPT@

10U_0402_6.3V6M

1

2

CV729

CV732

OPT@

10U_0402_6.3V6M

1

2

10U_0402_6.3V6M

1

2

CV735

1

2

Close to DRAM

CV650

1U_0402_6.3V6K

1

OPT@

2

CV733

1U_0402_6.3V6K

1

OPT@

2

Around DRAM

CV736

10U_0402_6.3V6M

1

OPT@

2

CV653

CV651

1U_0402_6.3V6K

1

OPT@

2

CV639

CV638

1U_0402_6.3V6K

1

OPT@

2

CV737

CV738

1

OPT@

@

2

22U_0603_6.3V6-M

CV730

CV652

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

1

2

1U_0402_6.3V6K

1

OPT@

2

CV641

CV640

1U_0402_6.3V6K

1

OPT@

2

CV739

CV740

1

@

2

22U_0603_6.3V6-M

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

N17S_GDDR5_Rank0_[64:32]

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

28 60

0.2

5

4

3

2

1

RV147 100K_0402_5%

@

RV152 100K_0402_5%

@

+1.8VG_AON

RV148 100K_0402_5%

@

1 2

RV153 100K_0402_5%

@

1 2

GPU

8Gb

4Gb

FB Memory (GDDR5) STR AP2

Samsung 8Gb

Micron 8Gb

Hynix 8Gb

Samsung 4Gb

Hynix 4Gb

Micron 4Gb

K4G80325F B-HC28

MT51J256M 32HF-70 :A

H5GC8H24M JR-R0C

K4G41325F E-HC28

H5GC4H24A JR-R0C

EDW4032BA BG-70-F

STRAP3 PCIE_CFGSMB_ALT_ADDR DEVID_SEL VGA _DEVICESTRAP5 STRAP4

RAMCFG[4 :0]

0(0x0000 )

1(0x0001 )

L

2(0x0010 ) H

7(0x0111 )

H

6(0x0110 )

8(0x1000 )

STRAP1

L

HH

STRAP0

LLL

H

LL

HH

L

MLL

X76

RV146 100K_0402_5%

@

D D

STRAP025 STRAP125 STRAP225

STRAP0 STRAP1 STRAP2

1 2

RV151 100K_0402_5%

@

1 2

+1.8VG_AON

0 0 0L L L 0

RV149 100K_0402_5%

C C

STRAP325 STRAP425 STRAP525

STRAP3 STRAP4 STRAP5

@

1 2

RV154 100K_0402_5%

OPT@

1 2

RV150 100K_0402_5%

@

1 2

RV155 100K_0402_5%

OPT@

1 2

RV219 100K_0402_5%

@

1 2

RV218 100K_0402_5%

OPT@

1 2

1: SMB_ALT_ADDR ENABLE

0: SMB_ALT_ADDR DISABLE

1: DEVID_SEL REBRAND

0: DEVID_SEL ORIGNAL

1: PCIE_CFG LOW POW ER

0: PCIE_CFG HIGH POW ER

1: VGA_DEVICE ENABLE

0: VGA_DEVICE DISABLE

+1.8VG_AON

B B

RV156 100K_0402_5%

OPT@

1 2

ROM_SI25 ROM_SO25 ROM_SCLK25

ROM_SI ROM_SO ROM_SCLK

RV159 100K_0402_5%

@

1 2

RV157 100K_0402_5%

OPT@

1 2

RV160 100K_0402_5%

@

1 2

RV158 100K_0402_5%

OPT@

1 2

RV161 100K_0402_5%

OPT@

1 2

ROM_SI

H

SOR_EXPOSED[3:0]ROM_SCLKROM_SO

M

000 0

1:ENABLE 0:DISABLE

SOR0/1/2/3 DISABLEH

DEVID_SEL

0

(Default )

1

PCIE_CFG

0

(Default )

1

SMBUS_ALT_ADDR

0

0x9E (Default)

1

0x9C (Multi-GPU usage)

VGA_DEVICE

0

3D Device (Class Code 302h)

1

VGA Device (Default)

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

N16X_MISC

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

29 60

0.2

5

4

3

2

1

+3VALW

1 2

RA213 0_0402_5%

+3VS

1 2

RA216 0_0402_5%@

D D

Analog power for mixers, & IO ports

+5VS +5VA

1 2

RA7 0_0603_5%

C C

0.1U_0201_6.3V6-K

2

CA42

1

+3VALW

+3VS +3VS_CARD

1U_0402_6.3V6K

1

@

C2062

2

+3VL

1 2

RA203 0_0402_5%

To solve the background noise while combojack connecting to an active speaker and system entry into S3/S4/S5 without analo g power.

Digital power for HDA link

Power supply for full-bridge left/Right channel

+5VS +5VD

EMC_NS@

1 2

LA25 BLM15PD600SN1D_2P

1 2

1U_0402_6.3V6K

Power for card reader controller

RA10 0_0603_5%EMC@

2

CA20

1

1 2

RA220 0_0402_5%@

1 2

RA219 0_0402_5%

Power for combo jack depop circuit at system shutdown mode

VDD_STB

DVDD_IO

2

CA2

0.1U_0201_6.3V6-K

1

Close to Pin7

CA178

10U_0805_10V6K

1

2

CA18 0.1U_0201_6.3V6-K

2

1

+1.8VS +1.8V_AUDIO

1 2

RA225 0_0402_5%

+1.8VALW

1 2

RA226 0_0402_5%@

DMIC_DATA33

DMIC_CLK33 HDA_SDOUT_AUDIO8 HDA_BITCLK_AUDIO8

HDA_SDIN08

HDA_SYNC_AUDIO8

RING2_CONN

CA19 0.1U_0201_6.3V6-K

MICBIASB

RING3_CONN

1 2

RA38 2.2K_0402_5%

1 2

RA37 2.2K_0402_5%

EC_MUTE#44

BEEP#44

PCH_BEEP8

SD_CMD_R31

SD_D3_R31

SD_D2_R31

USB20_N59

USB20_P59

+3VS_CARD

8/29 Add +1.8VS Circuit for Audio wei

DMIC_DATA DMIC_CLK

HDA_SDIN0 SDATA_IN

+3VS

PLUG_IN

SD_CMD_R SD_D3_R SD_D2_R

USB20_N5 USB20_N5_R USB20_P5 USB20_P5_R

4.7U_0402_6.3V6M

DA1

2

3

LBAT54CWT1G_SOT323-3

1 2

RA19 0_0402_5%

1 2

RA18 0_0402_5%

1 2

CA1 2.2U_0402_6.3V6M

1 2

RA16 33_0402_5%

DVDD_IO

1 2

RA205 100K_0402_1%

1 2

RA204 200K_0402_1%

1 2

CA41 2.2U_0402_6.3V6M

1 2

CW1 1U_0402_6.3V6K

1 2

CW2 1U_0402_6.3V6K

1 2

RW11 6.2K_0402_1%

1 2

RW12 0_0402_5%

1 2

RW13 0_0402_5%

CARD_3V3

1

2

RA35 0_0402_5%@

1

1 2

LRB751V-40T1G_SOD323-2

1 2

CW19

0.1u_0201_10V6K

2

DA4

1 2

RA211 0_0402_5%

CW18

@

DMIC_DATA_R DMIC_CLK_R HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO PC_BEEP

JSENSE

VDD_STB

LINE1_R LINE1_L

RREF

SPKR_MUTE#EC_MUTE#

12

RA43 10K_0402_5%

1 2

CA40

12

RA14 10K_0402_5%

UA1

1

HD-GPIO0/DMIC-DATA

2

HD-GPIO1/DMIC-CLK

3

HD-SDATA-OUT

4

HD-BCLK

5

HD-LDO3-CAP

6

HD-SDATA-IN

7

HD-DVDD-IO

8

HD-SYNC

9

HD-PCBEEP

10

HD-JD1(HP/LINE1)

11

HD-MIC2-L(RING)

12

HD-MIC2-R(SLEEVE)

13

HD-3V5V-STB

14

HD-MIC2-CAP

15

HD-LINE1-R

16

HD-LINE1-L

17

HD-LINE2-R

18

HD-LINE2-L

19

CR-SD-CMD

20

CR-SD-DAT[3]

21

CR-SD-DAT[2]

22

CR-SDREG

23

CR-TEST1

24

CR-V18-CAP

25

CR-RREF

26

CR-DM

27

CR-DP

28

CR-3V3-IN

29

CR-SD-3V3

RTS5199-CG_QFN56_7X7

0.1U_0201_6.3V6-K

30

CR-GPIO

CR-SD-CD

CR-SD-WP CR-SD-DAT[1] CR-SD-DAT[0]

CR-SD-CLK

HD-AVDD1 HD-LDO1-CAP

HD-VREF

HD-MIC2-VREFO

HD-LINE1-VREFO-L

HD-HPOUT-L

HD-HPOUT-R

HD-CPVEE

HD-CBN

HD-CPVDD

HD-CBP

HD-LDO2-CAP

HD-AVDD2

HD-PVDD1

HD-SPKOUT-LP HD-SPKOUT-LN HD-SPKOUT-RN HD-SPKOUT-RP

HD-PVDD2

HD-PDB

HD-DVDD

GNDPAD

PC_BEEPPC_BEEP1

SD_CD#

31

SD_WP

32

SD_D1_R

33

SD_D0_R

34

SD_CLK_R

35 36

+5VA LDO1_CAP

37 38 39

MICBIASB LINE1_VREF_L

40

HPOUT_L

41

HPOUT_R

42 43 44 45 46

HD_LDO2

47 48 49

+5VD SPK_L+

50

SPK_L-

51

SPK_R-

52

SPK_R+

53 54

+5VD SPKR_MUTE#

55 56

57

LINE1_L

CA45 1U_0402_6.3V6K

LINE1_VREF_L

RA41 4.7K_0402_5%

HPOUT_L A_HP_OUTL_R

LINE1_VREF_L

RA42 4.7K_0402_5%

LINE1_R

CA46 1U_0402_6.3V6K

1 2

CA43 2.2U_0402_6.3V6M

1 2

CA44 1U_0402_6.3V6K

1 2

CA47 1U _0402_6.3V6K

1 2

CC167 10U_0402_6.3V6M

1 2

SD_CD# 31 SD_WP 31 SD_D1_R 31 SD_D0_R 31 SD_CLK_R 31

1 2

CA48 1U_0402_6.3V6K

+1.8V_AUDIO

@

Analog power for DACs, ADCs

+3VS

Digital power for digital I/O circuit

2

0.1U_0201_6.3V6-K

2

1U_0402_6.3V6K

CA180

CA179

1

1 2

RA21 51_0402_1%

1 2

RA20 51_0402_1%

A_HP_OUTR_RHPOUT_R

12

CA44.7U_0603_6.3V6K

CC257

10U_0402_6.3V6M

+1.8V_AUDIO

2

1

11/8 SIT Vendor suggestion form 47 ohm change to 51om wei

1 2

HDA_RST_AUDIO#8

B B

GND

RING3_CONN RING2_CONN A_HP_OUTL_R A_HP_OUTR_R PLUG_IN

C185

A A

EMC_NS@

RA217 0_0402_5%@

1 2

RA1 0_0402_5%

EMC_NS@

1 2

RA4 0_0402_5%

EMC_NS@

1 2

RA9 0_0402_5%

1 2

RA12 0_0402_5%

EMC_NS@

AZ5123-01F.R7GR_DFN1006P2X2

1

DA5

1

2

EMC_NS@

2

47P_0201_25V8-J

2

GNDA

AZ5123-01F.R7GR_DFN1006P2X2

1

DA6

1

EMC_NS@

2

1

TC203@

JSPK1

ME@

1

2

3

4

5

GND1

6

GND2

ACES_88231-04001

USB20_N5 USB20_N5_R

USB20_P5

FOR EMI

LW2

1

4

EXC24CH900U_4P

EMC_NS@

2

USB20_P5_R

3

1 2

RA223 15_0402_5%C D@

1 2

RA224 15_0402_5%C D@

1 2

RA32 15_0402_5%CD @

1 2

RA33 15_0402_5%CD @

2

CA183

1

220P_0201_25V7-K

CD@

2

CA30

CA29

CA184

1

220P_0201_25V7-K

CD@

SPK_R+ SPK_RSPK_L+ SPK_L-

1 2

RA222 0_0402_5%

1 2

RA221 0_0402_5%

1 2

RA30 0_0402_5%

1 2

RA34 0_0402_5%

11/8 SIT Cost down to 0ohm wei

SPK_R+_CONN SPK_R-_CONN SPK_L+_CONN SPK_L-_CONN

470P_0201_50V7-K

CA31

1

EMC@

2

470P_0201_50V7-K

CA32

1

EMC@

2

470P_0201_50V7-K

CA181

CA182

1

EMC@

2

8/16 Update Audio Jack P/N SP011509163 wei

Audio Jack

RING2_CONN

1 2

R3124

0_0402_5%

DMIC_CLK

AZ5123-01F.R7GR_DFN1006P2X2

1

DA7

1

EMC_NS@

2

AZ5123-01F.R7GR_DFN1006P2X2

1

DA8

DA9

1

EMC_NS@

2

1

CA38

CA39

2

EMC_NS@

100P_0201_25V8J

DMIC_DATA

CA23

EMC_NS@

100P_0201_25V8J

1

2

EMC_NS@

22P_0201_258J

1 2

RA27 27_0402_5%

EMC@

CA25

CA24

1

EMC@

2

EMC_NS@

22P_0201_258J

33P_0201_50V8-J

1

2

33P_0201_50V8-J

HDA_SYNC_AUDIO HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO HDA_SDIN0

CA26

EMC_NS@

R3123

1 2

0_0402_5%

For EMI

1 2

C232

@

470P_0201_50V7-K@

1 2

C184

470P_0201_50V7-K@

A_HP_OUTL_R

PLUG_IN

A_HP_OUTR_R

RING3_CONN

1

2

100P_0201_25V8J

C182

EMC@

C183

EMC@

2

100P_0201_25V8J

JHP1

3

G/M

1

L

5

6

2

R

4

M/G

7

MS

SINGA_2SJ3095-140111F

ME@

8/16 Update Audio Jack P/N DC021608101 wei

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

Codec & CR_RTS5199

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG521

1

30 60

0.2

5

D D

4

3

CARD_3V3

2

1

SD / MMC

SD_D0_R30

SD_D1_R30

C C

B B

SD_D2_R30

SD_D3_R30

SD_CMD_R30

SD_CLK_R30

SD_D0_R

SD_D1_R

SD_D2_R

SD_D3_R

1 2

RW3 0_0402_5%

1 2

RW4 0_0402_5%

1 2

RW5 0_0402_5%

1 2

RW6 0_0402_5%

1 2

RW7 0_0402_5%

1 2

RW8 0_0402_5%

1 2

CW5 5.6P_0402_50V8-D

EMC@

1 2

CW6 5.6P_0402_50V8-D

EMC@

1 2

CW7 5.6P_0402_50V8-D

EMC@

1 2

CW8 5.6P_0402_50V8-D

EMC@

1 2

CW11 5.6P_0402_50V8-D

EMC@

1 2

CW12 5.6P_0402_50V8-D

EMC@

SD_D0

SD_D1

SD_D2

SD_D3

SD_CMDSD_CMD_R

SD_CLKSD_CLK_R

1

CW9

@

2

4.7U_0402_6.3V6M

Close to Connector

SD_CD#30 SD_WP30

CARD_3V3

1

2

1

CW17

2

0.1u_0201_10V6K

DW1

AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@

FOR ESD

SD_D3 SD_CMD

SD_CLK

SD_D0 SD_D1 SD_D2

SD_CD# SD_WP

JREAD1

1

CD/DAT3

2

CMD

3

VSS1

4

VDD

5

CLK

6

VSS2

7

DAT0

8

DAT1

9

DAT2

10

CARDDET ECT

11

WRITE PROTECT

T-SOL_5-251301001000-6_NR

ME@

SH1 SH2 SH3 SH4

8/16 Update Conn. P/N SP07000WG00 wei

12 13 14 15

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

3

LC Future Center Secret Data

Deciphered Date

2016/08/20

2

Titl e

Cardreader

Size Document Number Rev

Custom

Date : Sheet o f

Tuesday, April 25, 2017

EG521

31 60

1

0.2

5

4

3

2

1

1 2

D D

RTPM1 0_0603_5%TPM@

1

CTPM4

0.1u_0201_10V6K

TPM@

2

1

CTPM1 10U_0603_6.3V6M

2

TPM@

+3VS_TPM+3VS

1A

1

CTPM3

0.1u_0201_10V6K

TPM@

2

TPM

UTPM1

1

NC_1

2

C C

RTPM12

1 2

TPM@

0_0402_5%

Reserve for Nationz TPM

+3VALW

RTPM11

1 2

TPM@

0_0603_5%

Add for Nuvoton TPM

B B

NC_2

3

NC_3

7

PP

6

NC_4

9

NC_7

4

GND_1

11

GND_2

18

GND_3

5

NC_5

8

NC_6

12

NC_8

13

NC_9

14

NC_10

Z32H320TC-LPC-T28-LT1_TSSOP28

TPM@

VDD3 VDD1

LPCPD# SERIRQ

LAD0 LAD1

LFRAME#

LAD2 LAD3

GND_4

LCLK VDD2

CLK_RUN#

LRESET#

24 10

28

SERIRQ_TPM

27

LPC_AD0_TPM

26

LPC_AD1_TPM

23

LPC_FRAME#_TPM

22

LPC_AD2_TPM

20

LPC_AD3_TPM

17

25 21 19

TPM_CLKRUN#

15

16

1 2

RTPM2 4.7K_0402_5%TPM@

RTPM5 0_0402_5%TPM@ RTPM6 0_0402_5%TPM@ RTPM7 0_0402_5%TPM@ RTPM8 0_0402_5%TPM@ RTPM9 0_0402_5%TPM@ RTPM10 0_0402_5%TPM@

PLT_RST# 11,26,37,40,44

1 2 1 2 1 2 1 2 1 2 1 2

+3VS_TPM

Reserve for Nationz TPM

1 2

RTPM13

0_0402_5%

Reserve for Nuvoton TPM

12

RTPM4 0_0402_5%

TPM@

SERIRQ 7,44

LPC_AD0 7,44 LPC_AD1 7,44

LPC_FRAME# 7,44

LPC_AD2 7,44 LPC_AD3 7,44

CLK_PCI_TPM 7

@

+3VS_TPM

PM_CLKRUN# 7

Nationz TPM Nuvoton TPM

RTPM2

RTPM12

RTPM11 NC

Stuff

NC

Stuff

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

TPM

Size Document Number Re v

Custom

Date : Shee t o f

Tuesday, April 25, 2017

EG521

32 60

1

32 60

0.2

5

4

3

2

1

+3VS

1

C1

0.1u_0201_10V6K

D D

PCH_ENVDD

2

SY6288C20AAC_SOT23-5

U5 EN PIN VIH MIN 1.5V

V20B+ +LEDVDD

2A 80 mil

R17 0_0805_5%

LCD POWER CIRCUIT

U5

5

IN

4

EN

OUT

GND

OCB

1 2

1

2

3

R263

1 2

0_0805_5%

2A 80 mil

1

CD@

2

C14

4.7U_0805_25V6-K

Need short

+LCDVDD_CON+LCDVDD

CMOS Camera

W=60mil s

@

RF_NS@

1

2

4.7U_0402_6.3V6M

C121

1

EMC@

2

C15

0.1U_0201_25V6-K

1

2

33P_0402_50V8J

0.1u_0201_10V6K

C122

C123

For RF

CMOS_ON#

0.01U_0201_25V6-K

EMC_NS@

For EMI

Close to R5

C9

0.1u_0201_10V6K

1 2

R5

100K_0402_5%

1

2

+3VS +3VS_CMOS_R

W=40 mils

LP2301ALT1G_SOT23-3

Q7 @

1

C5

@

2

1

C10

0.1u_0201_10V6K

@

2

J1

112

JUMP_43X39

S

G

2

@

2

+3VS_CMOS

D

13

@

1

2

C6

0.01U_0201_10V6K

1 2

R3

0_0603_5%

1

C3

0.1u_0201_10V6K

CD@

2

@

W=40mil s

1

C4 10U_0603_6.3V6M

@

2

EMI Request

R1

1 2

@

0_0402_5%

1 2

PCH_ENVDD

12

+3VS

1 2

12

+3VS

1 2

12

R10

4.7K_0402_5%

@

DISPOFF#

ENBKL

R16 100K_0402_5%

R18 1K_0402_5%

@

INVT_PWM

R20 100K_0402_5%

ENBKL 44

R9

100K_0402_1%

@

1 2

R15

100K_0402_1%

@

1 2

PCH_CMOS_ON#8

EC_CMOS_ON#44

R296 0_0402_5%@

1 2

R297 0_0402_5%@

EMI request

DMIC_CLK

1

EMC@

2

C11

100P_0201_25V8J

PCH_ENVDD4

100K_0402_5%

C C

PCH_ENBKL

R11

1 2

BKOFF#44

PCH_ENBKL4

B B

PCH_EDP_PWM4

R12 0_0402_5%@

1 2

R14 0_0402_5%@

R19 0_0402_5%@

100K_0402_1%

DISPOFF#

+3VS

R8

@

1 2

EDP_AUX EDP_AUX#

R13

@

1 2

EMC_NS@

680P_0402_50V7K

CMOS_ON#

INVT_PWM

1

2

EMC_NS@

C12

470P_0201_50V7-K

1

2

EMC_NS@

C13

470P_0201_50V7-K

CPU_EDP_TX0+4 CPU_EDP_TX0-4

CPU_EDP_TX1+4 CPU_EDP_TX1-4

CPU_EDP_AUX4 CPU_EDP_AUX#4

+3VS

1 2

R21

@

0_0402_5%

1

C22

2

CPU_EDP_TX1+ EDP_TX1+

CPU_EDP_AUX EDP_AUX CPU_EDP_AUX# EDP_AUX#

CPU_EDP_HPD4

W=60mils

DMIC_DATA30

DMIC_CLK30

USB20_P89 USB20_N89

USB20_N8 USB20_N8_R

USB20_P8 USB20_P8_R

+LEDVDD

1 2

C19 0.1u_0201_10V6K

1 2

C16 0.1u_0201_10V6K

1 2

C17 0.1u_0201_10V6K

1 2

C18 0.1u_0201_10V6K

1 2

C20 0.1u_0201_10V6K

1 2

C21 0.1u_0201_10V6K

+LCDVDD_CON

+3VS

1 2

R182 0_0402_5%

1 2

R183 0_0402_5%

+3VS_CMOS

.047U_0201_6.3V6K

EMC_NS@

EMI request

L12

EMC_NS@

1

4

EXC24CH900U_4P

EDP_TX0+CPU_EDP_TX0+ EDP_TX0-CPU_EDP_TX0-

EDP_TX1-CPU_EDP_TX1-

DISPOFF#

INVT_PWM

USB20_P8_R USB20_N8_R

W=40mils

1

C24

2

For EMI

2

3

JEDP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

G1

32

G2

DRAPH_FC5AF301-3181H

ME@

Touch Screen

USB20_P6_CONN

USB20_P6

USB20_N6

A A

L15

1

4

EXC24CH900U_4P

EMC_NS@

For EMI

USB20_P6_CONN

2

USB20_N6_CONN

3

5

+5VS_TS

USB20_N6_CONN

1

D2

1

2

AZ5725-01F.R7GR_DFN1006P2X2

2

EMC_NS@

For ESD

4

3

2

D1 AZC199-02S.R7G_SOT23-3

EMC_NS@

1

Touch Sc reen

+5VS_TS+5VS

1 2

R26 0_0402_5%TS@

0.1u_0201_10V6K

Security Classifi cation

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORM ATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISC LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

1

C25

TS@

EC_TS_ON44

2

LC Future Center Secret Data

USB20_N69 USB20_P69

Deciphered Date

R28 0_0402_5%TS@

1 2

R23 0_0402_5%TS@

1 2

R24 0_0402_5%TS@

2016/08/20

2

JTS1

ME@

1

2

12

TS_RS

USB20_N6_CONN USB20_P6_CONN

Titl e

eDP/CMOS/Touch screen

Size Document Number Re v

Custom

Date : Sheet o f

2

3

4

5

6

CVILU_CI1806M2HR0-NH

Tuesday, April 25, 2017

GND1

GND2

EG521

7

8

0.2

33 60

1

0.2

5

L2

HDMI_CLK-_C

HDMI_CLK+_C HDMI_CLK+_CON

D D

HDMI_TX0-_C

HDMI_TX0+_C

HDMI_TX1-_C HDMI_TX1-_CON

HDMI_TX1+_C

HDMI_TX2-_C

HDMI_TX2+_C

1

4

EXC24CH900U_4P

L3

1

4

EXC24CH900U_4P

L4

1

4

EXC24CH900U_4P

L5

1

4

EXC24CH900U_4P

EMC@

HDMI_CLK-_CON

2

3

HDMI_TX0-_CON

2

HDMI_TX0+_CON

3

2

HDMI_TX1+_CON

3

HDMI_TX2-_CON

2

HDMI_TX2+_CON

3

For EMC

C C

B B

HDMI_CLK-_C

HDMI_CLK+_C

HDMI_TX0-_C

HDMI_TX0+_C

HDMI_TX1-_C

HDMI_TX1+_C

HDMI_TX2-_C

HDMI_TX2+_C

1 2

R29 470_0402_5%

1 2

R30 470_0402_5%

1 2

R31 470_0402_5%

1 2

R32 470_0402_5%

1 2

R33 470_0402_5%

1 2

R34 470_0402_5%

1 2

R37 470_0402_5%

1 2

R38 470_0402_5%

+3VS

1 2

R42

100K_0402_5%

13

D

2

G

S

@

4

EMC_NS@

1 2

C26 3.3P_0402_50V8-C

EMC_NS@

1 2

C27 3.3P_0402_50V8-C

EMC_NS@

1 2

C28 3.3P_0402_50V8-C

EMC_NS@

1 2

C29 3.3P_0402_50V8-C

EMC_NS@

1 2

C30 3.3P_0402_50V8-C

EMC_NS@

1 2

C31 3.3P_0402_50V8-C

EMC_NS@

1 2

C32 3.3P_0402_50V8-C

EMC_NS@

1 2

C33 3.3P_0402_50V8-C

HDMI_HPD4

Q13

2N7002KW_SOT323-3

DDPB_DATA4

1M_0402_5%

HDMI_TX0+4

HDMI_TX0-4

HDMI_TX1+4

HDMI_TX1-4

HDMI_TX2+4

HDMI_TX2-4

HDMI_CLK+4 HDMI_CLK-4

DDPB_CLK4

3

+3VS

5

G

Q1B

S

2N7002KDWH_SOT363-6

G

2

Q1A

S

61

R41 20K_0402_5%

1 2

12 12 12 12 12 12

12 12

D

+5VS

3

D4

1

D4

BAT54S-7-F_SOT23-3

2N7002KDWH_SOT363-6

+3VS

R35

G

2

Q12

1 2

2N7002KW_SOT323-3

13

D

S

HDMI_TX0+ HDMI_TX0+_C H DMI_TX0+_CON

C38 0.1u_0201_10V6K

HDMI_TX0- HDMI_TX0-_C HDMI_TX0-_CON

C37 0.1u_0201_10V6K

HDMI_TX1+

C40 0.1u_0201_10V6K

HDMI_TX1-

C39 0.1u_0201_10V6K

HDMI_TX2+ HDMI_TX2+_C H DMI_TX2+_CON

C42 0.1u_0201_10V6K

HDMI_TX2- HDMI_TX2-_C HDMI_TX2-_CON

C41 0.1u_0201_10V6K

HDMI_CLK+ HDMI_CLK+_C HDMI_CLK+_CON

C36 0.1u_0201_10V6K

HDMI_CLK- HDMI_CLK-_C HDMI_CLK-_CON

C35 0.1u_0201_10V6K

HDMICLK_R

34

D

HDMIDAT_R

2

@

HDMI_DET

SUSP46

R46 0_0402_5%@ R45 0_0402_5%@

HDMI_TX1+_C

R48 0_0402_5%@

HDMI_TX1-_C HDMI_TX1-_CON

R47 0_0402_5%@ R50 0_0402_5%@ R49 0_0402_5%@

R44 0_0402_5%@ R43 0_0402_5%@

12 12 12 12 12 12

12 12

+5VS

+5VS_HDMI

HDMI_TX1+_CON

2

HDMI_DET HDMI_DET

HDMIDAT_R

HDMICLK_R HDMICLK_R

+5VS_HDMI

D3

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

EMC_NS@

9

10

8

9

7

6

For EMC

D5

2

@

3

RB491D_SOT23-3

LP2301ALT1G_SOT23-3

1 3

D

S

Q22

G

2

JHDMI1

18

+5V_Power

7

TMDS_Data0+

9

TMDS_Data0-

4

TMDS_Data1+

6

TMDS_Data1-

1

TMDS_Data2+

3

TMDS_Data2-

8

TMDS_Data0_Shield

5

TMDS_Data1_Shield

2

TMDS_Data2_Shield

11

TMDS_Clock_Shield

10

TMDS_Clock+

12

TMDS_Clock-

ALLTO_C128S9-K1935-L

1

F1

0.5A_6V_1206L050YRHF

0.1u_0201_10V6K

DDC/CEC_Ground

Hot_Plug_Detect

21

ME@

GND1 GND2 GND3 GND4

SDA

CEC

Utility

SCL

+5VS_HDMI+5VS_HDMI_F

C34

15 16

13 17 19

14

20 21 22 23

1

2

HDMIDAT_R

+5VS_HDMI

HDMICLK_R HDMIDAT_R

HDMI_DET

1

14

23

RP1

2.2K_0404_4P2R_5%

8/16 Update HDMIConn. P/N DC021608081 wei

Close to JHDMI1

D6

1

HDMI_CLK-_CON HDMI_CLK-_CON

A A

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

EMC_NS@

HDMI_CLK+_CONHDMI_CLK +_CON

9

10

8

9

HDMI_TX0+_CONHDM I_TX0+_CON

7

6

For EMC

HDMI_TX1-_CON

HDMI_TX1+_CON

HDMI_TX2-_CON

HDMI_TX2+_CONHDMI_TX0-_CON HDMI_TX0-_CON

D7

1

2

4

5

3

8

AZ1045-04F_DFN2510P10E-10-9

EMC_NS@

9

10

8

9

7

6

HDMI_TX1-_CON

HDMI_TX1+_CON

HDMI_TX2-_CON

HDMI_TX2+_CON

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Title

HDMI_CONN

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

EG521

34 60

1

34 60

0.2

5

D D

C C

4

3

2

1

B B

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

P35-Blank

Size Document Number Re v

Custom

Date : Shee t o f

Tuesday, April 25, 2017

EG521

35 60

1

35 60

0.2

5

D D

C C

4

3

2

1

B B

A A

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Title

Blank

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

EG521

36 60

1

36 60

0.2

5

4

3

2

1

+3VALW TO +3VALW_LAN

+3VALW_LAN rising t i me ( 10 %~90 %):

+3VALW +3VALW_LAN

D D

LAN_PWR_ON#44

PCIE_WAKE#11,40,44

C C

LAN_WAKE#40,44

+3VS

12

ISOLATE#

12

RL9 1K_0402_1%

RL11 15K_0402_5%

@

RL2

100K_0402_5%

RL10

+3VALW

@

1 2

0_0402_5%

12

@

1 2

RL3

47K_0402_5%

LAN_PWR_ON#

@

0.1u_0201_10V6K

1 2

RL7 0_0402_5%@

1 2

RL6 0_0402_5%

CL8

1

2

@

Need short

JL1

112

JUMP_43X79

LP2301ALT1G_SOT23-3

S

Q14

G

2

+3VALW_LAN

RL5 10K_0402_5%

@

1 2

PCIE_WAKE#_R

PCIE_PRX_DTX_N59 PCIE_PRX_DTX_P59

2

@

D

13

@

CL9

@

PLT_RST#11,26,32,40,44

0. 5ms＜s p ec＜ 10 0ms

width : 40 mils

1

2

@

4.7U_0402_6.3V6M

@

1 2

0_0402_5%

1 2 1 2

1 2

RL8

2.49K_0402_1%

CL5

1

2

@

TL3 @

TL4 @

CL4

1

2

0.01U_0201_10V6K

Close to Pin11 Close to Pin32

RL12

CL10 0.1u_0201_10V6K CL11 0.1u_0201_10V6K

CL10 close to Pin18 CL11 close to Pin17

CL6

4.7U_0402_6.3V6M

CL7

1

2

1

2

0.1u_0201_10V6K

Close to Pin11 Close to Pin32

manual change the Codec PN to RTL8111GUL-CG

+3VALW_LAN RSET

+LAN_VDD10 LAN_XTALO LAN_XTALI

1

LAN_DISABLE#LAN_PWR_ON#

1

+LAN_REGOUT

+LAN_VDDREG +LAN_VDD10 PCIE_WAKE#_R

ISOLATE#

PLT_RST# PCIE_PRX_C_DTX_N5 PCIE_PRX_C_DTX_P5

UL1

33

GND

32

AVDD33_2

31

RSET

30

AVDD10

29

CKXTAL2

28

CKXTAL1

27

LED0

26

LED1/GPIO

25

LED2

24

REGOUT

23

VDDREG

22

DVDD10

21

LANWAK EB

20

ISOLATEB

19

PERSTB

18

HSON

17

HSOP

RTL8111GUL-CG QFN 32P

8111GUL@

+3VALW_LAN +LAN_VDDREG

RL1

@

1 2

0_0603_5%

CLK_PCIE_LAN#

16

REFCLK_N

REFCLK_P

HSIN

CLKREQB

AVDD33_1

MDIN3 MDIP3

AVDD10_2

MDIN2 MDIP2 MDIN1 MDIP1

AVDD10_1

MDIN0 MDIP0

HSIP

CLK_PCIE_LAN

15

PCIE_PTX_C_DRX_N5

14

PCIE_PTX_C_DRX_P5

13

LAN_CLKREQ#_R

12

+3VALW_LAN

11

LAN_MDI3-

10

LAN_MDI3+

9

+LAN_VDD10

8

LAN_MDI2-

7

LAN_MDI2+

6

LAN_MDI1-

5

LAN_MDI1+

4

+LAN_VDD10

3

LAN_MDI0-

2

LAN_MDI0+

1

CL1

4.7U_0402_6.3V6M

2

LAN_CLKREQ#_R

CLK_PCIE_LAN# 10 CLK_PCIE_LAN 10 PCIE_PTX_C_DRX_N5 9 PCIE_PTX_C_DRX_P5 9

LAN_MDI3- 38 LAN_MDI3+ 38

LAN_MDI2- 38 LAN_MDI2+ 38 LAN_MDI1- 38 LAN_MDI1+ 38

LAN_MDI0- 38 LAN_MDI0+ 38

1

CL2

0.1u_0201_10V6K

2

+3VALW_LAN +3VS

@

RL4

10K_0402_5%

1 2

2

G

QL1

1 3

D

2N7002KW_SOT323-3

1 2

RL18 0_0402_5%@

@

S

LAN_CLKREQ# 10

B B

LAN_XTALO_R

YL1

1

OSC1

GND12OSC2

1

CL12

12P_0402_50V8-J

A A

25MHZ_10PF_7V25000014

2

5

GND2

4

3

1

CL13 15P_0402_50V8J

2

1 2

RL21 1K_0402_5%

4

LAN_XTALI

LAN_XTALO

+LAN_REGOUT

For RTL8111GUL(SWR mode, reserved) For RTL8111H (LDO mode)

1 2

LL1

2.2UH_NLC252018T-2R2J-N_5%

1 2

RL20

Layout Note: LL1 must be within 200mil to Pin24, CL15,CL16 must be within 200mil to LL 1 +LAN_REGOUT: Width =60mil

8111GUL@

8111H@

0_0805_5%

4.7U_0402_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

CL15

2

3

1

CL16

0.1u_0201_10V6K

2

2015/08/20

+LAN_VDD10

1

CL17

0.1u_0201_10V6K

2

1

CL18

0.1u_0201_10V6K

2

Close to Pin3, 8, 22, 30

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

1

CL19

0.1u_0201_10V6K

2

1

CL20

0.1u_0201_10V6K

2

1

CL21 1U_0402_6.3V6K

2

1

CL22

0.1u_0201_10V6K

2

Close to Pin22(Reserved)

Titl e

LAN_RTL8111H_CG

Size Document Number Re v

Custom

Date : Shee t o f

Tuesday, April 25, 2017

EG521

37 60

1

37 60

0.2

5

DL1/DL2 1'S PN:SC300003M00

4

3

2

1

TL1

24

D D

LAN_MDI2+

LAN_MDI2-

LAN_MDI3+

LAN_MDI3-

C C

LAN_MDI1-

LAN_MDI1+

LAN_MDI0-

LAN_MDI0+

DL1

1

LINE1IN

2

3

4

11

12

1

2

3

4

11

12

LINE1OUT

LINE2IN

LINE2OUT

GND1

LINE3IN

LINE4IN5LINE4OUT

GND3

GND4

AZ3133-08F.R7G_DFN30 20P10E10

EMC_NS@

DL2

LINE1IN

LINE2IN

GND1

LINE3IN

LINE4IN5LINE4OUT

GND3

GND4

AZ3133-08F.R7G_DFN30 20P10E10

EMC_NS@

GND2

LINE3OUT

GND5

LINE1OUT

LINE2OUT

GND2

LINE3OUT

GND5

LAN_MDI2+

10

LAN_MDI2-

9

8

LAN_MDI3+

7

LAN_MDI3-

6

13

1

LAN_MDI1-

10

LAN_MDI1+

9

8

LAN_MDI0-

7

LAN_MDI0+

6

13

CL24

0.01U_0201_25V6-K

EMC@

2

EMC

LAN_MDI0+37

LAN_MDI0-37

LAN_MDI1+37

LAN_MDI1-37

LAN_MDI2+37

LAN_MDI2-37

LAN_MDI3+37

LAN_MDI3-37

LAN_MDI0+

LAN_MDI0-

LAN_MDI1+

LAN_MDI1-

LAN_MDI2+

LAN_MDI2-

LAN_MDI3+

LAN_MDI3-

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19

MX2-

18

MCT3

17

MX3+

16

MX3-

15

MCT4

14

MX4+

13

MX4-

BOTH_GST5009 LF

Place Close to TL1

EMC

B B

1 2

RL14 0_0603_5%EMC@

1 2

RL15 0_0603_5%EMC@

1 2

RL16 0_0603_5%EMC@

EMC

CHASSIS1_GND

TCT1

TD1+

TD1-

TCT2

TD2+

TD2-

TCT3

TD3+

TD3-

TCT4

TD4+

TD4-

1

2

3

4

5

6

7

8

9

10

11

12

MCT

LAN_MDO0+

LAN_MDO0-

MCT

LAN_MDO1+

LAN_MDO1-

MCT

LAN_MDO2+

LAN_MDO2-

MCT

LAN_MDO3+

LAN_MDO3-

LAN_MDO0+

LAN_MDO0-

LAN_MDO1+

LAN_MDO2+

LAN_MDO2-

LAN_MDO1-

LAN_MDO3+

LAN_MDO3-

12

EMC@

RL17 20_0603_5%

1

0.022U_0603_50V7K

CL32

EMC@

CHASSIS1_GND

JRJ1

1

TX_DA+

2

TX_DA-

3

RX_DB+

4

BI_DC+

5

BI_DC-

6

RX_DB-

7

BI_DD+

8

BI_DD-

ALLTO_C10235-108 39-L

2

GND_4

GND_3

GND_2

GND_1

8/16 Update RJ45 P/N DC021608091 wei

1

CL25 1000P_1206_2KV7-K

EMC@

2

EMC

ME@

12

11

10

9

CHASSIS1_GND

1

DL3

1

PDT5061_DO-214AA

EMC@

2

EMC

2

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/08/20

3

LC Future Center Secret Data

Deciphered Date

2016/08/20

2

Titl e

LAN_Transformer

Size

Document Number R ev

B

Tuesday, April 25, 2017

Date : Sheet o f

Tuesday, April 25, 2017

EG521

1

38 60

0.2

5

Close to U1

2200P_0201_25V7-K

D D

C44

@

REMOTE+_R

1

2

REMOTE-_R

REMOTE+_R

REMOTE-_R

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: Trace width/space:10/10 mil Trace length:<8"

SMSC thermal sensor

placed near DIMM

+3VS

R51

REMOTE+_R

REMOTE-_R

@

10K_0402_5%

1

C47

0.1u_0201_10V6K

@

2

+3VS

C C

U1

1

VDD

2

D+

3

D-

12

4

T_CRIT#

NCT7718W_MSOP8

Address 1001_101xb

SCL

SDA

ALERT#

GND

@

8

7

6

5

4

1 2

R175 0_0402_5%@

1 2

R176 0_0402_5%@

1 2

R177 0_0402_5%@

1 2

R178 0_0402_5%@

EC_SMB_CK2

EC_SMB_DA2

REMOTE1+

REMOTE2+

REMOTE2-

REMOTE1-

EC_SMB_CK2 7,26,44

EC_SMB_DA2 7,26,44

3

REMOTE1+

100P_0201_25V8J

REMOTE1-

C45

@

NTC_V1

2

1

Near GPU&VRAM

C

2

Q15

B

2

MMBT3904WH_SOT323-3

E

@

3 1

+3VALW

12

R36

13.7K_0402_1%

12

R287 100K_0402_1%_NCP15WF104F03RC

DIS@

R184 0_0402_5%

DIS@

1 2

EC_AGND

R185 0_0402_5%

@

1 2

REMOTE2+

100P_0201_25V8J

REMOTE2-

NTC_V2

1

C46

@

C

2

Q16

B

2

MMBT3904WH_SOT323-3

E

@

3 1

+3VALW

12

R25

13.7K_0402_1%

12

R288 100K_0402_1%_NCP15WF104F03RC

1

Near CPU core

Near CPU

for layout optimized, change the EC_AGND to GND

+5VLP

1

C7

0.1u_0201_10V6K

@

2

B B

A A

5

HW thermal sensor

21.5K_0402_1%

U4

1

2

3

4

over temperature threshold: RSET=3*RTMH 92+/-30C Hysteresis temperature threshold. RHYST=(RSET*RTML)/(3*RTML-RSET) 56+/-30C

@

VCC

TMSNS1

GND

RHYST1

OT1

TMSNS2

RHYST2

OT2

G718TM1U_SOT23-8

8

TMSNS1

7

PHYST1

6

TMSNS2

5

PHYST2

1 2

R6 10K_0402_5%@

1 2

R7 10K_0402_5%@

4

+5VLP +5VLP

R252

@

1 2

R253

21.5K_0402_1%

@

1 2

R196 0_0402_5%@

1 2

R197 0_0402_5%@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

NTC_V1

NTC_V2

2016/08/16

3

NTC_V1 44

NTC_V2 44EC_ON44,54,55

+5VS

1 2

R52 0_0603_5%

1

C49 10U_0805_10V6K

2

LC Future Center Secret Data

Deciphered Date

2017/08/15

2

@

1

2

C50

FAN Conn

JFAN1

EC_FAN_SPEED44 EC_FAN_PWM44

0.1u_0201_10V6K

+5VS_FAN

Titl e

Thermal sensor/FAN CONN

Size Document Number Rev

Custom

Date : Sheet o f

Tuesday, April 25, 2017

ME@

1

2

3

4

5

GND1

6

GND2

ACES_85205-04001

EG521

1

39 60

0.2

A

B

C

D

E

Mini-Express Card(WLAN/WiMAX)

R258

49.9K_0402_1%

+3VS

12

R259

49.9K_0402_1%

UART_RX_DEBUG 8

UART_TX_DEBUG 8

EC_RX 44

SUSCLK 10 PLT_RST# 11,26,32,37,44

PCH_BT_OFF# 8

PCH_WLAN_OFF# 8

SMB_DATA_S3 7,18 SMB_CLK_S3 7,18

EC_TX 44

+3VS_WLAN

Need short

@

J2

2

112

0.1u_0201_10V6K

1 2

AOAC@

0.1u_0201_10V6K

JUMP_43X79

+3VALW

C2083

C2081

LP2301ALT1G_SOT23-3

S

Q36

1

G

@

2

1 AOAC@

2

D

13

AOAC@

2

1 1

AOAC_ON#44

AOAC_ON#

R4677 100K_0402_5%

3/17 SDV Add AOAC Function wei

2 2

+3VS_WLAN+3VS

USB20_P79

1 2 1 2

1 2

USB20_N79

PCIE_PTX_C_DRX_P69 PCIE_PTX_C_DRX_N69

PCIE_PRX_DTX_P69 PCIE_PRX_DTX_N69

CLK_PCIE_WLAN10 CLK_PCIE_WLAN#10

WLAN_CLKREQ_Q# PCIE_WAKE#_WLAN

1

C53

0.1u_0201_10V6K

@

2

0.1u_0201_10V6K

C2082

1

@

2

WLAN_CLKREQ#10

PCIE_WAKE#11,37,44

LAN_WAKE#37,44

R61 0_0402_5% R262 0_0402_5%@

R57 0_0402_5%@

JWLAN1

1

GND1

3

USB_D+

5

USB_D-

7

GND2

9

SDIO_CLK

11

SDIO_CMD

13

SDIO_DATA0

15

SDIO_DATA1

17

SDIO_DATA2

19

SDIO_DATA3

21

SDIO_WAKE#

23

SDIO_RESET#

25 27 29 31

33

GND3

35

PETP0

37

PETN0

39

GND4

41

PERP0

43

PERN0

45

GND5

47

REFCLKP0

49

REFCLKN0

51

GND6

53

CLKREQ0#

55

PEWAKE0#

57

GND7

59

RSRVD/PETP1

61

RSRVD/PETN1

63

GND8

65

RSRVD/PERP1

67

RERVD/PERN1

69

GND9

71

RSRVD/REFCLKP1

73

RSRVD/REFCLKN1

75

GND10

77

GND15

ARGOS_NASE0-S6701-TS40

ME@

3.3VAUX1

3.3VAUX2 LED1#

PCM_CLK/I2S_SCK

PCM_SYNC/I2S_WS

PCM_IN/I2S_SD_IN

PCM_OUT/I2S_SD_OUT

LED#2

GND11

UART_WAKE#

UART_RXD

KEY E PIN24~PIN31 NC PIN

UART_TXD UART_CTS

UART_RTS VENDOR_DEFINED1 VENDOR_DEFINED2 VENDOR_DEFINED3

COEX3 COEX2 COEX1

SUSCLK

PERST0# W_DISABLE2# W_DISABLE1#

I2C_DATA

I2C_CLK

ALERT#

RSRVD

UIM_SWP/PERST1#

UIM_POWER_SNK/CLKREQ1#

UIM_POWER_SRC/GPIO1/PEWAKE1#

3.3VAUX3

3.3VAUX4

GND14

2 4 6 8 10 12 14 16 18 20 22

24 26 28 30

32 34 36 38 40 42 44 46 48 50 52 54 56

58 60 62 64 66 68 70 72 74

76

1

UART_RX_DEBUG_R

UART_TX_DEBUG_R

EC_TX_RSVD EC_RX_RSVD

SUSCLK_R PLT_RST# BT_OFF# WLAN_OFF#

WLAN_SMB_DATA WLAN_SMB_CLK

EC_TX_R

+3VS_WLAN

T2@

T3@

1 2

R256 0_0402_5%

1 2

R257 0_0402_5%

1 2

R62 0_0402_5%@

1 2

R63 0_0402_5%@

1 2

R88 0_0402_5%

1 2

R55 0_0402_5%

1 2

R53 1K_0402_5%

1 2

R56 0_0402_5%@

1 2

R58 0_0402_5%@

1 2

R59 0_0402_5%@

1 2

R89 0_0402_5%

12

R186 100K_0402_5%

8/16 Update Conn. P/N SP070013200 wei

Optane Memory

JSSD1 ME@

1

GND_1

3

GND_2

+3VS +VS_SSD

Need short

112

JUMP_43X79

2

@

22U_0603_6.3V6-M

C137

1

2

OPTANE@

R3102

10K_0402_5%

SSD_DET#9

10K_0402_5%

R3101

A

0.1u_0201_10V6K

22U_0603_6.3V6-M

C207

C146

1

2

OPTANE@

+VS_SSD

12

8/24 CPU side 10K PU wei

@

12

SSD_DET #

@

0-- SATA 1--PCIE

3 3

J14

4 4

0.1u_0201_10V6K

C2048

SSD_DET#

1

2

OPTANE@

MAX 1.5A

0.01U_0201_10V6K

C2049

0.01U_0201_10V6K

C2050

1

2

OPTANE@

B

PCIE_PRX_DTX_N99 PCIE_PRX_DTX_P99

PCIE_PTX_C_DRX_N99 PCIE_PTX_C_DRX_P99

PCIE_PRX_DTX_N109 PCIE_PRX_DTX_P109

PCIE_PTX_C_DRX_N109 PCIE_PTX_C_DRX_P109

PCIE_PRX_DTX_N119 PCIE_PRX_DTX_P119

PCIE_PTX_C_DRX_N119 PCIE_PTX_C_DRX_P119

PCIE_PRX_DTX_P129 PCIE_PRX_DTX_N129

PCIE_PTX_C_DRX_N129 PCIE_PTX_C_DRX_P129

CLK_PCIE_SSD#10 CLK_PCIE_SSD10

SSD_DET#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

C

5

PERN3

7

PERP3

9

GND_3

11

PETN3

13

PETP3

15

GND_4

17

PERN2

19

PERP2

21

GND_5

23

PETN2

25

PETP2

27

GND_6

29

PERN1

31

PERP1

33

GND_7

35

PETN1

37

PETP1

39

GND_8

41

PERN0/SATA_B+

43

PERP0/SATA_B-

45

GND_9

47

PETN0/SATA-A-

49

PETP0/SATA-A+

51

GND_10

53

REFCLKN

55

REFCLKP

57

GND_11

59

NC

61

NC

63

NC

65

NC

67

N/C_1

69

PEDET

71

GND_12

73

GND_13

75

GND_14

77

PEG1

ARGOS_NASM0-S6701-TSH4

2016/12/14

DAS/DSS#/LED1#

CLKREQ#

PEWAKE#

LC Future Center Secret Data

2

3.3V_1

4

3.3V_2

6

N/C_2

8

N/C_3

10 12

3.3V_3

14

3.3V_4

16

3.3V_5

18

3.3V_6

20

N/C_4

22

N/C_5

24

N/C_6

26

N/C_7

28

N/C_8

30

N/C_9

32

N/C_10

34

N/C_11

36

N/C_12

38

DEVSLP

40

N/C_13

42

N/C_14

44

N/C_15

46

N/C_16

48

N/C_17

50

PERST#

52 54 56

N/C_18

58

N/C_19

NC

60

NC

62

NCNC64

66

68

SUSCLK

70

3.3V_7

72

3.3V_8

74

3.3V_9

76

PEG2

Deciphered Date

D

+VS_SSD

PLT_RST# SSD_CLKREQ_Q#

1

@

TP264

+VS_SSD

R3099

@

10K_0402_5%

1 2

R3100 10K_0402_5%

1 2

R3098 0_0402_5%

2017/12/13

OPTANE@

SSD_PCIE_CLKREQ# 10

Titl e

NGFF WLAN&SSD

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

EG523

E

40 60

0.2

A

LEFT SIDE USB3.0 PORT x2

+5VALW +USB_VCCA

1 1

1

C128 1U_0402_6.3V6K

2

USB_ON#44

U2

5

OUT

IN

GND

4

OCB

ENB

SY6288D20AAC_SOT23-5

Low Active 2A

1

2

USB_OC1#

3

1

C140 1000P_0201_50V7-K

EMC_NS@

2

B

USB_OC1# 9

C

1 2

USB30_TX_P19

USB30_TX_N19

USB20_P19

USB20_N19

USB30_RX_P19

USB30_RX_N19

C126 0.1u_0201_10V6K

USB30_TX_N1 USB30_TX_C_N1 USB30_TX_R_N1

USB30_RX_P1 USB30_RX_R_P1

1 2

C124 0.1u_0201_10V6K

USB30_TX_C_P1 USB30_TX_R_P1USB30_TX_P1

R95 0_0402_5%@

R96 0_0402_5%@ R97 0_0402_5%@

R93 0_0402_5%@ R94 0_0402_5%@

R98 0_0402_5%@

1 2

1 2 1 2

1 2

D

+USB_VCCA

+

1 2

C55

220U_6.3V_M

1 2

C1117

47U_0805_6.3V6-M@

1 2

C125

1U_0402_10V6K@

1 2

C127

1U_0402_10V6K@

JUSB1

9

StdA_SSTX+

1

VBUS

8

USB20_P1_RUSB20_P1

USB20_N1_RUSB20_N1

USB30_RX_R_N1USB30_RX_N1

StdA_SSTX-

3

D+

7

GND_DRAIN

2

D-

6

StdA_SSRX+

4

GND_1

5

StdA_SSRX-

ALLTO_C190AG-10939-L

ME@

GND_2 GND_3 GND_4 GND_5

E

10 11 12 13

09/05 Update USBConn. P/N DC021609011 wei

L13

USB30_RX_N1 USB30_RX_R_N1

USB30_RX_P1 USB30_RX_R_P1

USB30_TX_C_N1 USB30_TX_R_N1

USB30_TX_C_P1 USB30_TX_R_P1

2 2

USB20_P1

USB20_N1

1

4

EXC24CH900U_4P

L16

1

4

EXC24CH900U_4P

L8

1

4

EXC24CH900U_4P

EMC@

2

3

2

3

USB20_P1_R

2

USB20_N1_R

3

+USB_VCCA

1

EMC@

2

AZ5725-01F.R7GR_DFN1006P2X2

D11

1

2

EMC

USB20_P1_R

USB20_N1_R

D12

EMC@

USB30_RX_R_N1

9

3

2

1

D13 AZC199-02S.R7G_SOT23-3

EMC@

USB30_RX_R_P1

USB30_TX_R_P1

10

8

9

7

6

AZ1045-04F_DFN2510P10E-10-9

USB30_RX_R_N1

1

USB30_RX_R_P1

2

USB30_TX_R_N1USB30_TX_R_N1

4

USB30_TX_R_P1

5

3

8

+USB_VCCA

1 2

C2060

1U_0402_10V6K@

1 2

C2059

L30

USB30_RX_N3 USB30_RX_R_N3

USB30_RX_P3 USB30_RX_R_P3

3 3

4 4

USB30_TX_C_N3 USB30_TX_R_N3

USB30_TX_C_P3 USB30_TX_R_P3

USB20_P3

USB20_N3

A

1

4

EXC24CH900U_4P

L29

1

4

EXC24CH900U_4P

L17

EMC@

1

4

EXC24CH900U_4P

EMC@

2

3

2

3

USB30_TX_P39

USB30_TX_N39

USB20_P39

USB20_N39

USB30_RX_P39

USB30_RX_N39

USB30_TX_N3 USB30_TX_C_N3 USB30_TX_R_N3

USB20_P3

USB20_N3

USB30_RX_P3 USB30_RX_R_P3

USB30_RX_N3

1 2

C2058 0.1u_0201_10V6K

1 2

C2057 0.1u_0201_10V6K

USB30_TX_C_P3 USB30_TX_R_P3USB30_TX_P3

1 2

R3119 0_0402_5%@

1 2

R3116 0_0402_5%@

1 2

R3103 0_0402_5%@

1 2

R942 0_0402_5%@

1 2

R3117 0_0402_5%@

1 2

R3114 0_0402_5%@

USB20_P3_R

USB20_N3_R

USB30_RX_R_N3

09/05 Update USBConn. P/N DC021609011 wei

USB20_P3_R

2

USB20_N3_R

3

USB20_P3_R

USB20_N3_R

3

2

D43 AZC199-02S.R7G_SOT23-3

EMC@

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

B

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

C

+USB_VCCA

1

2

AZ5725-01F.R7GR_DFN1006P2X2

2015/08/20

D34

1

EMC_NS@

2

LC Future Center Secret Data

Deciphered Date

D

Close to ConnectorFOR ESD

USB30_RX_R_N3

USB30_RX_R_P3

USB30_TX_R_P3 USB30_TX_R_P3

2016/08/20

1U_0402_10V6K@

JUSB3

9

StdA_SSTX+

1

VBUS

8

StdA_SSTX-

3

D+

7

GND_DRAIN

2

D-

6

StdA_SSRX+

4

GND_1

5

StdA_SSRX-

ALLTO_C190AG-10939-L

D45

9

10

8

9

7

6

AZ1045-04F_DFN2510P10E-10-9

Titl e

Size

C

Date: Sheet of

ME@

10

GND_2

11

GND_3

12

GND_4

13

GND_5

EMC@

USB30_RX_R_N3

1

USB30_RX_R_P3

2

USB30_TX_R_N3USB30_TX_R_N3

4

5

3

8

USB3.0 PORT (LEFT)

Document Number Rev

Tuesday, April 25, 2017

EG521

E

41 60

0.2

A

B

C

D

E

F

G

H

SATA HDD Conn.

1 1

+5VS_HDD

SATA_PTX_DRX_P09

1

C74 33P_0201_50V8-J

RF@

2

1

C76 33P_0201_50V8-J

RF@

2

1

C75

0.1u_0201_10V6K

2

1

C77 10U_0805_10V6K

2

1

C78 10U_0805_10V6K

@

2

SATA_PTX_DRX_N09

SATA_PRX_DTX_N09 SATA_PRX_DTX_P09

For EMC

2 2

+5VS +5V_ODD

Need Short

J4

@

2

112

JUMP_43X79

C85

1

CD@

2

10U_0603_10V6K

0.1u_0201_10V6K

C86

SATA_PTX_DRX_P0 SATA_PTX_DRX_N0

SATA_PRX_DTX_P0

1 2

C66 0.01U_0201_10V6K

1 2

C67 0.01U_0201_10V6K

1 2

C68 0.01U_0201_10V6K

1 2

C69 0.01U_0201_10V6K

+5VS +5VS_HDD

Need short

J3

JUMP_43X79

112

SATA_PTX_C_DRX_P0 SATA_PTX_C_DRX_N0

SATA_PRX_C_DTX_N0SATA_PRX_DTX_N0 SATA_PRX_C_DTX_P0

2

@

JHDD1

10

9

8

7

GND2

6

5

4

3

GND1

2

1

ELCO_006809610010846

ME@

12

11

FOR 14"

SATA ODD Conn.

3 3

4 4

SATA_PTX_DRX_P19 SATA_PTX_DRX_N19

SATA_PRX_DTX_N19 SATA_PRX_DTX_P19

A

SATA_PTX_DRX_P1 SATA_PTX_DRX_N1

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1

SATA_PTX_DRX_P1 SATA_PTX_DRX_N1

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1

1 2

C79 0.01U_0201_10V6K15@

1 2

C80 0.01U_0201_10V6K15@

1 2

C81 0.01U_0201_10V6K15@

1 2

C82 0.01U_0201_10V6K15@

SATA_PTX_C_DRX_P1_15 SATA_PTX_C_DRX_N1_15

SATA_PRX_C_DTX_N1_15 SATA_PRX_C_DTX_P1_15

+5V_ODD

8/16 Update Conn. P/N SP01001YV00 wei

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

D

2015/08/20

LC Future Center Secret Data

Deciphered Date

E

F

2016/08/20

Titl e

HDD/ODD CONN

Size Document Number Rev

Custom

Date : Sheet o f

G

FOR 15" 17''

SATA ODD FFC Conn

JODD2

1

ME@

1

2

3

4

5

6

7

8

9

GND1

10

GND2

HIGHS_FC5AF081-2931H

EG521

Tuesday, April 25, 2017

EG521

42 60

H

0.2

5

D D

4

3

2

1

USB30_TX_N29 USB30_TX_P29

USB30_RX_N29 USB30_RX_P29

C C

USB30_RX_N2 USB30_RX_P2

USB30_TX_N2 USB30_TX_P2

+3V_MUX +3V_MUX

B B

+3V_MUX

A A

USB30_TX_N2 USB30_TX_P2

USB30_RX_N2 USB30_RX_P2

+3VALW

C2068 0.1U_0201_6.3V6-K

1 2

C2067 0.1U_0201_6.3V6-K

1 2

C2065 0.1U_0201_6.3V6-K

1 2

C2066 0.1U_0201_6.3V6-K

1 2

R3139

R3142

10K_0402_5%

1 2

M1 M0

R3144 10K_0402_5%@

1 2

R3146 10K_0402_5%@

1 2

VBUS_EN

R3141 10K_0402_5%

1 2

PH at CPU side 09/06 wei

R3147 10K_0402_5%@

TYPE_C_OCP#

R3140 10K_0402_5%@

10K_0402_5%@

R4674 10K_0402_5%

1 2

R133 0_0402_5%

1 2

+3VS

R134 0_0402_5%@

1 2

TYPE_C_OCP# VBUS_EN

VMON

USB30_RX_N2_M USB30_RX_P2_M

USB30_TX_N2_M USB30_TX_P2_M

M1 M0

R3150

6.2K_0402_1%

Rp configuration

Rp:1.5A (now)

Rp:900mA

Rp:1.5A

Rp:3.0A

For C_VBUS power switch enable pin

Power switch enable pin

High Active

For C_VBUS power switch OCP pin

Power switch OCP pin

High Active

5

1 2

+3V_MUX +5V_MUX

U26

16

OCP_DET

15

VBUS_EN

17

VMON

4

SSRX_1P/2N

5

SSRX_1N/2P

SSTX_1P/2N SSTX_1N/2P

NC RP_SEL_M1 RP_SEL_M0

REXT

M1 M0

1

1 1

10Gbps 2:1 MUX

10

0

R3146 mountLow Active

R3141 mount

6 7

23 21 22

18

+5VALW

Realtek

RTS5449

RTS5449-GR_QFN24_4X4

R3144/R3142 mount

R3139/R3143 mount

R3139/R3142 mount

Note

R3147 mountLow Active

R3140 mount

+5VS

C_TX2_1P/2N C_TX2_1N/2P

C_RX2_1P/2N C_RX2_1N/2P

C_TX1_1P/2N C_TX1_1N/2P

C_RX1_1P/2N C_RX1_1N/2P

Note

VCON_IN

LDO_3V3

R173 0_0402_5%

1 2

R174 0_0402_5%@

1 2

2

1

12

CC1

14

CC2

MUX_TX2_N

11

MUX_TX2_P

10

24 1

MUX_TX1_N

8

MUX_TX1_P

9

2 3

13

19

5V_IN

20

25

E-PAD

4

CC1271 220P_0201_25V7-K

2

CC1272 220P_0201_25V7-K

1

CC1

C2076 0.1U_0201_6.3V6-K C2075 0.1U_0201_6.3V6-K

C2073 0.1U_0201_6.3V6-K C2074 0.1U_0201_6.3V6-K

CC1273

CC2

1 2 1 2

+3V_MUX

2

1

C2064

1

2

0.1u_0201_10V6K

4.7U_0402_6.3V6M

Close Pin19

USB20_P29

USB20_N29

+5VALW VBUS_P0

1 2

Iset =6800/3.3k=2.06A

11/16 SIT Reserve Power switch for OPC# flip issue wei

A5 B5

C_TX2_N

B3

C_TX2_P

B2

C_RX2_N

A10

C_RX2_P

A11

C_TX1_N

A3

C_TX1_P

A2

C_RX1_N

B10

C_RX1_P

+5V_MUX

B11

2

C2063

C2077

1

10U_0805_10V6K

0.1u_0201_10V6K

Close Pin13

@

R943 0_0402_5%

1 2

L23

112

4

EXC24CH900U_4P

@

R91 0_0402_5%

1 2

@

R944 0_0402_5%

12

L24

C_TX2_N

C_TX2_P C_TX2_P_C

C_RX2_P

C_RX2_N

EMC@

334

2

EXC24CH900U_4P

@

R3107 0 _0402_5%

12

@

R100 0_0402_5%

12

L25

EMC@

334

2

EXC24CH900U_4P

@

R101 0_0402_5%

12

47U_0805_6.3V6-M

VBUS_P0

EMC@

2

3

4

1

4

1

1.5A

1

C213

2

VBUS_EN TYPE_C_OCP#

12

R3155 200K_0402_1%

VMON

R3149 10K_0402_1%

1 2

C_DP

C_DM

C_TX2_N_C

C_RX2_P_C

C_RX2_N_C

3

U27

1

6

OUT

IN

2

5

R4183 .3K_0402_1%

VBUS_EN TYPE_C_OCP#

1

+

C1333 150U_B2_6.3VM_R35M

@

2

A1 B1 C1

D3

EMC_NS@

GND

ISET

3

4

OCB

EN/ENB

SY6861B1ABC_SOT23-6

VBUS_P0+5VALW

U6

VIN1 VIN2 VIN3

ON

GND3

GND2B2GND1

A2

C2

VBUS_P0

1

D38

1

2

AZ5725-01F.R7GR_DFN1006P2X2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A3

VOUT1

B3

VOUT2

C3

VOUT3

D1

OC_FLAGB

D2

ISET

FPF2595UCX_WLCSP12@

Rset 528 Min 1800mA Type 2000mA Max 2200mA Rset 469 Min 2025mA Type 2250mA Max 2475mA

1

12

C918

2

C_RX1_N

C_RX1_P

C_TX1_P C_TX1_P_C

C_TX1_N C_TX1_N_C

C919

@

2

10U_0805_25V6K

4.7U_0805_25V6-K

C922

0.47U_0402_25V6-K

@

R3135 0 _0402_5%

1 2

L31

4

112

EXC24CH900U_4P

@

R3137 0 _0402_5%

1 2

@

R3136 0 _0402_5%

1 2

L32

4

112

EXC24CH900U_4P

R3138 0 _0402_5%

1 2

2015/08/20

TYPE_C_OCP# 9

12

R604 523_0402_1%@

12

C921

C920

0.47U_0402_25V6-K

EMC@

3

2

EMC@

3

2

@

LC Future Center Secret Data

Deciphered Date

2

C1334

C_RX1_N_C

C_RX1_P_C

C_TX2_P_C

C_TX2_N_C

C_RX1_N_C

C_RX1_P_C

0.47U_0402_25V6-K

D36

EMC_NS@

9

10

1

8

9

2

7

4

6

5

3

8

AZ1045-04F_DFN2510P10 E-10-9

2016/08/20

28

GND525GND626GND727GND8

GND929GND1030GND1131GND12

HIGHS_UB11246-15A0C-1H

32

C_RX1_P_C

C_RX1_N_C

C_DM

C_DP

CC2

C_TX2_N_C

C_TX2_P_C

24

23

22

21

20

19

18

17

16

15

14

13

JP1

Power_GND_B12

SSRXp1_B11

SSRXn1_B10

VBUS_B9

SBU2_B8

Dn2_B7

Dp2_B6

CC2_B5

VBUS_B4

SSTXn2_B3

SSTXp2_B2

GND_B1

09/02 Update Type-C Conn. DC021608291 wei

CC1 CC2

312

D47

EMC_NS@

AZC199-02S.R7G_SOT23-3

C_TX2_P_C

1

C_TX2_N_C

2

C_RX1_N_C

4

C_RX1_P_C

5

3

C_TX1_P_C

C_TX1_N_C

C_RX2_P_C

9

8

7

6

For ESD

Title

3D Camera

Size Document Number Re v

Custom

Tuesday, April 25, 2017

Date: Sheet o f

3A

ME@

1

GND_A1

2

SSTXp1_A2

3

SSTXn1_A3

4

VBUS_A4

5

CC1_A5

6

Dp1_A6

7

Dn1_A7

8

SBU1_A8

9

VBUS_A9

10

SSRXn2_A10

11

SSRXp2_A11

12

GND_A12

C_DP C_DM

312

D48

AZC199-02S.R7G_SOT23-3

D20

EMC_NS@

10

1

2

9

2

4

7

4

5

6

5

3

8

AZ1045-04F_DFN2510P10 E-10-9

EG521

1

VBUS_P0

C_TX1_P_C

C_TX1_N_C

CC1

C_DP

C_DM

C_RX2_N_C

C_RX2_P_C

EMC_NS@

C_TX1_P_C

C_TX1_N_C

C_RX2_N_CC_RX2_N_C

C_RX2_P_C

43 60

0.2

5

For ESD

PLT_RST#

1

CE1 220P_0201_25V7-K

EMC@

2

D D

WRST#26

+3VL_EC

1 2

DE1

RB751V-40_SOD323-2

RE8

C C

+3VL_EC

2.2K_0404_4P2R_5%

+3VS

2.2K_0404_4P2R_5%

B B

+3VL

1 2

RE35 10K_0402_5%@

1 2

RE36 10K_0402_5%@

RE38 100K_0402_5%

1 2

RE40 10K_0402_5%

1 2

100K_0402_5%

RPE2

2 3 1 4

RPE3

1 4 2 3

H_PECI4

EC_VR_ON59

@

EC_ON

PM_SLP_S3#

12

For EMI

CLK_PCI_EC

KBRST#7

SERIRQ7,32

LPC_FRAME#7,32

LPC_AD37,32 LPC_AD27,32 LPC_AD17,32 LPC_AD07,32

CLK_PCI_EC7

1

CE12 1U_0402_6.3V6K

2

KSI[0..7]45

KSO[0..17]45

EC_SMB_DA1 EC_SMB_CK1

EC_SMB_CK2 EC_SMB_DA2

1 2

+3VL

DE2

ON/OFF

BKOFF#

LID_SW#

BKOFF#

12

1 2

RE58 0_0402_5%@

RE24 43_0402_5%

1 2

RE2 33_0402_5%

EMC@

22P_0402_50V8-J

RE56 0_0402_5%@ RE59 0_0402_5%@ RE60 0_0402_5% RE61 0_0402_5% RE62 0_0402_5% RE63 0_0402_5% RE64 0_0402_5%

EC_SMI#9 EC_RX40 EC_TX40

PLT_RST#11,26,32,37,40

EC_SCI#4

KSI[0..7]

KSO[0..17]

EC_SMB_CK1 EC_SMB_DA1

KSI7 KSI6 WRST#

For factory EC flash

ON/OFF45

EC_SMB_CK152,53 EC_SMB_DA152,53

LAN_PWR_ON#37

EC_SMB_CK27,26,3 9 EC_SMB_DA27,26,3 9

RE27 0_0402_5%@ RE272 0_0402_5%

RB751V-40_SOD323-2@

USB_ON#41

DPWROK_EC11

EC_RSMRST#11

PCIE_WAKE#11,37,40

AC_PRESENT11

1

CE2

EMC@

2

1 2 1 2 1 2 1 2 1 2

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1

PAD @

1 2 1 2

12 12

CLK_PCI_EC WRST#

EC_RX EC_TX PLT_RST#

EC_RTCRST#_ON

IT1 IT2 IT3 IT4 IT5

IT6 IT7 IT8

ON/OFF

EC_SMB_CK1 EC_SMB_DA1 PECI_EC

EC_SMB_CK2 EC_SMB_DA2

USB_ON#

PCIE_WAKE#

for EC version update to EX, manual modify PN to FX

+3VL

GPG2

A A

GPG2

when mirror, GPG2 pull high when no mirror, GPG2 pull low

12

RE43 10K_0402_5%@

12

RE44 10K_0402_5%

12

RE46 10K_0402_5%@

+3VL_EC

EC_SPI_CS0#

RE45 0_0402_5%@

EC_SPI_SI

RE47 0_0402_5%@

EC_SPI_SO

RE48 0_0402_5%@

EC_SPI_CLK

RE49 0_0402_5%@

5

4

Close EC

1 2

CE3

0.1u_0201_10V6K

Change RE6 to 0ohm jump

RE6 0_0402_5%@

LPC_FRAME#_EC LPC_AD3_EC LPC_AD2_EC LPC_AD1_EC LPC_AD0_EC

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

12

VCOREVCC

1 2

UE1

4

KBRST#/GPB6

5

SERIRQ/GPM6

6

LFRAME#/GPM5

7

LAD3/GPM3

8

LAD2/GPM2

9

LAD1/GPM1

10

LAD0/GPM0

13

LPCCLK/GPM4

14

WRST#

15

ECSMI#/GPD4

16

PWUREQ#/BBO/SMCLK2ALT/GPC7

17

LPCPD#/GPE6

22

LPCRST#/GPD2

23

ECSCI#/GPD3

126

GA20/GPB5

58

KSI0/STB#

59

KSI1/AFD#

60

KSI2/INIT#

61

KSI3/SLIN#

62

KSI4

63

KSI5

64

KSI6

65

KSI7

36

KSO0/PD0

37

KSO1/PD1

38

KSO2/PD2

39

KSO3/PD3

40

KSO4/PD4

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

56

KSO16/SMOSI/GPC3

57

KSO17/SMISO/GPC5

110

PWRSW#

111

XLP_OUT

115

SMCLK1/GPC1

116

SMDAT1/GPC2

117

SMCLK2/PECI/GPF6

118

SMDAT2/PECIRQT#/GPF7

94

CRX1/SIN1/SMCLK3/GPH1/ID1

95

CTX1/SOUT1/GPH2/SMDAT3/ID2

112

VSTBY0

125

GPE4

33

GINT/CTS0#/GPD5

35

RTS1#/GPE5

93

CLKRUN#/GPH0/ID0

2

CK32KE/GPJ7

128

CK32K/GPJ6

IT8586E-AX_LQFP128_14X14

SPI_CS0#

SPI_SI

SPI_SO

SPI_CLK

4

+3VS

11

12

3

VCC

VBAT

VCORE

IT8586E/AX LQFP-128L

Int. K/B Matrix

EXTERNAL SERIAL FLASH

SM Bus

WAKE UP

GPIO

Clock

1

SPI_CS0# 7

SPI_SI 7

SPI_SO 7

SPI_CLK 7

1 2

RE1 0_0603_5%

1 2

RE3 0_0603_5%@

+3VL_EC_R

74

50

92

114

121

127

AVCC

VSTBY2

VSTBY3

VSTBY4

VSTBY126VSTBY5

VSTBY(PLL)

PWM

LPC

SPI Flash ROM

VSS1

VSS2

VSS4

VSS5

VSS349VSS6

27

91

113

122

NOVO#

1

2

3

+3VL

+3VALW

+3VL_EC

All capacitors close to EC

1

CD@

2

0.1u_0201_10V6K

CE6

0.1u_0201_10V6K

CE7

minimum trace width 12 mil

PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5

PWM6/SSCK/GPA6

PWM7/RIG1#/GPA7

TMRI0/GPC4 TMRI1/GPC6

ADC0/GPI0 ADC1/GPI1 ADC2/GPI2

ADC

ADC3/GPI3

ADC4/GPI4 ADC5/DCD1#/GPI5 ADC6/DSR1#/GPI6

ADC7/CTS1#/GPI7

DAC2/TACH0B/GPJ2 DAC3/TACH1B/GPJ3

DAC

DAC4/DCD0#/GPJ4

DAC5/RIG0#/GPJ5

PS2CLK0/TMB0/CEC/GPF0

PS2DAT0/TMB1/GPF1

PS2

UART

GPIO

DTR1#/SBUSY/GPG1/ID7

AVSS

75

EC_AGND

CE48

0.01U_0201_10V6K

EMC_NS@

GPF2

GPF3 PS2CLK2/GPF4 PS2DAT2/GPF5

GPH3/ID3 GPH4/ID4 GPH5/ID5 GPH6/ID6

AC_IN#

LID_SW#

EGAD/GPE1 EGCS#/GPE2 EGCLK/GPE3

GPJ1 SSCE0#/GPG2 SSCE1#/GPG0

DSR0#/GPG6

CRX0/GPC0

CTX0/TMA0/GPB2

RI1#/GPD0 RI2#/GPD1

TACH2/GPJ0

TACH1A/TMA1/GPD7

TACH0A/GPD6

L80HLAT/BAO/GPE0

L80LLAT/GPE7

PECI_EC

BATT_TEMP

ACIN#

ON/OFF

NC1 NC2 NC3 NC4

3

2

+3VL_EC+3VL_EC

1 2

LE1 0_0603_5%@

1

2

CE10

0.1u_0201_10V6K

PWR_LED# 45 BATT_CHG_LED# 45 BATT_LOW_LED# 45

EC_VCCST_PWRGD 11 SYS_PWROK 11 EC_FAN_PWM 39 BEEP# 30

SUSP# 46

NTC_V1 39 NTC_V2 39

BATT_TEMP 52,53

PM_SLP_SUS# 11

CPU_VR_READY 59

ADP_I 53

1 2

SUSWARN# 11

SUSACK# 11

ENBKL 33

PBTN_OUT# 11 EC_SMB_CK3 55 EC_SMB_DA3 55

EC_LID_OUT# 45

CAPS_LED# 45 PCH_PWR_EN 46,55 EC_BKL_EN 45 PCH_PWROK 11

LID_SW# 45

AOAC_ON# 40

VDDQ_PGOOD 55

EC_VPP_PWREN 55

EC_MUTE# 30

EC_CMOS_ON# 33

1 2

BKOFF# 33

PM_SLP_S3# 11,13 PM_SLP_S4# 11 NOVO# 45

EC_TS_ON 33

EC_FAN_SPEED 39

NUM_LED# 45

1 2

0_0402_5%

100_0402_5%

2N7002KW_SOT323-3

2015/08/20

@

1

2

CE11

RE2760_0402_5%

1 2

RE267

QE1

2

G

0.1u_0201_10V6K

1 2

RE54

0_0402_5%

PSYS 53,59

RE570_0402_5%

SYSON

RE55 0_0402_5%@

12

Reserve for VGA_AC_DET

12

1

CE14 47P_0201_25V8-J

EMC_NS@

2

13

D

S

+3VS

1

2

ACIN#11

CE19

0.1u_0201_10V6K

LC Future Center Secret Data

Deciphered Date

+3VL_EC

1 2

LE2 0_0603_5%@

12

RE65 100K_0402_5%

VGA_AC_DET

ACIN#

2

CE4

0.1u_0201_10V6K

EC_VCCIO_EN

H_PROCHOT# 4,55

+3VL

1 2

13

D

S

2N7002KW_SOT323-3

@

EC_ON 39,54,55

RE42 100K_0402_5%

@

1

2

0.1u_0201_10V6K

CE8

24 25 28 29 30 31 32 34 120 124

66 67 68 69 70 71 72 73

78 79 80 81

85 86 87 88 89 90

96 97 98 99

101 102 103 105

108 109

82 83 84

77 100 106 104 107 119 123 18 21 76 48 47 19 20

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

0.1u_0201_10V6K

CE9

PWR_LED#

EC_VCCST_PWRGD

EC_FAN_PWM

EC_VCCST_EN_R EC_VCCST_EN LAN_WAKE#

SUSP#

BATT_TEMP

B+_Track

H_PROCHOT#_EC

EC_ON_GPIO

EC_SMB_CK3 EC_SMB_DA3

1

EC_LID_OUT#

EC_SPI_CS0# EC_SPI_SI EC_SPI_SO EC_SPI_CLK

ACIN# LID_SW#

EC_VPP_PWREN

GPG2

SYSON_R BKOFF#

EC_FAN_SPEED

VR_HOT#53,59

CE15 47P_0201_25V8-JEMC_NS@

CE16 100P_0201_25V8JEMC_NS@

CE17 100P_0201_25V8JEMC_NS@

CE18 1U_0402_6.3V6K@

Issued Date

TE1 @

RE271 0_0402_5%

RE34

H_PROCHOT#_EC

1 2

+3VL_EC_R

1

2

EC_AGND

EC_VCCST_EN 13

ME_FLASH 8 SYSON 55

EC_VCCIO_EN 13

VGA_AC_DET 26

1 2

RE262 0_0402_5%

QE2

2

G

2016/08/20

1

V20B+

12

B+_Track

LAN_WAKE# 37,40

+3VL_EC+3VALW

12

@

12

RE274 0_0402_5%

1

CE5 1000P_0201_50V7-K

2

EC_FAN_SPEED

EC_FAN_PWM

LPC_FRAME#

ENBKL

CPU_VR_READY

EC_CMOS_ON#

EC_LID_OUT#

+3VL_EC

12

RE5 10K_0402_5%

LAN_WAKE#

1 2

RE10 10K_0402_5%

1 2

RE11 10K_0402_5%@

1 2

RE7 10K_0402_5%@

1 2

RE9 100K_0402_5%@

1 2

RE270 10K_0402_5%

1 2

RE275 10K_0402_5%@

1 2

RE277 10K_0402_5%@

For PMIC

0_0402_5%

EC_SMB_DA3 EC_SMB_CK3

USB_ON#

SUSP#

SYSON_R

EC_VCCST_EN

EC_VCCIO_EN

RPE4

1 4 2 3

2.2K_0404_4P2R_5%

1 2

RE15 100K_0402_5%

1 2

RE18 100K_0402_5%@

1 2

RE19 100K_0402_5%

1 2

RE21 100K_0402_5%

1 2

RE269 100K_0402_5%@

1 2

RE268 100K_0402_5%@

Add to fix Reset&PWRGD test fail issue

VDDQ_PGOOD

CE51 0.01U_0201_10V6K

PM_SLP_S4#

CE50 1000P_0201_50V7-KEMC_NS@

PM_SLP_S3#

CE21 1000P_0201_50V7-KEMC_NS@

SYSON

CE13 1000P_0201_50V7-KEMC_NS@

RE273

1 2

EMC Request

DE3

1 2

RB751V-40_SOD323-2

12

@

ACIN 53

Tuesday, April 25, 2017

2

@

QE3

G

13

D

S

2N7002KW_SOT323-3@

EG521

1

EC_RTC_RST# 10

PM_SLP_S4#

EC_RTCRST#_ON

RE50

100K_0402_5%

Titl e

EC ITE8586LQFP

Size

Document Number Rev

C

Date: Sheet of

RE261 470K_0402_5%

@

R260 47K_0402_5%

@

+3VS

+5VALW

+3VL_EC

44 60

0.2

5

ON/OFF switch Novo button

100K_0402_5%

NOVO#

NOVO#44

ON/OFF

D D

1 2

J5

SHORT PADS

1 2

J6

SHORT PADS

+3VALW

+3VL

R83

R82

100K_0402_5%

@

1 2

R85 0_0402_5%@

1 2

R119 0_0402_5%@

@

R261

D15

BAT54CW_SOT323-3

+3VALW

R111 100K_0402_5%

@

1 2

ON/OFFON/O FFBTN#

1 2

0_0402_5%

2

3

@

4

NOVO_BTN#

1

+3VL

R114 100K_0402_5%

1 2

ON/OFF 44

8/16 Del Power Button wei

ON/OFFBTN#

1

D25

1

2

EMC@

2

AZ5123-01F.R7GR_DFN1006P2X2

3

2

SW2

NTC325-EKJ-A160T_3P

123

1

NOVO_BTN#

4

5

1

D24

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2

8/31 Update the P/N SN100008W00 wei

LID switch

1

C1105

0.01U_0201_10V6K

1 2

R264

+3VL

0_0402_5%

2

+VCC_LID

OUTPUT

2

VCC

AH9247-W-7_SC59-3

U14

1

GND

1

C1104 100P_0201_25V8J

2

LID_SW#

3

LID_SW# 44

K/B Connector

PWR_CAPS_LED

CAPS_LED#

NUM_LED#_R

C C

EMC_NS@

1 2

C133 100P_0201_25V8J

EMC@

1 2

C117 100P_0201_25V8J

1 2

C118 100P_0201_25V8J

EMC_15@

CAPS_LED# NUM_LED#_R

1

D22

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2

1

2

D23 AZ5123-01F.R7GR_DFN1006P2X2

EMC_15@

Finger Print Connector

+3VS

R3120

USB20_N4_CONN

B B

A A

USB20_P4_CONN

312

BATT_LOW_LED#44

BATT_CHG_LED#44

PWR_LED#44

BATT_LOW_LED#

1

2

BATT_CHG_LED#

1

2

PWR_LED#

PWR_LED Change to M/B (310->320) 08/17

5

AZC199-02S.R7G_SOT23-3

KSI[0..7]

KSO[0..17]

For EMC

FP_PWR

1 2

0_0402_5%

FP@

1

2

0.1u_0201_10V6K

C2061

DT2

EMC_NS@

9/7 Add for ESD wei

1 2

LED2

L-C192JFCT-LCFC_SUPER_AMBER

D18 AZ5123-01F.R7GR_DFN1006P2X2

EMC_NS@

1 2

LED3

L-C192WDT-LCFC_WHITE

D19 AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

1 2

LED4

L-C192WDT-LCFC

KSI[0..7] 44

KSO[0..17] 44

8/23 PWR LED function under check

PWR_LED#

1

D46

1

AZ5123-01F.R7GR_DFN1006P2X2

EMC@

2

USB20_N4

1 2

USB20_N49

USB20_P49

FP@

R3122 0_0402_5%FP@

USB20_P4 USB20_P4_CONN

1 2

R3121 0_0402_5%FP@

1 2

R143 470_0402_5%

1 2

R144 1.5K_0402_5%

1 2

R4672 1.5K_0402_5%

PWR_LED#

NUM_LED#44

CAPS_LED#44

R285 0_0402_5%

R279 0_0402_5%15@

KSO17

R281 0_0402_5%15@

KSO16

R280 0_0402_5%15@

R275 0_0402_5% R84

+3VALW

1 2 1 2 1 2 1 2

1 2 1 2

200_0402_1%

To be confirm Pin define

JFP1

USB20_N4_CONN

1

2

3

4

5

6

7

8

9

GND1

10

GND2

HIGHS_FC5AF081-2931H

8/23 Update FG Conn. P/N SP01001YV0 0 wei

+3VALW

+5VALW

4

PWR_LED#

1

D16

1

AZ5725-01F.R7GR_DFN1006P2X2

EMC_NS@

2

ON/OFFBTN#

NUM_LED#_R KSO17_R KSO16_R

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

CAPS_LED#_RCAPS_LED# PWR_CAPS_LED

JKB1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

CVILU_CF32321D0RONH

ME@

3

KB Ba cklight Connector

33

GND1

34

GND2

EC_BKL_EN44

EC_BKL_EN

0.1u_0201_10V6K

R265

10K_0402_5%

KBL@

2

G

1

C1109

KBL@

2

TP/B Co nnector

1 2

R141

0_0402_5%

TP_I2C_SCL0 TP_I2C_SDA0

312

DT1

EMC_NS@

For EMC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRA NSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R& D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT C ONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS S HEET NOR THE INFORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRI TTEN CONSENT OF LC FUTURE CENTER.

AZC199-02S.R7G_SOT23-3

2015/08/20

LC Future Center Secret Data

+5VALW

12

13

D

S

TP_PWR+3VS

1

2

C114

0.1u_0201_10V6K

Deciphered Date

2

+5VS

R266

1 2

100K_0402_5%

KBL@

Q32 2N7002KW_SOT323-3

KBL@

EC_LID_OUT#44 PCH_TP_INT#8

TP_I2C_SDA08 TP_I2C_SCL08

S

G

C1106

KBL@

+VCC_KB_LED

1

2

0.1u_0201_10V6K

+VCC_KB_LED

1

2

C1110

@

C1107

0.1u_0201_10V6K

KBL@

Q31 LP2301ALT1G_SOT23-3

KBL@

D

13

2

1

C1108

0.01U_0201_10V6K

KBL@

2

10U_0603_6.3V6M

8/31 Update KBL Conn. P/N SP01160824 1 wei

1 2

R4675 0_0402_5%

1 2

R4676 0_0402_5%

TP_PWR

1

2

EMC_NS@

C115

C116

100P_0201_25V8J

11/16 SIT change to 6Pin I2C interface T/P wei

Title

2016/08/20

Title

KBD/PWR/IO/LED/TP Conn.

Size

Document N umber Rev

Custom

Date: Sheet o f

1

2

EC_LID_OUT#_R TP_INT#

TP_I2C_SDA0 TP_I2C_SCL0

Tuesday, April 25, 2017

To be confirm Pin define

JKBL1

ME@

1

2

3

GND2

4

GND1

4

CVILU_CF50041D0RN-10-NH

JTP1

1

2

3

4

5

6

ELCO_04-6809-606-110-846-+

EG521

1

6 5

ME@

7

GND1

8

GND2

45 60

0.2

A

Load Switch +5VALW To +5VS +3VALW To +3VS

1 2

R64 0_0402_5%

1 1

SUSP# 5VSON

1 2

R27 0_0402_5%

1

C180

1U_0402_6.3V6K

2

1

C179 1U_0402_6.3V6K

2

3VSON

+3VALW

+5VALW

1

C178 1U_0402_6.3V6K

2

@

1

C177 1U_0402_6.3V6K

2

B

+5VALW

C

+3VS, C173 --> 2.74ms +5VS, C176 --> 2.03ms

VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm

5VSON

3VSON

Change the main source to SA000067600 (GMT) 7/16

U13

7

IN2_2

6

5

4

3

2 1

OUT2_1

IN2_1

OUT2_2

EN2

VBIAS

EN1

OUT1_1

IN1_2

OUT1_2

IN1_1

G5016KD1U_TDFN14_2X3

GPAD

GND

15

8 9

10

C176 1000P_0201_50V7-K

CT2

11

12

C173 2200P_0402_25V7-K

CT1

13 14

+5VS_LS

1 2

+3VS_LS

Need Short

J12

@

112

JUMP_43X79

J11

@

112

JUMP_43X79

Need Short

2

+5VS

1

C174

0.1u_0201_10V6K

@

2

D

+3VS

1

C175

0.1u_0201_10V6K

@

2

+1.8VALW +1.0VALW

1

EMC_NS@

C20910.1u_0201_10V6K

2

+5VALW

1

C20920.1u_0201_10V6K

2

EMC_NS@

1

C2078

0.1u_0201_10V6K

EMC_NS@

2

EMC_NS@

1

C20850.1u_0201_10V6K

C20860.1u_0201_10V6K

2

EMC_NS@

1

C20870.1u_0201_10V6K

2

1

C2080

0.1u_0201_10V6K

EMC_NS@

2

E

EMC_NS@

+3VALW

1

C20890.1u_0201_10V6K

2

EMC_NS@

1

C2079

0.1u_0201_10V6K

EMC_NS@

2

1

C20900.1u_0201_10V6K

2

EMC_NS@

1

C20880.1u_0201_10V6K

2

EMC_NS@

EMC

@

Q10

2

G

Q30

2

G

12

13

D

S

+5VALW

12

R155 100K_0402_5%

@

13

D

S

2N7002KW_SOT323-3@

R157 100K_0402_5%

@

2N7002KW_SOT323-3

C1103

22U_0603_6.3V6-M

1

@

2

PCH_PWR_EN#_R

2 2

PCH_PWR_EN#_R P CH_PWR_EN#

3 3

PCH_PWR_EN44,55

1 2

R158 100K_0402_5%@

SUSP34

SUSP#44

PCH_PWR_EN

100K_0402_5%

R156

100K_0402_5%

SUSP

R162

+5VLP +5VALW

12

+3VALW +3VALW _PCH

12

R87 100K_0402_5%

@

Need short

J7

@

112

JUMP_43X79

LP2301ALT1G_SOT23-3

D

S

Q29

13

G

2

1

C131

0.1u_0201_10V6K

@

2

+0.6VS

12

R159 47_0603_5%

@

13

D

S

2N7002KW_SOT323-3

+1.8VALW +1.8VS

2

C201

0.1u_0201_10V6K

1

@

1

C130

0.01U_0201_10V6K

@

2

1 2

SUSP

R201 0_0402_5%

Id=3.2A

2

12

R202

470K_0402_5%@

Q35

D

S

13

LP2301ALT1G_SOT23-3

G

2

C202

0.1u_0201_10V6K

1

2

0.6A

C203

0.1u_0201_10V6K

1

2

C204

0.1u_0201_10V6K

C205

0.1u_0201_10V6K

1

2

8/29 Add +1.8VS Circuit for Audio wei

For DisCharge

+2.5V_DDR

12

R278 200_0402_5%

@

13

Q11

2

SUSP

G

@

D

Q33

2

G

S

2N7002KW_SOT323-3

@

SUSP

4 4

A

B

08/29: Need double check enable signal and the resistance

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

C

2015/08/20

LC Future Center Secret Data

Deciphered Date

D

2016/08/20

Title

DC V TO VS INTERFACE

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

EG521

46 60

E

46 60

0.2

5

D D

AC MO DE

A1

VIN

V

PU301

V

BATT

MODE

C C

BATT

B1

4

B2

A2

+3VLP

V

B5

V

11

A3

A4

+3VALW

B4

B3

VR_REDY

V

VR_ON

V

EC

V

10

A2

PU904

V

B+

EC_ON

ON/OFF

NOVO

PU901 +CPU_COR E

3

PCH_PWR_EN#

1

DPWROK_EC

4

PCH_RSMRST#

5

PBTN_OUT #

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

V

PM_SLP_SUS#

12

PCH_PWROK

13

SYS_PWRO K

SYSON

2

Q25,+3V_PCH

V

3

+3V_PCH

1

V

PM_DRAM_PWR GD

V V

6

PCH

H_CPUPWRGD

CPU_PLTRST#

14

V

15

16

CPU

V

NVDD_PWR_EN

(DIS)

7

+1.35V PU501

V

Q31

V

+5VS

Vb

DGPU_PWR_EN

(DIS)

Va

+VGA_CORE

V

PU801

DGPU_PWROK

+1.5VS_VGA

V

PU601

VV

B B

SUSP#,SUSP

9

Q32

V

+3VS

PU602

V

+1.5VS

PU502

V

+1.05VSP_VGA

V

PU702

+3VS_VGA

V

Q27

VGA

V

V V

+0.675V

SUS_VCCP

A A

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

8

3

PU701

V

+1.05VS

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Title

Power sequence block

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

EG521

47 60

1

47 60

0.2

5

D D

C C

4

3

2

1

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

LC Future Center Secret Data

Deciphered Date

2016/08/20

1

Title

Virtual symbol

Size

Document Number Re v

E

EG521

Tuesday, April 25, 2017

Date: Sheet of

48 60

0.2

5

4

3

2

1

CPU Thermal Holex3 GPU Thermal Holex2

H1 HOLEA

D D

1

pad_c6p0d4p0

DC-IN x2

C C

H17 HOLEA

1

pad_o2p6x2p9d2p6x2p9n

SH1

ME@

B B

1

SPRING_FINGER_6.2X1.64

SH4

ME@

1

SPRING_FINGER_6.2X1.64

H2 HOLEA

1

pad_c6p0d4p0

H3 HOLEA

1

pad_c6p0d4p0

H10 HOLEA

1

pad_ct5p5d2p5

H18 HOLEA

1

PAD_CT7P0D3P0

SH2

ME@

1

SPRING_FINGER_6.2X1.64

SH5

ME@

1

SPRING_FINGER_6.2X1.64

H4 HOLEA

pad_c7p0d3p3

H19 HOLEA

1

PAD_CT7P0D3P0

SH3

1

SPRING_FINGER_6.2X1.64

SH6

1

SPRING_FINGER_6.2X1.64

1

WLAN Standoff

pad_ct7p0b6p0d3p3

ME@

H5 HOLEA

pad_c7p0d3p3

H11 HOLEA

1

pad_c3p3d3p3n

H20 HOLEA

1

USB3.0 Shielding

Close to RJ45 Close to Audio jack

H12 HOLEA

1

pad_ct7p0d3p0

PAD_C2P6D2P6N

H6 HOLEA

1

CHASSIS1_GND pad_ct7p0b8p0d3p0

pad_ct7p0d3p0

H22 HOLEA

1

SH12

1

SPRING_FINGER_6.2X1.64

SH13

1

SPRING_FINGER_6.2X1.64

ME@

H13 HOLEA

1

pad_ct5p0d2p5

H7 HOLEA

1

pad_ct7p0b8p0d3p0

H15 HOLEA

1

SH7

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH9

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

H16 HOLEA

1

pad_cb5p5d2p5

ME@

DDR4 Shielding

SHIELDING_SUL-35A2M_9P2X3P3_1P

PCB Fedical Mark PAD

FD1

FD2

1

SH8

ME@

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH10

ME@

1

FD4

FD3

1

SH14

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

SH11

1

SHIELDING_SUL-35A2M_9P2X3P3_1P

FD5

1

ME@

FD6

1

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2015/08/20

3

LC Future Center Secret Data

Deciphered Date

2016/08/20

2

Titl e

Hole

Size

Document Number R ev

B

Tuesday, April 25, 2017

Date : Sheet o f

Tuesday, April 25, 2017

EG521

1

49 60

0.2

5

D D

4

3

Silergy

LV5028AGQV VQFN40_5X5

LDO

EN

For DDR4

+1.0 5VGS /1.5A

2

NAPGOODEN_VGA

1

PCH_PW R_EN EN

PGOODEN

PGOOD

+5VLP/ 100mA

+5VA LW/ 6A

NA

+3VLP/ 100mA

+3VALW/ 5A

ALW_PW RGD

+1.2 V/7A

+0.6 VS/ 2A

VDDQ_P GOOD

PCH_PW R_EN

EC_VPP _PWREN

V20B+

Adaptor 45W/65W

C C

TI

EC_ON

SYSON

CPU_DR AMPG_C NTL

BQ24780SRUYR

Silergy

SY8288CRAC QFN20_3X3

Converter FOR SYSTEM

Silergy

SY8286BRAC QFN20_3X3

Converter FOR SYSTEM

Silergy

LV5028AGQV

S5

VQFN40_5X5

Switch Mode

S3

FOR DDR4

Silergy

LV5028AGQV

VQFN40_5X5

Converter

FOR PCH

Silergy

LV5028AGQV VQFN40_5X5

Converter

EN

For GPU

Silergy

LV5028AGQV VQFN40_5X5

LDO

EN

For DDR4

PGOOD

+1.0 VALW/6 A

NA

+1.8 VALW/1 A

NA

+2.5 V/1A

NA

Battery Charger

Switch Mode

PGOOD

+1.3 5V/ 8A

NA

+VGA _COR E/31A

DGPU_P WROK

MPS

NB685GQ-Z QFN16_3X3

Switch Mode

SMBus

B B

FBVDDQ _PWR_E N

Battery

polymer

PXS_PW REN

EN

FOR VRAM

Richtek

RT8812AGQW WQFN20_3X3

VID

Switch Mode

EN

FOR GPU VDDC

2S1P

PGOOD

CPU Core/23A

VCCG T/2 5A

VCCS A/7A

CPU_VR _READY

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

LC Future Center Secret D ata

Deciphered Date

2

2016/08/20

Title

PWR-Power Diagram

Size Document Number Re v

Custom

Date: Sheet o f

CG411

Tuesday, April 25, 2017

1

50 60

0.1

Onsemi

NCP81216MNR2G QFN60_7X7

Switch Mode

VID

EC_VR_ ON

A A

5

FOR CPU Core

EN

4

5

4

3

2

1

EMC@

12

PR102

1.5K_0402_1%

12

PR103

45.3K_0402_1%

12

HCB2012KF-121T50_0805

PL101

1 2

EMC_NS@

HCB2012KF-121T50_0805

PL102

1 2

RTC_VCC

JRTC1

1 2 3 4

HIGHS_WS33020-S0351-HF

ME@

1 2 GND1 GND2

JDCIN1

1 2 3 4 5 6 7

@

PC105 1U_0402_6.3V6K

ADPIN

1 GND1 GND2 GND3 GND4

D D

C C

GND5 GND6

HIGHS_PJSS0026-8B01H

ME@

VCCRTC

1 2

PF101

APDIN_F

7A_24VDC_F1206HI7000V024TM

BAT54CW_SOT323-3

21

2

1

3

PD101

PC101

1 2

EMC@

1000P_0201_50V7-K

PC102

EMC@

470P_0201_50V7-K

12

+3VL

PR101

1K_0603_5%

VIN

12

PC103

PC104

1 2

EMC@

1000P_0201_50V7-K

EMC@

470P_0201_50V7-K

RTC_VCC 20MIL +3VL 20MIL VCCRTC 20MIL

B B

No charge RTC with 35mm cable

RTC Battery for GCM BOM (2nd source and quoted price )

A A

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Title

PWR-DCIN / RTC charger

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

CG411

51 60

1

51 60

0.1

5

4

3

2

1

D D

C C

JBATT1

1 2

9

3

GND1

10

4

GND2

5 6 7 8

ME@

SUYIN_125022HB008M202ZL

VBAT

1 2

EC_SMCA

3

EC_SMDA

4 5 6 7 8

1

2

3

1

BATT_TEMP_IN

PD202

AZ5215-01F_DFN1006P2E2

EMC_NS@

2

PD201

AZC199-02S.R7G_SOT23-3

EMC_NS@

PR209

1 2

100K_0402_1%

PR213

1 2

10K_0402_5%

1 2

PR202 100 _0402_1%

1 2

PR201 100_0402_1%

+3VALW

BATT_TEMP 44,53

EC_SMB_CK1 44,53 EC_SMB_DA1 44,53

1 2

EMC@

HCB2012KF-121T50_0805

PL201

1 2

PL202

HCB2012KF-121T50_0805

EMC@

PC201

1000P_0201_50V7-K

EMC@

BATT+

12

PC202

0.01U_0201_25V6-K

EMC@

2S1P polymer battery voltage level: +6V ~

8.4 V

B B

A A

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENT ER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Title

PWR-BATTERY CONN/OTP

Size Document Number Re v

Custom

Date: Sheet of

Tuesday, April 25, 2017

CG411

52 60

1

52 60

0.1

5

4

3

2

1

AON6414AL_DFN8-5

VIN

D D

PC301

470P_0201_50V7-K

PR313 PR315 :432K and 64.9k change to 43k and 7.15k. vin detect volatege level:16.8V

C C

B B

PC309:0.1u change to 0.01u decrease ACDET deassert time

PQ311

5

4

12

PR302

4.7_0603_5%

12

PR310

4.02K_0603_1%

ADP_I44

N1

1 2 3

12

PR311

4.02K_0603_1%

7.15K_0402_1%

1 2

PR315

1 2

0.01U_0402_25V7K

BQ24780_VDD

ACIN44

EC_SMB_DA144,52

EC_SMB_CK144,52

1 2

PC325

PC324

100P_0201_25V8J

AON7408L_DFN8-5

1 2 3

PC302

0.022U_0402_25V7K

PC309

Psys44,59

4

IDCHG

PQ312

N2

5

PC303

1 2

10U_0603_25V6-M

VIN

12

PR313

PR324100K_0402_1% @

1 2

PC341

PR339 20K_0402_1%@

12

@

100P_0201_25V8J

1 2

316K_0402_1%

1U_0603_25V6K

VR_HOT#44,59

PR331

43K_0402_1%

1 2

PR325 0_0402_5%

1 2

PR320 0_0402_5%

1 2

PR322 0_0402_5%

1 2

PR323 0_0402_5%

PR340

20K_0402_1%

1 2

+3VALW

PJ301

JUMP_43X118

112

EMC_NS@

PC307

1U_0603_25V6K

VIN

PC315

12

ACDET

12

EC_SMB_DA1_R

EC_SMB_CK1_R

ADP_I_R

2

1 2

@

2

1

10_1206_5%

1 2

780_VCC

ACIN_R

PC328

0.1U_0201_25V6-K

PC304

1 2

12

BATT+

3

PD301

BAT54CW_SOT323-3

PR314

ILIM

PR330 0_0402_5%

1 2

12

PR333 100K_0402_1%

28

11

12

10

13

14

21

PR301

0.01_1206_1%

1

2

EMC_NS@

10U_0603_25V6-M

0.1U_0201_25V6-K

PC305

1 2

ACP

2

ACP

VCC

6

ACDET

BQ24780SRUYR_QFN24_4X4

3

CMSRC

4

ACDRV

5

ACOK

SDA

PU301

SCL

7

IADP

8

IDCHG

9

PMON

PROCHOT#

CMPIN

CMPOUT

ILIM

TB_STAT#ILIM_R

1 2

14.7K_0402_1% PR332

4

3

PC306

0.1U_0201_25V6-K

1 2

12

PC329

100P_0402_50V8J

EMC@

12

PC330

470P_0402_50V7K

EMC@

12

PC331

680P_0402_50V7K

EMC@

12

PC332

EMC@

4700P_0402_50V7-K

12

PC333

EMC@

6800P_0402_25V7-K

12

PC334

EMC@

0.01U_0201_25V6-K

BQ24780_BATDRV

499K_0402_1%

12

PC342

PC343

PC344

4700P_0402_50V7-K

EMC@

4

PC308

0.01U_0201_25V6-K

1 2

5

321

100P_0402_50V8J

0.1U_0201_25V6-K

EMC@

12

PR303

V20B+

PQ314 AON6324_DFN8-5

V20B+

ACN

BQ24780_VDD

1

ACN

24

REGN

25

BTST

26

HIDRV

27

PHASE

23

LODRV

22

GND

29

PAD

18

BATDRV

17

BATSRC

20

SRP

19

SRN

TB_STAT#

BATPRES#

16

15

1 2

PR316

BST_CHG

1 2

2.2_0603_5%

DH_CHG

LX_CHG

DL_CHG

BQ24780_BATDRV

SRP_R

PR328

SRN_R

PR329

BATT_TEMP 44,52

PC3162.2U_0603_10V6-K

0.047U_0603_16V7K

PC318

12

PR338 10_0603_5%

12

10_0603_5%

12

10_0603_5%

5

4

321

5

4

321

1 2

PQ316

AON7408L_DFN8-5

PQ317

AON7408L_DFN8-5

PC327

0.1U_0201_25V6-K

PC310

1 2

EMC@

2200P_0201_25V7-K

1 2

4.7UH_PCMB053T-4R7MS_4A_20%

12

PR321

2.2_0805_5%

EMC_@

12

PC321

1000P_0402_50V7K

EMC_@

PC313

PL302

1 2

PC314

10U_0805_25V6K

PR317

0.01_1206_1%

1

CHG

1 2

SRP

SRN

4

3

2

1 2

PC322

0.1U_0201_25V6-K

PC323

1 2

0.1U_0201_25V6-K

BATT+

PC319

1 2

PC320

10U_0805_25V6K

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

PWR-CHARGER

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

CG411

1

53 60

0.1

5

4

3

2

1

+3VALW

PR407

@

V20B+

@

PJ401

2

112

JUMP_43X79

D D

PR414

0_0402_5%

EC_ON +3/5VALW_EN

EC_ON39,44,55

1 2

12

PC401

EMC@

0.01U_0201_25V6-K

+3/5VALW_EN

12

PC402

PC452

10U_0805_25V6K

PR415

0_0402_5%

12

+3V_VIN

12

@

PC408

0.1U_0201_25V6-K

PU401

+3V_VIN

5

IN1

4

IN2

3

IN3

2

IN4

7

GND1

8

GND2

18

GND3

21

GND4

12

EN1

11

EN2

10

NC1

15

NC2

PR401

+3VLP +3VL

NC316LDO

1M_0402_5%

@

PJ404

2

JUMP_43X39

9

PG

1

BS

6

LX1

19

LX2

20

LX3

14

OUT

13

SY8286BRAC_QFN20_3X3

FF

17

112

+3V_PWRGD +3VBS

+3VLX

100 mA

1 2

PC403

0.1U_0603_25V7-M

+3VALW_P

+3VALW_FB

+3VLP

12

PC409

1 2

12

4.7U_0603_6.3V6K

100K_0402_5%

2.2UH_PCMB053T-2R2MS_5.5A_20% PL401

1 2

PR403

2.2_0805_5%

EMC_NS@

PC410

1000P_0402_50V7K

EMC_NS@

1 2

PC411

1000P_0201_25V7K

12

PC434

22U_0603_6.3V6-M

1 2

1K_0402_1%

PR405

+3VALW

@

PJ402

+3VALW_P

12

PC432

PC431

PC435

22U_0603_6.3V6-M

2

JUMP_43X79

5A

112

Vout=3.3V ± 5 % Vset=3.37 V± 1.5% OCP= 12A OVP=(1.15 ~1. 25) *Vout UVP=(0.55 ~0. 65) *Vout Fsw=600 Khz

C C

V20B+

+3/5VALW_EN

B B

@

PJ405

2

JUMP_43X79

PU402

+5V_VIN

SY8288CRAC_QFN20_3X3

5

IN1

4

IN2

3

IN3

2

IN4

7

GND1

8

GND2

18

GND3

21

GND4

12

EN1

11

EN2

10

NC1 NC216VCC

112

12

PC412

EMC@

12

@

12

PC414

PC413

10U_0805_25V6K

0.01U_0201_25V6-K

12

PC421

PR412

1M_0402_5%

0.1U_0201_25V6-K

ALW_PWRGD

9

PG

1

+5VBS

BS

6

LX1

19

LX2

20

LX3

14

OUT

13

FF

15

LDO

17

+5VVCC

PC415

1 2

0.1U_0603_25V7-M

12

PC416

1U_0603_25V6M

+5VLX

1 2

PR410

0_0402_5%

12

+3VALW

+5VLP

100 mA

PC422

4.7U_0603_6.3V6K

+5VALW_P+5VALW_OUT

PR406 100K_0402_5%

1 2

@

ALW_PWRGD 55

PL402

1 2

2.2UH_PCMB063T-2R2MS_8A_20%

12

PR411

2.2_0805_5%

EMC_NS@

12

PC423

1000P_0402_50V7K

EMC_NS@

PC424

1 2

+5VFB

1000P_0201_25V7K

12

PR413

1 2

1K_0402_1%

+5VALW_P

12

PC417

22U_0603_6.3V6-M

12

PC420

PC418

PC419

22U_0603_6.3V6-M

PJ406

2

JUMP_43X79

@

+5VALW

8A

112

Vout=5V± 3% Vset=5.1V ± 1 .5% OCP= 12A OVP=(1.15 ~1. 25) *Vout UVP=(0.55 ~0. 65) *Vout Fsw=600 Khz

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

PWR_3VALW/5VALW

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

CG411

1

54 60

0.1

5

D D

C C

B B

SYSON44

CPU_DRAMPG_CNTL5

PCH_PWR_EN44,46

EC_VPP_PWREN44

1 2

PR501 0_0402_5%

1 2

PR503 0_0402_5%

1 2

PR507

0_0402_5%

1 2

PR506 0_0402_5%

1 2

PR508

0_0402_5%

+1.8VALW_L_EN

12

PR525

1M_0402_5%

+2.5V_DDR_EN

@

0.1u_0201_10V6K

+1.8VALW_B_EN

+1.0VALW_EN

PC504

1 2

VDDQ_EN

VTT_EN

PC506

@

0.1u_0201_10V6K

1 2

@

0.1u_0201_10V6K

4

+5VALW

+5VLP

PR505

VDDQ_P

1 2

10_0402_5%

PC505

PC503

1 2

PC508

1 2

@

0.1u_0201_10V6K

+5VALW

PJ500

@

2

112

JUMP_43X39

PJ508

@

2

112

JUMP_43X39

1 2

PC517 10U_0603_10V6K

PJ504

PR515

1 2

33K_0402_1%

PJ502

2

JUMP_43X39

2

JUMP_43X39

@

112

+0.6VS

12

22U_0603_6.3V6-M

@

112

PR520

1 2

10_0603_5%

1 2

+2.5V_DDR_EN

+1.8VALW_L_EN

+1.0VALW_EN

+1.8VALW_B_EN

+1.0VALW_B_VIN

12

PC510

0.1u_0201_10V6K

PC509

+1.8VALW_B_VIN

12

PC534 22U_0603_6.3V6-M

+1.2V_P

12

22U_0603_6.3V6-M

PC521

1 2

10U_0603_10V6K

PR502

@

1 2

10_0603_5%

PC502

0.1u_0201_10V6K

VDDQ_EN

VTT_EN

EMC_NS@

PC519

2.2U_0603_6.3V6K

29

11

16

31

36

19

38

39

40

30

PMIC_VCC

PC500

1 2

VSYS_PMIC

28

EN_LDO1

1

EN_LDO2

EN_V1P0A

EN_V1P8A

EN_VDDQ

EN_VTT

7

VIN_V1P0A1

8

VIN_V1P0A2

VIN_V1P8A

VIN_VTT

VTT

VSNS_VTT

CS_VDDQ

5

VIN_LDO1

4

VIN_LDO2

PU500 LV5028RPC_QFN40_5X5

VSYS

3

27

VCC

PMIC_EN

9

41

PMIC_EN

PG_V1P0A

PG_V1P8A

PG_VDDQ

LX_V1P0A1 LX_V1P0A2 LX_V1P0A3 LX_V1P0A4

VO_V1P0A

LX_V1P8A1 LX_V1P8A2

VO_V1P8A

UGATE_VDDQ

BS_VDDQ

LX_VDDQ

LGATE_VDDQ

VSNS_VDDQ

1 2

PR521 0_0402_5%

1 2

PR522 0_0402_5%@

LDO1

LDO2

SDA

SCL

OT

PMIC_SMB_DAT1

25

PMIC_SMB_CLK1

26

PMIC_ALERT#

24

+1.0VALW_PG

22

+1.05VGS_B_PG

21

23

LX_1P0

12 13 14 15

+1.0VALW_FB

10

17

LX_1P8 + 1.8VALW_FB

18

+1.8VALW_FB

20

UG_VDDQ

33

BST_VDDQ

32

LX_VDDQ

34

LG_VDDQ

35

37

+2.5V_P+2.5V_DDR_VIN

6

1 2

PC520 22U_0603_6.3V6-M

3

2

GND

FB_LDO2

EC_ON 39,44,54

ALW_PWRGD 54

1 2

PR510 0_0402_5%

1 2

PR511 0_0402_5%

PR512 0_0402_5%@

1

VDDQ_PGOOD

0.47UH_CMMB062D-R47MS_15A_20%

+1.2V_P

1

PL500

1 2

PL502

1 2

1UH_PH041H-1R0MS_3.8A_20%

PR526

1 2

0_0603_5%

0.1U_0603_25V7-M

UG_VDDQ

LX_VDDQ

LG_VDDQ

PC518

2

12

PTC501PAD @

PTC502PAD @

12

PJ503

JUMP_43X39

4

112

@

5

321

5

321

12

PC511

+2.5V_DDR+3VALW

AON7506_DFN

2

EC_SMB_DA3 44

EC_SMB_CK3 44

H_PROCHOT# 4,44

12

PC513

PC512

22U_0603_6.3V6-M

12

PC535

PC536

@

22U_0603_6.3V6-M

PQ500

AON7408L_DFN8-5

0.47UH_CMMB062D-R47MS_15A_20%

2.2_0805_5% PR518

PQ501

EMC_NS@

1 2

12

1000P_0402_50V7K

EMC_NS@

22U_0603_6.3V6-M

PC533

12

PC514

@

22U_0603_6.3V6-M

1 2

PL501

1

+3VALW

12

PR513

R_0402

100K_0402_5%

VDDQ_PGOOD 44

PJ501

12

0.1U_0201_25V6-K

@

12

2

112

JUMP_43X79

PJ509

2

112

JUMP_43X79

LX_1P0

12

PR535

4.7_0603_5%

EMC_NS@

12

PC544

1200P_0402_50V7-K

EMC_NS@

12

PC525

10U_0805_25V6K

12

PC527

PC528

22U_0603_6.3V6-M

@

+1.0VALW

@

+1.8VALW

LX_1P8

12

PR536

4.7_0603_5%

EMC_NS@

12

PC539

1200P_0402_50V7-K

EMC_NS@

PJ506

VDDQ_P

PC526

10U_0805_25V6K

+1.2V_P

12

PC530

PC529

PC531

22U_0603_6.3V6-M

2

JUMP_43X39

2

@

112

@

PJ507

112

JUMP_43X79

V20B+

+1.2V

+1.0VALW_FB

12

PC515

PC516

@

22U_0603_6.3V6-M

12

PC524

EMC@

@

12

PC538

22U_0603_6.3V6-M

A A

Title

Security Classification LC Future Center Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2015/08/20

2

Deciphered Date

2016/08/20

Title

PWR PMIC-DDR4/1.0ALW/1.8ALW

Size

Document Number Re v

A2

Date: Sheet of

CG411

Tuesday, April 25, 2017

1

55 60

0.1

5

D D

C C

B B

4

3

2

1

A A

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUT URE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

PWR

Size Document Number Re v

Custom

Date : Shee t o f

Tuesday, April 25, 2017

CG411

56 60

1

56 60

0.1

5

4

3

2

1

D D

FBVDDQ_PWR_EN22,24

C C

V20B+

1 2

PD1401

@

RB751V-40_SOD323-2

OPT@

PR1412

1 2

0_0402_5%

1A

@

PC1416

0.1u_0201_10V6K

2

JUMP_43X79

1 2

PJ1401

+3VALW

@

112

12

PC1401

EMC_NS@

0.1U_0402_25V6

+3VALW

1 2

PR1405

OPT@

4.7_0402_5%

OPT@

PC1402

10U_0805_25V6K

OPT@

PR1408

1 2

10K_0402_1%

100K_0402_1%

PC1411

OPT@

1.35V_GND

12

PR1403

1U_0402_6.3V6K

12

OPT@

PC1403

10U_0805_25V6K

+1.35V_VIN

+1.35V_S3

+1.35V_S5

12

@

+1.35V_3V3

1.35V_GND

+1.35V_Mode

PR1410 0_0402_5%

OPT@

1 2

PU1401

1

VIN

16

EN1

15

EN2

12

PG

3

3V3

4

AGND

2

PGND

14

MODE

OPT@

1.35V_GND

PJ1404

1 2

JUMPER

@

PJ1402

@

112

+1.35VGS

8A

10

BST

9

SW

13

FB

6

VDDQ

5

VTT

NB685GQ-Z_QFN16_3X3

8

VTTS

7

VTTREF

11

OTW#

+1.35V_LX

+1.35V_FB

+1.35V_P

MPS_VTTREF

12

OPT@

PC1415

1U_0402_6.3V6K

1.35V_GND

1 2

OPT@

PR1401 0_0603_5%

+1.35V_BST +1.35V_BST_R

PC1404

0.1U_0603_25V7-M

1 2

12

PR1402

2.2_0805_5%

EMC_OPTNS@

+1.35V_SN

12

PC1412

1000P_0402_50V7K

EMC_OPTNS@

OPT@

0.47UH_PCMB053T-R47MS_13A_20% PL1401

1 2

12

PR1404 1M_0402_5%

@

+1.35V_COMP

12

PR1406 499_0402_1%

@

12

PC1405 220P_0402_50V7K

@

12

1.35V_GND

12

PC1406

OPT@

PR1407

41.2K_0402_1%

OPT@

PR1411

32.4K_0402_1%

OPT@

+1.35V_P

12

PC1407

22U_0603_6.3V6-M

OPT@

Vout=1.35 V± 5% Vset=1.36 V± 2% OCP= 13A Vref=0. 6V OVP=(1.25 ~1. 35) *Vref UVP=(0.7~ 0.8 )*Vre f Fsw=700Kh z(R mod e=0) Fsw=500Kh z(Rm ode =1 50K )

12

PC1408

PC1409

@

22U_0603_6.3V6-M

OPT@

2

1

OPT@

+

PC1417 330U_B2_2.5VM_R9M

2

PC1410

22U_0603_6.3V6-M

OPT_NS@

JUMP_43X79

B B

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

PWR-+1.05VGS/+1.35V_VRAM

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

CG411

1

57 60

0.1

5

Component ValuePWM-VID Specification

@

1 2

PR808

OPT@

1 2

PD801

1 2

0_0402_5%

R1 (K Ω ) R2 (K Ω ) R3 (K Ω )

R4( KΩ )

R5( KΩ )

C(n F)

+1.8VG_AON

@

PR809

OPT@

12

PR812

20.5K_0402_1%

OPT@

PR816

6.19K_0402_1%

1 2

12

PC826 4700P_0402_25V7-K

OPT@

12

Conf ig Vmin (V) Vmax (V)

Vboo t(V ) Vstep(m V) N(le vel ) Fpwm(KH z)

D D

Tdmin(n S)

T(u S)

PSI_VGA20

+3VS

DGPU_PWROK8,22,24

PC825

NVVDD_PWM_VID20

NVVDD_EN22

16.5K_0402_1%

OPT@

12

309_0402_1%

OPT@

PR813

PR818

C C

4700P_0402_25V7-K

B B

@

0.3

1.3

0.8

6.2 5 160 675

9.2 6 <10 0

OPT@

PR802 0_0402_5%

1 2

PR804

1 2

10K_0402_1%

1.1K_0402_1%

LRB751V-40T1G_SOD323-2

12

PC818

1U_0402_25V6-K

OPT@

12

PR815

1 2

4.32K_0402_1%

12

RT@

1 2

UPI@

PR827

0_0402_5%

1 2

PR826 0_0402_5%

OPT@

NVVDD_FBRTN

+5VALW

PR806

5.1K_0402_1%

OPT@

PR807

1 2

5.1K_0402_1%

PR94 40 PR94 34 PR94 36 PR94 37 PR94 31 PC12 77

12

OPT@

PR801 2_0603_5%

NVVDD_PVCC

12

PC804 1U_0402_6.3V6K

OPT@

NVVDD_PSI_R

@

NVVDD_EN_R

12

PC815 .1U_0402_10V6-K

OPT@

NVVDD_VID_R

12

PC816

0.1U_0402_10V7K

NVVDD_VREF

NVVDD_REFIN

NVVDD_VIDBUF

PR820

71.5K_0402_1%

1 2

OPT@

NVVDD_FS

PR819 115K_0402_1%

OPT@

1 2

18

21

4

13

3

5

@

8

7

6

9

4

6.1 9

20. 5

4.3 2

16. 5

0.3 09

4.7

PU801

PVCC

GND

PSI

PGOOD

EN

VID

VREF

REFIN

REFADJ

TON

UP1666QQKF_WQFN20_3X3

OPT@

PSI Level Power Mode

Connected to PVCC

Hig h

Intermed iat e

Low

2

UGATE1

1

BOOT1

20

PHASE1

19

LGATE1

14

UGATE2

15

BOOT2

16

PHASE2

17

LGATE2

10

RGND

11

VSNS

12

OCSET/SS

51K_0402_1%

NVVDD_HG1

NVVDD_BS1

NVVDD_PH1

NVVDD_LG1

NVVDD_HG2

NVVDD_BS2

NVVDD_PH2

NVVDD_LG2

NVVDD_FBRTN

NVVDD_FB

NVVDD_COMP

PR821

OPT@

Phase Configuration PSH PS0 PS1 PS2

2.2_0603_5%

1 2

2.2_0603_5%

1 2

12

1 2

2Phase Auto CCM/DCM 2Phase FCCM 2Phase Auto CCM 1Phase Auto CCM/DCM

PC805

PR805

0.22U_0603_25V7K

1 2

0.22U_0603_25V7K

PC834 1000P_0402_25V7-K

PR831 0_0402_5%

OPT@

PC817

1 2

OPT@

PR810

OPT@

12

PC835 33P_0402_50V8J

@

3

@

PR830

0_0402_5%

1 2

2

+VGA_CORE_VIN

12

PC802

PC803

10U_0805_25V6K

OPT@

+VGA_CORE_VIN

12

PC831

10U_0805_25V6K

OPT@

PR814

100_0402_1%

1 2

OPT@

PR817

0_0402_5%

1 2

OPT@

PR824

0_0402_5%

1 2

OPT@

PR825

100_0402_1%

1 2

OPT@

12

1

+

2

OPT@

NVVDD_VSS_SENSE 21

NVVDD_VCC_SENSE 21

+VGA_CORE

12

PC801

0.1U_0201_25V6-K

EMC_OPT@

PQ801

2

435

2

435

AON6982_DFN8-7

OPT@

NVVDD_PH1

7

PQ802 AON6982_DFN8-7

OPT@

NVVDD_PH2

7

12

PR803

2.2_0805_5%

EMC_OPTNS@

12

PC814

1000P_0402_50V7K

EMC_OPTNS@

12

PR811

2.2_0805_5%

EMC_OPTNS@

12

PC824

1000P_0402_50V7K

EMC_OPTNS@

OPT@

0.22UH_PCME064T-R22MS0R985_28A_20% PL801

1 2

PC833

1 2

PL802

0.22UH_PCME064T-R22MS0R985_28A_20%

OPT@

1

6

1

6

VR Remote Sense - Tie to GPU sense points

12

PR828

10K_0402_1%

1 2

@

OPT@

PR829

0_0402_5%

1 2

PC836

1000P_0402_50V7K

1 2

@

PC827

@

1000P_0402_25V7-K

@

PJ801

2

112

JUMP_43X79

1

12

+

PC806

PC807

2

330U_D2_2V_Y

OPT@

1

12

+

PC819

@

2

PC820

330U_D2_2V_Y

OPT@

Vboot=0 .8V Ripple=± 20mV TDC=30A Iccmax=60A OCP≈ 7 2A Vref =2V FUVP:Vfb =0. 2V SUVP:Vco mp= 3V OVP:Vfb =2V Fsw=400 KHz

PC808

22U_0603_6.3V6-M

@

12

22U_0603_6.3V6-M

OPT@

12

V20B+

12

PC809

22U_0603_6.3V6-M

OPT@

PC821

22U_0603_6.3V6-M

1

PC810

12

OPT@

22U_0603_6.3V6-M

PC822

12

OPT@

22U_0603_6.3V6-M

OPT@

12

PC811

22U_0603_6.3V6-M

OPT@

12

PC823

22U_0603_6.3V6-M

+VGA_CORE

12

PC812

PC813

22U_0603_6.3V6-M

@

+VGA_CORE

A A

Titl e

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

5

4

MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CE NTER.

3

2015/08/20

LC Future Center Secret Data

Deciphered Date

2

2016/08/20

Titl e

PWR-VGA_CORE

Size

Document Number Rev

C

Date: Sheet of

Tuesday, April 25, 2017

CG411

1

58 60

0.1

5

SVID Specification

Vmin( V) Vmax( V)

Vstep (mV)

RFsw

28.7 K

D D

RVboo t

35.7 K

C C

B B

A A

Core/ GT

0V

Confi g

0

1.52 5

SA

550K550K

GTCore

0V

5

SA

1.05 V

EC_VR_ON44

VCCGT_VCC_SEN12

1000P_0402_50V7K

VCCGT_VSS_SEN12

VCORE_VCC_SEN12

VCORE_VSS_SEN12

VCCSA_VCC_SEN13

1000P_0402_50V7K

VCCSA_VSS_SEN13

12

PC907

1000P_0402_50V7K

PR937

49.9_0402_1%

1 2

PR940 1K_0402_1%

12

PC926

+VCCST_CPU

@

12

PR905

1K_0402_1%

1 2

PR919 3.3K_0402_1%

1 2

3.3K_0402_1% PR907

PR923

2.7K_0402_1%

1 2

PC911 15P_0402_50V8J

PC912 1000P_0402_50V7K

PR924 34K_0402_1%

12

PC914

PC922

470P_0402_50V7K

IA_FB_1

1 2

PR944 1.5K_0402_1%

PR945

1 2

1.5K_0402_1%

PR950

1.5K_0402_1%

1 2

PC930 15P_0402_50V8J

4

PR911

1 2

0_0402_5%

Psys44,53

GT_VSP_1

1 2

PC906

1000P_0402_50V7K

1 2

PR920 1K_0402_1%

1 2

PC908 330P_0402_50V7K

PC910

1500P_0402_50V6-K

1 2

PC913 470P_0402_50V7K

1 2

PR927 64.9K_0402_1%

1 2

PR930 1K_0402_1%

1 2

PC917 3300P_0402_50V7-K

1 2

PC918 470P_0402_50V7K

1 2

PR933 24.3K_0402_1%

PR938

4.75K_0402_1%

1 2

PC924 22P_0402_50V8-J

SA_VSP_1

PR948 499_0402_1%

SA_COMP_1 SA_COMP

PR953 15.8K_0402_1%

PC932 1000P_0402_50V7K

PR954 47K_0402_1%

PC934 470P_0402_50V7K

1 2

PC925

1000P_0402_50V7K

1 2

PC928 220P_0402_50V7K

PC929

1 2

0.015U_0402_25V7-K

1 2

4

VR_SVID_ALRT#_1

VR_SVID_CLK_1

VR_SVID_DAT_1

PC923

2200P_0402_50V7K

1 2

VR_EN

GT_VSP

GT_VSN

GT_COMPGT_COMP_1

GT_ILIM

GT_IOUT

IA_VSN

IA_IOUT

IA_DIFFOUT

IA_COMPIA_COMP_1

SA_VSP

SA_VSN

SA_ILIM

SA_Iout

IA_FB

V20B+ +5VS

12

VR_VRMP

12

37

EN

33

ALERT#

34

SCLK

32

SDIO

46

PSYS

24

VSP_1A

25

VSN_1A

26

COMP_1A

27

ILIM_1A

30

IOUT_1A

47

VSP_2PH

48

VSN_2PH

1

IOUT_2PH

2

DIFFOUT_2PH

3

FB_2PH

4

COMP_2PH

45

VSP_1B

44

VSN_1B

43

COMP_1B

42

ILIM_1B

39

IOUT_1B

14

12

PR955

28.7K_0402_1%

PR901

1K_0402_1%

12

PC901

0.01U_0402_25V7K

VRMP

PU901

NCP81218MNTXG_QFN48_6X6

ROSC_SAUS15ROSC_COREGT

ICCMAX_2PH18ICCMAX_1A

19

12

PR957

PR956

PR958

102K_0402_1%

100K_0402_1%

19.6K_0402_1%

3

12

PR902

2.2_0603_5%

12

PC902

VR_VCC

2.2U_0603_10V7K

13

VCC

38

VR_RDY

31

VR_HOT#

35

DRVON

22

PWM_1A

GT_CSP

29

CSP_1A

28

CSN_1A

23

TSENSE_1PH

16

PWM1_2PH

17

PWM2_2PH

IA_CSP1

10

CSP1_2PH

IA_CSP2

9

CSP2_2PH

IA_CSREF

8

CSREF_2PH

IA_CSSUM

7

CSSUM_2PH

IA_CSCOMP IA_CSCOMP_1

6

CSCOMP_2PH

TSENSE_2PH

ADDR_VBOOT21ICCMAX_1B

20

12

PR959

PR960

35.7K_0402_1%

ILIM_2PH

TAB

49

3

PWM_1B

CSP_1B

CSN_1B

5

11

36

40

41

IA_ILIM

IA_TSENSE

+VCCST_CPU

@

12

PR903

1K_0402_1%

54.9_0402_1%

need change to 3900P

12

PC904

3300P_0402_50V7-K

GT_TSENSE

12

PC915

0.1U_0402_10V7K

12

PC919

0.1U_0402_10V7K

1 2

PR943

19.6K_0402_1%

1 2

PR946

0_0402_5%

12

PC927 .1U_0402_10V6-K

SA_CSP

12

PC931

8200P_0402_25V7-K

12

PR904

1 2

PC905

0.022U_0402_25V7K

PR918

22K_0402_1%

12

PC935 2200P_0402_50V7K

1 2

PR921

0_0402_5%

12

PC909 .1U_0402_10V6-K

12

PC916

0.1U_0402_10V7K

1 2

PC920 680P_0402_50V7K

1 2

PC921 150P_0402_50V8-J

PR939

1 2

75K_0402_1%

1 2

PH903

220K_0402_5%_TSM0B224J4702RE

1 2

PR947 8.25K_0402_1%

1 2

PH904 100K_0402_1%_TSM0B104F4251RZ

Place close to MOSFET

PR951 7.5K_0402_1%

PC936 2200P_0402_50V7K

PR952 22K_0402_1%

2015/08/20

PC933

2700P_0402_50V7-K

12

Security Classification LC Future Center Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

CPU_VR_READY 44

VR_HOT# 44,53

1 2

PR917 7.5K_0402_1%

PH901

GT_CSP_1

1 2

100K_0402_1%_TSM0B104F4251RZ

PR961

1 2

10_0402_1%

1 2

PR922 8.25K_0402_1%

1 2

PH902 100K_0402_1%_TSM0B104F4251RZ

Place close to MOSFET

1 2

PR928 1.78K_0402_1%

1 2

PR929 1.78K_0402_1%

1 2

PR932 10_0402_1%

1 2

PR934 10_0402_1%

1 2

PR941

154K_0402_1%

2

PR962

1 2

10_0402_1%

1 2

SA_CSP_1

100K_0402_1%_TSM0B104F4251RZ

Deciphered Date

VR_SVID_DAT_1

VR_SVID_ALRT#_1

VR_SVID_CLK_1

PWM_1A

PWM1_2PH

PWM2_2PH

PR936

86.6K_0402_1%

PR942

86.6K_0402_1%

1 2

PH905

2016/08/20

+VCCST_CPU

12

PC903

1U_0402_6.3V6K

PR912

10_0402_1%

12

PR915

0_0402_5%

12

PR906

49.9_0402_1%

12

DRON 60

PWM_1A 60

GT_PH 60

+VCC_GT 12,60

PWM1_2PH 60

PWM2_2PH 60

IA_PH1 59,60

IA_PH2 59,60

+CPU_CORE 12,59,60

IA_PH1 59,60

IA_PH2 59,60

PWM_1B

1

12

@

PR908

PWM_1B 60

SA_PH 60

+VCCSA 13,60

Title

Size

A2

Date: Sheet of

PR910

PR909

45.3_0402_1%

PWR-CPU_CORE

Document Number Re v

100_0402_1%

75_0402_1%

CG411

Tuesday, April 25, 2017

1

VR_SVID_DAT 12

VR_SVID_ALRT# 12

VR_SVID_CLK 12

59 60

0.1

5

4

3

2

1

12

PC1014

22U_0603_6.3V6-M

@

+CPU_CORE

12

PC1054

22U_0603_6.3V6-M

+VCC_GT

12

PC1015

22U_0603_6.3V6-M

1

+

2

V20B+

12

V20B+

1

+

PC1422 22U_25V_M

2

@

+VCC_GT

330U_2.0V_M PC1084

12

PC1043

PC1042

22U_0603_6.3V6-M

12

PC1058

PC1057

22U_0603_6.3V6-M

12

PC1008

PC1006

PC1007

22U_0603_6.3V6-M

@

12

PC1017

22U_0603_6.3V6-M

12

PC1044

22U_0603_6.3V6-M

12

PC1059

22U_0603_6.3V6-M

12

PC1045

PC1046

22U_0603_6.3V6-M

12

PC1061

PC1060

22U_0603_6.3V6-M

12

PC1019

PC1018

22U_0603_6.3V6-M

12

PC1047

PC1048

22U_0603_6.3V6-M

12

PC1062

PC1063

22U_0603_6.3V6-M

@

12

PC1010

PC1009

22U_0603_6.3V6-M

PC1020

22U_0603_6.3V6-M

PC1049

22U_0603_6.3V6-M

PC1064

22U_0603_6.3V6-M

@

PC1011

PC1012

22U_0603_6.3V6-M

@

12

PC1022

PC1021

22U_0603_6.3V6-M

12

PC1051

PC1050

22U_0603_6.3V6-M

12

PC1065

PC1066

22U_0603_6.3V6-M

@

PC1013

22U_0603_6.3V6-M

@

22U_0603_6.3V6-M

12

PC1053

PC1052

22U_0603_6.3V6-M

12

PC1067

22U_0603_6.3V6-M

+5VS

PR1002

2.2_0603_5%

1 2

PWM_1A59

12

D D

DRON59,60

PC1016

1U_0402_10V6K

GT_VCC

PU1001

BST

4

VCC

DRVH

2

PWM

SW

3

EN

DRVL

9

FLAG

GND

NCP81253MNTBG_DFN8_2X2

1 2

2.2_0603_5%

GT_BST

1

8

GT_PH

7

GT_LG

5

6

+5VS

PR1008

2.2_0603_5%

1 2

PWM2_2PH59

12

DRON59,60

PC1034

C C

1U_0402_10V6K

IA_VCC2

PU1002 NCP81151MNTBG_DFN8_2X2

4

VCC

2

PWM

3

EN

9

FLAG

+5VS

PR1014

2.2_0603_5%

1 2

12

PWM1_2PH59

DRON59,60

PC1055

1U_0402_10V6K

B B

IA_VCC1

PU1003 NCP81151MNTBG_DFN8_2X2

4

BST

VCC

2

PWM

DRVH

3

EN

SW

9

FLAG

DRVL

GND

1

8

7

5

6

PR1001

DRVH

DRVL

BST

SW

GND

PC1001

1 2

0.22U_0603_16V7K

IA_BST2

1

8

7

5

6

1 2

2.2_0603_5%

IA_BST1

IA_HG1

IA_PH1

IA_LG1

GT_HG

1 2

PR1007

2.2_0603_5%

IA_HG2

IA_PH2

IA_LG2

PR1013

1

6

PC1030

1 2

0.22U_0603_16V7K

PC1038

1 2

0.22U_0603_16V7K

PQ1001

2

AON6982_DFN8-7

435

4

1

+

PC1036

2

330U_D2_2V_Y

220U_D2_2VM_R6M

PC1035

1

+

PC1005 68U_25V_M

2

1

+

220U_D2_2VM_R6M

PC1027

2 3

12

@

10U_0603_25V6-M

12

PC1003

PC1004

@

10U_0805_25V6K

12

PC1418

+CPU_CORE 12,59,60

IA_PH2 59

12

10U_0805_25V6K

@

PC1419

10U_0603_25V6-M

12

PC1420

10U_0603_25V6-M

+CPU_CORE 12,59,60

IA_PH1 59

12

PC1421

PC1425

10U_0603_25V6-M

@

+VCC_GT 12, 59

GT_PH 59

1

+

2

12

PC1426

10U_0603_25V6-M

+CPU_CORE

330U_2.0V_M PC1056

+CPU_CORE

1

+

2 3

1 2

PL1001

12

PC1033

@

10U_0805_25V6K

PC1040

@

10U_0805_25V6K

1 2

PL1003

12

EMC@

PC1002

0.1U_0201_25V6-K

12

PC1041

@

10U_0805_25V6K

12

PC1424

PC1423

10U_0603_25V6-M

GT_PH

7

5

321

5

321

5

4

321

5

4

321

PQ1003 AON6380_DFN8-5

PQ1004

12

AON6324_DFN8-5

12

PQ1005 AON6380_DFN8-5

PQ1006 AON6324_DFN8-5

12

PR1004

2.2_0805_5%

EMC_NS@

12

PC1029

1200P_0402_50V7-K

EMC_NS@

PR1010

2.2_0805_5%

EMC_NS@

PC1037

1200P_0402_50V7-K

EMC_NS@

12

1200P_0402_50V7-K

0.15UH_PCME063T-R15MS0R907_37A_20%

12

PC1032

EMC@

PC1031

@

10U_0805_25V6K

0.1U_0201_25V6-K

0.15UH_PCME063T-R15MS0R907_37A_20%

1 2

PL1002

12

EMC@

PC1039

0.1U_0201_25V6-K

0.15UH_PCME063T-R15MS0R907_37A_20%

PR1016

2.2_0805_5%

EMC_NS@

PC1068

EMC_NS@

@

2

PJ1003

2

JUMP_43X79

Deciphered Date

112

V20B+

+VCCSA

12

PC1077

22U_0603_6.3V6-M

2016/08/20

12

PC1079

PC1078

22U_0603_6.3V6-M

12

PC1080

PC1081

PC1082

22U_0603_6.3V6-M

Title

PWR-CPU_CORE

Size

Document Number Re v

A2

Date: Sheet of

CG411

Tuesday, April 25, 2017

1

60 60

0.1

12

PC1076

22U_0603_6.3V6-M

+VCCSA 13,59

SA_PH 59

2015/08/20

SA_VIN

+5VS

PR1020

2.2_0603_5%

1 2

PWM_1B59

12

DRON59,60

PC1073

A A

5

1U_0402_10V6K

SA_VCC

4

2

3

9

NCP81253MNTBG_DFN8_2X2

4

PU1004

VCC

PWM

EN

FLAG

DRVH

DRVL

BST

SW

GND

1 2

2.2_0603_5%

SA_BST

1

SA_HG

8

SA_PH

7

SA_LG

5

6

PR1019

PC1069

1 2

0.22U_0603_16V7K

5

PQ1007

4

AON7408L_DFN8-5

321

PQ1008

3

12

PR1022

2.2_0805_5%

EMC_NS@

12

PC1083

1200P_0402_50V7-K

EMC_NS@

5

AON7506_DFN

4

321

EMC@

12

PC1071

10U_0805_25V6K

PL1004

1 2

12

PC1072

10U_0805_25V6K

12

PC1070

0.1U_0201_25V6-K

0.47UH_PCMB053T-R47MS_13A_20%

Security Classification LC Future Center Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PRO PRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.