Lenovo GS44D,GS54D Schematic

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

A

1 1

B

C

D

E

2 2

LCFC NM-C711

GS44D/GS54D MB Schematics Document

ICL U42 with DDR4 + Nvidia N16V-GM

2019-06

REV:0.1

3 3

4 4

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

E

1 60

1 60

1 60

0.1

0.1

0.1

Запросы

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Для каждого устройства в одном месте.

на

поиск

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- FAQ, user manual

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- Technical documentation (schematic, service manual)

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- and other reference information
For each device in one place.

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Join !!!

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A

LCFC confidential

B

C

D

E

NV N16x/N17x

1 1

Package: FCBGA595

VRAM: 256*32

PCI-Express

4x Gen3

GDDR5*2: 2GB

HDMI Conn.

eDP Conn

HDMI (DDI 1)

eDP x2

Memory Bus

1.2V DDR4

x1

USB3.0 x1

x1

DDR4 SO-DIMM+MDx4

Page 17/18

USB3.0 Conn

Intel MCP

SATA HDD

2 2

SATA x1

Ice Lake-U42 15W

USB2.0

NGFF PCI-Express

SSD

4x Gen3

BGA1526
50mm*25mm

I2C

Page 3~16

Page 43

PCIe x1

USB2.0 x1

HD Audio

USB2.0

x1

x1

NGFF

WLAN&BT

SPK Conn.

Page 30

Realtek

3 3

HP&Mic
Combo Conn.

Page 30

RTS5199

SPI

x1
x1

Touch Pad

SPI ROM (16MB)

W25Q128JVSIQ

Page 45

Page 07

USB3.0 Conn

USB2.0 Conn

EC

LPC

Page 44

GPIO

HALL Sensor

SD Conn.

IO Board

ITE IT8227E-LQFP128

Int.KBD

Page 45

4 4

A

B

Thermal Sensor

F75303M

Page 39

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

E

2 60

2 60

2 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

S3

2 2

Battery only

S5 S4
AC Only

S5 S4
Battery only

S5 S4
AC & Battery
don't exist

SMBUS Control Table

3 3

EC_SMB_DA1

EC_SMB_CK0
EC_SMB_DA0

EC_SMB_CK3
EC_SMB_DA3

PCH_SMB_CLK
PCH_SMB_DATA

( O --> Means ON , X --> Means OFF )

+3VALW
+5VALW

V9B+

+3VALW_PCH
+1.8VALW
VCC_AUX

O

O

O

O X

O

O

O

O

O

X X

X X

SOURCE

IT8227EEC_SMB_CK1

+3VL_EC

IT8227E

IT8227E

+3VAWL

+3VALW_PCH

+3VS

PCH

BATT

V

X

X

ChargerVDGPU

X

X

V

+3VG_AON

X

X

+1.2V
+2.5V_DDR
+VCCST

+VCCSTG

O

O

O

+5VS

+3VS

+1.8VS

+CPU_CORE

+0.6VS

O

X

X

X

X

PCH

X

X

V

X

PMIC

SODIMM

X

X

X

V

+3VS

X

IT8227E

Memory
Down

V

+3VL_EC

+3VS

X

V

X X

V VX X X X X X X

X

X X

+3VALW_PCH

Thermal
Sensor

X

V

X

WLAN
WiMAX

X

X

X

X

HSIO PORT

USB3.0

USB2.0

PCIE

STATE

Full ON

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Function

1

USB3.0 Conn

2

USB3.0 Conn

3

NC

4

NC

5

6

1

USB3.0 Conn

2

USB3.0 Conn

3

NC

4

NC

5

Camere

6

Touch Screen

7

Finger Print

8

Card Reader

9

USB2.0 conn

10

Bluetooth

5~8

DGPU

X4

9

WLAN

10

NC

SATA HDD

11

12

NC

13~16

PCIE/SATA SSD

X4

SIGNAL

SLP_S3#SLP_S4#SLP_S5#+VALW +V +VS Clock

ON

ON

ON

ON

ON ON ON

ON

OFF

OFF

OFF

OFF

OFFLOW LOW LOW

OFF

OFF

OFF

HIGH HIGH HIGH

LOW

HIGH

HIGH

LOWLOW

LOW

BTO ItemBOM Structure

@
14@
15@

CD@

EMC@
EMC_15@
EMC_NS@

ME@

UMA@
OPT@
OPTN16@
OPTN17@

TS@
TP@

Un-stuff

For 14" part

For 15" part

For cost down

For EMC part

For EMC 15" part

For EMC un-stuff part

For ME part

For UMA part

For NV GPU part

For NV N16S-GTR GPU part

For NV N17S-G1 GPU part

For touch screen part

For TOuch Pad Part

EC SMBus1 address

Device

Smart Battery

4 4

Charger

need to update
0001 0010 b

EC SMBus2 address

Device

Thermal Sensor(NCT7718W)
DGPU

1001_100xb
need to update

EC SMBus3 address

Device AddressAddress

PMIC

need to update

A

B

PCH SM Bus address

Device AddressAddress

DDR4 SODIMM

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEETNOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEETNOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEETNOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTENCONSENT OF LC FUTURE CENTER.

C

need to update

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

E

3 60

3 60

3 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

4

3

2

1

UC1A

Y5

DDIA_TXN_0

Y3

DDIA_TXP_0

Y1

DDIA_TXN_1

Y2

DDIA_TXP_1

V2

DDIA_TXN_2

V1

DDIA_TXP_2

V3

DDIA_TXN_3

V5

DDIA_TXP_3

W4

DDIA_AUX_N

W3

DDIA_AUX_P

AE3

DDIB_TXN_0

AE5

DDIB_TXP_0

AE2

DDIB_TXN_1

AE1

DDIB_TXP_1

AC5

DDIB_TXN_2

AC3

DDIB_TXP_2

AC1

DDIB_TXN_3

AC2

DDIB_TXP_3

AD3

DDIB_AUX_N

AD4

DDIB_AUX_P

DP15

GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN

DJ17

GPP_E23/DDPA_CTRLDATA/BK4/SBK4

DL40

GPP_H16/DDPB_CTRLCLK

DP42

GPP_H17/DDPB_CTRLDATA

DL17

GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD

DK17

GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD

DN17

GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD

DP17

GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD

DK34

GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD

DL34

GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD

DN33

GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD

DL33

GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD

DW11

GPP_E14/DPPE_HPDA/DISP_MISCA

CV42

GPP_A18/DDSP_HPDB/DISP_MISCB

CV39

GPP_A19/DDSP_HPD1/DISP_MISC1

CY43

GPP_A20/DDSP_HPD2/DISP_MISC2

CR41

GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3

CT41

GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4

DV14

GPP_E17

DN21

EDP_VDDEN

DL19

EDP_BKLTEN

DU19

EDP_BKLTCTL

J3

RSVD_1

D2

DISP_UTILS

R2

DISP_RCOMP

ICELAKE-U_BGA1526

@

1 0f 19

TCP0_TX_N0
TCP0_TX_P0
TCP0_TX_N1

TCP0_TX_P1
TCP0_TXRX_N0
TCP0_TXRX_P0
TCP0_TXRX_N1
TCP0_TXRX_P1

TCP0_AUX_N
TCP0_AUX_P

TCP1_TX_N0

TCP1_TX_P0

TCP1_TX_N1

TCP1_TX_P1
TCP1_TXRX_N0
TCP1_TXRX_P0
TCP1_TXRX_N1
TCP1_TXRX_P1

TCP1_AUX_N
TCP1_AUX_P

TCP2_TX_N0

TCP2_TX_P0

TCP2_TX_N1

TCP2_TX_P1
TCP2_TXRX_N0
TCP2_TXRX_P0
TCP2_TXRX_N1
TCP2_TXRX_P1

TCP2_AUX_N
TCP2_AUX_P

TCP3_TX_N0

TCP3_TX_P0

TCP3_TX_N1

TCP3_TX_P1
TCP3_TXRX_N0
TCP3_TXRX_P0
TCP3_TXRX_N1
TCP3_TXRX_P1

TCP3_AUX_N
TCP3_AUX_P

TC_RCOMP_N
TC_RCOMP_P

GPP_A17/DISP_MISCC

GPP_A21
GPP_A22

BB5
BB6
AV6
AV5
BH2
BH1
BF1
BF2

AY5
AY6

AR5
AR6
AL5
AL3
BD2
BD1
BB1
BB2

AN3
AN5

BF6
BF5
BJ5
BJ6
BL1
BL2
BM2
BM1

BG6
BG5

BP6
BP5
BV5
BV6
BR1
BR2
BT2
BT1

BT6
BT5

AY1
AY2

CT38
CV43
CV41

TCRCOMP_N

RC401 1/20W_150_1%_0201

TCRCOMP_P

1 2

TP401 @
TP402 @

CPU_EDP_TX0­CPU_EDP_TX0+
CPU_EDP_TX1­CPU_EDP_TX1+

CPU_EDP_AUX#
CPU_EDP_AUX

CPU_HDMI_TXN2
CPU_HDMI_TXP2
CPU_HDMI_TXN1
CPU_HDMI_TXP1
CPU_HDMI_TXN0
CPU_HDMI_TXP0
CPU_HDMI_CLKN
CPU_HDMI_CLKP

PCH_HDMI_DDC_CLK
PCH_HDMI_DDC_DATA

GPP_E19

GPP_E21

GPP_D10

GPP_D12

CPU_EDP_HPD
CPU_HDMI_HPD

USB_OC1#
USB_OC2#

PCH_ENVDD
PCH_ENBKL
PCH_EDP_PWM

DSI_DE_TE_2

1

DISP_UTILS

1

EDP_COMP

12

1/20W_150_1%_0201

RC402

CPU_EDP_TX0-33
CPU_EDP_TX0+33
CPU_EDP_TX1-33
CPU_EDP_TX1+33

D D

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

C C

+3VS

RPC401

1 4
2 3

2.2K_0404_4P2R_5%

+3VALW_PCH

B B

PCH_HDMI_DDC_CLK
PCH_HDMI_DDC_DATA

12
12
12
12
12
12
12
12

An external pull-up resistor is required if the pin is
used as HDMI Display I2C, instead of TBT LSx
0 = DDPx I2C / TBT LSx pins at 1.8V
1 = DDPx I2C / TBT LSx pins at 3.3V

GPP_E19

RC4031/20W_4.7K_1%_0201 @
RC4041/20W_20K_5%_0201 @

GPP_E21

RC4051/20W_4.7K_5%_0201 @
RC4061/20W_20K_5%_0201 @

GPP_D10

RC4071/20W_4.7K_5%_0201 @
RC4081/20W_20K_5%_0201 @

GPP_D12

RC4091/20W_4.7K_5%_0201 @
RC4101/20W_20K_5%_0201 @

CPU_EDP_AUX#33
CPU_EDP_AUX33

CPU_HDMI_TXN234
CPU_HDMI_TXP234
CPU_HDMI_TXN134
CPU_HDMI_TXP134
CPU_HDMI_TXN034
CPU_HDMI_TXP034
CPU_HDMI_CLKN34
CPU_HDMI_CLKP34

PCH_HDMI_DDC_CLK34
PCH_HDMI_DDC_DATA34

CPU_EDP_HPD33
CPU_HDMI_HPD34

USB_OC1#41
USB_OC2#43

PCH_ENVDD33
PCH_ENBKL33,44
PCH_EDP_PWM33

+1.8VALW_PCH

1 2

RC411 10K_0201_5%

1 2

RC412 10K_0201_5%

1 2

RC413 100K_0201_5%

CC401

12

0.33U 10V K X5R 0402

@

RPC402

100K_0404_4P2R_5%

CC402

A A

12

0.33U 10V K X5R 0402

@

USB_OC1#
USB_OC2#

CPU_EDP_HPD

PCH_ENVDD

14

PCH_ENBKL

23

5

4

GPIO Group Power Supply

GPP_A 1.8V

GPP_B/C/D/E 3.3V

GPP_F 1.8V(only)

GPP_G/H 3.3V
GPP_R/S 1.8V

GPD 3.3V(only)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

1

4 60

4 60

4 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

4

3

2

1

DDRA_DQS#[0..7]18
DDRA_DQS[0..7]18
DDRB_DQS#[0..7]17

SO_DIMM

D D

C C

DDRA_DQ[0..63]18

1 2

RC501 1/20W_100_1%_0201

1 2

RC502 1/20W_100_1%_0201

1 2

RC503 1/20W_100_1%_0201

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

DDR_RCOMP_0
DDR_RCOMP_1
DDR_RCOMP_2

UC1B

CA48

DDRA_DQ0_0/DDR0_DQ0_0

CA47

DDRA_DQ0_1/DDR0_DQ0_1

CA49

DDRA_DQ0_2/DDR0_DQ0_2

BV49

DDRA_DQ0_3/DDR0_DQ0_3

CA45

DDRA_DQ0_4/DDR0_DQ0_4

BV47

DDRA_DQ0_5/DDR0_DQ0_5

BV45

DDRA_DQ0_6/DDR0_DQ0_6

BV48

DDRA_DQ0_7/DDR0_DQ0_7

CC42

DDRA_DQ1_0/DDR0_DQ1_0

CC39

DDRA_DQ1_1/DDR0_DQ1_1

CC43

DDRA_DQ1_2/DDR0_DQ1_2

CE38

DDRA_DQ1_3/DDR0_DQ1_3

CC38

DDRA_DQ1_4/DDR0_DQ1_4

CE39

DDRA_DQ1_5/DDR0_DQ1_5

CE42

DDRA_DQ1_6/DDR0_DQ1_6

CE43

DDRA_DQ1_7/DDR0_DQ1_7

BT48

DDRA_DQ2_0/DDR0_DQ2_0

BT47

DDRA_DQ2_1/DDR0_DQ2_1

BT49

DDRA_DQ2_2/DDR0_DQ2_2

BN49

DDRA_DQ2_3/DDR0_DQ2_3

BT45

DDRA_DQ2_4/DDR0_DQ2_4

BN47

DDRA_DQ2_5/DDR0_DQ2_5

BN45

DDRA_DQ2_6/DDR0_DQ2_6

BN48

DDRA_DQ2_7/DDR0_DQ2_7

BV42

DDRA_DQ3_0/DDR0_DQ3_0

BV39

DDRA_DQ3_1/DDR0_DQ3_1

BV43

DDRA_DQ3_2/DDR0_DQ3_2

BW38

DDRA_DQ3_3/DDR0_DQ3_3

BV38

DDRA_DQ3_4/DDR0_DQ3_4

BW39

DDRA_DQ3_5/DDR0_DQ3_5

BW42

DDRA_DQ3_6/DDR0_DQ3_6

BW43

DDRA_DQ3_7/DDR0_DQ3_7

AY48

DDRB_DQ0_0/DDR0_DQ4_0

AY47

DDRB_DQ0_1/DDR0_DQ4_1

AY49

DDRB_DQ0_2/DDR0_DQ4_2

AU45

DDRB_DQ0_3/DDR0_DQ4_3

AY45

DDRB_DQ0_4/DDR0_DQ4_4

AU47

DDRB_DQ0_5/DDR0_DQ4_5

AU48

DDRB_DQ0_6/DDR0_DQ4_6

AU49

DDRB_DQ0_7/DDR0_DQ4_7

AY42

DDRB_DQ1_0/DDR0_DQ5_0

AY38

DDRB_DQ1_1/DDR0_DQ5_1

AY43

DDRB_DQ1_2/DDR0_DQ5_2

BB39

DDRB_DQ1_3/DDR0_DQ5_3

AY39

DDRB_DQ1_4/DDR0_DQ5_4

BB38

DDRB_DQ1_5/DDR0_DQ5_5

BB42

DDRB_DQ1_6/DDR0_DQ5_6

BB43

DDRB_DQ1_7/DDR0_DQ5_7

AR48

DDRB_DQ2_0/DDR0_DQ6_0

AR47

DDRB_DQ2_1/DDR0_DQ6_1

AR49

DDRB_DQ2_2/DDR0_DQ6_2

AM45

DDRB_DQ2_3/DDR0_DQ6_3

AR45

DDRB_DQ2_4/DDR0_DQ6_4

AM47

DDRB_DQ2_5/DDR0_DQ6_5

AM48

DDRB_DQ2_6/DDR0_DQ6_6

AM49

DDRB_DQ2_7/DDR0_DQ6_7

AT42

DDRB_DQ3_0/DDR0_DQ7_0

AT39

DDRB_DQ3_1/DDR0_DQ7_1

AR43

DDRB_DQ3_2/DDR0_DQ7_2

AT38

DDRB_DQ3_3/DDR0_DQ7_3

AR38

DDRB_DQ3_4/DDR0_DQ7_4

AR39

DDRB_DQ3_5/DDR0_DQ7_5

AR42

DDRB_DQ3_6/DDR0_DQ7_6

AT43

DDRB_DQ3_7/DDR0_DQ7_7

D47

DDR_RCOMP_0

E46

DDR_RCOMP_1

C47

DDR_RCOMP_2

ICELAKE-U_BGA1526

@

DDRA_CLK_N/DDR0_CLK_N_0
DDRA_CLK_P/DDR0_CLK_P_0
DDRB_CLK_N/DDR0_CLK_N_1
DDRB_CLK_P/DDR0_CLK_P_1

DDRA_CKE0/DDR0_CKE0

DDRB_CKE1/DDR0_CKE1

DDRA_CS_0/DDR0_CS_N_0

DDRB_CS_1/DDR0_CS_N_1

DDRB_CA0/DDR0_MA13

DDRB_CA2/DDR0_MA14WE_N
DDRB_CA1/DDR0_MA15CAS_N
DDRB_CA3/DDR0_MA16RAS_N

DDRA_DQSN_0/DDR0_DQSN_0
DDRA_DQSP_0/DDR0_DQSP_0
DDRA_DQSN_1/DDR0_DQSN_1
DDRA_DQSP_1/DDR0_DQSP_1
DDRA_DQSN_2/DDR0_DQSN_2
DDRA_DQSP_2/DDR0_DQSP_2
DDRA_DQSN_3/DDR0_DQSN_3
DDRA_DQSP_3/DDR0_DQSP_3
DDRB_DQSN_0/DDR0_DQSN_4
DDRB_DQSP_0/DDR0_DQSP_4
DDRB_DQSN_1/DDR0_DQSN_5
DDRB_DQSP_1/DDR0_DQSP_5
DDRB_DQSN_2/DDR0_DQSN_6
DDRB_DQSP_2/DDR0_DQSP_6
DDRB_DQSN_3/DDR0_DQSN_7
DDRB_DQSP_3/DDR0_DQSP_7

2 of 19

DDRA_CKE1/NC
DDRB_CKE0/NC

DDRA_CS_1/NC
DDRB_CS_0/NC

DDRB_CA4/DDR0_BA0

NC/DDR0_BA1

DDRA_CA5/DDR0_BG0

NC/DDR0_BG1
NC/DDR0_MA0

NC/DDR0_MA1

DDRB_CA5/DDR0_MA2

NC/DDR0_MA3

NC/DDR0_MA4
DDRA_CA0/DDR0_MA5
DDRA_CA2/DDR0_MA6
DDRA_CA4/DDR0_MA7
DDRA_CA3/DDR0_MA8
DDRA_CA1/DDR0_MA9

NC/DDR0_MA10
NC/DDR0_MA11
NC/DDR0_MA12

NC/DDR0_ODT_0
NC/DDR0_ODT_1

NC/DDR0_PAR

NC/DDR0_ACT_N

NC/DDR0_ALERT_N

RSVD_73
DDR0_VREF_CA
DDR1_VREF_CA

DDR_VTT_CTL

DRAM_RESET_N

DDRA_CLK0#

BL48

DDRA_CLK0

BL47

DDRA_CLK1#

BF42

DDRA_CLK1

BF43

DDRA_CKE0

BG49
BJ47
BF38

DDRA_CKE1

BF41

DDRA_CS0#

BM38
BM42
BP42

DDRA_CS1#

BG42

DDRA_BS0#

BM43

DDRA_BS1#

BG39

DDRA_BG0

BB49

DDRA_BG1

BD47

DDRA_MA0

BB48

DDRA_MA1

BL49

DDRA_MA2

BG38

DDRA_MA3

BL45

DDRA_MA4

BJ46

DDRA_MA5

BG48

DDRA_MA6

BE45

DDRA_MA7

BG45

DDRA_MA8

BG47

DDRA_MA9

BE47

DDRA_MA10

BJ38

DDRA_MA11

BB47

DDRA_MA12

BE48

DDRA_MA13

BM39

DDRA_MA14_WE#

BG43

DDRA_MA15_CAS#

BJ42

DDRA_MA16_RAS#

BM41

DDRA_ODT0

BJ39

DDRA_ODT1

BB45

DDRA_DQS#0

BY47

DDRA_DQS0

BY46

DDRA_DQS#1

CC41

DDRA_DQS1 DDRB_DQS#1

CE41

DDRA_DQS#2

BR47

DDRA_DQS2

BR46

DDRA_DQS#3

BV41

DDRA_DQS3

BW41

DDRA_DQS#4

AV46

DDRA_DQS4

AV47

DDRA_DQS#5

AY41

DDRA_DQS5

BB41

DDRA_DQS#6

AN46

DDRA_DQS6

AN47

DDRA_DQS#7

AR41

DDRA_DQS7

AT41

DDRA_PAR

BF39

DDRA_ACT#

BE49

DDRA_ALERT#

BD46
M38

DDR_SA_VREFCA

C44

DDR_SB_VREFCA

B45

DDR_VTT_CNTL

M39

CPU_DRAMRST#_R

DK47

DDRA_CLK0# 18
DDRA_CLK0 18
DDRA_CLK1# 18
DDRA_CLK1 18

DDRA_CKE0 18

DDRA_CKE1 18
DDRA_CS0# 18

DDRA_CS1# 18
DDRA_BS0# 18

DDRA_BS1# 18
DDRA_BG0 18

DDRA_BG1 18
DDRA_MA0 18

DDRA_MA1 18
DDRA_MA2 18
DDRA_MA3 18
DDRA_MA4 18
DDRA_MA5 18
DDRA_MA6 18
DDRA_MA7 18
DDRA_MA8 18
DDRA_MA9 18
DDRA_MA10 18
DDRA_MA11 18
DDRA_MA12 18
DDRA_MA13 18
DDRA_MA14_WE# 18
DDRA_MA15_CAS# 18
DDRA_MA16_RAS# 18

DDRA_ODT0 18
DDRA_ODT1 18

DDRA_PAR 18
DDRA_ACT# 18
DDRA_ALERT# 18

DDR_SA_VREFCA 18
DDR_SB_VREFCA 17

DDRB_DQS[0..7]17

DDRB_DQ[0..63]17

DDRA_DQS#[0..7]
DDRA_DQS[0..7]
DDRB_DQS#[0..7]
DDRB_DQS[0..7]

DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

UC1C

AK48

DDRC_DQ0_0/DDR1_DQ0_0

AK45

DDRC_DQ0_1/DDR1_DQ0_1

AK49

DDRC_DQ0_2/DDR1_DQ0_2

AG47

DDRC_DQ0_3/DDR1_DQ0_3

AK47

DDRC_DQ0_4/DDR1_DQ0_4

AG45

DDRC_DQ0_5/DDR1_DQ0_5

AG48

DDRC_DQ0_6/DDR1_DQ0_6

AG49

DDRC_DQ0_7/DDR1_DQ0_7

AJ38

DDRC_DQ1_0/DDR1_DQ1_0

AL39

DDRC_DQ1_1/DDR1_DQ1_1

AJ39

DDRC_DQ1_2/DDR1_DQ1_2

AL43

DDRC_DQ1_3/DDR1_DQ1_3

AL38

DDRC_DQ1_4/DDR1_DQ1_4

AJ42

DDRC_DQ1_5/DDR1_DQ1_5

AL42

DDRC_DQ1_6/DDR1_DQ1_6

AJ43

DDRC_DQ1_7/DDR1_DQ1_7

AB49

DDRC_DQ2_0/DDR1_DQ2_0

AB48

DDRC_DQ2_1/DDR1_DQ2_1

AE49

DDRC_DQ2_2/DDR1_DQ2_2

AE47

DDRC_DQ2_3/DDR1_DQ2_3

AE48

DDRC_DQ2_4/DDR1_DQ2_4

AB47

DDRC_DQ2_5/DDR1_DQ2_5

AB45

DDRC_DQ2_6/DDR1_DQ2_6

AE45

DDRC_DQ2_7/DDR1_DQ2_7

AD38

DDRC_DQ3_0/DDR1_DQ3_0

AD39

DDRC_DQ3_1/DDR1_DQ3_1

AE39

DDRC_DQ3_2/DDR1_DQ3_2

AE43

DDRC_DQ3_3/DDR1_DQ3_3

AE38

DDRC_DQ3_4/DDR1_DQ3_4

AD43

DDRC_DQ3_5/DDR1_DQ3_5

AD42

DDRC_DQ3_6/DDR1_DQ3_6

AE42

DDRC_DQ3_7/DDR1_DQ3_7

J48

DDRD_DQ0_0/DDR1_DQ4_0

J45

DDRD_DQ0_1/DDR1_DQ4_1

J49

DDRD_DQ0_2/DDR1_DQ4_2

G47

DDRD_DQ0_3/DDR1_DQ4_3

J47

DDRD_DQ0_4/DDR1_DQ4_4

G45

DDRD_DQ0_5/DDR1_DQ4_5

G48

DDRD_DQ0_6/DDR1_DQ4_6

E48

DDRD_DQ0_7/DDR1_DQ4_7

J38

DDRD_DQ1_0/DDR1_DQ5_0

G39

DDRD_DQ1_1/DDR1_DQ5_1

G38

DDRD_DQ1_2/DDR1_DQ5_2

G42

DDRD_DQ1_3/DDR1_DQ5_3

J39

DDRD_DQ1_4/DDR1_DQ5_4

J42

DDRD_DQ1_5/DDR1_DQ5_5

G43

DDRD_DQ1_6/DDR1_DQ5_6

J43

DDRD_DQ1_7/DDR1_DQ5_7

B43

DDRD_DQ2_0/DDR1_DQ6_0

D43

DDRD_DQ2_1/DDR1_DQ6_1

A43

DDRD_DQ2_2/DDR1_DQ6_2

C40

DDRD_DQ2_3/DDR1_DQ6_3

C43

DDRD_DQ2_4/DDR1_DQ6_4

D40

DDRD_DQ2_5/DDR1_DQ6_5

B40

DDRD_DQ2_6/DDR1_DQ6_6

A40

DDRD_DQ2_7/DDR1_DQ6_7

B35

DDRD_DQ3_0/DDR1_DQ7_0

D35

DDRD_DQ3_1/DDR1_DQ7_1

A35

DDRD_DQ3_2/DDR1_DQ7_2

D38

DDRD_DQ3_3/DDR1_DQ7_3

C35

DDRD_DQ3_4/DDR1_DQ7_4

C38

DDRD_DQ3_5/DDR1_DQ7_5

B38

DDRD_DQ3_6/DDR1_DQ7_6

A38

DDRD_DQ3_7/DDR1_DQ7_7

ICELAKE-U_BGA1526

@

MD

DDRC_CLK_N/DDR1_CLK_N_0
DDRC_CLK_P/DDR1_CLK_P_0
DDRD_CLK_N/DDR1_CLK_N_1
DDRD_CLK_P/DDR1_CLK_P_1

DDRD_CA2/DDR1_MA14WE_N
DDRD_CA1/DDR1_MA15CAS_N
DDRD_CA3/DDR1_MA16RAS_N

DDRC_DQSN_0/DDR1_DQSN_0
DDRC_DQSP_0/DDR1_DQSP_0
DDRC_DQSN_1/DDR1_DQSN_1
DDRC_DQSP_1/DDR1_DQSP_1
DDRC_DQSN_2/DDR1_DQSN_2
DDRC_DQSP_2/DDR1_DQSP_2
DDRC_DQSN_3/DDR1_DQSN_3
DDRC_DQSP_3/DDR1_DQSP_3
DDRD_DQSN_0/DDR1_DQSN_4
DDRD_DQSP_0/DDR1_DQSP_4
DDRD_DQSN_1/DDR1_DQSN_5
DDRD_DQSP_1/DDR1_DQSP_5
DDRD_DQSN_2/DDR1_DQSN_6
DDRD_DQSP_2/DDR1_DQSP_6
DDRD_DQSN_3/DDR1_DQSN_7
DDRD_DQSP_3/DDR1_DQSP_7

3 of 19

DDRC_CKE0/DDR1_CKE0

DDRC_CKE1/NC
DDRD_CKE0/NC

DDRD_CKE1/DDR1_CKE1

DDRC_CS_0/DDR1_CS_N_0

DDRC_CS_1/NC
DDRD_CS_0/NC

DDRD_CS_1/DDR1_CS_N_1

DDRD_CA4/DDR1_BA0

NC/DDR1_BA1

DDRC_CA5/DDR1_BG0

NC/DDR1_BG1
NC/DDR1_MA0

NC/DDR1_MA1

DDRD_CA5/DDR1_MA2

NC/DDR1_MA3

NC/DDR1_MA4
DDRC_CA0/DDR1_MA5
DDRC_CA2/DDR1_MA6
DDRC_CA4/DDR1_MA7
DDRC_CA3/DDR1_MA8
DDRC_CA1/DDR1_MA9

NC/DDR1_MA10
NC/DDR1_MA11
NC/DDR1_MA12

DDRD_CA0/DDR1_MA13

NC/DDR1_ODT_0
NC/DDR1_ODT_1

NC/DDR1_PAR

NC/DDR1_ACT_N

NC/DDR1_ALERT_N

DDRB_CLK0#

DDRB_CLK0

Y48
Y47
M43
M42

U45
V46
M41
P43

V42
V39
Y39
T39

T38
T42

R45
N47

P42
Y49
U48
Y45
U47
R49
U49
M47
M45
R47
P39
N46
R48
Y41
V41
Y42
V47

V43
V38

AH46
AH47
AJ41
AL41
AC47
AC46
AE41
AD41
H47
H46
G41
J41
C42
D42
D36
C36

P38
M48
M49

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0

DDRB_CS0#

DDRB_BS0#
DDRB_BS1#

DDRB_BG0
DDRB_BG1

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_MA14_WE#
DDRB_MA15_CAS#
DDRB_MA16_RAS#

DDRB_ODT0

DDRB_DQS#0
DDRB_DQS0

DDRB_DQS1
DDRB_DQS#2
DDRB_DQS2
DDRB_DQS#3
DDRB_DQS3
DDRB_DQS#4
DDRB_DQS4
DDRB_DQS#5
DDRB_DQS5
DDRB_DQS#6
DDRB_DQS6
DDRB_DQS#7
DDRB_DQS7

DDRB_PAR
DDRB_ACT#
DDRB_ALERT#

1

CC502

330P_0402_50V8J

@

2

DDRB_CLK0# 17
DDRB_CLK0 17

DDRB_CKE0 17

DDRB_CS0# 17

DDRB_BS0# 17
DDRB_BS1# 17

DDRB_BG0 17
DDRB_BG1 17

DDRB_MA0 17
DDRB_MA1 17
DDRB_MA2 17
DDRB_MA3 17
DDRB_MA4 17
DDRB_MA5 17
DDRB_MA6 17
DDRB_MA7 17
DDRB_MA8 17
DDRB_MA9 17
DDRB_MA10 17
DDRB_MA11 17
DDRB_MA12 17
DDRB_MA13 17
DDRB_MA14_WE# 17
DDRB_MA15_CAS# 17
DDRB_MA16_RAS# 17

DDRB_ODT0 17

DDRB_PAR 17
DDRB_ACT# 17
DDRB_ALERT# 17

B B

+3VALW

12

RC504

100K_0402_5%

+1.2V

12

RC505
1/16W_470_1%_0402

CPU_DRAMRST#_R

A A

5

RC507

1 2

0_0402_5%

1

CC501

0.1U_6.3V_K_X5R_0201

@

2

CPU_DRAMRST# 17,18

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

+1.2V

RC506

1 2

1K_0402_5%

DDR_VTT_CNTL

2018/12/04

2018/12/04

2018/12/04

C

2

QC501

B

MMBT3904WH_SOT323-3

E

3 1

RC508

10K_0402_5%

@

1 2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

CPU_DRAMPG_CNTL 55

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

1

5 60

5 60

5 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

www.teknisi-indonesia.com

+VCCSTG_TERM

1 2

RC601 51_0402_5%

1 2

RC602 51_0402_5%@

1 2

RC603 51_0402_5%@

1 2

RC604 1K_0402_5%

1 2

RC605 51_0402_5%

D D

+3VALW_PCH

1 2

RC607 100K_0402_5%

1 2

RC609 4.7K_0402_5%@

PM_SLP_S0IX_R_N:
External pull-up is required.
This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.

+3VALW_PCH

1 2

RC614 1/20W_4.7K_5%_0201@

GPP_H2(PCIE_WAKE#_WLAN_R):
This signal has a 20K+/-30% internal pull-down.
0 = Master Attached Flash Sharing (MAFS) is enabled. (Default)
1 = Slave Attached Flash Sharing (SAFS) is enabled.
Notes:

1. The internal pull-down is disabled after RSMRST# de-asserts.

C C

B B

2. This signal is in the primary well

+VCCST_CPU

1 2

RC615 1K_0402_5%

1 2

RC616 1/20W_49.9_1%_0201@

+3VS

1 2

RC617 10K_0402_5%

HDA_SDO_R

GPP_R2(HDA_SDO_R):
This signal has a 20K ±30% internal pull-down.
0 = Enable security measures defined in the Flash Descriptor. (Default)
1 = Disable Flash Descriptor Security (override). This strap should only
be asserted high using external Pull-up in manufacturing/debug
environments ONLY.
Notes:

1. The internal pull-down is disabled after PCH_PWROK is high.

2. This signal is in the primary well.

PCH_JTAG_TDO_CPU
PCH_JTAG_TDI_CPU
PCH_JTAG_TMS_CPU
H_PROCHOT#

PCH_TCK_JTAGX_CPU

GPP_E6

H_THRMTRIP#
CATERR#

EC_SCI#

+1.8VALW_PCH

12

12

RC6250_0402_5%

12

CC60156P_50V_J_NPO_0402

12

CC6022P_25V_C_NPO_0201@

12

CC6032P_25V_C_NPO_0201@

12

CC60510P_0201_50V8F@

12

RC63175K_0402_1%

12

CC60433P_0201_50V8-JEMC_NS@

GPP_H2

RC622

4.7K_0402_5%

ME_FLASH 44

HDA_BCLK_R
HDA_SYNC_R
HDA_SDO_R
HDA_SDIN0

CNVI_RF_RESET#_PCH
CNVI_MODEM_CLKREQ_PCH

4

H_PECI44

H_PROCHOT#13,44,55

RC608 1/20W_49.9_1%_0201
RC610 1/20W_49.9_1%_0201
RC611 1/20W_49.9_1%_0201@
RC612 1/20W_49.9_1%_0201@

PCIE_WAKE#_WLAN_R40

1 2

HDA_BITCLK_AUDIO30
HDA_SYNC_AUDIO30
HDA_SDOUT_AUDIO30
HDA_SDIN030

CNVI_RF_RESET#40

CNVI_MODEM_CLKREQ40

RC618 1/20W_33_1%_0201

1 2

RC619 1/20W_33_1%_0201

1 2

RC620 1/20W_33_1%_0201

1 2

RC624 33_0402_5%

1 2

RC626 33_0402_5%

3

1 2

RC606 499_0402_1%

1 2
1 2
1 2
1 2

EC_SCI#44
EC_SMI45

1 2

RC613 0_0201_5%

HDA_BCLK_R
HDA_SYNC_R
HDA_SDO_R
HDA_SDIN0

CNVI_RF_RESET#_PCH
CNVI_MODEM_CLKREQ_PCH

CATERR#
H_PECI
H_PROCHOT#_R
H_THRMTRIP#

PROC_OPI_RCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
CPU_EOPIO_RCOMP

DBG_PMODE

GPP_E6
GPP_H2

CY46
CV49
CY47
CV45
DA47

DP33
DC45

DA49
DA45
DA48
CT49
CT48
CV47
CT47

CY39
CY38

DB39
DD38

DF38
DD39

CJ41

DL15
DV11

DT11
CR38
CR39

DT12
DJ38
DL38

UC1G

GPP_R0/HDA_BCLK/I2S0_SCLK
GPP_R1/HDA_SYNC/I2S0_SFRM
GPP_R2/HDA_SDO/I2S0_TXD
GPP_R3/HDA_SDI0/I2S0_RXD
GPP_R4/HDA_RST_N

GPP_D19/I2S_MCLK
GPP_A23/I2S1_SCLK

GPP_R5/HDA_SDI1/I2S1_SFRM
GPP_R6/I2S1_TXD
GPP_R7/I2S1_RXD
GPP_A7/I2S2_SCLK
GPP_A8/I2S2_SFRM/CNV_RF_RESET_N
GPP_A10/I2S2_RXD
GPP_A9/I2S2_TXD/MODEM_CLKREQ

GPP_S0/SNDW1_CLK
GPP_S1/SNDW1_DATA

GPP_S2/SNDW2_CLK
GPP_S3/SNDW2_DATA

GPP_S4/SNDW3_CLK/DMIC_CLK1
GPP_S5/SNDW3_DATA/DMIC_DATA1

ICELAKE-U_BGA1526

@

UC1D

J4

CATERR_N

CD5

PECI

C3

PROCHOT_N

E3

THRMTRIP_N
PROC_POPIRCOMP

DU3

PCH_OPIRCOMP

A14

RSVD_25

B14

RSVD_26
DBG_PMODE
GPP_E3/CPU_GP0

GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_E6
GPP_H2/CNV_BT_I2S_SDO
GPP_H19/TIME_SYNC0

ICELAKE-U_BGA1526

2

P3

PROC_TCK

K5

PROC_TDI

K3

PROC_TDO

P4

PROC_TMS

N1

PROC_TRST_N

N5

PCH_TRST_N

R5

PCH_TCK

K1

PCH_TDI

K2

PCH_TDO

N3

PCH_TMS

N2

PCH_JTAGX

P6

PROC_PRDY_N

M6

PROC_PREQ_N

4 of 19

@

GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

SD3.0

GPP_H0/CNV_BT_I2S_SDO

GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO

GPP_S6/SNDW4_CLK/DMIC_CLK0

GPP_S7/SNDW4_DATA/DMIC_DATA0

AUDIO

7 of 19

PCH_TCK_JTAGX_CPU
PCH_JTAG_TDI_CPU
PCH_JTAG_TDO_CPU
PCH_JTAG_TMS_CPU
XDP_TRST_CPU_N

XDP_TRST_CPU_N
PCH_JTAG_TCK
PCH_JTAG_TDI_CPU
PCH_JTAG_TDO_CPU
PCH_JTAG_TMS_CPU
PCH_TCK_JTAGX_CPU

PROC_PRDY_N
PROC_PREQ_N

GPP_G6/SD_CLK

GPP_G0/SD_CMD

GPP_G7/SD_WP

GPP_G5/SD_CD_N

SD3_RCOMP

SNDW_RCOMP

1

1

TP601 @

1

TP602 @

1

TP603 @

1

TP604 @

CE46
CC48
CC49
CC47
CF45
CC45
CF49
CE47

DK38

WIFI_WAKE_N PCIE_WAKE#_WLAN_R

DG38

SD_COMP

CJ43

DG36
DG34

SNDW_RCOMP

CV38

1 2

RC621 0_0201_5%@

1 2

RC623 1/20W_200_1%_0201

1 2

RC627 1/20W_200_1%_0201

+3VALW_PCH

1 2

RC632 100K_0201_5%@

A A

1 2

RC633 1K_0201_5%@

DBG_PMODE(Reserved): Rising edge of RSMRST#
This strap has a 20 kohm ± 30% internal pull-up.
This strap should sample high. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.
Notes:

1. The internal pull-up is disabled after RSMRST# deasserts.

2. This signal is in the primary well.

5

DBG_PMODE

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

6 60

6 60

6 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

4

3

2

1

PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

D D

+3VALW_PCH

RPC701

PCH_SML0_CLK

14

PCH_SML0_DATA

23

2.2K_0404_4P2R_5%
RPC702

PCH_SML1_CLK

2 3

PCH_SML1_DATA

1 4

2.2K_0404_4P2R_5%

1 2

RC708 4.7K_0402_5%

1 2

RC701 4.7K_0402_5%@

C C

+1.8VALW_PCH

ESPI_RST#

B B

+3VALW_PCH

PCH_SPI_SI / PCH_SPI_WP#(IO2) / PCH_SPI_HOLD#(IO3):
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.

RC712 75K_0402_1%
CC701 0.033UC_10VC_KC_X5RC_0201@

PCH_SPI_SO SPI_SO

RC722 49.9_0402_1%

PCH_SPI_CLK SPI_CLK

RC724 49.9_0402_1%

PCH_SMB_ALERT#
PCH_SML0_ALERT#

12

RC7091K_0402_5% @

12

RC71075K_0402_1% @

1 2

1 2

PCH_SPI_CS0#

12

RC714150K_0402_5% @

12

RC716100K_0402_5%

PCH_SPI_IO2 SPI_IO2

12

RC718100K_0402_5%

12

RC720100K_0402_5%

1 2
1 2

1 2

RC713 100K_0402_5%

GPP_C2(PCH_SMB_ALERT#):
This signal is used to wake the system or generate SMI#.
External Pull-up resistor is required.Rising edge of RSMRST#
This signal has a 20K+/-30% internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security (TLS)
cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security (TLS)
cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS.
Notes:

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. This signal is in the primary well.

GPP_C5(PCH_SML0_ALERT#):
Rising edge of RSMRST#
This signal has a 20K+/-30% internal pull-down.
0 = Enable eSPI. (Default)
1 = Disable eSPI.
Notes:

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. This signal is in the primary well

ESPI_CS#

1 2

EMC_NS@

SPI_CS#

SPI_SIPCH_SPI_SI

SPI_IO3PCH_SPI_IO3

1 2

RC715 0_0402_5%

1 2

RC717 49.9_0402_1%

1 2

RC719 49.9_0402_1%

1 2

RC721 49.9_0402_1%

1 2

RC723 100K_0402_5%@
CC703 5P_50V_B_NPO_0402

PCH_SPI_IO2 PCH_SMB_ALERT#
PCH_SPI_IO3
PCH_SPI_CS0#

UC1E

DB42

SPI0_CLK

DD43

SPI0_MOSI

DF43

SPI0_MISO

DF42

SPI0_IO2

DD41

SPI0_IO3

DB43

SPI0_CS0_N

DF41

SPI0_CS1_N

DB41

SPI0_CS2_N

DV16

GPP_E11/SPI1_CLK/BK1/SBK1

DT16

GPP_E13/SPI1_MOSI/BK3/SBK3

DU18

GPP_E12/SPI1_MISO/BK2/SBK2

DT18

GPP_E1/SPI1_IO2

DW18

GPP_E2/SPI1_IO3

DW16

GPP_E10/SPI1_CS_N/BK0/SBK0

DU16

GPP_E8/SATALED_N/SPI1_CS1_N

DV19

CL_CLK

DW19

CL_DATA

DT19

CL_RST_N

ICELAKE-U_BGA1526

@

2.2K_0404_4P2R_5%

PCH_SMB_CLK

PCH_SMB_DATA

SPI_CS#44
SPI_SO44

RPC703

+3VALW_PCH

1 4

+3VALW_PCH

SPI_CS#
SPI_SO
SPI_IO2

SPI 0 SPI 1 MLINK

SMBUSSML 0SML1eSPI

GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK

5 of 19

+3VS

2

G

QC701A

2 3

6 1

D

2N7002KDWH_SOT363-6

QC701B

2N7002KDWH_SOT363-6

1 2

RC711 0_0402_5%MP@

DC701

2

211

RB521CM-30T2R_VMN2M-2

NPI@

UC702

1

/CS

2

DO(IO1)

/HOLD(IO3)

3

/WP(IO2)

4

GND

W25Q128JVSIQ_SO8

GPP_C1/SMBDATA

GPP_C2/SMBALERT_N

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT_N

GPP_C7/SML1DATA/SUSACK_N

GPP_A5/ESPI_CLK

GPP_A0/ESPI_IO0
GPP_A1/ESPI_IO1
GPP_A2/ESPI_IO2
GPP_A3/ESPI_IO3

GPP_A4/ESPI_CS_N

GPP_A6/ESPI_RESET_N

+3VS

1 4

S

5

G

3 4

S

D

+3V_SPI

+3V_SPI

8

VCC

SPI_IO3

7

SPI_CLK

6

CLK

SPI_SI

5

DI(IO0)

GPP_C0/SMBCLK

RPC704

2.2K_0404_4P2R_5%

2 3

1

0.1U_6.3V_K_X5R_0201

2

DK27
DP24
DL24

DK24
DJ24
DP22

DN22
DL22

CR47
CN45
CN48
CN49
CN47
CT45
CR46

SMB_CLK_S3 18

SMB_DATA_S3 18

CC702

SPI_CLK 44

SPI_SI 44

PCH_SMB_CLK
PCH_SMB_DATA

PCH_SML0_CLK
PCH_SML0_DATA
PCH_SML0_ALERT#

PCH_SML1_CLK
PCH_SML1_DATA

ESPI_CLK_R

RC702 1/20W_49.9_1%_0201

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R
ESPI_CS#_R

1 2

RC703 1/20W_10_1%_0201

1 2

RC704 1/20W_10_1%_0201

1 2

RC705 1/20W_10_1%_0201

1 2

RC706 1/20W_10_1%_0201

1 2

RC707 0_0402_5%

12

ESPI_CLK 44
ESPI_IO0 44
ESPI_IO1 44
ESPI_IO2 44
ESPI_IO3 44
ESPI_CS# 44
ESPI_RST# 44

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

7 60

7 60

7 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

4

3

2

1

PCH_I2C1_SDA_TP

PCH_TP_INT#45

D D

DGPU_PWROK23,58

PCH_WLAN_PERST#40
PCH_WLAN_OFF#40
PCH_BEEP30

RC806 0_0402_5%OPT@

1 2

DEBUG

TS

TP

PCH_I2C1_SDA_TP45
PCH_I2C1_SCL_TP45

PCH_TP_INT#
GPP_B18
PCH_WLAN_PERST#
PCH_WLAN_OFF#
PCH_BEEP

SML1_ALERT#
DGPU_PWROK_R

UART2_RXD
UART2_TXD

PCH_I2C1_SDA_TP
PCH_I2C1_SCL_TP

SENSOR

C C

1 2

RC811 100K_0201_5%@

+3VALW_PCH

B B

1 2

RC814 1/20W_150K_5%_0201@

1 2

RC818 1/20W_20K_5%_0201

GPP_B23(SML1_ALERT#):
This signal has a 20K+-30% internal pull-down.
0 = 38.4 MHz clock (direct from crystal) (default)
1 = 19.2 MHz clock (derived from 38.4 MHz crystal)
Notes:

1. The internal pull-down is disabled after RSMRST# de-asserts

2.When used as PCHHOT# and strap low, a 150K pull-up
is needed to ensure it does not override the internal pull-down
strap sampling.

3. This signal is in the primary well

PCH_WLAN_PERST#

SML1_ALERT#

+3VS

RC815 4.7K_0402_5%@

GPP_B14(PCH_BEEP):
Rising edge of PCH_PWROK
The strap has a 20 kohm ± 30% internal pull-down.
0 = Disable Top Swap mode. (Default)
1 = Enable Top Swap mode. This inverts an address on access to SPI
and firmware hub, so the processor believes it fetches the alternate
boot block instead of the original boot-block. PCH will invert A16
(default) for cycles going to the upper two 64-KB blocks in the FWH
or the appropriate address lines (A16, A17, or A18) as selected
in Top Swap Block size soft strap.
Notes:

1. The internal pull-down is disabled after PCH_PWROK is high.

2. Software will not be able to clear the Top Swap bit until the system
is rebooted.

3. The status of this strap is readable using the Top Swap bit
(Bus0, Device31, Function0, offset DCh, bit4).

4. This signal is in the primary well.

UC1F

CH48

GPP_B16/GSPI0_CLK

CF48

GPP_B18/GSPI0_MOSI

CF47

GPP_B17/GSPI0_MISO

CH49

GPP_B15/GSPI0_CS0_N

CH47

GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1_N

CL47

GPP_B20/GSPI1_CLK

CK47

GPP_B22/GSPI1_MOSI

CK46

GPP_B21/GSPI1_MISO

CH45

GPP_B19/GSPI1_CS0_N

CL48

GPP_B23/SML1ALERT_N/PCHHOT_N/GSPI1_CS1_N

DP21

GPP_C8/UART0_RXD

DK21

GPP_C9/UART0_TXD

DL21

GPP_C10/UART0_RTS_N

DJ22

GPP_C11/UART0_CTS_N

DT22

GPP_C20/UART2_RXD

DW22

GPP_C21/UART2_TXD

DV22

GPP_C22/UART2_RTS_N

DU22

GPP_C23/UART2_CTS_N

DT24

GPP_C16/I2C0_SDA

DT23

GPP_C17/I2C0_SCL

DW23

GPP_C18/I2C1_SDA

DU23

GPP_C19/I2C1_SCL

DU41

GPP_H4/I2C2_SDA

DV41

GPP_H5/I2C2_SCL

DW41

GPP_H6/I2C3_SDA

DT41

GPP_H7/I2C3_SCL

DT40

GPP_H8/I2C4_SDA/CNV_MFUART2_RXD

DW40

GPP_H9/I2C4_SCL/CNV_MFUART2_TXD

ICELAKE-U_BGA1526

@

1 2

GPP_D13/ISH_UART0_RXD

GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5

6 of 19

PCH_BEEP

GPP_D14/ISH_UART0_TXD

GPP_D16/ISH_UART0_CTS_N/CNV_WCEN

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS_N/ISH_UART1_RTS_N
GPP_C15/UART1_CTS_N/ISH_UART1_CTS_N

GPP_B5/ISH_I2C0_SDA
GPP_B6/ISH_I2C0_SCL

GPP_B7/ISH_I2C1_SDA
GPP_B8/ISH_I2C1_SCL

GPP_B9/I2C5_SDA/ISH_I2C2_SDA

GPP_B10/I2C5_SCL/ISH_I2C2_SCL

GPP_D0/ISH_GP0
GPP_D1/ISH_GP1
GPP_D2/ISH_GP2

GPP_D3/ISH_GP3
GPP_D17/ISH_GP4
GPP_D18/ISH_GP5
GPP_E15/ISH_GP6
GPP_E16/ISH_GP7

+3VS

RC816 1/20W_4.7K_5%_0201@
RC819 1/20W_20K_5%_0201@

GPP_B18:Rising edge of PCH_PWROK
The signal has a weak internal pull-down.
0 = Disable No Reboot mode. (Default)
1 = Enable No Reboot mode (PCH will disable the
TCO Timer system reboot feature). This function is
useful when running ITP/XDP.
Notes:

1. The internal pull-down is disabled after
PCH_PWROK is high.

2. This signal is in the primary well.

1 2
1 2

DV33
DW33
DT33
DU33

DK22
DW24
DV24
DU24

CN43
CN42

CN41
CL43

CL41
CJ39
DU36
DV36
DW36
DT36
DU34
DW34
DT14
DU14

FB_GC6_EN_R
GPU_EVENT#
PXS_PWREN_R
PXS_RST#_R

GPP_B18

1 2

RC804 1K_0201_5%OPT@

1 2

RC805 0_0402_5%OPT@

FB_GC6_EN_R 23,26

GPU_EVENT# 26

PXS_PWREN 23
PXS_RST# 26

PCH_I2C1_SCL_TP

PCH_TP_INT#

UART2_TXD
UART2_RXD

PXS_PWREN_R

PXS_RST#_R

FB_GC6_EN_R

GPU_EVENT#

PXS_RST#

DGPU_PWROK_R

RPC801

1 4
2 3

2.2K_0404_4P2R_5%

1 2

RC801 10K_0402_5%

1 2

RC802 49.9K_0402_1%

1 2

RC803 49.9K_0402_1%

1 2

RC807 10K_0201_5%OPT@

1 2

RC808 10K_0201_5%@

1 2

RC809 10K_0201_5%@

1 2

RC810 10K_0201_5%OPT@

1 2

RC812 10K_0201_5%@

1 2

RC813 10K_0201_5%OPT@

1 2

RC817 10K_0201_5%@

1 2

CC801 0.01U_6.3V_K_X7R_0201

OPT@

1 2

RC820 10K_0201_5%UMA@

+3VS

+3VS

+3VS

+3VS

+3VS

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

8 60

8 60

8 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

PCIE_CRX_GTX_N[5..8]20

PCIE_CRX_GTX_P[5..8]20
PCIE_CTX_C_GRX_N[5..8]20
PCIE_CTX_C_GRX_P[5..8]20

PCIE_CTX_C_GRX_N7 PCIE_CTX_GRX_N7

D D

dGPU

WLAN

HDD

1 2

1 2
1 2

SSD

12

C C

+3VALW_PCH

RC904 10K_0201_5%

+1.8VALW_PCH

RC906 10K_0201_5%
RC907 10K_0201_5%

B B

RC908 10K_0201_5%@

PCIE_CTX_C_GRX_P7 PCIE_CTX_GRX_P7

PCIE_CTX_C_GRX_N8 PCIE_CTX_GRX_N8
PCIE_CTX_C_GRX_P8 PCIE_CTX_GRX_P8

PCIE_PRX_DTX_N940
PCIE_PRX_DTX_P940
PCIE_PTX_C_DRX_N940
PCIE_PTX_C_DRX_P940

SATA_PRX_DTX_N037
SATA_PRX_DTX_P037
SATA_PTX_DRX_N037
SATA_PTX_DRX_P037

PCIE_PRX_DTX_N1337
PCIE_PRX_DTX_P1337
PCIE_PTX_DRX_N1337
PCIE_PTX_DRX_P1337

PCIE_PRX_DTX_N1437
PCIE_PRX_DTX_P1437
PCIE_PTX_DRX_N1437
PCIE_PTX_DRX_P1437

PCIE_PRX_DTX_N1537
PCIE_PRX_DTX_P1537
PCIE_PTX_DRX_N1537
PCIE_PTX_DRX_P1537

PCIE_PRX_DTX_N1637
PCIE_PRX_DTX_P1637
PCIE_PTX_DRX_N1637
PCIE_PTX_DRX_P1637

USB_OC0#

USB_OC3#
SSD_PCIE_DET#
PCH_SATA_2_DEVSLP

PCH_BT_OFF#40
SSD_PCIE_DET#37
USB_OC0#43

4

1 2

CC9010.22U_0201_6.3V6-KOPT@

1 2

CC9020.22U_0201_6.3V6-KOPT@

1 2

CC9030.22U_0201_6.3V6-KOPT@

1 2

CC9040.22U_0201_6.3V6-KOPT@

1 2

CC905 0.1U_6.3V_K_X5R_0201

1 2

CC906 0.1U_6.3V_K_X5R_0201

Native OD output

1 2

RC905 1/20W_100_1%_0201

PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P7

PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P8

PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

PCIE_PRX_DTX_N13
PCIE_PRX_DTX_P13
PCIE_PTX_DRX_N13
PCIE_PTX_DRX_P13

PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14
PCIE_PTX_DRX_N14
PCIE_PTX_DRX_P14

PCIE_PRX_DTX_N15
PCIE_PRX_DTX_P15
PCIE_PTX_DRX_N15
PCIE_PTX_DRX_P15

PCIE_PRX_DTX_N16
PCIE_PRX_DTX_P16
PCIE_PTX_DRX_N16
PCIE_PTX_DRX_P16

SSD_PCIE_DET#
USB_OC0#

USB_OC3#

PCH_SATA_2_DEVSLP

PCIE_RCOMPN
PCIE_RCOMPP

PCH_SATA_2_DEVSLP

UC1H

CV7

PCIE7_RXN

CV6

PCIE7_RXP

DD3

PCIE7_TXN

DD5

PCIE7_TXP

CT6

PCIE8_RXN

CT7

PCIE8_RXP

DA3

PCIE8_TXN

DA5

PCIE8_TXP

CP7

PCIE9_RXN

CP6

PCIE9_RXP

DA2

PCIE9_TXN

DA1

PCIE9_TXP

CM7

PCIE10_RXN

CM6

PCIE10_RXP

CY3

PCIE10_TXN

CY4

PCIE10_TXP

CK7

PCIE11_RXN/SATA0_RXN

CK6

PCIE11_RXP/SATA0_RXP

CW2

PCIE11_TXN/SATA0_TXN

CW1

PCIE11_TXP/SATA0_TXP

CJ6

PCIE12_RXN/SATA1A_RXN

CJ7

PCIE12_RXP/SATA1A_RXP

CW5

PCIE12_TXN/SATA1A_TXN

CW3

PCIE12_TXP/SATA1A_TXP

CG7

PCIE13_RXN

CG6

PCIE13_RXP

CT3

PCIE13_TXN

CT5

PCIE13_TXP

CE6

PCIE14_RXN

CE7

PCIE14_RXP

CT2

PCIE14_TXN

CT1

PCIE14_TXP

CC5

PCIE15_RXN/SATA1B_RXN

CC6

PCIE15_RXP/SATA1B_RXP

CR3

PCIE15_TXN/SATA1B_TXN

CR4

PCIE15_TXP/SATA1B_TXP

CA6

PCIE16_RXN/SATA2_RXN

CA5

PCIE16_RXP/SATA2_RXP

CP1

PCIE16_TXN/SATA2_TXN

CP2

PCIE16_TXP/SATA2_TXP

DW12

GPP_E0/SATAXPCIE0/SATAGP0

CR42

GPP_A12/SATAXPCIE1/SATAGP1

CR43

GPP_A13/SATAXPCIE2/SATAGP2

DW14

GPP_E9/USB_OC0_N

CT43

GPP_A16/USB_OC3_N

DU12

GPP_E4/DEVSLP0

DU11

GPP_E5/DEVSLP1

CV48

GPP_A11/SATA_DEVSLP2

DT38

GPP_H12/M2_SKT2_CFG0

DW38

GPP_H13/M2_SKT2_CFG1

DV38

GPP_H14/M2_SKT2_CFG2

DU38

GPP_H15/M2_SKT2_CFG3

DN1

PCIE_RCOMPN

DN3

PCIE_RCOMPP

ICELAKE-U_BGA1526

@

+1.8VALW_PCH

2

G1

8 of 19

RC909

100K_0402_5%

1 2

6

D1

QC901A

S1

1

PJT7838_SOT363-6

3

PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP

PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP

PCIE2_RXN/USB31_2_RXN
PCIE2_RXP/USB31_2_RXP

PCIE2_TXN/USB31_2_TXN
PCIE2_TXP/USB31_2_TXP

PCIE3_RXN/USB31_3_RXN
PCIE3_RXP/USB31_3_RXP

PCIE3_TXN/USB31_3_TXN
PCIE3_TXP/USB31_3_TXP

PCIE4_RXN/USB31_4_RXN
PCIE4_RXP/USB31_4_RXP

PCIE4_TXN/USB31_4_TXN
PCIE4_TXP/USB31_4_TXP

PCIE5_RXN/USB31_5_RXN
PCIE5_RXP/USB31_5_RXP

PCIE5_TXN/USB31_5_TXN
PCIE5_TXP/USB31_5_TXP

PCIE6_RXN/USB31_6_RXN
PCIE6_RXP/USB31_6_RXP

PCIE6_TXN/USB31_6_TXN
PCIE6_TXP/USB31_6_TXP

USB_VBUSSENSE

USB2_COMP

3

5

G2

4

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB_ID

RSVD_81

PCH_SATA_DEVSLP

D2

QC901B

S2

PJT7838_SOT363-6

2

USB30_RX_N1

DJ8

USB30_RX_P1

DJ6

USB30_TX_N1

DJ2

USB30_TX_P1

DJ1

USB30_RX_N2

DG9

USB30_RX_P2

DG7

USB30_TX_N2

DJ3

USB30_TX_P2

DJ5
DE7

DE9
DF3
DF5

DC7
DC9
DF2
DF1

PCIE_CRX_GTX_N5

DA6

PCIE_CRX_GTX_P5

DA7

PCIE_CTX_GRX_N5 PCIE_CTX_C_GRX_N5

DE4

PCIE_CTX_GRX_P5 PCIE_CTX_C_GRX_P5

DE3

PCIE_CRX_GTX_N6

CY7

PCIE_CRX_GTX_P6

CY6

PCIE_CTX_GRX_N6 PCIE_CTX_C_GRX_N6

DD1

PCIE_CTX_GRX_P6 PCIE_CTX_C_GRX_P6

DD2

USB20_N1

DN8

USB20_P1

DP8

USB20_N2

DK11

USB20_P2

DJ11
DP13

DN13
DK10

DJ10

USB20_N5

DL5

USB20_P5

DL3

USB20_N6

DP11

USB20_P6

DN11

USB20_N7

DK13

USB20_P7

DJ13

USB20_N8

DN6

USB20_P8

DP6

USB20_N9

DL2

USB20_P9

DL1

USB20_N10

DP10

USB20_P10

DN10

USB2_ID

DL6

USB2_VBUSSENSE

DL11

USB2_COMP

DN5
CD3

PCH_SATA_DEVSLP 37

USB30_RX_N1 43
USB30_RX_P1 43
USB30_TX_N1 43
USB30_TX_P1 43

USB30_RX_N2 41
USB30_RX_P2 41
USB30_TX_N2 41
USB30_TX_P2 41

12

CC907 0.22U_0201_6.3V6-K OPT@

12

CC908 0.22U_0201_6.3V6-K OPT@

12

CC909 0.22U_0201_6.3V6-K OPT@

12

CC910 0.22U_0201_6.3V6-K OPT@

USB20_N1 41
USB20_P1 41

USB20_N2 43
USB20_P2 43

USB3.0 Port2
USB3.0 Port1

TBT

Type-C B

USB20_N5 33
USB20_P5 33

USB20_N6 33
USB20_P6 33

USB20_N7 45
USB20_P7 45

USB20_N8 30
USB20_P8 30

USB20_N9 43
USB20_P9 43

USB20_N10 40
USB20_P10 40

1 2

RC901 0_0201_5%

1 2

RC902 0_0201_5%

1 2

RC903 1/16W_113_1%_0402

Camera

Touch Screen

Finger Print

Card reader
USB2.0

BT

USB3.0 Port1

USB3.0 Port2

1

dGPU

PCH_SATA_2_DEVSLP PCH_SATA_DEVSLP

1. DEVSLP is an open-drain pin on the PCH side and is not required external pull-up orpull-down. The PCH will
tri-state this pin to signal to the SATA device that it may enter a lower power state (pin will go high due to pull-up
that’s internal to the SATAdevice, per DEVSLP specification). PCH will drive pin low to signal an exit fromDEVSLP state.

2. DEVSLP is supported in direct connect, mSATA/mPCIe, uSSD, M.2.

3. 1 DEVSLP pin is required to support EACH DEVSLP enabled RAID storage device.

A A

(Example: 2 DEVSLP pins are required to support 2 DEVSLP RAID storage devices).

5

4

@

1 2

RC910 0_0402_5%

3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

9 60

9 60

9 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

www.teknisi-indonesia.com

4

3

2

1

UC1I

D12

CSI_E_CLK_N

C12

CSI_E_CLK_P

B12

CSI_E_DN_0

A12

CSI_E_DP_0

G13

CSI_E_DN_1

F13

CSI_E_DP_1

K10

CSI_F_CLK_N

L10

CSI_F_CLK_P

L8

CSI_F_DN_0

M8

CSI_F_DP_0

D D

1 2

RC1008 100_0402_1%

+3VS

C C

B B

XTAL_PCH_38P4M_IN

XTAL_PCH_38P4M_OUT

XTAL_PCH_38P4M_IN_R

A A

CC1004

10P_0402_50V8J

WLAN_CLKREQ#

12

RC101210K_0201_5% @

SSD_CLKREQ#

12

RC101310K_0201_5%

GPU_CLKREQ#

12

RC101410K_0201_5%

CLK_PCIE_WLAN#40
CLK_PCIE_WLAN40
WLAN_CLKREQ#40

CLK_PCIE_SSD#37
CLK_PCIE_SSD37
SSD_CLKREQ#37

CLK_PCIE_GPU#20
CLK_PCIE_GPU20
GPU_CLKREQ#20

RC1017 0_0402_5%

4

4

1

1

EXC24CH500U_4P

1 2

RC1021 0_0402_5%

1 2

RC1023 200K_0402_1%

YC1001

4

NC1
OSC11NC2

1

38.4MHZ_10PF_7R38400001

2

1 2

LC1000

EMC_NS@

OSC2

3

3

2

2

3
2

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#

CLK_PCIE_SSD#
CLK_PCIE_SSD
SSD_CLKREQ#

CLK_PCIE_GPU#
CLK_PCIE_GPU
GPU_CLKREQ#

XTAL_PCH_38P4M_OUT_R

1

10P_0402_50V8J

2

M11
L11

D9
C9
A7
B7
B9
A9
D7
C7
D8
C8

G11
J11

F6
G6

G10
F10

G8

J8
K6

L6

CSI2_COMP

B4

DT34
DP38
DK36
DL36
DN38

CJ3
CJ5

DK33

CL2
CL1

DN34

CL3
CL5

DP34

CK3
CK4

DP36

CJ2
CJ1

DN40

XTAL_PCH_38P4M_IN_R

XTAL_PCH_38P4M_OUT_R

CC1005

CSI_F_DN_1
CSI_F_DP_1

CSI_D_CLK_N
CSI_D_CLK_P
CSI_D_DN_0
CSI_D_DP_0
CSI_D_DN_1
CSI_D_DP_1
CSI_D_DN_2/CSI_C_DN_0
CSI_D_DP_2/CSI_C_DP_0
CSI_D_DN_3/CSI_C_CLK_N
CSI_D_DP_3/CSI_C_CLK_P

CSI_H_CLK_N
CSI_H_CLK_P
CSI_H_DN_0
CSI_H_DP_0
CSI_H_DN_1
CSI_H_DP_1
CSI_H_DN_2/CSI_G_DN_0
CSI_H_DP_2/CSI_G_DP_0
CSI_H_DN_3/CSI_G_CLK_N
CSI_H_DP_3/CSI_G_CLK_P

CSI_RCOMP
GPP_D4/IMGCLKOUT0

GPP_H20/IMGCLKOUT1
GPP_H21/IMGCLKOUT2
GPP_H22/IMGCLKOUT3
GPP_H23/IMGCLKOUT4

ICELAKE-U_BGA1526

@

UC1J

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_D5/SRCCLKREQ0_N

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_D6/SRCCLKREQ1_N

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_D7/SRCCLKREQ2_N

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_D8/SRCCLKREQ3_N

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_H10/SRCCLKREQ4_N

ICELAKE-U_BGA1526

@

CSI2

9 of 19

GPP_H11/SRCCLKREQ5_N

10 of 19

RC1022 10M_0402_5%

32.768KHZ 9PF 202934-PG14

1

10P_0402_50V8J

2

GPP_F8/EMMC_DATA0

GPP_F9/EMMC_DATA1
GPP_F10/EMMC_DATA2
GPP_F11/EMMC_DATA3
GPP_F12/EMMC_DATA4
GPP_F13/EMMC_DATA5
GPP_F14/EMMC_DATA6

eMMCCNVi

GPP_F15/EMMC_DATA7

GPP_F7/EMMC_CMD

GPP_F16/EMMC_RCLK

GPP_F17/EMMC_CLK

GPP_F18/EMMC_RESET_N

EMMC_RCOMP

CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N

CNV_WT_D1P
CNV_WT_CLKN
CNV_WT_CLKP

CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N

CNV_WR_D1P
CNV_WR_CLKN
CNV_WR_CLKP

GPP_F1/CNV_BRI_RSP/UART0_RXD

GPP_F0/CNV_BRI_DT/UART0_RTS_N

GPP_F3/CNV_RGI_RSP/UART0_CTS_N

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

GPD8/SUSCLK

XCLK_BIASREF

CC1002

CNV_WT_RCOMP

GPP_F2/CNV_RGI_DT/UART0_TXD

GPP_F4/CNV_RF_RESET_N

GPP_F6/CNV_PA_BLANKING

GPP_F19/A4WP_PRESENT

GPP_F5/MODEM_CLKREQ

CF5
CF3
DP40

RTC_X1

DL48

RTCX1

RTC_X2

DL49

RTCX2

RTC_RST#

DT47

RTCRST_N

SRTCRST_N

XTAL_IN

XTAL_OUT

1 2

YC1000

1 2

SRTC_RST#

DK46
DF49

SUSCLK

XTAL_PCH_38P4M_IN

DW8

XTAL_PCH_38P4M_OUT

DU8

XCLK_BIASREF

DU6

1

2

10P_0402_50V8J

CC1003

BOARD_ID0

DP27

BOARD_ID1

DU30

BOARD_ID2

DT30

BOARD_ID3

DT29

BOARD_ID4

DV30

BOARD_ID5

DU29

BOARD_ID6

DW30

BOARD_ID7

DW29

BOARD_ID8

DV28

BOARD_ID9

DW28

BOARD_ID10

DN27

BOARD_ID11

DT28

EMMC_COMP

DU28

CNV_WT_D0N

DV45

CNV_WT_D0P

DU45

CNV_WT_D1N

DU44

CNV_WT_D1P

DT44

CNV_WT_CLKN

DL42

CNV_WT_CLKP

DK42

CNV_WR_D0N

DP44

CNV_WR_D0P

DN44

CNV_WR_D1N

DG42

CNV_WR_D1P

DG44

CNV_WR_CLKN

DK44

CNV_WR_CLKP

DJ44

CNV_WT_RCOMP

DT45

CNVI_BRI_RSP

DL29

CNVI_RGI_DT_R

DP31

CNVI_BRI_DT_R

DL31

CNVI_RGI_RSP

DN29

BOARD_ID12

DJ29
DP29

WP_PRESENT

DL27
DK29

SUSCLK 40

1 2

RC1016 1/20W_60.4_1%_0201

12

RC10151K_0402_5% @

RTC_X1
RTC_X2

1 2

RC1003 200_0402_1%

CNV_WT_D0N 40
CNV_WT_D0P 40
CNV_WT_D1N 40
CNV_WT_D1P 40
CNV_WT_CLKN 40
CNV_WT_CLKP 40

CNV_WR_D0N 40
CNV_WR_D0P 40
CNV_WR_D1N 40
CNV_WR_D1P 40
CNV_WR_CLKN 40
CNV_WR_CLKP 40

1 2

RC1005 150_0402_1%

CNVI_BRI_RSP 40

1 2

RC1006 1/20W_22_5%_0201

1 2

RC1007 1/20W_22_5%_0201

CNVI_RGI_RSP 40

1 2

RC1010 1/20W_75K_5%_0201

SUSCLK

VCCRTC

1 2

RC1018 20K_0402_1%

1 2

RC1020 20K_0402_1%

CNVI_RGI_DT 40
CNVI_BRI_DT 40

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
BOARD_ID9
BOARD_ID10
BOARD_ID11
BOARD_ID12

1

CC1000

1U_6.3V_K_X5R_0201

2

RTC_RST#
SRTC_RST#

1

CC1001

1U_6.3V_K_X5R_0201

2

+1.8VALW_PCH

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

RC1019 0_0402_5%

RC833

@

RC846

@

12

100K_0201_5%

12

@

1 2

RC832

@

RC845

12

100K_0201_5%

12

RC831

@

RC844

@

BOARD ID

100K_0201_5%

100K_0201_5%

RC829

RC830

12

12

@

@

RC842

100K_0201_5%

RC843

100K_0201_5%

12

12

@

@

CNVI_RGI_RSP
CNVI_BRI_RSP

CNVI_BRI_DT_R

GPP_F0 /CNV_BRI_DT /UART0_RTS#
XTAL Frequency Selection, Rising edge of RSMRST#
This strap has a 20 kohm ± 30% internal pull-down.
This strap should not be pulled high since 24 MHz crystal is not
supported on the PCH.
0 = 38.4 MHz (default)
1 = 24 MHz
Notes:

1. The internal pull-down is disabled after RSMRST# de-asserts.

2. This signal is in the primary well.

CNVI_RGI_DT_R

GPP_F2 /CNV_RGI_DT /UART0_TXD:
M.2 CNVI MODES, Rising edge of RSMRST#
A weak external pull-up is required.
0 = Integrated CNVi enabled.
1 = Integrated CNVi disabled.
Note:
When a RF companion chip is connected to the PCH CNVi interface,
the device internal pulldown resistor will pull the strap low to
enable CNVi interface.

100K_0201_5%

100K_0201_5%

RC827

RC828

12

12

@

@

RC840

100K_0201_5%

RC841

100K_0201_5%

12

12

@

@

BOARD_ID5

BOARD_ID6/7/8/9

EC_RTC_RST# 44

100K_0201_5%

RC826

12

15@

RC839

100K_0201_5%

12

14@

Sumsang
Hynix
Micron

1 2

RC1000 20K_0402_5%@

1 2

RC1001 20K_0402_5%@

1 2

RC1002 4.7K_0402_5%@

1 2

RC1004 1/20W_20K_5%_0201@

RC1009 100K_0402_5%@
RC1011 4.7K_0402_5%@

100K_0201_5%

RC825

12

@

RC838

100K_0201_5%

12

@

H 15"
L 14"

Pull up at CONN

1 2
1 2

100K_0201_5%

RC824

12

@

RC837

100K_0201_5%

12

@

0000
0001
0010

100K_0201_5%

12

100K_0201_5%

12

@

RC823

@

RC836

100K_0201_5%

12

@

100K_0201_5%

12

@

+1.8VALW_PCH

+1.8VALW_PCH

+1.8VALW_PCH

100K_0201_5%

RC821

RC822

12

@

RC835

RC834

100K_0201_5%

12

@

12

12

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

10 60

10 60

10 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

D D

PLT_RST#26,37,40,44

PCH_PWROK44
SYS_PWROK44

4

PM_SLP_SUS#44
PM_SLP_S4#44

PM_SLP_S3#44
PM_SLP_S0#44
PM_SLP_WLAN#40

1 2

RC1101 0_0201_5%

1 2

RC1105 0_0201_5%

1 2

RC1106 0_0201_5%

PM_SLP_SUS#
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
PM_SLP_A#
PM_SLP_S0#_R

PM_SLP_WLAN#
PM_SLP_LAN#

PCH_RSMRST#_R
SYS_RESET#
PLT_RST#_R

PCH_DPWROK_R
PCH_PWROK_R
SYS_PWROK_R

INPUT3VSEL
INTRUDER#

DM49

CM49

DF45
DC48
DF47
DH47
CL45

DE49
DN48

DG49
DK19

DR48
DN47
DP19

DN49
DR47

UC1K

SLP_SUS_N
GPD10/SLP_S5_N
GPD5/SLP_S4_N
GPD4/SLP_S3_N
GPD6/SLP_A_N
GPP_B12/SLP_S0_N

GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO
GPD9/SPL_WLAN_N
SLP_LAN_N

RSMRST_N
SYS_RESET_N
GPP_B13/PLTRST_N

DSW_PWROK
PCH_PWROK
SYS_PWROK

INPUT3VSEL
INTRUDER_N

ICELAKE-U_BGA1526

@

11 of 19

3

GPD3/PWRBTN_N

GPD1/ACPRESENT

GPD0/BATLOW_N

GPP_B11/PMCALERT

GPP_H18/CPU_C10_GATE_N

GPD_2/LAN_WAKE_N

GPD11/LANPHYPC/DSWLDO_MON

VCCST_OVERRIDE

VCCST_PWRGD

VCCSTPWRGOOD_TCSS

PROCPWRGD

WAKE_N

GPD7

CY42
DE46
DH48

CL39
DU40
DG40

DL45
DE47

DF48
CE4

CF2
CE3
CF1

DC47

PBTN_OUT#_R
AC_PRESENT_R
BATLOW#

CPU_C10_GATE#
SX_EXIT_HOLDOFF#

PCH_LAN_WAKE#
PCH_CNVI_EN#

VCCST_OVERRIDE_R
VCCST_PWRGD_R
VCCSTPWRGOOD_TCSS
CPU_PROCPWRGD

2

PBTN_OUT#_R 44
AC_PRESENT_R 44

1

TP1102 @

1

TP1101 @

PCIE_WAKE# 40

1 2

RC1100 0_0402_5%

1 2

RC1102 0_0201_5%

1 2

RC1103 60.4_0402_1%

1 2

RC1104 0_0201_5%

1

TP1100 @

CNVI_EN# 40

VCCST_OVERRIDE

VCCST_OVERRIDE
EC_VCCST_PWRGD 44

46

1

DSW_PWROK and RSMRST# are always separate power good signals

PCH_DPWROK44

EC_RSMRST#44

C C

B B

A A

PCH_DPWROK PCH_DPWROK_R

EC_RSMRST#

+3VALW_PCH

RC1111 4.7K_0402_5%@
RC1112 100K_0402_5%

CAD NOTE:
INPUT3VSEL: 3V SELECT STRAP
LOW-> 3.3V +/-5%
HIGH->3.0V +/-5%

VCCRTC

1 2

RC1118 1M_0402_5%@

1 2

RC1121 10K_0402_5%

@

12

CC1100 0.1U_6.3V_K_X5R_0201

SPI Voltage Configuration:
The VCCSPI voltage (3.3V or 1.8V) is selected via a hard strap
on the INTRUDER#.
This strap sets the SPI interface signaling voltage at the rising edge
of RTCRST#. Designers should strap this pin to match the expected
interface operational voltage for their target SPI device as follows.
0 = SPI interface operation voltage is 3.3V
(ground through a 10kohm resistor)
1 = SPI interface operation voltage is 1.8V
(pulled up with 1 Mohm to VCCRTC)

PCH_RSMRST#_R
PCH_DPWROK_R

CC1107 1000P_0201_50V7-K EMC_NS@
CC1109 1000P_0201_50V7-K EMC_NS@

1 2

RC1107 0_0402_5%

1 2

RC1108 10K_0402_5%

1 2

RC1109 0_0402_5%

1 2

RC1110 10K_0402_5%

12
12

INTRUDER#

12
12

FOR EMC

INPUT3VSEL

PCH_RSMRST#_R

PM_SLP_S3#

Glitch Free Requirements:
Pull-up resistor is required if a device is monitoring SLP_S0#
before RSMRST# de-assertion
100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

PM_SLP_S0#_R

Glitch Free Requirements:
Cap or pull-down resistor is required

Option 1:Cap Implementation
330 nF for 3.3v Ramp Rate from 5-50ms
33 nF for 3.3V Ramp Rate Less than 5ms

Option 2:Pull-down Resistor Implementation
100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

PM_SLP_SUS#

PM_SLP_S3#

PM_SLP_S4#

PM_SLP_A#

PM_SLP_WLAN#

PM_SLP_LAN#

PM_SLP_S5#

PLT_RST#

RC1126 100K_0201_5%
CC1101 0.033UC_10VC_KC_X5RC_0201@

RC1128 100K_0201_5%
CC1102 0.033UC_10VC_KC_X5RC_0201@

RC1129 100K_0201_5%
CC1103 0.033UC_10VC_KC_X5RC_0201@

RC1130 100K_0201_5%@
CC1104 0.033UC_10VC_KC_X5RC_0201@

RC1131 100K_0201_5%@
CC1105 0.033UC_10VC_KC_X5RC_0201@

RC1132 100K_0201_5%@
CC1106 0.033UC_10VC_KC_X5RC_0201@

RC1133 100K_0201_5%@
CC1108 0.033UC_10VC_KC_X5RC_0201@

RC1134 100K_0201_5%

+3VALW

RC1135

100K_0201_5%

@

1 2

61

D

2

G

S

QC1101A

2N7002KDWH_SOT363-6

@

1 2

RC1115 100K_0201_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2
1 2

1 2

1 2

1 2

1 2

1 2

5

G

EC_VCCST_PWRGD

34

D

QC1101B

2N7002KDWH_SOT363-6

S

@

+3VALW_PCH

EC_VCCST_PWRGD

SYS_RESET#

PCIE_WAKE#
PCH_LAN_WAKE#
PBTN_OUT#_R
BATLOW#
AC_PRESENT_R
CPU_C10_GATE#

PCH_PWROK
SYS_PWROK
VCCST_OVERRIDE

1 2

RC1113 1K_0402_5%

1 2

RC1114 10K_0201_5%

1 2

RC1116 10K_0201_5%

1 2

RC1117 10K_0402_5%

1 2

RC1119 100K_0201_5%@

1 2

RC1120 100K_0201_5%

1 2

RC1122 100K_0402_5%

1 2

RC1123 1/20W_20K_5%_0201@

1 2

RC1124 10K_0201_5%

1 2

RC1125 10K_0201_5%

1 2

RC1127 100K_0402_5%

+VCCST_CPU

+3VS

+3VALW_PCH

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

11 60

11 60

11 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

+VCCIN +VCCIN

D D

C C

VR_SVID_ALRT#56

VR_SVID_CLK56

VR_SVID_DAT56

VR_SVID_ALERT_N
VR_SVID_CLK
VR_SVID_DAT

AC12

BN10
BP11

BR10
BT11

BU10
BV36

BW10
BW36

BY10

CA36
CB10

CC11
CC36

CD10
CE11

CE34
CE35
CF10
CF33
CG11
CG34
CG35
CH10

CJ11
CJ34

A19
V13

W12

Y13
K29
K31
B19
B23
B27
B29

BP9

A21
BT9

BV9

BW9

C19
C23
A23
C27
C29

CA9

CC9

A24

J30

A27

H1
H2
H3

UC1L

VCCIN_1
VCCIN_2
VCCIN_3
VCCIN_4
VCCIN_5
VCCIN_6
VCCIN_7
VCCIN_8
VCCIN_9
VCCIN_10
VCCIN_11
VCCIN_12
VCCIN_13
VCCIN_14
VCCIN_15
VCCIN_16
VCCIN_17
VCCIN_18
VCCIN_19
VCCIN_20
VCCIN_21
VCCIN_22
VCCIN_23
VCCIN_24
VCCIN_25
VCCIN_26
VCCIN_27
VCCIN_28
VCCIN_29
VCCIN_30
VCCIN_31
VCCIN_32
VCCIN_33
VCCIN_34
VCCIN_35
VCCIN_36
VCCIN_37
VCCIN_38
VCCIN_39
VCCIN_40
VCCIN_41
VCCIN_42
VCCIN_43
VCCIN_44
VCCIN_45
VCCIN_46
VCCIN_47
VCCIN_48
VCCIN_49
VCCIN_50
VCCIN_51

VIDALERT
VIDSCK
VIDSOUT

ICELAKE-U_BGA1526

12 of 19

@

VCCIN_52
VCCIN_53
VCCIN_54
VCCIN_55
VCCIN_56
VCCIN_57
VCCIN_58
VCCIN_59
VCCIN_60
VCCIN_61
VCCIN_62
VCCIN_63
VCCIN_64
VCCIN_65
VCCIN_66
VCCIN_67
VCCIN_68
VCCIN_69
VCCIN_70
VCCIN_71
VCCIN_72
VCCIN_73
VCCIN_74
VCCIN_75
VCCIN_76
VCCIN_77
VCCIN_78
VCCIN_79
VCCIN_80
VCCIN_81
VCCIN_82
VCCIN_83
VCCIN_84
VCCIN_85
VCCIN_86
VCCIN_87
VCCIN_88
VCCIN_89
VCCIN_90
VCCIN_91
VCCIN_92
VCCIN_93
VCCIN_94
VCCIN_95
VCCIN_96
VCCIN_97
VCCIN_98

VCCIN_99
VCCIN_100
VCCIN_101
VCCIN_102
VCCIN_103
VCCIN_104

VCCIN_SENSE
VSSIN_SENSE

CJ35
CK10
J32
CL34
CL35
CN34
CN35
CP33
CR34
A29
CR35
CT33
CT34
CT35
CU33
D19
D21
D23
D24
D27
AA12
D29
F19
F21
F23
F24
F27
F29
G1
G19
G23
AB1
G27
G29
H19
H23
H27
H29
J18
J20
J22
J23
AB13
J26
J28
K17
K19
K21
K23
K24
K27
M1
U1

F17
G17

4

+VCCIN

+VCCST_CPU

CAD NOTE:
Alert signal must be routed between Clk and Data signals
to minimize Cross-Talk.

12

RC1204

1/20W_100_1%_0201

12

RC1205

1/20W_100_1%_0201

1 2

RC1201 100_0402_1%

1 2

RC1202 56_0402_5%

1 2

RC1203 1/16W_45.3_1%_0402@

VCCIN_SENSE 56
VSSIN_SENSE 56

VR_SVID_DAT
VR_SVID_ALRT#
VR_SVID_CLK

3

+1.2V +1.2V

AA37

VDDQ_1

AG36

VDDQ_2

AJ36

VDDQ_3

AL36

VDDQ_4

AL49

VDDQ_5

AN36

VDDQ_6

AP37

VDDQ_7

AR36

VDDQ_8

AR37

VDDQ_9

AT36

VDDQ_10

AT49

VDDQ_11

AA49

VDDQ_12

AV36

VDDQ_13

AW37

VDDQ_14

AY36

VDDQ_15

BA37

VDDQ_16

BA49

VDDQ_17

BB36

VDDQ_18

BD36

VDDQ_19

BE37

VDDQ_20

BF36

VDDQ_21

BF37

VDDQ_22

AB36

VDDQ_23

BF49

VDDQ_24

BG36

VDDQ_25

BJ36

VDDQ_26

BL37

VDDQ_27

BM49

VDDQ_28

BN37

VDDQ_29

BP38

+VCCST_CPU

+VCCSTG_CPU +VCCSTG_OUT_R

+VCCSTG_OUT

+VCCSTG_OUT_LGC

0.605A

0.119A

INTERNAL RAIL.

INTERNAL RAIL.

VDDQ_30

CB1

VCCST

BY1

VCCSTG

F33

VCCSTG_OUT_1

G33

VCCSTG_OUT_2

E5

VCCSTG_OUT_LGC

@

UC1M

ICELAKE-U_BGA1526

13 of 19

2

VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44
VDDQ_45
VDDQ_46
VDDQ_47

RSVD_77

RSVD_2
RSVD_3

VCC1P8A_1
VCC1P8A_2
VCC1P8A_3
VCC1P8A_4
VCC1P8A_5

VCCSTG_OUT_3
VCCSTG_OUT_4
VCCSTG_OUT_5
VCCSTG_OUT_6
VCCSTG_OUT_7

RSVD_74
RSVD_75
RSVD_76

VCCPLL_1

VCCPLL_OC_1
VCCPLL_OC_2
VCCPLL_OC_3
VCCPLL_OC_4

VCCIO_OUT

BP39
BR37
BT38
AC35
BU37
BU49
CA39
CB49
L38
L49
N36
T49
AC37
AD35
AD36
AE36
AF49

C33
A33

B33
BG9

BJ9
BM9
BW1
BW2

R35
V34
T34
U35
AB34
W35
AA35
Y34

CD2
CG38

CG41
CG42
CG49

AD7

INTERNAL RAIL.

0.7A

+VCC1P8A

+VCC1.05_OUT_SFR

+VCCSFR_OC
+VCCIO_OUT

1

0.09A

0.16A

+VCCST_CPU

+1.8VALW_PCH +VCC1P8A

RC1208

1 2

1/2W_0.01_+-1%_0603_50PPM/C

NPI@

B B

+1.2V +VCCSFR_OC

RC1207

12

1/16W_0.01_1%_0402

NPI@

+VCCSTG_OUT

RC1210

1 2

1/2W_0.01_+-1%_0603_50PPM/C

NPI@

A A

10U 6.3V M X5R 0402

CC1204

1

2

0.16A

CC1216

1

2

+VCCSTG_OUT_R

CC1211

1

2

0.7A

22UC_6.3VC_MC_X5RC_0603

0.1U_6.3V_K_X5R_0201

CC1205

CC1206

1

1

VCC1P8A
1x10uF 0402 close toBGA
1x0603(hold)

2

If VCCST is enabled by SLP_S4#,
no power gate is required for
VCCPLL_OC and it can
be merged with VDDQ directly.

1U_6.3V_M_X5R_0201

VCCPLL_OC:
1x1uF 0402 Close SOC
1x0402 (holder

W>1.8mm

）

2

@

1U_6.3V_M_X5R_0201

CC1217

1

2

@

1U_6.3V_M_X5R_0201

5

4

+VCCSTG_OUT_LGC +VCCSTG_TERM

RC1206

1 2

1/2W_0.01_+-1%_0603_50PPM/C

NPI@

3

+VCCSTG_CPU

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CC1213

1

2

@

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CC1215

1

2

@

VCCST:
1x1uF 0402 Close SOC
1x0402 (holder

VCCSTG:
1x1uF 0402 Close SOC
1x0402 (holder

2018/08/20

2018/08/20

2018/08/20

）

）

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

1

12 60

12 60

12 60

0.1

0.1

0.1

CC1212

1

2

CC1214

1

2

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

4

3

2

1

NPI@

+1.8VALW_PCH

+VCCPDSW_3P3

4mA

1U_6.3V_M_X5R_0201

CC1301

1

2

+VCCPRIM_3P3

1U_6.3V_M_X5R_0201

CC1302

1

2

+V3.3A_1.8A_PCH_SPI

1U_6.3V_M_X5R_0201

CC1304

1

2

+VCCPRIM_1P8

1U_6.3V_M_X5R_0201

CC1308

1

2

+VCCPGPPR_3P3_1P8

1U_6.3V_M_X5R_0201

CC1306

1

2

202mA

0.1U_6.3V_K_X5R_0201

CC1303

1

2

3mASPI

0.1U_6.3V_K_X5R_0201

CC1305

1

2

1.3A

1U_6.3V_M_X5R_0201

CC1309

1

1

2

2

5mA

VCCPGPPR:Audio Power:

0.1U_6.3V_K_X5R_0201

CC1307

1

2

VCCDSW_3P3:
1x0402(holder）DE31

VCCPRIM_3P3:
1x0402(holder）DG26
1x0402(holder）DF23

1U_6.3V_M_X5R_0201

VCCPRIM_1P8:

CC1310

1x0402(holder）DG20

+1.8VALW

+VCCIN_AUX

D D

+VCCIN_AUX

12

RC1304

100_0402_1%

RC1306

100_0402_1%

VCCIN_AUX_VCCSENSE
VCCIN_AUX_VSSSENSE

12

+V1.05A_BYPASS

+VNN_BYPASS
+VCCPRIM_3P3
+VCCPRIM_1P8

+V3.3A_1.8A_PCH_SPI

1.05V

1.05V / 0.76V

VCCIN_AUX_VCCSENSE55
VCCIN_AUX_VSSSENSE55

C C

B B

AH1

AW10

AY11

AY9

BA10

BB9

CH1
CK11
CL10
CM11

CN1

AJ1
CN10
CP11
CR10
CT11
CU10

CV1

CV11

CW10

CY11

DC1
AL1
P13
R12

T13

U12
DC11
DE12
DF12

AM1

AN1
AT11

AT9
AU10

AV9

BF9

BD9

0.2A

DJ15

0.2A

CY34
DC33
DD35
DB34

UC1N

VCCIN_AUX_1
VCCIN_AUX_2
VCCIN_AUX_3
VCCIN_AUX_4
VCCIN_AUX_5
VCCIN_AUX_6
VCCIN_AUX_7
VCCIN_AUX_8
VCCIN_AUX_9
VCCIN_AUX_10
VCCIN_AUX_11
VCCIN_AUX_12
VCCIN_AUX_13
VCCIN_AUX_14
VCCIN_AUX_15
VCCIN_AUX_16
VCCIN_AUX_17
VCCIN_AUX_18
VCCIN_AUX_19
VCCIN_AUX_20
VCCIN_AUX_21
VCCIN_AUX_22
VCCIN_AUX_23
VCCIN_AUX_24
VCCIN_AUX_25
VCCIN_AUX_26
VCCIN_AUX_27
VCCIN_AUX_28
VCCIN_AUX_29
VCCIN_AUX_30
VCCIN_AUX_31
VCCIN_AUX_32
VCCIN_AUX_33
VCCIN_AUX_34
VCCIN_AUX_35
VCCIN_AUX_36

VCCIN_AUX_VCCSENSE
VCCIN_AUX_VSSSENSE

VCC_V1P05EXT_1P05
VCC_VNNEXT_1P05
VCCPRIM_3P3_1
VCCPRIM_1P8_1
VCCSPI

ICELAKE-U_BGA1526

@

14 of 19

VCCPRIM_3P3_2
VCCPRIM_3P3_3
VCCPRIM_3P3_4

VCCPRIM_1P8_2
VCCPRIM_1P8_3
VCCPRIM_1P8_4
VCCPRIM_1P8_5
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCPRIM_1P8_8
VCCPRIM_1P8_9

VCCLDOSTD_0P85

VCCA_CLKLDO_1P8

VCCDPHY_1P24

VCCDSW_1P05

VCCPRIM_1P05_1
VCCPRIM_1P05_2
VCCPRIM_1P05_3
VCCPRIM_1P05_4

VCCDSW_3P3

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
GPP_B2/VRALERT_N

H_PROCHOT#6,44,55

VCC1P05_1
VCC1P05_2
VCC1P05_3

VCCPLL_2

VCCRTC

VCCPGPPR

DF23
DG26
DG28

DF15
DF17
DF18
DF20
DG17
DG18
DG20
DF34

DW37
DW15
DW32
DD34
BY2

CB2
CC1

CD1
DG31
DG29
DF29
DF31
DG33
DE31
DF26
CL38

CJ38
CN38

+VCCPRIM_3P3

+VCCPRIM_1P8

INTERNAL RAIL.

0.165A

INTERNAL RAIL.

INTERNAL RAIL.

INTERNAL RAIL.

VCCIN_AUX_VID0
VCCIN_AUX_VID1
GPPC_B2_VRALERT_N

DC1301

2

211

RB521CM-30T2R_VMN2M-2

@

1 2

RC1314 0_0402_5%@

+VCCLDOSTD_OUT_0P85
+VCCA_CLKLDO_1P8
+VCCDPHY_1P24
+VCCDSW_1P05

+VCC1.05_OUT_FET
+VCC1.05_OUT_SFR

+VCC1.05_OUT_PCH
VCCRTC
+VCCPDSW_3P3
+VCCPGPPR_3P3_1P8

VCCIN_AUX_VID0 55
VCCIN_AUX_VID1 55

+3VALW_PCH

12

RC1312
20K_0201_5%

GPPC_B2_VRALERT_N

FET TO VCCST_CPU & VCCSTG_CPU

SHORT TO CPU SIDE VCCPLL.

VCCPRIM_1P05 is internal supply rail.
Do not connect to external supply
Merge the pins together.

VID[1]

VCCIN_AUXVID[0]

0

0 0
1

0

1.1

1

0

1.65

1

1 1.8

+3VALW_PCH

+3VALW_PCH

+3VALW_PCH

+1.8VALW_PCH

+1.8VALW_PCH

RC1301

1 2

1/2W_0.01_+-1%_0603_50PPM/C

RC1302

1 2

1/16W_0.01_1%_0402

NPI@

RC1303

1 2

1/16W_0.01_1%_0402

NPI@

RC1305

1 2

1/16W_0.01_1%_0402

NPI@

RC1308

1 2

1/2W_0.01_+-1%_0603_50PPM/C

NPI@

RC1307

1 2

1/16W_0.01_1%_0402

NPI@

VCCRTC

1U_6.3V_M_X5R_0201

CC1316

1

2

A A

VCCRTC:
1x0.1uF 0402 DG33
1x1uF 0402

1

2

0.1U_6.3V_K_X5R_0201

CC1317

+VCC1.05_OUT_SFR

1U_6.3V_M_X5R_0201

CC1218

1

1

2

2

VCCPLL:
1x1uF 0402 SOC
1x0402 (holder

1U_6.3V_M_X5R_0201

CC1219

@

VCCDSW_1P05:
1x1uF 0402 DD34

）

1U_6.3V_M_X5R_0201

CC1312

1

2

VCCDSW_1P05:
1x4.7uF 0402
edge w/i3 mm

5

+VCCLDOSTD_OUT_0P85+VCCDSW_1P05 +VCCDPHY_1P24 +V1.05A_BYPASS +VNN_BYPASS

100K_0201_5%

12

1

2

CC1313

4.7U_0402_6.3V6M

4

CC1311

2.2U_0402_6.3V6M

1

2

VCCLDOSTD_0P85
1x2.2uF 0402
edge w/i 3 mm

RC1309

@

For volume segment platform this rail is disabled.
Keep the pin floating (do not short this pin to
ground).

1K_0402_5%

12

RC1311

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

+VCCPRIM_1P8

Deciphered Date

Deciphered Date

Deciphered Date

2

NPI@

1 2

RC1310 1/2W_0.01_+-1%_0603_50PPM/C

LC1301

1 2

0.6UH_HBLE041B-R60MSA_7.65A_20%

@

2018/08/20

2018/08/20

2018/08/20

+VCCA_CLKLDO_1P8

12

1

2

Title

Title

Title

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

0.165A

0_0402_5%

RC1313

47U_6.3V_M_X5R_0805_H1.25

CC1314

1

2

S740-ICL

S740-ICL

S740-ICL

VCCA_CLKLDO_1P8:
By Default: 47uF 0603 is stuffed
with a 0 Ohm resistor; Inductor is
placeholder; 100mOhm Resistor is
stuffed only when Inductor is
stuffed.
Place the component near to package
pin
DW15 right after signal breakout.
It is recommended to have GND

1U_6.3V_M_X5R_0201

shield around the VCC trace

CC1315

routing, and minimum of 4nH of loop
inductance from BGA to LC filter

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

1

13 60

13 60

13 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

+1.2V

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CC1414

CC1405

1

D D

1

2

2

10U 6.3V M X5R 0402

CC1415

CC1406

1

1

2

2

4

VDDQ:
6x1uF 0402 Back ,Outer row
2x10uF 0402 back Outer row
3x0402 (holder）back Outer row
2x22uF 0603 (SODIMM need)
1x0603(holder)

3

2

1

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CC1402

1

2

@

C C

B B

1U_6.3V_M_X5R_0201

CC1432

1

2

1U_6.3V_M_X5R_0201

CC1426

1

2

@

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CC1413

CC1401

1

1

2

2

@

@

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CC1434

CC1409

1

1

2

2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CC1428

CC1429

1

1

2

2

@

@

+VCCIN +VCCIN_AUX

CC1435

100P_0402_50V8J

1

1

2

2

EMC_NS@

10U 6.3V M X5R 0402

CC1418

CC1419

1

1

2

2

@

@

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CC1424

CC1411

1

1

2

2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CC1410

CC1430

1

1

2

2

@

@

0.1U_6.3V_K_X5R_0201

CC1436

12P_50V_F_COG_ 0402

CC1437

1

2

EMC_NS@

EMC_NS@

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CC1421

CC1404

1

1

2

2

@

@

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CC1407

CC1425

1

1

2

2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CC1408

CC1433

1

1

2

2

@

@

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CC1422

1

2

@

1U_6.3V_M_X5R_0201

CC1412

1

2

@

CC1438

100P_0402_50V8J

1

2

EMC_NS@

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CC1403

CC1420

1

2

@

1U_6.3V_M_X5R_0201

CC1431

1

2

@

CC1439

12P_50V_F_COG_ 0402

1

2

EMC_NS@

CC1416

1

1

2

2

@

@

1U_6.3V_M_X5R_0201

CC1427

1

2

@

10U 6.3V M X5R 0402

CC1417

CC1423

1

1

2

2

@

@

EMC CAPS refer CRB EMC CAPS refer CRB

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

1

14 60

14 60

14 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

4

3

2

1

UC1O

A11

VSS_1

D D

C C

B B

A46

VSS_2

BA45

VSS_3

BA47

VSS_4

BB11

VSS_5

BB3

VSS_6

BB7

VSS_7

BC37

VSS_8

BD3

VSS_9

BD38

VSS_10

BD39

VSS_11

BD41

VSS_12

A48

VSS_13

BD42

VSS_14

BD43

VSS_15

BD45

VSS_16

BD49

VSS_17

BD5

VSS_18

BD6

VSS_19

BD7

VSS_20

BE1

VSS_21

BE2

VSS_22

BF3

VSS_23

A49

VSS_24

BF45

VSS_25

BF47

VSS_26

BF7

VSS_27

BG3

VSS_28

BG41

VSS_29

BG7

VSS_30

BH37

VSS_31

BJ1

VSS_32

BJ2

VSS_33

BJ3

VSS_34

AA45

VSS_35

BJ41

VSS_36

BJ43

VSS_37

BJ45

VSS_38

BJ49

VSS_39

BJ7

VSS_40

BM11

VSS_41

BM3

VSS_42

BM45

VSS_43

BM47

VSS_44

BM5

VSS_45

AA47

VSS_46

BM6

VSS_47

BM7

VSS_48

BP1

VSS_49

BP2

VSS_50

BP3

VSS_51

BP43

VSS_52

BP7

VSS_53

BR45

VSS_54

BR49

VSS_55

AB11

VSS_56

AB3

VSS_57

AB38

VSS_58

AB39

VSS_59

AB41

VSS_60

A17

VSS_61

AB42

VSS_62

AB43

VSS_63

AB5

VSS_64

AB6

VSS_65

AC45

VSS_66

AC49

VSS_67

AD10

VSS_68

AD11

VSS_69

AD34

VSS_70

AD37

VSS_71

A3

VSS_72

AE6

VSS_73

AF37

VSS_74

15 of 19

ICELAKE-U_BGA1526

@

VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148

AF45
AF47
AG1
AG11
AG3
AG38
AG39
AG41
A31
AG42
AG43
AG5
AG9
AH2
AH37
AH45
AH49
AJ2
AJ3
A34
AK37
AL2
AL45
AL47
AL6
AM2
AM37
AN2
AN38
AN39
A36
AN41
AN42
AN43
AN45
AN49
AN6
AR1
AR11
AR2
AR3
A39
AR7
AR9
AT3
AT45
AT47
AT5
AT6
AT7
AU37
AV11
A42
AV3
AV38
AV39
AV41
AV42
AV43
AV45
AV49
AV7
AY3
A44
AY7
B17
B2
B21
B24
B3
B31
B48
BA1
BA2

BT3
BT39
BT41
BT42
BT43

BT7
BU45
BU47

BV1

BV11

BV2
BV3
BV7
BW3

BW37

BW5
BW6

BW7
BY37
BY45
BY49

C11
C13
C14
C17
C21
C24
C31
C34
C39
C48
C49

C6

CA3
CA38
CA41
CA42
CA43

CA7
CB37
CB45
CB47

CC3

CC7
CE37
CE45
CE49

CE9

CG37
CG39
CG43
CG45
CG47

CG9

CH3

CH5
CJ37
CJ42

CJ9
CK45
CK49

CK9
CL37
CL42
CL49

CM45
CM47

CM9

CN3
CN37
CN39

CN5

CP9
CR32

ICELAKE-U_BGA1526

UC1P

VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222

16 of 19

@

VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296

CR37
CR45
CR49
CT37
CT39
CT42
CT9
CU45
CU47
CU49
CV3
CV34
CV35
CV5
CV9
CY41
CY45
CY49
CY9
D13
D17
D31
D44
D49
DA10
DA33
DA9
DB32
DB35
DB38
DB45
DB47
DB49
DC3
DC49
DC5
DC6
DD37
DD42
DE10
DE13
DE17
DE18
DE20
DE22
DE23
DE26
DE28
DE29
DE33
DE45
DE6
DF13
DF22
DF28
DF33
DF35
DF39
DG10
DG12
DG13
DG15
DG22
DG23
DG47
DG6
DH1
DH3
DH45
DH5
DJ19
DJ21
DJ27
DJ31

DJ33
DJ36
DJ42

DK3
DK4

DK49

DK6

DK8
DL10
DL13
DL44
DL47

DM47

DN15
DN19
DN24
DN31
DN36
DN42
DP45
DR49

DT1
DT10
DT15
DT20
DT27

DT3
DT32
DT37
DT42
DT49

DT6

DT7

DT8

DU1
DU10
DU15

DU2
DU20
DU27
DU32
DU37
DU48
DU49

DU7

DV2
DV44
DV48

DV8

DW1

DW10

DW2
DW20
DW27
DW44
DW46
DW48
DW49

DW7

E11
E34
E36
E39
E42

E6

ICELAKE-U_BGA1526

UC1Q

VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361

17 of 19

F11

VSS_362

F31

VSS_363

F45

VSS_364

F47

VSS_365

F8

VSS_366

G21

VSS_367

G24

VSS_368

G3

VSS_369

G31

VSS_370

G36

VSS_371

G49

VSS_372

G5

VSS_373

H17

VSS_374

H21

VSS_375

H24

VSS_376

H31

VSS_377

H33

VSS_378

H36

VSS_379

H45

VSS_380

H49

VSS_381

J10

VSS_382

J13

VSS_383

J16

VSS_384

J36

VSS_385

J6

VSS_386

K11

VSS_387

K33

VSS_388

K8

VSS_389

L36

VSS_390

L39

VSS_391

L41

VSS_392

L42

VSS_393

L43

VSS_394

L45

VSS_395

L47

VSS_396

M10

VSS_397

M3

VSS_398

M36

VSS_399

M5

VSS_400

N45

VSS_401

N49

VSS_402

P11

VSS_403

P41

VSS_404

P8

VSS_405

R3

VSS_406

R37

VSS_407

T11

VSS_408

T36

VSS_409

T41

VSS_410

T43

VSS_411

T45

VSS_412

T47

VSS_413

U3

VSS_414

U37

VSS_415

U5

VSS_416

V11

VSS_417

V36

VSS_418

V45

VSS_419

V49

VSS_420

V9

VSS_421

W37

VSS_422

Y36

VSS_423

Y38

VSS_424

Y43

VSS_425

Y9

VSS_426

DE15

VSS_427

@

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

1

15 60

15 60

15 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

4

3

2

1

PROCESSOR CFG STRAPS

+VCCIO_OUT

1 2

UC1R

N34

RSVD_TP_27

AK10

RSVD_TP_28

BT36

RSVD_7

TP_M34

CFG0
CFG1

CFG4

CFG8
CFG9
CFG10

CFG12
CFG13

CFG16

CFG18

AH10
BC10
CH33

CJ32
AM10
BH10

CG32

CK33
BP41
AL11
BG11
AN11

DU42

DW42

J34
Y11

L34

AJ11

M13
M34

D33
L13
K13

AG6
AE7
AG7
AD9
AE9
AB9
AJ6
AB7
V10
AJ5
Y10
AJ7

AB10

AL7
AL9
AJ9

V6
V7

Y6
Y7

AD6

T9
T7

T10

T6

BJ11
BL10

AV1
AT2

AT1
AU1
AU2

AV2
DP3

DT2

AR10
AP10
BP36
BM36

J15

K15

C5
D4
A5

RSVD_TP_29
RSVD_TP_30
RSVD_TP_31

RSVD_12
RSVD_TP_32
RSVD_TP_33
RSVD_TP_34

RSVD_9
RSVD_10

RSVD_17
RSVD_21

RSVD_22
RSVD_20
RSVD_23
RSVD_24
RSVD_16
RSVD_18
RSVD_19

RSVD_42
RSVD_43
RSVD_44
RSVD_45
RSVD_47

ICELAKE-U_BGA1526

@

UC1S

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

CFG_16
CFG_17

CFG_18
CFG_19

CFG_RCOMP
BPM_N_0

BPM_N_1
BPM_N_2
BPM_N_3

RSVD_62
RSVD_63

RSVD_TP_17
RSVD_TP_18

RSVD_TP_20
RSVD_TP_19
RSVD_TP_21

RSVD_TP_22
RSVD_67

RSVD_68
RSVD_69

RSVD_71
RSVD_70
RSVD_72

VSS_430
VSS_431

SKTOCC_N
RSVD_78
RSVD_64

ICELAKE-U_BGA1526

@

18 of 19

19 of 19

D D

1

TP1608Test_Point_12MIL

C C

1

TP1611Test_Point_12MIL

1

TP1613Test_Point_12MIL

1

TP1615Test_Point_12MIL

TP1617Test_Point_12MIL
TP1618Test_Point_12MIL
TP1619Test_Point_12MIL
TP1620Test_Point_12MIL

TP1621Test_Point_12MIL

TP1622

Test_Point_12MIL

12

1
1
1
1

1

1

B B

RC1603 1/20W_49.9_1%_0201

A A

RSVD_TP_35
RSVD_TP_36
RSVD_TP_37

RSVD_32
RSVD_33
RSVD_34

IST_TP_0

IST_TP_1
IST_TRIG_0
IST_TRIG_1

PCH_IST_TP_0
PCH_IST_TP_1

RSVD_27

RSVD_28

RSVD_35

RSVD_46

RSVD_48

RSVD_49

RSVD_50

RSVD_51

RSVD_52

RSVD_53

RSVD_54

RSVD_36

RSVD_37

RSVD_38

RSVD_39

RSVD_40

RSVD_41

RSVD_TP_1

RSVD_TP_2

RSVD_57
RSVD_58

RSVD_TP_10
RSVD_TP_11

RSVD_79
RSVD_80

RSVD_TP_5

RSVD_TP_6

VSS_428
VSS_429

RSVD_55
RSVD_56

RSVD_65
RSVD_66

RSVD_59
RSVD_60

RSVD_TP_13
RSVD_TP_14

RSVD_TP_24
RSVD_TP_25

RSVD_TP_15
RSVD_TP_16

RSVD_TP_12

RSVD_TP_7

RSVD_TP_8

RSVD_TP_9

RSVD_TP_23

VSS_432

RSVD_TP_26

TP_3
TP_4

TP_1
TP_2

DA11
CL32
CN32
CY35
DB37
DF37

BF11
BD11
BE10
BF10

CW33
CY32

CY37
CV37

G34
H34
DJ34
DK31
DK15
CP3
CP5
AN9
AN7
AF10
AE11
H5
D1
DJ40
DK40

A47
B47

C1
E1

CT32
CV32

G15
F15

BW11
CA11

C16
A16

C2
A4

DP5
DR5

D14
E16

DV6
DW6

DP2
DP1

DW4
DV4

CM33
DB10

R1
DW3

DV3
DH49
DL8
DW47

DV47
DU47

P10

IST_TP_0
IST_TP_1
IST_TRIG_0
IST_TRIG_1

PCH_IST_TP_0
PCH_IST_TP_1

1

TP1601Test_Point_12MIL

1

TP1602Test_Point_12MIL

1

TP1603Test_Point_12MIL

1

TP1604Test_Point_12MIL

1

TP1605Test_Point_12MIL

1

TP1607Test_Point_12MIL

Stall reset sequence after PCU
PLL lock until de-asserted

CFG0

Embedded Display Port Presence Strap

CFG4

RC1606 1K_0201_5%

CFG0

RC1601 1K_0201_5%@

1:Normal(Default)
0:Stall

CFG1

RC1607 1K_0201_5%

CFG8

RC1608 1K_0201_5%

CFG9

RC1609 1K_0201_5%

CFG10

RC1610 1K_0201_5%

CFG12

RC1611 1K_0201_5%

CFG13

RC1612 1K_0201_5%

CFG4

RC1602 1K_0402_5%

1:Disable
0:Enable(Default)

CFG16

RC1604 51_0402_5%

CFG18

RC1605 51_0402_5%

1 2

1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2
1 2

*

+VCCIO_OUT

*

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2018/12/04

2018/12/04

2018/12/04

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/08/20

2018/08/20

2018/08/20

Title

Title

Title

S740-ICL

S740-ICL

S740-ICL

Size Document Name Rev

Size Document Name Rev

Size Document Name Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

1

16 60

16 60

16 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

DDR4 Memory Down

@

DDRB_DM1
DDRB_DM0

UD1701

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

MT40A1G16HBA-083E-A_FBGA96

@

UD1703

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

MT40A1G16HBA-083E-A_FBGA96

VDD10
VDDQ1

VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VREFCA

LDQ0
LDQ1
LDQ2
LDQ3
LDQ4
LDQ5
LDQ6
LDQ7
UDQ0
UDQ1
UDQ2
UDQ3
UDQ4
UDQ5
UDQ6
UDQ7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS8

VSS7

VDDQ10

VREFCA

BG1
UZQ

LZQ

LDQ0
LDQ1
LDQ2
LDQ3
LDQ4
LDQ5
LDQ6
LDQ7
UDQ0
UDQ1
UDQ2
UDQ3
UDQ4
UDQ5
UDQ6
UDQ7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDD10
VDDQ1

VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS8

VSS7

BG1
UZQ

LZQ

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1
E1

K1
N1
T1
B2
G8
K9

T7

RD1761 0_0402_5%

M9
E9

F9

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1
E1

K1
N1
T1
B2
G8
K9

1 2

T7

RD1750 0_0402_5%

DDRB_BG1_R

M9

UD1_DDRB_UZQ

E9
F9

12

DDRB_DQ36
DDRB_DQ38
DDRB_DQ34
DDRB_DQ35
DDRB_DQ32
DDRB_DQ39
DDRB_DQ33
DDRB_DQ37
DDRB_DQ49
DDRB_DQ51
DDRB_DQ50
DDRB_DQ55
DDRB_DQ52
DDRB_DQ54
DDRB_DQ48
DDRB_DQ53

DDP@

1 2

DDRB_BG1_R
UD3_DDRB_UZQ

12

RD1763
240_0402_1%

MD@

DDRB_DQ11
DDRB_DQ8
DDRB_DQ14
DDRB_DQ15
DDRB_DQ9
DDRB_DQ10
DDRB_DQ12
DDRB_DQ13
DDRB_DQ4
DDRB_DQ6
DDRB_DQ1
DDRB_DQ3
DDRB_DQ0
DDRB_DQ7
DDRB_DQ2
DDRB_DQ5

+VREF_CA_MD

DDP@

RD1753
240_0402_1%

MD@

+1.2V

+VREF_CA_MD

1

2

CD1748

MD@

.047U_0402_16V7K

CD1705

1

MD@

2

DDRB_DQ[0..63]
DDRB_DQS#[0..7]
DDRB_DQS[0..7]

.047U_0402_16V7K

CD1706

1

2

@

0.1U_6.3V_K_X5R_0201

CD1750

1

2

@

0.1U_6.3V_K_X5R_0201

Byte 4

Byte 6

1

2

DDRB_MA05
DDRB_MA15
DDRB_MA25
DDRB_MA35
DDRB_MA45
DDRB_MA55

D D

C C

B B

A A

DDRB_MA65
DDRB_MA75
DDRB_MA85
DDRB_MA95
DDRB_MA105
DDRB_MA115
DDRB_MA125
DDRB_MA135

DDRB_MA14_WE#5
DDRB_MA15_CAS#5
DDRB_MA16_RAS#5

DDRB_CLK0#5
DDRB_CLK05

DDRB_CKE05

+1.2V +1.2V

DDRB_BS0#5
DDRB_BS1#5

DDRB_ACT#5
DDRB_CS0#5
DDRB_ALERT#5

DDRB_BG05
DDRB_ODT05
DDRB_PAR5

1 2

RD1745 10K_0402_5%MD@

CPU_DRAMRST#5,18

+1.2V

RD1755 0_0402_5% @
RD1756 0_0402_5% @

RD1759 10K_0402_5%MD@

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13

DDRB_MA14_WE#
DDRB_MA15_CAS#
DDRB_MA16_RAS#

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0
DDRB_DQS#1

DDRB_DQS1
DDRB_DQS#0
DDRB_DQS0

1 2

RD1732 0_0402_5%@

1 2

RD1735 0_0402_5%@

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13

DDRB_MA14_WE#
DDRB_MA15_CAS#
DDRB_MA16_RAS#

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0
DDRB_DQS#4

DDRB_DQS4
DDRB_DQS#6
DDRB_DQS6

1 2
1 2

DDRB_BS0#
DDRB_BS1#

DDRB_ACT#
DDRB_CS0#
DDRB_ALERT#

DDRB_BG0
DDRB_ODT0
DDRB_PAR

1 2

CPU_DRAMRST#

DDRB_BS0#
DDRB_BS1#

DDRB_ACT#
DDRB_CS0#
DDRB_ALERT#

DDRB_BG0
DDRB_ODT0
DDRB_PAR
TEN_UD1 TEN_UD2
CPU_DRAMRST#

DDRB_DM4
DDRB_DM5 DDRB_DM6

TEN_UD3

4

@

DDRB_DM2
DDRB_DM3

UD1702

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

MT40A1G16HBA-083E-A_FBGA96

@

UD1704

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC_N

T8

A13

L2

WE_N/A14

M8

CAS_N/A15

L8

RAS_N/A16

K8

CK_C

K7

CK_T

K2

CKE

F3

LDQS_C

G3

LDQS_T

A7

UDQS_C

B7

UDQS_T

E2

NF/UDM_N/UDBI_N

E7

NF/LDM_N/LDBI_N

N2

BA0

N8

BA1

L3

ACT_N

L7

CS_N

P9

ALERT_N

M2

BG0

K3

ODT

T3

PAR

N9

TEN

P1

RESET_N

F1

VSSQ1

H1

VSSQ2

A2

VSSQ3

D2

VSSQ4

E3

VSSQ5

A8

VSSQ6

D8

VSSQ7

E8

VSSQ8

C9

VSSQ9

H9

VSSQ10

MT40A1G16HBA-083E-A_FBGA96

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3

Byte 1

Byte 0 Byte 5

DDRB_DQ[0..63] 5
DDRB_DQS#[0..7] 5
DDRB_DQS[0..7] 5

+2.5V_DDR

CD1704

1U_6.3V_M_X5R_0201

CD1703

1U_6.3V_M_X5R_0201

1

1

2

+2.5V_DDR

CD1747

MD@

MD@

MD@

2

1U_6.3V_M_X5R_0201

CD1749

1U_6.3V_M_X5R_0201

1

2

MD@

RD1747 10K_0402_5%MD@

+1.2V

RD1757 0_0402_5% @
RD1758 0_0402_5% @1 2

RD1760 10K_0402_5%MD@1 2

DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13

DDRB_MA14_WE#
DDRB_MA15_CAS#
DDRB_MA16_RAS#

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0

1 2

RD1733 0_0402_5% @

1 2

RD1736 0_0402_5% @

1 2

CPU_DRAMRST#

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13

DDRB_MA14_WE#
DDRB_MA15_CAS#
DDRB_MA16_RAS#

DDRB_CLK0#
DDRB_CLK0

DDRB_CKE0
DDRB_DQS#2

DDRB_DQS2
DDRB_DQS#3
DDRB_DQS3

1 2

DDRB_DQS#7
DDRB_DQS7
DDRB_DQS#5
DDRB_DQS5

DDRB_BS0#
DDRB_BS1#

DDRB_ACT#
DDRB_CS0#
DDRB_ALERT#

DDRB_BG0
DDRB_ODT0
DDRB_PAR

DDRB_DM7
DDRB_BS0#

DDRB_BS1#
DDRB_ACT#

DDRB_CS0#
DDRB_ALERT#

DDRB_BG0
DDRB_ODT0
DDRB_PAR
TEN_UD4
CPU_DRAMRST#

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VREFCA

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDDQ10

VREFCA

VDD10

VDD10

LDQ0
LDQ1
LDQ2
LDQ3
LDQ4
LDQ5
LDQ6
LDQ7
UDQ0
UDQ1
UDQ2
UDQ3
UDQ4
UDQ5
UDQ6
UDQ7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS8

VSS7

BG1
UZQ

LZQ

LDQ0
LDQ1
LDQ2
LDQ3
LDQ4
LDQ5
LDQ6
LDQ7
UDQ0
UDQ1
UDQ2
UDQ3
UDQ4
UDQ5
UDQ6
UDQ7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VPP1
VPP2

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS8

VSS7

BG1
UZQ

LZQ

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1
E1

K1
N1
T1
B2
G8
K9

DDP@

T7

1 2

RD1751 0_0402_5%

DDRB_BG1_R

M9

UD2_DDRB_UZQ

E9
F9

12

RD1754
240_0402_1%

MD@

G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7

D1
J1
L1
R1
B3
G7
B9
J9
L9
T9

A1
C1
G1
F2
J2
F8
J8
A9
D9
G9

B1
R9

M1
E1

K1
N1
T1
B2
G8
K9

T7

1 2

RD1762 0_0402_5%

DDRB_BG1_R

M9

UD4_DDRB_UZQ

E9
F9

12

RD1764
240_0402_1%

MD@

3

DDP@

DDRB_DQ61
DDRB_DQ60
DDRB_DQ59
DDRB_DQ57
DDRB_DQ62
DDRB_DQ58
DDRB_DQ63
DDRB_DQ56
DDRB_DQ45
DDRB_DQ42
DDRB_DQ47
DDRB_DQ41
DDRB_DQ46
DDRB_DQ40
DDRB_DQ43
DDRB_DQ44

+1.2V+1.2V

DDRB_DQ18
DDRB_DQ17
DDRB_DQ23
DDRB_DQ21
DDRB_DQ19
DDRB_DQ16
DDRB_DQ20
DDRB_DQ22
DDRB_DQ26
DDRB_DQ30
DDRB_DQ31
DDRB_DQ29
DDRB_DQ28
DDRB_DQ24
DDRB_DQ27
DDRB_DQ25

+1.2V

+VREF_CA_MD

1

2

+VREF_CA_MD

Byte 7

0.1U_6.3V_K_X5R_0201

.047U_0402_16V7K

CD1710

1

CD1708

1

2

2

MD@

@

Byte 2

Byte 3

CD1753

.047U_0402_16V7K

CD1754

0.1U_6.3V_K_X5R_0201

1

1

MD@

2

2

@

@

CD1707

+2.5V_DDR

1U_6.3V_M_X5R_0201

CD1751

1

MD@

2

1

2

+2.5V_DDR

1U_6.3V_M_X5R_0201

2

RD1701 0_0201_5%

12

RD1765
0_0201_5%

SDP@

0.1U_6.3V_K_X5R_0201

1 2

2.7_0402_1%

1

CD1711

0.022U_16V_K_X7R_0402

2

MD@

12

RD1752

24.9_0402_1%

MD@

+1.2V

DDP@

1 2

RD1706 0_0402_5%
RD1709 240_0402_1%DDP@1 2

RD1711 0_0402_5%SDP@
RD1712 240_0402_1%DDP@1 2

RD1715 0_0402_5%SDP@
RD1718 240_0402_1%DDP@1 2

RD1721 0_0402_5%SDP@
RD1724 240_0402_1%DDP@1 2

CD1702

@

RD1748

DDRB_BG1

SDP@

1 2

1 2

1 2

1 2

+1.2V

1

12

RD1743

1.8K_0402_1%

2

MD@

MD@

12

RD1749

1.8K_0402_1%

MD@

VDDQ:
16x1uF 4 per DRAM
5x10uF distribute evenly across dram

DDRB_BG1 5

+VREF_CA_MD

1

CD1712

0.1U_6.3V_K_X5R_0201

@

2

DDRB_CLK0#
DDRB_CLK0

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3

DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8

DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12

DDRB_MA13
DDRB_MA14_WE#
DDRB_MA15_CAS#
DDRB_MA16_RAS#

DDRB_BG0
DDRB_BG1_R

DDRB_BS0#
DDRB_BS1#

DDRB_ACT#
DDRB_PAR

DDRB_CKE0
DDRB_CS0#
DDRB_ODT0

DDRB_ALERT#

DDRB_BG1_R

UD1_DDRB_UZQ

UD2_DDRB_UZQ

UD3_DDRB_UZQ

UD4_DDRB_UZQ

1U_6.3V_M_X5R_0201

CD1709

MD@

DDR_SB_VREFCA5

RD1704 1/20W_39_5%_0201MD@1 2

1 2

RD1705 1/20W_39_5%_0201MD@

1 2

RD1713 1/20W_39_5%_0201MD@
RD1714 1/20W_39_5%_0201MD@1 2

1 2

RD1716 1/20W_39_5%_0201MD@

1 2

RD1717 1/20W_39_5%_0201MD@

1 2

RD1719 1/20W_39_5%_0201MD@
RD1720 1/20W_39_5%_0201MD@1 2

1 2

RD1722 1/20W_39_5%_0201MD@

1 2

RD1723 1/20W_39_5%_0201MD@

1 2

RD1725 1/20W_39_5%_0201MD@
RD1726 1/20W_39_5%_0201MD@1 2

1 2

RD1727 1/20W_39_5%_0201MD@

1 2

RD1728 1/20W_39_5%_0201MD@

1 2

RD1729 1/20W_39_5%_0201MD@

1 2

RD1730 1/20W_39_5%_0201MD@

1 2

RD1731 1/20W_39_5%_0201MD@

1 2

RD1734 1/20W_39_5%_0201MD@

1 2

RD1737 1/20W_39_5%_0201MD@

1 2

RD1738 1/20W_39_5%_0201MD@

1 2

RD1739 1/20W_39_5%_0201DDP@
RD1740 1/20W_39_5%_0201MD@1 2

1 2

RD1741 1/20W_39_5%_0201MD@

1 2

RD1742 1/20W_39_5%_0201MD@

1 2

RD1744 1/20W_39_5%_0201MD@

1 2

RD1710 1/20W_39_5%_0201MD@

1 2

RD1707 1/20W_39_5%_0201MD@
RD1708 1/20W_39_5%_0201MD@1 2

1 2

RD1746 49.9_0402_1%MD@

1

RD1702

0_0402_5%

+1.2V

+0.6VS

12

2

CD1701

.01U_0402_16V7-K

MD@

@

1

+0.6VS

+1.2V

First DRAM 1x10uF 4x1uF 2nd DRAM 1x10uF 4x1uF

CD1732

10U 6.3V M X5R 0402

CD1731

4.3U_0402_4V6-M

CD1715

1U_6.3V_M_X5R_0201

CD1716

1U_6.3V_M_X5R_0201

CD1717

1U_6.3V_M_X5R_0201

CD1728

CD1729

4.3U_0402_4V6-M

CD1723

1U_6.3V_M_X5R_0201

CD1724

1U_6.3V_M_X5R_0201

CD1719

1U_6.3V_M_X5R_0201

CD1713

1U_6.3V_M_X5R_0201

1

1

34

1

MD_3T@

MD_N3T@

2

1

2

MD_N3T@

2

2

UD1701 UD1704

3rd DRAM 1x10uF 4x1uF 4th DRAM 2x10uF 4x1uF

CD1721

1U_6.3V_M_X5R_0201

CD1725

1U_6.3V_M_X5R_0201

CD1722

1U_6.3V_M_X5R_0201

1

1

MD_N3T@

2

2

@

@

1

1

1

MD@

MD_N3T@

MD_N3T@

2

2

2

CD1734

10U 6.3V M X5R 0402

CD1718

1U_6.3V_M_X5R_0201

1

1

MD_N3T@

2

2

@

1

1

34

1

MD_3T@

MD_N3T@

2

2

2

1U_6.3V_M_X5R_0201

CD1730

4.3U_0402_4V6-M
CD1720

1

1

34

1

@

MD_3T@

2

2

2

1U_6.3V _M_X5R_02 01

CD1733

10U 6.3V M X5R 0402

CD1742

1

1

@

MD_N3T@

2

2

CD1727

1U_6.3V_M_X5R_0201

CD1726

1U_6.3V_M_X5R_0201

1

1

@

MD_N3T@

2

2

22P_0402_50V8-J

1

1

MD_N3T@

MD@

2

2

@

CD1735

10U 6.3V M X5R 0402

CD1736

10U 6.3V M X5R 0402

CD1741

CD1714

1U_6.3V_M_X5R_0201

MD_N3T@

22P_0402_50V8-J

1

1

1

MD@

MD@

2

2

2

@

UD1703 UD1702

+2.5V_DDR

VPP:

CD1737

10U 6.3V M X5R 0402

8x1uF
3x10uF

1

1U_6.3V_M_X5R_0201

CD1752

1

2

@

VTT:
8x1uF
2x10uF

1

MD@

2

2

+0.6VS

CD1743

4.3U_0402_4V6-M

34

1

MD_3T@

2

CD1740

10U 6.3V M X5R 0402

CD1738

10U 6.3V M X5R 0402

CD1739

10U 6.3V M X5R 0402

CD1745

22P_0402_50V8-J

CD1746

1

1

MD@

MD@

2

2

CD1755

1U_6.3V _M_X5R_02 01

CD1744

4.3U_0402_4V6-M

1

34

1

MD_N3T@

MD_3T@

2

2

22P_0402_50V8-J

1

1

MD@

2

2

@

@

CD1759

1U_6.3V_M_X5R_0201

CD1758

1U_6.3V_M_X5R_0201

CD1756

1U_6.3V_M_X5R_0201

CD1757

1U_6.3V_M_X5R_0201

1

1

1

1

MD_N3T@

MD_N3T@

MD_N3T@

MD_N3T@

2

2

2

2

CD1762

1U_6.3V_M_X5R_0201

CD1761

1U_6.3V_M_X5R_0201

CD1760

1U_6.3V_M_X5R_0201

1

1

1

MD_N3T@

MD_N3T@

MD_N3T@

2

2

2

CD1765

22P_0402_50V8-J

CD1764

10U 6.3V M X5R 0402

CD1763

10U 6.3V M X5R 0402

CD1766

22P_0402_50V8-J

1

1

1

MD@

2

1

2

2

2

@

@

@

5

4

3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEETMAY NOT BE TRANSFEREDFROM THE CUSTODYOF THE COMPETENTDIVISION OF R&D

ANDTRADE SECRET INFORMATION. THIS SHEETMAY NOT BE TRANSFEREDFROM THE CUSTODYOF THE COMPETENTDIVISION OF R&D

ANDTRADE SECRET INFORMATION. THIS SHEETMAY NOT BE TRANSFEREDFROM THE CUSTODYOF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BYOR DISCLOSED TO ANYTHIRD PARTY WITHOUTPRIOR WRITTEN CONSENTOF LCFUTURE CENTER.

MAYBE USED BYOR DISCLOSED TO ANYTHIRD PARTY WITHOUTPRIOR WRITTEN CONSENTOF LCFUTURE CENTER.

MAYBE USED BYOR DISCLOSED TO ANYTHIRD PARTY WITHOUTPRIOR WRITTEN CONSENTOF LCFUTURE CENTER.

2

2017/06/24

2017/06/24

2017/06/24

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2018/06/23

2018/06/23

2018/06/23

Title

Title

Title

DDR4 Memory Down

DDR4 Memory Down

DDR4 Memory Down

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

1

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

17 60

17 60

17 60

0.1

0.1

0.1

www.DeviceDB.xyz

Telegram: https://t.me/DeviceDB

5

DDR4 SO-DIMM

VSS_2

DQ4

VSS_4

DQ0

VSS_6
VSS_7

DQ6

VSS_9

DQ2

VSS_11

DQ12

VSS_13

DQ8
VSS_15
DQS1_c

DQS1_t

VSS_18

DQ14

VSS_20

DQ11

VSS_22

DQ20

VSS_24

DQ16

VSS_26
VSS_27

DQ22

VSS_29

DQ18

VSS_31

DQ28

VSS_33

DQ24
VSS_35
DQS3_c

DQS3_t

VSS_38

DQ31
VSS_40

DQ27
VSS_42
CB4/NC
VSS_44
CB0/NC
VSS_46

VSS_47
CB6/NC
VSS_49
CB7/NC
VSS_51

RESET_n

CKE1

VDD_2
ACT_n

ALERT_n

VDD_4

A11

VDD_6

VDD_8

RD1806

RD1808
1K_0402_1%

+1.2V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122

A7

124
126

A5

128

A4

130

+VREF_CA_DIMM

0.1U_6.3V_K_X5R_0201

1

2

+1.2V

DDRA_DQ61
DDRA_DQ62
DDRA_DQS#7

12

RD1803

240_0402_1%

DDRA_DQS7
DDRA_DQ56
DDRA_DQ63
DDRA_DQ51
DDRA_DQ54

DDRA_DQ50
DDRA_DQ48
DDRA_DQ35
DDRA_DQ39
DDRA_DQS#4

DDRA_DQS4
DDRA_DQ33
DDRA_DQ36
DDRA_DQ44
DDRA_DQ41

DDRA_DQ46
DDRA_DQ47

DDRA_DQS#8
DDRA_DQS8

DDRA_CKE0
DDRA_BG1

DDRA_BG0
DDRA_MA12

DDRA_MA9
DDRA_MA8

DDRA_MA6

1 2

RD1807 2_0402_5%

1

CD1815

0.022U_16V_K_X7R_0402

2

12

RD1809

24.9_0402_1%

D D

+1.2V

12

RD1802

C C

B B

240_0402_1%

DDRA_CKE05
DDRA_BG15

DDRA_BG05

DDR_SA_VREFCA5

JDDR1A

1

VSS_1

3

DQ5

5

VSS_3

7

DQ1

9

VSS_5

11

DQS0_C

DM0_n/DBIO_n/NC

13

DQS0_t

15

VSS_8

17

DQ7

19

VSS_10

21

DQ3

23

VSS_12

25

DQ13

27

VSS_14

29

DQ9

31

VSS_16

33

DM1_n/DBl1_n/NC

35

VSS_17

37

DQ15

39

VSS_19

41

DQ10

43

VSS_21

45

DQ21

47

VSS_23

49

DQ17

51

VSS_25

53

DQS2_c

DM2_n/DBl2_n/NC

55

DQS2_t

57

VSS_28

59

DQ23

61

VSS_30

63

DQ19

65

VSS_32

67

DQ29

69

VSS_34

71

DQ25

73

VSS_36

75

DM3_n/DBl3_n/NC

77

VSS_37

79

DQ30

81

VSS_39

83

DQ26

85

VSS_41

87

CB5/NC

89

VSS_43

91

CB1/NC

93

VSS_45

95

DQS8_c

DM8_n/DBI8_n/NC

97

DQS8_t

99

VSS_48

101

CB2/NC

103

VSS_50

105

CB3/NC

107

VSS_52

109

CKE0

111

VDD_1

113

BG1

115

BG0

117

VDD_3

119

A12

121

A9

123

VDD_5

125

A8

127

A6

129

VDD_7

ARGOS_D4AR0-26001-1P40

ME@

0.1U_6.3V_K_X5R_0201

CD1806

1

2

+1.2V

12

1K_0402_1%

12

DDRA_DQ60
DDRA_DQ58

DDRA_DQ57
DDRA_DQ59
DDRA_DQ53
DDRA_DQ55
DDRA_DQS#6

DDRA_DQS6
DDRA_DQ49
DDRA_DQ52
DDRA_DQ37
DDRA_DQ38

DDRA_DQ32
DDRA_DQ34
DDRA_DQ40
DDRA_DQ42
DDRA_DQS#5

DDRA_DQS5
DDRA_DQ43
DDRA_DQ45

CPU_DRAMRST#
DDRA_CKE1

DDRA_ACT#
DDRA_ALERT#

DDRA_MA11
DDRA_MA7

DDRA_MA5
DDRA_MA4

CD1816

4

DDRA_DQ[0..63]
DDRA_DQS#[0..7]
DDRA_DQS[0..7]
DDRA_MA[0..13]

DDRA_CKE1 5
DDRA_ACT# 5

DDRA_ALERT# 5

VDDQ:
8x1uF
8x10uF

+1.2V

CD1803

1

2

@

DDRA_DQ[0..63] 5
DDRA_DQS#[0..7] 5
DDRA_DQS[0..7] 5

DDRA_MA[0..13] 5

0.1U_6.3V_K_X5R_0201

CPU_DRAMRST# 5,17

10U 6.3V M X5R 0402

CD1818

1

2

@

10U 6.3V M X5R 0402

CD1819

1

2

@

3

DDRA_MA14_WE#5

RD1804

1 2

+3VS

1/10W_0_+-5%_0603

+2.5V_DDR

2nd DRAM 1x10uF 4x1uF

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CD1820

1

2

10U 6.3V M X5R 0402

CD1822

CD1823

1

1

2

2

DDRA_CLK05
DDRA_CLK0#5

DDRA_PAR5

DDRA_BS1#5
DDRA_CS0#5

DDRA_ODT05
DDRA_CS1#5

DDRA_ODT15

SMB_CLK_S37

RD1805

1 2

1/10W_0_+-5%_0603

10U 6.3V M X5R 0402

CD1824

1

1

2

2

@

+1.2V

JDDR1B

DDRA_MA3
DDRA_MA1

DDRA_CLK0
DDRA_CLK0#

DDRA_PAR

DDRA_BS1#
DDRA_CS0#

DDRA_ODT0
DDRA_CS1#

DDRA_ODT1

DDRA_DQ25
DDRA_DQ24
DDRA_DQS#3

DDRA_DQS3
DDRA_DQ29
DDRA_DQ27
DDRA_DQ19
DDRA_DQ21

DDRA_DQ18
DDRA_DQ20
DDRA_DQ6 DDRA_DQ5
DDRA_DQ3
DDRA_DQS#0

DDRA_DQS0
DDRA_DQ2
DDRA_DQ1
DDRA_DQ9
DDRA_DQ12

DDRA_DQ14
DDRA_DQ15
SMB_CLK_S3

+VDD_SPD

2.2U_0402_6.3V6M

CD1804

1

1

2

2

+VPP

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

CD1817

CD1821

1

1

2

2

@

@

131

A3

133

A1

135

VDD_9

137

CK0_t

139

CK0_c

141

VDD_11

143

Parity

145

BA1

147

VDD_13

149

CS0_n

151

WE_n/A14

153

VDD_15

155

ODT0

157

CS1_n

159

VDD_17

161

ODT1

163

VDD_19

165

C1/CS3_n/NC

167

VSS_53

169

DQ37

171

VSS_55

173

DQ33

175

VSS_57

177

DQS4_c

DM4_n/DBl4_n/NC

179

DQS4_t

181

VSS_60

183

DQ38

185

VSS_62

187

DQ34

189

VSS_64

191

DQ44

193

VSS_66

195

DQ40

197

VSS_68

199

DM5_n/DBl5_n/NC

201

VSS_69

203

DQ46

205

VSS_71

207

DQ42

209

VSS_73

211

DQ52

213

VSS_75

215

DQ49

217

VSS_77

219

DQS6_c

DM6_n/DBl6_n/NC

221

DQS6_t

223

VSS_80

225

DQ55

227

VSS_82

229

DQ51

231

VSS_84

233

DQ61

235

VSS_86

237

DQ56

239

VSS_88

241

DM7_n/DBl7_n/NC

243

VSS_89

245

DQ62

247

VSS_91

249

DQ58

251

VSS_93

253

SCL

255

VDDSPD

257

0.1U_6.3V_K_X5R_0201

CD1805

4.7U_0402_6.3V6M

CD1833

259
261

4.7U_0402_6.3V6M

CD1834

1

2

@

VPP_1
VPP_2

GND_1

ARGOS_D4AR0-26001-1P40

ME@

VDDSPD:
1x2.2uF
1x0.1uF

0.1U_6.3V_K_X5R_0201
CD1836

CD1835

1

1

2

2

@

@

2

EVENT_n

RAS_n/A16
CAS_n/A15

C0/CS2_n/NC

0.1U_6.3V_K_X5R_0201

VDD_10

CK1_t

CK1_c

VDD_12

A10/AP

VDD_14

VDD_16

VDD_18

VREFCA

VSS_54

DQ36

VSS_56

DQ32

VSS_58
VSS_59

DQ39

VSS_61

DQ35

VSS_63

DQ45

VSS_65

DQ41
VSS_67
DQS5_c

DQS5_t

VSS_70

DQ47
VSS_72

DQ43
VSS_74

DQ53
VSS_76

DQ48
VSS_78

VSS_79

DQ54
VSS_81

DQ50
VSS_83

DQ60
VSS_85

DQ57
VSS_87
DQS7_c

DQS7_t

VSS_90

DQ63
VSS_92

DQ59
VSS_94

GND_2

1

2

@

BA0

A13

SA2

SDA

SA0
VTT
SA1

CD1837

132

A2

134
136
138
140
142
144

A0

146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260

262

33P_0402_50V8J

CD1838

1

2

@

+1.2V

DDRA_MA2
DDRA_EVENT#

DDRA_CLK1
DDRA_CLK1#

DDRA_MA0

DDRA_MA10
DDRA_BS0#

DDRA_MA16_RAS#DDRA_MA14_WE#
DDRA_MA15_CAS#

DDRA_MA13

+VREF_CA_DIMM
DDRA_SA2

DDRA_DQ28
DDRA_DQ26

DDRA_DQ31
DDRA_DQ30
DDRA_DQ22
DDRA_DQ23
DDRA_DQS#2

DDRA_DQS2
DDRA_DQ17
DDRA_DQ16

DDRA_DQ7

DDRA_DQ4
DDRA_DQ0
DDRA_DQ8
DDRA_DQ10
DDRA_DQS#1

DDRA_DQS1
DDRA_DQ13
DDRA_DQ11
SMB_DATA_S3

DDRA_SA0
DDRA_SA1

33P_0402_50V8J

RD1801

240_0402_1%

@

DDRA_BS0# 5
DDRA_MA16_RAS# 5

DDRA_MA15_CAS# 5

0.1U_6.3V_K_X5R_0201

CD1801

1

2

SMB_DATA_S3 7

+0.6VS

+2.5V_DDR

VPP:
1x1uF
1x10uF

+1.2V

12

DDRA_CLK1 5
DDRA_CLK1# 5

2.2U_0402_6.3V6M

CD1802

1

2

@

10U 6.3V M X5R 0402

CD1812

1

2

1

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

10U 6.3V M X5R 0402

CD1813

CD1814

CD1811

1

1

1

2

2

2

@

@

+3VS +3VS +3VS

12

RD1810
0_0402_5%

@

DDRA_SA0 DDRA_SA1 DDRA_SA2

12

RD1813

A A

0_0402_5%

12

12

RD1811
0_0402_5%

@

RD1814
0_0402_5%

12

RD1812
0_0402_5%

@

12

RD1815

0_0402_5%

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CD1825

CD1826

1

2

@

CD1828

1

1

2

2

1U_6.3V_M_X5R_0201

CD1829

CD1830

1

1

2

2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

CD1832

1

2

1U_6.3V_M_X5R_0201

CD1831

CD1827

1

1

2

2

@

@

VTT:
2x1uF
1x10uF

+0.6VS

10U 6.3V M X5R 0402

CD1809

1

2

@

1U_6.3V_M_X5R_0201

10U 6.3V M X5R 0402

CD1810

1

2

@

1U_6.3V_M_X5R_0201

CD1807

CD1808

1

1

2

2

SPD Address = A0

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2015/08/20

2015/08/20

2015/08/20

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2016/08/20

2016/08/20

2016/08/20

Title

Title

Title

DDR4 SO-DIMM

DDR4 SO-DIMM

DDR4 SO-DIMM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Tuesday, July 30, 2019

Tuesday, July 30, 2019

Tuesday, July 30, 2019

GS44D/GS54D

GS44D/GS54D

GS44D/GS54D

1

18 60

18 60

18 60

0.1

0.1

0.1