Lenovo G580,G580A,G585 Schematic

A

B

C

D

E

1

Compal Confidential

2

QIWG5/QIWG6 UMA M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point PCH

2012-05-11

2

3

A-7987P

www.rosefix.com

L

3

REV:1.0

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA-7987P

E

1 50Tuesday, October 30, 2012

of

4

1.0

A

Compal confidential

File Name : QIWG5/QIWG6

1

HDMI C

onnector

CRT

2

Connector

LVDS Connector

USB3.0 *2(Left)

Option

USB3.0

Renesas

uPD720202

3

Arthros

AR8161(GLAN)

AR8162(10/100)

RJ-45 Connector

PCI Express

Mini Card Slot *1

WLAN

4

Page24

Page23

Page22

Page34

Page26

Page27

Page25

PCI-E(WLAN)

B

PCI-E x1 *6

S

PIROM

BIOS

C

Intel

Ivy Bridge

Socket-rPGA988B

37.5mm*37.5mm

Page4-10

100MHz

2.7GT/s

FDI *8

MI *4

D

Intel

Panther Point

HM75 / HM76

FCBGA 989

25mm*25mm

Page13-21

Page13

LPC BUS

Page31

EC

ENE KB9012

Touch Pad Int. KBD

Page32

Thermal Sensor

EMC1403

Page28

DDR3 SO-DIMM *2

B

Dual Channel

DR3 1066MHz(1.5V)

D DDR3 1333MHz(1.5V) DDR3 1600MHz(1.5V)

Audio Codec

AZALIA

USB2.0 *14

ATA *6

S

Page32

Conexant

CX20671-21Z

ANK 0, 1, 2, 3

Up to 8GB

Page30

S

ATA HDD

SATA ODD

D

ZZZ1

DAZ_PCB

DAZ0N200601

15@

Page11-12

2 channel speaker

nt. MIC x1

I

Audio Jacks

Camera Conn.

BlueTooth Conn.

Mini Card Slot *1

Card Reader

Page22

Page29

Page25

Page32

Reltek

RTS5178 for SDR50 SDXC/MMC

USB2.0 *2(Right)

Page 32;33

USB2.0 *2(Left)

Page34

Page29

E

QIWG5

ZZZ

LA7987

DAZ_PCB

DAZ0N100701

14@

(Port 0/Port 1 support SATA3)

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B

QIWG6

LS7981P CardReader/B LS7982P USB/B LS7983P PWR/B LS7984P LED/B LS7985P ODD/B

Page30

Page32

1

2

3

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-7987P

E

2 50Tuesday, October 30, 2012

1.0

of

Voltage Rails

power

1

2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

plane

State

S0

S3

S5 S4/AC

EC SM Bus1 address

Device

Smart Battery

PCH SM Bus address

Device Address

3

DDR DIMM0

DDR DIMM2

SMBUS Control Table

SOURCE

4

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

KB9012

+3VALW

KB9012

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

A

+B

+5VALW

+3VALW

O

X

Address

0001 011X b

1001 000Xb

1001 010Xb

VGA BATT KB9012 SODIMM

X V

+3VALW

X

V

+3VS

X

B

+5VS

+3VS

+1.5VS

+V1.05S_VCCP

+1.5V

+VCC_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS

+1.05VS

O

X

O

X X

X

X X X

EC SM Bus2 address

Device

Thermal Sen sor F75303M

X

V

+3VS

V

+3VS

X

WLAN WWAN

X

XX

V

+3VS

X

Address

1001_101xb

Thermal Sensor

+3VS

X

XX

V

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

D

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

OFF

E

ON ON

ON

OFF

LOW

OFF

1

Board ID / SKU ID Table for AD channelBOARD ID Table

Board ID

0

PCB Revision

0.1

1 2 3 4

OO

5 6 7

X

USB Port Table

EHCI1

USB3.0

EHCI2

PCH

USB 2.0 Port

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

0 1 2 3 4 5 6 7 8

9 10 11 12 13

3 External USB Port

USB Port (Right Side CR-BD)

USB Port (Left Side) USB Port (Left Side)

Camera

USB/B (Right Side USB-BD)

Mini Card(WLAN) Card Reader

Blue Tooth

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5%

7 NC

USB3.0

AD_BID

0 V

V typ

AD_BID

V

max

AD_BID

0 V 0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

2.200 V

3.300 V

2.341 V

3.300 V

BOM Structure Table

BTO Item BOM Structure

HDMI HDMI@ Interna-Intel-USB3.0 IU3@ External-NEC-USB3.0 EU3@ Blue Tooth BT@ Connector ME@ 45 LEVEL 45@ 10/100 LAN 8162@ GIGA LAN GIGA@ LAN LDO Mode LDO@ LAN Switch mode SWR@ Cameara CMOS@ For QIWG5 (14") 14@ For QIWG6 (15") Unpop G5/G6/G9(Low/Mid END) G9 High-END

15@

@

nonBBH@

BBH@

Porject Phase

G-series

MP

G-series

PVT

G-series

DVT

G-series

EVT

Y-series

EVT

Y-series

DVT

Y-series

PVT

Y-series

MP

2

3

X

V

+3VS

X

XX X

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

LA-7987P

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

of

3 50Tuesday, October 30, 2012

of

3 50Tuesday, October 30, 2012

of

3 50Tuesday, October 30, 2012

E

1.0

5

D

C

B

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

+V1.05S_VCCP

24.9_0402_1%

4

JCPU1A

eDP_HPD

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0 ]

H19

FDI0_TX#[1 ]

E19

FDI0_TX#[2 ]

F18

FDI0_TX#[3 ]

B21

FDI1_TX#[0 ]

C20

FDI1_TX#[1 ]

D18

FDI1_TX#[2 ]

E17

FDI1_TX#[3 ]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMP IO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0 ]

E16

eDP_TX#[1 ]

D16

eDP_TX#[2 ]

F15

eDP_TX#[3 ]

TYCO_2013620-2_IVY BRIDGE

DMI

Intel(R) FDI

eDP

DMI_CRX_PTX_N0<15>

DMI_CRX_PTX_N1<15>

DMI_CRX_PTX_N2<15>

DMI_CRX_PTX_N3<15>

DMI_CRX_PTX_P0<15>

DMI_CRX_PTX_P1<15>

DMI_CRX_PTX_P2<15>

DMI_CRX_PTX_P3<15>

DMI_CTX_PRX_N0<15>

DMI_CTX_PRX_N1<15>

DMI_CTX_PRX_N2<15>

DMI_CTX_PRX_N3<15>

DMI_CTX_PRX_P0<15>

DMI_CTX_PRX_P1<15>

DMI_CTX_PRX_P2<15>

DMI_CTX_PRX_P3<15>

FDI_CTX_PRX_N0<15>

FDI_CTX_PRX_N1<15> FDI_CTX_PRX_N2<15>

FDI_CTX_PRX_N3<15> FDI_CTX_PRX_N4<15> FDI_CTX_PRX_N5<15>

FDI_CTX_PRX_N6<15> FDI_CTX_PRX_N7<15>

FDI_CTX_PRX_P0<15> FDI_CTX_PRX_P1<15> FDI_CTX_PRX_P2<15>

FDI_CTX_PRX_P3<15> FDI_CTX_PRX_P4<15>

FDI_CTX_PRX_P5<15> FDI_CTX_PRX_P6<15>

FDI_CTX_PRX_P7<15>

FDI_FSYNC0<15> FDI_FSYNC1<15>

1

R7

2

FDI_INT<15>

FDI_LSYNC0<15>

FDI_LSYNC1<15>

EDP_COMP

PEG_ICOMP I

PEG_ICOMP O

PEG_RCO MPO

PEG_RX# [0] PEG_RX# [1] PEG_RX# [2]

PEG_RX# [3] PEG_RX# [4]

PEG_RX# [5] PEG_RX# [6]

PEG_RX# [7] PEG_RX# [8] PEG_RX# [9]

PEG_RX# [10] PEG_RX# [11]

PEG_RX# [12] PEG_RX# [13] PEG_RX# [14]

PEG_RX# [15]

PEG_RX[0 ]

PEG_RX[1 ] PEG_RX[2 ]

PEG_RX[3 ] PEG_RX[4 ] PEG_RX[5 ]

PEG_RX[6 ] PEG_RX[7 ]

PEG_RX[8 ] PEG_RX[9 ]

PEG_RX[1 0] PEG_RX[1 1] PEG_RX[1 2]

PEG_RX[1 3] PEG_RX[1 4]

PEG_RX[1 5]

PEG_TX# [0] PEG_TX# [1]

PEG_TX# [2] PEG_TX# [3]

PEG_TX# [4] PEG_TX# [5]

PEG_TX# [6] PEG_TX# [7] PEG_TX# [8]

PEG_TX# [9]

PEG_TX# [10]

PEG_TX# [11] PEG_TX# [12]

PCI EXPRESS* - GRAPHICS

PEG_TX# [13]

PEG_TX# [14] PEG_TX# [15]

PEG_TX[0 ] PEG_TX[1 ]

PEG_TX[2 ] PEG_TX[3 ] PEG_TX[4 ]

PEG_TX[5 ] PEG_TX[6 ]

PEG_TX[7 ] PEG_TX[8 ] PEG_TX[9 ]

PEG_TX[1 0] PEG_TX[1 1]

PEG_TX[1 2] PEG_TX[1 3]

PEG_TX[1 4]

PEG_TX[1 5]

3

+V1.05S_VCCP

R1

24.9_0402_1%

J30 J28

H29 G27

E29 F27 D28

F26 E25

M28 M33

M30 L31 L28

K30 K27

J29 J27 H28

G28 E28

F28 D27

E26 D25

PEG_COMP

J22

J21 H22

K33 M35 L34

J35 J32

H34 H31

G33 G30 F35

E34 E32

D33 D31 B33

C32

J33

L35 K34

H35 H32 G34

G31 F33

F30 E35

E33 F32 D34

E31 C33

B32

M29 M32

M31 L32

L29 K31

K28

2

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms

1

2

PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

1

D

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

Compal Secret Data

3

Deciphered Date

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

LA-7987P

Date: Sheet

2

Date: Sheet

1

of

4 50Tuesday, October 30, 2012

of

4 50Tuesday, October 30, 2012

of

4 50Tuesday, October 30, 2012

A

1.0

5

D

+V1.05S_VCCP

1

R9

62_0402_5%

H_PROCHOT#<31,37>

C

H_CPUPWRGD<18>

H_PROCHOT#

1

100P_0402_50V8J

EMI Add

2

H_PM_SYNC<15>

2

R260_0402_5%

2

R27

R02

C549

R27

1

10K_0402_5%

1

2

4

JCPU1B

H_SNB_IVB#<18>

H_PROCHOT#_R

2

R22

2

H_CPUPWRGD_R

PM_DRAM_PWR GD_R

2

BUF_CPU_RST#

H_CATERR#

H_PM_SYNC_R

T48

H_PECI<18,31>

R15

56_0402_5%

1

H_THRMTRIP#<18>

@

1

0_0402_5%

R29

1

130_0402_5%

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

3

A28

BCLK

A27

BCLK#

PRDY# PREQ#

TMS

TRST#

TDO

DBR#

BPM#[0]

BPM#[1] BPM#[2] BPM#[3]

BPM#[4] BPM#[5]

BPM#[6] BPM#[7]

TCK

A16

A15

R8

AK1

A5 A4

AP29 AP27

AR26 AR27 AP30

AR28

TDI

AP26

AL35

AT28

AR29 AR30 AT30

AP32 AR31

AT31 AR32

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]

SM_RCOMP[1] SM_RCOMP[2]

DDR3

MISC

DDR3

MISC

JTAG & BPM

2

R10;R11 put on U4 side

@

CLK_CPU_DMI_R

CLK_CPU_DMII#_R

2

R12 1K_0402_5%

2

H_DRAMRST#

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

R13 1K_0402_5%

2

@

0_0402_5%

@

1

H_DRAMRST# <6>

1

R16 140_0402_1%

1

R17 25.5_0402_1%

1

R18 200_0402_1%

DDR3 Compensation Signals

XDP_PRDY#

XDP_PREQ#

XDP_TCK

XDP_TMS

XDP_TRST#

XDP_TDI

XDP_TDO

XDP_DBRESET#

XDP_BPM#0

XDP_BPM#1

XDP_BPM#2

XDP_BPM#3

XDP_BPM#4

XDP_BPM#5

XDP_BPM#6

XDP_BPM#7

T97

T98

T102

T103

2

R28 1K_0402_5%

T49

T90

T91

T92

T92 T93

T93

T94

T95

T96

1

R10

1

2

+V1.05S_VCCP

CLK_CPU_DMI <14>

CLK_CPU_DMI# <14>

1

R11

D

For ESD fail issue del XDP_TMS & XDP_TDO net , but keep R20&R23 for debug use

2

R20 51_0402_5%@

XDP_TDI

XDP_TCK XDP_TRST#

1

R20 51_0402_5%@

2

R21 51_0402_5%

2

R23 51_0402_5%@

2

R24 51_0402_5%

2

R25 51_0402_5%

+3VS

+V1.05S_VCCP

1

PU/PD for JTAG signals

C

TYCO_2013620-2_IVY BRIDGE

+3VALW

1

C33

0.1U_0402_16V4Z

B

SYS_PWROK<15>

A

1

2

R880

@

R880

@

0_0402_5%

1

R161

+3VS

10K_0402_5%

PM_DRAM_PWR GD<15>

RUN_ON_CPU1.5VS3#<9>

5

2

U1

2

5

1

P

B

2

A

G

74AHC1G09GW_TSSOP5

3

PM_SYS_PWRGD_BUF

4

O

2

G

+1.5V_CPU_VDDQ

1

@

R33

39_0402_5%

2

1

D

Q1

Q1 2N7002H_SOT23-3

2N7002H_SOT23-3

S

3

1

2

@

R30

200_0402_5%

4

BUF_CPU_RST#

TYCO_2013620-2_IVY BRIDGE

1

R35

@

R35

@

0_0402_5%

2

Buffered reset to CPU

+3VS

+V1.05S_VCCP

0.1U_0402_16V4Z

1

R32

75_0402_5%

R34

2

43_0402_1%

1

BUFO_CPU_RST#

2

SN74LVC1G07DCKR_SC70-5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

1

C34

2

5

U2

4

1

P

NC

Y

PCH_PLTRST#

2

A

G

3

2011/06/15 2012/07/11

3V

PCH_PLTRST# <17>

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

LA-7987P

Date: Sheet

1

of

5 50Tuesday, October 30, 2012

of

5 50Tuesday, October 30, 2012

of

5 50Tuesday, October 30, 2012

B

A

1.0

5

JCPU1C

DDR_A_D[0..63]<11>

D

C

B

DDR_A_BS0<11>

DDR_A_BS1<11> DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D0 DDR_A_D1

DDR_A_D2

DDR_A_D3 DDR_A_D4

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D8

DDR_A_D9

DDR_A_D10

DDR_A_D11

DDR_A_D12 DDR_A_D13

DDR_A_D14

DDR_A_D15

DDR_A_D16

DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D20 DDR_A_D21

DDR_A_D22

DDR_A_D23

DDR_A_D24

DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_D28

DDR_A_D29

DDR_A_D30

DDR_A_D31

DDR_A_D32 DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D36 DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D44

DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D48

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58

DDR_A_D59

DDR_A_D60

DDR_A_D61

DDR_A_D62 DDR_A_D63

G10

N10

M10

AG6

AG5

AK6 AK5

AH5 AH6

AK8

AK9

AH8

AH9

AL9

AL8

AP11

AN11

AL12

AM12

AM11

AL11 AP12

AN12

AJ14

AH14

AL15

AK15 AL14 AK14

AJ15

AH15

AE10

AF10

AE8 AD9

AF9

C5 D5

D3 D2 D6

C6 C2

C3

F10

F8

G9

G8 G7 K4

K5 K1

K2

M8

N8 N7

M9 N9

M7

AJ5 AJ6

AJ8

AJ9

V6

F9 F7

J1 J5

J4 J2

SA_DQ[0] SA_DQ[1]

SA_DQ[2] SA_DQ[3] SA_DQ[4]

SA_DQ[5] SA_DQ[6]

SA_DQ[7] SA_DQ[8] SA_DQ[9]

SA_DQ[10] SA_DQ[11]

SA_DQ[12] SA_DQ[13]

SA_DQ[14] SA_DQ[15] SA_DQ[16]

SA_DQ[17] SA_DQ[18]

SA_DQ[19] SA_DQ[20]

SA_DQ[21] SA_DQ[22] SA_DQ[23]

SA_DQ[24] SA_DQ[25]

SA_DQ[26] SA_DQ[27] SA_DQ[28]

SA_DQ[29] SA_DQ[30]

SA_DQ[31] SA_DQ[32]

SA_DQ[33] SA_DQ[34] SA_DQ[35]

SA_DQ[36] SA_DQ[37]

SA_DQ[38] SA_DQ[39]

SA_DQ[40] SA_DQ[41] SA_DQ[42]

SA_DQ[43] SA_DQ[44]

SA_DQ[45] SA_DQ[46]

SA_DQ[47] SA_DQ[48] SA_DQ[49]

SA_DQ[50] SA_DQ[51]

SA_DQ[52] SA_DQ[53] SA_DQ[54]

SA_DQ[55] SA_DQ[56]

SA_DQ[57] SA_DQ[58]

SA_DQ[59] SA_DQ[60] SA_DQ[61]

SA_DQ[62] SA_DQ[63]

SA_BS[0]

SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS#

SA_WE#

4

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

RSVD_TP[1]

AA4

RSVD_TP[2]

W9

RSVD_TP[3]

AB3

RSVD_TP[4]

AA3

RSVD_TP[5]

W10

RSVD_TP[6]

AK3

SA_CS#[0]

AL3

SA_CS#[1]

AG1

RSVD_TP[7]

AH1

RSVD_TP[8]

AH3

SA_ODT[0]

AG3

SA_ODT[1]

AG2

RSVD_TP[9]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4] SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_MA[0] SA_MA[1]

SA_MA[2] SA_MA[3]

SA_MA[4] SA_MA[5] SA_MA[6]

SA_MA[7] SA_MA[8]

SA_MA[9]

SA_MA[10]

SA_MA[11] SA_MA[12] SA_MA[13]

SA_MA[14] SA_MA[15]

AH2

C4 G6

J3

M6

AL6

AM8

AR12

AM15

D4

F6

K3

N6

AL5 AM9

AR11

AM14

AD10 W1

W2 W7

V3 V2 W3

W6 V1

W5 AD8

V4 W4 AF8

V5 V7

DDR_A_DQS#0

DDR_A_DQS#1

DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5

DDR_A_DQS#6

DDR_A_DQS#7

DDR_A_DQS0

DDR_A_DQS1

DDR_A_DQS2

DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5

DDR_A_DQS6

DDR_A_DQS7

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2 DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6 DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10 DDR_A_MA11

DDR_A_MA12 DDR_A_MA13

DDR_A_MA14

DDR_A_MA15

RSVD_TP[10]

SA_DQS#[0] SA_DQS#[1]

SA_DQS#[2]

SA_DQS#[3]

SA_DQS#[4]

SA_DQS#[5]

SA_DQS#[6]

SA_DQS#[7]

DDR SYSTEM MEMORY A

M_CLK_DDR0 <11> M_CLK_DDR#0 <11>

DDR_CKE0_DIMMA <11>

M_CLK_DDR1 <11> M_CLK_DDR#1 <11>

DDR_CKE1_DIMMA <11>

DDR_CS0_DIMMA# <11>

DDR_CS1_DIMMA# <11>

M_ODT0 <11> M_ODT1 <11>

3

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

2

JCPU1D

AH11

AH12

AN14 AR14

AA10

D10

K10

J10

AM5

AM6 AR3

AP3 AN3 AN2

AN1

AP2

AP5

AN9

AT5

AT6

AP6

AN8

AR6

AR5

AR9

AJ11

AT8

AT9

AR8

AJ12

AT11

AT14 AT12

AN15 AR15 AT15

AA9

AA7

R6

AB8 AB9

C9 A7

C8 A9

A8 D9

D8 G4

F4

F1

G1

G5

F5

F2

G2

J7

J8

K9

J9

K8 K7

M5 N4

N2 N1

M4 N5 M2

M1

JCPU1D

SB_DQ[0] SB_DQ[1]

SB_DQ[2] SB_DQ[3] SB_DQ[4]

SB_DQ[5] SB_DQ[6]

SB_DQ[7] SB_DQ[8] SB_DQ[9]

SB_DQ[10] SB_DQ[11]

SB_DQ[12] SB_DQ[13]

SB_DQ[14] SB_DQ[15] SB_DQ[16]

SB_DQ[17] SB_DQ[18]

SB_DQ[19] SB_DQ[20]

SB_DQ[21] SB_DQ[22] SB_DQ[23]

SB_DQ[24] SB_DQ[25]

SB_DQ[26] SB_DQ[27]

SB_DQ[28] SB_DQ[29] SB_DQ[30]

SB_DQ[31] SB_DQ[32]

SB_DQ[33] SB_DQ[34]

SB_DQ[35] SB_DQ[36] SB_DQ[37]

SB_DQ[38] SB_DQ[39]

SB_DQ[40] SB_DQ[41] SB_DQ[42]

SB_DQ[43] SB_DQ[44]

SB_DQ[45] SB_DQ[46]

SB_DQ[47] SB_DQ[48] SB_DQ[49]

SB_DQ[50] SB_DQ[51]

SB_DQ[52] SB_DQ[53]

SB_DQ[54] SB_DQ[55] SB_DQ[56]

SB_DQ[57] SB_DQ[58]

SB_DQ[59] SB_DQ[60]

SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0]

SB_BS[1] SB_BS[2]

SB_CAS#

SB_RAS# SB_WE#

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

SB_CS#[0]

SB_CS#[1]

SB_ODT[0]

SB_ODT[1]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_MA[0] SB_MA[1]

SB_MA[2] SB_MA[3]

SB_MA[4] SB_MA[5] SB_MA[6]

SB_MA[7] SB_MA[8]

SB_MA[9]

SB_MA[10]

SB_MA[11] SB_MA[12] SB_MA[13]

SB_MA[14] SB_MA[15]

AB2 AA2

T9

AA1

AB1 T10

AD3

AE3 AD6

AE6

AE4

AD4

AD5

AE5

DDR_B_DQS#0

D7

DDR_B_DQS#1

F3

DDR_B_DQS#2

K6

DDR_B_DQS#3

N3

DDR_B_DQS#4

AN5

DDR_B_DQS#5

AP9

DDR_B_DQS#6

AK12

DDR_B_DQS#7

AP15

DDR_B_DQS0

C7

DDR_B_DQS1

G3

DDR_B_DQS2

J6

DDR_B_DQS3

M3

DDR_B_DQS4

AN6

DDR_B_DQS5

AP8

DDR_B_DQS6

AK11

DDR_B_DQS7

AP14

DDR_B_MA0

AA8

DDR_B_MA1

T7

DDR_B_MA2

R7

DDR_B_MA3

T6

DDR_B_MA4

T2

DDR_B_MA5

T4

DDR_B_MA6

T3

DDR_B_MA7

R2

DDR_B_MA8

T5

DDR_B_MA9

R3

DDR_B_MA10

AB7

DDR_B_MA11

R1

DDR_B_MA12

T1

DDR_B_MA13

AB10

DDR_B_MA14

DDR_B_MA15

R5 R4

RSVD_TP[11] RSVD_TP[12]

RSVD_TP[13]

RSVD_TP[14]

RSVD_TP[15] RSVD_TP[16]

RSVD_TP[17]

RSVD_TP[18]

RSVD_TP[19]

RSVD_TP[20]

SB_DQS#[0]

SB_DQS#[1]

SB_DQS#[2] SB_DQS#[3]

SB_DQS#[4] SB_DQS#[5]

SB_DQS#[6]

SB_DQS#[7]

DDR SYSTEM MEMORY B

DDR_B_D[0..63]<12>

DDR_B_D0

DDR_B_D1

DDR_B_D2

DDR_B_D3

DDR_B_D4

DDR_B_D5

DDR_B_D6

DDR_B_D7

DDR_B_D8

DDR_B_D9

DDR_B_D10

DDR_B_D11

DDR_B_D12

DDR_B_D13

DDR_B_D14

DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D20

DDR_B_D21

DDR_B_D22

DDR_B_D23

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_D27

DDR_B_D28

DDR_B_D29

DDR_B_D30

DDR_B_D31

DDR_B_D32

DDR_B_D33

DDR_B_D34

DDR_B_D35

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D44

DDR_B_D45

DDR_B_D46

DDR_B_D47

DDR_B_D48

DDR_B_D49

DDR_B_D50

DDR_B_D51

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

DDR_B_D60

DDR_B_D61

DDR_B_D62

DDR_B_D63

DDR_B_BS0<12> DDR_B_BS1<12>

DDR_B_BS2<12>

DDR_B_CAS#<12>

DDR_B_RAS#<12> DDR_B_WE#<12>

1

M_CLK_DDR2 <12> M_CLK_DDR#2 <12> DDR_CKE2_DIMMB <12>

M_CLK_DDR3 <12>

M_CLK_DDR#3 <12>

DDR_CKE3_DIMMB <12>

DDR_CS2_DIMMB# <12>

DDR_CS3_DIMMB# <12>

M_ODT2 <12> M_ODT3 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

D

C

B

TYCO_2013620-2_IVY BRIDGE

+1.5V

R36

@

R36

@

0_0402_5%

1

2

D

S

D

S

1

3

Q2

G

LBSS138LT1G_SOT-23-3

2

1

C35

0.047U 16V K X7R 0402

2

DDR3_DRAMRST#_R

5

H_DRAMRST#

4.99K_0402_1%

2

R39

1

DRAMRST_CNTRL

H_DRAMRST#<5>

A

1

R37

1K_0402_5%

Eiffel used 0.01u Module design used 0.047u

2

R38

R38 1K_0402_5%

1K_0402_5%

1

4

2

DDR3_DRAMRST# <11,12>

DRAMRST_CNTRL_PC H<14>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

R02

1

R40 0_0402_5%

3

2

DRAMRST_CNTRL

@

Compal Secret Data

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

DRAMRST_CNTRL <9>

2

Compal Electronics, Inc.

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Custom

LA-7987P

Date: Sheet

1

of

6 50Tuesday, October 30, 2012

of

6 50Tuesday, October 30, 2012

of

6 50Tuesday, October 30, 2012

A

1.0

5

4

3

2

1

CFG Straps for Processor

CFG2

D

JCPU1E

AK28

CFG[0]

AK29

CFG2

CFG4

CFG5

CFG6

CFG7

+VCC_GFXCORE_AXG

+VCC_CORE

R253

49.9_0402_1%

C

49.9_0402_1%

2

R252

49.9_0402_1%

2

1

R82 100_0402_ 1%@

1

R88 100_040 2_1%@

2

VCC_AXG_VAL_SENSE

VSS_AXG_VAL_SENSE

VCC_VAL_SENSE

VSS_VAL_SENSE

Need PWR add new circuit on 1.0 5V(refer CRB)

VSS_AXG_VAL_SENSE

Check

R255

49.9_0402_1%

INTEL 12/28 recommand to add RC120, RC121, RC122, RC123

B

Please place as close as JCPU1

2

1

VSS_VAL_SENSE

2

R257

49.9_0402_1%

1

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

CFG

VCC_DIE_SENSE

VSS_DIE_SENSE

RESERVED

RSVD_NCTF10

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

Interl request AH26 short GND check on EVT phase

AH27

AH26

1

2

@

R02

RSVD28

RSVD29 RSVD30 RSVD31

RSVD32

RSVD33

RSVD34 RSVD35

RSVD37

RSVD38 RSVD39

RSVD40

RSVD_NCTF1

RSVD_NCTF2

RSVD_NCTF3

RSVD_NCTF4

RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7

RSVD_NCTF8 RSVD_NCTF9

RSVD51 RSVD52

BCLK_ITP

BCLK_ITP#

KEY

L7

AG7 AE7 AK2

W8

AT26

AM33 AJ27

T8

J16 H16

G16

AR35

AT34

AT33

AP35

AR34

B34 A33

A34 B35 C35

AJ32 AK32

AN35

AM35

AT2 AT1 AR1

B1

R60 0_0402_5%

PEG Static Lane Reversal - CFG2 is for the 16x

T13PAD

CFG2

*

Display Port Presence Strap

CFG4

*

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

1

R41

R41 1K_0402_1%

1K_0402_1%

2

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

1K_0402_1%

1

R42

@

R42

@

1K_0402_1%

2

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

CFG7

@

1

R44

@

R44

2

1

2

@

1K_0402_1%

2

R45

@

R45

@

1K_0402_1%

R43

D

C

B

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

LA-7987P

1

7 50Tuesday, October 30, 2012

A

1.0

of

5

POWER

+VCC_CORE

JCPU1F

POWER

QC=94A DC=53A

D

C

B

A

AG35

AG34 AG33

AG32 AG31 AG30

AG29 AG28

AG27 AG26

AF35

AF34 AF33

AF32 AF31

AF30 AF29 AF28

AF27 AF26

AD35 AD34 AD33

AD32 AD31

AD30 AD29

AD28 AD27 AD26

AC35 AC34

AC33 AC32

AC31

AC30 AC29

AC28 AC27

AC26 AA35 AA34

AA33 AA32

AA31 AA30 AA29

AA28 AA27

AA26

VCC1

VCC2 VCC3

VCC4 VCC5 VCC6

VCC7 VCC8

VCC9 VCC10 VCC11

VCC12 VCC13

VCC14 VCC15

VCC16 VCC17 VCC18

VCC19 VCC20

VCC21 VCC22 VCC23

VCC24 VCC25

VCC26 VCC27

VCC28 VCC29 VCC30

VCC31 VCC32

VCC33 VCC34 VCC35

VCC36 VCC37

VCC38 VCC39

VCC40 VCC41 VCC42

VCC43 VCC44

VCC45 VCC46 VCC47

VCC48 VCC49

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CORE SUPPLY

4

8.5A

AH13

VCCIO1

AH10

VCCIO2

AG10

VCCIO3

AC10

VCCIO4

Y10

VCCIO5

U10

VCCIO6

P10

VCCIO7

L10

VCCIO8

J14

VCCIO9

J13

VCCIO10

J12

VCCIO11

J11

VCCIO12

H14

VCCIO13

H12

VCCIO14

H11

VCCIO15

G14

VCCIO16

G13

VCCIO17

G12

VCCIO18

F14

VCCIO19

F13

VCCIO20

F12

VCCIO21

F11

VCCIO22

E14

VCCIO23

E12

VCCIO24

E11

VCCIO25

D14

VCCIO26

D13

VCCIO27

D12

VCCIO28

D11

VCCIO29

C14

VCCIO30

C13

VCCIO31

PEG AND DDR

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

VCCIO32 VCCIO33 VCCIO34

VCCIO35 VCCIO36

VCCIO37 VCCIO38

VCCIO39

VCCIO40

VIDALERT#

VIDSCLK VIDSOUT

C12 C11 B14

B12 A14

A13 A12

A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10

A10

3

+V1.05S_VCCP

1

C99

0.1U_0402_10V6K

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

0.1U_0402_10V6K

1

2

R47 43_0402_5%

1

2

R480_0402_5 % @

1

2

R490_0402_ 5% @

1

2

R50 130_0402_5%

2

1

R46

75_0402_5%

2

+V1.05S_VCCP

VR_SVID_CLK

VR_SVID_ALRT# <43> VR_SVID_CLK <43> VR_SVID_DAT <43>

0

.1uF on power side

series-resistors close to VR

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

Trace Impedance =27-33 ohm Trace Length Matc < 25 mils

VCCSENSE_R VSSSENSE_R

VSSIO_SENSE_L

VSS_SENCE 100ohm +-1% pull-down to GND near processor

1

2

R52 0_0402_5%@

1

2

R53 0_0402_5%@

VSSIO_SENSE

1

2

R74

10_0402_1%@

R74 & R79 put together

VSSIO_SENSE_L <42>

R79

2

10_0402_1%

VCCIO_SENSE <41,42>

+V1.05S_VCCP

1

2

+VCC_CORE

1

R51

100_0402_1%

1

R66

R66 100_0402_1%

100_0402_1%

2

@

1

R54

R54 100_0402_1%

100_0402_1%

2

VCCSENSE <43> VSSSENSE <43>

1

D

C

B

A

Security Classification

TYCO_2013620-2_IVY BRIDGE

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

LA-7987P

Date: Sheet

2

Date: Sheet

8 50Tuesday, October 30, 2012

1

1.0

of

5

4

3

2

1

+1.5V

1

PAD-OPEN 4x4m

U3

DMN3030LSS-13_SOP8L-8

8

7

6

5

RUN_ON_CPU1.5VS3

Q4

2N7002_SOT23

AT24 AT23 AT21

AT20 AT18

AT17

AR24

AR23 AR21 AR20

AR18 AR17

AP24 AP23 AP21

AP20 AP18

AP17 AN24

AN23 AN21 AN20

AN18 AN17

AM24 AM23 AM21

AM20 AM18

AM17

AL24

AL23 AL21 AL20

AL18 AL17

AK24 AK23

AK21 AK20 AK18

AK17 AJ24

AJ23 AJ21 AJ20

AJ18 AJ17

AH24 AH23

AH21 AH20 AH18

AH17

B6 A6

A2

PAD-OPEN 4x4m

JCPU1G

VAXG1 VAXG2 VAXG3

VAXG4 VAXG5

VAXG6 VAXG7

VAXG8 VAXG9 VAXG10

VAXG11 VAXG12

VAXG13 VAXG14 VAXG15

VAXG16 VAXG17

VAXG18 VAXG19

VAXG20 VAXG21 VAXG22

VAXG23 VAXG24

VAXG25 VAXG26 VAXG27

VAXG28 VAXG29

VAXG30 VAXG31

VAXG32 VAXG33 VAXG34

VAXG35 VAXG36

VAXG37 VAXG38

VAXG39 VAXG40 VAXG41

VAXG42 VAXG43

VAXG44 VAXG45 VAXG46

VAXG47 VAXG48

VAXG49 VAXG50

VAXG51 VAXG52 VAXG53

VAXG54

VCCPLL1 VCCPLL2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

R668

@

R668

@

1

@

22U_0805_6.3V6M

@

0_0402_5%

C345

Check

10U

1

2

C130

10U_0603_6.3V6M

C130

10U_0603_6.3V6M

1

2

+VSB

1

R03

R56

R56 82K_0402_5%

82K_0402_5%

2

1

D

2

G

S

3

RUN_ON_CPU1.5VS3# <5>

+VCC_GFXCORE_AXG

1.5A

+1.8VS_VCCPLL

C131

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

C132

1U_0402_6.3V6K

C132

1U_0402_6.3V6K

1

2

SUSP<35,42>

R667

@

R667

@

100K_0402_5%

2

R580_0402_5% @

2

R590_0402_5% @

R69 0_0805_5%

1

2

@

+3VALW

1

2

RUN_ON_CPU1.5VS3#

1

D

G

S

3

22U_0805_6.3V6M

1

@

2

Q7

Q7 2N7002_SOT23

2N7002_SOT23

C154

1

2

D

CPU1.5V_S3_GATE<31,35,42>

SUSP#<31,35,40,41,42>

C

B

A

1

+1.8VS

+1.5V_CPU_VDDQ

J1

@

J1

@

2

1

2

3

4

R885

1

15K_0402_1%

R57

330K_0402_5%

@

2

POWER

GRAPHICS

1.8V RAIL

@

R55

220_0402_5%

AP4800 Id=9.6A

R02

2

1

C97

0.047U_0603_25V7K

2

SENSE

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

@

@ Q3

Q3

2N7002_SOT23

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

VDDQ1

VDDQ2 VDDQ3

VDDQ4 VDDQ5 VDDQ6

VDDQ7 VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12 VDDQ13

VDDQ14 VDDQ15

VCCSA1

VCCSA2 VCCSA3

VCCSA4 VCCSA5

VCCSA6 VCCSA7 VCCSA8

VCCSA_SENSE

VCCSA_VID[0]

VCCSA_VID[1]

VCCIO_SEL

1

2

1

D

2

G

S

3

+VCC_GFXCORE_AXG

AK35 AK34

+V_SM_VREF_CNT

AL1

+V_DDR_REFA_R

B4

+V_DDR_REFB_R

D1

AF7

AF4 AF1

AC7 AC4 AC1

Y7 Y4

Y1 U7

U4

U1 P7

P4 P1

+VCCSA

M27

M26 L26

J26 J25

J24 H26 H25

H23

C22

C24

A19

1

@

C92

0.1U_0402_10V6K

2

RUN_ON_CPU1.5VS3#

1

R616

10_0402_1%

2

1

R626

10_0402_1%

2

H_VCCSA_VID0 <41> H_VCCSA_VID1 <41>

VCC_AXG_SENSE <43>

1

R89

@

R89

@

100_0402_1%

2

VSS_AXG_SENSE <43>

+V_SM_VREF should have 20 mil trace width

10U_0603_6.3V6M

1

C117

10U_0603_6.3V6M

C117

10U_0603_6.3V6M

1

2

10U

C124

10U_0603_6.3V6M

C124

10U_0603_6.3V6M

1

10U_0603_6.3V6M

1

2

+VREF_DQ_DIMMA

+VREF_DQ_DIMMB

DRAMRST_CNTRL

LBSS138LT1G_SOT-23-3

2

G

Q9

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

RUN_ON_CPU1.5VS3

+1.5V_CPU_VDDQ

1

R67

1K_0402_1%

2

1

C98

0.1U_0402_10V6K

C118

1

2

C126

10U_0603_6.3V6M

C126

10U_0603_6.3V6M

1

C125

2

1

R68 0_0402_5%

10U_0603_6.3V6M

2

10U_0603_6.3V6M

C120

10U_0603_6.3V6M

C120

10U_0603_6.3V6M

1

C119

2

+VCCSA

C127

10U_0603_6.3V6M

C127

10U_0603_6.3V6M

1

2

@

2

H_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SEL

IVY Bridge drives VCCIO_SEL low VCCP_PWRCTRL:0 Sandy Bridge is NC for A19 VCCP_PWRCTRL:1

R78

1K_0402_1%

2

+1.5V_CPU_VDDQ

1

C122

10U_0603_6.3V6M

C122

10U_0603_6.3V6M

1

C121

+

C123

330U_2.5V_M

2

1

+

C128

@

C128

@

330U_D2_2.5VY_R9M

2

+VCCSA_SENSE <41>

1

2

R77 0_0402_5%

10K_0402_5%

R670

1

R671

1

D

S

3

+3VS

2

R75

1

Q6

1

D

LBSS138LT1G_SOT-23-3

DRAMRST_CNTRL

2

G

@

S

3

+V_DDR_REFA_R

0_0402_5%~D

@

2

0_0402_5%~D

R353

1K_0402_1%

+V_DDR_REFB_R

1

@

2

1

1K_0402_1%

1K_0402_1% @

@

2

Q5-orignal part AP2302GN-HF_SOT23-3 SB523020210

G

2

PMV45EN_SOT23-3

PMV45EN_SOT23-3 Q5

@

Q5

@

1

3

D

S

D

S

@

2

+1.5V

2

R76

@

R76

@

10K_0402_5%

1

+V_SM_VREF

C396

0.1U_0402_10V6K

1

C129

0.1U_0402_10V6K

1

C96

0.1U_0402_10V6K

1

2

C95

0.1U_0402_10V6K

1

VCCP_PWRCTRL <41>

R61

1

0_0402_5%

+3VALW

R64

+1.5V

+1.5V_CPU_VDDQ

@

2

@

2

1

2

1

R63

R63 1K_0402_1%

1K_0402_1%

2

DRAMRST_CNTRL <6>

R62

@

R62

@

1K_0402_1%

@

D

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07/11

Compal Secret Data

Deciphered Date

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

LA-7987P

Date: Sheet

2

Date: Sheet

1

9 50Tuesday, October 30, 2012

1.0

of

5

AT35 AT32

AT29 AT27

AT25 AT22

AT19 AT16 AT13

D

C

B

A

5

AT10

AT7

AT4 AT3

AR25

AR22 AR19

AR16 AR13

AR10

AR7 AR4

AR2

AP34

AP31 AP28 AP25

AP22 AP19

AP16 AP13

AP10

AP7 AP4

AP1

AN30

AN27 AN25 AN22

AN19 AN16

AN13 AN10

AN7 AN4

AM29

AM25 AM22

AM19 AM16

AM13 AM10

AM7

AM4 AM3

AM2 AM1

AL34

AL31 AL28

AL25 AL22

AL19 AL16 AL13

AL10

AL7

AL4 AL2

AK33

AK30 AK27

AK25 AK22

AK19 AK16 AK13

AK10

AK7

AK4

AJ25

4

JCPU1H

VSS1 VSS2

VSS3 VSS4

VSS5 VSS6

VSS7 VSS8 VSS9

VSS10 VSS11

VSS12 VSS13 VSS14

VSS15 VSS16

VSS17 VSS18

VSS19 VSS20 VSS21

VSS22 VSS23

VSS24 VSS25 VSS26

VSS27 VSS28

VSS29 VSS30

VSS31 VSS32 VSS33

VSS34 VSS35

VSS36 VSS37 VSS38

VSS39 VSS40

VSS41 VSS42

VSS43 VSS44 VSS45

VSS46 VSS47

VSS48 VSS49

VSS50 VSS51 VSS52

VSS53 VSS54

VSS55 VSS56 VSS57

VSS58 VSS59

VSS60 VSS61

VSS62 VSS63 VSS64

VSS65 VSS66

VSS67 VSS68 VSS69

VSS70 VSS71

VSS72 VSS73

VSS74 VSS75 VSS76

VSS77 VSS78

VSS79 VSS80

TYCO_2013620-2_IVY BRIDGE

VSS

4

3

JCPU1I

AJ22

VSS81

AJ19

VSS82

AJ16

VSS83

AJ13

VSS84

AJ10

VSS85

AJ7

VSS86

AJ4

VSS87

AJ3

VSS88

AJ2

VSS89

AJ1

VSS90

AH35

VSS91

AH34

VSS92

AH32

VSS93

AH30

VSS94

AH29

VSS95

AH28

VSS96

AH25

VSS98

AH22

VSS99

AH19

VSS100

AH16

VSS101

AH7

VSS102

AH4

VSS103

AG9

VSS104

AG8

VSS105

AG4

VSS106

AF6

VSS107

AF5

VSS108

AF3

VSS109

AF2

VSS110

AE35

VSS111

AE34

VSS112

AE33

VSS113

AE32

VSS114

AE31

VSS115

AE30

VSS116

AE29

VSS117

AE28

VSS118

AE27

VSS119

AE26

VSS120

AE9

VSS121

AD7

VSS122

AC9

VSS123

AC8

VSS124

AC6

VSS125

AC5

VSS126

AC3

VSS127

AC2

VSS128

AB35

VSS129

AB34

VSS130

AB33

VSS131

AB32

VSS132

AB31

VSS133

AB30

VSS134

AB29

VSS135

AB28

VSS136

AB27

VSS137

AB26

VSS138

Y9

VSS139

Y8

VSS140

Y6

VSS141

Y5

VSS142

Y3

VSS143

Y2

VSS144

W35

VSS145

W34

VSS146

W33

VSS147

W32

VSS148

W31

VSS149

W30

VSS150

W29

VSS151

W28

VSS152

W27

VSS153

W26

VSS154

U9

VSS155

U8

VSS156

U6

VSS157

U5

VSS158

U3

VSS159

U2

VSS160

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

3

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

TYCO_2013620-2_IVY BRIDGE

Compal Secret Data

Deciphered Date

VSS

2

VSS234 VSS235

VSS236 VSS237

VSS238 VSS239

VSS240 VSS241 VSS242

VSS243 VSS244

VSS245 VSS246 VSS247

VSS248 VSS249

VSS250 VSS251

VSS252 VSS253 VSS254

VSS255 VSS256

VSS257 VSS258

VSS259 VSS260 VSS261

VSS262 VSS263

VSS264 VSS265 VSS266

VSS267 VSS268

VSS269 VSS270

VSS271 VSS272 VSS273

VSS274 VSS275

VSS276 VSS277

VSS278 VSS279 VSS280

VSS281 VSS282

VSS283 VSS284

VSS285

2

F22 F19

E30 E27

E24 E21

E18 E15 E13

E10 E9

E8 E7 E6

E5 E4

E3 E2

E1 D35 D32

D29 D26

D20 D17

C34 C31 C28

C27 C25

C23 C10

C1

B22 B19

B17 B15

B13 B11 B9

B8 B7

B5 B3

B2 A35 A32

A29 A26

A23 A20

A3

1

Compal Electronics, Inc.

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

LA-7987P

Date: Sheet

1

of

10 50Tuesday, October 30, 2012

of

10 50Tuesday, October 30, 2012

of

10 50Tuesday, October 30, 2012

D

C

B

A

1.0

+VREF_DQ_DIMMA

D

C

B

A

1K_0402_1%

R70

R70 1K_0402_1%

1K_0402_1%

DDR_CKE0_DIMMA<6>

DDR_A_BS2<6>

M_CLK_DDR0<6> M_CLK_DDR#0<6>

DDR_A_BS0<6>

5

+1.5V

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

JDIMM1

2.2U_0603_6.3V4Z C134

C134

1

2

DDR_A_WE#<6>

DDR_A_CAS#<6>

DDR_CS1_DIMMA#<6>

+3VS

5

DDR_A_D0

C133

DDR_A_D1

DDR_A_DM0

DDR_A_D2

DDR_A_D3

DDR_A_D8

DDR_A_D9

DDR_A_DQS#1

DDR_A_DQS1

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_DQS#2

DDR_A_DQS2

DDR_A_D18

DDR_A_D19

DDR_A_D24

DDR_A_D25

DDR_A_DM3

DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12

DDR_A_MA9

DDR_A_MA8

DDR_A_MA5

DDR_A_MA3

DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10

DDR_A_BS0

DDR_A_WE#

DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32

DDR_A_D33

DDR_A_DQS#4

DDR_A_DQS4

DDR_A_D34

DDR_A_D35

DDR_A_D40

DDR_A_D41

DDR_A_DM5

DDR_A_D42

DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_DQS#6

DDR_A_DQS6

DDR_A_D50

DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_DM7

DDR_A_D58

DDR_A_D59

1

2

R81

10K_0402_5%

0.1U_0402_10V6K

0.1U_0402_10V6K C156

C156

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C155

C155

1

2

10K_0402_5%

1

2

+VREF_DQ_DIMMA

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

JDIMM1

1

VREF_DQ

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

129 131

133

135

137

139

141

143 145

147

149

151

153

155 157

159

161

163

165

167

169 171

173

175

177

179

181 183

185

187

189

191

193

195 197

199

201

R83

203

205

VREF_CA

VSS27

DQ32 DQ33

VSS29

DQS#4

DQS4

VSS32

DQ34

DQ35 VSS34

DQ40

DQ41

VSS36

DM5

VSS37 DQ42

DQ43

VSS39

DQ48

DQ49

VSS41

DQS#6 DQS6

VSS44

DQ50

DQ51

VSS46

DQ56 DQ57

VSS48

DM7

VSS49

DQ58

DQ59

VSS51 SA0

VDDSPD

SA1

VTT1

G1

FOX_AS0A626-U4SN-7F

FOX_AS0A626-U4SN-7F ME@

ME@

+1.5V

1

2

1

R71

2

VSS1

DQ4

DQ5

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12

DQ13

VSS10

RESET#

VSS12

DQ14

DQ15

VSS14

DQ20

DQ21

VSS16

VSS17

DQ22

DQ23

VSS19

DQ28

DQ29

VSS21

DQS#3

DQS3

VSS24

DQ30

DQ31

VSS26

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36

DQ37

VSS30

VSS31

DQ38

DQ39

VSS33

DQ44

DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46

DQ47

VSS40

DQ52

DQ53

VSS42

VSS43

DQ54

DQ55

VSS45

DQ60

DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62

DQ63

VSS52

EVENT#

DQ6

DQ7

DM1

DM2

VTT2

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12

14

DDR_A_D6

16

DDR_A_D7

18

20

DDR_A_D12

22

DDR_A_D13

24

26

DDR_A_DM1

28

DDR3_DRAMRST#

30

32

DDR_A_D14

34

DDR_A_D15

36

38

DDR_A_D20

40

DDR_A_D21

42

44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52

54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64

66

DDR_A_D30

68

DDR_A_D31

70 72

DDR_CKE1_DIMMA

74

76

DDR_A_MA15

78

A15

A14

A11

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

DDR_A_MA14

80

82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

DDR_A_MA4

A6

92

A4

94

DDR_A_MA2

96

DDR_A_MA0

A2

98

A0

100

M_CLK_DDR1

102

M_CLK_DDR#1

104

106

DDR_A_BS1

108

DDR_A_RAS#

110 112

DDR_CS0_DIMMA#

114

M_ODT0

116

118

M_ODT1

120

122 124

126

128

DDR_A_D36

DDR_A_D37

130

132

DDR_A_DM4

134

136

DDR_A_D38

138

DDR_A_D39

140

142

DDR_A_D44

144

DDR_A_D45

146

148

DDR_A_DQS#5

150

DDR_A_DQS5

152

154

DDR_A_D46

156

DDR_A_D47

158

160

DDR_A_D52

162

DDR_A_D53

164

166

DDR_A_DM6

168

170

DDR_A_D54

172

DDR_A_D55

174

176

DDR_A_D60

178

DDR_A_D61

180

182

DDR_A_DQS#7

184

DDR_A_DQS7

186

188

DDR_A_D62

190

DDR_A_D63

192

194

196

SMB_DATA_S3

198

SMB_CLK_S3

200

202 204

206

G2

4

+0.75VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR3_DRAMRST# <6,12>

DDR_CKE1_DIMMA <6>

M_CLK_DDR1 <6>

M_CLK_DDR#1 <6>

DDR_A_BS1 <6> DDR_A_RAS# <6>

DDR_CS0_DIMMA# <6> M_ODT0 <6>

M_ODT1 <6>

0.1U_0402_10V6K

1

2

VDDQ(1.5V) =

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

VREF =

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <12,14,25>

SMB_CLK_S3 <12,14,25>

C135

1

2

DDR_A_D[0..63]<6>

DDR_A_DQS[0..7]<6>

DDR_A_DQS#[0..7]<6>

DDR_A_MA[0..15]<6>

R72

1K_0402_1%

+VREF_CA

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z C136

C136

1K_0402_1%

4*0402 1uf

1*0402 2.2uf

3

2

1

D

C

(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)OSCAN

+1.5V

1

2

1

R73

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Layout Note: Place near DIMM

+1.5V

C138

10U_0603_6.3V6M

C138

10U_0603_6.3V6M

C139

10U_0603_6.3V6M

C139

C137

10U_0603_6.3V6M

C137

10U_0603_6.3V6M

1

@

2

Layout Note: Place near DIMM

+0.75VS

@

C151

1U_0402_6.3V6K

C151

1U_0402_6.3V6K

C150

1U_0402_6.3V6K

C150

1U_0402_6.3V6K

1

2

2011/06/15 2012/07/11

10U_0603_6.3V6M

1

2

@

C152

1U_0402_6.3V6K

C152

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

C153

1U_0402_6.3V6K

1

2

Compal Secret Data

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

C141

10U_0603_6.3V6M

C141

10U_0603_6.3V6M

C140

10U_0603_6.3V6M

C140

10U_0603_6.3V6M

1

2

Deciphered Date

1

2

7/28 Update connect GND directly

DDR_A_DM0

DDR_A_DM1 DDR_A_DM2 DDR_A_DM3

DDR_A_DM4 DDR_A_DM5

DDR_A_DM6 DDR_A_DM7

2

C142

10U_0603_6.3V6M

C142

10U_0603_6.3V6M

1

2

Layout Note: Place near DIMM

C145

0.1U_0402_10V6K

C145

C143

0.1U_0402_10V6K

C144

10U_0603_6.3V6M

C144

10U_0603_6.3V6M

1

2

1

2

Custom

C147

0.1U_0402_10V6K

C147

0.1U_0402_10V6K

C146

0.1U_0402_10V6K

C146

0.1U_0402_10V6K

1

2

Title

Size Document Number Rev

Date: Sheet

EVT Check

1

C148

0.1U_0402_10V6K

C148

0.1U_0402_10V6K

+

C149

@

C149

1

2

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

@

220U_6.3V_M

2

LA-7987P

1

of

11 50Tuesday, October 30, 2012

of

11 50Tuesday, October 30, 2012

of

11 50Tuesday, October 30, 2012

B

A

1.0

+VREF_DQ_DIMMB

D

For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit.

C

B

A

+1.5V

@

1

2

1

2

R84

1K_0402_1%

R85

5

3A@1.5V

3A@1.5V3A@1.5V

+1.5V

JDIMM2

+VREF_DQ_DIMMB

DDR_B_D0

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

1

C158

2

@

DDR_CKE2_DIMMB<6>

DDR_B_BS2<6>

M_CLK_DDR2<6>

M_CLK_DDR#2<6>

DDR_B_BS0<6>

DDR_B_WE#<6> DDR_B_CAS#<6>

DDR_CS3_DIMMB#<6>

+3VS

2.2U_0603_6.3V4Z

1

2

@

5

DDR_B_D1

DDR_B_DM0

1

C157

DDR_B_D2

DDR_B_D3

2

DDR_B_D8

DDR_B_D9

DDR_B_DQS#1

DDR_B_DQS1

DDR_B_D10

DDR_B_D11

DDR_B_D16

DDR_B_D17

DDR_B_DQS#2

DDR_B_DQS2

DDR_B_D18

DDR_B_D19

DDR_B_D24

DDR_B_D25

DDR_B_DM3

DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12

DDR_B_MA9

DDR_B_MA8

DDR_B_MA5

DDR_B_MA3

DDR_B_MA1

M_CLK_DDR2

M_CLK_DDR#2

DDR_B_MA10

DDR_B_BS0

DDR_B_WE#

DDR_B_CAS#

DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32

DDR_B_D33

DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34

DDR_B_D35

DDR_B_D40

DDR_B_D41

DDR_B_DM5

DDR_B_D42

DDR_B_D43

DDR_B_D48

DDR_B_D49

DDR_B_DQS#6

DDR_B_DQS6

DDR_B_D50

DDR_B_D51

DDR_B_D56

DDR_B_D57

DDR_B_DM7

DDR_B_D58

DDR_B_D59

1

2

R95

10K_0402_5%

1

@

0.1U_0402_10V6K

R97 10K_0402_5%

C177

R97 10K_0402_5%

C178

@

1

2

@

1

VREF_DQ

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

29

DQS1

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25

61

VSS22

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

2

SA1

203

VTT1

205

G1

4

VSS1

DQ4

DQ5

VSS3

DQS#0

DQS0 VSS6

DQ6

DQ7

VSS8

DQ12

DQ13

VSS10

DM1

RESET#

VSS12

DQ14

DQ15

VSS14

DQ20

DQ21

VSS16

DM2

VSS17

DQ22 DQ23

VSS19

DQ28

DQ29

VSS21

DQS#3

DQS3

VSS24

DQ30

DQ31

VSS26

CKE1

VDD2

A15

A14

VDD4

A11

A7

VDD6

A6

A4

VDD8

A2

A0

VDD10

CK1

CK1#

VDD12

BA1

RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36

DQ37

VSS30

DM4

VSS31

DQ38

DQ39

VSS33

DQ44

DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46

DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54

DQ55

VSS45

DQ60

DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62

DQ63

VSS52

EVENT#

SDA

SCL

VTT2

FOX_AS0A626-U8SN-7F

ME@

4

3

+VREF_CB

2.2U_0603_6.3V4Z

1

2

@

4*0402 1uf

C160

DDR_B_D[0..63]<6>

DDR_B_DQS[0..7]<6>

DDR_B_DQS#[0..7]<6>

DDR_B_MA[0..15]<6>

+1.5V

1

R86

1K_0402_1%

2

@

1

R87

1K_0402_1%

2

@

1*0402 2.2uf

3

Layout Note: Place near DIMM

10U_0603_6.3V6M

C162

@

C174

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

1

2

@

10U_0603_6.3V6M

1

2

@

C175

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

1

2

Compal Secret Data

C161

1

@

2

Layout Note: Place near DIMM

+0.75VS

@

C173

1U_0402_6.3V6K

C173

1U_0402_6.3V6K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/06/15 2012/07/11

+1.5V

2

DDR_B_D4

4

DDR_B_D5

6

8

DDR_B_DQS#0

10

DDR_B_DQS0

12 14

DDR_B_D6

16

DDR_B_D7

18

20

DDR_B_D12

22

DDR_B_D13

24 26

DDR_B_DM1

28

DDR3_DRAMRST#

30

32

DDR_B_D14

34

DDR_B_D15

36

38

DDR_B_D20

40

DDR_B_D21

42

44

DDR_B_DM2

46

48

DDR_B_D22

50

DDR_B_D23

52

54

DDR_B_D28

56

DDR_B_D29

58

60

DDR_B_DQS#3

62

DDR_B_DQS3

64

66

DDR_B_D30

68

DDR_B_D31

70

72

DDR_CKE3_DIMMB

74

76

DDR_B_MA15

78

DDR_B_MA14

80 82

DDR_B_MA11

84

DDR_B_MA7

86

88

DDR_B_MA6

90

DDR_B_MA4

92

94

DDR_B_MA2

96

DDR_B_MA0

98

100

M_CLK_DDR3

102

M_CLK_DDR#3

104

106

DDR_B_BS1

108

DDR_B_RAS#

110

112

DDR_CS2_DIMMB#

114

M_ODT2

116

118

M_ODT3

120

122

124

126 128

DDR_B_D36

130

DDR_B_D37

132

DDR_B_DM4

134

136

138

DDR_B_D38

DDR_B_D39

140

142

DDR_B_D44

144

DDR_B_D45

146

148

DDR_B_DQS#5

150

DDR_B_DQS5

152 154

DDR_B_D46

156

DDR_B_D47

158

160

DDR_B_D52

162

DDR_B_D53

164 166

DDR_B_DM6

168

170

DDR_B_D54

172

DDR_B_D55

174

176

DDR_B_D60

178

DDR_B_D61

180

182

DDR_B_DQS#7

184

DDR_B_DQS7

186

188

DDR_B_D62

190

DDR_B_D63

192

194

196

SMB_DATA_S3

198

SMB_CLK_S3

200

202

204

206

G2

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DDR3_DRAMRST# <6,11>

DDR_CKE3_DIMMB <6>

M_CLK_DDR3 <6> M_CLK_DDR#3 <6>

DDR_B_BS1 <6> DDR_B_RAS# <6>

DDR_CS2_DIMMB# <6> M_ODT2 <6>

M_ODT3 <6>

0.1U_0402_10V6K

C159

1

2

VDDQ(1.5V) =

@

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

6*0603 10uf (PER CONNECTOR)

VTT(0.75V) =

3*0805 10uf

1*0402 0.1uf

VDDSPD (3.3V)=

1*0402 0.1uf 1*0402 2.2uf

SMB_DATA_S3 <11,14,25>

SMB_CLK_S3 <11,14,25>

+0.75VS

2

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

+1.5V

10U_0603_6.3V6M

C165

C163

1

2

@

C176

1U_0402_6.3V6K

C176

1U_0402_6.3V6K

1

2

@

Deciphered Date

C165

C164

1

2

@

DDR_B_DM0 DDR_B_DM1

DDR_B_DM2 DDR_B_DM3 DDR_B_DM4

DDR_B_DM5

1

DDR_B_DM6 DDR_B_DM7

2

10U_0603_6.3V6M

C166

1

2

@

Layout Note: Place near DIMM

1

D

C

10U_0603_6.3V6M

0.1U_0402_10V6K

C167

C168

1

2

@

0.1U_0402_10V6K C169

1

2

C169

1

2

@

Title

Size Document Number Rev

Date: Sheet

0.1U_0402_10V6K

1

2

@

C171

1

2

LA-7987P

1

0.1U_0402_10V6K C172

C172

@

0.1U_0402_10V6K

C170

1

2

@

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

B

A

1.0

of

12 50Tuesday, October 30, 2012

of

12 50Tuesday, October 30, 2012

of

12 50Tuesday, October 30, 2012

5

W=20milsW=20mils

+RTCVCC

R99

1K_0402_5%

1

C179

1U_0603_1 0V4Z

2

D

+RTCBAT T

2

1

CLRP1

SHORT PA DS

2

C180

18P_0402_5 0V8J

4

1

R98 10M_0402_ 5%

1

2

Y1

1

2

PCH_RTC X1

PCH_RTC X2

32.768KHZ_ 12.5PF_CM31532 768DZFT

1

C181

18P_0402_5 0V8J

2

3

2

1

D

+RTCVCC

1

R101 1M_0402_ 5%

R101 1M_0402 _5%

1

R102 330K_0402 _5%

INTVRMEN

H

：：：：

Integrated VRM enable

*

L

：：：：

Integrated VRM disable

2

SM_INTRU DER#

PCH_INTV RMEN

(INTVRMEN should always be pull high.)

+3VS

1

R105 1K_0402_5 %@

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

C

+3V_PCH

R106 1K_0402_5%@

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

R108 1K_0402_5%

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smaple d high

1.8V when sample d low

*

Needs to be pull ed High for Chi ef River platfr om

HDA_BITC LK_AUDIO<30>

HDA_SYNC_ AUDIO<30>

B

HDA_RS T_AUDIO#<3 0>

HDA_SD OUT_AUDIO<30>

+3V_PCH

1

@

@ R121

R121

200_0402_5 %

PCH_JTA G_TDO

2

1

@

@ R125

R125

100_0402_1 %

2

A

2

1

2

1

2

33_0402_5%

1

R114

33_0402_5%

1

33_0402_5%

1

33_0402_5%

1

+3V_PCH

1

@

R122

200_0402_5 %

PCH_JTA G_TMS

2

1

@

R126

100_0402_1 %

2

R112

R116

R118

HDA_BIT_ CLK

2

HDA_SYNC_ R

2

HDA_RST #

2

HDA_SDO UT

2

+3V_PCH

1

PCH_JTA G_TDI

2

1

2

HDA_SPK R

HDA_SDO UT

HDA_SYNC

@

@ R123

R123

200_0402_5 %

@

@ R128

R128

100_0402_1 %

DPDG1.1

CMOS

+RTCVCC

1U_0603_1 0V4Z

1

R103 20K_04 02_5%

1

R100 20K_04 02_5%

C182

1U_0603_1 0V4Z

+3V_PCH

ME_FLAS H

R107 1K_04 02_1%@

R107 1K_0 402_1%@

+5VS

G

2

3

S

R175

1

0_0402_5%

ME_FLAS H<31>

2

R878

1M_0402_5 %

1

Del Q10 check with codec VDDIO using 3VALW

1

C183

2

1

2

HDA_SPK R<30>

HDA_SDIN 0<30 >

1

2

R110

51_0402_5%

Q10

LBSS138LT 1G_SOT-23-3

HDA_SYNC

1

D

@

2

R124

33_0402_5%

@

C190

22P_0402_5 0V8J

@

U4A

CLRP2

SHORT PADS

CLRP2

SHORT PADS

PCH_RTC X1

PCH_RTC X2

PCH_RTC RST#

PCH_SRT CRST#

CLRP3

SHORT PADS

CLRP3

SHORT PADS

SM_INTRU DER#

PCH_INTV RMEN

HDA_BIT_ CLK

HDA_SYNC

HDA_SPK R

HDA_RST #

HDA_SDIN 0

R109

0_0402_5%

R26410K_0402_5 % @

PCH_JTA G_TCK

1

PCH_JTA G_TMS

PCH_JTA G_TDI

PCH_JTA G_TDO

SPI_CLK_P CH_R

SPI_SB_C S0#

SPI_SI

SPI_SO_R

SPI_CLK_P CH_R

1

HDA_SDO UT

2

PCH_GPIO33

1

SPI_SB_C S1#

U4A

A20

RTCX1

C20

RTCX2

D20

RTCRST #

G22

SRTCRS T#

K22

INTRUDE R#

C17

INTVRME N

N34

HDA_BC LK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RS T#

E34

HDA_SD IN0

G34

HDA_SD IN1

C34

HDA_SD IN2

A34

HDA_SD IN3

A36

HDA_SD O

C36

HDA_DOC K_EN# / GPIO33

N32

HDA_DOC K_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHE R-POINT_FCBGA98 9

R124;c190 close to U4.T3 pin

2

RTC

IHDA

JTAG

SPI

LPC

FWH4 / LF RAME#

LDRQ1# / GPIO23

SATA

SATA0GP / GP IO21

SATA1GP / GP IO19

HM76@

SATA 6G

SATA3RC OMPO

U4

LDRQ0#

SERIRQ

SATA0RX N SATA0RX P SATA0TX N

SATA0TX P

SATA1RX N

SATA1RX P

SATA1TX N

SATA1TX P

SATA2RX N SATA2RX P

SATA2TX N SATA2TX P

SATA3RX N SATA3RX P

SATA3TX N SATA3TX P

SATA4RX N

SATA4RX P

SATA4TX N

SATA4TX P

SATA5RX N

SATA5RX P

SATA5TX N SATA5TX P

SATALED #

HM70@

C38 A38 B37

C37

D36

E36

K36

V5

AM3 AM1 AP7

AP5

AM10

AM8 AP11

AP10

AD7 AD5

AH5 AH4

AB8 AB10

AF3 AF1

Y7

Y5 AD3

AD1

Y3 Y1

AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

FWH0 / LA D0 FWH1 / LA D1 FWH2 / LA D2

FWH3 / LA D3

SATAICOM PO

SATAICOM PI

SATA3COM PI

SATA3RB IAS

BD82HM70 SJTNV C1

SA00005M Q80

LPC_AD0

LPC_AD1

LPC_AD2

LPC_AD3

LPC_FRA ME#

R104 10K_0402_5%

SERIRQ

SATA_ITX_ C_DRX_N0

SATA_ITX_ C_DRX_P0

SATA_DT X_C_IRX_N2

SATA_DT X_C_IRX_P2 SATA_ITX_ C_DRX_N2

SATA_ITX_ C_DRX_P2

SATA_COM P

SATA3_C OMP

RBIAS_SA TA3

SATALED #

PCH_GPIO21

BBS_BIT0_ R

+3VS

2

R221

R129

LPC_AD0 <25 ,31> LPC_AD1 <25 ,31>

LPC_AD2 <25 ,31> LPC_AD3 <25 ,31>

LPC_FRA ME# <25,31>

2

R111

37.4_0402_1%

1

49.9_0402_1%

1

750_0402_1 %

R117 10K_0402_ 5%

R119 10K_0402_ 5%

R187 10K_0402_5 %

R266

1

R127

1

SERIRQ <31>

2

R113

R115

1

CAP on Conn, side

+1.05VS_VC C_SATA

+1.05VS_SA TA3

2

SPI_WP #1

2

3.3K_0402_5 %

SPI_HOLD# 1

2

3.3K_0402_5 %

SPI_WP #

2

3.3K_0402_5 %

SPI_HOLD#

2

3.3K_0402_5 %

EC and Mini card debug port

+3VS

SATA_DT X_C_IRX_N0

SATA_DT X_C_IRX_P0

SATA_ITX_ DRX_N0

1

2

C1840.01U_0402_ 25V7K

SATA_ITX_ DRX_P0

1

2

C1850.01U_0402_25V 7K

SATA_DT X_C_IRX_N2 <29>

SATA_DT X_C_IRX_P2 <29>

SATA_ITX_ C_DRX_N2 <29>

SATA_ITX_ C_DRX_P2 <29>

SPI_SB_C S1#

+3VS

SPI_SO_R

+3VS

SPI_SB_C S0#

SPI_SO_R

SATA_DT X_C_IRX_N0 <29>

SATA_DT X_C_IRX_P0 <29>

SATA_ITX_ DRX_N0 <29> SATA_ITX_ DRX_P0 <29>

ODD

8MB SPI ROM FOR ME & Non-share ROM.

R291

CS1#

0_0402_5%

SPI_SO1

1

2

SPI_WP #1

1

2

R188

33_0402_5%

U6 Rersver 4M+2M Solution

R130

0_0402_5%

0_0402_5% 1

1

2

33_0402_5%

R131

CS#

SPI_SO_L

2

SPI_WP #

U6

1

CS#

2

SO

HOLD#

3

WP#

SCLK

4

GND

16M W2 5Q16BVSSIG SOIC 8P

U5

1

CS#

2

SO

3

WP#

4

GND

32M W2 5Q32BVSSIG SOIC 8P

VCC

SI

VCC

HOLD#

SCLK

HDD

SI

8

7 6

5

+3VS

SPI_HOLD# 1

SPI_CLK1 SPI_SI1

+3VS

8

SPI_HOLD#

7

SPI_CLK_P CH

6

SPI_SI_R

5

0_0402_5%

1

C191

1

2

0.1U_0402_1 6V4Z

R132

0_0402_5%

1

R199

SPI_CLK_P CH_R SPI_SI

2

R196

33_0402_5%

SPI_CLK_P CH_R

2

SPI_SI

2

R133

R133 33_0402_5%

33_0402_5%

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 201 2/07/11

2011/06/15 20 12/07/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

LA-7987P

Date: S heet

1

of

13 50Tuesday, October 30, 2012

of

13 50Tuesday, October 30, 2012

of

13 50Tuesday, October 30, 2012

1.0

5

LAN

WLAN

D

USB3.0

C

LAN

WLAN

USB3.0

B

PCIE_PRX _DTX_N1<26> PCIE_PRX _DTX_P1<26>

PCIE_PTX _C_DRX_N1<26>

PCIE_PTX _C_DRX_P1<26>

PCIE_PRX _DTX_N2<25>

PCIE_PRX _DTX_P2<25> PCIE_PTX _C_DRX_N2<25> PCIE_PTX _C_DRX_P2<25>

PCIE_PRX _DTX_N4<34>

PCIE_PRX _DTX_P4<34>

PCIE_PTX _C_DRX_N4<34>

PCIE_PTX _C_DRX_P4<34>

CLK_PCIE _LAN#<26>

CLK_PCIE _LAN<26 >

CLKREQ_L AN#<26>

CLK_PCIE _WLAN1#<25> CLK_PCIE _WLAN1<25>

CLKREQ_W LAN#<25>

CLK_PCIE _USB30#< 34>

CLK_PCIE _USB30<34>

CLKREQ_U SB30#<34>

+3V_PCH

+3VS

+3V_PCH

C309 0.1U_0402_10 V7K@

C308 0.1U_0402_10V7K@

+3VS

1

C192 0.1U_040 2_10V7K

C193 0.1U_0402_1 0V7K

C194 0.1U_040 2_10V7K

C195 0.1U_0402_10 V7K

R153 0_040 2_5%

R154 0_040 2_5%

R151 0_0402_5 %

R152 10K_040 2_5%

R149 0_040 2_5%

R150 0_0402_5%

R156 0_0402_ 5%

R158 10K_040 2_5%

R147 10K_0402 _5%

R334 0_0402_5%@

R330 0_040 2_5%@

R326 0_0402_5%@

R301 10K_0402_ 5%

R165 10K_0 402_5%

R168 10K _0402_5%

R170 10K_0402_5 %

R172 10K_ 0402_5%

R174 10K_0402_5 %

2

1

2

1

2

1

2

1

2

1

2

CAP on Conn, side

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

4

PCIE_PRX _DTX_N1 PCIE_PRX _DTX_P1

PCIE_PTX _DRX_N1

PCIE_PTX _DRX_P1

PCIE_PRX _DTX_N2

PCIE_PRX _DTX_P2

PCIE_PTX _DRX_N2

PCIE_PTX _DRX_P2

PCIE_PRX _DTX_N4 PCIE_PRX _DTX_P4

PCIE_PTX _DRX_N4

PCIE_PTX _DRX_P4

CLK_PCIE _LAN#_R

CLK_PCIE _LAN_R

CLKREQ_L AN#_R

CLK_PCIE _WLAN1#_R

CLK_PCIE _WLAN1_R

CLKREQ_W LAN#_R

PCH_GPIO20

CLK_USB 30#

CLK_USB 30

CLKREQ_U SB30#_R

PCH_GPIO26

PCH_GPIO44

PCH_GPIO56

PCH_GPIO45

PCH_GPIO46

PCIE_CLK_8N PCIE_CLK_8P

U4B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_P CIE0N

Y39

CLKOUT_P CIE0P

J2

PCIECLKR Q0# / GPIO73

AB49

CLKOUT_P CIE1N

AB47

CLKOUT_P CIE1P

M1

PCIECLKR Q1# / GPIO18

AA48

CLKOUT_P CIE2N

AA47

CLKOUT_P CIE2P

V10

PCIECLKR Q2# / GPIO20

Y37

CLKOUT_P CIE3N

Y36

CLKOUT_P CIE3P

A8

PCIECLKR Q3# / GPIO25

Y43

CLKOUT_P CIE4N

Y45

CLKOUT_P CIE4P

L12

PCIECLKR Q4# / GPIO26

V45

CLKOUT_P CIE5N

V46

CLKOUT_P CIE5P

L14

PCIECLKR Q5# / GPIO44

AB42

CLKOUT_P EG_B_N

AB40

CLKOUT_P EG_B_P

E6

PEG_B_CL KRQ# / GPIO56

V40

CLKOUT_P CIE6N

V42

CLKOUT_P CIE6P

T13

PCIECLKR Q6# / GPIO45

V38

CLKOUT_P CIE7N

V37

CLKOUT_P CIE7P

K12

PCIECLKR Q7# / GPIO46

AK14

CLKOUT_IT PXDP_N

AK13

CLKOUT_IT PXDP_P

PANTHE R-POINT_FCBGA98 9

PCI-E*

CLOCKS

3

SMBALE RT# / GPIO11

SMBCLK

SMBDAT A

SML0ALE RT# / GPIO60

SMBUSController

SML1ALE RT# / PCHHOT# / GPIO74

Link

PEG_A_CL KRQ# / GPIO47

FLEX CLOCKS

SML0CLK

SML0DAT A

SML1CLK / GPIO58

SML1DAT A / GPIO75

CL_CLK1

CL_DATA 1

CL_RST1#

CLKOUT_P EG_A_N CLKOUT_P EG_A_P

CLKOUT_D MI_N CLKOUT_D MI_P

CLKOUT_D P_N CLKOUT_D P_P

CLKIN_DM I_N

CLKIN_DM I_P

CLKIN_GND 1_N

CLKIN_GND 1_P

CLKIN_DOT _96N

CLKIN_DOT _96P

CLKIN_SA TA_N

CLKIN_SA TA_P

REFCLK1 4IN

CLKIN_PC ILOOPBACK

XTAL25_IN

XTAL25_OU T

XCLK_RC OMP

CLKOUTFL EX0 / GPIO64

CLKOUTFL EX1 / GPIO65

CLKOUTFL EX2 / GPIO66

CLKOUTFL EX3 / GPIO67

PCH_GPI01 1

E12

PCH_SM BCLK

H14

PCH_SM BDATA

C9

DRAMRS T_CNTRL_PCH

A12

PCH_SM L0CLK

C8

PCH_SM L0DATA

G12

PCH_HOT #

C13

SML1CLK

E14

SML1DAT A

M16

M7

T11

P10

PEG_CLKR EQ#_R

M10

AB37 AB38

CLK_CPU _DMI#

AV22

CLK_CPU _DMI

AU22

AM12 AM13

CLK_BUF _CPU_DMI#

BF18

CLK_BUF _CPU_DMI

BE18

CLKIN_DM I2#

BJ30

CLKIN_DM I2

BG30

CLK_BUF _DREF_96M#

G24

CLK_BUF _DREF_96M

E24

CLK_BUF _PCIE_SATA#

AK7

CLK_BUF _PCIE_SATA

AK5

CLK_BUF _ICH_14M

K45

CLK_PCI_L PBACK

H45

XTAL25_IN

V47

XTAL25_OU T

V49

XCLK_RC OMP

Y47

27M_SSC

K43

F47

LAN_48M

H47

PCH_GPIO67

K49

BIOS Request SKU ID

2

10K_0402_5 %

2

+3V_PCH

2

1

R207 22_04 02_5%@

1

R134

R140 10K_0 402_5%

R143

10K_0402_5 %

R155 10K_0402_5 %

R155 10K_0402_ 5%

+3V_PCH

2

1

R157 10K_ 0402_5%

R159 10K_ 0402_5%

R160 10K _0402_5%

R162 10K_ 0402_5%

R163 10K _0402_5%

R164 10K _0402_5%

R166 10K_ 0402_5%

R167 10K_0402 _5%

R171

90.9_0402_1%

1

+3V_PCH

PCH_HOT # <31>

1

2

R145 10K_04 02_5%@

CLK_CPU _DMI# <5> CLK_CPU _DMI <5>

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

CLK_PCI_L PBACK <17>

+1.05VS_VC CDIFFCLKN

2

PCH_GPIO67 <18>

2

+3V_PCH

DRAMRS T_CNTRL_PCH <6>

1

R139

+3V_PCH

1K_0402_5%

+3V_PCH

PCH_LAN _48M

2.2K_0402_5 %

2.2K_0402_5 % 1

R136

1

R135

2.2K_0402_5 %

1

R141

1

R142

2.2K_0402_5 %

2

XTAL25_IN

XTAL25_OU T

Q60A

Q60A 2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6

SMB_CLK _S3

6

2.2K_0402_5 %

1

2

+3VS

1

5

2.2K_0402_5 %

SMB_DA TA_S3

3

4

2N7002DW -T/R7_SOT363-6

Q60B

Q61A

Q61A 2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6

6

1

2

+3VS

5

3

2N7002DW -T/R7_SOT363-6

2N7002DW -T/R7_SOT363-6 Q61B

Q61B

C196

12P_0402_5 0V8J

1

2

R137

2

R138

EC_SMB _CK2

EC_SMB _DA2

4

PCH_SM L0CLK

PCH_SM L0DATA

1

2

R169 1M_040 2_5%

3

OSC

2

NC

Y2

25MHZ_1 0PF_7V25000014

1

R02

2

1

SMB_CLK _S3 <11,12,25>

DIMM1 DIMM2 MINI CARD

SMB_DA TA_S3 <11,12,25>

EC_SMB _CK2 <28,31>

VGA EC thermal sensor

EC_SMB _DA2 <28,31>

+3V_PCH

2

R544

2.2K_0402_5 %

NC

OSC

R544

4

1

2

1

C197

12P_0402_5 0V8J

R545

2.2K_0402_5 %

D

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 2012/07 /11

2011/06/15 2012 /07/11

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sh eet

2

Date: S heet

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

LA-7987P

1

14 50Tuesday, October 30, 2012

of

A

1.0

5

4

3

2

1

D

VGATE<43>

PCH_PW ROK

C

AEPWROK can be c onnect to PWROK if iAMT di sable

PCH_POK

+3VS

@

+3V_PCH

B

@

2

R556 200_0402 _5%

2

R192 300K_0402 _5%

2

R194 1 0K_0402_5%

1

R195 200K_0402_ 5%

2

R197 10K_0402 _5%

R191

1

0_0402_5%

1

2

1

2

U15

U15 MC74VH C1G08DFT2G SC70 5P

MC74VH C1G08DFT2G SC70 5P

3

1

G

A

Y

2

B

P

5

+3VS

APWR OK

PM_DRA M_PWRGD

SUSW ARN#

AC_PRES ENT_R

PCH_RSM RST#_R

SYS_PWR OK

4

1

R180

R180 100K_0402_ 1%

100K_0402_ 1%

2

SYS_PWR OK <5>

@

SUSACK# is only used on platfor m that support the Deep Sx state.

PCH_PW ROK<31>

PCH_APW ROK<31>

PM_DRA M_PWRGD<5>

EC_RSM RST#<31>

PBTN_OUT #<31>

ACIN<31,38>

DMI_CTX_ PRX_N0< 4>

DMI_CTX_ PRX_N1<4 >

DMI_CTX_ PRX_N2<4 >

DMI_CTX_ PRX_N3<4 >

DMI_CTX_ PRX_P0<4>

DMI_CTX_ PRX_P1<4> DMI_CTX_ PRX_P2<4> DMI_CTX_ PRX_P3<4>

DMI_CRX _PTX_N0<4>

DMI_CRX _PTX_N1<4>

DMI_CRX _PTX_N2<4>

DMI_CRX _PTX_N3<4>

DMI_CRX _PTX_P0<4> DMI_CRX _PTX_P1<4>

DMI_CRX _PTX_P2<4> DMI_CRX _PTX_P3<4>

+1.05VS

1

R177 49.9_0402_1 %

1

R178 750_0402_1 %

4mil width and place within 500mil of the PCH

T72

+3VS

PCH_PW ROK

D29

CH751H-40 PT_SOD323-2

+3V_PCH

2

1

R190 0_0402_5%

1

R193 0_0402_5%

1

R198 0_0402_5%

2

1

2

R18410K_0402_5%

2

@

R3020 _0402_5%

2

R200

R200 10K_0402_5 %

10K_0402_5 %

R201

10K_0402_5 %

DMI_CTX_ PRX_N0

DMI_CTX_ PRX_N1

DMI_CTX_ PRX_N2

DMI_CTX_ PRX_N3

DMI_CTX_ PRX_P0

DMI_CTX_ PRX_P1

DMI_CTX_ PRX_P2

DMI_CTX_ PRX_P3

DMI_CRX _PTX_N0

DMI_CRX _PTX_N1

DMI_CRX _PTX_N2

DMI_CRX _PTX_N3

DMI_CRX _PTX_P0

DMI_CRX _PTX_P1

DMI_CRX _PTX_P2

DMI_CRX _PTX_P3

DMI_IRCOM P

RBIAS_CP Y

SUSACK #

SYS_RST#

1

SYS_PWR OK

PCH_POK

APWR OK

2

PM_DRA M_PWRGD

PCH_RSM RST#_R

SUSW ARN#

PBTN_OUT #_R

AC_PRES ENT_R

PCH_GPIO72

1

RI#

1

U4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOM P

BG25

DMI_IRCOM P

BH21

DMI2RBIAS

C12

SUSACK #

K3

SYS_RESET #

P12

SYS_PWR OK

L22

PWROK

L10

APWR OK

B13

DRAMPW ROK

C21

RSMRST #

K16

SUSW ARN#/SUSPW RDNACK/GPIO30

E20

PWRB TN#

H20

ACPRES ENT / GPIO31

E10

BATLOW # / GPIO72

A10

RI#

PANTHE R-POINT_FCBGA98 9

FDI_RXN0 FDI_RXN1

FDI_RXN2 FDI_RXN3

FDI_RXN4 FDI_RXN5 FDI_RXN6

FDI_RXN7

FDI_RXP0

FDI_RXP1 FDI_RXP2

FDI_RXP3 FDI_RXP4 FDI_RXP5

DMI

System Power Management

FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWV RMEN

DPWR OK

WAKE#

CLKRUN # / GPIO32

SUS_STA T# / GPIO61

SUSCLK / GP IO62

SLP_S5# / GPIO6 3

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS #

PMSYNCH

SLP_LAN# / GPIO29

AY14

BE14 BH13

BC12 BJ12 BG10

BG9

BG14

BB14 BF14

BG13 BE12 BG12

BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_CTX_P RX_N1

FDI_CTX_P RX_N2 FDI_CTX_P RX_N3

FDI_CTX_P RX_N4 FDI_CTX_P RX_N5 FDI_CTX_P RX_N6

FDI_CTX_P RX_N7

FDI_CTX_P RX_P0

FDI_CTX_P RX_P1 FDI_CTX_P RX_P2

FDI_CTX_P RX_P3 FDI_CTX_P RX_P4

FDI_CTX_P RX_P5

FDI_CTX_P RX_P6

FDI_CTX_P RX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWOD VREN

PCH_DPW ROK

WAKE#

PM_CLKR UN#

SUS_STA T#

SLP_A#

PM_SLP_ SUS#

H_PM_SYNC

PCH_GPIO29

FDI_CTX_P RX_N0

BJ14

1

2

R185 0_0402_5 %

1

2

R186

1

2

R261

@

R261

@

10K_0402_5 %

FDI_CTX_P RX_N0 <4> FDI_CTX_P RX_N1 <4>

FDI_CTX_P RX_N2 <4> FDI_CTX_P RX_N3 <4> FDI_CTX_P RX_N4 <4>

FDI_CTX_P RX_N5 <4> FDI_CTX_P RX_N6 <4>

FDI_CTX_P RX_N7 <4>

FDI_CTX_P RX_P0 <4> FDI_CTX_P RX_P1 <4>

FDI_CTX_P RX_P2 <4> FDI_CTX_P RX_P3 <4>

FDI_CTX_P RX_P4 <4> FDI_CTX_P RX_P5 <4>

FDI_CTX_P RX_P6 <4> FDI_CTX_P RX_P7 <4>

FDI_INT <4>

FDI_FSYNC0 <4>

FDI_FSYNC1 <4>

FDI_LSYNC0 <4>

FDI_LSYNC1 <4>

R181

R181 0_0402_5%

0_0402_5%

10K_0402_5 %

T74

T99

T71

H_PM_SYNC <5>

+3V_PCH

PCH_RSM RST#_R

1

2

PCIE_W AKE# <25 ,26,34>

+3V_PCH

SUSCLK <31>

PM_SLP_ S5# <31>

PM_SLP_ S4# <31>

PM_SLP_ S3# <31>

*

DSWODVREN - On D ie DSW VR Enabl e H

：

Enable

L

：

Disable

+3VS

R189 8.2K_0402 _5%@

1

2

R299 10K_0402 _5%

1

2

Can be left NC when IAMT is not support on the platfrom

Can be left NC i f no use integrated LAN.

+RTCVCC

1

2

R179

R179 330K_0402_ 5%

330K_0402_ 5%

1

R183

330K_0402_ 5%

@

2

D

C

B

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2011/06/15 201 2/07/11

2011/06/15 20 12/07/11

Compal Secret Data

Deciphered Date

Size Document Number Rev

Custom

Date: S heet

2

Date: S heet

Compal Electronics, Inc.

Title

PCH (3/9) DMI,FDI,PM,

LA-7987P

of

15 50Tuesday, October 30, 2012

of

15 50Tuesday, October 30, 2012

of

1

15 50Tuesday, October 30, 2012

A

1.0

Lenovo G580,G580A,G585 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual