LENOVO G580 Schematics
A
B
C
D
E
1
1
Compal Confidential
2
QIWG5/QIWG6 DIS M/B Schematics Document
Intel Ivy Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13X
2012-05-21
2
3
3
LA-7986P
REV:1.0
4
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
D
Date: Sheet
Compal Electronics, Inc.
Cover Page
LA-7986P
E
1 62Wedn esday, August 08, 2012
of
4
1.0
A
Compal confidential
File Name : QIWG5/QIWG6
1
HDMI
Connector
CRT
2
Connector
LVDS
Connector
USB3.0 *2(Left)
Option
USB3.0
Renesas
uPD720202
3
Arthros
AR8161(GLAN)
AR8162(10/100)
RJ-45
Connector
PCI Express
Mini Card Slot *1
WLAN
4
nVIDIA N13M-GE
VIDIA N13P-GL
n
VR A M 1 2 8* 1 6
Page35
Page34
P
age33
Page45
Page37
Page38
PCI-E(WLAN)
Page36
Page23-32
DD R3 *8
B
PCI-E x16
PCI-E x1 *6
SPIROM
BIOS
Page14
Touch Pad Int. KBD
Ivy Bridge
Socket-rPGA988B
37.5mm*37.5mm
100MHz
2.7GT/s
Panther Point
HM75 / HM76
EC
ENE KB9012
Page43
Thermal Sensor
EMC1403
Intel
Page5-11
FDI *8
Intel
FCBGA 989
25mm*25mm
Page14-22
LPC BUS
Page42
Page39
C
Dual Channel
DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
DDR3 1600MHz(1.5V)
DMI *4
AZALIA
USB2.0 *14
SATA *6
Page43
ZZZ 5
LA7986
15@
DAZ_PCB
DAZ0N200501
D
ZZ Z
LA7986
14@
DAZ_PCB
DAZ0N100601
ZZZ 7
G6_DA@
DA_PCB
DA80000SU00
ZZZ 1
G5_DA@
DA_PCB
DA80000SU00
ZZZ 6
G6_DA@
DA_PCB
DA400016P10
ZZZ 2
G5_DA@
DA_PCB
DA400016P10
ZZZ 8
G6_DA@
DA_PCB
DA400016Q10
DDR3 SO-DIMM *2
BANK 0, 1, 2, 3
Up to 8GB
Audio Codec
Conexant
CX20671-21Z
Page41
Camera Conn.
BlueTooth Conn.
Mini Card Slot *1
Card Reader
Reltek
RTS5178 for SDR50
SDXC/MMC
USB2.0 *2(Right)
USB2.0 *2(Left)
SATA HDD
SATA ODD
ZZZ 3
G5_DA@
DA_PCB
DA400016Q10
ZZZ 9
G6_DA@
DA_PCB
DA400016R10
Page12-13
ZZZ 4
G5_DA@
DA_PCB
DA400018T10
ZZZ1 0
G6_DA@
DA_PCB
DA400016S10
2 channel speaker
Int. MIC x1
Audio Jacks
Page33
Page40
Page36
Page43
Page 43;44
Page45
Page40
P
age40
ZZZ1 1
G6_DA@
DA_PCB
DA400018T10
Page41
Page41
Page43
(Port 0/Port 1 support SATA3)
E
QIWG5
LS7986P CardReader/B
LS7982P USB/B
LS7983P PWR/B
QIWG6
LS7986P CardReader/B
LS7982P USB/B
LS7983P PWR/B
LS7984P LED/B
LS7985P ODD/B
QIWG9
LS7986P CardReader/B
LS7982P USB/B
L
S7983P PWR/B
LS8612P LED/B
LS7985P ODD/B
1
2
3
4
www.schematic-x.blogspot.com
A
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
D
Date: Sheet
Compal Electronics, Inc.
Block Diagram
LA-7986P
E
2 62Wedn esday, August 08, 2012
1.0
of
Voltage Rails
power
1
2
S5 S4/ Battery only
S5 S4/AC & Battery
do
n't exist
plane
State
S0
S3
S5 S4/AC
EC SM Bus1 address
Device
Smart Battery
PCH SM Bus address
Device Address
DDR D IMM0
3
DDR D IMM2
NV-GPU SM Bus address
Device Address
Internal thermal sensor
A
Address
000 1 011 X b
+B
O
O
O
O
X
100 1 000 Xb
100 1 010 Xb
100 1 111 Xb (0x9E )
B
+5VALW
+3VALW
+1.5V
+VCC_GFXCORE_AXG
O
O
O
X
O
X X
X
X X X
EC SM Bus2 address
Device
Thermal Sensor F75303M
Address
100 1_101 xb
+5VS
+3VS
+1.5VS
+V1.05S_VCCP
+VCC_CORE
+VGA_CORE
+1.8VS
+0.75VS
+1.05VS
OO
X
X
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
USB Port Table
USB 2.0
UHCI0
EHCI1
USB3.0
EHCI2
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
C
PCB Revision
0.1
Port
0
USB Port (Right Side CR-BD)
1
2
USB Port (Left Side)
3
USB Port (Left Side)
4
5
Camera
6
7
8
USB/B (Right Side USB-BD)
9
10
Mini Card(WLAN)
11
Card Reader
12
13
Blue Tooth
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7 NC
3 External
USB Port
D
STATE
Full ON
S1(P ower On Suspend)
S3 ( Suspend to RAM)
S4 ( Suspend to Disk)
S5 ( Soft OFF)
SIGNAL
SLP_S1# SLP_S3#
100K +/- 5%Ra/Rc/Re
Rb / Rd / Rf V min
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
USB 3.0
USB 3.0
E
SLP_S4#
SLP_S5#
HIGH HIGH HIGH H IGH
LOW
LOW
LOW
HIGH
LOWLOWLOW
LOW LOW LOW LOW
HIGHHIGHHIGH
HIGH
HIGH
+VALW
ON
ON
ON
ON
ON
+V
ONONON ON
ON
OFF
OFF
Board ID / SKU ID Table for AD channel
AD_BID
V typ
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
V
max
AD_BID
0 V 0 V
0.538 V
0.875 V
2.341 V
3.300 V
BOM Structure Table
BTO Item BOM Structure
N13P@ GPU:N13P-GL
HDMI HDMI@
Interna-Intel-USB3.0 IU3@
External-NEC-USB3.0 EU3@
Blue Tooth BT@
Connector ME@
45 LEVEL 45@
10/100 LAN 8162@
GIGA LAN GIGA@
LAN LDO Mode LDO@
LAN Switch mode SWR@
Cameara CMOS@
For QIWG5 (14") 14@
For QIWG6 (15") 15@
Unpop
G5/G6/G9(Low/Mid END)
G9 High-END
G9
G5/G6/G9(Low/Mid END) 15_nonBBH@
N13M@GPU:N13M-GE
@
nonBBH@
BBH@
G9 @
+VS
Clock
ON
LOW
OFF
OFF
OFF
OFF
OFF
OFF
Porject Phase
G-ser ies
MP
G-ser ies
PVT
G-ser ies
DVT
G-ser ies
EVT
Y-ser ies
EV
Y-ser ies
DVT
Y-ser ies
PVT
Y-ser ies
MP
1
T
2
3
SMBUS Control Table
SOURCE
4
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
KB9012
+3VALW
KB9012
+3VALW
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW
VGA BATT KB9012 SODIMM
X V
+3VALW
X
X
X
V
+3VS
A
X
X
X
X
X
X
V
+3VS
X
X
V
+3VS
X
WLAN
WWAN
X
XX
V
+3VS
X
B
Thermal
Sensor
X
X
X
XX
V
+3VS
PCH
X
V
+3VS
X
X
XX X
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
D
Title
Size Doc ument Number Re v
B
LA-7986P
Date: Sheet
Compal Electronics, Inc.
Notes List
of
3 62Wedn esday, August 08, 2012
E
4
1.0
5
4
3
2
1
Hot pl ug detect for IFP link C
VGA and GDDR3 Voltage Rails (N13x GPIO)
GPIO I/O ACTIVE Function Description
GPIO0
D
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
C
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
B
+1.05 VS_VGA
OUT GPU VID4-
OUT
OUT
OUT
OUT
OUT
OUT
I/O
OUT
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
+3VS_VG A
+VGA_ CORE
+1.5V S_VGA
-
GPU VID3OUT
Panel Back-Li ght b rightness(PWM capable)
H
Pan el Powe r Enable
H
Panel Back-Li ght On/Off (PWM)
H
GPU VID1
-
GPU VID2
-
N/A
Thermal Catast rophic Over Temperature
-
Therma l Alert
-
Memory VREF Control
-
GPU VID0-OUT
AC Pow er Det ect Input
GPU VID5-
N/A
Hot pl ug detect for IFP link C
N/A
N/A
Hot Pl ug Detect for IFPE
N/A
tNVVDD >0
tFBVDDQ >0
tPEX_VDD >0
(10K pull low)
Performance Mode P0 TDP at Tj = 102 C* (GDDR3)
PU Mem NVCLK
G
(4) (1,5) (6)
Products
N13P-GL
64bit
1GB
GDDR3
Physi cal
Stra pping pin
ROM_SCL K
(W) (W) (MHz)
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
ROM_SI
ROM_SO FB[0]
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
/MCLK NVVDD
TBD TBD
Power Rail
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
(V) (A) (W) (A) (W )
Logical
S
trapp ing Bit3
PCI_DEVID[4]
FB[1]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
SOR3_EXPOSED
RESERVED PCIE_SPEED_
FBVDD
Logical
Stra pping Bit 2
SUB_V ENDOR
USER[2] USER[1] USER[0]USER[3]
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]
SOR2_EXPOSED SOR1_EXPOSED
CHANGE_GEN3
Device ID
N13P-GL
(28nm)
N13M-GE
(28nm)
GPU STRAP2 STRAP1 ST RAP0
N13P-GL
N13M-GE
???
???
FB Memory (GDDR3)
Samsung
2500MHz
Hynix
2500MHz
Samsung
2500MHz
2500MHz
K4G10325FG-HC04
H5GQ1H24BFR-T2C
K4G20325FG-HC04
H5GQ2H24MFR-T2CHynix
ROM_SO
32Mx32
32Mx32 PD 15K
PD 10K
64Mx32
64Mx32
FBVDDQ PCI Express I/O and
(GPU+Mem)
(1.35V)(1.35V)
(A) (W) (W)(mA) (W) ( W) (W)(mA) (mA) (mA)
(1.05V)
Logical
Stra pping Bit 1
SLOT_CLK_CFG
RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]
PLLVDD
Logical
Stra pping Bit 0
PEX_PLL_EN_TERM
AM_CFG[0]
R
VGA_D EVICESMB_A LT_ADDR
3GIO_PAD_CFG_ADR[0]
PCIE_MAX_SPEED DP_PLL_VDD33V
SOR0_EXPOSED
ROM_SCLK ROM_SI
PD 15K
PD 15K
PD 20KPD 10K PU 45K
PU 20K
PU 20K
PD 15K PD 35KPU 20KPD 10K PD 20K PU 45K
PD 15K PD 35KPU 20KPD 10K PD 20K PU 45K
X76
I/O and
PLLVDD
PD 35K
PD 35K
Other
(3.3V)(1.05V)(1.8V)
D
C
PU 45K
B
1. all power rail ramp up time should be larger than 40us
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
A
1.all GPU power rails should be turned off within 10ms
5
Tpower-off <10ms
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
3
Compal Secret Data
Deciphered Date
Title
Size Doc ument Number Re v
Cus tom
2
Date: Sheet
Compal Electronics, Inc.
VGA Notes List
LA-7986P
4 62Wedn esday, August 08, 2012
1
of
A
1.0
5
D
C
24.9_04 02_1%
B
eDP_COMPIO and ICOMPO signals
should be short ed near balls
and routed with typical
impedance <25 mohms
+V1.05S _VCCP
1
R7
2
2
PEG_ICOM PI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
1
2
PEG_ICOM PO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1: No rmal Opera tion; Lane # definition matches
socke t pin map definition
0:Lan e Reversed
*
PCIE_CTX_GR X_N15
PCIE_CTX_GR X_N14
PCIE_CTX_GR X_N13
PCIE_CTX_GR X_N12
PCIE_CTX_GR X_N11
PCIE_CTX_GR X_N10
PCIE_CTX_GR X_N9
PCIE_CTX_GR X_N8
PCIE_CTX_GR X_N7
PCIE_CTX_GR X_N6
PCIE_CTX_GR X_N5
PCIE_CTX_GR X_N4
PCIE_CTX_GR X_N3
PCIE_CTX_GR X_N2
PCIE_CTX_GR X_N1
PCIE_CTX_GR X_N0
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0
PCIE_CTX_ GRX_N[0..15] <23>
PCIE_CTX_GR X_P[0..15] <23>
PEG_ICOMP I
PEG_ICOMP O
PEG_RCO MPO
PEG_RX# [0]
PEG_RX# [1]
PEG_RX# [2]
PEG_RX# [3]
PEG_RX# [4]
PEG_RX# [5]
PEG_RX# [6]
PEG_RX# [7]
PEG_RX# [8]
PEG_RX# [9]
PEG_RX# [10]
PEG_RX# [11]
PEG_RX# [12]
PEG_RX# [13]
PEG_RX# [14]
PEG_RX# [15]
PEG_RX[0 ]
PEG_RX[1 ]
PEG_RX[2 ]
PEG_RX[3 ]
PEG_RX[4 ]
PEG_RX[5 ]
PEG_RX[6 ]
PEG_RX[7 ]
PEG_RX[8 ]
PEG_RX[9 ]
PEG_RX[1 0]
PEG_RX[1 1]
PEG_RX[1 2]
PEG_RX[1 3]
PEG_RX[1 4]
PEG_RX[1 5]
PEG_TX# [0]
PEG_TX# [1]
PEG_TX# [2]
PEG_TX# [3]
PEG_TX# [4]
PEG_TX# [5]
PEG_TX# [6]
PEG_TX# [7]
PEG_TX# [8]
PEG_TX# [9]
PEG_TX# [10]
PEG_TX# [11]
PEG_TX# [12]
PCI EXPRESS* - GRAPHICS
PEG_TX# [13]
PEG_TX# [14]
PEG_TX# [15]
PEG_TX[0 ]
PEG_TX[1 ]
PEG_TX[2 ]
PEG_TX[3 ]
PEG_TX[4 ]
PEG_TX[5 ]
PEG_TX[6 ]
PEG_TX[7 ]
PEG_TX[8 ]
PEG_TX[9 ]
PEG_TX[1 0]
PEG_TX[1 1]
PEG_TX[1 2]
PEG_TX[1 3]
PEG_TX[1 4]
PEG_TX[1 5]
3
+V1.05S _VCCP
R1
24.9_0402_1%
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_COMP
PCIE_CRX_G TX_N15
PCIE_CRX_G TX_N14
PCIE_CRX_G TX_N13
PCIE_CRX_G TX_N12
PCIE_CRX_G TX_N11
PCIE_CRX_G TX_N10
PCIE_CRX_G TX_N9
PCIE_CRX_G TX_N8
PCIE_CRX_G TX_N7
PCIE_CRX_G TX_N6
PCIE_CRX_G TX_N5
PCIE_CRX_G TX_N4
PCIE_CRX_G TX_N3
PCIE_CRX_G TX_N2
PCIE_CRX_G TX_N1
PCIE_CRX_G TX_N0
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P0
PCIE_CTX_GR X_C_N15
PCIE_CTX_GR X_C_N14
PCIE_CTX_GR X_C_N13
PCIE_CTX_GR X_C_N12
PCIE_CTX_GR X_C_N11
PCIE_CTX_GR X_C_N10
PCIE_CTX_GR X_C_N9
PCIE_CTX_GR X_C_N8
PCIE_CTX_GR X_C_N7
PCIE_CTX_GR X_C_N6
PCIE_CTX_GR X_C_N5
PCIE_CTX_GR X_C_N4
PCIE_CTX_GR X_C_N3
PCIE_CTX_GR X_C_N2
PCIE_CTX_GR X_C_N1
PCIE_CTX_GR X_C_N0
PCIE_CTX_GR X_C_P15
PCIE_CTX_GR X_C_P14
PCIE_CTX_GR X_C_P13
PCIE_CTX_GR X_C_P12
PCIE_CTX_GR X_C_P11
PCIE_CTX_GR X_C_P10
PCIE_CTX_GR X_C_P9
PCIE_CTX_GR X_C_P8
PCIE_CTX_GR X_C_P7
PCIE_CTX_GR X_C_P6
PCIE_CTX_GR X_C_P5
PCIE_CTX_GR X_C_P4
PCIE_CTX_GR X_C_P3
PCIE_CTX_GR X_C_P2
PCIE_CTX_GR X_C_P1
PCIE_CTX_GR X_C_P0
PCIE_CRX_G TX_N[0..15] <23>
PCIE_CRX_G TX_P[0..15] <23>
C1 0.1U_04 02_10V7KN13P@
1
C2 0.1U_04 02_10V7KN13P@
1
C3 0.1U_04 02_10V7KN13P@
1
C4 0.1U_04 02_10V7KN13P@
1
C5 0.1U_04 02_10V7KN13P@
1
C6 0.1U_04 02_10V7KN13P@
1
C7 0.1U_04 02_10V7KN13P@
1
C8 0.1U_04 02_10V7KN13P@
1
C9 0.1U_04 02_10V7K
1
C10 0.1U_04 02_10V7K
1
C11 0.1U_04 02_10V7K
1
C12 0.1U_04 02_10V7K
1
C13 0.1U_04 02_10V7K
1
C14 0.1U_04 02_10V7K
1
C15 0.1U_04 02_10V7K
1
C16 0.1U_04 02_10V7K
1
C17 0.1U_04 02_10V7KN13P@
1
C18 0.1U_04 02_10V7KN13P@
1
C19 0.1U_04 02_10V7KN13P@
1
C20 0.1U_04 02_10V7KN13P@
1
C21 0.1U_04 02_10V7KN13P@
1
C22 0.1U_04 02_10V7KN13P@
1
C23 0.1U_04 02_10V7KN13P@
1
C24 0.1U_04 02_10V7KN13P@
1
C25 0.1U_04 02_10V7K
1
C26 0.1U_04 02_10V7K
1
C27 0.1U_04 02_10V7K
1
C28 0.1U_04 02_10V7K
1
C29 0.1U_04 02_10V7K
1
C30 0.1U_04 02_10V7K
1
C31 0.1U_04 02_10V7K
1
C32 0.1U_04 02_10V7K
1
4
JCPU 1A
eDP_HPD
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0 ]
H19
FDI0_TX#[1 ]
E19
FDI0_TX#[2 ]
F18
FDI0_TX#[3 ]
B21
FDI1_TX#[0 ]
C20
FDI1_TX#[1 ]
D18
FDI1_TX#[2 ]
E17
FDI1_TX#[3 ]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMP IO
A17
eDP_ICOMPO
B16
eDP_HPD#
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0 ]
E16
eDP_TX#[1 ]
D16
eDP_TX#[2 ]
F15
eDP_TX#[3 ]
TYCO_ 20136 20-2_IVY BRIDGE
DMI
Intel(R) FDI
eDP
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
FDI_CTX_PRX_ N0<16>
FDI_CTX_PRX_ N1<16>
FDI_CTX_PRX_ N2<16>
FDI_CTX_PRX_ N3<16>
FDI_CTX_PRX_ N4<16>
FDI_CTX_PRX_ N5<16>
FDI_CTX_PRX_ N6<16>
FDI_CTX_PRX_ N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FD I_FSY NC0<16>
FD I_FSY NC1<16>
FD I_INT<16>
FD I_LSYN C0<16>
FD I_LSYN C1<16>
EDP_COMP
1
D
C
B
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
Compal Secret Data
3
Deciphered Date
Title
PROCESSOR(1/7) DMI,FDI,PEG
Size D ocumen t Number Re v
Cust om
LA-7986P
2
Dat e: Sheet
1
o f
5 62We dnesda y, August 08 , 2012
A
1.0
5
4
3
2
1
D
H_SNB _IVB#<19>
+V1.05S_VCCP
H_CATERR #
H_PRO CHOT#_R
2
H_PM _SYNC_R
2
H_CPU PWRGD_R
PM_DRAM_PWR GD_R
2
BUF_C PU_RST#
BUF_C PU_RST#
H_THRMTRIP#<19>
@
R30
200_0402_5%
T48
H_PEC I<19,42>
R15
56_0402_5%
1
R22
1
0_0402_5%
R29
1
130_0402_5%
1
R9
62_0402_5%
H_PRO CHOT#<42,48>
C
H_CPU PWRGD<19>
B
SYS_PW ROK<16>
+3VS
PM_DRAM_PWR GD<16>
H_PROCH OT#
1
100P_0402_50V8J
EMI Reserve
0.1U_0402_16V4Z
R880
@
1
2
0_0402_5%
R161
1
2
10K_0402_5%
RUN_O N_CPU1.5VS3#<10>
2
H_PM _SYNC<16>
R260_0402_5%
2
2
R27
1
C549
@
C33
1
2
1
2
+3VALW
1
2
U1
5
P
B
4
O
A
G
74AHC1G09GW_TSSOP5
3
10K_0402_5%
PM_SYS _PWRGD_BUF
2
G
+1.5V_ CPU_VDDQ
1
@
R33
39_0402_5%
2
1
D
Q1
@
2N7002H_SOT23-3
S
3
1
2
JCPU1B
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWR OK
AR33
RESET#
TYCO_20 13620-2_IV Y BRIDGE
1
R35
@
0_0402_5%
2
+V1.05S_VCCP
1
R32
75_0402_5%
R34
2
43_0402_1%
1
2
SN74L VC1G07DCKR_SC70-5
MISCTHERMALPWR MANAGEMENT
CLOCKS
DDR3
JTAG & BPM
Buffered reset to CPU
C34
0.1U_0402_16V4Z
BUFO_ CPU_RST#
MISC
1
2
U2
4
Y
BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PRDY#
PREQ#
TRST#
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
+3VS
5
1
P
NC
2
A
G
3
CLK_C PU_DMI_R
A28
CLK_C PU_DMII#_R
A27
A16
A15
R8
AK1
A5
A4
2
2
H_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DDR3 C ompensation Signals
XDP_P RDY#
AP29
XDP_PREQ#
AP27
XDP_TCK
AR26
TCK
XDP_TMS
AR27
TMS
XDP_TRST#
AP30
XDP_TDI
AR28
TDI
XDP_TDO
AP26
TDO
XDP_DBRESET#
AL35
XDP_BPM#0
AT28
XDP_BPM#1
AR29
XDP_BPM#2
AR30
XDP_BPM#3
AT30
XDP_BPM#4
AP32
XDP_BPM#5
AR31
XDP_BPM#6
AT31
XDP_BPM#7
AR32
PCH_PLTRST#
3V
PCH_PLTRST# <18>
R10;R11 put on U4 side
R10
@
0_0402_5%
1
0_0402_5%
R12 1K_0402_5%
1
R13 1K_0402_5%
1
H_DRAMRST# <7>
R16 140_0402_1%
1
2
R17 25.5_0402_1%
1
2
R18 200_0402_1%
1
2
T97
T98
R28 1K_0402_5%
2
T49
T90
T91
T92
T93
T94
T95
T96
2
1
2
@
R11
1
+V1.05S_VCCP
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TCK
XDP_TRST#
CLK_C PU_DMI <15>
CLK_C PU_DMI# <15>
R20 51_0402_5%
2
R21 51_0402_5%
2
R23 51_0402_5%@
2
R24 51_0402_5%
2
R25 51_0402_5%
2
+3VS
D
+V1.05S_VCCP
1
1
1
1
1
PU/PD for JTAG signals
C
B
A
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
PROCESSOR(2/7) PM,XDP,CLK
Size Doc ument Number Re v
Cus tom
LA-7986P
2
Date: Sheet
1
of
6 62Wedn esday, August 08, 2012
A
1.0
5
4
3
2
1
JCPU 1C
DDR_ A_D[0..63 ]<12>
D
C
B
DDR_A_BS 0<12>
DDR_A_BS 1<12>
DDR_A_BS 2<12>
DDR_A _CAS#<12>
DDR_A _RAS#<12>
DDR_A_W E#<12>
DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A _D10
DDR_A _D11
DDR_A _D12
DDR_A _D13
DDR_A _D14
DDR_A _D15
DDR_A _D16
DDR_A _D17
DDR_A _D18
DDR_A _D19
DDR_A _D20
DDR_A _D21
DDR_A _D22
DDR_A _D23
DDR_A _D24
DDR_A _D25
DDR_A _D26
DDR_A _D27
DDR_A _D28
DDR_A _D29
DDR_A _D30
DDR_A _D31
DDR_A _D32
DDR_A _D33
DDR_A _D34
DDR_A _D35
DDR_A _D36
DDR_A _D37
DDR_A _D38
DDR_A _D39
DDR_A _D40
DDR_A _D41
DDR_A _D42
DDR_A _D43
DDR_A _D44
DDR_A _D45
DDR_A _D46
DDR_A _D47
DDR_A _D48
DDR_A _D49
DDR_A _D50
DDR_A _D51
DDR_A _D52
DDR_A _D53
DDR_A _D54
DDR_A _D55
DDR_A _D56
DDR_A _D57
DDR_A _D58
DDR_A _D59
DDR_A _D60
DDR_A _D61
DDR_A _D62
DDR_A _D63
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
SA_DQ[41]
AJ9
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
AL9
SA_DQ[46]
AL8
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
V6
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
RSVD_TP[10]
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A _DQS#0
DDR_A _DQS#1
DDR_A _DQS#2
DDR_A _DQS#3
DDR_A _DQS#4
DDR_A _DQS#5
DDR_A _DQS#6
DDR_A _DQS#7
DDR_A _DQS0
DDR_A _DQS1
DDR_A _DQS2
DDR_A _DQS3
DDR_A _DQS4
DDR_A _DQS5
DDR_A _DQS6
DDR_A _DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DD R0 <12>
M_CLK_DD R#0 <12>
DDR_CKE 0_DIMMA <12>
M_CLK_DD R1 <12>
M_CLK_DD R#1 <12>
DDR_CKE 1_DIMMA <12>
DDR_C S0_DIMMA# <12>
DDR_C S1_DIMMA# <12>
M_ODT0 <12>
M_ODT1 <12>
DDR_A _DQS#[0.. 7] <12>
DDR_ A_DQS[0.. 7] <12>
DDR_A _MA[0..15] <12>
DDR _B_D[0..6 3]<13>
DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B _D10
DDR_B _D11
DDR_B _D12
DDR_B _D13
DDR_B _D14
DDR_B _D15
DDR_B _D16
DDR_B _D17
DDR_B _D18
DDR_B _D19
DDR_B _D20
DDR_B _D21
DDR_B _D22
DDR_B _D23
DDR_B _D24
DDR_B _D25
DDR_B _D26
DDR_B _D27
DDR_B _D28
DDR_B _D29
DDR_B _D30
DDR_B _D31
DDR_B _D32
DDR_B _D33
DDR_B _D34
DDR_B _D35
DDR_B _D36
DDR_B _D37
DDR_B _D38
DDR_B _D39
DDR_B _D40
DDR_B _D41
DDR_B _D42
DDR_B _D43
DDR_B _D44
DDR_B _D45
DDR_B _D46
DDR_B _D47
DDR_B _D48
DDR_B _D49
DDR_B _D50
DDR_B _D51
DDR_B _D52
DDR_B _D53
DDR_B _D54
DDR_B _D55
DDR_B _D56
DDR_B _D57
DDR_B _D58
DDR_B _D59
DDR_B _D60
DDR_B _D61
DDR_B _D62
DDR_B _D63
DDR_B_BS 0<13>
DDR_B_BS 1<13>
DDR_B_BS 2<13>
DDR_B _CAS#<13>
DDR_B _RAS#<13>
DDR_B _WE#<13>
AM5
AM6
AR3
AN3
AN2
AN1
AN9
AN8
AR6
AR5
AR9
AJ11
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA10
JCPU 1D
AE2
SB_CLK[0]
AD2
DDR SYSTEM MEMORY B
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B _DQS#0
DDR_B _DQS#1
DDR_B _DQS#2
DDR_B _DQS#3
DDR_B _DQS#4
DDR_B _DQS#5
DDR_B _DQS#6
DDR_B _DQS#7
DDR_B _DQS0
DDR_B _DQS1
DDR_B _DQS2
DDR_B _DQS3
DDR_B _DQS4
DDR_B _DQS5
DDR_B _DQS6
DDR_B _DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
AP3
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
M_CLK_DD R2 <13>
M_CLK_DDR#2 <13>
DDR_CKE 2_DIMMB <13>
M_CLK_DD R3 <13>
M_CLK_DDR#3 <13>
DDR_CKE 3_DIMMB <13>
DDR_CS2_D IMMB# <13>
DDR_CS3_D IMMB# <13>
M_ODT2 <13>
M_ODT3 <13>
DDR_B _DQS#[0.. 7] <13>
DDR_ B_DQS[0.. 7] <13>
DDR_B _MA[0..15] <13>
D
C
B
DRAMRST_CNTRL <10>
Deciphered Date
TYCO_20 13620-2_IV Y BRIDGE
2
Title
Size Doc ument Number Re v
Cus tom
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
LA-7986P
1
of
7 62Wedn esday, August 08, 2012
A
1.0
TYCO_20 13620-2_IV Y BRIDGE
R36
@
0_0402_5%
1
2
D
S
1
3
Q2
G
LBSS138LT1G_SOT-23-3
2
1
C35
0.047U 16V K X7R 0402
2
DDR3_ DRAMRST#_R
5
H_DRAMRST#
4.99K_0402_1%
2
R39
1
DRAMRST_CNTRL
H_DRAMRST#<6>
A
+1.5V
1
R37
1K_0402_5%
R38
2
1K_0402_5%
1
2
Eiffel used 0.01u
Module design used 0.047u
4
DRAM RST_CNTRL_PCH<15>
DDR3_DR AMRST# <12,13>
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
R40 0_0402_5%
3
R02
@
2
DRAMRST_CNTRL
2011/06/15 2012/07/11
Compal Secret Data
5
4
3
2
1
CFG Straps for Processor
CFG2
D
JCPU1E
RESERVED
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD_NCTF10
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
AK28
CFG[0]
AK29
CFG2
CFG4
CFG5
CFG6
CFG7
+VCC_GFXCORE_AXG
+VCC_C ORE
R253
C
49.9_0402_1%
2
R252
49.9_0402_1%
2
1
1
R82 100_0402_1%@
1
R88 100_0402_1%@
2
1
2
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
Nee d PWR a dd ne w cir cu it on 1.0 5V(r efer CRB )
VSS_AXG_VAL_SENSE
Check
R255
49.9_0402_1%
INTEL 12/28 recommand
to add RC120, RC121, RC122, RC123
B
Please place as close as JCPU1
2
1
VSS_VAL_SENSE
2
R257
49.9_0402_1%
1
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
TYCO_20 13620-2_IV Y BRIDGE
CFG
Interl reque st AH2 6 s hor t GND
check on EVT ph ase
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
KEY
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
R60 0_0402_5%
@
1
2
R02
PEG Static Lane Reversal - CFG2 is for the 16x
T13PAD
CFG2
*
Display Port Presence Strap
CFG4
*
N13M@
PCIE Port Bifurcation Straps
11: (Def aul t) x1 6 - Devic e 1 functi ons 1 and 2 disabled
CFG[6:5 ]
*
10: x8, x8 - Devi ce 1 funct ion 1 enab led ; func tion 2
01: Rese rve d - ( Device 1 function 1 disabled ; function
00: x8,x 4,x 4 - Devi ce 1 funct ions 1 and 2 enable d
1
R41
1K_0402_1%
2
1: N orma l O peration ; Lane # definition matches
sock et p in map def inition
0:La ne Revers ed
CFG4
1K_0402_1%
1
R42
@
1K_0402_1%
2
1 : Disa bled; No Physi cal Displa y Port
atta ched to Embe dded Displ ay Port
0 : Enab led ; An ext ernal Disp lay Port d evice is
conn ecte d to the Embed ded Displa y Port
CFG6
CFG5
1
1
R43
2
R44
@
1K_0402_1%
2
disabled
2 enabled)
CFG7
1
@
2
R45
1K_0402_1%
D
C
B
PEG DEFER TRAINING
1: ( Defa ult ) PEG Train imme diately fo llowing xx RESETB
CFG7
de as sertion
A
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
0: P EG W ait for BIOS for t raining
Title
PROCESSOR(4/7) RSVD,CFG
Size Doc ument Number Re v
Cus tom
LA-7986P
2
Date: Sheet
Compal Electronics, Inc.
1
8 62Wedn esday, August 08, 2012
A
1.0
of
5
4
3
2
1
+VCC_C ORE
JCPU 1F
QC=94A
DC=53A
D
C
B
A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
POWER
CORE SUPPLY
PEG AND DDR
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
+V1.05S_VCCP
8.5A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
H_CPU _SVIDALRT#
H_CPU _SVIDCLK
H_CPU _SVIDDAT
0.1U_0402_10V6K
R47 43_0402_5%
1
2
1
2
1
2
R50 130_0402_5%
1
2
C99
R480_0402_5% @
R490_0402_5% @
1
2
+V1.05S_VCCP
1
R46
75_0402_5%
2
+V1.05S_VCCP
VR_SVID_CLK
VR_SVID_ALR T# <55>
VR_SV ID_CLK <55>
VR_SVID_DAT <55>
0.1u F on po wer side
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
Trace Impedance =27-33 ohm
Trace Length Matc < 25 mils
VCCS ENSE_R
AJ35
VSSSENSE_R
AJ34
B10
VSSIO_SENSE_L
A10
R74 & R79 put toget her
VSS_SENCE 100ohm +-1% pull-down to GND near processor
1
2
1
2
VSSIO_SENSE
R74
1
2
10_0402_1%
@
VSSIO_SENSE_L <53 >
R52 0_0402_5%@
R53 0_0402_5%@
R79
2
10_0402_1%
VCCIO_ SENSE <52,53>
+V1.05S_VCCP
1
series -resistors close to VR
+VCC_ CORE
1
R51
100_0402_1%
2
R66
1
100_0402_1%
1
@
R54
2
100_0402_1%
2
VCCSENS E <55>
VSSSENSE <55>
D
C
B
A
TYCO_20 13620-2_IV Y BRIDGE
5
4
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
3
Compal Secret Data
Deciphered Date
Title
PROCESSOR(5/7) PWR,BYPASS
Size Doc ument Number Re v
Cus tom
LA-7986P
2
Date: Sheet
9 62Wedn esday, August 08, 2012
1
1.0
of
5
4
3
2
1
+1.5V
R668
@
1
SUSP<46,53,54>
R667
@
100K_0402_5%
2
2
R580_0402_5% @
G
2
R590_0402_5% @
+3VALW
1
2
RUN_O N_CPU1.5VS 3#
1
D
Q7
2N7002_SOT23
S
3
D
CPU1.5V_S3_ GATE<42,46,53>
SUSP#<25,42, 46,51,52,53,54>
C
B
1
1
0_0402_5%
@
2
Check
+VSB
1
R03
R56
82K_0402_5%
2
1
D
Q4
2
G
2N7002_SOT23
S
3
RUN_O N_CPU1.5VS3# <6>
+VCC_GFXCORE_AXG
@
1
PAD- OPEN 4x4m
U3
DMN3030LSS-13_S OP8L-8
8
7
6
5
RUN_O N_CPU1.5VS 3
JCPU 1G
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
VAXG13
AP23
VAXG14
AP21
VAXG15
AP20
VAXG16
AP18
VAXG17
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
AN18
VAXG23
AN17
VAXG24
AM24
VAXG25
AM23
VAXG26
AM21
VAXG27
AM20
VAXG28
AM18
VAXG29
AM17
VAXG30
AL24
VAXG31
AL23
VAXG32
AL21
VAXG33
AL20
VAXG34
AL18
VAXG35
AL17
VAXG36
AK24
VAXG37
AK23
VAXG38
AK21
VAXG39
AK20
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48
AH24
VAXG49
AH23
VAXG50
AH21
VAXG51
AH20
VAXG52
AH18
VAXG53
AH17
VAXG54
J1
2
4
1
1
15K_0402_1%
R57
330K_0402_5%
@
2
+1.5V _CPU_VDDQ
1
AP4800
2
Id=9.6A
3
R02
R885
2
1
2
POWER
GRAPHICS
220_0402_5%
2N7002_SOT23
C97
0.047U_0603_25 V7K
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
DDR3 -1.5V RAILS
@
R55
@
Q3
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
1
2
1
D
G
S
3
AK35
AK34
AL1
B4
D1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
1
@
C92
0.1U_0402_10V 6K
2
RUN_O N_CPU1.5VS 3#
2
+VCC_GFXCORE_AXG
1
R616
10_0402_1%
2
1
R626
10_0402_1%
2
+V_SM_VREF_CNT
+V_D DR_REFA_R
+V_D DR_REFB_R
+VCCSA
1
R89
100_0402_1%
2
1
2
1
2
VCC_AXG_SENSE <55>
@
VSS_AXG_SENSE <55>
+V_SM_VREF should
have 2 0 mil t race width
C117
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C118
10U_0603_6.3V6M
1
1
2
2
10U
C125
10U_0603_6.3V6M
10U_0603_6.3V6M
C124
1
1
2
2
Q6
1
D
LBSS138LT1G_SOT-23-3
+VREF_DQ_DI MMA
+VREF_DQ_DI MMB
DRAMR ST_CNTRL
LBSS138LT1G_SOT-23-3
R670
1
1
R671
1
D
2
G
S
3
Q9
@
@
S
3
0_0402_5%~D
2
0_0402_5%~D
2
1K_0402_1%
R353
2
G
@
M3 Cir cuit ( Processor Generated SO-DIMM VREF_DQ)
RUN_O N_CPU1.5VS 3
Q5- or ign al p art
AP2 30 2GN -HF _SOT23-3
SB5 23 020210
G
2
1
3
D
S
R61
@
1
0_0402_5%
+1.5V
PMV45EN_SOT23-3
Q5
@
2
C98
0.1U_0402_10V 6K
C119
C120
10U_0603_6.3V6M
1
2
C127
10U_0603_6.3V6M
C126
1
2
1
2
+1.5 V_CPU_VDDQ
C121
10U_0603_6.3V6M
1
1
2
2
+VCCSA
1
+
C128
330U_D2 _2.5VY_R9M
2
+1.5 V_CPU_VDDQ
1
R67
1K_0402_1%
2
1
R78
1K_0402_1%
2
1
C122
10U_0603_6.3V6M
+
C123
330U_2.5V_M
2
@
DRAMR ST_CNTRL
+V_D DR_REFA_R
+V_D DR_REFB_R
1
1
R64
1K_0402_1%
@
2
2
+V_SM_VREF
+1.5 V_CPU_VDDQ
C396
@
0.1U_0402_10V 6K
1
2
C129
@
0.1U_0402_10V 6K
1
2
C96
0.1U_0402_10V 6K
1
2
C95
0.1U_0402_10V 6K
1
2
+1.5V
1
R62
1K_0402_1%
2
1
R63
1K_0402_1%
2
DRAMRST _CNTRL <7>
D
@
C
@
B
SA RAIL
+1.8VS
R69 0_0805_5%
1
2
@
VCCIO_SEL
H23
C22
C24
A19
H_VCC SA_VID0 <52>
H_VCC SA_VID1 <52>
@
1
R68 0_0402_5%
10U
C154
22U_0805_6.3V6M
1
1
@
2
2
C130
10U_0603_6.3V6M
C345
22U_0805_6.3V6M
1
@
2
1
2
C131
1U_0402_6.3V6K
1.5A
+1.8VS_VCCP LL
C132
1U_0402_6.3V6K
1
2
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
TYCO _2013620-2_IVY BRIDGE
1.8V RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
2
H_VCCP_ SELH_VCCP_SELH_VCCP_S ELH_VCCP_SELH_VCCP_S ELH _VCCP_SELH_VCCP _SELH_VCCP_SELH_VCCP_ SELH_VCCP_SEL
+VCCSA_SENS E <52>
10K_0402_5%
@
1
2
R77 0_0402_5%
R02
+3VALW
+3VS
2
2
R75
R76
@
10K_0402_5%
1
1
VCCP _PWRCTRL <52>
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
Compal Secret Data
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
Deciphered Date
2
Title
PROCESSOR(6/7) PWR
Size Doc ument Number Re v
Cust om
LA-7986P
Date : Sheet
1
of
10 62Wed nesday, August 08, 201 2
A
1.0
3
JC PU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
TYC O_201 3620- 2_IVY BRIDGE
VSS
Compal Secret Data
2011/06/15 2012/07/11
3
Deciphered Date
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
4
AJ22
VSS81
AJ19
VSS82
AJ16
VSS83
AJ13
VSS84
AJ10
VSS85
AJ7
VSS86
AJ4
VSS87
AJ3
VSS88
AJ2
VSS89
AJ1
VSS90
AH35
VSS91
AH34
VSS92
AH32
VSS93
AH30
VSS94
AH29
VSS95
AH28
VSS96
AH25
VSS98
AH22
VSS99
AH19
VSS100
AH16
VSS101
AH7
VSS102
AH4
VSS103
AG9
VSS104
AG8
VSS105
AG4
VSS106
AF6
VSS107
AF5
VSS108
AF3
VSS109
AF2
VSS110
AE35
VSS111
AE34
VSS112
AE33
VSS113
AE32
VSS114
AE31
VSS115
AE30
VSS116
AE29
VSS117
AE28
VSS118
VSS
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
5
JCP U1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
D
C
B
A
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
TYC O_201 3620- 2_IVY BRIDGE
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
2
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
Compal Electronics, Inc.
Title
PROCESSOR(7/7) VSS
Size Docu ment Num ber R ev
Cus tom
LA-7986P
Dat e: Sheet
1
D
C
B
A
1.0
o f
11 62We dnesda y, Augus t 08, 2 012
1
+VR EF_D Q_DIMMA
D
C
B
A
R7 1
1K_ 0402_1%
+1.5 V
1
R7 0
1K_ 0402_1%
2
1
2
3
+1.5 V
1
2
1
R7 3
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Lay ou t N ote:
Pl ace near DIM M
+1.5 V
C1 38
10U_ 0603_ 6.3V6M
C1 39
C1 37
10U_ 0603_ 6.3V6M
1
@
@
2
Lay ou t N ote:
Pl ace near DIM M
+0.7 5VS
@
C1 50
1U_0 402_6 .3V6K
C1 51
1U_0 402_6 .3V6K
1
2
2011/06/15 2012/07/11
10U_ 0603_ 6.3V6M
1
2
C1 52
1U_0 402_6 .3V6K
1
2
1
1
2
2
@
C1 53
1U_0 402_6 .3V6K
1
1
2
2
Compal Secret Data
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
SDA
SCL
VTT2
4
+1.5 V
2
DD R_A _D4
4
DD R_A _D5
6
8
DD R_A_ DQS# 0
10
DD R_A _DQS 0
12
14
DD R_A _D6
16
DD R_A _D7
18
20
DD R_A _D12
22
DD R_A _D13
24
26
DD R_A_ DM1
28
DD R3_DR AMRS T#
30
32
DD R_A _D14
34
DD R_A _D15
36
38
DD R_A _D20
40
DD R_A _D21
42
44
DD R_A_ DM2
46
48
DD R_A _D22
50
DD R_A _D23
52
54
DD R_A _D28
56
DD R_A _D29
58
60
DD R_A_ DQS# 3
62
DD R_A _DQS 3
64
66
DD R_A _D30
68
DD R_A _D31
70
72
DDR_ CKE1 _DIM MA
74
76
DDR_ A_MA 15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_ A_MA 14
DDR_A_MA 11
DDR_ A_M A7
DDR_A_MA6
DDR_ A_M A4
DDR_ A_M A2
DDR_ A_M A0
M _CLK_ DDR1
M _CLK_ DDR#1
DD R_A_ BS1
DD R_A_ RAS#
DDR_ CS0_ DIMM A#
M_OD T0
M_OD T1
DD R_A _D36
DD R_A _D37
DD R_A_ DM4
DD R_A _D38
DD R_A _D39
DD R_A _D44
DD R_A _D45
DD R_A_ DQS# 5
DD R_A _DQS 5
DD R_A _D46
DD R_A _D47
DD R_A _D52
DD R_A _D53
DD R_A_ DM6
DD R_A _D54
DD R_A _D55
DD R_A _D60
DD R_A _D61
DD R_A_ DQS# 7
DD R_A _DQS 7
DD R_A _D62
DD R_A _D63
SMB _DATA_S3
SMB _CLK_S 3
4
+0.7 5VS
0.
0. 65 A @0 . 75 V
65 A @0 . 75 V
0.0.
65 A @0 . 75 V65 A @0 . 75 V
DD R3_DR AMRS T# <7,13 >
DDR_ CKE1 _DIM MA <7>
M_ CLK_D DR1 <7>
M_C LK_DD R#1 <7>
DD R_A_B S1 <7>
DD R_A_ RAS# <7>
DDR_ CS0_ DIMM A# <7>
M_ODT 0 <7>
M_ODT 1 <7>
0.1U _0402 _10V6K
C1 35
1
2
VDDQ(1 .5V) =
3*330u f / 12 m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER C ONNECTOR)
VTT(0. 75V) =
3*0805 10uf
VREF =
1*0402 0.1uf
VDDSPD (3.3V )=
1*0402 0.1uf 1*0402 2.2uf
SMB_ DATA_S3 < 13,15 ,36>
SMB _CLK_S3 < 13,15 ,36>
1
2
+VR EF_C A
2.2U _0603 _6.3V 4Z
C1 36
DD R_A _D[0 ..63]<7>
DD R_A _DQS [0..7 ]<7>
DD R_A_ DQS# [0..7 ]<7>
DDR_ A_MA [0.. 15]<7>
R7 2
1K_ 0402_1%
1K_ 0402_1%
4*0402 1uf
1*0402 2.2uf
5
+1.5 V
3A @
3A @ 1. 5 V
1. 5 V
3A @3A @
1. 5 V1. 5 V
DDR3 SO-DIMM A
2.2U _0603 _6.3V 4Z
C1 34
1
1
2
2
DDR_ CKE0 _DIM MA<7>
DD R_A_B S2<7>
M_ CLK_D DR0<7>
M_C LK_DD R#0<7>
DD R_A_B S0<7>
DD R_A_ WE#<7>
DD R_A_ CAS#<7>
DDR_ CS1_ DIMM A#<7>
+3VS
5
+VR EF_D Q_DIMM A
0.1U _0402 _10V6K
1
2
DD R_A _D0
C1 33
DD R_A _D1
DD R_A_ DM0
DD R_A _D2
DD R_A _D3
DD R_A _D8
DD R_A _D9
DD R_A_ DQS# 1
DD R_A _DQS 1
DD R_A _D10
DD R_A _D11
DD R_A _D16
DD R_A _D17
DD R_A_ DQS# 2
DD R_A _DQS 2
DD R_A _D18
DD R_A _D19
DD R_A _D24
DD R_A _D25
DD R_A_ DM3
DD R_A _D26
DD R_A _D27
DDR_ CKE0 _DIM MA
DD R_A_ BS2
DDR_ A_MA 12
DDR_ A_M A9
DDR_A_MA8
DDR_ A_M A5
DDR_ A_M A3
DDR_ A_M A1
M _CLK_ DDR0
M _CLK_ DDR#0
DDR_ A_MA 10
DD R_A_ BS0
DD R_A _WE#
DD R_A_ CAS#
DDR_ A_MA 13
DDR_ CS1_ DIMM A#
DD R_A _D32
DD R_A _D33
DD R_A_ DQS# 4
DD R_A _DQS 4
DD R_A _D34
DD R_A _D35
DD R_A _D40
DD R_A _D41
DD R_A_ DM5
DD R_A _D42
DD R_A _D43
DD R_A _D48
DD R_A _D49
DD R_A_ DQS# 6
DD R_A _DQS 6
DD R_A _D50
DD R_A _D51
DD R_A _D56
DD R_A _D57
DD R_A_ DM7
DD R_A _D58
DD R_A _D59
R8 1
1
2
10K _0402_5%
2.2U _0603 _6.3V 4Z
0.1U _0402 _10V6K
C1 55
C1 56
1
2
10K _0402_5%
1
2
JDI MM1
1
VREF_DQ
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
29
DQS1
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
R8 3
205
RESET#
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VREF_CA
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
EVENT#
VDDSPD
SA1
VTT1
G1
FOX _AS0 A626-U4SN -7F
E
@
M
2
(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)OSCAN
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
C1 40
10U_ 0603_ 6.3V6M
C1 41
10U_ 0603_ 6.3V6M
1
1
2
2
7/28 U pdate conne ct GND directly
DD R_A_ DM0
DD R_A_ DM1
DD R_A_ DM2
DD R_A_ DM3
DD R_A_ DM4
DD R_A_ DM5
DD R_A_ DM6
DD R_A_ DM7
Deciphered Date
2
C1 43
10U_ 0603_ 6.3V6M
C1 42
10U_ 0603_ 6.3V6M
1
2
Lay ou t N ote:
Pl ace near DIM M
C1 46
0.1U _0402 _10V6K
C1 47
C1 44
10U_ 0603_ 6.3V6M
C1 45
0.1U _0402 _10V6K
1
1
2
2
0.1U _0402 _10V6K
1
1
2
2
Title
Size D ocum ent N umber Re v
Cu sto m
Da te: She et
Compal Electronics, Inc.
1
EVT Ch eck
C1 48
0.1U _0402 _10V6K
1
1
+
C1 49
@
220U _6.3V_M
2
2
DDRIII-SODIMM SLOT1
LA-7986P
1
12 62We dnesd ay, Augus t 08 , 201 2
D
C
B
A
1. 0
o f
+VR EF_D Q_DIMMB
D
For Arr anale only +VREF_DQ_DIMMB
s
upply fr om a exter nal 1. 5V vol tage d ivide
circuit.
C
B
A
+1.5V
1
2
1
2
@
R8 4
1K_ 0402_1%
@
R8 5
1K_ 0402_1%
1
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C1 71
1
2
C1 72
1
@
2
DDRIII-SODIMM SLOT2
LA-7986P
1
o f
13 62We dnesd ay, Augus t 08 , 201 2
D
C
B
A
1. 0
+1.5 V
10U_ 0603_6. 3V6M
C1 64
@
@
C1 76
1U_0 402_6 .3V6K
1
2
Deciphered Date
2
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
10U_ 0603_6. 3V6M
C1 65
1
2
DD R_B_ DM0
DD R_B_ DM1
DD R_B_ DM2
DD R_B_ DM3
DD R_B_ DM4
DD R_B_ DM5
DD R_B_ DM6
DD R_B_ DM7
10U_ 0603_6. 3V6M
C1 66
1
@
2
Lay ou t N ote:
Pl ace near DIM M
10U_ 0603_6. 3V6M
1
@
2
2
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C1 68
C1 67
1
1
@
@
@
2
2
0.1U _0402 _10V6K
0.1U _0402 _10V6K
C1 70
C1 69
1
1
@
@
2
2
Title
Size D ocum ent N umber Re v
Da te: She et
Compal Electronics, Inc.
DD R_B _D[0 ..63]<7>
DD R_B _DQS [0..7 ]<7>
DD R_B_ DQS# [0..7 ]<7>
DDR_ B_MA [0.. 15]<7>
+1.5 V
@
R8 6
1K_ 0402_1%
@
@
R8 7
1K_ 0402_1%
4*0402 1uf
1*0402 2.2uf
3
Lay ou t N ote:
1
2
1
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Pl ace near DIM M
10U_ 0603_6. 3V6M
10U_ 0603_6. 3V6M
C1 61
C1 62
1
@
2
@
C1 74
1U_0 402_6 .3V6K
1
2
C1 63
1
@
2
@
C1 75
1U_0 402_6 .3V6K
1
2
Compal Secret Data
1
@
2
Lay ou t N ote:
Pl ace near DIM M
+0.7 5VS
@
C1 73
1U_0 402_6 .3V6K
1
2
2011/06/15 2012/07/11
VSS1
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
4
+1.5 V
2
DD R_B _D4
4
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DD R_B _D5
DD R_B_ DQS# 0
DD R_B _DQS 0
DD R_B _D6
DD R_B _D7
DD R_B _D12
DD R_B _D13
DD R_B_ DM1
DD R3_DR AMRS T#
DD R_B _D14
DD R_B _D15
DD R_B _D20
DD R_B _D21
DD R_B_ DM2
DD R_B _D22
DD R_B _D23
DD R_B _D28
DD R_B _D29
DD R_B_ DQS# 3
DD R_B _DQS 3
DD R_B _D30
DD R_B _D31
DDR_ CKE3 _DIM MB
DDR_ B_MA 15
DDR_ B_MA 14
DDR_B_MA 11
DDR_ B_M A7
DDR_B_MA6
DDR_ B_M A4
DDR_ B_M A2
DDR_ B_M A0
M _CLK_ DDR3
M _CLK_ DDR#3
DD R_B_ BS1
DD R_B_ RAS#
DDR_ CS2_ DIMM B#
M_OD T2
M_OD T3
DD R_B _D36
DD R_B _D37
DD R_B_ DM4
DD R_B _D38
DD R_B _D39
DD R_B _D44
DD R_B _D45
DD R_B_ DQS# 5
DD R_B _DQS 5
DD R_B _D46
DD R_B _D47
DD R_B _D52
DD R_B _D53
DD R_B_ DM6
DD R_B _D54
DD R_B _D55
DD R_B _D60
DD R_B _D61
DD R_B_ DQS# 7
DD R_B _DQS 7
DD R_B _D62
DD R_B _D63
SMB _DATA_S3
SMB _CLK_S 3
0.
0. 65 A @0 . 75 V
65 A @0 . 75 V
0.0.
65 A @0 . 75 V65 A @0 . 75 V
DD R3_DR AMRS T# <7,12 >
DDR_ CKE3 _DIM MB <7>
M_ CLK_D DR3 <7>
M_C LK_DD R#3 <7>
DD R_B_B S1 <7>
DD R_B_ RAS# <7>
DDR_ CS2_ DIMM B# <7>
M_ODT 2 <7>
M_ODT 3 <7>
+VR EF_C B
2.2U _0603 _6.3V 4Z
0.1U _0402 _10V6K
C1 60
C1 59
1
1
2
2
@
VDDQ(1 .5V) =
3*330u f / 12 m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER C ONNECTOR)
VTT(0. 75V) =
3*0805 10uf
1*0402 0.1uf
VDDSPD (3.3V )=
1*0402 0.1uf 1*0402 2.2uf
SMB_D ATA_S3 < 12,15, 36>
SMB _CLK_S3 < 12,15 ,36>
+0.7 5VS
5
3A @
3A @ 1. 5 V
1. 5 V
3A @3A @
1. 5 V1. 5 V
+1.5 V
+VR EF_D Q_DIMM B
DD R_B _D0
0.1U _0402 _10V6K
2.2U _0603 _6.3V 4Z
1
C1 58
@
2
DDR_ CKE2 _DIMM B<7>
DDR_ B_BS 2<7 >
M_ CLK_D DR2<7>
M_C LK_DD R#2<7>
DDR_ B_BS 0<7 >
DD R_B_ WE#<7>
DD R_B_ CAS#<7>
DDR_ CS3_ DIMM B#<7>
2.2U _0603 _6.3V 4Z
+3VS
1
2
5
DD R_B _D1
DD R_B_ DM0
1
C1 57
@
DD R_B _D2
DD R_B _D3
2
DD R_B _D8
DD R_B _D9
DD R_B_ DQS# 1
DD R_B _DQS 1
DD R_B _D10
DD R_B _D11
DD R_B _D16
DD R_B _D17
DD R_B_ DQS# 2
DD R_B _DQS 2
DD R_B _D18
DD R_B _D19
DD R_B _D24
DD R_B _D25
DD R_B_ DM3
DD R_B _D26
DD R_B _D27
DDR_ CKE2 _DIM MB
DD R_B_ BS2
DDR_ B_MA 12
DDR_ B_M A9
DDR_B_MA8
DDR_ B_M A5
DDR_ B_M A3
DDR_ B_M A1
M _CLK_ DDR2
M _CLK_ DDR#2
DDR_ B_MA 10
DD R_B_ BS0
DD R_B _WE#
DD R_B_ CAS#
DDR_ B_MA 13
DDR_ CS3_ DIMM B#
DD R_B _D32
DD R_B _D33
DD R_B_ DQS# 4
DD R_B _DQS 4
DD R_B _D34
DD R_B _D35
DD R_B _D40
DD R_B _D41
DD R_B_ DM5
DD R_B _D42
DD R_B _D43
DD R_B _D48
DD R_B _D49
DD R_B_ DQS# 6
DD R_B _DQS 6
DD R_B _D50
DD R_B _D51
DD R_B _D56
DD R_B _D57
DD R_B_ DM7
DD R_B _D58
DD R_B _D59
@
R9 5
1
2
10K _0402_5%
1
0.1U _0402 _10V6K
C1 78
C1 77
@
@
1
2
2
R9 7 10 K_0402 _5%
@
JDI MM2
1
VREF_DQ
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
29
DQS1
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
61
VSS22
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX _AS0 A626-U8SN -7F
ME@
5
W=20mi lsW=20mi ls
+RTCVCC
R99
1K_0402_5%
1
C179
1U_0603_1 0V4Z
2
D
1
+RTCBATT
2
1
CLRP1
SHOR T PADS
2
C180
18P_0402_5 0V8J
4
1
R98 10M_040 2_5%
Y1
1
1
2
PCH_RTC X1
2
2
PCH_RTC X2
32.76 8KHZ_ 12.5PF_CM31532 768DZFT
1
C181
18P_0402_5 0V8J
2
3
2
1
D
+RTCVCC
R101 1M_0402_5%
1
R102 330K_0402_ 5%
1
INTVRMEN
H Inte grate
：：：：
*
L Inte grate d VR
：：：：
2
2
d VRM en able
SM_ INTRUDER#
PCH _INTVRMEN
M disabl e
(INTVR MEN should alw ays be pull high.)
+3VS
R105 1K_0402_5%@
1
HIGH= Enable ( No Reboot )
LOW= D isable (Default)
*
C
+3V_PCH
R106 1K_0402_5%@
Low = Disab led (D efault)
*
High = Enabled [Fla sh Des criptor Sec urity Overide]
+3V_PCH
R108 1K_0402_5 %
Thi s sig na l has a we ak i nter nal pull -dow n
On Di e P LL V R i s su ppli ed by
1.5 V whe n sma pled hig h
1.8 V whe n samp led low
*
Nee ds to b e pul le d H ig h f or C hief Rive r pl atfr om
HDA _BITCL K_AUDIO<41>
HD A_SYNC _AUD IO<41>
B
HDA _RST_A UDIO#<41>
HDA _SDOU T_AUDIO<41>
+3V_PCH
12
@
R121
200_0402_5 %
PCH_JTA G_TDO
12
@
R125
100_0402_1 %
A
2
1
2
1
2
R112
33_0402_5%
1
R114
33_0402_5%
1
R116
33_0402_5%
1
R118
33_0402_5%
1
+3V_PCH
1
@
R122
200_0402_5 %
2
PCH_JTAG_TM S
1
@
R126
100_0402_1 %
2
2
2
2
2
+3V_PCH
1
2
1
2
HDA _SPKR
HDA _SDOUT
HD A_SYN C
HDA _BIT_CLK
HD A_SYN C_R
HDA_RS T#
HDA _SDOUT
@
R123
200_0402_5 %
PCH _JTAG_TDI
@
R128
100_0402_1 %
DPDG1.1
CMOS
CLRP2
+RTC VCC
C183
1U_0603_1 0V4Z
1
1
1U_0603_1 0V4Z
R107 1K_0402_1%@
+3V_PCH
+5VS
G
3
S
R175
1
0_0402_5%
2
2
C182
HDA _SPKR<41>
HDA _SDIN0<41 >
ME_FLAS H
1
2
1
D
R103 20K_0402_5%
R100 20K_0402_5%
ME_FLAS H<42 >
2
R878
1M_0402_5%
1
check with vender
Del Q10 check with codec
VDDI O using 3VALW
SHORT PAD S
1
1
2
2
CLRP3
SHORT PAD S
1
1
2
2
R109
0_0402_5%
1
2
R26410K_0402_5 % @
2
R110
1
2
51_0402_5%
Q10
LBSS138LT1G_SOT-23 -3
HD A_SYN C
@
2
PCH_RTC X1
PCH_RTC X2
PCH_RTC RST#
PCH_SR TCRST#
SM_ INTRUDER#
PCH _INTVRMEN
HDA _BIT_CLK
HD A_SYN C
HDA _SPKR
HDA_RS T#
HDA _SDIN0
HDA _SDOUT
2
PCH _GPIO33
1
PCH_JTA G_TCK
PCH_JTAG_TM S
PCH _JTAG_TDI
PCH_JTA G_TDO
SPI_ CLK_PCH _R
SPI_SB_C S0#
SPI_SB_C S1#
SPI_ SI
SPI_S O_R
R124;c190 cl ose to U4 .T3 pin
SPI_ CLK_PCH _R
1
R124
33_0402_5%
@
2
C190
22P_0402_5 0V8J
@
U4A
A20
RTCX1
C20
RTCX2
D20
RTCRST #
G22
SRTCRS T#
K22
INTRUDE R#
C17
INTVRME N
N34
HDA_BC LK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RS T#
E34
HDA_SD IN0
G34
HDA_SD IN1
C34
HDA_SD IN2
A34
HDA_SD IN3
A36
HDA_SD O
C36
HDA_DOC K_EN# / GPIO33
N32
HDA_DOC K_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PAN THER-POINT _FCBGA989
HM76@
HM70@
U4
BD82HM70 QPXH C1
SA00005M Q80
LPC_AD0
LDRQ0#
SERIRQ
SATA0RX N
SATA0RX P
SATA0TX N
SATA0TX P
SATA1RX N
SATA1RX P
SATA1TX N
SATA1TX P
SATA2RX N
SATA2RX P
SATA2TX N
SATA2TX P
SATA3RX N
SATA3RX P
SATA3TX N
SATA3TX P
SATA4RX N
SATA4RX P
SATA4TX N
SATA4TX P
SATA5RX N
SATA5RX P
SATA5TX N
SATA5TX P
SATALED #
C38
LPC_AD1
A38
LPC_AD2
B37
LPC_AD3
C37
LPC_FRA ME#
D36
E36
K36
SER IRQ
SER IRQ
V5
AM3
AM1
SATA_ITX_C_DRX_N 0
AP7
SATA_ITX_C_DRX_P0
AP5
AM10
AM8
AP11
AP10
SATA_DTX_C_IRX_N 2
AD7
SATA_DTX_C_IRX_P2
AD5
SATA_ITX_C_DRX_N 2
AH5
SATA_ITX_C_DRX_P2
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
RBIAS_SA TA3
AH1
SATALED #
P3
PCH _GPIO21
V14
BBS_BIT0_ R
P1
SATA_COMP
SATA3_COMP
FWH0 / LA D0
FWH1 / LA D1
FWH2 / LA D2
FWH3 / LA D3
LPC
FWH4 / LF RAME#
LDRQ1# / GPIO23
RTC
SATA 6G
IHDA
SATA
SATAICOM PO
SPI
SATAICOM PI
SATA3RC OMPO
SATA3COM PI
SATA3RB IAS
SATA0GP / GP IO21
SATA1GP / GP IO19
JTAG
LPC_AD0 <36,42 >
LPC_AD1 <36,42 >
LPC_AD2 <36,42 >
LPC_AD3 <36,42 >
LPC_FRA ME# <36,42>
R104 10K_0402_ 5%
2
R111
37.4_0402_1%
1
R113
49.9_0402_1%
1
1
R115
750_0402_1 %
R117 10K_0402_5 %
1
2
R119 10K_0402_5 %
1
2
R187 10K_0402_5 %
1
2
+3VS
R266
1
R221
1
R127
1
R129
1
1
SER IRQ <42>
CAP o n Con n, si de
+1.05VS_VC C_SATA
2
+1.05VS_SATA3
2
2
SPI_WP #1
2
3.3K_0402_5 %
SPI_ HOLD#1
2
3.3K_0402_5 %
SPI_WP #
2
3.3K_0402_5 %
SPI_ HOLD#
2
3.3K_0402_5 %
E
C
and Min i card debug port
+3VS
SATA_DTX_C_IRX_N 0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
C1840.01U_0402_ 25V7K
1
2
1
2
SATA_DTX_C_IRX_N 2 <40>
SATA_DTX_C_IRX_P2 <40>
SATA_ITX_C_DRX_N 2 <40>
SATA_ITX_C_DRX_P2 <40>
+3VS
+3VS
+3VS
C1850.01U_0402_ 25V7K
SATA_ITX_DRX_P0
SPI_SB_C S1#
SPI_S O_R
SPI_SB_C S0#
SPI_S O_R
ODD
R291
0_0402_5%
1
1
R188
33_0402_5%
R130
0_0402_5%
1
1
33_0402_5%
R131
SATA_DTX_C_IRX _N0 <40>
SATA_DTX_C_IRX_P0 <40>
SATA_ITX_DRX_N0 <40>
SATA_ITX_DRX_P0 <40 >
HDD
8MB SPI ROM FOR ME
& Non-share ROM.
2
2
CS1#
SPI_SO1
U
2
2
SPI_WP #1
CS#
SPI_SO_L
U6
1
CS#
2
SO
3
WP#
4
GND
16M W25Q1 6BVSSIG SOIC 8P
VCC
HOLD#
SCLK
8
7
6
5
SI
6 Rersver 4M +2M So lution
U5
SPI_WP #
1
CS#
2
SO
3
WP#
4
GND
32M W25Q3 2BVSSIG SOIC 8P
VCC
HOLD#
SCLK
8
7
6
5
SI
+3VS
SPI_ HOLD#1
SPI_C LK1
SPI_ SI1
+3VS
0.1U _0402_16V4Z
SPI_ HOLD#
SPI_ CLK_PCH
SPI_ SI_R
0_0402_5%
1
1
C191
1
R199
2
R132
0_0402_5%
1
1
SPI_ CLK_PCH _R
2
SPI_ SI
2
R196
33_0402_5%
SPI_ CLK_PCH _R
2
SPI_ SI
2
R133
33_0402_5%
C
B
A
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Size Do cumen t Number Re v
Cu stom
LA-7986P
2
Dat e: S heet
14 62W ednes day, Augu st 08, 2 012
1
1.0
o f
1
SMB_CLK _S3 <12,13,36>
DIMM1
R137
2
2
R138
IMM2
D
MINI CARD
SMB_DATA_S3 <12,13,36>
EC_SMB _CK2 <23,39,42>
VGA
EC
thermal sensor
EC_SMB _DA2 <23,39,42>
2.2K_0402_5 %
PCH_SM L0CLK
PCH_SM L0DATA
2
4
NC
1
R02
1
12P_0402_5 0V8J
2
C197
R544
+3V_PCH
2
1
2
R545
2.2K_0402_5 %
1
D
C
B
+3V_PCH
R139
2
1K_0402_5%
+3V_PCH
PCH_HOT # <42>
2
2
2
2
2
2
2
2
2
2
2
+3V_PCH
DRA MRST_CNTRL _PCH <7>
1
+3V_PCH
+3V_PCH
CLK_REQ_ VGA# <23>
CLK_ PCIE_VGA#
CLK_ PCIE_VGA
PCH_LAN _48M
2.2K_0402_5 %
R136
1
1
R135
2.2K_0402_5 %
2.2K_0402_5 %
R141
1
1
R142
2.2K_0402_5 %
XTAL25_IN
XTAL25_OUT
12P_0402_5 0V8J
Q60A
2N7002DW -T/R7_SOT363-6
6
2
2
3
2N7002DW -T/R7_SOT363-6
Q60B
Q61A
2N7002DW -T/R7_SOT363-6
6
2
2
3
2N7002DW -T/R7_SOT363-6
Q61B
CLK_ PCIE_VGA# <23>
CLK_ PCIE_VGA <23>
1
C196
2
SMB_CLK_S3
1
2.2K_0402_5 %
1
2
+3VS
1
5
2.2K_0402_5 %
SMB_DATA_S3
4
EC_SMB _CK2
1
2
+3VS
5
EC_SMB _DA2
4
1
R169 1M_0402_5%
3
OSC
2
OSC
NC
Y2
25MHZ_10 PF_7V25000014
5
LAN
WLAN
D
USB3.0
C
LAN
WLAN
USB3.0
B
PCIE_PRX_DTX _N1< 37>
PCIE_PRX_DTX_P 1<37>
PCIE_PTX _C_DRX_N1<37>
PCIE_PTX_C_DR X_P1<37>
PCIE_PRX_DTX _N2< 36>
PCIE_PRX_DTX_P 2<36>
PCIE_PTX _C_DRX_N2<36>
PCIE_PTX_C_DR X_P2<36>
PCIE_PRX_DTX _N4< 45>
PCIE_PRX_DTX_P 4<45>
PCIE_PTX _C_DRX_N4<45>
PCIE_PTX_C_DR X_P4< 45>
CLK_ PCIE_LAN#<37>
CLK_ PCIE_LAN<37>
CLKR EQ_LAN#<37>
CLK_ PCIE_WLA N1#<36>
CLK_ PCIE_WLA N1<36>
CLKR EQ_WLAN#<36>
CLK_ PCIE_USB3 0#<45>
CLK_ PCIE_USB3 0<45>
CLKR EQ_USB30#<45>
C192 0.1U_0402_10V7 K
C193 0.1U_0402_10V7 K
C194 0.1U_0402_10V7 K
C195 0.1U_0402_10V7 K
C309 0.1U_0402_1 0V7KEU3@
C308 0.1U_0402_1 0V7KEU3@
R153 0_0402_5%
1
R154 0_0402_5%
1
R151 0_0402_5%
1
R152 10K_0402_ 5%
+3V_PCH
R149 0_0402_5%
1
R150 0_0402_5%
1
R156 0_0402_5%
1
R158 10K_0402_5 %
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
2
R147 10K_0402_ 5%
+3VS
R334 0_0402_5%EU3@
R330 0_0402_5%EU3@
R326 0_0402_5%EU3@
R301 10K_0402_ 5%
R165 10K_0402_ 5%
R168 10K_0402_ 5%
R170 10K_0402_ 5%
R172 10K_0402_ 5%
R174 10K_0402_ 5%
1
2
1
2
1
2
1
2
1
2
1
2
CAP o n Con n, si de
2
2
2
1
2
2
2
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4
PCIE_PRX_DTX _N1
PCIE_PRX_DTX_P 1
PCIE_PTX_DRX _N1
PCIE_PTX_DRX_P 1
PCIE_PRX_DTX _N2
PCIE_PRX_DTX_P 2
PCIE_PTX_DRX _N2
PCIE_PTX_DRX_P 2
PCIE_PRX_DTX _N4
PCIE_PRX_DTX_P 4
PCIE_PTX_DRX _N4
PCIE_PTX_DRX_P 4
CLK_ PCIE_LAN #_R
CLK_ PCIE_LAN _R
CLKR EQ_LAN#_R
CLK_ PCIE_W LAN1#_R
CLK_ PCIE_W LAN1_R
CLKR EQ_WLAN #_R
PCH _GPIO20
CLK_USB 30#
CLK_USB 30
CLKR EQ_USB30#_R
PCH _GPIO26
PCH _GPIO44
PCH _GPIO56
PCH _GPIO45
PCH _GPIO46
PCIE_ CLK_8N
PCIE_ CLK_8P
U4B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_P CIE0N
Y39
CLKOUT_P CIE0P
J2
PCIECLKR Q0# / GPIO73
AB49
CLKOUT_P CIE1N
AB47
CLKOUT_P CIE1P
M1
PCIECLKR Q1# / GPIO18
AA48
CLKOUT_P CIE2N
AA47
CLKOUT_P CIE2P
V10
PCIECLKR Q2# / GPIO20
Y37
CLKOUT_P CIE3N
Y36
CLKOUT_P CIE3P
A8
PCIECLKR Q3# / GPIO25
Y43
CLKOUT_P CIE4N
Y45
CLKOUT_P CIE4P
L12
PCIECLKR Q4# / GPIO26
V45
CLKOUT_P CIE5N
V46
CLKOUT_P CIE5P
L14
PCIECLKR Q5# / GPIO44
AB42
CLKOUT_P EG_B_N
AB40
CLKOUT_P EG_B_P
E6
PEG_B_CL KRQ# / GPIO56
V40
CLKOUT_P CIE6N
V42
CLKOUT_P CIE6P
T13
PCIECLKR Q6# / GPIO45
V38
CLKOUT_P CIE7N
V37
CLKOUT_P CIE7P
K12
PCIECLKR Q7# / GPIO46
AK14
CLKOUT_IT PXDP_N
AK13
CLKOUT_IT PXDP_P
PAN THER-POINT _FCBGA989
SMBUSController
SML1ALE RT# / PCHHOT# / GPIO74
PCI-E*
CLOCKS
3
SMBALE RT# / GPIO11
SML0ALE RT# / GPIO60
SML0DAT A
SML1CLK / GPIO58
SML1DAT A / GPIO75
Link
PEG_A_CL KRQ# / GPIO47
CLKOUT_P EG_A_N
CLKOUT_P EG_A_P
CLKOUT_D MI_N
CLKOUT_D MI_P
CLKOUT_D P_N
CLKOUT_D P_P
CLKIN_DM I_N
CLKIN_DM I_P
CLKIN_GND 1_N
CLKIN_GND 1_P
CLKIN_DOT _96N
CLKIN_DOT _96P
CLKIN_SA TA_N
CLKIN_SA TA_P
REFCLK1 4IN
CLKIN_PC ILOOPBACK
XTAL25_IN
XTAL25_OU T
XCLK_RC OMP
CLKOUTFL EX0 / GPIO64
CLKOUTFL EX1 / GPIO65
CLKOUTFL EX2 / GPIO66
CLKOUTFL EX3 / GPIO67
FLEX CLOCKS
E12
H14
SMBCLK
C9
SMBDAT A
A12
C8
SML0CLK
G12
C13
E14
M16
M7
CL_CLK1
T11
CL_DATA 1
P10
CL_RST1#
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
BIOS Reques t SKU ID
PCH _GPI011
PCH_SM BCLK
PCH_SM BDATA
DRA MRST_CNTR L_PCH
PCH_SM L0CLK
PCH_SM L0DATA
SML1CLK
SML1DATA
PEG_ CLKREQ#_R
CLK_ PCIE_VGA#_R
CLK_ PCIE_VGA_R
CLK_ CPU_DMI#
CLK_ CPU_DMI
CLK_ BUF_CP U_DMI#
CLK_ BUF_CP U_DMI
CLKI N_DMI2#
CLKI N_DMI2
CLK_ BUF_DREF _96M#
CLK_ BUF_DREF _96M
CLK_ BUF_PCIE_SA TA#
CLK_ BUF_PCIE_SA TA
CLK_ BUF_ICH_ 14M
CLK_ PCI_LPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
27M_S SC
LAN_48M
PCH _GPIO67
PCH_HOT #
R140 1 0K_0402_5%
2
+3V_PCH
2
1
1
R134
1
2
10K_0402_5 %
1
R143
10K_0402_5 %
R144 0_0402_5%
1
R145 1 0K_0402_5%
1
2
R146 0_0402_5%
R148 0_0402_5%
R207 2 2_0402_5%@
@
1
2
1
2
CLK_ CPU_DMI# <6>
CLK_ CPU_DMI <6>
R155 10K_0402_ 5%
1
R157 10K_0402_ 5%
1
R159 10K_0402_ 5%
1
R160 10K_0402_ 5%
1
R162 10K_0402_ 5%
1
R163 10K_0402_ 5%
1
R164 10K_0402_ 5%
1
R166 10K_0402_ 5%
1
R167 10K_0402_ 5%
1
CLK_ PCI_LPBACK <18>
+1.0 5VS_VC CDIFFC LKN
R171
90.9_0402_1%
1
2
2
PCH _GPIO67 <19>
A
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
Title
Size Do cumen t Number Re v
Cu stom
2
Dat e: S heet
Compal Electronics, Inc.
PCH (2/9) PCIE, SMBUS, CLK
LA-7986P
1
15 62W ednes day, Augu st 08, 2 012
o f
A
1.0
5
4
3
2
1
D
VGATE<55>
PCH _PWROK
C
AEP WR OK ca n be co nnec t to
PWR OK if i AMT disa ble
PCH_POK
+3VS
+3V_PCH
B
R194 10K_0 402_5%
R195 200K_ 0402_5%
R197 10K_0 402_5%
1
@
@
R556 2 00_0402_5%
2
R192 300_0402_5%
2
2
1
2
R191
0_0402_5%
1
1
1
2
1
2
U15
MC7 4VHC1 G08DFT2G SC70 5P
3
1
G
A
Y
2
B
P
5
+3VS
APWR OK
PM_DRA M_PWRGD
SUS WARN#
AC_PRES ENT_R
PCH_RS MRST#_R
SYS_P WROK
4
1
R180
100K_0402_ 1%
2
SYS_P WROK <6 >
@
DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>
DMI_CRX_PTX_N 0<5>
DMI_CRX_PTX_N 1<5>
DMI_CRX_PTX_N 2<5>
DMI_CRX_PTX_N 3<5>
DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
+1.05VS
R177 4 9.9_0402_1%
R178 7 50_0402_1%
4mil width and place
with in 500 mil of th e PCH
SUS AC K# is o nly use d on pla tfor m
tha t sup po rt th e De ep S x st ate.
+3VS
PCH _PWROK<42>
PCH _APWROK<42>
PM_DRA M_PWRGD<6>
EC_RSM RST#<42>
PBTN_OUT #<42>
AC IN<42 ,49>
PCH _PWROK
R190 0 _0402_5%
R193 0_0402_5%
R198 0_0402_5%
D29
1
CH7 51H-40PT_SOD323 -2
+3V_PCH
1
1
T72
2
R18410K_0402_ 5%
@
1
R02
1
R3020_0402_5%
1
1
2
R200
2
10K_0402_5 %
R201
2
10K_0402_5 %
2
2
2
@
@
R02
@
R02
DMI_CTX_PRX_N 0
DMI_CTX_PRX_N 1
DMI_CTX_PRX_N 2
DMI_CTX_PRX_N 3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N 0
DMI_CRX_PTX_N 1
DMI_CRX_PTX_N 2
DMI_CRX_PTX_N 3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_ IRCOMP
RB IAS_CP Y
SUSACK #
SYS_R ST#
1
SYS_P WROK
PCH_POK
APWR OK
2
PM_DRA M_PWRGD
PCH_RS MRST#_R
2
SUS WARN#
PBTN_OUT #_R
2
AC_PRES ENT_R
PCH _GPIO72
1
RI#
1
U4C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOM P
BG25
DMI_IRCOM P
BH21
DMI2RBIAS
C12
SUSACK #
K3
SYS_RESET #
P12
SYS_PWR OK
L22
PWROK
L10
APWR OK
B13
DRAMPW ROK
C21
RSMRST #
K16
SUSW ARN#/SUSPW RDNACK/GPIO30
E20
PWRB TN#
H20
ACPRES ENT / GPIO31
E10
BATLOW # / GPIO72
A10
RI#
PAN THER-POINT _FCBGA989
DMI
FDI
CLKRUN # / GPIO32
SUS_STA T# / GPIO61
SUSCLK / GP IO62
SLP_S5# / GPIO6 3
System Power Management
SLP_LAN# / GPIO29
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWV RMEN
DPWR OK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS #
PMSYNCH
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
A18
E22
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
FDI_CTX_P RX_N0
FDI_CTX_P RX_N1
FDI_CTX_P RX_N2
FDI_CTX_P RX_N3
FDI_CTX_P RX_N4
FDI_CTX_P RX_N5
FDI_CTX_P RX_N6
FDI_CTX_P RX_N7
FDI_CTX_PRX_ P0
FDI_CTX_PRX_ P1
FDI_CTX_PRX_ P2
FDI_CTX_PRX_ P3
FDI_CTX_PRX_ P4
FDI_CTX_PRX_ P5
FDI_CTX_PRX_ P6
FDI_CTX_PRX_ P7
FD I_INT
FD I_FS YNC0
FD I_FS YNC1
FD I_LSYN C0
FD I_LSYN C1
DSW ODVREN
PCH _DPWROK
WAKE#
PM_CLKR UN#
SUS_STAT#
SLP_A#
PM_SLP_SUS #
H_PM _SYNC
PCH _GPIO29
R02
@
R185 0 _0402_5%
1
2
10K_0402_5 %
1
2
R186
1
2
R261
@
10K_0402_5 %
FDI_CTX_P RX_N0 <5>
FDI_CTX_P RX_N1 <5>
FDI_CTX_P RX_N2 <5>
FDI_CTX_P RX_N3 <5>
FDI_CTX_P RX_N4 <5>
FDI_CTX_P RX_N5 <5>
FDI_CTX_P RX_N6 <5>
FDI_CTX_P RX_N7 <5>
FDI_CTX_PRX_ P0 <5>
FDI_CTX_PRX_ P1 <5>
FDI_CTX_PRX_ P2 <5>
FDI_CTX_PRX_ P3 <5>
FDI_CTX_PRX_ P4 <5>
FDI_CTX_PRX_ P5 <5>
FDI_CTX_PRX_ P6 <5>
FDI_CTX_PRX_ P7 <5>
FDI _INT <5>
FD I_FS YNC0 <5>
FD I_FS YNC1 <5>
FD I_LSYN C0 <5>
FD I_LSYN C1 <5>
R02
R181 0 _0402_5%@
1
T74
T99
T71
H_PM _SYNC < 6>
+3V_PCH
2
PCIE_W AKE# <36,37 ,45>
+3V_PCH
SUSCLK <42>
PM_SLP_S5# <4 2>
PM_SLP_S4# <4 2>
PM_SLP_S3# <4 2>
*
DSW OD VRE N - On Die DSW VR E nabl e
H En
：
able
：
sable
L Di
PCH_RS MRST#_R
R189 8.2K_0402_5 %@
1
2
R299 10K_0402_5 %
1
2
Can b e l eft NC
whe n IAM T i s no t
sup po rt on t he
pla tfr om
+RTC VCC
1
R179
330K_0402_ 5%
2
1
R183
+3VS
330K_0402_ 5%
@
2
Can b e l ef t NC if no use
int eg rat ed L AN.
D
C
B
A
Secur ity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/06/15 2012/07/11
Compal Secret Data
Deciphered Date
Title
Size Do cumen t Number Re v
Cu stom
2
Dat e: S heet
Compal Electronics, Inc.
PCH (3/9) DMI,FDI,PM,
LA-7986P
1
o f
16 62W ednes day, Augu st 08, 2 012
A
1.0
5
+3VS
4
3
2
1
1
2
1
R234
2.2K_0402_5%
2
EDI D_CLK
EDID_D ATA
DAC_B LU<34>
DAC _GRN<34>
DAC _RED<34>
+3VS
PCH_E NBKL<33>
PCH _ENVDD<33>
PCH_P WM<33>
EDID _CLK< 33>
EDID_D ATA<33>
R2042.2K_0402_5%
1
2
R2052.2K_0402_5%
1
2
R2062.37K_0402_1%
1
2
LVDS_ ACLK#<33>
LVDS_ ACLK<33>
LVDS_A0#<33>
LVDS_A1#<33>
LVDS_A2#<33>
LVDS_A0<33>
LVDS_A1<33>
LVDS_A2<33>
R208 150_0402_1%
2
R209 150_0402_1%
2
R210 150_0402_1%
2
CRT_ DDC_CLK< 34>
CRT_ DDC_DATA<34>
CRT _HSYNC<34>
CRT _VSYNC<34>
1
1
1
DAC_B LU
DAC _GRN
DAC _RED
1K_0402_1%
EDI D_CLK
EDID_D ATA
CTRL_CLK
CTRL_DATA
LVDS_ IBG
LVD_V REF
CRT_ DDC_CLK
CRT_ DDC_DATA
CR T_IREF
1
R211
2
D
C
B
R559
2.2K_0402_5%
2.2K_0402_5%
+3VS
1
2
R523
1
R524
2.2K_0402_5%
2
CRT_ DDC_CLK
CRT_ DDC_DATA
U4D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DAT A
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
PANTH ER-POINT_FCBGA989
LVDS
CRT
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDAT A
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDAT A
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
HDMI@
AP39
2.2K_0402_5%
AP40
HD MICLK_NB
P38
HDMIDAT _NB
M39
AT49
AT47
AT40
TMDS_B_DATA2#_PCH
AV42
TMDS_B_DATA2_PCH
AV40
TMDS_B_DATA1#_PCH
AV45
TMDS_B_DATA1_PCH
AV46
TMDS_B_DATA0#_PCH
AU48
TMDS_B_DATA0_PCH
AU47
TMDS_B_CL K#_PCH
AV47
TMDS_B_CL K_PCH
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
1
R202
2
+3VS
1
R203
HDMI@
2.2K_0402_5%
2
HDMIC LK_NB <35>
HDMIDAT _NB <35>
TMDS_B_HPD# <35>
C200 0.1U_0402_10V6KHDMI@
1
C201 0.1U_0402_10V6KHDMI@
C202 0.1U_0402_10V6KHDMI@
C203 0.1U_0402_10V6KHDMI@
C204 0.1U_0402_10V6KHDMI@
C205 0.1U_0402_10V6KHDMI@
C206 0.1U_0402_10V6KHDMI@
C207 0.1U_0402_10V6KHDMI@
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
CAP mo ve on Con n, sid e
HDMI_TX2-_CK <35>
HDMI_TX2+_CK <35>
HDMI_TX1-_CK <35>
HDMI_TX1+_CK <35>
HDMI_TX0-_CK <35>
HDMI_TX0+_CK <35>
HDMI_C LK-_CK <35>
HDMI_C LK+_CK <35>
HDMI
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
D
C
B
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/15 2012/07/11
3
Compal Secret Data
Deciphered Date
Title
PCH (4/9) LVDS,CRT,DP,HDMI
Size Docum ent Number R ev
B
LA-7986P
2
Dat e: Sheet
1
o f
17 62We dnesday, Au gust 08, 20 12
A
1.0
+3VS
5
4
3
2
1
RP2
8
7
6
5
8.2K_0804_8P4R_5%
D
C
GNT1#/
GPIO51
PCH_ WL_OFF#
B
A16 swap overide St rap/T op-Bl ock
Swap Override jumpe r
RP1
8
7
6
5
8.2K_0804_8P4R_5%
R213 8.2K_0402_5%
1
R225 8.2K_0402_5%
1
R292 8.2K_0402_5%@
1
R557 8.2K_0402_5%@
1
R259 8.2K_0402_5%
1
R212 8.2K_0402_5%
1
R214 8.2K_0402_5%@
1
Boot BIOS Strap bit 1 BBS 1
DGPU _PWR_EN_R
PCI_GNT3#
A
PLT_RST#<23,36,37,42,4 5>
PCI_P IRQA#
1
PCI_P IRQD#
2
PCI_P IRQC#
3
PCI_P IRQB#
4
PCH _GPIO2
1
DGPU _PWR_EN_R
2
PCH _GPIO4
3
ODD_ DA#_R
4
2
2
2
2
2
2
2
Bit11
Bit10
0 1
0
1
1
1
0
1
@
1
C208
1U_0402_6.3V4Z
5
*
2
2
0
R319 0_0402_5%
R215 1K_0402_5%@
Low=A16 swap
override/Top-Block
Swap Override enabl ed
High=Default
PCH _GPIO5
PCH_ WL_OFF#
PCH_GP IO51
PCH_GP IO53
DGPU_P WR_EN1
DGPU_H OLD_RST#_R
DGPU_H OLD_RST#_R
Boot BIOS
Destination
Reserved
Reserved
SPI
(Default)
LPC
NVDD _PWR_EN
GPIO55
*
1
1
@
2
2
PPT EDS DOC#474146
USB3_RX1_N<45>
USB3_RX2_N<45>
USB3_RX1_P<45>
USB3_RX2_P<45>
USB3_TX1_N<45>
USB3_TX2_N<45>
USB3_TX1_P<45>
USB3_TX2_P<45>
DGPU_HOLD_R ST#<23>
NVDD _PWR_EN<54>
DGPU_PW R_EN<23,25>
PCH_ WL_OFF#<36>
ODD_DA #<40,42>
CLK_PCI_LPBA CK<15>
CLK_ PCI_EC<42>
CLK_P CI_DB<36>
R222
1
2
0_0402_5%
4
Y
+3VS
R223
100K_0402_5%
3
G
A
B
P
5
MC74VHC1G08DFT2G SC70 5P
PCH_PLTRST#
1
2
U7
@
T1829
T1825
T1832
T1826
T1831
T1827
T1830
T1828
R553 0_0402_5%
1
R692 0_0402_5%
1
R691 0_0402_5%
1
R715 0_0402_5%@
1
PCI_PME#<42>
PCH_PLTRST#<6>
1
1
2
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
2
2
R21922_0402_5%
2
R22022_0402_5%
2
R17322_0402_5% @
1
Issued Date
USB3_RX1_N
USB3_RX2_N
USB3_RX3_N
USB3_RX4_N
USB3_RX1_P
USB3_RX2_P
USB3_RX3_P
USB3_RX4_P
USB3_TX1_N
USB3_TX2_N
USB3_TX3_N
USB3_TX4_N
USB3_TX1_P
USB3_TX2_P
USB3_TX3_P
USB3_TX4_P
PCI_P IRQA#
PCI_P IRQB#
PCI_P IRQC#
PCI_P IRQD#
DGPU_H OLD_RST#_R
DGPU_P WR_EN1
DGPU _PWR_EN_R
PCH_GP IO51
PCH_GP IO53
PCH_ WL_OFF#
PCH _GPIO2
ODD_ DA#_R
PCH _GPIO4
PCH _GPIO5
PCH_PLTRST#
CLK_PCI_L PBACK_R
CLK_ PCI_EC_R
CLK_ PCI_DB_R
2011/06/15 2012/07/11
U4E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3Tp1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
PANTHER-PO INT_FCBGA989
3
RSVD
PCI
USB
Compal Secret Data
Deciphered Date
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N11
USB20_P11
USBR BIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC1#
USB_OC5#
SMIB
USB_OC7#
2
USB DEBUG=PORT1 AND PORT9
USB20_N0 <45>
USB20_P0 <45>
USB20_N1 <45>
USB20_P1 <45>
USB20_N2 <43>
USB20_P2 <43>
USB20_N3 <33>
USB20_P3 <33>
USB20_N8 <40>
USB20_P8 <40>
USB20_N9 <44>
USB20_P9 <44>
USB20_N10 <36>
USB20_P10 <36>
USB20_N11 <43>
USB20_P11 <43>
R218
1
2
22.6_0402_1%
Within 500 mils
Title
Size Document Number R ev
Cus tom
Date : Sheet
LEFT USB
LEFT USB
(USB 3.0)
(CR-B/D USB)
USB Camera
Bluetooth
RIGHT USB
WLAN
CARD READER
USB_OC0# Share with USB_ OC4#
due to same power s witch
USB_OC0# <45>
USB_OC1# <44>
USB_OC1# <44>
SMIB <45>
R03
PCH (5/9) PCI, USB
LA-7986P
USB_OC5#
USB_OC2#
USB_OC7#
USB_OC0#
USB_OC1#
USB_OC3#
SMIB
1
RP310K_1206_8P4R_5%
4
3
2
1
4
3
2
1
RP410K_1206_8P4R_5%
R262
1
10K_0402_5%
of
18 62Wed nesday, Au gust 08, 2012
5
6
7
8
5
6
7
8
2
D
C
B
+3V_PCH
A
1.0
5
D
+3V_ PCH
GP IO28
On-D ie P LL Volt age Regu lator
This sig nal has a w eak int ern al pull up
*
*
PCH_ GPIO 27 (Hav e in ter nal Pull-Hig h)
High : VC CVR M VR Enable
Low: VCC VRM VR Disab le
C
B
Weak in ter nal pu ll-h igh
2
R250
10K_0402_5 %
R547
10K_0402_5 %
@
EC_S MI#
PCH _GPIO28
PCH _GPIO27
+3VS
1
2
1
2
R235 10K_040 2_5%
1
2
H On-Die vol tag e r egu lato r e n
：
：
L On-Die PLL Vo lta ge Regu lat or dis
R240 1K_0402_5%@
1
R245 10K_0402_5 %@
1
2
+3VS
1
R244
@
10K_0402_5 %
2
PCH _GPIO37
1
R881
10K_0402_5 %
2
BIOS Req ues t SKU ID
+3VS
1
2
R246
R711
@
@
R708
A
2
1
2
1
10K_0402_5%
10K_0402_5%
PCH _GPIO38
PCH _GPIO67
1
R298
10K_0402_5%
PCH_GPIO38 PCH_GPIO67
2
10K_0402_5%
PCH _GPIO67 <15>
0
0 1
1
1 1
5
able
able
PCH _GPIO36
0
0
+3VS
+3VS
+3V_ PCH
EC_L ID_OUT#< 42>
DGPU _PWR OK<4 6,54>
PU o n po wer side
+3VS
BT_D ISABLE< 36>
R02
PCH _BT_ON#<36,40>
+3VS
+3VS
+3VS
+3V_ PCH
Functi on
ptimus
O
Res erved
DIS
UMA
4
R233 10K_040 2_5%
1
2
R227 10K_040 2_5%
1
2
R228 10K_040 2_5%
1
2
EC_ SCI#<42>
EC_S MI#<42>
R229 10K_040 2_5%@
1
R02
R297 0 _0402_5%
+3VS
+3VS
+3V_ PCH
R247 10K_0 402_5%
R248 10K_0 402_5%
R249 10K_0 402_5%
R251 10K_0 402_5%
2
R230 1K_040 2_5%
1
2
R231 10K_040 2_5%
1
2
1
2
R232 10K_040 2_1%@
1
2
R238 10K_040 2_5%
1
2
R241
1
2
R242 10K_040 2_5%
1
2
R243 10K_040 2_5%
1
2
1
2
1
2
1
2
1
2
4
ODD _EN<40>
10K_ 0402_5%
PC H_GPIO1
PC H_GPIO6
EC _SCI#
EC_S MI#
PCH _GPIO12
EC_L ID_OUT#
PCH _GPIO16
DGPU _PWR OK_R
BT_D ISABLE
OD D_EN
PCH _GPIO27
PCH _GPIO28
PCH _BT_ON#
PCH _GPIO35
PCH _GPIO36
PCH _GPIO37
PCH _GPIO38
PCH _GPIO39
PCH _GPIO48
PCH _GPIO49
PCH _GPIO57
3
PCH_GPIO69
0
1
U4 F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PW R_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GP IO39
V13
SDATAOUT1 / GP IO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
PAN THER-P OINT_F CBGA989
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
GPIO
Functi on
HM76 by PCH
HM70 by PCH
A20GATE
PECI
RCIN#
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
NC_1
C40
B41
C41
A40
P4
AU16
P5
AY11
AY10
T14
AY1
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
Compal Secret Data
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
PROCPW RGD
CPU/MISC
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
NCTF
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
2011/06/15 2012/07/11
PCH _GPIO69
PCH _GPIO68
PCH _GPIO69
PCH _GPIO70
PCH _GPIO71
PC H_PEC I_R
KBRST#
PCH _THRM TRIP#_R
IN IT3_ 3V
This signal has weak internal PU,can't pull low
NV_C LE
Deciphered Date
2
2
R702
1
10K_0402_5%
2
R707
@
1
10K_0402_5%
R2241 0K_0402_5%
1
@
1
2
R2370_0402_5%
1
R239 3 90_0402_5%
2
PCH _GPIO70
200K _0402_5%
2
2
R703
@
1
2
R705
1
+3VS
2
+3VS
2
1
H_ PECI <6,42>
KBRST# <42>
H_ CPUPW RGD <6>
H_TH RMTRIP#
NV_CLE
Weak in ter nal
PU,D o n ot pul l l ow
1
PCH_GPIO70
0
1
10K_0402_5%
PCH_GPIO71
0
1
R236
10K_0402_5 %
GATEA20 <42>
PCH _THRM TRIP#_R < 23>
DMI Termination Voltage
Set to Vcc when HIGH
Set to Vss when LOW
Title
PCH (6/9) GPIO, CPU, MISC
Size D ocume nt N umber R ev
Cu stom
LA-7986P
Da te: S heet
Functi on
4/15"
1
17"
USB3.0 by PCH
USB3.0 by NEC
KBRST#
R226 10K_0402_5 %
H_TH RMTRIP# <6>
+1.8VS
1
2
1
2
R217 1K_ 0402_5%
CLOSE TO THE BRANCHING POINT
1
R216
2.2K _0402_5%
H_SN B_IVB# <6>
1
Compal Electronics, Inc.
R704
@
PCH _GPIO71
R706
200K _0402_5%
2
19 62We dnesd ay, A ugust 08 , 2012
+3VS+3VS +3V S
2
1
10K_0402_5%
2
D
1
+3VS
C
B
A
1.0
o f
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