Lenovo G575 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

PAWGC / PAWGD Schematics Document

AMD APU Ontario-FT1 + FCH Hudson-M1 + GPU Roberson XT

3 3

2010-11-10

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, I NC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, I NC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document N umber Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

LA6755P/7P

148Tuesday, November 30, 2010

E

1.0

of

A

B

C

D

E

Compal confidential

File Name : PAWGC/D

For PAWGC

1. POWER BOARD

2. Card Reader BOARD

1 1

LVDS Conn.

page 10

CRT Conn.

page 12

AMD Brazos APU

FT1

Memory BUS(DDRIII)

Single Channel

1.5V DDRIII 1333

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 8,9

BGA 413-Ball

AMD Robson

VRAM 64*16

DDR3*4

page 18 ~ 24

2 2

HDMI Conn.

page 11

x4 PCI-E GPP GEN2

4 * x1 PCI-E 2.0

WLAN &WiMax

page 30

GIGA LAN

AR8151/8152

page 25,26

3 3

PCI Express Mini card Slot 1

WLAN/WiMAX

page 30

USB(WiMAX)

PCI-E(WLAN)

SPI ROM

page 15

Touch Pad

19mm x 19mm

x4 UMI Gen. 1

2.5GT/s per lane

Hudson M1

BGA 605-Ball 23mm x 23mm

page 13,14,15,16,17

EC

ENE KB930

page 32

page 5,6,7

LPC BUS

page 31

AZALIA

14*USB2.0

6*SATA serial

Int.KBD

page 32

SPI ROM

page 33

Audio Codec

CX20671

page 27

2Channel Speaker

Internal MIC

Audio Jacks

page 27

Stereo HeadPhone Output

CMOS Camera

page 10

BlueTooth CONN

USB PORT 2.0 x3(Left)

USB PORT 2.0 x1(Right)

Microphone Input

page 34

page 35

WLAN/WiMAX

Card Reader

Realtek RTS5139 SD/MMC/MS/MS Pro/XD

ESATA HDD AND USB CONN (Left)

SATA3.0 HDD CONN

page 29

page 34

For PAWGD

1. POWER BOARD

2. Card reader BOARD

3. 4*LED+SW(3pin) +SW(4pin) BOARD

4. ODD BOARD

Thermal Sensor

4 4

EMC1403

page 28

SATA ODD CONN

page 29

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

LA6755P/7P

248Tuesday, November 30, 2010

E

1.0

of

A

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

1 1

2 2

+APU_CORE_NB 1.0V switched power rail ON OFF

+1.5V

+0.75VS 0.75VS s witched power rail for DDR terminator

+1.0VS

+1.1VS 1.1VS switched power rail ON OFF OFF

+1.8VS 1.8V switched power rail

+3VALW

+3V_LAN 3.3V power rail for LAN ON ON(WOL) OFF

+3VS

+5VALW

+5VS

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU (0.7-1.2V)

1.5V power rail for CPU VDDIO and DDRIII

1.0V switched power rail for NB VDDC & VGA

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

EC SM Bus2 address

Address Address

0001-011xb

HEX

Device

EMC1412-2 (dGPU )

EMC1403-2(DDR,WLAN)

SB-TSI

B

S1 S3 S5

N/A N/A N/A

ON OFF

ON

ON OFF OFF

ON

1111-100xb

1001-101xb

1001-100xb

N/AN/AN/A

OFF

ON

OFF

ON ON*

OFF

ON

ON*

OFF

OFFON

ONON

ON ON*ON+1.1VALW 1.1V always on power rail

HEX

F8H15H

9AH

98H

C

FCH Hudson-M1 USB Port List

USB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

NC

Left USB1

USB Camera

Left(Combo)

Left USB2

Right USB

BT

CardReader

Mini-PCIE

NC

Brazos PCIE Port List

PCIE0

APUFCH

PCIE1

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

GPU PCIE x4

LAN

WLAN

NC

D

FCH Hudson-M1 SATA Port List

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

HDD

ODD

eSATA

NC

BOM Structure

UMA@ : UMA only PX@ : DIS muxluss

- PX3@ : PX3.0 only

- BACO@ : Baco only

GIGA@ : AR8151

E

8152@ : AR8152

SM Bus Controller 0

Device Address

APU SIC/SID (FCH_SMB3)

H_THERMTRIP# (FCH_ALERT#)

(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)

HEX

CMOS@ : USB camera HDMI@ : HDMI function nonHDMI@ : w/o HDMI function ESATA@: eSATA function BT@ : BT function ME@ : ME components X76@, H1G@, H512@, S1G@, S512@ : VRAM 45@ : 45 Level

3 3

SM Bus Controller 1

Device Address HEX

DDR DIMM1 (FCH_SMB0)

DDR DIMM2 (FCH_SMB0)

WLAN (FCH_SMB0)

1001-000xb

1001-001xb

(FCH_SMB0)





HWM@ : hardware monitor function nonHWM@: w/o hardware monitor function

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

LA6755P/7P

348Tuesday, November 30, 2010

E

1.0

of

5

Power-Up/Down Sequence

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.

2. VDDR3 should ramp-up before or simultaneously with VDDC.

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before

D D

DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up.

5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)

4

3

2

1

tŝƚŚŽƵƚKŽƉƚŝŽŶ

Wͺ'W/KϬ>ŽǁͲхZĞƐĞƚĚ'Wh,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ Wͺ'W/Kϭ>ŽǁͲхĚ'WhWŽǁĞƌK&&,ŝŐŚͲхĚ'WhWŽǁĞƌKE

KŽƉƚŝŽŶ

Wͺ'W/KϬ,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ;Ě'WhŝƐŶŽƚƌĞƐĞƚŽŶKŵŽĚĞͿ Wͺ'W/Kϭ>ŽǁͲхĚ'WhWŽǁĞƌK&&,ŝŐŚͲхĚ'WhWŽǁĞƌKE;ĂůǁĂǇƐ,ŝŐŚͿ

Ě'WhWŽǁĞƌWŝŶƐ DĂǆĐƵƌƌĞŶƚ

W/ͺWsW/ͺsZd^ssZϰsͺd WͺWsW΀&΁ͺsϭϴW΀΁ͺWs W΀΁ͺsϭϴssϭ/ϮsYsϮ/ W>>ͺWsDWsϭϴĂŶĚ^Wsϭϴ

W΀&΁ͺsϭϬW΀΁ͺsϭϬW>>ͺsĂŶĚ

sŽůƚĂŐĞ

ϭϴs

ϭϬs

WyϯϬ

K&&

KDŽĚĞ

KE

ϭϲϳϵŵ

ϱϳϱŵ

^WsϭϬ

VDDR3(3.3VGS)

Note: Do not drive any IOs before VDDR3 is ramped up.

W/ͺs

sZϯĂŶĚϮs

/&ͺs;ĐƵƌƌĞŶƚĐŽŶƐƵŵƉƚŝŽŶсϱϱŵΛϭϬsŝŶ

PCIE_VDDC(1.0V)

KŵŽĚĞͿ

sZϭ

C C

VDDR1(1.5VGS)

ss/

ϭϬs

ϯϯs

^ĂŵĞĂƐ s

ϭϱs

ϭϭϮs

K&&

KE

KE ^ĂŵĞĂƐ W/ͺs

K&&

Ϯ

ϭϵϬŵ

ϳϬŵ

Ϯϴ

ϭϮϵ

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

ŝ'Wh

PERSTb

REFCLK

B B

Straps Reset

Straps Valid

PE_GPIO0 PE_EN

Ě'Wh

BIF_VDDC

PE_GPIO1

нϯϯs>t

нϭϬs

MOS

Regulator

нϯϯs'^

ϭ

нϭϬs'^

Ϯ

PX_mode

нϭϱs

K^ǁŝƚĐŚ

SI4800

нϭϱs'^

ϯ

Global ASIC Reset

н

нϭϴs

T4+16clock

A A

Security Classific ation

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/30 2012/07/14

3

Compal Secret Data

Deciphered Date

SI4800

2

нϭϴs'^

ϱ

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

B

Date: Sheet

Compal Electronics, Inc.

Regulator

dGPU Block Diagram

LA6755P/7P

ϰ

1

нs'ͺKZ

PWRGOOD

448Tuesday, November 30, 2010

of

1.0

5

+1.8VS

R404 300_0402_5%R404 300_0402_5%

D D

R399 1K_0402_5%R399 1K_0402_5% R400 1K_0402_5%R400 1K_0402_5% R405 300_0402_5%R405 300_0402_5% R401 300_0402_5%R401 300_0402_5% R402 510_0402_1%R402 510_0402_1% R403 1K_0402_5%R403 1K_0402_5%

+3VS

R811 10K_0402_5%R811 10K_0402_5%

R812 10K_0402_5%R812 10K_0402_5%

R410 1K_0402_5%R410 1K_0402_5%

R411 1K_0402_5%R411 1K_0402_5%

R412 1K_0402_5%R412 1K_0402_5%

R414 1K_0402_5%R414 1K_0402_5%

C C

EC_PROCHOT#(31)

B B

APU_THERMTRIP#

If FCH internal pull-up disabled, level-shifter could be deleted. Need BIOS to disable internal pull-up!!

A A

12 1 2 1 2

12

12 1 2 1 2

1 2

R425

1K_0402_5%

2N7002DW-T/R7_SOT363-6

APU_DBREQ# APU_SVC APU_SVD LDT_RST# APU_PWRGD TEST_25_L TEST36

HDMI_DATA

HDMI_CLK

APU_PROCHOT#

APU_ALERT#_R

APU_SIC

APU_SID

R807 0_0402_5%@R807 0_0402_5%@

1 2

R808 0_0402_5%R808 0_0402_5%

1 2

+3VS

12

R424

R424 10K_0402_5%

10K_0402_5%

B

2

1 2

E

3 1

C

MMBT3904_NL_SOT23-3

1 2

R427 0_0402_5%@R427 0_0402_5%@

+3VS

12

R428

R428 10K_0402_5%

10K_0402_5%

@

2

@

61

Q80A

1 2

R431 0_0402_5%R431 0_0402_5%

5

@

EC_SMB_CKAPU_SIC

3

4

Q80B

1 2

R434 0_0402_5%R434 0_0402_5%

5

APU_PROCHOT#

Connection to EC, FCH input need to pull-down

Q79

H_THERMTRIP# (14)

2N7002DW-T/R7

Vgs(th): min 1.0V

If Q80 or R429, R432 implemented, R747 & R748 need to be mounted

EC_SMB_DAAPU_SID

@

1 2

R429 0_0402_5%

1 2

R430 0_0402_5%R430 0_0402_5%

@

1 2

R432 0_0402_5%

1 2

R433 0_0402_5%R433 0_0402_5%

Typ 1.6V Max 2.0V

FCH_SID

EC_SMB_DA2

FCH_SIC

EC_SMB_CK2

HDMI_TX2P(11)

HDMI_TX2N(11)

HDMI_TX1P(11)

HDMI_TX1N(11)

HDMI_TX0P(11)

HDMI_TX0N(11)

HDMI_CLKP(11)

HDMI_CLKN(11)

APU_ALERT#_FCH(15)FCH_PROCHOT#(13) APU_ALERT#_EC(31)

APU_VDDNB_RUN_FB_H(44)

APU_VDD0_RUN_FB_H(44)

APU_VDD0_RUN_FB_L(44)

FCH_SID (14)

EC_SMB_DA2 (19,29,31)

FCH_SIC (14)

EC_SMB_CK2 (19,29,31)

4

C508 0.1U_0402_16V7KC508 0.1U_0402_16V7K

1 2

C509 0.1U_0402_16V7KC509 0.1U_0402_16V7K

1 2

C510 0.1U_0402_16V7KC510 0.1U_0402_16V7K

1 2

C511 0.1U_0402_16V7KC511 0.1U_0402_16V7K

1 2

C512 0.1U_0402_16V7KC512 0.1U_0402_16V7K

1 2

C513 0.1U_0402_16V7KC513 0.1U_0402_16V7K

1 2

C514 0.1U_0402_16V7KC514 0.1U_0402_16V7K

1 2

C515 0.1U_0402_16V7KC515 0.1U_0402_16V7K

1 2

APU_CLK(13) APU_CLK#(13)

DISP_CLK(13) DISP_CLK#(13)

APU_SVC(44) APU_SVD(44)

LDT_RST#(13) APU_PWRGD(13)

R418 0_0402_5%@R418 0_0402_5%@ R873 0_0402_5%R873 0_0402_5%

T93PADT93PAD T94PADT94PAD

Close to APU

T0 FCH

4

LVDS_A2(10) LVDS_A2#(10)

LVDS_A1(10) LVDS_A1#(10)

LVDS_A0(10) LVDS_A0#(10)

LVDS_ACLK(10) LVDS_ACLK#(10)

1 2 1 2

TO EC

T77PADT77PAD

3

U22B

HDMI_TX2P_C HDMI_TX2N_C

HDMI_TX1P_C HDMI_TX1N_C

HDMI_TX0P_C HDMI_TX0N_C

HDMI_CLKP_C HDMI_CLKN_C

APU_PROCHOT# APU_THERMTRIP#

APU_ALERT#_R

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

APU_SIC APU_SID

U22B

A8

TDP1_TXP0

B8

TDP1_TXN0

B9

TDP1_TXP1

A9

TDP1_TXN1

D10

TDP1_TXP2

C10

TDP1_TXN2

A10

TDP1_TXP3

B10

TDP1_TXN3

B5

LTDP0_TXP0

A5

LTDP0_TXN0

D6

LTDP0_TXP1

C6

LTDP0_TXN1

A6

LTDP0_TXP2

B6

LTDP0_TXN2

D8

LTDP0_TXP3

C8

LTDP0_TXN3

V2

CLKIN_H

V1

CLKIN_L

D2

DISP_CLKIN_H

D1

DISP_CLKIN_L

J1

SVC

J2

SVD

P3

SIC

P4

SID

T3

RESET_L

T4

PWROK

U1

PROCHOT_L

U2

THERMTRIP_L

T2

ALERT_L

N2

TDI

N1

TDO

P1

TCK

P2

TMS

M4

TRST_L

M3

DBRDY

M1

DBREQ_L

F4

VDDCR_NB_SENSE

G1

VDDCR_CPU_SENSE

F3

VDDIO_MEM_S_SENSE

F1

VSS_SENSE

B4

RSVD_1

W11

RSVD_2

V5

RSVD_3

ONTARIO-2M161000-1.6G_BGA413

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

DISPLAYPORT 1

DISPLAYPORT 0

CLK

SER

JTAG CTRL

+1.8VS

R842

1K_0402_5%

1 2

APU_TRST#

2010/06/30 2012/06/30

3

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

DP MISC

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_REDB

DAC_GREEN

DAC_GREENB

DAC_BLUE

DAC_BLUEB

DAC_HSYNC DAC_VSYNC

VGA DAC

DAC_SCL DAC_SDA

DAC_ZVSS

TEST4 TEST5

TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19

TEST25_H

TEST25_L

TEST28_H

TEST

TEST28_L

TEST31

TEST33_H

TEST33_L

TEST34_H

TEST34_L

TEST35 TEST36 TEST37

TEST38

DMAACTIVE_L

need to pop for HDT debug 20101012

@

0_0402_5%

R846

1 2

R847 10K_0402_5%@R 847 10K_0402_5%@

R848 10K_0402_5%@R 848 10K_0402_5%@

R849 10K_0402_5%@R 849 10K_0402_5%@

Compal Secret Data

R398 150_0402_1%R398 150_0402_1%

H3

G2 H2 H1

HDMI_CLK

B2

HDMI_DATA

C2

C1

EDID_CLK

A3

EDID_DATA

B3

R406 100K_0402_5%R406 100K_0402_5%

D3

C12

R407 150_0402_1%R407 150_0402_1%

D13 A12

R408 150_0402_1%R408 150_0402_1%

B12 A13

R409 150_0402_1%R409 150_0402_1%

B13

E1 E2

F2 D4

R413 499_0402_1%R413 499_0402_1%

D12

R1 R2 R6 T5

TEST15

E4 K4 L1

TEST18

L2

TEST19

M2

TEST25_H

K1

TEST_25_L

K2

TEST28_H

L5

TEST28_L

M5

TEST31

M21

TEST33_H

J18

TEST33_L

J19

Delete Test point for layout limitation

U15

20100818

T15

TEST35

H4

TEST36

N5

TEST37

R5

K3 T1

APU_TRST#_R

12

Deciphered Date

2

1 2

T66

PAD

T67

PAD

T68

PAD

R415 1K_0402_5%@R415 1K_0402_5%@

1 2

T69

PAD

T95

PAD

R416 1K_0402_5%R416 1K_0402_5%

1 2

R417 1K_0402_5%R417 1K_0402_5%

1 2

R419 510_0402_1%R419 510_0402_1%

1 2

T71

PAD

T72

PAD

T73

PAD

C516 0.1U_0402_16V4ZC516 0.1U_0402_16V4Z

1 2

C517 0.1U_0402_16V4ZC517 0.1U_0402_16V4Z

1 2

R422 1K_0402_5%

1 2

nonHDMI@

R958 1K_0402_5%

1 2

T76

PAD

R423 1K_0402_5%R423 1K_0402_5%

1 2

HDMI@

AMD Debug

2

1

APU_ENBKL (10) APU_ENVDD (10) APU_BLPWM (10)

HDMI_CLK (11)

HDMI_DATA (11)

HDMI_DET (11)

EDID_CLK (10) EDID_DATA (10)

DAC_RED (12)

DAC_GRN (12)

DAC_BLU (12)

CRT_HSYNC (12) CRT_VSYNC (12)

CRT_DDC_CLK (12) CRT_DDC_DATA (12)

AMD check list update 20101110

R420 51_0402_1%R420 51_0402_1%

1 2

R421 51_0402_1%R421 51_0402_1%

1 2

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWRGD

LDT_RST#

APU_DBRDY

APU_DBREQ#

J108_PLLTST0

J108_PLLTST1

+1.8VS

R843 1K_0402_5%R843 1K_0402_5%

R844 1K_0402_5%R844 1K_0402_5%

R845 1K_0402_5%R845 1K_0402_5%

R850 300_0402_5%@R850 300_0402_5%@

1 2

R851 0_0402_5%@R851 0_0402_5%@

1 2

R852 0_0402_5%@R852 0_0402_5%@

1 2

12

Pull-high to enable HDMI function 20100812

ALLOW_STOP# (13)

+1.8VS

Please be noted about TEST_18 and TEST_19

need to pop for HDT debug 20101012

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

)7&75/'3&57

/$33

1

TEST_19

TEST_18

548Tuesday, November 30, 2010

+1.8VS

1.0

of

A

U22E

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6

4 4

3 3

2 2

DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0(8,9) DDR_A_BS1(8,9) DDR_A_BS2(8,9)

DDR_A_DQS0(8,9)

DDR_A_DQS#0(8,9)

DDR_A_DQS1(8,9)

DDR_A_DQS#1(8,9)

DDR_A_DQS2(8,9)

DDR_A_DQS#2(8,9)

DDR_A_DQS3(8,9)

DDR_A_DQS#3(8,9)

DDR_A_DQS4(8,9)

DDR_A_DQS#4(8,9)

DDR_A_DQS5(8,9)

DDR_A_DQS#5(8,9)

DDR_A_DQS6(8,9)

DDR_A_DQS#6(8,9)

DDR_A_DQS7(8,9)

DDR_A_DQS#7(8,9)

DDR_A_CLK0(8) DDR_A_CLK#0(8) DDR_A_CLK1(8) DDR_A_CLK#1(8) DDR_B_CLK2(9) DDR_B_CLK#2(9) DDR_B_CLK3(9) DDR_B_CLK#3(9)

DDR_RST#(8,9)

DDR_EVENT#(8,9)

DDR_CKE0(8,9) DDR_CKE1(8,9)

DDR_A_ODT0(8) DDR_A_ODT1(8) DDR_B_ODT0(9) DDR_B_ODT1(9)

DDR_CS0_DIMMA#(8) DDR_CS1_DIMMA#(8) DDR_CS0_DIMMB#(9) DDR_CS1_DIMMB#(9)

DDR_A_RAS#(8,9) DDR_A_CAS#(8,9) DDR_A_WE#(8,9)

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3

DDR_RST# DDR_EVENT#

DDR_CKE0 DDR_CKE1

DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

U22E

R17

M_ADD0

H19

M_ADD1

J17

M_ADD2

H18

M_ADD3

H17

M_ADD4

G17

M_ADD5

H15

M_ADD6

G18

M_ADD7

F19

M_ADD8

E19

M_ADD9

T19

M_ADD10

F17

M_ADD11

E18

M_ADD12

W17

M_ADD13

E16

M_ADD14

G15

M_ADD15

R18

M_BANK0

T18

M_BANK1

F16

M_BANK2

D15

M_DM0

B19

M_DM1

D21

M_DM2

H22

M_DM3

P23

M_DM4

V23

M_DM5

AB20

M_DM6

AA16

M_DM7

A16

M_DQS_H0

B16

M_DQS_L0

B20

M_DQS_H1

A20

M_DQS_L1

E23

M_DQS_H2

E22

M_DQS_L2

J22

M_DQS_H3

J23

M_DQS_L3

R22

M_DQS_H4

P22

M_DQS_L4

W22

M_DQS_H5

V22

M_DQS_L5

AC20

M_DQS_H6

AC21

M_DQS_L6

AB16

M_DQS_H7

AC16

M_DQS_L7

M17

M_CLK_H0

M16

M_CLK_L0

M19

M_CLK_H1

M18

M_CLK_L1

N18

M_CLK_H2

N19

M_CLK_L2

L18

M_CLK_H3

L17

M_CLK_L3

L23

M_RESET_L

N17

M_EVENT_L

F15

M_CKE0

E15

M_CKE1

W19

M0_ODT0

V15

M0_ODT1

U19

M1_ODT0

W15

M1_ODT1

T17

M0_CS_L0

W16

M0_CS_L1

U17

M1_CS_L0

V16

M1_CS_L1

U18

M_RAS_L

V19

M_CAS_L

V17

M_WE_L

ONTARIO-2M161000-1.6G_BGA413

DDR SYSTEM MEMORY

B

M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7

M_DATA8

M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15

M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23

M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31

M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39

M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47

M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55

M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63

M_VREF

M_ZVDDIO_ME M_S

B14 A15 A17 D18 A14 C14 C16 D16

C18 A19 B21 D20 A18 B18 A21 C20

C23 D23 F23 F22 C22 D22 F20 F21

H21 H23 K22 K21 G23 H20 K20 K23

N23 P21 T20 T23 M20 P20 R23 T22

V20 V21 Y23 Y22 T21 U23 W23 Y21

Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18

AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15

M23

M22

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

+MEM_VREF

R437

39.2_0402_1%

C

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

PCIE_CRX_GTX_P0(18) PCIE_CRX_GTX_N0(18)

PCIE_CRX_GTX_P1(18) PCIE_CRX_GTX_N1(18)

PCIE_CRX_GTX_P2(18) PCIE_CRX_GTX_N2(18)

PCIE_CRX_GTX_P3(18) PCIE_CRX_GTX_N3(18)

+1.0VS

UMI_RX0P(13) UMI_RX0N(13)

UMI_RX1P(13) UMI_RX1N(13)

UMI_RX2P(13) UMI_RX2N(13)

UMI_RX3P(13) UMI_RX3N(13)

12

+1.5V

R435 2K_0402_1%R435 2K_0402_1%

Less than 1"

1 2

DDR_A_D[0..63] (8,9)

DDR_A_MA[0..15] (8,9)

DDR_A_DM[0..7] (8,9)

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

P_ZVDD_10

U22A

AA6

P_GPP_RXP0

Y6

P_GPP_RXN0

AB4

P_GPP_RXP1

AC4

P_GPP_RXN1

AA1

P_GPP_RXP2

AA2

P_GPP_RXN2

Y4

P_GPP_RXP3

Y3

P_GPP_RXN3

Y14

P_ZVDD_10

AA12

P_UMI_RXP0

Y12

P_UMI_RXN0

AA10

P_UMI_RXP1

Y10

P_UMI_RXN1

AB10

P_UMI_RXP2

AC10

P_UMI_RXN2

AC7

P_UMI_RXP3

AB7

P_UMI_RXN3

ONTARIO-2M161000-1.6G_BGA413

PCIE I/F

UMI I/F

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3 P_GPP_TXN3

P_ZVSS

P_UMI_TXP0 P_UMI_TXN0

P_UMI_TXP1 P_UMI_TXN1

P_UMI_TXP2 P_UMI_TXN2

P_UMI_TXP3 P_UMI_TXN3

D

PCIE_CTX_C_GRX_P0

AB6

PCIE_CTX_C_GRX_N0

AC6

PCIE_CTX_C_GRX_P1

AB3

PCIE_CTX_C_GRX_N1

AC3

PCIE_CTX_C_GRX_P2

Y1

PCIE_CTX_C_GRX_N2

Y2

PCIE_CTX_C_GRX_P3

V3

PCIE_CTX_C_GRX_N3

V4

P_ZVSS

AA14

UMI_TX0P_C

AB12

UMI_TX0N_C

AC12

UMI_TX1P_C

AC11

UMI_TX1N_C

AB11

UMI_TX2P_C

AA8

UMI_TX2N_C

Y8

UMI_TX3P_C

AB8

UMI_TX3N_C

AC8

C518 0.1U_0402_16V7KC518 0.1U_0402_16V7K

1 2

C519 0.1U_0402_16V7KC519 0.1U_0402_16V7K

1 2

C520 0.1U_0402_16V7KC520 0.1U_0402_16V7K

1 2

C521 0.1U_0402_16V7KC521 0.1U_0402_16V7K

1 2

C522 0.1U_0402_16V7KC522 0.1U_0402_16V7K

1 2

C523 0.1U_0402_16V7KC523 0.1U_0402_16V7K

1 2

C524 0.1U_0402_16V7KC524 0.1U_0402_16V7K

1 2

C525 0.1U_0402_16V7KC525 0.1U_0402_16V7K

1 2

R436 1.27K_0402_1%R436 1.27K_0402_1%

1 2

Less than 1"

C526 0.1U_0402_16V7KC526 0.1U_0402_16V7K

1 2

C527 0.1U_0402_16V7KC527 0.1U_0402_16V7K

1 2

C528 0.1U_0402_16V7KC528 0.1U_0402_16V7K

1 2

C529 0.1U_0402_16V7KC529 0.1U_0402_16V7K

1 2

C530 0.1U_0402_16V7KC530 0.1U_0402_16V7K

1 2

C531 0.1U_0402_16V7KC531 0.1U_0402_16V7K

1 2

C532 0.1U_0402_16V7KC532 0.1U_0402_16V7K

1 2

C533 0.1U_0402_16V7KC533 0.1U_0402_16V7K

1 2

E

PCIE_CTX_GRX_P0 (18) PCIE_CTX_GRX_N0 (18)

PCIE_CTX_GRX_P1 (18) PCIE_CTX_GRX_N1 (18)

PCIE_CTX_GRX_P2 (18) PCIE_CTX_GRX_N2 (18)

PCIE_CTX_GRX_P3 (18) PCIE_CTX_GRX_N3 (18)

UMI_TX0P (13) UMI_TX0N (13)

UMI_TX1P (13) UMI_TX1N (13)

UMI_TX2P (13) UMI_TX2N (13)

UMI_TX3P (13) UMI_TX3N (13)

+1.5V

R444

1 2

1K_0402_5%

1 1

DDR_EVENT#

A

R438

1K_0402_1%

R439

1K_0402_1%

1 2

1

C534

1000P_0402_50V7K

2

1 2

Place within 1000 mils to APU 20100526

B

C535

+MEM_VREF

1

0.1U_0402_16V4Z

2

Security Classifica tion

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELEC TRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED T O ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PART Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/0630

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

FT1 DDRIII/UMI/PCIE

LA6755P/7P

E

648Tuesday, November 30, 2010

of

1.0

5

4

3

2

1

+APU_CORE

U22C

11A

E5

VDDCR_CPU_1

E6

VDDCR_CPU_2

F5

VDDCR_CPU_3

F7

VDDCR_CPU_4

G6

VDDCR_CPU_5

G8

VDDCR_CPU_6

H5

VDDCR_CPU_7

H7

VDDCR_CPU_8

J6

VDDCR_CPU_9

J8

VDDCR_CPU_10

L7

VDDCR_CPU_11

M6

VDDCR_CPU_12

M8

VDDCR_CPU_13

N7

VDDCR_CPU_14

R8

VDDCR_CPU_15

10A

E8

VDDCR_NB_1

E11

VDDCR_NB_2

E13

VDDCR_NB_3

F9

VDDCR_NB_4

F12

VDDCR_NB_5

G11

VDDCR_NB_6

G13

VDDCR_NB_7

H9

VDDCR_NB_8

H12

VDDCR_NB_9

K11

VDDCR_NB_10

K13

VDDCR_NB_11

L10

VDDCR_NB_12

L12

VDDCR_NB_13

L14

VDDCR_NB_14

M11

VDDCR_NB_15

M12

VDDCR_NB_16

M13

VDDCR_NB_17

N10

VDDCR_NB_18

N12

VDDCR_NB_19

N14

VDDCR_NB_20

P11

VDDCR_NB_21

P13

VDDCR_NB_22

2A

G16

VDDIO_ MEM_S_1

G19

VDDIO_ MEM_S_2

E17

VDDIO_ MEM_S_3

J16

VDDIO_ MEM_S_4

L16

VDDIO_ MEM_S_5

L19

VDDIO_ MEM_S_6

N16

VDDIO_ MEM_S_7

R16

VDDIO_ MEM_S_8

R19

VDDIO_ MEM_S_9

W18

VDDIO_ MEM_S_10

U16

VDDIO_ MEM_S_11

ONTARIO-2M161000-1.6G_BGA413

1

C589

2

1

C595

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C590

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C597

2

1

C596

2

CPU CORE

DAC

GPU AND NB CORE

POWER

DDR3

C598

1U_0402_6.3V6K

TSense/PLL/DP/PCIE/IO

VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6 VDD_18_7

VDD_18_DAC

DIS PLL

VDDPL_10

PCIE/IO/DDR3 Phy

VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4

DP Phy/IO

1

2

1U_0402_6.3V6K

10U_0603_6.3V6M

0.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C544

2

1

C554

2

1

D D

C539

2

1

C550

2

1

C559

2

+APU_CORE_NB

C C

C575

C582

C591

B B

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

1

C536

2

1

C551

2

1

C560

2

1

C576

2

1

C583

2

1

C592

2

POWER

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

+1.0VS

1

C541

2

1

C552

2

1

C561

2

1

C577

2

1

C584

2

1

C593

2

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

C542

C553

C562

C578

C585

C594

1

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

1

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

1

C543

2

1

C563

2

1

C579

2

1

C586

2

10U_0603_6.3V6M

180P_0402_50V8J

1

C587

2

180P_0402_50V8J

1

C540

2

1

C555

2

1

C588

2

10U_0603_6.3V6M

+APU_CORE_NB

180P_0402_50V8J

+APU_CORE

+1.5V

VDD_33

2A

+VDD_18

U8 W8 U6 U9 W6 T7 V7

0.15A

+VDD_18_DAC

W9

0.2A

+VDDL_10

U11

5.5A

U13 W13 V12 T12

0.5A

A4

+VDD_10

1

C545

2

1

C556

2

1

C564

2

1

C568

2

1

C580

2

1

C537

C546

2

0.1U_0402_16V7K

180P_0402_50V8J

1

C557

C558

2

180P_0402_50V8J

1U_0402_6.3V6K

1

C565

C566

2

0.1U_0402_16V7K

180P_0402_50V8J

1

C570

C569

2

0.1U_0402_16V7K

180P_0402_50V8J

1

C581

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

2

1

2

1

2

1

2

+3VS

1

C538

C547

2

1U_0402_6.3V6K

Change from SM010014520 to SD002000080 20100816

L30

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

1

C567

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C571

C572

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C549

C548

2

1U_0402_6.3V6K

10U_0603_6.3V6M

+1.8VS

12

+1.0VS has been raised to +1.05VS for AMD design guide 45339_R1.02 update 20101004

FBMA-L11-201209-221LMA30T_0805

1

C573

C574

2

1U_0402_6.3V6K

10U_0603_6.3V6M

+1.8VS

L29

12

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

+1.0VS

L31

12

L32

12

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

U22D

A7

VSS_1

B7

VSS_2

B11

VSS_3

B17

VSS_4

B22

VSS_5

C4

VSS_6

D5

VSS_7

D7

VSS_8

D9

VSS_9

D11

VSS_10

D14

VSS_11

B15

VSS_12

D17

VSS_13

D19

VSS_14

E7

VSS_15

E9

VSS_16

E12

VSS_17

E20

VSS_18

F8

VSS_19

F11

VSS_20

F13

VSS_21

G4

VSS_22

G5

VSS_23

G7

VSS_24

G9

VSS_25

G12

VSS_26

G20

VSS_27

G22

VSS_28

H6

VSS_29

H11

VSS_30

H13

VSS_31

J4

VSS_32

J5

VSS_33

J7

VSS_34

J20

VSS_35

K10

VSS_36

K14

VSS_37

L4

VSS_38

L6

VSS_39

L8

VSS_40

L11

VSS_41

L13

VSS_42

L20

VSS_43

L22

VSS_44

M7

VSS_45

N4

VSS_46

N6

VSS_47

N8

VSS_48

N11

VSS_49

ONTARIO-2M161000-1.6G_BGA413

N13

VSS_50

N20

VSS_51

N22

VSS_52

P10

VSS_53

P14

VSS_54

R4

VSS_55

R7

VSS_56

R20

VSS_57

T6

VSS_58

T9

VSS_59

T11

VSS_60

T13

VSS_61

U4

VSS_62

U5

VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97

VSSBG_DAC

U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11

GND

1

+

C620

@

+APU_CORE

1

+

C605

2

330U_D2E_2.5VM_R9M

+APU_CORE_NB

A A

1

+

C618

2

330U_D2_2.5VY_R9M

(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00)

+

C621

2

10U_0603_6.3V6M

220U_B2_2.5VM_R35

1

C599

2

0.1U_0402_16V7K

C600

1

2

0.1U_0402_16V7K

C601

1

2

0.1U_0402_16V7K

C602

1

2

180P_0402_50V8J

1

C603

2

180P_0402_50V8J

POWER

1

+

C606

2

1

C619

2

5

1

+

C607

2

330U_D2E_2.5VM_R9M

Near CPU Socket

10U_0603_6.3V6M

1

C616

@

2

10U_0603_6.3V6M 330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

10U_0603_6.3V6M

Near CPU Socket Near CPU Socket

(S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU)*1=(SF000002000) 20100813

+1.5V +1.8VS

POWER POWER

unpop for PVT 20101004

1

+

C622

2

1

C623

@

2

330U_2.5V_M

22U_0805_6.3V6M

C624

Near CPU Socket

4

By case (Along split)

+1.5V

1

+

C625

@

2

330U_6.3V_M

10U_0603_6.3V6M

Security Classification

Issu ed Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30 2012/06/30

Compal Secret Data

Deciphered D ate

2

1

C608

2

0.1U_0402_16V7K

C609

2

0.1U_0402_16V7K

1

C611

C610

2

0.1U_0402_16V7K

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

C

Date: Sheet

P07-FT1 PWR/VSS

1

C612

2

180P_0402_50V8J

LA6755P/7P

1

C613

2

180P_0402_50V8J

1

C614

2

180P_0402_50V8J

of

748Tuesday, November 30, 2010

C615

1.0

5

+1.5V

JDIMM1

ME@JDIMM1

+VREF_DQ

1

C626

2

D D

DDR_A_DQS#1(6,9) DDR_A_DQS1(6,9)

DDR_A_DQS#2(6,9) DDR_A_DQS2(6,9)

C C

DDR_CS1_DIMMA#(6)

B B

A A

+3VS

DDR_A_DQS#4(6,9) DDR_A_DQS4(6,9)

DDR_A_DQS#6(6,9) DDR_A_DQS6(6,9)

C646

1

C627

2

0.1U_0402_16V4Z

DDR_CKE0(6,9)

DDR_A_BS2(6,9)

DDR_A_CLK0(6) DDR_A_CLK#0(6)

DDR_A_BS0(6,9)

DDR_A_WE#(6,9)

DDR_A_CAS#(6,9)

1

C647

2

2.2U_0603_6.3V4Z

5

1000P_0402_50V7K

0.1U_0402_16V4Z

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R445 10K_0402_5%R445 10K_0402_5%

1 2

12

R446

10K_0402_5%

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205 207

ME@

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

GND1 BOSS1

LCN_DAN06-K4406-0103

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT

GND2

BOSS2

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8 10 12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60 62 64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

NC

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

4

DDR_A_DQS#0 (6,9) DDR_A_DQS0 (6,9)

DDR_RST# (6,9)

DDR_A_DQS#3 (6,9) DDR_A_DQS3 (6,9)

DDR_CKE1 (6,9)

DDR_A_CLK1 (6) DDR_A_CLK#1 (6)

DDR_A_BS1 (6,9) DDR_A_RAS# (6,9)

DDR_CS0_DIMMA# (6) DDR_A_ODT0 (6)

DDR_A_ODT1 (6)

C645

DDR_A_DQS#5 (6,9) DDR_A_DQS5 (6,9)

DDR_A_DQS#7 (6,9) DDR_A_DQS7 (6,9)

DDR_EVENT# (6,9)

FCH_SMDAT0 (9,14,30)

+0.75VS

DDR3 SO-DIMM A Reverse Type

FCH_SMCLK0 (9,14,30)

1

2

1

C644

2

1000P_0402_50V7K

0.1U_0402_16V4Z

3

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.5V

2

C628

1

0.1U_0402_16V4Z

+VREF_CA

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, I NC.

3

2010/06/30 2012/06/30

0.1U_0402_16V4Z

2

C629

1

DDR_A_D[0..63] (6,9)

DDR_A_MA[0..15] (6,9)

DDR_A_DM[0..7] (6,9)

0.1U_0402_16V4Z

2

C630

1

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

2

C631

1

2

C632

1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

+VREF_DQ

0.1U_0402_16V4Z

2

C634

@

1

0.1U_0402_16V4Z

2

C635

@

1

0.1U_0402_16V4Z

2

C633

1

CRB 0.1u X1 4.7u X1

+0.75VS

2

C641

C640

@

Place near JDIMM1

1

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

1

+1.5V

R440

R440 1K_0402_1%

1K_0402_1%

1 2

R442

R442 1K_0402_1%

1K_0402_1%

1 2

+VREF_CA

Combine to one?

0.1U_0402_16V4Z

2

C636

@

1

2

C637

@

1

2

C638

@

1

0.1U_0402_16V4Z

CRB 100U X2

+1.5V

1

C642

2

4.7U_0603_6.3V6K

C643

SF000002Y00

Compal Electronics, Inc.

DDR3 SODIMM-I Socket

LA6755P/7P

1

+1.5V

R441

R441 1K_0402_1%

1K_0402_1%

1 2

R443

R443 1K_0402_1%

1K_0402_1%

1 2

0.1U_0402_16V4Z

2

C639

@

1

+

2

220U_6.3V_M

20100729

848Tuesday, November 30, 2010

1.0

of

5

4

3

2

1

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A11

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8 10 12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60 62 64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6 A4

A2 A0

G2

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

4

DDR_A_DQS#0 (6,8) DDR_A_DQS0 (6,8)

DDR_RST# (6,8)

DDR_A_DQS#3 (6,8) DDR_A_DQS3 (6,8)

DDR_CKE1 (6,8)

DDR_B_CLK3 (6) DDR_B_CLK#3 (6)

DDR_A_BS1 (6,8) DDR_A_RAS# (6,8)

DDR_CS0_DIMMB# (6)

DDR_B_ODT1 (6)

DDR_A_DQS#5 (6,8) DDR_A_DQS5 (6,8)

DDR_A_DQS#7 (6,8) DDR_A_DQS7 (6,8)

DDR_EVENT# (6,8)

FCH_SMDAT0 (8,14,30)

+0.75VS

DDR3 SO-DIMM B Reverse Type

FCH_SMCLK0 (8,14,30)

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.5V

0.1U_0402_16V4Z

2

C650

C651

1

0.1U_0402_16V4Z

+VREF_CA

1

2

0.1U_0402_16V4Z

1

C666

C665

C666

2

1000P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

3

C651

1

0.1U_0402_16V4Z

2010/06/30 2012/06/30

DDR_A_D[0..63] (6,8)

DDR_A_MA[0..15] (6,8)

DDR_A_DM[0..7] (6,8)

0.1U_0402_16V4Z

2

1

Compal Secret Data

C652

Deciphered Date

C653

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

C654

2

C655

1

2

C656

@

1

0.1U_0402_16V4Z

2

C657

@

1

0.1U_0402_16V4Z

2

C658

@

1

0.1U_0402_16V4Z

2

C659

@

1

0.1U_0402_16V4Z

2

C660

@

1

CRB 0.1u X1 4,7uX1

+0.75VS

1

2

C664

C663

C662

1

@

0.1U_0402_16V4Z

Place near JDIMM2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

DDR3 SODIMM-II Socket

LA6755P/7P

2

1

0.1U_0402_16V4Z

1

C661

0.1U_0402_16V4Z

@

4.7U_0603_6.3V6K

of

948Tuesday, November 30, 2010

1.0

+1.5V

JDIMM2

ME@

+VREF_DQ

1

C649

C648

D D

C C

B B

For DRAM strap pin reservation 20100817

+3VS

A A

2

0.1U_0402_16V4Z

DDR_A_DQS#1(6,8) DDR_A_DQS1(6,8)

DDR_A_DQS#2(6,8) DDR_A_DQS2(6,8)

DDR_CKE0(6,8)

DDR_A_BS2(6,8)

DDR_B_CLK2(6) DDR_B_CLK#2(6)

DDR_A_BS0(6,8)

DDR_A_WE#(6,8)

DDR_A_CAS#(6,8) DDR_B_ODT0 (6)

DDR_CS1_DIMMB#(6)

DDR_A_DQS#4(6,8) DDR_A_DQS4(6,8)

DDR_A_DQS#6(6,8) DDR_A_DQS6(6,8)

R961 10K_0402_5%R961 10K_0402_5%

1 2

R448 10K_0402_5%@R448 10K_0402_5%@

1 2

1

C667

2.2U_0603_6.3V4Z

2

CRB only one 4.7k

5

1

2

1000P_0402_50V7K

1

C668

2

0.1U_0402_16V4Z

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

@

1 2

R449

10K_0402_5%

R962

10K_0402_5%

1 2

For DRAM strap pin reservation 20100817

11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

ME@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST

VREF_CA VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

LCN_DAN06-K4806-0103

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

VTT2

5

4

3

2

1

LCD POWER CIRCUIT

+LCDVDD

D D

C675

EDID_CLK EDID_DATA

LVDS_A0 LVDS_A0#

LVDS_A1 LVDS_A1#

LVDS_A2 LVDS_A2#

LVDS_ACLK LVDS_ACLK#

@

1 2

R491 0_0402_5%

1 2

R490 0_0402_5%R490 0_0402_5%

pop R490 instead of R491 20100727

+LCDVDD_CONN

1

@

2

EDID_CLK EDID_DATA

(60 MIL)

AMD check list update 20101110

12

R486

2K_0402_5%

CE_EN(31)

+5VS

12

INVTPWM

+LEDVDD B+

1

C673

680P_0402_50V7K

R487

R487 2K_0402_5%

2K_0402_5%

CE_EN INVTPWM DISPOFF#

JLVDS1

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

GND31GND

ACES_87142-3041-BS

ME@

680P_0402_50V7K

@

+3VS_CMOS

USB20_N1 USB20_P1

LVDS_A0# LVDS_A0

LVDS_A1# LVDS_A1

LVDS_A2# LVDS_A2

LVDS_ACLK# LVDS_ACLK

2

C674

4.7U_0805_25V6-K

2

USB20_N1 (14) USB20_P1 (14)

R479 0_0805_5%R479 0_0805_5%

1 2

CMOS

APU_ENVDD(5)

2N7002H_SOT23-3

Change footprint 20100812

13

D

Q81

S

R473

100K_0402_5%

APU_ENBKL(5)

EDID_CLK(5) EDID_DATA(5)

LVDS_A0(5) LVDS_A0#(5)

LVDS_A1(5) LVDS_A1#(5)

LVDS_A2(5) LVDS_A2#(5)

LVDS_ACLK(5) LVDS_ACLK#(5)

APU_BLPWM(5 )

INVT_PW M(31)

C C

+3VS

680P_0402_50V7K

B B

R458

R458 150_0603_1%

150_0603_1%

2

G

2

12

@R 473

@

BKOFF#(31)

+5VALW

12

R459

R459 100K_0402_5%

100K_0402_5%

R462 220K_0402_5%R462 220K_0402_5%

1 2

1

OUT

IN

GND

Q83

DTC124EKAT146_SC59-3

3

R477 0_0402_5%R477 0_0402_5%

1 2

12

R485

R485 10K_0402_5%

10K_0402_5%

+3VS

Change footprint 20100812

2

1

C670

0.1U_0402_16V4Z

2

FBMA-L11-201209-221LMA30T_0805

R480

100K_0402_1%

1 2

R484 0_0402_5%R484 0_0402_5%

21

RB751V_SOD323

RB751V_SOD323 D4

@D4

@

W=60mils

1

C669

31

4.7U_0603_6.3V6K

2

Q82

Q82 AP2301GN-HF_SOT23-3

AP2301GN-HF_SOT23-3

+LCDVDD

L33

1 2

4.7U_0603_6.3V6K

Change footprint 20100812

ENBKL (31)

+3VS

12

@

R483

R483 10K_0402_5%

10K_0402_5%

DISPOFF#

Change footprint 20100812

W=60mils

+LCDVDD_CONN

1

C671

2

1

C672

0.1U_0402_16V4Z

2

CMOS Camera

Q84 AP2301GN-HF_SOT23-3

R927 0_0402_5%@R927 0_0402_5%@

+5VS

DISPOFF#

@

1

C677

2

470P_0402_50V7K

@

1

C679

2

470P_0402_50V7K

+3VS

+5VALW

20100728

For EMI

A A

1 2

R928 0_0402_5%CMOS@R 928 0_0402_5%CMOS@

1 2

R488 100K_0402_5%CMOS@R488 100K_0402_5%CMOS@

20100728

CMOS_OFF#(31)

R938

0_0402_5%

@

1 2

+5VS_CMOSAPU_BLPWM +CMOS_PW

1

OUT

2

IN

GND

3

Q84 AP2301GN-HF_SOT23-3

3 1

2

R880

CMOS@

CMOS1

1 2

150K_0402_5%

Q85

Q85 DTC124EKAT146_SC59-3

DTC124EKAT146_SC59-3

CMOS@

Change footprint 20100812

C680

1 2

0.1U_0402_16V4Z

CMOS@

12

R489

R489 0_0603_5%

0_0603_5%

CMOS@

1

C681

C681 10U_0805_10V4Z

10U_0805_10V4Z

2

CMOS@

1

C676

0.1U_0402_16V4Z

2

CMOS@

+3VS_CMOS

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

3

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

LVDS/CAMERA

LA6755P/7P

1

1.0

of

10 48Tuesday, November 30, 2010

5

4

3

2

1

R513 0_0402_5%HDMI@R513 0_0402_5%HDMI@

HDMI_CLKP(5) HDMI_CLKN(5)

HDMI_TX0P(5)

HDMI_TX0N(5) HDMI_TX1P(5) HDMI_TX1N(5) HDMI_TX2P(5) HDMI_TX2N(5)

D D

L34

@L34

HDMI_CLKP

HDMI_CLKN

HDMI_TX0P

HDMI_TX0N

HDMI_TX1P

C C

B B

A A

HDMI_TX1N

HDMI_TX2P

HDMI_TX2N

@

1

4

WCM-2012-900T_4P

L35

@L35

@

1

4

WCM-2012-900T_4P

L36

@L36

@

1

4

WCM-2012-900T_4P

L37

@L37

@

1

4

WCM-2012-900T_4P

1 2

R514 0_0402_5%HDMI@R514 0_0402_5%HDMI@

1 2

R515 0_0402_5%HDMI@R515 0_0402_5%HDMI@

1 2

R516 0_0402_5%HDMI@R516 0_0402_5%HDMI@

1 2

R517 0_0402_5%HDMI@R517 0_0402_5%HDMI@

1 2

R518 0_0402_5%HDMI@R518 0_0402_5%HDMI@

1 2

R519 0_0402_5%HDMI@R519 0_0402_5%HDMI@

1 2

R520 0_0402_5%HDMI@R520 0_0402_5%HDMI@

1 2

HDMI_CLK+_CONN

2

HDMI_CLK-_CONN

3

HDMI_TX0+_CONN

2

HDMI_TX0-_CONN

3

HDMI_TX1+_CONN

2

HDMI_TX1-_CONN

3

HDMI_TX2+_CONN

2

HDMI_TX2-_CONN

3

HDMI_DET(5)

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

R500 499_0402_1%HDMI@R500 499_0402_1%HDMI@

R501 499_0402_1%HDMI@R501 499_0402_1%HDMI@

R502 499_0402_1%HDMI@R502 499_0402_1%HDMI@

R503 499_0402_1%HDMI@R503 499_0402_1%HDMI@

R505 499_0402_1%HDMI@R505 499_0402_1%HDMI@

R506 499_0402_1%HDMI@R506 499_0402_1%HDMI@

R508 499_0402_1%HDMI@R508 499_0402_1%HDMI@

R509 499_0402_1%HDMI@R509 499_0402_1%HDMI@

+5VS

NEAR CONNECT

R524

1 2

0_0402_5%

HDMI@

MMBT3904_NL_SOT23-3

+3VS

C

Q88

@

Q88

@

3 1

12

1 2

2

B

E

R530

R530 100K_0402_5%

100K_0402_5%

HDMI@

12

@

R512

R512 100K_0402_5%

100K_0402_5%

R525

1 2

150K_0402_5%

@

13

D

2

G

S

R527

200K_0402_5%

Q87

Q87 2N7002H_SOT23-3

2N7002H_SOT23-3

HDMI@

HDMI_HPD

12

@

1 2

@

R528

R528 100K_0402_5%

100K_0402_5%

+5VS

3

2

HDMI_HPD

1

@

D8

D8 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

HDMI_CLK(5)

HDMI_DATA(5)

Add fuse for safety requirement 20100923

+5VS +5VS

3

2

1.1A_6V_SMD1812P110TF

HDMI@

R522

2K_0402_5%

AMD check list update 20101110

1

@

D5

D5 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

+3VS

2

61

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6 Q86A

Q86A

HDMI@

2N7002KDWH_SOT363-6

@

1 2

R815

1 2

R816

+5VS_HDMI_F

21

HDMI@

F2

+5VS_HDMI

HDMI@

R523

R523 2K_0402_5%

2K_0402_5%

1 2

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

5

Q86B

HDMI@

0_0402_5%

0_0402_5%@

HDMI_HPD

HDMIDAT_R HDMICLK_R

3

2

Change footprint 20100812

34

R521

@R521

@

0_0805_5%

D7

RB491D_SC59-3

HDMI@

C690

1

0.1U_0402_16V4Z

HDMI@

2

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

HDMICLK_RHDMIDAT_R

1

@

D6

D6 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

21

+5VS

JHDMI1

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

SUYIN_100042GR019M23DZL

ME@

20

G1

21

G2

22

G3

23

G4

HDMICLK_R

HDMIDAT_R

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

3

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

HDMI Connector

LA6755P/7P

11 48Tuesday, November 30, 2010

1

1.0

of

A

1 1

DAC_RED(5)

DAC_GRN(5)

DAC_BLU(5)

DAC_RED

DAC_GRN

DAC_BLU

12

R531

R531 150_0402_1%

150_0402_1%

12

R532

R532 150_0402_1%

150_0402_1%

12

R533

R533 150_0402_1%

150_0402_1%

CLOSE TO CONN

+CRT_VCC

R537

1 2

1

C699

0.1U_0402_16V4Z

2 2

CRT_HSYNC(5)

CRT_VSYNC(5)

3 3

CRT_DDC_DATA(5)

CRT_DDC_CLK(5 )

4 4

0.1U_0402_16V4Z

R546

2K_0402_5%

A

12

C701

+3VS

12

R547

R547 2K_0402_5%

2K_0402_5%

Change footprint 20100812

2

1

2

2N7002KDWH_SOT363-6

1K_0402_5%

1

5

P

4

OE#

A2Y

G

U23

U23 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

+CRT_VCC

R543

1 2

1K_0402_5%

1

5

P

4

OE#

A2Y

G

U24

U24 SN74AHCT1G125DCKR_SC70-5

SN74AHCT1G125DCKR_SC70-5

3

+3VS

1 2

R964 0_0402_5%

1 2

R965 0_0402_5%

5

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6 Q89B

Q89B

2

61

Q89A

@

B

1

C692

2

10P_0402_50V8J

CRT_HSYNC_1

CRT_VSYNC_1

+CRT_VCC

R548

2K_0402_5%

34

100P_0402_50V8J

B

FCM1608CF-121T03 0603

1

C693

C694

C694 10P_0402_50V8J

10P_0402_50V8J

2

10P_0402_50V8J

1 2

L41

FCM1608CF-121T03 0603

1 2

L42

FCM1608CF-121T03 0603

12

R549

R549 2K_0402_5%

2K_0402_5%

CRT_DDC_DAT_CONN

CRT_DDC_CLK_CONN

1

@

2

@

C704

C704 68P_0402_50V8K

68P_0402_50V8K

2

@

C703

AMD check list update 20101110

C

1 2

L38

1 2

L39

1 2

L40

10P_0402_50V8J

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C697

2

Issued Date

1

C695

2

10P_0402_50V8J

1

@

C700

C700 10P_0402_50V8J

10P_0402_50V8J

2

1

C702

@C702

@

10P_0402_50V8J

2

RED

GREEN

BLUE

1

C696

C696 10P_0402_50V8J

10P_0402_50V8J

2

JVGA_HS

JVGA_VS

Compal Secret Data

2010/06/30 2012/06/30

C

Compal Secret Data

Deciphered Date

D

+5VS +5VS +5VS

3

2

1

@

D9

D9 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

3

1

2

@

D10

D10 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

+5VS +5VS

3

1

2

@

D12

D12 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

D14

2 1

RB491D_SC59-3

+CRT_VCC

CRT Connector

F1

1.1A_6V_SMD1812P110TF

+5VS

W=40mils

RED

CRT_DDC_DAT_CONN GREEN

JVGA_HS BLUE

JVGA_VS

CRT_DDC_CLK_CONN

1

C698

100P_0402_50V8J

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

&57&RQQHFWRU

Custom

LA6755P/7P

3

2

3

2

21

E

REDGREENBLUE

1

BAT54S-7-F_SOT23-3

@

D11

JVGA_VSJVGA_HS

1

@

D13

D13 BAT54S-7-F_SOT23-3

BAT54S-7-F_SOT23-3

1

C691

0.1U_0402_16V4Z

2

JCRT1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

CONTE_80431-5K1-152

ME@

E

16

G

17

G

1.0

of

12 48Tuesday, November 30, 2010

A

+3VALW

@

C705

12

5

U25

@ U25

0.1U_0402_16V4Z

SB_ARST#_GATE

PLT_RST#

12

R555

R555 100K_0402_5%

100K_0402_5%

1 1

update for PX function 20100811

2 2

3 3

4 4

@

2

P

B

4

Y

1

A

G

3

NC7SZ08P5X_NL_SC70-5

PX@

1 2

R559 0_0603_5%

PLT_RST# (26,30,31)

LAN WLAN

LAN

WLAN

PX_RST# (18)

PCIE_FTX_C_DRX_P0(26) PCIE_FTX_C_DRX_N0(26) PCIE_FTX_C_DRX_P1(30) PCIE_FTX_C_DRX_N1(30)

+PCIE_VDDAN

PCIE_FRX_DTX_P0(26) PCIE_FRX_DTX_N0(26) PCIE_FRX_DTX_P1(30) PCIE_FRX_DTX_N1(30)

CLK_PCIE_VGA(18) CLK_PCIE_VGA#(18)

CLK_PCIE_LAN(26) CLK_PCIE_LAN#(26)

CLK_PCIE_WLAN(30) CLK_PCIE_WLAN#(30)

UMI_RX0P(6) UMI_RX0N(6) UMI_RX1P(6) UMI_RX1N(6) UMI_RX2P(6) UMI_RX2N(6) UMI_RX3P(6) UMI_RX3N(6)

UMI_TX0P(6)

UMI_TX0N(6)

UMI_TX1P(6)

UMI_TX1N(6)

UMI_TX2P(6)

UMI_TX2N(6)

UMI_TX3P(6)

UMI_TX3N(6)

DISP_CLK(5) DISP_CLK#(5)

APU_CLK(5) APU_CLK#(5)

B

update for PX function 20100811

R557 33_0402_5%R557 33_0402_5%

C707 0.1U_0402_16V7KC707 0.1U_0402_16V7K

1 2

C708 0.1U_0402_16V7KC708 0.1U_0402_16V7K

1 2

C709 0.1U_0402_16V7KC709 0.1U_0402_16V7K

1 2

C710 0.1U_0402_16V7KC710 0.1U_0402_16V7K

1 2

C711 0.1U_0402_16V7KC711 0.1U_0402_16V7K

1 2

C712 0.1U_0402_16V7KC712 0.1U_0402_16V7K

1 2

C713 0.1U_0402_16V7KC713 0.1U_0402_16V7K

1 2

C714 0.1U_0402_16V7KC714 0.1U_0402_16V7K

1 2

R560 590_0402_1%R560 590_0402_1% R561 2K_0402_1%R561 2K_0402_1%

C715 0.1U_0402_16V7KC715 0.1U_0402_16V7K

1 2

C716 0.1U_0402_16V7KC716 0.1U_0402_16V7K

1 2

C717 0.1U_0402_16V7KC717 0.1U_0402_16V7K

1 2

C718 0.1U_0402_16V7KC718 0.1U_0402_16V7K

1 2

150P_0402_50V8J

C706

12 12

close to FCH within 1"

R564 0_0402_5%R564 0_0402_5%

1 2

R565 0_0402_5%R565 0_0402_5%

1 2

R566 0_0402_5%R566 0_0402_5%

1 2

R567 0_0402_5%R567 0_0402_5%

1 2

R569 0_0402_5%R569 0_0402_5%

1 2

R570 0_0402_5%R570 0_0402_5%

1 2

R571 0_0402_5%R571 0_0402_5%

1 2

R572 0_0402_5%R572 0_0402_5%

1 2

R573 0_0402_5%R573 0_0402_5%

1 2

R574 0_0402_5%R574 0_0402_5%

1 2

C721

22P_0402_50V8J

C722

22P_0402_50V8J

1 2

12

Y5

25MHZ_20PF_7A25000012

1 2

12

UMI_RX0P_C UMI_RX0N_C UMI_RX1P_C UMI_RX1N_C UMI_RX2P_C UMI_RX2N_C UMI_RX3P_C UMI_RX3N_C

PCIE_FTX_DRX_P0 PCIE_FTX_DRX_N0 PCIE_FTX_DRX_P1 PCIE_FTX_DRX_N1

DISP_CLK_R DISP_CLK#_R

APU_CLK_R APU_CLK#_R

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

1M_0603_5%

1M_0603_5% R576

R576

A_RST#PLT_RST#

25M_CLK_X1

25M_CLK_X2

T78

T78 PAD

PAD

U26E

P1

PCIE_RST_L

L1

A_RST_L

AD26

UMI_TX0P

AD27

UMI_TX0N

AC28

UMI_TX1P

AC29

UMI_TX1N

AB29

UMI_TX2P

AB28

UMI_TX2N

AB26

UMI_TX3P

AB27

UMI_TX3N

AE24

UMI_RX0P

AE23

UMI_RX0N

AD25

UMI_RX1P

AD24

UMI_RX1N

AC24

UMI_RX2P

AC25

UMI_RX2N

AB25

UMI_RX3P

AB24

UMI_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

21807-A11-HUDSON-M1_FCBGA605

C

PCI EXPRESS I/F

CLOCK GENERATOR

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI I/F

REQ2_L/CLK_REQ8_L/GPIO41 REQ3_L/CLK_REQ5_L/GPIO42

GNT3_L/CLK_REQ7_L/GPIO46

LPC

LDRQ1_L/CLK_REQ6_L/GPIO49

CPU

ALLOW_LDTSTP/DMA_ACTIVE_L

RTC

INTRUDER_ALERT_L

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST_L

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

CBE0_L CBE1_L CBE2_L CBE3_L

FRAME_L

DEVSEL_L

IRDY_L

TRDY_L

PAR STOP_L PERR_L SERR_L REQ0_L

REQ1_L/GPIO40

GNT0_L

GNT1_L/GPO44 GNT2_L/GPO45

CLKRUN_L

LOCK_L

INTE_L/GPIO32

INTF_L/GPIO33 INTG_L/GPIO34 INTH_L/GPIO35

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME_L

LDRQ0_L

SERIRQ/GPIO48

PROCHOT_L

LDT_PG LDT_STP_L LDT_RST_L

32K_X1

32K_X2

RTCCLK

VDDBT_RTC_G

D

Watchdog timer on NB_PWRGD enable for pull-up disable for pull-down 20100527

W2 W1 W3 W4 Y1

V2

AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6 AB12 AB11 AD7

AJ6 AG6 AG4 AJ4

H24 H25 J27 J26 H29 H28 G28 J25 AA18 AB19

G21 H21 K19 G22 J24

C1

C2

D2 B2 B1

T96PADT96PAD

PCI_CLK2

T92PADT92PAD

SB_ARST#_GATE

For PX function reserved

CLK_PCI_DB_R (17)

R853 0_0402_5%R853 0_0402_5%

1 2

R575 22_0402_5%R575 22_0402_5%

1 2

R854 0_0402_5%@R854 0_0402_5%@

1 2

@

RTC_32KHI

RTC_32KHO

@

R920 0_0402_5%

1 2

@

R921 0_0402_5%

1 2

SUSCLK (31)

1

2

1U_0402_6.3V4Z

PCI_CLK1 (17)

PCI_CLK3 (17) PCI_CLK4 (17)

PE_GPIO0 (18)

PCI_AD23 (17) PCI_AD24 (17) PCI_AD25 (17) PCI_AD26 (17) PCI_AD27 (17)

PE_GPIO1 (20,21,43)

LPC_AD0 (30,31) LPC_AD1 (30,31) LPC_AD2 (30,31) LPC_AD3 (30,31) LPC_FRAME# (30,31)

W=20mils

C723

+3VS

12

@

R554

12

R558

APU_PWRGD

SERIRQ (31)

ALLOW_STOP# (5) FCH_PROCHOT# (5) APU_PWRGD (5)

LDT_RST# (5)

1 2

R577 510_0402_5%R577 510_0402_5%

E

10K_0402_5%

PE_GPIO1

R919 100K_0402_5%@R919 100K_0402_5%@

PE_GPIO0

1 2

R918 100K_0402_5%PX@R918 100K_0402_5%PX@

1 2

20101012

Close to SB

R562 20M_0402_5%@R562 20M_0402_5%@

1 2

Change from 22P to 18P for RTC correction 20101012

C719

1 2

18P_0402_50V8J

20M_0603_5%

18P_0402_50V8J

LPCCLK0 (17)

LPC_CLK0_EC (31) CLK_PCI_DB (30)

R563

C720

1 2

S

FDV301N_NL_SOT23-3

FCH_RTCX1_OUT (31)

FCH_RTCX2_OUT (31)

+RTCBATT

12

CLRP1 SHORT PADS

SHORT PADS

12

+1.8VS +3V S

G

2

Q90

4

1

32.768KHZ_12.5PF_9H03200413

R568

10K_0402_5%

13

D

Reserve for EMI for PVT build 20101005

@CLRP1

@

for Clear CMOS

RTC_32KHO

Y4

OSC

NC

OSC

NC

RTC_32KHI

12

1

@

C1011

C1011 100P_0402_50V8J

100P_0402_50V8J

2

3

2

H_PWRGD_L (44)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF CO MPAL ELECTRONICS, INC.

2010/06/30 2012/06/30

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

)&+3&,(3&,$&3,/3&57&

/$33

E

of

13 48Tuesday, November 30, 2010

1.0

+3VALW

1 2

R870 10K_0402_5%R870 10K_0402_5%

1 2

R871 10K_0402_5%R871 10K_0402_5%

1 2

R872 10K_0402_5%R872 10K_0402_5%

1 2

R603 10K_0402_5%R603 10K_0402_5%

1 2

R604 10K_0402_5%R604 10K_0402_5%

1 2

1 1

2 2

3 3

4 4

R605 10K_0402_5%R605 10K_0402_5%

+3VS

1 2

R817 10K_0402_5%R817 10K_0402_5%

1 2

R818 10K_0402_5%R818 10K_0402_5%

1 2

R597 4.7K_0402_5%R597 4.7K_0402_5%

1 2

R598 2.2K_0402_5%R598 2.2K_0402_5%

1 2

R599 2.2K_0402_5%R599 2.2K_0402_5%

FCH_PWRGD(44)

C1008

100P_0402_50V8J

Reserve for EMI for PVT build 20101005

@

1 2

R823 10K_0402_5%

1 2

R587 10K_0402_5%R587 10K_0402_5%

1 2

R588 10K_0402_5%R588 10K_0402_5%

1 2

R606 2.2K_0402_5%R606 2.2K_0402_5%

@

1 2

R607 10K_0402_5%

@

1 2

R608 10K_0402_5%

1 2

R609 10K_0402_5%R609 10K_0402_5%

Pull-down for enable high performance mode 20100527 (required for M1)

12

PX@

R911

R912

nonHDMI@

BOARD Config.

12

HDMI@

10K_0402_5%

12

UMA@

R915

10K_0402_5%

R914

10K_0402_5%

A

USB_OC2#

USB_OC1#

USB_OC0#

FCH_SIC

FCH_SID

FCH_PCIE_WAKE#

LAN_CLKREQ#

WLAN_CLKREQ#

NB_PWRGD

FCH_SMCLK0

FCH_SMDAT0

R580 0_0402_5%@R580 0_0402_5%@

R581 0_0402_5%R581 0_0402_5%

4

2

1

@

C725

0.1U_0402_16V7K

1

2

PEG_CLKREQ#_R

+3VALW+3VALW+3VALW

12

R910

BACO@

10K_0402_5%

GPIO189 GPIO190 GPIO191

12

UMA@

R913

10K_0402_5%

+3VS

@

C724 0.1U_0402_16V7K

1 2

5

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

U27

FCH_SMCLK1

FCH_SMDAT1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

HDA_SDOUT

R913

0_0402_5%

SD028000080

PX3@

12

@

GPIO189 GPIO190 GPIO191

00

01

10

0

110

HDA_SYNC_AUDIO(28)

HDA_RST_AUDIO#(28)

+3VALW

USB_OC7#

EC_LID_OUT#

USB_OC5#

ODD_DA#_FCH

ODD_DETECT#

R579 10K_0402_5%@R579 10K_0402_5%@

ICH_POK (31)

VGATE (31,44)

+3VALW

1 2

R929 10K_0402_5%R929 10K_0402_5%

@

1 2

R930 10K_0402_5%

1 2

R931 10K_0402_5%R931 10K_0402_5%

1 2

R932 10K_0402_5%R932 10K_0402_5%

1 2

R933 10K_0402_5%R933 10K_0402_5%

1

@

C1009

C1009 100P_0402_50V8J

100P_0402_50V8J

2

Reserve for EMI for PVT build 20101005

HDA_BITCLK_AUDIO(28) HDA_SDOUT_AUDIO(28)

HDA_SDIN0(28)

Function

UMA

DIS

PX3

PX4

w/o HDMIxx1

A

B

1 2

PEG_CLKREQ#(19)

R593 10K_0402_5%R593 10K_0402_5%

FCH_PCIE_WAKE#(26,30)

H_THERMTRIP#(5)

EC_RSMRST#(31)

LAN_CLKREQ#(26)

WLAN_CLKREQ#(30)

ODD_DA#_FCH(46) ODD_DETECT#(46)

R583 33_0402_5%R583 33_0402_5%

1 2

R585 33_0402_5%R585 33_0402_5%

1 2

R589 33_0402_5%R589 33_0402_5%

1 2

R590 33_0402_5%R590 33_0402_5%

1 2

B

C

U26A

GPIO187 GPIO188

J2

PCI_PME_L/GEVENT4_L

K1

RI_L/GEVENT22_L

D3

SPI_CS3_L/GBE_STAT1/GEVENT21_L

F1

SLP_S3_L

H1

SLP_S5_L

F2

PWR_BTN_L

H5

PWR_GOOD

G6

SUS_STAT_L

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0_L

AE21

KBRST_L/GEVENT1_L

K2

LPC_PME_L/GEVENT3_L

J29

LPC_SMI_L/GEVENT23_L

H2

GEVENT5_L

J1

SYS_RESET_L/GEVENT19_L

H6

WAKE_L/GEVENT8_L

F3

IR_RX1/GEVENT20_L

J6

THRMTRIP_L/SMBALERT_L/GEVENT2_L

AC19

NB_PWRGD

G1

RSMRST_L

AD19

CLK_REQ4_L/SATA_IS0_L/GPIO64

AA16

CLK_REQ3_L/SATA_IS1_L/GPIO63

AB21

SMARTVOLT1/SATA_IS2_L/GPIO50

AC18

CLK_REQ0_L/SATA_IS3_L/GPIO60

AF20

SATA_IS4_L/FANOUT3/GPIO55

AE19

SATA_IS5_L/FANIN3/GPIO59

AF19

SPKR_GPIO66

AD22

SCL0_GPIO43

AE22

SDA0_GPIO47

F5

SCL1_GPIO227

F4

SDA1_GPIO228

AH21

CLK_REQ2_L/FANIN4_GPIO62

AB18

CLK_REQ1_L/FANOUT4_GPIO61

E1

IR_LED_L/LLB_L/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN_L/GPIO51

H4

DDR3_RST_L/GEVENT7_L

D5

GBE_LED0/GPIO183

D7

GBE_LED1/GEVENT9_L

G5

GBE_LED2/GEVENT10_L

K3

GBE_STAT0/GEVENT11_L

AA20

CLK_REQG_L/GPIO65_OSCIN

H3

BLINK/USB_OC7_L/GEVENT18_L

D1

USB_OC6_L/IR_TX1/GEVENT6_L

E4

USB_OC5_L/IR_TX0/GEVENT17_L

D4

USB_OC4_L/IR_RX0/GEVENT16_L

E8

USB_OC3_L/AC_PRES/TDO/GEVENT15_L

F7

USB_OC2_L/TCK/GEVENT14_L

E7

USB_OC1_L/TDI/GEVENT13_L

F8

USB_OC0_L/TRST_L/GEVENT12_L

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GPIO167

M2

AZ_SDIN1/GPIO168

M1

AZ_SDIN2/GPIO169

M4

AZ_SDIN3/GPIO170

N2

AZ_SYNC

P2

AZ_RST_L

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST_L

V7

GBE_PHY_INTR

E23

PS2_DAT/SDA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2_L/GBE_STAT2/GPIO166

G29

FC_RST_L/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

21807-A11-HUDSON-M1_FCBGA605

HD AUDIO

GBE LAN

PCI_PME#(31)

Kill_SW#(46)

SLP_S3#(31) SLP_S5#(31)

PBTN_OUT#(31)

GATEA20(31) KB_RST#(31) EC_SCI#(31) EC_SMI#(31)

SATA_DET#(33)

FCH_SPKR(28) FCH_SMCLK0(8,9,30) USB20_P7 (30) FCH_SMDAT0(8,9,30)

R582

0_0402_5%@

EC_LID_OUT#(31)

USB_OC2#(34) USB_OC1#(33) USB_OC0#(33)

R591 10K_0402_5%R591 10K_0402_5%

1 2

R592 10K_0402_5%R592 10K_0402_5%

1 2

R596 10K_0402_5%R596 10K_0402_5%

1 2

R600 10K_0402_5%R600 10K_0402_5%

1 2

20100802

12

T85 PADT85 PAD T86 PADT86 PAD

20100810

FCH_PWRGD

T82PADT82PAD T83PADT83PAD T84PADT84PAD

NB_PWRGD

FCH_SMCLK1 FCH_SMDAT1

PEG_CLKREQ#_R

USB_OC7#

USB_OC5#

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

GPIO189 GPIO190 GPIO191

For BRD Config.

ACPI/WAKE UP EVENTS

GPIO

USB OC

USB MISC

USBCLK/14M_25M_48M_OSC

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200

USB 1.1

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB 2.0

SCL3_LV/GPIO195 SDA3_LV/GPIO196

EMBEDDED CTRL

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

SCL2/GPIO193 SDA2/GPIO194

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217

KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226

D

A10

G19

J10 H11

H9 J8

B12 A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

D25 F23 B26 E26 F25 E22 F22 E21

G24 G25 E28 E29 D29 D28 C29 C28

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

USB_RCOMP

1 2

10mils and <1"

GPIO193

R584 10K_0402_5%R584 10K_0402_5%

GPIO194

R586 10K_0402_5%R586 10K_0402_5%

EC_PWM2 EC_PWM3

R578

11.8K_0402_1%

USB20_N7 (30)

USB20_P6 (34) USB20_N6 (34)

USB20_P5 (33) USB20_N5 (33)

USB20_P4 (34) USB20_N4 (34)

USB20_P3 (33) USB20_N3 (33)

USB20_P2 (33) USB20_N2 (33)

USB20_P1 (10) USB20_N1 (10)

USB20_P0 (33) USB20_N0 (33)

12 12

FCH_SIC (5) FCH_SID (5)

Internal Pull-Up available

EC_PWM3 EC_PWM2 ROM TYPE

x

0

xx

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

D

0

Title

Size Document Number Rev

Custom

Date: Sheet

0

x

Compal Electronics, Inc.

FCH HDA/USB/ACPI

LA6755P/7P

E

WLAN

CR

BT

RP

LP2

COMBO

CMOS

LP1

EC_PWM3

EC_PWM2

SPI ROM

Reserved

LPC ROM

E

R594

@

@ 1 2

10K_0402_5%

12

R601

2.2K_0402_5%

Root

+3VALW

R595

@

@ 1 2

10K_0402_5%

12

R602

@

2.2K_0402_5%

14 48Tuesday, November 30, 2010



1.0

of

A

1 1

C726 0.01U_0402_16V7KC726 0.01U_0402_16V7K

SATA_ITX_DRX_P0(29)

HDD

ODD

eSATA

2 2

SATA_ITX_DRX_N0(29)

SATA_DTX_C_IRX_N0(29) SATA_DTX_C_IRX_P0(29)

SATA_ITX_DRX_P1(46) SATA_ITX_DRX_N1(46)

SATA_DTX_C_IRX_N1(46) SATA_DTX_C_IRX_P1(46)

SATA_ITX_DRX_P2(33) SATA_ITX_DRX_N2(33)

SATA_DTX_C_IRX_N2(33) SATA_DTX_C_IRX_P2(33)

1 2

C727 0.01U_0402_16V7KC727 0.01U_0402_16V7K

1 2

C728 0.01U_0402_16V7KC728 0.01U_0402_16V7K

1 2

C729 0.01U_0402_16V7KC729 0.01U_0402_16V7K

1 2

ESATA@

C730 0.01U_0402_16V7K

1 2

C731 0.01U_0402_16V7K

1 2

ESATA@

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1

SATA_ITX_C_DRX_P2 SATA_ITX_C_DRX_N2

10 mils and < 1"

R610 1K_0402_1%R610 1K_0402_1%

1 2

R611 931_0402_1%R611 931_0402_1%

+1.1VS

HDD_LED#(46)

+3VS

3 3

1 2

R616 10K_0402_5%R616 10K_0402_5%

1 2

C980

@

22P_0402_50V8J

C981

@

22P_0402_50V8J

1 2

12

Y7

@

25MHZ_20PF_7A25000012

T87 PADT87 PAD

@

1M_0603_5%

1M_0603_5% R861

R861

SATA_CALRP SATA_CALRN

25M_SATA_X1

25M_SATA_X2

SPI_SO_R SPI_SI_R SPI_CLK_FCH_R SPI_SB_CS0#_R GPIO161

B

U26B

AH9

SATA_TX0P

AJ9

SATA_TX0N

AJ8

SATA_RX0N

AH8

SATA_RX0P

AH10

SATA_TX1P

AJ10

SATA_TX1N

AG10

SATA_RX1N

AF10

SATA_RX1P

AG12

SATA_TX2P

AF12

SATA_TX2N

AJ12

SATA_RX2N

AH12

SATA_RX2P

AH14

SATA_TX3P

AJ14

SATA_TX3N

AG14

SATA_RX3N

AF14

SATA_RX3P

AG17

SATA_TX4P

AF17

SATA_TX4N

AJ17

SATA_RX4N

AH17

SATA_RX4P

AJ18

SATA_TX5P

AH18

SATA_TX5N

AH19

SATA_RX5N

AJ19

SATA_RX5P

AB14

SATA_CALRP

AA14

SATA_CALRN

AD11

SATA_ACT_L/GPIO67

AD16

SATA_X1

AC16

SATA_X2

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO163

K4

SPI_CLK/GPIO162

K9

SPI_CS1_L/GPIO165

G2

ROM_RST_L/GPIO161

21807-A11-HUDSON-M1_FCBGA605

SERIAL ATA

SPI ROM

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FC_OE_L/GPIOD145

FC_AVD_L/GPIOD146

FC_WE_L/GPIOD148 FC_CE1_L/GPIOD149 FC_CE2_L/GPIOD150

FC_INT1/GPIOD144

GPIOD

FC_INT2/GPIOD147

FC_ADQ0/GPIOD128

FC_ADQ1/GPIOD129

FC_ADQ2/GPIOD130

FC_ADQ3/GPIOD131

FC_ADQ4/GPIOD132

FC_ADQ5/GPIOD133

FC_ADQ6/GPIOD134

FC_ADQ7/GPIOD135

FC_ADQ8/GPIOD136

FC_ADQ9/GPIOD137

FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143

HW MONITOR

FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173

TEMPIN3/TALERT_L/GPIO174

TEMP_COMM

VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

NC1 NC2

C

AH28 AG28 AF26

AF28 AG29 AG26 AF27 AE29 AF29 AH27

AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26

W5 W6 Y9

W7 V9 W8

TEMPIN0

B6

TEMPIN1

A6

TEMPIN2

A5 B5 C7

GPIO175

A3

GPIO176

B4

GPIO177

A4

GPIO178

C5

GPIO179

A7

GPIO180

B7

GPIO181

B8

GPIO182

A8

G27 Y2

ODD_EN (29) BT_OFF# (33)

WL_OFF# (30)

R612 10K_0402_5%R612 10K_0402_5% R613 10K_0402_5%R613 10K_0402_5% R614 10K_0402_5%R614 10K_0402_5% R615 10K_0402_5%R615 10K_0402_5%

R617 10K_0402_5%R617 10K_0402_5% R618 10K_0402_5%R618 10K_0402_5% R619 10K_0402_5%R619 10K_0402_5% R620 10K_0402_5%R620 10K_0402_5% R621 10K_0402_5%R621 10K_0402_5% R622 10K_0402_5%R622 10K_0402_5% R623 10K_0402_5%@R623 10K_0402_5%@ R624 10K_0402_5%R624 10K_0402_5%

12 12 12 12

12 12 12 12 12 12 12 12

D

APU_ALERT#_FCH (5)

VIN6/GBE_STAT3/GPIO181 Enable integrated pull-down/up and leave unconnected

E

0%63,520 1RQVKDUH520

+3VS

1 2

SPI_SB_CS0#

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

U28

1

CS#

VCC

2

SO

HOLD#

3

WP#

SCLK

4

GND

MX25L1605AM2C-12G_SO8

SA00003FO00 SA00002KI00

SI

8 7 6 5

+3VS

C733

1 2

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_FCH SPI_SI

1 2 1 2

33_0402_5%

R630

R626

4 4

SPI_SB_CS0#_R SPI_SO_R SPI_SO_L

R628

0_0402_5%

1 2 1 2

33_0402_5%

R629

A

R627

22P_0402_50V8J

R6310_0402_5% R6310_0402_5%

SPI_CLK_FCH_R SPI_SI_R

B

SPI_CLK_FCH

R625

33_0402_5%

@

C732

12

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

FCH-SATA/SPI

LA6755P/7P

15 48Tuesday, November 30, 2010

E

1.0

of

ME limitation, change one 22u_0805 to two 10u_0603 20101006

+3VS

1 1

+1.8VS

R632

1 2

0_0603_5%

Change from SM010014520 to SD002000080 20101012

+1.1VS

L45

FBMA-L11-201209-221LMA30T_0805

2 2

Change from SM010014520 to SD002000080 20101012

+3VALW

FBMA-L11-201209-221LMA30T_0805

change from SM01000CB00 to SD013000080 20101012

+1.1VALW

3 3

L46

L48

FBMA-L11-160808-221LMT_2P

A

1

C1006

C1007

2

10U_0603_6.3V6M

GPIO I/F implemented: tied to +1.8V_S0 GPIO I/F not implemented: tied to

+1.8V_S0 or 0 ohm to ground

12

R633

@

+3VS

12

C762

12

2

1

C735

C736

1

2

10U_0603_6.3V6M

0.1U_0402_16V7K

2

C745

C744

1

0_0402_5%

4.7U_0603_6.3V6K

L44

FBMA-L11-160808-221LMT_2P

C754

1

2

10U_0603_6.3V6M

12

1

C755

2

22U_0805_6.3V6M

1U_0402_6.3V6K

1

C763

C764

2

10U_0603_6.3V6M

2

C737

1

0.1U_0402_16V7K

+VDDIO_18_FC

2

C746

1

0.1U_0402_16V7K

+VDDPL33_PCIE

1

C753

2

+PCIE_VDDAN

2.2U_0603_6.3V6K

2

C756

2

C757

1

0.1U_0402_16V7K

+VDDPL_33_SATA

+AVDD_SATA

1354.2mA

+AVDD_USB

534.5mA

1

C766

C765

2

1U_0402_6.3V6K

0.1U_0402_16V7K

+VDDAN_11_USB

1

2

C770

2

2.2U_0603_6.3V6K

88.6mA

C771

1

0.1U_0402_16V7K

42mA

0.16mA

22.5mA

1115.6mA

15.5mA

B

U26C

AH1

VDDIO_33_PCIGP_1

V6

VDDIO_33_PCIGP_2

Y19

VDDIO_33_PCIGP_3

AE5

VDDIO_33_PCIGP_4

AC21

VDDIO_33_PCIGP_5

AA2

VDDIO_33_PCIGP_6

AB4

VDDIO_33_PCIGP_7

AC8

VDDIO_33_PCIGP_8

AA7

VDDIO_33_PCIGP_9

AA9

VDDIO_33_PCIGP_10

AF7

VDDIO_33_PCIGP_11

AA19

VDDIO_33_PCIGP_12

AF22

VDDIO_18_FC_1

AE25

VDDIO_18_FC_2

AF24

VDDIO_18_FC_3

AC22

VDDIO_18_FC_4

AE28

VDDPL_33_PCIE

U26

VDDAN_11_PCIE_1

V22

VDDAN_11_PCIE_2

V26

VDDAN_11_PCIE_3

V27

VDDAN_11_PCIE_4

V28

VDDAN_11_PCIE_5

V29

VDDAN_11_PCIE_6

W22

VDDAN_11_PCIE_7

W26

VDDAN_11_PCIE_8

AD14

VDDPL_33_SATA

AJ20

VDDAN_11_SATA_1

AF18

VDDAN_11_SATA_4

AH20

VDDAN_11_SATA_2

AG19

VDDAN_11_SATA_3

AE18

VDDAN_11_SATA_5

AD18

VDDAN_11_SATA_6

AE16

VDDAN_11_SATA_7

A18

VDDAN_33_USB_S_1

A19

VDDAN_33_USB_S_2

A20

VDDAN_33_USB_S_3

B18

VDDAN_33_USB_S_4

B19

VDDAN_33_USB_S_5

B20

VDDAN_33_USB_S_6

C18

VDDAN_33_USB_S_7

C20

VDDAN_33_USB_S_8

D18

VDDAN_33_USB_S_9

D19

VDDAN_33_USB_S_10

D20

VDDAN_33_USB_S_11

E19

VDDAN_33_USB_S_12

C11

VDDAN_11_USB_S_1

D11

VDDAN_11_USB_S_2

21807-A11-HUDSON-M1_FCBGA605

POWER

PCI/GPIO I/O

FLASH I/O

PCI EXPRESS

SERIAL ATA

USB I/O

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDRF_GBE_S

VDDIO_33_GBE_S

GBE LAN

VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2

VDDIO_GBE_S_1 VDDIO_GBE_S_2

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

CORE S5CORE S0 CLKGEN I/O 3.3V_S5 I/O

VDDCR_11_S_1 VDDCR_11_S_2

VDDIO_AZ_S

VDDCR_11_USB_S_1 VDDCR_11_USB_S_2

VDDPL_33_SYS

PLL

VDDPL_11_SYS_S

VDDPL_33_USB_S

VDDAN_33_HWM_S

VDDXL_33_S

C

N13 R15 N17 U13 U17 V12 V18 W12 W18

+VDDAN_11_CLK

K28 K29 J28 K26 J21 J20 K21 J22

V1

M10

L7 L9

M6 P8

49.5mA

A21 D21 B21 K10 L10 J9 T6 T8

F26 G26

15.3mA

M8

58mA

A11 B11

46.5mA

M21

65.3mA

L22

16.1mA

F19

11.4mA

D6

+VDDXL_33_S

L20

5mA

979.4mA

165.2mA

+VDDCR_11_USB

1

C738

2

0.1U_0402_16V7K

382.9mA

1

C749

2

0.1U_0402_16V7K

+VDDIO_AZ

+VDDPL33

+VDDPL11

+AVDD_USB

+VDDAN33_HWM

1

C772

2

2.2U_0603_6.3V6K

1

C747

C750

C758

C760

1

C739

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C751

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C759

2

1

2

FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

1

C761

2

1U_0402_6.3V6K

L49

D

C740

C752

12

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C743

2

1U_0402_6.3V6K

22U_0805_6.3V6M

+3VALW

+1.1VALW

1

C767

C768

2

0.1U_0402_16V7K

+3VS

1

C748

C740

+1.1VS

Change from SM010014520 to SD002000080 20101012

FBMA-L11-201209-221LMA30T_0805

1

2

L43

12

+1.1VS

L47

FBMA-L11-201209-221LMA30T_0805

1

C769

0_0805, no bead needed for this rail

2

10U_0603_6.3V6M

2010/07/04

0.1U_0402_16V7K

12

+1.1VALW

+1.1VS

C741

E

1

+

2

330U_D2_2.5VY_R9M

1

C742

2

10U_0603_6.3V6M

Change from SM010014520 to SD002000080

L51

+3VS

+1.1VALW

4 4

+3VS

L51

FBMA-L11-160808-221LMT_2P

C777 2.2U_0603_6.3V6KC777 2.2U_0603_6.3V6K

1 2

L52

FBMA-L11-160808-221LMT_2P

C780 2.2U_0603_6.3V6KC780 2.2U_0603_6.3V6K

1 2

L55

FBMA-L11-160808-221LMT_2P

C783 2.2U_0603_6.3V6KC783 2.2U_0603_6.3V6K

1 2

+VDDPL_33_SATA

12

+VDDPL11

12

+VDDPL33

12

A

20101012

+1.1VS

FBMA-L11-201209-221LMA30T_0805

+3VALW

FBMA-L11-160808-221LMT_2P

L53

0_0603_5%

SD013000080

nonHWM@

L50

L53

HWM@

12

1

C774

C773

2

22U_0805_6.3V6M

1

2

C781

C782

2

1

2.2U_0603_6.3V6K

HWM@ C781

HWM@

B

1

C778

2

1U_0402_6.3V6K

+VDDAN33_HWM

0.1U_0402_16V7K

1

C775

2

1U_0402_6.3V6K

+AVDD_SATA

1

C776

2

0.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF EN GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRO NICS, INC.

+VDDIO_AZ +3VALW

1 2

R634 0_0603_5%R634 0_0603_5%

1

C779

2.2U_0603_6.3V6K

2

2010/06/30 2012/06/30

C

For 3V AZ device

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

FCH PWR

LA6755P/7P

16 48Tuesday, November 30, 2010

E

1.0

of

Lenovo G575 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual