Lenovo E460,BE460 Schematic

A

B

C

D

E

PCI-Express 4X Gen2

PCIE , Port 9~12

1 1

Exo Pro 2G DDR3 S3 Meso XT 2G DDR3 S3

VRAM 256M*16 *4

Page 24~33

USB 2.0 , port 7

SkyLake

Intel

SkyLake-U 2+2 type

Memory BUS (DDRIII) 1DPC

1.35V DDRIIIL 1333/1600 MT/s

USB 2.0 , Port 4

DDR3L-SO-DIMM X2

BANK 0, 1, 2, 3

Page 22~23

UP TO 16G

Processor

eDP Conn.

Page 42

eDP , Port 1

BGA1356

40mm*24mm

HDMI Conn.

Page 50

One Link(DP port)

2 2

Page 38

HDMI_redriver

Page 49

DP_redriver

Page 37

DDI , CH2

DDI , CH1

+

USB 2.0 x 3

5V 480MHz

USB 3.0 X 3 5V 5GT/s

PCIe Gen1 , Port 3

USB 2.0 , Port 6

USB 3.0 , Port 3 USB 2.0 x 4

Intel

RJ45 Conn.

Page 52

WGI219V Non Vpro WGI219LM Vpro

PCIe , port 4

Page 51

PCIe Gen1, Port4

Intel PCH-LP

USB 2.0 , Port 1&2

USB3.0 redriver X2

PS87 13B

USB 3.0 Port 1&2

NGFF Card WLAN

USB charger (AOU)

TPS2546R TER USB 2.0 Port 3

Page 57

Page 43

USB 2.0 Port 6

PCIe Port 3

page 56

USB Left

USB 3.0 Port 1&2 USB 2.0 Port 1&2

USB3.0 redriver

PS87 13B

USB 3.0 Port 4

USB Right

USB 2.0 Port 3 USB 3.0 Port 3

Sub/B

Page 44 Page 45

Page 57

page 36

One-Link

USB 3.0 Port 4 USB 2.0 Port 4

Page 36~38

Realtek RTS5227S SD/MMC/XD

Sub/B

3 3

Page 58

JCARD Conn.

PCIe port 6

Page 57

SPI ROM 8M+4M

TPM NPCT650LAAYX

Mirror function

4 4

G-Sensor LIS3DHTR

LCFC Confidential

A

PCIe Gen1 , Port 6

Page 21

Page 60

B

SPI BUS

3.3V 33MHz

Touch Pad Track Point

Page 53

SATA Gen3 , Port 0

HD Audio

3.3V 24MHz

LPC BUS

3.3V 33MHz

Page 5~21

EC ITE IT8586EX

Page 66

Int.KBD

Page 55

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

Thermal Sensor F75303M

C

2013/09/07

Int. Camera

USB 2.0 Port 7

Finger printer

USB 2.0 Port 9

Page 59

LC Future Center Secret Data

Deciphered Date

Page 42

Page 54

SATA HDD

SATA Port 0

page 41

Codec CX1185 2-11Z

Page 39

MIC_CLK/MI C_DAT A

Int. MIC Conn. (JLCD Conn.)

Page 42 Page 57

D

Touch Panel

USB 2.0 Port 5

SP_OUTR /L

HP_R/L_J ACK

Ext. MIC Conn.

Sub/B

2014/09/07

Page 55

SPK Conn.

Page 40

HP Conn.

Title

BLOCK DIAGRAM

Size Document Number Re v

Custom

Monday, August 10, 2015

Date: Sheet of

Monday, August 10, 2015

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

E

2 83

1.0

A

B

C

D

E

Voltage Rails

Power Plane

1 1

State

S0

S3

2 2

S5 S4/AC Only

S5 S4 Battery only

( O --> Means ON , X --> Means OFF )

+1VALW

B+

+1.8VALW

+1.35V

+3VALW

+5VALW

O

O O O

OO

O

X

X X

+5VS +3VS +0.675V S

+VCC_CO RE

+VGA_CO RE

+3VS_VG A

+1.8VS_V GA

+1.35VS_ VGA

+1VS_VG A

X

STATE

S0

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

USB2 Port

1 2 3 4 5 6 7 8 9

SIGNAL

SLP_A# SLP_ S3# S LP_S4# SLP_S5# EC_ON SUSP#

HIGH HIGH HIGH HIGH

LOW LOW

DevicePor t

On Board On Board SUB/B ONE-Link DOCK Touch Panel BT CMO S FPR

X

HIGH

LOWLOWLOW

USB3 Port

1 2 3 4

ON ON

ON OFF

HIGH

ON

HIGH

ON

DevicePor t

On Board On Board SUB/B ONE-Link DOCK

OFF

OFFLOW LOW LOW LOW

PCIE Port

1 2 3 4 5 6 7 8 9 10 11 12

DevicePor t

X

WLA N LAN

X

CardReader

X

GPU GPU GPU GPU

SATA Port

1 2 3 4

DevicePor t

HDD

X X X

S5 S4 AC & Battery don't exist

X X

X

SMBUS Control Table

SOURCE

Main VGA

BATT SODIM M

WLAN WiMAX

Thermal Sensor

PCH

CP Module

Seccuri ty ROM

LAN PHY

G-Senso r

Issued Date

IT8580FEC_SMB_C K1

IT8580F

+3VS

PCH

+3VALW_P CH

PCH

+3VALW_P CH

C

EC_SMB_D A1

3 3

4 4

LCFC Confidential

A

B

EC_SMB_C K3

EC_SMB_D A3

PCH_SMB_ CLK PCH_SMB_D ATA

PCH_SML0_ CLK PCH_SML0_ DAT

Security Cl assification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

X

V

+3VS_VG A +3VS

X X

X X X X X X X X

2013/09/07

V

+3VALW+3VL

X

V

+3VS

LC Future Center Secret Data

Deciphered Date

X

D

X

V

X

2014/09/07

X

V

+3VALW_P CH

X

XX

V

+5VS

Title

Size Document Number Re v

Date: Sheet of

NOTE LIST

Custom

X

V

+3VS

+3VALW

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

BE460_NM-A551BE460_NM-A551

X

V

E

X

V

+3VALW

X

3 83

1.0

5

4

3

2

1

VGA and DDR3 Voltage Rails (JET TOPAZ GPIO)

GPIO I/ O

GPIO0

D D

C C

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO15

GPIO16

GPIO17

GPIO19

GPIO20 IN IN

GPIO21

GPIO22

GPIO29

GPIO30

ACTIVE

OUT

N/A

-

IN

-

IN

N/A

OUT

-

OUT

-

OUT

-

OUT

N/A

OUT

N/A

OUT

N/A

IN

N/A

OUT

N/A

OUT N/A

OUT

N/A

OUT

N/A

Function Description

GPIO5_AC_BATT

GPIO6

GPIO8_ROMSO

GPIO9_ROMSI

GPIO10_ROMSCK

SVI2_SVD

GPIO19_CTF

SVI2_SVC

GPIO22_ROMCSB

BOM Structure Table

BOM Structure

EXO @ For GPU_EXO

MESO@

DIS @

X76 @

TPM @

DIMM1@

DIMM2@

UMA @

For GPU_MESO

For GPU function

GPU VRAM Setting

Trusted Platform Module(TPM)

JDIMM1 function

JDIMM2 function

UMA SKU ID

DPRE@ DP re-driver function

NODPRE@ Disable DP re-driver

MIRROR@ For mirror function

ME@

ME Connector

For EMC functionEMC @

NVPRO@

For Non-VPRO function

For VPRO functionVPRO@

For U3 port1 redriver functionU31 @

For U3 port2 redriver functionU32 @

U33 @ For U3 port3 redriver function

NU3R@ No U3 redriver function (All port)

NOT E

RF@ For RF function

+3VS_VG A

TS@ For Touch function

+0.95VS_ VGA

B B

A A

+1.8VS_V GA

+VGA_CO RE

+1.35VS_ VGA

RESET

5

RV104

Samsung

Hynix

Micron

Issued Date

Memory (GDDR3)

3

1G

2G

1G

2G

1G

2G

2013/09/07

SA22225SH 30*4

SA000063F 00*4

SA00005VS 10*4

SA00005YL 10*4

SA00005M1 00*4

SA000060I 00*4

LC Future Center Secret Data

Deciphered Date

PU 8.45K

PU 3.4K PD 10K

PU 4.53K PD 2K

PU 4.75K NC

NC PD 4.75K

PU 3.24K PD 5.62K

2

2014/09/07

10us

1. all power rail ramp up time should be within 20ms

Device ID

JET-XT 0x6664

TOPAZ XT 0x6900

Security Cl assification

LCFC Confidential

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

RV105

PD 2K

Title

VGA NOTE

Size Document Number Re v

Custom

Wednesday, August 05, 2015

Date: Sheet of

Wednesday, August 05, 2015

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

1

4 83

1.0

5

D D

4

3

2

1

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

@

CPU_EDP_TX0-

C47

CPU_EDP_TX0+

C46

CPU_EDP_TX1-

D46

CPU_EDP_TX1+

C45 A45 B45 A47 B47

CPU_EDP_AUX#

E45

CPU_EDP_AUX

F45

B52

DOCK_AUXN

G50

DOCK_AUXP

F50 E48 F48 G46 F46

DOCKDP_HPD

L9

HDMI_HPD

L7 L6 N9

CPU_EDP_HPD

L10

R12

ENBKL PCH_EDP_PWM

R11

PCH_ENVDD

U13

?1 OF 20REV = 1

CPU_EDP_TX0- [42] CPU_EDP_TX0+ [42] CPU_EDP_TX1- [42] CPU_EDP_TX1+ [42]

CPU_EDP_AUX# [42] CPU_EDP_AUX [42]

DOCK_AUXN [37] DOCK_AUXP [37]

DOCKDP_HPD [37,38] HDMI_HPD [49]

CPU_EDP_HPD [42]

ENBKL [66] PCH_EDP_PWM [42] PCH_ENVDD [42]

ENBKL

CPU_EDP_HPD

[SKL PDG]EDP_HPD Pull down to ground via 100k ohm resistor

EDP

HDMI_H PD: Re-driver internal pull down

DOCKDP_ HPD: have been pulled down on page 38.

2014.1 2.15

20141208

1 2

RC209 100K_0402_5%

1 2

RC159 100K_0402_5%

?

DOCK_TX0-[37]

DOCKING

For 14" : HDMI

C C

DOCK_TX0+[37] DOCK_TX1-[37] DOCK_TX1+[37]

H_HDMI_TX2-[49] H_HDMI_TX2+[49] H_HDMI_TX1-[49] H_HDMI_TX1+[49] H_HDMI_TX0-[49] H_HDMI_TX0+[49] H_HDMI_TXC-[49] H_HDMI_TXC+[49]

20141126

HDMI_CLK[49] HDMI_DAT[49]

20141106

1 2

+VCC_IO

RC344 24.9_0402_1%

DOCK_TX0DOCK_TX0+ DOCK_TX1DOCK_TX1+

H_HDMI_TX2H_HDMI_TX2+ H_HDMI_TX1H_HDMI_TX1+ H_HDMI_TX0H_HDMI_TX0+ H_HDMI_TXCH_HDMI_TXC+

DP_DDC_CLK DP_DDC_DAT

HDMI_CLK HDMI_DAT

EDP_COMP

[SKL PDG]EDP_RCOMP Pull up to V CCIO via 24.9 ohm resistor

[SKL PDG]EDP_RCOMP

1. Trace width=20 mils, Spacing=25mil, Max length=100mils

2. RC1 close to MCP

B B

DDPB_CTRLDATA, DDPC_CTRLDATA Internal PD 20K

HDMI_CL K/HDMI _DAT, Re-driver IC has internal pull up through 2.36k.

2014.1 2.15

+3VS

1 2

RC277 2.2K_0402_5%@

1 2

RC287 2.2K_0402_5%@

1 2

RC1 2.2K_0402_5%@

1 2

RC2 2.2K_0402_5%

HDMI_CLK

HDMI_DAT

DP_DDC_CLK

DP_DDC_DAT

20141208

2015030 6

UC1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKYLAKE-U_BGA1356

SKL_U LT

DP

DDI

HDMI

DISPLAY SIDEBANDS

EDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

A A

Title

Security Cl assification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(1/16):DDI/EDP

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

5 83

1

5 83

1.0

5

D D

+VCC_STG

12

RC294 1K_0402_5%

+VCC_ST

H_PECI VR_HOT#

[SKL PDG]1 KΩ pull- up t o VCCST

1 2

RC53 1K_0402_1%

1 2

RC54 0_0402_5%@

EC_WAKE#[25,66]

[SKL PDG]PROC_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm ± 1 %. [SKL PDG]PCH_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm ± 1 %.

[SKL PDG]On Package Interface Compensation (OPI) Guidelines

Should be referenced to VSS plane only. VSS reference planes must be continuous

‧

Require low DC resistance routing <0.2 ohm

‧

Avoid routing next to clock pins or noisy signals.

‧

H_PECI[66]

C C

[SKL PDG]If THERMTRIP# goes active, the CPU is indicating an overheat condition, and the PCH will immediately transition to an S5 state. CPU_GP can be used from external sensors for the thermal management.

VR_HOT#[66,71,74]

H_THERMTRIP#[25]

4

201503 04

1 2

RC5 499_0402_1%

EC_WAKE#

1 2

RC40 0_0402_5%@

1 2

RC151 49.9_0402_1%

1 2

RC55 49.9_0402_1%

1 2

RC200 49.9_0402_1%

1 2

RC56 49.9_0402_1%

T60

T15 T16 T19 T20

1

VR_HOT#_R THRMTRIP#

XDP_BPM#0

1

XDP_BPM#1

1

XDP_BPM#2

1

XDP_BPM#3

1

EC_WAKE#_L

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP

UC1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

SKYLAKE-U_BGA1356

REV = 1

3

SKL_U LT

CPU MISC

?

JTAG

PROC_TCK

PROC_TDI PROC_TDO PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS

PCH_TRST#

4 OF 20

?

JTAGX

@

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

XDP_TCLK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST# PCH_JTAGX

2

201505 26

XDP_TDO

RC404 51_0402_1%

[SKL PDG]Refer Figure 45-1

201503 04

XDP_TDO

XDP_TDI

XDP_TMS

XDP_TCLK

XDP_TRST#

PCH_JTAG_TCK

RC3 51_0402_1%

RC31 51_0402_1%XDP@

RC34 51_0402_1%XDP@

RC4 51_0402_1%

RC6 51_0402_1%

RC372 51_0402_1%

1

T5

1

T4

1

T6

1

T3

1

T14

1

T9

1

T10

1

T11

1

T12

1

T8

1

T13

1 2

@

1 2

1

+VCC_STG

+VCC_ST

2015030 9

+1VALW_PCH

PCH_JTAG_TDI

PCH_JTAG_TMS

1 2

RC373 51_0402_1%XDP@

1 2

RC374 51_0402_1%XDP@

B B

A A

+3VALW_PCH

+3VS

RPC26

VGA_ON

18

DGPU_HOLD_RST#

27

EC_WAKE#

36 45

10K_0804_8P4R_5%

LCFC Confidential

5

VGA_ON [14,24,33,79] DGPU_HOLD_RST# [14,24]

4

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(2/16):MISC/JTAG

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

6 83

1

6 83

1.0

5

D D

DDR_A_D[0..63][22] DDR_A_DQS#[0..7][22] DDR_A_DQS[0..7][22] DDR_A_MA[0..15][22]

4

3

2

1

20141201

?

UC1B

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8

C C

B B

DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356

SKL_U LT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA [5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA [9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA [6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA [8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA [7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA [12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA [11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT # DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA [13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_M A[15]

DDR0_WE#/DDR0_C AB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_M A[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA [2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA [10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA [1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA [0]

DDR0_DQSN[2]/DDR0_DQSN[4]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[3]/DDR0_DQSP[5]

DDR0_DQSN[4]/DDR1_DQSN[0]

DDR0_DQSP[4]/DDR1_DQSP[0]

DDR0_DQSN[5]/DDR1_DQSN[1]

DDR0_DQSP[5]/DDR1_DQSP[1]

DDR0_DQSN[6]/DDR1_DQSN[4]

DDR0_DQSP[6]/DDR1_DQSP[4]

DDR0_DQSN[7]/DDR1_DQSN[5]

DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

?2 OF 20REV = 1

@

SA_CLK_DDR#0

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

AW50 AT52

AY67 AY68 BA67

AW67

SA_CLK_DDR0 SA_CLK_DDR#1 SA_CLK_DDR1

DDRA_CKE0_DIMMA DDRA_CKE1_DIMMA

DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# DDRA_ODT0_DIMMA# DDRA_ODT1_DIMMA#

DDR_A_MA5 DDR_A_MA9 DDR_A_MA6 DDR_A_MA8 DDR_A_MA7 DDR_A_BS2 DDR_A_MA12 DDR_A_MA11 DDR_A_MA15 DDR_A_MA14

DDR_A_MA13 DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_BS0 DDR_A_MA2 DDR_A_BS1 DDR_A_MA10 DDR_A_MA1 DDR_A_MA0 DDR_A_MA3 DDR_A_MA4

DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7

DDR0_ALERT#

SM_DIMM_VREFCA SA_DIMM_VREFDQ SB_DIMM_VREFDQ

DDR_PG_CTRL

SA_CLK_DDR#0 [22] SA_CLK_DDR0 [22] SA_CLK_DDR#1 [22] SA_CLK_DDR1 [22]

DDRA_CKE0_DIMMA [22] DDRA_CKE1_DIMMA [22]

DDRA_CS0_DIMMA# [22] DDRA_CS1_DIMMA# [22] DDRA_ODT0_DIMMA# [22] DDRA_ODT1_DIMMA# [22]

DDR_A_BS2 [22]

DDR_A_CAS# [22] DDR_A_WE# [22] DDR_A_RAS# [22] DDR_A_BS0 [22]

DDR_A_BS1 [22]

20141201

SM_DIMM_VREFCA [22] SA_DIMM_VREFDQ [22] SB_DIMM_VREFDQ [23]

DDR_PG_CTRL [22]

A A

Title

Security Cl assification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(3/16):DDR3L CH.A

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

7 83

1

7 83

1.0

5

4

3

2

1

D D

C C

B B

DDR_B_D[0..63][23] DDR_B_DQS#[0..7][23] DDR_B_DQS[0..7][23] DDR_B_MA[0..15][23]

DDR_B_D13 DDR_B_D9 DDR_B_D11 DDR_B_D14 DDR_B_D12 DDR_B_D8 DDR_B_D15 DDR_B_D10 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D5 DDR_B_D4 DDR_B_D7 DDR_B_D6 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D29 DDR_B_D28 DDR_B_D30 DDR_B_D31 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D21 DDR_B_D20 DDR_B_D22 DDR_B_D23 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

UC1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKYLAKE-U_BGA1356

REV = 1

SKL_U LT

?

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA [5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA [9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA [6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA [8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA [7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA [12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA [11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT # DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA [13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_M A[15]

DDR1_WE#/DDR1_C AB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_M A[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA [2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA [10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA [1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA [0]

DDR1_DQSN[0]/DDR0_DQSN[2]

DDR1_DQSP[0]/DDR0_DQSP[2]

DDR1_DQSN[1]/DDR0_DQSN[3]

DDR1_DQSP[1]/DDR0_DQSP[3]

DDR1_DQSN[2]/DDR0_DQSN[6]

DDR1_DQSP[2]/DDR0_DQSP[6]

DDR1_DQSN[3]/DDR0_DQSN[7]

DDR1_DQSP[3]/DDR0_DQSP[7]

DDR1_DQSN[4]/DDR1_DQSN[2]

DDR1_DQSP[4]/DDR1_DQSP[2]

DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

@

SB_CLK_DDR#0

AN45

SB_CLK_DDR#1

AN46

SB_CLK_DDR0

AP45

SB_CLK_DDR1

AP46

DDRB_CKE0_DIMMB

AN56

DDRB_CKE1_DIMMB

AP55 AN55 AP53

DDRB_CS0_DIMMB#

BB42

DDRB_CS1_DIMMB#

AY42

DDRB_ODT0_DIMMB#

BA42

DDRB_ODT1_DIMMB#

AW42

DDR_B_MA5

AY48

DDR_B_MA9

AP50

DDR_B_MA6

BA48

DDR_B_MA8

BB48

DDR_B_MA7

AP48

DDR_B_BS2

AP52

DDR_B_MA12

AN50

DDR_B_MA11

AN48

DDR_B_MA15

AN53

DDR_B_MA14

AN52

DDR_B_MA13

BA43

DDR_B_CAS#

AY43

DDR_B_WE#

AY44

DDR_B_RAS#

AW44

DDR_B_BS0

BB44

DDR_B_MA2

AY47

?

BA44 AW46 AY46 BA46 BB46 BA47

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21

AN43 AP43 AT13 AR18 AT18 AU18

DDR_B_BS1 DDR_B_MA10 DDR_B_MA1 DDR_B_MA0 DDR_B_MA3 DDR_B_MA4

DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7

DDR1_ALERT#

DDR3_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SB_CLK_DDR#0 [23] SB_CLK_DDR#1 [23] SB_CLK_DDR0 [23] SB_CLK_DDR1 [23]

DDRB_CKE0_DIMMB [23] DDRB_CKE1_DIMMB [23]

DDRB_CS0_DIMMB# [23] DDRB_CS1_DIMMB# [23]

DDRB_ODT0_DIMMB# [23] DDRB_ODT1_DIMMB# [23]

DDR_B_BS2 [23]

DDR_B_CAS# [23] DDR_B_WE# [23] DDR_B_RAS# [23] DDR_B_BS0 [23]

DDR_B_BS1 [23]

20141022

1 2

RC8 121_0402_1%

1 2

RC9 80.6_0402_1%

1 2

RC10 100_0402_1%

[SKL PDG]for DDR3L DDR_RCOMP[0] Pull down 121 ohm resistor DDR_RCOMP[1] Pull down 80.6 ohm resistor DDR_RCOMP[2] Pull down 100 ohm resistor

[SKL PDG]DDR_RCOMP

1. Trace width=12~15 mils, Spacing=20mil, Max length=500mils

2. R close to MCP

20141202

DDR3_DRAMRST# [22,23]

A A

Title

Security Cl assification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(4/16):DDR3L CH.B

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

8 83

1

8 83

1.0

5

D D

[SKL PDG]Manufacturing Mode Jumper

1. If strap is sampled low, the security measures def i ned i n t he Fl ash Descri pt or will be i n e f fect ( def ault)

2. If sampled high, the Flash Descriptor Security will be overridden.

33_0804_8P4R_5%

1 2

1

RF_NS@

CC538 47P_0402_50V8-J

2

RPC2

1 8 2 7 3 6 4 5

SD30000370T

HDA_BCLK

+3VALW_PCH

PCH_HDA_RST#[39] PCH_HDA_BCLK[39] PCH_HDA_SDOUT[39] PCH_HDA_SYNC[39]

C C

GPP_B14, Internal PD 20K No Reboot on TCO Timer expiration pull-up to VCC3_3 through a 1– 8.2 KΩ ± 5 % resistor to disable this capability

ME_FLASH[66]

PCH_HDA_RST# HDA_RST# PCH_HDA_BCLK HDA_BCLK PCH_HDA_SDOUT HDA_SDOUT PCH_HDA_SYNC HDA_SYNC

RC21 0_0402_5%@

PCH_HDA_BCLK

20141202

PCH_BEEP

B B

RC95

RC300

1 2

@

8.2K_0402_5%

1 2

20K_0402_5%

20141202

Processor Strapping 543016 _543016_SKL_PDG_UY_1_0_pu b P78 0

PCH_HDA_SDIN0

RC297

RC301

1 2

@

1 2

20K_0402_5%@

RGB( 0,255,128)

1K_0402_5%

+VCC_IO

4

Close to CPU

1 2

RC364 0_0402_5%@

PCH_HDA_SDIN0[39]

20141024

20141106

PCH_BEEP[40]

HDA_SYNC HDA_BCLK_R HDA_SDOUT PCH_HDA_SDIN0

HDA_RST#

PCH_BEEP

UC1G

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

SKYLAKE-U_BGA1356

REV = 1

AUDIO

3

?

SKL_U LT

7 OF 20

SDIO/SDXC

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD# GPP_G6/SD_CLK

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

@

GPP_G7/SD_WP

SD_RCOMP

GPP_F23

[SKL PDG] internal SD Card

?

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

2

RC363

1 2

200_0402_1%

1

20141106

20141202

+VCC_HDA

HDA_SDOUT

A A

HDA_SYNC

RC367

LCFC Confidential

5

RC299

RC302

1 2

@

1 2

@

1K_0402_5%

1 2

20K_0402_5%@

RGB( 0,255,128)

20141202

1K_0402_5%

+3VALW_PCH

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(5/16):HDA/SDIO

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

9 83

1

9 83

1.0

5

4

3

2

1

RTC External Circuit

1 2

RC11 0_0402_5%@

1

+RTCBATT, +RTCVCC Trace width = 20mils

D D

C C

CC2 1U_0402_10V6K

2

+3VS

1

2

20141202

1 2

RC29 10K_0402_5%DIS@

1 2

RC32 10K_0402_5%UMA@

WLAN

LAN

201410 24

VGA

+3VS

UMA@

1 2

RC165 10K_0402_5%

DIS@

1 2

RC166 10K_0402_5%

B B

CR

JCMOS, JME Setting, Need Under DDR Door

+RTCVCC+RTCVCC+RTCBATT

C8542

0.1U_0402_10V6-K

CLK_PCIE_WLAN#[56] CLK_PCIE_WLAN[56] CLKREQ_PCIE2_WLAN#[56]

CLK_PCIE_LAN#[51] CLK_PCIE_LAN[51] CLKREQ_PCIE3_LAN#[51]

CLK_PCIE_VGA#[24] CLK_PCIE_VGA[24] CLKREQ_PCIE4_VGA#[24]

CLK_PCIE_CR#[57] CLK_PCIE_CR[57] CLKREQ_PCIE5_CR#[57]

[SKL PDG]Exte rnal pull-up resistor required if used for CLKREQ# function ality.

CLKREQ_PCIE4_VGA#

RC12

1 2

20K_0402_5%

RC14

1 2

20K_0402_5%

DISCRETE_PRESENCE

+3VS

PCH_RTCRST#

CC1 1U_0402_10V6K

PCH_SRTCRST#

CC5 1U_0402_10V6K

CLK_PCIE_WLAN# SUSCLK_32K CLK_PCIE_WLAN CLKREQ_PCIE2_WLAN#

CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_PCIE3_LAN#

CLK_PCIE_VGA# CLK_PCIE_VGA CLKREQ_PCIE4_VGA#

CLK_PCIE_CR# CLK_PCIE_CR CLKREQ_PCIE5_CR#

RPC200

1 8 2 7 3 6 4 5

CLKREQ_PCIE2_WLAN# CLKREQ_PCIE3_LAN#

CLKREQ_PCIE5_CR#

10K_0804_8P4R_5%

JCMOS1 @

1 2

JME1 @

1 2

UC1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKYLAKE-U_BGA1356

REV = 1

201410 24

SKL_U LT

CLOCK SIGNALS

?

10 OF 20

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

@

F43 E43

BA17

E37 E35

E42

AM18 AM20

AN18 AM16

?

[SKL PDG]Used to set BIAS reference for differential clocks. Connect to a 2.71K ± 0.5% precision resistor to 1.0v.

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

PCH_XTAL24_IN PCH_XTAL24_OUT

DIFFCLK_BIASREF

PCH_RTCX1 PCH_RTCX2

PCH_SRTCRST# PCH_RTCRST#

1

T52

1

T53

SUSCLK_32K [56]

1 2

20141126

RC362

2.7K_0402_1%

2015030 5

+1VALW

20141126

[SKL PDG]

1.Space > 15mils

2.No trace under crystal

3.Place on oppsosit side of MCP for temp inf l uence

4.The exact capacitor values forC1 and C2 must be based on the crystal maker recommendat i ons. Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF.

RTC Crystal

RC13

1 2

10M_0402_5%

YC1

Only Change P/N of YC1 to SJ10000J900 The Descripton of P/N is 9H03280012

A A

Security Cl assification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

1 2

32.768KHZ_12.5PF_9H03200042

1

CC3

5.6P_0402_50V8-D

2

3

2014/05/07

PCH_RTCX1

PCH_RTCX2

[SKL PDG]Max Crystal ESR = 50k Ohm.

1

CC4

5.6P_0402_50V8-D

2

LC Future Center Secret Data

Deciphered Date

[SKL PDG]

1.A 24 MHz crystal with crystal frequency tolerance and stability of +/-30 ppm

2.Two External Load Capacitors (Ce1 and Ce2)

3.A 1-Mo hm bias resistor (Rf)

2

2015/05/07

PCH_XTAL24_IN

PCH_XTAL24_OUT

CC6

12P_0402_50V8-J

Title

SKL(6/16):CLOCK SIGNALS

Size Document Number Re v

Custom

Date: Sheet of

RC30

1 2

1M_0402_5%

YC2

1

GND1

1

2

Wednesday, August 05, 2015

GND2

2

4

24MHZ_10PF_8Y24000011

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

3

1

CC7 12P_0402_50V8-J

2

10 83

1.0

5

4

3

2

1

Functional Strap Definitio ns

GPP_C2, Internal PD 20K

SPI0_MOSI

This signal has an internal pull-up. This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

D D

SPI_SI

20141202

SPI_SO

20141202

RC298

20150305

1 2

RC308

20150305

1 2

@

8.2K_0402_5%

@

8.2K_0402_5%

+3VALW_PCH

L:Disable Intel ME Crypto TLS cipher suite (no confidentiality). *H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality).Support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.

+3VALW_PCH+3VALW_PCH

GPP_C2

RC306

RC307

1 2

20K_0402_5%@

RGB( 0,255,128)

1K_0402_5%

GPP_C5, Internal PD 20K

*L: LPC H: eSPI

GPP_C5

RC83 1K_0402_5%@

RC84 20K_0402_5%

+3VALW_PCH

12

1 2

SPI_SO[21,60] SPI_SI[21,60] SPI_IO2[21]

SPI_IO3[21] SPI_CS0#_8MB[21] SPI_CS1#_4MB[21] SPI_CS2#_TPM[60]

CL_DATA_WLAN[56] CL_RST_WLAN#[56]

KBRST#[66]

SERIRQ[60,66]

20141202

0_0402_5%@

EC_SCI#[66]

CL_CLK_WLAN[56]

PCH_SPI_CLK SPI_SO SPI_SI SPI_IO2 SPI_IO3 SPI_CS0#_8MB SPI_CS1#_4MB SPI_CS2#_TPM

EC_SCI#

KBRST#

SERIRQ

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

M2 M3

J4 V1 V2

M1

G3 G2 G1

AW13

AY11

SKYLAKE-U_BGA1356

REV = 1

UC1E

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

Close to CPU

C C

SPI_CLK[21,60]

RC365

2014 110 6

SKL_U LT

?

5 OF 20

LPC

SMBUS, SMLINK

GPP_C2/SMBALERT#

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

[SKL PDG]RCIN# Pull-up to Vcc3_3 with 10 Kohm resistor.

B B

+3VS

RPC22

18

SERIRQ EC_SCI#

27 36 45

10K_0804_8P4R_5%

A A

KBRST#

PCH_SML0_CLK PCH_SML0_DAT

PCH_SMB_CLK PCH_SMB_DATA PCH_SML1CLK PCH_SML1DATA

GPP_B23

[SKL PDG]SERIRQ uses a 8.2 KΩ pull-up to +V3.3S power-rail. [SKL CRB]SERIRQ uses a 10 KΩ pull-up to +V3.3S power-rail.

1 2

RC92 499_0402_1%

1 2

RC93 499_0402_1%

1 2

RC375 4.7K_0402_5%

1 2

RC376 4.7K_0402_5%

1 2

RC377 2.2K_0402_1%

1 2

RC378 2.2K_0402_1%

RC101 1K_0402_5%

12

+3VALW_PCH

PCH_SMB_CLK

+3VS

PCH_SMB_DATA PCH_SML1DATA

SB000013A00

2N7002KDWH_SOT363-6 QC1A

6 1

D

S

G

2

5

G

3 4

S

D

QC1B 2N7002KDWH_SOT363-6

SB000013A00

RC106 4.7K_0402_5%

RC107 4.7K_0402_5%

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C3/SML0CLK

GPP_C6/SML1CLK

GPP_A8/CLKRUN#

?

1 2

@

PCH_SMB_CLK

R7

PCH_SMB_DATA

R8

GPP_C2

R10

PCH_SML0_CLK

R9

PCH_SML0_DAT

W2

GPP_C5

W1

PCH_SML1CLK

W3

PCH_SML1DATA

V3

GPP_B23

AM7

AY13 BA13 BB13 AY12 BA12

SUS_STAT#

BA11

PCH_PCI_CLK_R

AW9 AY9 AW11

CLKRUN#

[SKL PDG]CLKRUN# Requires an 8.2 KΩ we ak pull -up r esi st or t o Vcc3_3

PM_SMB_CLK [21,22,23,53]

+3VS

PM_SMB_DAT [21,22,23,53]

DIMM1, DIMM2, Security EEPROM, C lick Pad

PCH_SML0_CLK [51] PCH_SML0_DAT [51]

EC,dGPU,Thermal Sensor

LPC_AD0 [66] LPC_AD1 [66] LPC_AD2 [66] LPC_AD3 [66] LPC_FRAME# [66]

1 2

RC52 8.2K_0402_5%

+3VS

RC47 0_0402_5%@

RC24 22_0402_5%EMC@

+3VS

20141202

PCH_SML1CLK

1 2

2N7002KDWH_SOT363-6 QC2A

6 1

D

3 4

D

QC2B 2N7002KDWH_SOT363-6

2

5

LAN

G

SB000013A00

S

SB000013A00

1

RF_NS@

CC537 47P_0402_50V8-J

2

T18

2014 112 8

CLK_PCI_EC [66]

2014 112 8

EC_SMB_CK3 [25,37, 59,60,66]

EC_SMB_DA3 [25,37, 59,60,66]

Title

Security Classification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(7/16):LPC/SPI/SMBUS/CL

Size

Document Number Re v

C

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

1

11 83

1.0

5

D D

VCCST_PG_EC

PCH_SYSPWROK[66]

PCH_PWROK[66] EC_DPWROK[66]

20141205

C C

20141208

[SKL PDG]AC_PRESENT:8.2~10 KΩ pull- up t o DS W well.

[SKL PDG]BATLOW#:8.2~10 KΩ pull- up t o DS W well.

[SKL PDG]WAKE# :10 KΩ pull - up to Vcc DS W3_3.

[SKL PDG]APWROK :There is no corresponding APWROK signal input to the PCH, but the PCH does have an internally generated version of APWROK

that is t i med fr o m SL P_A#.

LANPHYPC[51]

4

[SKL PDG]SYS_RESET#:Connect this signal on PCH directly to the reset but t on and pull- up this si gnal t o +V3. 3 V core r ail t hr ough a weak pull-up resistor (8.2~10 Kohm).

[SKL PDG]PROCPWRGD

1.Indicates that VCCIN, VDDQ power supplies and clocks are stable. This signal will be asserted only af t er PC H_P WR OK assert i on.

2.PROCPWRGD is used only for power sequence debug and is not required to be connected to anything on the plat f or m.

+3VS

PLTRST#[24]

1 2

RC108 10K_0402_5%

EC_RSMRST#[66]

1 2

RC387 60.4_0402_1%

1 2

RC41 0_0402_5%@

1 2

EC_RSMRST#

RC286 0_0402_5 %@

1 2

RC352 0_0402_5%@

1 2

RC109 0_0402_5%@

PCIE_WAKE#

LANPHYPC

VCCST_PG_EC[66]

PWROK

T59

1 2

1

RC403 10K_0402_5%

@

PLTRST# SYS_RESET#

EC_RSMRST#

H_CPUPWRGD

VCCST_PWRGD_R

PCH_SYSPWROK PWROK

EC_DPWROK_R

SUSWARN# SUSACK#

GPD7

@

RC411

1 2

0_0402_5%

AN10

B5

AY17

A68 B65

B6 BA20 BB20

AR13 AP11

BB15 AM15

AW17

AT15

SKYLAKE-U_BGA1356

REV = 1

3

UC1K

GPP_B13/PLTRST# SYS_RESET# RSMRST#

PROCPWRGD VCCST_PWRGD

SYS_PWROK PCH_PWROK DSW_PWR OK

GPP_A13/SUSWARN#/SUS PWRDNACK GPP_A15/SUSACK#

WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD

SKL_U LT

SYSTEM POWER MANAGEMENT

+VCC_STG

RC123

10K_0402_5%

VCCST_PWRGD

?

12

@

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B11/EXT_PWR_GATE#

INTRUDER#

GPP_B2/VRALERT#

2

[SKL PDG]SLP_S3, SLP_S4, SLP_S5 No pull-up/pull-down resistors needed. Signals driven by the PCH.

[SKL PDG]SLP_A:No pull-up/pull-down resistors needed. Signals driven by the PCH. Can be lef t as NC when I nt el R Act i ve Manag ement Tec hnol ogy ( IntelR AMT) is not

@

supported on the plat f or m. When asserted ( 0) I nt el R ME is i n M- Off

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

PCH_SLP_LAN# PCH_SLP_WLAN# PM_SLP_A#

PBTN_OUT# AC_PRESENT

BATLOW#

PME#

PCH_INTRUDER#

EXT_PWR_GATE#

VRALERT#

20141106

1

T50

PM_SLP_S3# [66] PM_SLP_S4# [66] PM_SLP_S5# [66]

PCH_SLP_LAN# [51,66] PCH_SLP_WLAN# [66] PM_SLP_A# [66]

PBTN_OUT# [66]

AC_PRESENT [66]

1

T62

RC16 1M_0402_5%

1 1

12

T61 T49

20141205

2015030 5

+RTCVCC

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#

PM_SLP_A#

PBTN_OUT#

Connect to Power

?11 OF 20

[SKL PDG]EXT_PWR_GATE#(External Power Gate)

1.HSIO Power Control: Used to control power to VCCMPHYGT_1p0, VCCMPHYPLL_1p0 and VCCSRAM_1p0 in S0 & Sx.

2.PCH will drive EXT_PWR_GATE# low when all the high speed IO controllers (xHCI, SATA and PCIe) are idle or have no devices at t ached.

1

TP125

1

TP126

1

TP127

1

TP128

1

TP129

+3VALW

B B

[SKL PDG]RSMRST#:Recommend an 8.2~10 Kohm pull-down resistor to ground. Note: CRB uses 10 KΩ pull - down.

A A

1 8 2 7 3 6 4 5

RC379

RC351

RC353

EMC_NS@

RPC18

10K_0804_8P4R_5%

SD300002P0T

RPC6

18 27 36 45

10K_0804_8P4R_5%

@

1 2

10K_0402_5%

@

1 2

10K_0402_5%

@

1 2

10K_0402_5%

RC27

1 2

10K_0402_5%

Close to CPU

CC527

1 2

5P_0402_50V9-C

CC528

1 2

5P_0402_50V9-C

CC529

1 2

5P_0402_50V9-C

AC_PRESENT BATLOW#

PCH_SLP_LAN#

PCIE_WAKE#

PCH_SLP_WLAN#

PBTN_OUT#

GPD7

EC_DPWROK

20141124

2015030 4

VCCST_PG_EC

2015030 5

20141210

EC_RSMRST#

PCH_SYSPWROK

PWROK

EC_DPWROK_R

LCFC Confidential

5

4

+VCC_STG

RC383 1K_0402_5%

1 2

UC3

1

NC

PLTRST#

RC26

100K_0402_5%

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

2

IN_A

3

12

GND

TC7SG17FE_SON5

LC Future Center Secret Data

Deciphered Date

VCC

OUT_Y

+3VALW

5

4

1 2

RC348 33_0402_5%

1 2

RC48 33_0402_5%

1

CC9

100P_0402_25V8J

2015/05/07

2

PLTRST_NEAR# [21]

1

CC102 100P_0402_25V8J

2

Size Document Number Re v

Date: Sheet of

PLTRST_FAR# [51,56,57,60,66]

Title

SKL(8/16):SYSTEM PM

Custom

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

12 83

1

12 83

1.0

5

D D

+VCC_CORE

[SKL PDG]VCC

[SKL PDG] 10uF x 3 , 1uF x 34.

10U_0603_6.3V6-M

CC235

12

@

4

+VCC_GT

[SKL PDG]VCCGT

[SKL PDG] 10uF x 4, 1uF x 16

10U_0603_6.3V6-M

CC274

CC273

12

@

CC276

CC275

12

@

3

10U_0603_6.3V6-M

CC277

CC278

12

@

10U_0603_6.3V6-M

CC279

CC280

12

@

10U_0603_6.3V6-M

CC281

CC282

12

10U_0603_6.3V6-M

CC520

12

10U_0603_6.3V6-M

CC521

12

2

1

20141126

1U_0201_6.3V6-M

CC236

CC237

12

@

C C

1U_0201_6.3V6-M

CC247

CC248

1

2

CC239

CC238

12

1U_0201_6.3V6-M

CC249

1

2

CC240

12

1U_0201_6.3V6-M

CC251

CC250

1

2

10U_0603_6.3V6-M

CC241

CC243

12

1U_0201_6.3V6-M

CC253

CC252

1

2

1U_0201_6.3V6-M

CC244

1

2

1U_0201_6.3V6-M

CC254

1

2

1U_0201_6.3V6-M

CC245

1

2

1U_0201_6.3V6-M

CC255

1

2

1U_0201_6.3V6-M

CC246

1

2

1U_0201_6.3V6-M

CC256

1

2

1U_0201_6.3V6-M

CC284

CC283

1

2

1U_0201_6.3V6-M

CC293

CC294

1

2

1U_0201_6.3V6-M

CC285

CC286

1

2

1U_0201_6.3V6-M

1

2

1U_0201_6.3V6-M

CC287

CC288

1

2

1U_0201_6.3V6-M

CC290

CC289

1

2

1U_0201_6.3V6-M

CC292

CC291

1

2

CC522

1

2

1U_0201_6.3V6-M

CC523

CC524

1

2

1U_0201_6.3V6-M

CC525

1

2

1U_0201_6.3V6-M

CC505

CC503

1

2

1U_0201_6.3V6-M

CC515

CC512

B B

A A

1

2

1U_0201_6.3V6-M

CC257

CC242

1

2

10U_0603_6.3V6-M

CC267

CC266

12

CC506

CC504

1

2

1U_0201_6.3V6-M

CC514

CC516

1

2

10U_0603_6.3V6-M

12

10U_0603_6.3V6-M

CC268

CC269

12

1U_0201_6.3V6-M

LCFC Confidential

5

1U_0201_6.3V6-M

CC507

CC508

1

2

1U_0201_6.3V6-M

CC517

1

2

10U_0603_6.3V6-M

CC271

12

CC509

1

2

1U_0201_6.3V6-M

CC518

CC519

1

2

10U_0603_6.3V6-M

CC272

CC270

12

1U_0201_6.3V6-M

CC501

CC500

1

2

1U_0201_6.3V6-M

CC510

CC511

1

2

10U_0603_6.3V6-M

12

1U_0201_6.3V6-M

CC502

1

2

1U_0201_6.3V6-M

1

2

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(9/16):Decoupling

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

13 83

1

13 83

1.0

5

4

3

2

1

GPP_B18, Internal PD 20K

*L: Disable “ No Reboot” mode H: Enable “ No Reboot” mode

D D

GPP_B18

C C

2015030 5

RC97 1K_0402_5%@

1 2

RC98 20K_0402_5%@

20141211

BT_ON[56]

F4_LED#[55] PCH_TSOFF#[55]

VGA_ON[6,24,33,79] DGPU_HOLD_RST#[6,24]

RF_OFF#[56]

PCH_CMOS_ON[42]

CP_BYPASS[53,66]

+3VALW_PCH +3VALW_PCH

12

RF_OFF#

PCH_CMOS_ON

BT_ON

CP_BYPASS

TP_REST[53,66]

TP_REST

DGPU_PWROK

F4_LED# PCH_TSOFF#

VGA_ON DGPU_HOLD_RST#

20141210

+3VALW_PCH

RC371

RF_OFF#

B B

1 2

10K_0402_5%

20141222

GPP_B22, Internal PD 20K

*L: SPI H: LPC

GPP_B22

TC119 TC120

12 12 12

@

RC406 0_0402_5% RC407 0_0402_5%

RC389 0_0402_5 %@

2015030 9

@

RC99 1K_0402_5%

1 2

RC100 20K_0402_5%

2015030 5

GPP_B18

GPP_B22

PLANARID0 CP_BYPASS_R

TP_REST_R

1 1

PLANARID1

MIC_HW_EN

RC366 0_0402_5%

1 2

12

UC1F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

SKYLAKE-U_BGA1356

AH11

REV = 1

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

?

LPSS ISH

SKL_U LT

6 OF 20

GPP_D5/ISH_I2C0_SDA

GPP_D7/ISH_I2C1_SDA

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BD ATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK /I2C4B_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALE RT#

GPP_C12/UART1_RXD/ISH_UART1_R XD

GPP_C13/UART1_TXD/ISH_UART1_TX D GPP_C14/UART1_RTS#/ISH_UART1_R TS# GPP_C15/UART1_CTS#/ISH_UART1_C TS#

?

GPP_A12/BM_BUSY#/ISH_GP6

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D6/ISH_I2C0_SCL

GPP_D8/ISH_I2C1_SCL

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

Project ID

PLANAR ID0

(GPP_B 5) PLA NARID2

(GPP_C 8)

L

14"

15"

PLANARID0

PLANARID1

DGPU_PWROK

UMA

DIS

10K_0402_5%

H

@

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

FN_LED# F1_LED#

0_0402_5%

1

RC405

TC118

CP_RESET#CP_RESET#_R

12

FN_LED# [55] F1_LED# [55]

CP_RESET# [53,66]

DGPU_PWROK[15,33,79]

(GPP_C 10)

1(X )

12

RC67

12

@

RC71

DGPU_P WROK (GPP_A 7)

* *

Only for 14NM

12

RC409

10K_0402_5%

@

12

RC410

10K_0402_5%

@

10K_0402_5%

+3VS

12

RC70

@

12

RC74

+3VS

A A

2015030 9 (delete RC349 , CMOS_ON pull high)

LCFC Confidential

5

RPC8

18

F4_LED#

27

F1_LED#

36

FN_LED#

45

10K_0804_8P4R_5%

@

RPC10

18 27 36 45

10K_0804_8P4R_5%

4

BT_ON CP_BYPASS PCH_TSOFF#

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(10/16):GPIO/CPU/MISC

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

14 83

1

14 83

1.0

5

D D

4

3

2

1

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

?

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E9/USB2_OC0#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E8/SATALED#

@

USB3P1_RXN

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6 AG3 AG4

A9 C9 D9 B9

J1 J2 J3

H2 H3 G4

H1

USBCOMP

ONEDOCK_DET#

USB3P1_RXP USB3P1_TXN USB3P1_TXP

USB3P2_RXN USB3P2_RXP USB3P2_TXN USB3P2_TXP

USB3P3_RXN USB3P3_RXP USB3P3_TXN USB3P3_TXP

USB3P4_RE_RXN USB3P4_RE_RXP USB3P4_TXN USB3P4_TXP

USB20_N0 USB20_P0

USB20_N1 USB20_P1

USB20_N2 USB20_P2

USB20_N3 USB20_P3

USB20_N4_TPANEL USB20_P4_TPANEL

USB20_N5 USB20_P5

USB20_N6 USB20_P6

USB20_N8 USB20_P8

RC359 113_0402_1%

RC385 1K_0402_5%

RC386 1K_0402_5%

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

HDD_DEVSLP0 SSD_DEVSLP1

GPP_E0

1 2 1 2 1 2

USB3P1_RXN [43] USB3P1_RXP [43] USB3P1_TXN [43] USB3P1_TXP [43]

USB3P2_RXN [43] USB3P2_RXP [43] USB3P2_TXN [43] USB3P2_TXP [43]

USB3P3_RXN [57] USB3P3_RXP [57] USB3P3_TXN [57] USB3P3_TXP [57]

USB3P4_RE_RXN [36] USB3P4_RE_RXP [36] USB3P4_TXN [36] USB3P4_TXP [36]

USB20_N0 [44] USB20_P0 [44]

USB20_N1 [45] USB20_P1 [45]

USB20_N2 [57] USB20_P2 [57]

USB20_N3 [38] USB20_P3 [38]

USB20_N4_TPANEL [55] USB20_P4_TPANEL [55]

USB20_N5 [56] USB20_P5 [56]

USB20_N6 [42] USB20_P6 [42]

USB20_N8 [54] USB20_P8 [54]

20150519

USB_OC0# [44] USB_OC1# [57]

TP117

HDD_DEVSLP0 [41]

1

ONEDOCK_DET# [38]

On Board (Right-Front)

On Board (Ri ght-Back)

S/B (AOU Port)

20141024

Ddcking

20141024

On Board (Right-Front)

On Board (Ri ght-Back)

S/B (AOU Port)

DOCKING

Touch Panel

BT

USB_OC0#

USB_OC1#

USB_OC2#

USB_OC3#

USB Port Number

Port 0, Port1

Port 2, Port3

Port 4, Port5

Port 6, Port7

CAMERA

FPR

SMART CARD (Hub)

[SKL PDG]USBCOMP:112.5 ohm ± 1 % connected t o GND

20141121

ONEDOCK_DET#

RC368

1 2

10K_0402_5%

+3VALW_PCH

?

3D camera

CR

HDD

ODD(NGFF)

GPU

SKL_U LT

USB3.0 on board

ChargerPort

WLAN

LAN

Sub/B Charger Port

8 OF 20

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

Docking

On board

ONE DOCK

Touch Panel

USB2

BT

Camera

FPR

Smart Card

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

UC1H

PCIE/US B3/S ATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE3_CRX_DTX_N[56]

WLAN

LAN

C C

Card Rea der

HDD

PCIE3_CTX_C_DRX_N[ 56] PCIE3_CTX_C_DRX_P[56]

PCIE4_CTX_C_DRX_N[ 51] PCIE4_CTX_C_DRX_P[51]

PCIE6_CRX_DTX_N[57]

PCIE6_CRX_DTX_P[57] PCIE6_CTX_C_DRX_N[ 57] PCIE6_CTX_C_DRX_P[57]

SATA_PRX_DTX_N0[41]

SATA_PRX_DTX_P0[41] SATA_PTX_DRX_N0[41] SATA_PTX_DRX_P0[41]

CC18 0.1U_0402_10V7-K CC19 0.1U_0402_10V7-K

CC92 0.1U_0402_10V7-K CC93 0.1U_0402_10V7-K

PCIE3_CRX_DTX_P[56]

1 2 1 2

PCIE4_CRX_DTX_N[51] PCIE4_CRX_DTX_P[51]

1 2 1 2

1 2

CC20 0.1U_0402_10V7-K

1 2

CC21 0.1U_0402_10V7-K

SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0

PCIE3_CRX_DTX_N PCIE3_CRX_DTX_P PCIE3_CTX_DRX_N PCIE3_CTX_DRX_P

PCIE4_CRX_DTX_N PCIE4_CRX_DTX_P PCIE4_CTX_DRX_N PCIE4_CTX_DRX_P

PCIE6_CTX_DRX_N PCIE6_CTX_DRX_P

ODD, only for 15"

PCIE_RCOMP

1 1

PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P0 PCIE1_PTX_DRX_N0 PCIE1_PTX_DRX_P0

PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE2_PTX_DRX_N1 PCIE2_PTX_DRX_P1

XDP_PRDY_N XDP_PREQ_N

DGPU_PWROK_R

PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE3_PTX_DRX_N2 PCIE3_PTX_DRX_P2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE4_PTX_DRX_N3 PCIE4_PTX_DRX_P3

PCIE_CRX_GTX_N0[24]

1 2

PCIE_CTX_C_GRX_N0[24] PCIE_CTX_C_GRX_P0[24]

PCIE_CTX_C_GRX_N1[24] PCIE_CTX_C_GRX_P1[24]

DGPU_PWROK[14,33,79]

B B

GPU

PCIE_CTX_C_GRX_N2[24] PCIE_CTX_C_GRX_P2[24]

PCIE_CTX_C_GRX_N3[24] PCIE_CTX_C_GRX_P3[24]

CC86 0.1U_0402_10V7-KDIS@ CC87 0.1U_0402_10V7-KDIS@

CC88 0.1U_0402_10V7-KDIS@ CC89 0.1U_0402_10V7-KDIS@

CC90 0.1U_0402_10V7-KDIS@ CC23 0.1U_0402_10V7-KDIS@

CC24 0.1U_0402_10V7-KDIS@ CC91 0.1U_0402_10V7-KDIS@

1 2

1 2 1 2

PCIE_CRX_GTX_P0[24]

PCIE_CRX_GTX_N1[24] PCIE_CRX_GTX_P1[24]

100_0402_1%

1 2

RC360

20141124

TP115 TP116

@

1 2

RC384 0_0402_5%

PCIE_CRX_GTX_N2[24] PCIE_CRX_GTX_P2[24]

PCIE_CRX_GTX_N3[24] PCIE_CRX_GTX_P3[24]

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKYLAKE-U_BGA1356

REV = 1

[SKL PDG]PCIE_RCOMP

1.100 ohm +/-0.1% external resistor between RCOMPP/RCOMPN

2.SATA compensat i on circ ui t i s code s hare wi th PCIE_RCOMPP/N dif f er ent ial pair. Refer to PCI Express Design Guidelines chapter for PCIE_RCOMPP/N guideline.

3.Width: 12~15Mil Space:>12M il Length:Both RCOMP & RCOMPN need to matched to less than 1% trace and board

A A

Security Classification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

[SKL PDG] OC [x] pins require a pull-up to VccSus3_3 with 8.2~10 Kohm resistors

[SKL PCH EDS]no external pull-up or pull-down termination required when used as DEVSLP

HDD_DEVSLP0

GPP_E0

DGPU_PWROK_R

2015/05/07

USB_OC2# USB_OC1# USB_OC0# USB_OC3#

12

RC88 10K_0402_5%

12

RC388 10K_0402_5%

20150519

12

RC408 10K_0402_5%

20150714

Title

SKL(11/16):PCIE/USB/SATA

Size

Document Number Re v

C

Date: Sheet o f

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

+3VS

RPC15

10K_0804_8P4R_5%

1

18 27 36 45

15 83

1.0

5

+VCC_CORE +VCC_CORE

D D

20141126

C C

AK33 AK35 AK37 AK38 AK40 AL33 AL37

AL40 AM32 AM33 AM35 AM37 AM38

AK32

AB62

AC63

AE63

AE62

AG62

AL63

AJ62

A30 A34 A39 A44

G30

K32

P62 V62

H63

G61

SKL_U LT

UC1L

CPU POWER 1 OF 4

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

SKYLAKE-U_BGA1356

REV = 1

VCCOPC_SENSE VSSOPC_SENSE

VCCEOPIO_AE62 VCCEOPIO_AG62

VCCEOPIO_SENSE VSSEOPIO_SENSE

20141126

+VCC_STG +VCC_ST +VCC_ST

1U_0402_10V6K

CC68

1

B B

[SKL PDG]VCCSTG

[SKL PDG]1uF x1

CC94

[SKL PDG]VDDQC

[SKL PDG]1uF x1

A A

2

Primary side cap

[SKL PDG]VCCST

[SKL PDG]1uF x1

+1.35V

1U_0402_10V6K

1U_0201_6.3V6-M

CC344

1

2

2015030 9

2

Primary side cap

[SKL PDG]VCCPLL

[SKL PDG]1uF x1 Close to AL23

VCCGT_SENSE[74]

VSSGT_SENSE[74]

CC69

+1.35V

CC526

1U_0402_10V6K

1

2015030 9

2

Primary side cap

[SKL PDG]VCCPLL

[SKL PDG]1uF x1 Close to K20,K21

1U_0201_6.3V6-M

1

2

+VCC_GT

RC125

100_0402_1%

RC184

100_0402_1%

12

RC124 0_0402_5%@ RC183 0_0402_5%@

12

1U_0402_10V6K

CC70

1

2

1 2 1 2

+VCC_GT

4

?

VCC_SENSE VSS_SENSE

VIDALERT#

VCCSTG_G20

12 OF 20

UC1M

A48

VCCGT_A48

A53

VCCGT_A53

A58

VCCGT_A58

A62

VCCGT_A62

A66

VCCGT_A66

AA63

VCCGT_AA63

AA64

VCCGT_AA64

AA66

VCCGT_AA66

AA67

VCCGT_AA67

AA69

VCCGT_AA69

AA70

VCCGT_AA70

AA71

VCCGT_AA71

AC64

VCCGT_AC64

AC65

VCCGT_AC65

AC66

VCCGT_AC66

AC67

VCCGT_AC67

AC68

VCCGT_AC68

AC69

VCCGT_AC69

AC70

VCCGT_AC70

AC71

VCCGT_AC71

J43

VCCGT_J43

J45

VCCGT_J45

J46

VCCGT_J46

J48

VCCGT_J48

J50

VCCGT_J50

J52

VCCGT_J52

J53

VCCGT_J53

J55

VCCGT_J55

J56

VCCGT_J56

J58

SKYLAKE-U_BGA1356

VCCGT_J58

J60

REV = 1

VCCGT_J60

K48

VCCGT_K48

K50

VCCGT_K50

K52

VCCGT_K52

K53

VCCGT_K53

K55

VCCGT_K55

K56

VCCGT_K56

K58

VCCGT_K58

K60

VCCGT_K60

L62

VCCGT_L62

L63

VCCGT_L63

L64

VCCGT_L64

L65

VCCGT_L65

L66

VCCGT_L66

L67

VCCGT_L67

L68

VCCGT_L68

L69

VCCGT_L69

L70

VCCGT_L70

L71

VCCGT_L71

M62

VCCGT_M62

N63

VCCGT_N63

N64

VCCGT_N64

N66

VCCGT_N66

N67

VCCGT_N67

N69

VCCGT_N69

J70

VCCGT_SENSE

J69

VSSGT_SENSE

@

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VIDSCK

VIDSOUT

SKL_U LT

CPU POWER 2 OF 4

3

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

VR_SVID_ALRT#_R

B63

VR_SVID_CLK

A63

VR_SVID_DAT

D64

G20

+VCC_ST

12

Rpu1

RC356

@

VR_SVID_CLK VR_SVID_DATVR_SVID_ALRT#VR_SVID_ALRT#_R

1 2

RC121 0_0402_5%@

1 2

RC142 0_0402_5%@

+VCC_STG

100_0402_1%

2015030 5 2015030 5

+VCC_CORE

[SKL PDG]VIDSCK [SKL PDG]VIDALERT# [SKL PDG]VIDSOUT

VR_SVID_CLK [74] VR_SVID_DAT [74]VR_SVID_ALRT# [74]

12

RC120 100_0402_1%

VCC_SENSE [74]

12

RC143 100_0402_1%

VSS_SENSE [74]

[SKL PDDG]Package Sensing Recommendations

1.Trace Length Match: <25mil

2.Space: >25mil

3.Trace impedance:50ohm

4.Sense traces should be referenced to a solid ground plane

5.Avoid crossing over plane splits

?

[SKL PDG]SVID

1.Alert signal must be routed between Clk and Data signals to minimize Cross-Talk.

VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71 VCCGT_T62 VCCGT_U65 VCCGT_U68

VCCGT_U71 VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71

VCCGT_Y62

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE

VSSGTX_SENSE

?

@

13 OF 20

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCC_GT

Primary side cap

10U_0603_6.3V6-M

CC205

CC209

12

10U_0603_6.3V6-M

CC210

CC340

1

12

2

20141126

+1.35V

10U_0603_6.3V6-M

CC207

CC206

12

1U_0201_6.3V6-M

CC341

CC342

1

2

+1.35V

+VCC_ST

+VCC_STG

+1.35V

?

+VCC_ST

10U_0603_6.3V6-M

CC208

12

1U_0201_6.3V6-M

CC343

1

2

[SKL PDG]VDDQ

[SKL PDG]10uF x6, 1uF x4

SKL_U LT

UC1N

CPU POWER 3 OF 4

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

AM40

VDDQC

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

K20

VCCPLL_K20

K21

VCCPLL_K21

SKYLAKE-U_BGA1356

REV = 1

2

Rpu1

12

RC20 56_0402_1%

Rs1

1 2

RC19 220_0402_1%

?

@

VCCIO_AK28 VCCIO_AK30 VCCIO_AL30

VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42

VCCSA_AK23 VCCSA_AK25

VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28

VCCSA_J22 VCCSA_J23

VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

VCCIO_SENSE

AM23

VSSIO_SENSE

AM22

H21 H20

14 OF 20

+VCC_IO

RC126 0_0402_5%@ RC185 0_0402_5%@

[SKL PDG]VCCIO

[SKL PDG]10uF x2, 1uF x8

10U_0603_6.3V6-M

CC212

CC211

12

+VCC_SA

[SKL PDG]VCCSA

[SKL PDG]10uF x13, 1uF x7

10U_0603_6.3V6-M

CC213

12

@

10U_0603_6.3V6-M

CC223

12

1 2

RC192 100_0402_1%

1 2

RC189 100_0402_1%

1 2 1 2

10U_0603_6.3V6-M

12

CC214

12

@

CC224

12

?

100_0402_1%

CC336

1

2

10U_0603_6.3V6-M

CC215

@

10U_0603_6.3V6-M

CC225

RC370

RC369

2015030 9

1U_0201_6.3V6-M

CC337

1

2

10U_0603_6.3V6-M

CC216

12

@

10U_0603_6.3V6-M

CC329

12

VSSSA_SENSE VCCSA_SENSE

+VCC_SA

12

1

+VCC_ST+VCC_ST

Rpu2

12

RC355 100_0402_1%

Here were 4 Cap of 1U_0402, directly delete it.

1U_0201_6.3V6-M

CC338

1U_0201_6.3V6-M

CC339

1

2

Primary side cap

10U_0603_6.3V6-M

CC217

12

@

1U_0201_6.3V6-M

CC330

1

2

+VCC_IO

20141224

VCCSA_SENSE

VSSSA_SENSE

10U_0603_6.3V6-M

CC218

CC219

12

@

1U_0201_6.3V6-M

CC331

CC332

1

2

10U_0603_6.3V6-M

CC221

CC220

12

1U_0201_6.3V6-M

CC333

CC334

1

2

VSSSA_SENSE [74]

VCCSA_SENSE [74]

10U_0603_6.3V6-M

CC222

12

1U_0201_6.3V6-M

CC335

1

2

Title

Security Cl assification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(12/16):POWER

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

16 83

1

16 83

1.0

5

SRAM Primary Well 1.0 V. Dedicated SRAM rail and can have on board power down gate control.

2015/03/1 2 2015/03/1 2

[SKL PDG]VccSRAM

[SKL PDG]1uF x1 [SKL PDG]Close AF20,

D D

C C

Placement type:Edge<10mm(394mil)

+VCC_MPHYG T

+1VALW _PCH

+VCC_AMP HYPLL

LC1 close to K15

0 ohm

LC1 0_080 5_5%@

0 ohm

LC2 0_080 5_5%@

LC2 close to V15

@

1U_0201_6.3V6

CC46

1

2

1 2

20150526

+VCC_MPHYG T +VCC_MPHYGT

CC47 close to AF20

1U_0201_6.3V6

1

CC47

20150526 20150526

2015/03/1 2

20150520

+VCC_AMP HYPLL

20150520

+1VALW _PLL

[SKL PDG]VccAPLLEBB [SKL PDG]1uF x1

2

[SKL PDG]1uF x1 [SKL PDG]Close N18, Placement type:Edge<3mm(118mil)

Reserve for Sense Resistor

+1.8VALW +1.8VA LW_P CH

RC173 0_0603_ 5%

+3VALW +3VAL W_PCH

RC341 0_080 5_5%@

+1VALW +1VAL W_PCH

RC176 0_080 5_5%@

+1VALW +VCC_MPHYGT

CC58 close to N18

@

1 2

JC2

112

JUMP_43X 118

@

20141 205

2

20150 311

VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.)

1U_0201_6.3V6

2015/03/1 2

1

[SKL PDG]VccMPHYGT

CC52

[SKL PDG]Close N15, Placement type:Edge<3mm(118mil)

2

[SKL PDG]47uF x1 [SKL PDG]Close N15, Placement type:Edge<10mm(394mil)

Mod PHY Always On Primary 1.0 V: Always on primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic

[SKL PDG]VccMPHYAON

[SKL PDG]1uF x1 [SKL PDG]Close K17, Placement type:Edge<3mm(118mil)

Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM power, USB AFE Digital Logic, JTAG, Thermal Sensor and MIPI DPHY.

2015/03/1 2

[SKL PDG]VCCPRIM

[SKL PDG]1uF x1 [SKL PDG]Close AB19, Placement type:Edge<10mm(394mil)

4

CC50 & C194 close to N15

20150526

CC49 close to K17

CC95 close to AB19

+VCC_MPHYG T

20150520

1U_0201_6.3V6

C194

47UF_0805_6.3V

CC50

1

2

+1VALW _PCH

1U_0201_6.3V6

CC49

1

20150526

2

+1VALW _PCH

1U_0201_6.3V6

CC95

1

20150526

2

Core Logic Primary Well: This rail scales from 0.85 V to 1.0 V.

+1VALW _PCH

[SKL PDG]VccPRIM_Core

[SKL PDG]1uF x1 [SKL PDG]Close AF18, Placement type:Edge<10mm(394mil)

+1VALW _PCH

+1VALW _PLL

+VCC_HDA

RC304

2

20150520

CC535

+PCH_COR E

47UF_08 05_6.3V

1 2

0.1U_0402_10V6-K

1

RF_NS@

1

CC539

2

RF_NS@

1

CC540

2

20141 205

0_0805 _5%

20150520

+VCC_MPHYG T

+VCC_AMP HYPLL

+1VALW _PLL

+VCC_DS W3P3

+VCC_HDA

+3V_SPI

+3VALW _PRIM

Primary Well 3.3 V

+PCH_COR E

1U_0201_6.3V6

CC96

1

[SKL PDG]VCCPRIM

[SKL PDG]1uF x1 [SKL PDG]Close V19, Placement type:Edge<3mm(118mil)

2

20150526 20150526

2

CC536 47UF_08 05_6.3V

1

+DCPDSW

+3VALW _PCH

RC326 0_ 0402_5 %@

1 2

3

UC1O

AB19

VCCPRIM_1P0_AB19

AB20

VCCPRIM_1P0_AB20

P18

VCCPRIM_1P0_P18

AF18

VCCPRIM_CORE_AF18

AF19

VCCPRIM_CORE_AF19

V20

VCCPRIM_CORE_V20

V21

VCCPRIM_CORE_V21

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0_K17

L1

VCCMPHYAON_1P0_L1

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0_K15

L15

VCCAMPHYPLL_1P0_L15

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0_AF20

AF21

VCCSRAM_1P0_AF21

T19

VCCSRAM_1P0_T19

T20

VCCSRAM_1P0_T20

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKYLAKE -U_BGA13 56

REV = 1

+3VALW _PRIM

1U_0201_6.3V6

1

2

CC97

SKL_ULT

CPU POWER 4 OF 4

@

?

1100mA

600mA

22mA

1500mA

88mA

26mA

118mA

68mA

565mA

75mA 33mA 33mA

HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Definition Audio.

+3VALW _PCH

[SKL PDG]VccHDA

[SKL PDG]1uF x1 [SKL PDG]Close AJ19, Placement type:Edge<10mm(394mil)

AK15

VCCPGPPA

AG15

VCCPGPPB

Y16

VCCPGPPC

Y15

VCCPGPPD

T16

VCCPGPPE

AF16

VCCPGPPF

AD15

VCCPGPPG

V19

VCCPRIM_3P3_V19

T1

VCCPRIM_1P0_T1

AA1

VCCATS_1P8

AK17

VCCRTCPRIM_3P3

AK19

VCCRTC_AK19

BB14

VCCRTC_BB14

BB10

DCPRTC

A14

VCCCLK1

K19

VCCCLK2

L21

VCCCLK3

N20

VCCCLK4

L19

VCCCLK5

A10

VCCCLK6

AN11

GPP_B0/CORE_VID0

AN13

GPP_B1/CORE_VID1

[SKL PDG]The CORE_VID[0:1] signal is used by external VRs to indicate the final settling voltage for VCCPRIM_CORE rail.

?15 OF 20

1 2

RC330 0_040 2_5%@

20150526

85mA

+DCPRTC

+1VALW _CLK2

+1VALW _CLK4

+1VALW _CLK5

20150526

+VCC_HDA

1U_0201_6.3V6

CC99

1

2

1U_0201_6.3V6

1

20150526

2

Near AG15 Near Y16 Near T16

161mA

+1.8VALW _PCH

+3VALW _PRIM

+1.8VALW _PCH

+3VALW _RTCP RIM

+RTCVCC

0 ohm

1 2

LC3 0_0805 _5%@

0 ohm

1 2

LC4 0_0805 _5%@

0 ohm

1 2

LC5 0_0805 _5%@

1

T56

20141 208

Thermal Sensor Primary Well 1.8 V

[SKL PDG]VccATS

[SKL PDG]1uF x1 [SKL PDG]Close AA1, Placement type:Edge<10mm(394mil)

20150526 20150526

1U_0201_6.3V6

CC530

1

2

20150520

2

+3VALW _PCH

1U_0201_6.3V6

CC531

CC532

1

2

135mA

+1VALW _PCH

RTC de-coupling capacitor only. This rail should NOT be driven.

+DCPDSW

[SKL PDG]DcpRTC

CC60

1

[SKL PDG]0.1uF x1 [SKL PDG]Close BB10, Placement type:Edge<3mm(118mil)

2

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

2015052620 15052620150526

0.1U_0201_6.3V6K

1U_0201_6.3V6

C200

C201

CC58

1

2

[SKL PDG]VccRTC

[SKL PDG]Close AK19, Placement type:Edge<3mm(118mil)

20150526

Deep Sx Well 1.0 V: This rail is generated by on die DSW low dropout (LDO) linear voltage regulator to supply DSW

+1.8VALW _PCH

GPIOs, DSW core logic and DSW USB2 logic. Board needs to connect 1 uF capacitor to this rail and power should NOT be driven from the board. When primary well power is up, this rail is bypassed from VCCPRIM_1p0.

1U_0201_6.3V6

CC61

1

[SKL PDG]DcpDSW

2

[SKL PDG]1uF x1 [SKL PDG]Close AL1, Placement type:Edge<3mm(118mil)

RTC Logic Primary Well 3.3 V. This power supplies the RTC internal VRM. It will be off during Deep Sx mode.

+3VALW _PCH

[SKL PDG]VccRTCPRIM [SKL PDG]1uF x1

[SKL PDG]1uF x1,0.1uF x2 [SKL PDG]Close AK17, Placement type:Edge<3mm(118mil)

Deep Sx Well for GPD GPIOs and USB2

+3VALW _PCH

[SKL PDG]VccDSW

20150526

1 2

RC333 0_ 0402_5 %@

1 2

RC127 0_0402 _5%@

+3VL +VC C_DSW 3P3

1 2

RC132 0_0402 _5%@

1U_0201_6.3V6

+3VALW _RTCP RIM

20150526

1

C197

0.1U_020 1_6.3V6 K

2

20150526

+DCPRTC

+RTCVCC

1U_0201_6.3V6

CC59

1

2

B B

A A

5

4

3

20141 205

Security C lassification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2014/05/07

LC Future Center Secret Data

Deciphered Date

2015/05/07

Title

SKL(13/16):POWER

Size

Document Number Rev

D

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

Date: Sheet of

1

17 83

LCFC Confidential

1.0

5

D D

4

3

2

1

@

AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58

?

16 OF 20

SKL_U LT

UC1Q

GND 2 OF 3

AT63

VSS_AT63

AT68

VSS_AT68

AT71

VSS_AT71

AU10

VSS_AU10

AU15

VSS_AU15

AU20

VSS_AU20

AU32

VSS_AU32

AU38

VSS_AU38

AV1

VSS_AV1

AV68

VSS_AV68

AV69

VSS_AV69

AV70

VSS_AV70

AV71

VSS_AV71

AW10

VSS_AW10

AW12

VSS_AW12

AW14

VSS_AW14

AW16

VSS_AW16

AW18

VSS_AW18

AW21

VSS_AW21

AW23

VSS_AW23

AW26

VSS_AW26

AW28

VSS_AW28

AW30

VSS_AW30

AW32

VSS_AW32

AW34

VSS_AW34

AW36

VSS_AW36

AW38

VSS_AW38

AW41

VSS_AW41

AW43

VSS_AW43

AW45

SKYLAKE-U_BGA1356

VSS_AW45

AW47

?

AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

BA45

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

F68

REV = 1

VSS_AW47 VSS_AW49 VSS_AW51 VSS_AW53 VSS_AW55 VSS_AW57 VSS_AW6 VSS_AW60 VSS_AW62 VSS_AW64 VSS_AW66 VSS_AW8 VSS_AY66 VSS_B10 VSS_B14 VSS_B18 VSS_B22 VSS_B30 VSS_B34 VSS_B39 VSS_B44 VSS_B48 VSS_B53 VSS_B58 VSS_B62 VSS_B66 VSS_B71 VSS_BA1 VSS_BA10 VSS_BA14 VSS_BA18 VSS_BA2 VSS_BA23 VSS_BA28 VSS_BA32 VSS_BA36 VSS_F68 VSS_BA45

SKL_U LT

UC1P

GND 1 OF 3

A5

VSS_A5

A67

VSS_A67

A70

VSS_A70

AA2

VSS_AA2

AA4

VSS_AA4

AA65

VSS_AA65

AA68

VSS_AA68

AB15

VSS_AB15

AB16

VSS_AB16

AB18

VSS_AB18

AB21

VSS_AB21

AB8

VSS_AB8

AD13

VSS_AD13

AD16

VSS_AD16

AD19

VSS_AD19

AD20

VSS_AD20

AD21

VSS_AD21

AD62

C C

B B

VSS_AD62

AD8

VSS_AD8

AE64

VSS_AE64

AE65

VSS_AE65

AE66

VSS_AE66

AE67

VSS_AE67

AE68

VSS_AE68

AE69

VSS_AE69

AF1

VSS_AF1

AF10

VSS_AF10

AF15

VSS_AF15

AF17

VSS_AF17

AF2

SKYLAKE-U_BGA1356

VSS_AF2

AF4

REV = 1

VSS_AF4

AF63

VSS_AF63

AG16

VSS_AG16

AG17

VSS_AG17

AG18

VSS_AG18

AG19

VSS_AG19

AG20

VSS_AG20

AG21

VSS_AG21

AG71

VSS_AG71

AH13

VSS_AH13

AH6

VSS_AH6

AH63

VSS_AH63

AH64

VSS_AH64

AH67

VSS_AH67

AJ15

VSS_AJ15

AJ18

VSS_AJ18

AJ20

VSS_AJ20

AJ4

VSS_AJ4

AK11

VSS_AK11

AK16

VSS_AK16

AK18

VSS_AK18

AK21

VSS_AK21

AK22

VSS_AK22

AK27

VSS_AK27

AK63

VSS_AK63

AK68

VSS_AK68

AK69

VSS_AK69

AK8

VSS_AK8

AL2

VSS_AL2

AL28

VSS_AL28

AL32

VSS_AL32

AL35

VSS_AL35

AL38

VSS_AL38

AL4

VSS_AL4

AL45

VSS_AL45

AL48

VSS_AL48

AL52

VSS_AL52

AL55

VSS_AL55

AL58

VSS_AL58

AL64

VSS_AL64

VSS_AL65

VSS_AL66 VSS_AM13 VSS_AM21 VSS_AM25 VSS_AM27 VSS_AM43 VSS_AM45 VSS_AM46 VSS_AM55 VSS_AM60 VSS_AM61 VSS_AM68 VSS_AM71

VSS_AM8 VSS_AN20 VSS_AN23 VSS_AN28 VSS_AN30 VSS_AN32 VSS_AN33 VSS_AN35 VSS_AN37 VSS_AN38 VSS_AN40 VSS_AN42 VSS_AN58 VSS_AN63

VSS_AP10 VSS_AP18 VSS_AP20 VSS_AP23 VSS_AP28 VSS_AP32 VSS_AP35 VSS_AP38 VSS_AP42 VSS_AP58 VSS_AP63 VSS_AP68

VSS_AP70 VSS_AR11 VSS_AR15 VSS_AR16 VSS_AR20 VSS_AR23 VSS_AR28 VSS_AR35 VSS_AR42 VSS_AR43 VSS_AR45 VSS_AR46 VSS_AR48

VSS_AR5 VSS_AR50 VSS_AR52 VSS_AR53 VSS_AR55 VSS_AR58 VSS_AR63

VSS_AR8

VSS_AT2

VSS_AT20 VSS_AT23 VSS_AT28 VSS_AT35

VSS_AT4

VSS_AT42 VSS_AT56 VSS_AT58

VSS_BA49 VSS_BA53 VSS_BA57

VSS_BA6 VSS_BA62 VSS_BA66 VSS_BA71 VSS_BB18 VSS_BB26 VSS_BB30 VSS_BB34 VSS_BB38 VSS_BB43 VSS_BB55

VSS_BB6 VSS_BB60 VSS_BB64 VSS_BB67 VSS_BB70

VSS_C1

VSS_C25

VSS_C5 VSS_D10 VSS_D11 VSS_D14 VSS_D18 VSS_D22 VSS_D25 VSS_D26 VSS_D30 VSS_D34 VSS_D39 VSS_D44 VSS_D45 VSS_D47 VSS_D48 VSS_D53 VSS_D58

VSS_D6 VSS_D62 VSS_D66 VSS_D69 VSS_E11 VSS_E15 VSS_E18 VSS_E21 VSS_E46 VSS_E50 VSS_E53 VSS_E56

VSS_E6 VSS_E65 VSS_E71

VSS_F1 VSS_F13

VSS_F2 VSS_F22 VSS_F23 VSS_F27 VSS_F28 VSS_F32 VSS_F33 VSS_F35 VSS_F37 VSS_F38

VSS_F4 VSS_F40 VSS_F42

VSS_BA41

@

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

?

17 OF 20

?

SKL_U LT

UC1R

GND 3 OF 3

F8

VSS_F8

G10

VSS_G10

G22

VSS_G22

G43

VSS_G43

G45

VSS_G45

G48

VSS_G48

G5

VSS_G5

G52

VSS_G52

G55

VSS_G55

G58

VSS_G58

G6

VSS_G6

G60

VSS_G60

G63

VSS_G63

G66

VSS_G66

H15

VSS_H15

H18

VSS_H18

H71

VSS_H71

J11

VSS_J11

J13

VSS_J13

J25

VSS_J25

J28

VSS_J28

J32

VSS_J32

J35

VSS_J35

J38

VSS_J38

J42

VSS_J42

J8

VSS_J8

K16

VSS_K16

K18

VSS_K18

K22

VSS_K22

K61

VSS_K61

K63

SKYLAKE-U_BGA1356

VSS_K63

K64

REV = 1

VSS_K64

K65

VSS_K65

K66

VSS_K66

K67

VSS_K67

K68

VSS_K68

K70

VSS_K70

K71

VSS_K71

L11

VSS_L11

L16

VSS_L16

L17

VSS_L17

VSS_L18

VSS_L2

VSS_L20

VSS_L4

VSS_L8 VSS_N10 VSS_N13 VSS_N19 VSS_N21

VSS_N6 VSS_N65 VSS_N68 VSS_P17 VSS_P19 VSS_P20 VSS_P21 VSS_R13

VSS_R6 VSS_T15 VSS_T17 VSS_T18

VSS_T2 VSS_T21

VSS_T4 VSS_U10 VSS_U63 VSS_U64 VSS_U66 VSS_U67 VSS_U69 VSS_U70 VSS_V16 VSS_V17 VSS_V18

VSS_W13

VSS_W6

VSS_W9 VSS_Y17 VSS_Y19 VSS_Y20 VSS_Y21

?

@

L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69

18 OF 20

U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21

?

A A

Title

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

LCFC Confidential

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(14/16):GND

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

18 83

1

18 83

1.0

5

D D

4

3

2

1

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_COMP

EMMC_RCOMP

@

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

?

RC361

1 2

200_0402_1%

@

20141106

UC1I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

C C

B B

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKYLAKE-U_BGA1356

REV = 1

SKL_U LT

?

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

9 OF 20

A A

Title

Security Cl assification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(15/16):CSI-2/EMMC

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

19 83

1

19 83

1.0

5

4

3

2

1

[SKL EDS]

CFG0

12

100K_0402_1%

@

12

[SKL EDS]Zero Voltage Mode:VCCOPC is fixed OPC VR output voltage of 1V, the processor can drive VR to LPM (Low Power Mode) which sets VR output to 0V using ZVM# signal as shown below:

ZVM# state

0V

1V

+VCC_ST

[SKL EDS]Minimum Speed Mode: VCCEOPIO can be connected to OPC VR in this case VCCEOPIO is fixed to 1V. The processor can drive VR to LPM (Low Power Mode) which sets VR output to 0V using ZVM# signal . In order to achieve better power/performance it is recommended to use a separate VR for VCCEOPIO in this case VCCEOPIO is configurable to 0.8V/1V. The processor drives the VR to set VCCEOPIO value(0.8V/1V) using MSM# signal, based on the required bandwidth for the EOPIO interface as shown below:

RC105 1K_0402_5%@

RC201 1K_0402_1%@

D D

2015030 9 (Test point change to 12mil)

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1

CFG_RCOMP

ITP_PMODE

1 1

1

1 1

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG17

CFG18 CFG19

TP36 TP38 TP40 TP41 TP42 TP44 TP46 TP47 TP48 TP50 TP52 TP53 TP55 TP56 TP57 TP58

TP61

C C

[SKL CRB]

RC152 49.9_0402_1%

[SKL PDG]Route HOOK[6] to Skylake ITP_PMODE. Termination: Resistor value from 1K ohm to 3K ohm pull up to PCH_V1.0A Rail.

B B

+1VALW_PCH

RC354 1.5K_0402_5%

12

TP63

TP62 TP65

TP24 TP26

TP74 TP30

TP86 TP85

TP88 TP87

TP90 TP89

TP32

TP91

TP92 TP93

TP94 TP95

TP96 TP97

UC1S

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

SKYLAKE-U_BGA1356

D1

REV = 1

RSVD_D1

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

BA70

RSVD_TP_BA70

BA68

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

SKL_U LT

RESERVED SIGNALS-1

?

19 OF 20

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

TP5 TP6

RSVD_D5 RSVD_D4

RSVD_B2

RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4

RSVD_C4

TP4

RSVD_A69 RSVD_B69

RSVD_AY3

RSVD_D71 RSVD_C70

RSVD_C54 RSVD_D54

TP1 TP2

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

@

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1

E1 E2

BA4 BB4

A4 C4

BB5

A69 B69

AY3

D71 C70

C54 D54

AY4 BB3

AY71 AR56

AW71 AW70

AP56 C64

?

RC296 0_0402_5%@

RC295 0_0402_5%@

L:Stall. *H:(Default) Normal Operation; No stall.

1

TP37

1

TP39

1

TP43

1

TP45

1

TP49

1

TP51

1

TP59

1

TP60

1

TP22

1

TP23

1

TP25

1

TP27

1

TP64

1

TP66

1

TP29

1

TP31

1

TP33

1

TP34

1

TP35

1

TP67

1

TP68

1

TP54

1

TP927

1

1 2

TP928

1

TP929

1

TP930

1

TP931

1

TP932

1

TP933

1

TP934

1

TP935

1

TP936

1

TP937

1

TP938

20141202

RC358

[SKL CRB]

@

RSVD_F6

RSVD_E3

RSVD_C11

RSVD_B11

RSVD_A11 RSVD_D12 RSVD_C12

RSVD_F52

20 OF 20REV = 1

?

F6 E3 C11 B11 A11 D12 C12 F52

1

TP106

1

TP107

1

TP108

1

TP109

1

TP110

1

TP111

1

TP112

1

TP113

SKL_U LT

UC1T

1

TP98

1

TP99

1

TP100

1

TP101

1

TP102

1

TP103

1

TP104

1

TP105

A A

AW69 AW68

AU56

AW48

C7 U12 U11 H11

SPARE

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SKYLAKE-U_BGA1356

CFG4

CFG4CFG0

*L: Embedded DisplayPort Enabled H: Embedded DisplayPort Disabled

RC104 1K_0402_5%@

RC144 1K_0402_1%

TABLE

CFG0 : Stall Reset Sequence after PCU PLL Lock until de-asserted

1 : No Stall 0 : Stall

CFG4 : eDP Enable

1 : Disabled 0 : Enabled

CFG9 : SVID Bus Communication 1 : Enabled 0 : Disabled

VCCOPC

0V

1V

ZVM# state

0V

1V

12

MSM# state

X

0V

1V 1V

+VCC_IO+VCC_IO

VCCEOPI O

0V

0.8V

Title

Security Cl assification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

3

2014/05/07

LC Future Center Secret Data

Deciphered Date

2

2015/05/07

Title

SKL(16/16):CFG/RESERVED

Size Document Number Re v

Custom

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

Wednesday, August 05, 2015

20 83

1

20 83

1.0

5

4

3

2

1

Security ROM

USROM1

1

HOLD#

SPI_CLK SPI_SI SPI_IO2

2 3 4

+3V_SPI

8

VCC

SPI_IO3_8MB

7

SPI_CLK_8MB

6

CLK

SPI_SI_8MB

5

DI

PLTRST_NEAR#[12]

D D

SPI_IO3

+3V_SPI

SPI_CS0#_8MB[11] SPI_CS1#_4MB[11]

C C

@

1 2

RC380 1K_0402_5%

[SKL]SPI0_CS0#: SPI FLASH SPI0_CS1#: SPI FLASH SPI0_CS2#: SPI TPM

1 2

RC117 1K_0402_5%

1 2

RC118 1K_0402_5%

SPI_CS0#_8MB

SPI_SO_8MB

SPI_IO2_8MB

SPI_IO3_8MB SPI_IO3 SPI_CLK_8MB SPI_SI_8MB SPI_IO2_8MB

Near SPI ROM

SPI_SO_8MB SPI_SO SPI_SO_4MB SPI_SO

PLTRST_NEAR#

2015/03/08

SPI_IO2 SPI_IO3

UC8M1

1

CS#

2

DO

3

WP#

4

GND

W25Q64FVSSIQ_SO8

RPC23

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SD30000370T

1 2

RC103 33_0402_5%

@

NC_1 NC_2 PROT# GND

PCA24S08AD_SO8

SA00004MK00/SA00004ML00

8

VCC

7

WP

6

SCL

5

SDA

+3V_SPI

SPI_IO3 [11]

SPI_CLK [11,60]

SPI_SI [11,60]

SPI_IO2 [11]

SPI_SO [ 11,60]

PM_SMB_CLK PM_SMB_DAT

20150304

1

CC25

0.1U_0402_10V7-K

2

PM_SMB_CLK [11,22,23,53] PM_SMB_DAT [11,22,23,53]

SPI_CS1#_4MB SPI_SO_4MB SPI_IO2_4MB

Near SPI ROM

+3VS

1

CC22

@

0.1U_0402_10V6-K

2

4MB(32Mb) for VPRO SKU8MB(64Mb)

UC4M1

1

CS#

VCC

2

DO

HOLD#

3

WP#

CLK

4

GND

@

RPC24

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SD30000370T

@

1 2

@

DI

SPI_CLK SPI_SI SPI_IO2

W25Q32FVSSIQ_SO8

SPI_IO3_4MB SPI_IO3 SPI_CLK_4MB SPI_SI_4MB SPI_IO2_4MB

RC102 33_0402_5%

8 7 6 5

+3V_SPI SPI_IO3_4MB SPI_CLK_4MB SPI_SI_4MB

M3 Support + Intel LAN PHY / Wireless LAN Solut i on

+3V_SPI

+3VS

+3VALW

1 2

RC110 0_0402_5%@

1 2

RC310 0_0402_5%@

+3V_SPI

1

CC26

@

0.1U_0402_10V7-K

2

20150304

+3V_SPI

0.085 A

Mirror Code

1 2

FSCE#[66] SPI_FMOSI#[66] SPI_FMISO[66] SPI_FSCK[66]

RC311 0_0402_5%@

1 2

RC312 0_0402_5%@

1 2

RC313 0_0402_5%@

1 2

RC314 0_0402_5%@

SPI_CS0#_8MB SPI_SI_8MB SPI_SO_8MB SPI_CLK_8MB

Close to SPI ROM (UC8M1).

B B

A A

Title

Security Classification

Issued Date

LCFC Confidential

5

4

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CE NTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF L C FUTURE CENTER.

3

2013/09/07

LC Future Center Secret Data

Deciphered Date

2

2014/09/07

Title

XXXX

Size

Document Number Re v

C

Wednesday, August 05, 2015

Date: Sheet o f

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

1

21 83

1.0

5

SA_DIMM_VREFDQ[7]

1 2

D D

C C

B B

A A

1

CD2

DIMM1@

0.022U_0402_25V7-K

2

12

RD4

DIMM1@

24.9_0402_1%

+1.35V

12

RD1

DIMM1@

1.8K_0402_1%

12

1.8K_0402_1%

RD3

0.1U_0402_10V7-K

DIMM1@

1

CD3

2

DIMM1@

RD2

2_0402_1%

Close to JDIMM1

DDRA_CKE0_DIMMA[7]

DDR_A_BS2[7]

SA_CLK_DDR0[7] SA_CLK_DDR#0[7]

DDR_A_BS0[7]

DDR_A_WE#[7] DDR_A_CAS#[7]

DDRA_CS1_DIMMA#[7]

+3VS

+0.675VS +0.675VS

2.2U_0402_6.3V6-K

0.1U_0402_10V6-K

@

DIMM1@

1

CD29

2

2.2U_0402_6.3V6-K

1

CD1

@

2

DDRA_CKE0_DIMMA

DDR_A_BS2

DDRA_CS1_DIMMA#

CD30

1

@

0_0402_5%

2

1 2

+V_DDR_REFA

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

SA_CLK_DDR0 SA_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

RC316

@

0_0402_5%

1 2

LCFC Confidential

5

4

+1.35V +1.35V

RC315

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA SCL

VTT2

DQ4 DQ5

DQ6 DQ7

A15 A14

A11

CK1

BA1

S0#

NC2

ME@

A7

A6 A4

A2 A0

G2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

Channel A

4

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDRA_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

SA_CLK_DDR1 SA_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDRA_CS0_DIMMA#

DDRA_ODT0_DIMMA#

DDRA_ODT1_DIMMA#

+VREF_CA

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

+1.35V

12

RD21

470_0402_5%

1

CD59

0.1U_0402_10V7-KEMC_NS@

2

DDRA_CKE1_DIMMA [7]

SA_CLK_DDR1 [7] SA_CLK_DDR#1 [7]

DDR_A_BS1 [7] DDR_A_RAS# [7]

DDRA_CS0_DIMMA# [7] DDRA_ODT0_DIMMA# [7]

DDRA_ODT1_DIMMA# [7]

20141202

0.1U_0402_10V7-K

2.2U_0402_6.3V6-K

DIMM1@

1

CD17

@

2

3

1

CD18

2

DDR_A_DQS#[0..7] [7]

DDR_A_DQS[0..7] [7]

DDR_A_D[0..31] [7]

DDR_A_MA[0..15] [7]

DDR_A_D[32..63] [7]

DDR3_DRAMRST# [8,23]

+1.35V

12

RD9

1.8K_0402_1%

RD10

1 2

12

2_0402_1%

RD11

1.8K_0402_1%

+VREF_CA [23]

All VREF traces should have 10 mil trace width

1

CD12

0.022U_0402_25V7-K

2

12

RD12

24.9_0402_1%

2

SM_DIMM_VREFCA [7]

close to JDDR3L.126

DDR_PG_CTRL[7]

PM_SMB_DAT [11,21,23,53] PM_SMB_CLK [11,21,23,53]

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

LC Future Center Secret Data

Deciphered Date

DDR_PG_CTRL

12

@

2

Layout Note: Place near JDIMM1

DIMM1@

CD13

10U_0603_6.3V6-M

1

2

DIMM1@

CD8

1U_0402_6.3VA-K

@

1

2

1U_0402_6.3VA-K

+1.35V

2

RD24 10K_0402_5%

2014/09/07

DIMM1@

CD14

1

2

CD9

1

2

DIMM1@

CD23

1

2

+3V_DDR

12

1

3

DIMM1@

CD15

10U_0603_6.3V6-M

1

2

DIMM1@

CD10

1U_0402_6.3VA-K

@

1

2

Layout Note: Place near JDIMM1.203,204

DIMM1@

CD24

1U_0402_6.3VA-K

1

2

RD23 100K_0402_5%

SM_PG_CTRL

QD1 DTC115TMT2L_VMT3

Title

Size Document Number Re v

Custom

Date: Sheet of

DIMM1@

CD19

CD16

10U_0603_6.3V6-M

1

2

For RF solution.

CD11

CRF1

2200P_0402_50V7-K

RF_NS@

1

2

CD26

CD25

1U_0402_6.3VA-K

@

1

2

20141230

XXXX

Wednesday, August 05, 2015

1

DIMM1@

CD20

CD21

10U_0603_6.3V6-M

1

2

CRF2

47P_0402_50V8-J

RF_NS@

1

2

+0.675VS

SM_PG_CTRL [73]

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

1

+1.35V

CD22

330U_D2_2V_Y

1

+

2

22 83

1.0

5

+1.35V

12

RD15

DIMM2@

RD17

SB_DIMM_VREFDQ[7]

D D

DIMM2@

1 2

1

2_0402_1%

CD310.022U_0402_25V7-K

DIMM2@

2

12

RD1824.9_0402_1%

1.8K_0402_1%

12

RD16

DIMM2@

1.8K_0402_1%

2.2U_0402_6.3V6-K

CD32

0.1U_0402_10V7-K

1

CD33

DIMM2@

@

2

Close to JDIMM2

DDRB_CKE0_DIMMB[8]

+3VS

+0.675VS

DDR_B_BS2[8]

SB_CLK_DDR0[8] SB_CLK_DDR#0[8]

DDR_B_BS0[8]

DDR_B_WE#[8] DDR_B_CAS#[8]

DDRB_CS1_DIMMB#[8]

+3VS

12

RD19

DIMM2@

10K_0402_5%

2.2U_0402_6.3V6-K

CD58

0.1U_0402_10V6-K

@

1

DIMM2@

CD57

2

C C

B B

A A

LCFC Confidential

5

4

+1.35V +1.35V

+V_DDR_REFB

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D24 DDR_B_D25

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D26 DDR_B_D27

DDR_B_D16 DDR_B_D17

DDR_B_D18 DDR_B_D19

DDRB_CKE0_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

SB_CLK_DDR0 SB_CLK_DDR#0

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13

DDRB_CS1_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

RC317 0_0402_5%

@

1 2

JDIMM2

1

VREF_DQ

3

VSS_1

5

DQ0

7

DQ1

9

VSS_3

11

DM0

13

VSS_5

15

DQ2

17

DQ3

19

VSS_7

21

DQ8

23

DQ9

25

VSS_9

27

DQS1#

29

DQS1

31

VSS_11

33

DQ10

35

DQ11

37

VSS_13

39

DQ16

41

DQ17

43

VSS_15

45

DQS2#

47

DQS2

49

VSS_17

51

DQ18

53

DQ19

55

VSS_19

57

DQ24

59

DQ25

61

VSS_21

63

DM3

65

VSS_23

67

DQ26

69

DQ27

71

VSS_25

73

CKE0

75

VDD_1

77

NC_1

79

BA2

81

VDD_3

83

A12/BC#

85

A9

87

VDD_5

89

A8

91

A5

93

VDD_7

95

A3

97

A1

99

VDD_9

101

CK0

103

CK0#

105

VDD_11

107

A10/AP

109

BA0

111

VDD_13

113

WE#

115

CAS#

117

VDD_15

119

A13

121

S1#

123

VDD_17

125

TEST

127

VSS_27

129

DQ32

131

DQ33

133

VSS_29

135

DQS4#

137

DQS4

139

VSS_31

141

DQ34

143

DQ35

145

VSS_33

147

DQ40

149

DQ41

151

VSS_36

153

DM5

155

VSS_37

157

DQ42

159

DQ43

161

VSS_39

163

DQ48

165

DQ49

167

VSS_41

169

DQS6#

171

DQS6

173

VSS_43

175

DQ50

177

DQ51

179

VSS_45

181

DQ56

183

DQ57

185

VSS_47

187

DM7

189

VSS_49

191

DQ58

193

DQ59

195

VSS_51

197

SA0

199

VDDSPD

201

SA1

203

VTT_1

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

Channel B

<Address: SA1:SA0=10>

DIMM_2 STD H:4mm

4

VSS_2

DQ4 DQ5

VSS_4

DQS0#

DQS0

VSS_6

DQ6 DQ7

VSS_8

DQ12 DQ13

VSS_10

DM1

RESET#

VSS_12

DQ14 DQ15

VSS_14

DQ20 DQ21

VSS_16

DM2

VSS_18

DQ22 DQ23

VSS_20

DQ28 DQ29

VSS_22

DQS3#

DQS3

VSS_24

DQ30 DQ31

VSS_26

CKE1

VDD_2

VDD_4

VDD_6

VDD_8

VDD_10

CK1#

VDD_12

RAS#

VDD_14

ODT0

VDD_16

ODT1

NC_2

VDD_18

VREF_CA

VSS_28

DQ36 DQ37

VSS_30

DM4

VSS_32

DQ38 DQ39

VSS_34

DQ44 DQ45

VSS_35

DQS5#

DQS5

VSS_38

DQ46 DQ47

VSS_40

DQ52 DQ53

VSS_42

DM6

VSS_44

DQ54 DQ55

VSS_46

DQ60 DQ61

VSS_48

DQS7#

DQS7

VSS_50

DQ62 DQ63

VSS_52

EVENT#

SDA

VTT_2

GND2

BOSS2

CK1

BA1

SCL

ME@

A15 A14

A11

A7

A6 A4

A2 A0

S0#

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

3

2013/09/07

DDR_B_DQS#[0..3] [8]

DDR_B_DQS[0..3] [8]

DDR_B_D[0..31] [8]

DDR_B_MA[0..15] [8]

DDR_B_D[32..63] [8]

DDR_B_DQS#[4..7] [8]

DDR_B_DQS[4..7] [8]

20141202

+VREF_CA [22]

All VREF traces should have 10 mil trace width

LC Future Center Secret Data

Deciphered Date

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D28 DDR_B_D29

DDR_B_D30 DDR_B_D31

DDR_B_D20 DDR_B_D21

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D22 DDR_B_D23

DDRB_CKE1_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

SB_CLK_DDR1 SB_CLK_DDR#1

DDR_B_BS1 DDR_B_RAS#

DDRB_CS0_DIMMB# DDRB_ODT0_DIMMB#

DDRB_ODT1_DIMMB#

+VREF_CA

DDR_B_D36 DDR_B_D37

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

+0.675VS

Security Cl assification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENTER.

1

2

PM_SMB_DAT [11,21,22,53] PM_SMB_CLK [11,21,22,53]

Issued Date

3

DDR3_DRAMRST# [8,22]

EMC_NS@

CD60

0.1U_0402_10V7-K

DDRB_CKE1_DIMMB [8]

SB_CLK_DDR1 [8] SB_CLK_DDR#1 [8]

DDR_B_BS1 [8] DDR_B_RAS# [8]

DDRB_CS0_DIMMB# [8]

DDRB_ODT0_DIMMB# [8]

DDRB_ODT1_DIMMB# [8]

1

CD49

DIMM2@

0.1U_0402_10V7-K

2

DIMM2@

CD42

10U_0603_6.3V6-M

CD38

1U_0402_6.3VA-K

2014/09/07

1

Layout Note: Place near JDIMM2

+0.675VS

10U_0603_6.3V6-M

1

2

23 83

+1.35V

1.0

DIMM2@

CD43

10U_0603_6.3V6-M

1

2

DIMM2@

CD39

1U_0402_6.3VA-K

@

1

2

DIMM2@

CD51

1U_0402_6.3VA-K

1

2

DIMM2@

CD44

CD45

10U_0603_6.3V6-M

1

2

DIMM2@

CD40

CD41

1U_0402_6.3VA-K

@

1

2

Layout Note: Place near JDIMM2.203,204

DIMM2@

CD53

CD52

Size Document Number Re v

Date: Sheet of

1

2

Title

Custom

1U_0402_6.3VA-K

XXXX

1U_0402_6.3VA-K

1

2

Wednesday, August 05, 2015

DIMM2@

CD47

CD46

10U_0603_6.3V6-M

1

2

For RF solution.

CRF3

CRF4

2200P_0402_50V7-K

47P_0402_50V8-J

RF_NS@

1

2

DIMM2@

CD55

CD54

1

2

10U_0603_6.3V6-M

1U_0402_6.3VA-K

1

2

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

1

DIMM2@

CD48

10U_0603_6.3V6-M

1

2

DIMM2@

CD56

1

2

3

4

5

UV3G

AF30

PCIE_RX0P

AE31

PCIE_RX0N

AE29

PCIE_RX1P

AD28

PCIE_RX1N

AD30

PCIE_RX2P

AC31

PCIE_RX2N

AC29

PCIE_RX3P

AB28

PCIE_RX3N

AB30

PCIE_RX4P

AA31

PCIE_RX4N

AA29

PCIE_RX5P

Y28

PCIE_RX5N

Y30

PCIE_RX6P

W31

PCIE_RX6N

W29

PCIE_RX7P

V28

PCIE_RX7N

V30

NC_121

U31

NC_122

U29

NC_123

T28

NC_124

T30

NC_125

R31

NC_126

R29

NC_127

P28

NC_128

P30

NC_129

N31

NC_130

N29

NC_131

M28

NC_132

M30

NC_133

L31

NC_134

L29

NC_135

K30

NC_136

CLOCK

AK30

PCIE_REFCLKP

AK32

PCIE_REFCLKN

N10

TEST_PG

AL27

PERSTB

216-0858020-A0_FCBGA631

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1

IN1

2

IN2

MC74VHC1G08DFT2G_SC70-5

DIS@

PCIE_CTX_C_GRX_N[0..3]

PCIE_CTX_C_GRX_P[0..3]

PCIE_CRX_GTX_N[0..3]

PCIE_CRX_GTX_P[0..3]

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3

+3VS

5

UV4

VCC

4

OUT

GND

3

CLK_PCIE_VGA[10] CLK_PCIE_VGA#[10]

+3VS_VGA

12

RV43 10K_0402_5%

@

PLT_RST_VGA#

RV44 100K_0402_5%

CLK_PCIE_VGA CLK_PCIE_VGA#

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3

PLT_RST_VGA# [25,79]

1 2

RV40 1K_0402_5%DIS@

PLT_RST_VGA#

PCIE_CTX_C_GRX_N[0..3][15]

PCIE_CTX_C_GRX_P[0..3][15]

PCIE_CRX_GTX_N[0..3][15]

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PLTRST#[12]

PCIE_CRX_GTX_P[0..3][15]

CV132 0.1U_0402_10V7-KDIS@ CV133 0.1U_0402_10V7-KDIS@ CV134 0.1U_0402_10V7-KDIS@ CV135 0.1U_0402_10V7-KDIS@ CV136 0.1U_0402_10V7-KDIS@ CV137 0.1U_0402_10V7-KDIS@ CV138 0.1U_0402_10V7-KDIS@ CV139 0.1U_0402_10V7-KDIS@

PLTRST#

DGPU_HOLD_RST#

DIS@

A A

B B

DGPU_HOLD_RST#[6,14]

C C

PCI EXPRESS INTERFACE

@

PCIE_TX0P

PCIE_TX0N

PCIE_TX1P

PCIE_TX1N

PCIE_TX2P

PCIE_TX2N

PCIE_TX3P

PCIE_TX3N

PCIE_TX4P

PCIE_TX4N

PCIE_TX5P

PCIE_TX5N

PCIE_TX6P

PCIE_TX6N

PCIE_TX7P

PCIE_TX7N

CALIBRATIO N

PCIE_CALR_TX

PCIE_CALR_RX

NC_137 NC_138

NC_139 NC_140

NC_141 NC_142

NC_143 NC_144

NC_145 NC_146

NC_147 NC_148

NC_149 NC_150

NC_151 NC_152

AH30 AG31

AG29 AF28

AF27 AF26

AD27 AD26

AC25 AB25

Y23 Y24

AB27 AB26

Y27 Y26

W24 W23

V27 U26

U24 U23

T26 T27

T24 T23

P27 P26

P24 P23

M27 N26

Y22

AA22

1 2

RV47 1.69K_0402_1%DIS@

1 2

RV48 1K_0402_1%

PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0

PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1

PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2

PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3

DIS@

CLKREQ_PCIE4_VGA#[10]

+0.95VS_VGA

+3VS_VGA

12

RV50 10K_0402_5%@

RV49

@

VGA_ON[6,14,33,79]

10K_0402_5%

CV141

@

12

0.1U_0402_10V7-K

1

2

CV140

0.1U_0402_10V7-K

1

@

2

1 3

D

2N7002KW_SOT323-3

SB000019400

1 2

RV51 0_0402_5%

+3VS_VGA

12

RV52

@

2

G

QV7

S

@

10K_0402_5%@

CLK_REQ_GPU#

RV53 10K_0402_5%

@

1 2

CLK_REQ_GPU# [25]

D D

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

LCFC Confidential

1

2

THIS SHEET OF ENGINEERING DR AWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

3

2013/09/07

LC Future Center Secret Data

Deciphered Date

4

2014/09/07

Title

Topaz & Jet PCIE

Size Document Number Re v

Custom

Wednesday, August 05, 2015

Date: Sheet o f

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

5

24 83

1.0

5

4

3

2

1

UV3A

1 1 1 1 1 1

G

5

S

D

DIS@

1 2

RV113 0_0402_5%@

1 2

RV114 0_0402_5%@

+3VS_VGA

12

RV64 10K_0402_5%

@

XTALOUT

+3VS_VGA

G

S

2N7002KDWH_SOT363-6

DIS@

QV2B

SB000013A00

34

12

2

QV2A

SB000013A00

61

D

PU AT EC SIDE, +3VS AND 4.7K

VGA_AC_DC#[66]

+3VS_VGA

12

RV61 10K_0402_5%

DIS@

OCP_L

12

RV65

RV66

10K_0402_5%

@

4

1

27MHZ_16PF_7V27000011

1

CV143

DIS@

22P_0402_50V8-J

2

1 2

1K_0402_1%

YV1

NC2

OSC1

VGA_AC_DC#

RV62

12

RV68

1 2

1M_0402_5%

DIS@

OSC2

JTAG_TRSTB

NC1

+3VS_VGA

@

RV67 10K_0402_5%

@

JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

DIS@

3

2

22P_0402_50V8-J

RB751V-40_SOD323-2

DIS@

1

2

12

EC_SMB_CK3 [11,37,59,60,66]

EC_SMB_DA3 [11,37,59,60,66]

DIS@

1 2

RV111 2.2K_0402_5%

DV2

GPIO5_AC_BATT

1 2

SCS00007P00

GPIO6

CV142

0.1U_0402_10V7-K

@

EC_WAKE#[6,66]

XTALIN

1

CV144

DIS@

2

D D

SMBCLK

SMBDAT

2N7002KDWH_SOT363-6

C C

GPU_VR_HOT#[66,79]

B B

RV63 10K_0402_5%

@

A A

+1.8VS_VGA

RV54

4.7K_0402_5%

MESO@

1

TPV1Test_Point_20MIL

1

TPV2Test_Point_20MIL

+3VS_VGA

請

B I O S

直直直

CLK_REQ_GPU#[24]

+3VS_VGA

RV140 0_0402_5%

1 2

+1.8VS_VGA

@

1 2

RV115

4.7K_0402_5%

@

12

1

TPV7Test_Point_20MIL

1

TPV8Test_Point_20MIL

1

TPV9Test_Point_20MIL

1

TPV10Test_Point_20MIL

1

TPV11Test_Point_20MIL

12

RV55

4.7K_0402_5%

MESO@

SVI2_SVD

GPIO19_CTF SVI2_SVC

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

+3VS_VGA

2

G

@

1 3

D

2N7002KW_SOT323-3

SB000019400

CV145

1U_0402_10V6-K

1

DIS@

2

1

QV4

S

RV72 4.7K_0402_5%DI S@

RV73 4.7K_0402_5%DI S@

SMBDAT SMBCLK

GPIO5_AC_BATT

GPIO6

RV76 5.11K_0402_1%@

RV77 1K_0402_1%D IS@

TPV12Test_Point_20MIL

+3VS_VGA

RV70

4.7K_0402_5% @

1 2

RV117 0_0402_5%@

1 2

RV116 0_0402_5%@

RV112 0_0402_5%@ RV75 10K_0402_5%DIS@

1 2

RV78 0_0402_5%@

RV79 0_0402_5%@

RV80 4.7K_0402_5%

RV106 4.7K_0402_5%

RV81 16.2K_0402_1%

RV82 10K_0402_5%DIS@ RV83 10K_0402_5%DIS@

+3VS_VGA

12

RV74 10K_0402_5%@

1 2 1 2

1 2

1 2 1 2

1

TPV3Test_Point_20MIL

1

TPV4Test_Point_20MIL

1

TPV5Test_Point_20MIL

1 2

1

TPV6Test_Point_20MIL

@

MESO@

RV84

1 1 1 1 1 1 1 1 1 1 1 1

12

RV71

4.7K_0402_5%@

GPIO8_ROMSO GPIO9_ROMSI GPIO10_ROMSCK

GPIO22_ROMCSB

1

TPV13Test_Point_20MIL

XTALIN XTALOUT

EXO@

1 2

10K_0402_5%

N9

TPV17Test_Point_20MIL TPV18Test_Point_20MIL TPV19Test_Point_20MIL TPV20Test_Point_20MIL TPV21Test_Point_20MIL TPV22Test_Point_20MIL TPV23Test_Point_20MIL TPV24Test_Point_20MIL TPV25Test_Point_20MIL TPV26Test_Point_20MIL TPV27Test_Point_20MIL TPV28Test_Point_20MIL TPV29Test_Point_20MIL TPV30Test_Point_20MIL TPV31Test_Point_20MIL TPV32Test_Point_20MIL TPV33Test_Point_20MIL TPV34Test_Point_20MIL

GPIO15

GPIO20

FDO

NC_DBG_DATA16

L9

NC_DBG_DATA15

AE9

NC_DBG_DATA14

Y11

NC_DBG_DATA13

AE8

NC_DBG_DATA12

AD9

DBG_DATA11

AC10

DBG_DATA10

AD7

DBG_DATA9

AC8

DBG_DATA8

AC7

DBG_DATA7

AB9

DBG_DATA6

AB8

DBG_DATA5

AB7

DBG_DATA4

AB4

DBG_DATA3

AB2

DBG_DATA2

Y8

DBG_DATA1

Y7

DBG_DATA0

AL9

NC_DBG_CNTL0

U1

BP_0

U3

BP_1

AM26

DIECRACKMON

W6

NC_2

V6

NC_3

AC6

NC_4

AC5

NC_5

AA5

NC_6

AA6

NC_7

Y6

NC_8

I2C

R1

SCL

R3

SDA

GENERAL PURPOSE I/O

U6

GPIO_0

U8

SMBDATA

U7

SMBCLK

T9

GPIO_5_AC_BATT

T8

GPIO_6_TACH

T7

NC_GPIO_7

P10

GPIO_8_ROMSO

P4

GPIO_9_ROMSI

P2

GPIO_10_ROMSCK

N6

NC_GPIO_11

N5

NC_GPIO_12

N3

NC_GPIO_13

N1

GPIO_15_PWRCNTL_0

M4

GPIO_16

R6

GPIO_17_THERMAL_INT

M2

GPIO_19_CTF

P8

GPIO_20_PWRCNTL_1

P7

GPIO_21

N8

GPIO_22_ROMCSB

AK10

GPIO_29

AM10

GPIO_30

N7

CLKREQB

L6

JTAG_TRSTB

L5

JTAG_TDI

L3

JTAG_TCK

L1

JTAG_TMS

K4

JTAG_TDO

K7

TESTEN

AF24

NC_9

W8

NC_GENERICB

W7

NC_GENERICD

AD10

NC_GENERICE_HPD4

AJ9

NC_10

AB16

PX_EN

AJ27

WAKEB

AC16

NC_DBG_VREFG

PLL/CLOCK

AA1

PLL_ANALOG_IN

AA3

PLL_ANALOG_OUT

AM28

XTALIN

AK28

XTALOUT

AC22

XO_IN

AB22

XO_IN2

T4

DPLUS

T2

DMINUS

R5

GPIO28_FDO

AD17

TSVDD

AC17

TSVSS

AE19

TS_A

216-0858020-A0_FCBGA631

DBG

THERMAL

NC_DPA

NC_DPB

NC_DPC

NC_AVSSN_1

NC_AVSSN_2

NC_AVSSN_3

NC_DAC1

NC_GENLK_CLK

NC_GENLK_VSYNC

MLPS&SVI 2

NC_SWAPLOCKA

NC_SWAPLOCKB

NC_DDC/AUX

NC_DDC1CLK

NC_DDC1DATA

NC_DDCVGACLK

NC_DDCVGADATA

@

NC_13 NC_14

NC_15 NC_16

NC_17 NC_18

NC_19 NC_20

NC_21 NC_22

NC_23 NC_24

NC_25 NC_26

NC_27 NC_28

NC_29 NC_30

NC_31

NC_32 NC_33

NC_34

NC_35

NC_HSYNC

NC_RSET

NC_AVDD

NC_AVSSQ

NC_VDD1DI NC_VSS1DI

NC_CEC_1

GPIO_SVD GPIO_SVT GPIO_SVC

NC_AUX1P NC_AUX1N

NC_AUX2P NC_AUX2N

NC_36 NC_37

AF2 AF4

AG3 AG5

AH3 AH1

AK3 AK1

AK5 AM3

AK6 AM5

AJ7 AH6

AK8 AL7

V4 U5

V2

Y4 W5

Y2

J8

AL25

NC_G

AK26

AJ25 AH24

NC_B

AG25

AH26

AD22

AG24 AE22

AE23 AD23

AM12

AK12

1 2

RV107 0_0402_5%MESO@

1 2

AL11

RV108 0_0402_5%MESO@

1 2

AJ11

RV109 0_0402_5%MESO@

AL13 AJ13

AG13

PS_0

AC19

PS_0

AH12

PS_1

AD19

PS_1

PS_2

PS_3

PS_2

AE17

PS_3

AE20

AE6 AE5

AD2 AD4

AD13 AD11

AE16 AD16

AC1 AC3

GPIO15

GPIO20

SVI2_SVD SVI2_SVT SVI2_SVC

PLT_RST_VGA#[24,79]

RV89 33_0402_5%@

RV90 33_0402_5%@

8.45K_0402_1%

RV99 2K_0402_1%

4.75K_0402_1%

GPIO19_CTF

1 2

SVI2_SVD [79] SVI2_SVT [79] SVI2_SVC [79]

+1.8VS_VGA

RV98

+1.8VS_VGA

DIS@

RV103

12

DIS@

1 2

12

@

RV102 10K_0402_1%

12

PLT_RST_VGA#

RV91 10K_0402_5%

@

RV93 10K_0402_5%

@

CV153

0.1U_0402_10V7-K

1

@

2

CV155

0.1U_0402_10V7-K

1

@

2

RV86 47K_0402_5%@

+3VS_VGA

12

PS_0

PS_1

1 2

12

RB751V-40_SOD323-2

SCS00007P00

RV92 10K_0402_5%

@

RV94 10K_0402_5%

@

CV151

@

4.75K_0402_1%

3.24K_0402_1%

5.62K_0402_1%

@

DV1

1 2

0.1U_0402_10V7-K

1

2

SVI2_SVD

SVI2_SVT

SVI2_SVC

+1.8VS_VGA

DIS@

RV101

+1.8VS_VGA

RV104

X76@

RV105

X76@

CV152

@

12

+3VS_VGA

10U_0603_6.3V6-M

1

2

RV118 10K_0402_5%

@

1 2

@

RV100 10K_0402_1%

CV154

@

CV156

@

CV149

@

0.1U_0402_10V7-K

1

2

0.1U_0402_10V7-K

1

2

12

RV88 100K_0402_5%

@

0.1U_0402_10V7-K

1

2

RV95

1 2

10K_0402_5%

@

PS_2

PS_3

RV87

1 2

2.2K_0402_5%

1

2

3

5

74AVCH2T45GD_XSON8_3X2

+3VS_VGA

RV119 10K_0402_5%

@

1 2

@

UV9

VCC(A)

1A

2A

DIR

Samsun g

Hynix

Micro n

2

B

CV148

0.1U_0402_10V7-K

E

1

@

2

@

8

VCC(B)

7

1B

6

2B

4

GND

RV120 10K_0402_5%

EXO@

1 2

Memory (GDDR3)

C

QV3 MMST3904-7-F_SOT323-3

SB000010U00

3 1 @

+1.8VS_VGA

CV150

0.1U_0402_10V7-K

1

@

2

1 2

RV96 33_0402_5%@

1 2

RV97 33_0402_5%@

SVI2_SVD

SVI2_SVT

SVI2_SVC

VID CODES

SVC SVD Boot Voltage

1G

2G

1G

2G

1G

2G

RV121 10K_0402_5%

@

1 2

RV122 10K_0402_5%

DIS@

1 2

0 0 001

1

1 1

SA22225 SH30* 4

SA00006 3F00* 4

SA00005 VS10* 4

SA00005 YL10* 4

SA00005 M100* 4

SA00006 0I00* 4

H_THERMTRIP# [6]

SVI2_SVD

SVI2_SVC

+1.8VS_VGA

RV123 10K_0402_5%

@

1 2

RV124 10K_0402_5%

@

1 2

1.1V

1.0V

0.9V(Default)

0.8V

RV104

PU 8.45K

PU 3 .4K PD 10K

PU 4.53K PD 2K

PU 4.75K NC

NC PD 4.75K

PU 3.24K PD 5.62K

RV125 10K_0402_5%

MESO@

1 2

RV126 10K_0402_5%

@

1 2

RV105

PD 2K

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY O F LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERTY O F LC FUTURE CENTER. AND CONTAINS C ONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY L C FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTE N CONSENT OF LC FUTURE CE NTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTE N CONSENT OF LC FUTURE CE NTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRITTE N CONSENT OF LC FUTURE CE NTER.

2

2013/09/07

LC Future Center Secret Data

Deciphered Date

2014/09/07

Title

Topaz & Jet GPIO

Size

Document N umber R ev

Custom

Date: Sheet of

Wednesday, August 05, 2015

1

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

25 83

1.0

LCFC Confidential

1

2

3

4

5

TPV14

+1.35VS_VGA

CV3

CV4

CV18

CV21

CV25

CV5

2.2U_0402_6.3V6-K

1

DIS@

2

CV19

10U_0603_6.3V6-M

1U_0402_10V6-K

1

DIS@

2

1U_0402_10V6-K

1

DIS@

2

0.1U_0402_10V7-K

1

DIS@

2

CV2

+1.8VS_VGA

+3VS_VGA

+1.8VS_VGA

+0.95VS_VGA

CV1

.01U_0402_16V7-K

1

DIS@

2

1 2

BLM18PG221SN1D_2P

1 2

BLM18PG121SN1D_2P

1 2

BLM18PG121SN1D_2P

A A

B B

C C

LV3

LV4

DIS@

LV5

DIS@

CV8

0.1U_0402_10V7-K

1

DIS@

2

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

1

DIS@

2

CV9

1U_0402_10V6-K

1

DIS@

2

CV10

1U_0402_10V6-K

1

DIS@

2

CV17

10U_0603_6.3V6-M

1

DIS@

2

CV20

10U_0603_6.3V6-M

1

DIS@

2

CV24

1U_0402_10V6-K

1

DIS@

2

CV6

DIS@

1

2

2.2U_0402_6.3V6-K

MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

CV7

2.2U_0402_6.3V6-K

1

@

2

90mA

75mA

100mA

UV3B

MEM I/O

H13

VMEMIO_1

H16

VMEMIO_2

H19

VMEMIO_3

J10

VMEMIO_4

J23

VMEMIO_5

J24

VMEMIO_6

J9

VMEMIO_7

K10

VMEMIO_8

K23

VMEMIO_9

K24

VMEMIO_10

K9

VMEMIO_11

L11

VMEMIO_12

L12

VMEMIO_13

L13

VMEMIO_14

L20

VMEMIO_15

L21

VMEMIO_16

L22

VMEMIO_17

LEVE L TRANSLAT ION

AA20

VDD_GPIO18_1

AA21

VDD_GPIO18_2

AB20

VDD_GPIO18_3

AB21

VDD_GPIO18_4

I/O

AA17

VDD_GPIO33_1

AA18

VDD_GPIO33_2

AB17

VDD_GPIO33_3

AB18

VDD_GPIO33_4

V12

NC_VDDR4_1

Y12

NC_VDDR4_2

U12

NC_VDDR4_3

PLL

L8

MPLL_PVDD

H7

SPLL_PVDD

H8

SPLL_VDDC

J7

SPLL_PVSS

216-0858020-A0_FCBGA631

PCIE_PVDD

PCIE

NC_38 NC_39 NC_40 NC_41 NC_42 NC_43 NC_44 NC_45

PCIE_VDDC_1 PCIE_VDDC_2 PCIE_VDDC_3 PCIE_VDDC_4 PCIE_VDDC_5 PCIE_VDDC_6 PCIE_VDDC_7 PCIE_VDDC_8

PCIE_VDDC_9 PCIE_VDDC_10 PCIE_VDDC_11 PCIE_VDDC_12

CORE

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20

POWER

VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36

FB_VDDC

FB_GND_1

BIF_VDDC_1 BIF_VDDC_2

ISOLATE D

CORE I/O

VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4 VDDCI_5 VDDCI_6 VDDCI_7 VDDCI_8

FB_VDDCI FB_GND_2

VDDC_SEN[79]

VDDC_RTN[79]

VDDC_SEN

VDDC_RTN

Test_Point_32MIL

@

AM30

AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26

L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22

AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 AA12 M11 N12 U11 AB13 U10 W9 Y9 W10 T10 AC14 AB12 AB11 AC11 AC13

AC20 AD20

R21 U21

M13 M15 M16 M17 M18 M20 M21 N20

W1 W3

1

Only available on TOPAZ, NC balls on JET

TOPAZ_VDDC_SEN TOPAZ_VDDC_RTN

CV59

FOR JET,PUT VIAS UNDER ASIC

1 2

RV1 0_0402_5%E XO@

1 2

RV2 0_0402_5%E XO@

CV29

CV37

CV51

1

DIS@

2

10U_0603_6.3V6-M

1

DIS@

2

CV38

2.2U_0402_6.3V6-K

1

DIS@

2

CV52

2.2U_0402_6.3V6-K

1

DIS@

2

CV60

10U_0603_6.3V6-M

1

DIS@

2

1U_0402_10V6-K

1

DIS@

2

CV39

2.2U_0402_6.3V6-K

1

DIS@

2

CV53

2.2U_0402_6.3V6-K

1

DIS@

2

CV61

10U_0603_6.3V6-M

1U_0402_10V6-K

1

DIS@

2

CV31

CV30

CV62

DIS@

CV32

DIS@

CV40

DIS@

CV54

DIS@

1U_0402_10V6-K

1

2

1U_0402_10V6-K

1

2

2.2U_0402_6.3V6-K

1

2

2.2U_0402_6.3V6-K

1

2

CV63

1

DIS@

2

+VGA_CORE

CV26

CV33

CV41

CV55

10U_0603_6.3V6-M

1

DIS@

2

1U_0402_10V6-K

1

DIS@

2

2.2U_0402_6.3V6-K

1

DIS@

2

2.2U_0402_6.3V6-K

1

@

2

CV64

1U_0402_10V6-K

DIS@

CV27

1U_0402_10V6-K

1

DIS@

2

CV34

1U_0402_10V6-K

1

DIS@

2

CV42

2.2U_0402_6.3V6-K

1

DIS@

2

CV56

2.2U_0402_6.3V6-K

1

@

2

+0.95VS_VGA

0.1U_0402_10V7-K

1

2

CV28

DIS@

CV35

DIS@

CV43

DIS@

CV57

@

+VGA_CORE

CV65

0.1U_0402_10V7-K

1

DIS@

2

+1.8VS_VGA

1U_0402_10V6-K

1

2

1U_0402_10V6-K

1

2

2.2U_0402_6.3V6-K

1

2

2.2U_0402_6.3V6-K

1

2

CV36

CV44

CV58

+0.95VS_VGA

1U_0402_10V6-K

1

@

2

+VGA_CORE

CV47

CV48

2.2U_0402_6.3V6-K

1

DIS@

2

1

@

2

CV22

DIS@

10U_0603_6.3V6-M

1

DIS@

2

2.2U_0402_6.3V6-K

1U_0402_10V6-K

1

2

10U_0603_6.3V6-M

1

DIS@

2

CV46

CV45

CV49

10U_0603_6.3V6-M

1

DIS@

2

CV50

10U_0603_6.3V6-M

1

DIS@

@

2

D D

VDDC_SEN

VDDC_RTN

MESO@

1 2

RV3 0_0402_5%

MESO@

1 2

RV4 0_0402_5%

LCFC Confidential

1

2

3

TOPAZ_VDDC_SEN

TOPAZ_VDDC_RTN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/09/07

LC Future Center Secret Data

Deciphered Date

4

2014/09/07

Title

Topaz & Jet Core Power

Size Document Number Re v

Custom

Wednesday, August 05, 2015

Date: Sheet of

BE460_NM-A551

BE460_NM-A551BE460_NM-A551

5

26 83

1.0

Lenovo E460,BE460 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual