Lenovo 110-15ISK Schematics
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B
C
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Compal Confidential
2 2
Nano 110
DIS M/B Schematics Document
Intel Skylake / Kabylake U Processor with DDR4
AMD R17M-M1-70
2016-12-05
3 3
LA-D562P
R E V
：
2 . 0
4 4
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
Cover Page
Cover Page
Cover Page
Document Number Re v
Document Number Re v
Document Number Re v
LA-D562P
LA-D562P
LA-D562P
E
1 52Monday, April 10, 2017
1 52Monday, April 10, 2017
1 52Monday, April 10, 2017
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Channel A
1 1
eDP Conn.
HDMI Conn.
2 2
RJ45 Conn.
AMD Radeon 520M
VRAM DDR3L x4
LAN
RTL8107E-CG
10/100
PCIe Port 5
PCIe X4
Gen2
eDP X1
(2 Lanes)
DDI X1
(4 Lanes)
PCIe X1
(1 Lanes)
Intel Kabylake U
SOC
1356 pin BGA
DDR4 2133MHz (1.2V , 2.5V)
Channel B
DDR4 2133MHz (1.2V , 2.5V)
USB3.0 x1
USB2.0 x1
USB2.0 x1
USB2.0 x1
PCIe X1 for WLAN
(1 Lanes)
USB2.0 x1 for BT
On board DDR4 X 4
4G
DDR4 SO DIMM X1
2G/4G2G
Left USB3.0 x1
USB30 Port 2
USB20 Port 2
Left USB2.0 x1
USB20 Port 4
Int. Camera
USB 2.0 Port 5
WLAN / BT
PCIe Port 6
Card Reader
Realtek
RTS5170
USB 2.0 Port 6
3 3
DC to DC
USB2.0 x1
SPILPC
SATA X1
SATA X1
HDA
HDD Conn.
SATA Port 0
ODD Conn.
SATA Port 1
Audio Codec
CONEXANT
CX11802
EC
Nuvoton
NPCE388N
SPI ROM
8MB
Int. MIC Conn. Int. Speaker Conn.
Audio Combo Jack
HP & MIC
LED
4 4
A
B
Touch Pad Int. KBD
C
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
Block Diagram
Block Diagram
Block Diagram
LA-D562P
LA-D562P
LA-D562P
E
2 52Monday, April 10, 2017
2 52Monday, April 10, 2017
2 52Monday, April 10, 2017
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Voltage Rails
power
State
S0
S3
S5 S4/AC
plane
Address
0001 011xSmart Battery
+B
O
O
O
O
X
+5VALW
+3VALW
O
O
O
X
A A
B B
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
EC SM Bus1 address
Device
2
+1.2V
O O
O
X
+5VS
+3VS
+1.35VGS
+VCCSA
+VCCCORE
+VCCGT
+VGACORE
+1.8VS
+0.6VS
+1VS
X
XX
X
XXX
USB Port Table
USB 2.0
UHCI0
EHCI1
Port
Port
0
1
UHCI1
UHCI2
UHCI3
USB 3.0 Port Table
1
2
USB3 MB(JUSB1)
3
4
5
6
SATA Port Table
HDD
ODD
3
Port
3 External
USB Port
1
USB Port (Left Side)
2
3
4
USB Port (Left Side)
5
Camera
6
Card Reader
7
NGFF(WLAN)
USB 3.0
USB 2.0
PCIE Port Table
Port
Lane
1
1
2
2
3
3
4
4
5
6
7
8
9
10
4
GPU
LAN
NGFF WLAN+BT
BOM Structure Table
CIWP0 (14")
CIWP1 (15") 15@
GPU R16M-M1-30 M1@
GPU R17M-M1-70 M2@
For DIS
EMI pop
EMI Un-pop
ESD pop
ESD Un-pop
VRAM indentify
System RAM indentify X 76RAM@
SA000092P60
SA000094250
SA000093780 CPU 4@
SA00009QZ10
SA00009QX10
SA0000ACL40
SA0000A3430
SA0000A3730
SA0000A3870
X7667538L06 M4G 2@
X7672938L04
X7672938L05
X7667538L03
X7667538L04
X7667538L05
BOM StructureItem
14@
PX@
UMA@For UMA
CMOS@Came ra
EMI@
@EMI@
ESD@
@ESD@
RF@RF pop
@RF@RF unpop
RS@R-Sh ort
TP@Test Point
X76@
45@HDMI Royalty
ME@Connect or
CPU1@
CPU2@SA000092OA0
CPU3@
CPU5@
CPU6@
CPU7@
CPU8@
CPU9@
CPU1 0@
S4G@X7667538L01
M4G@X7667538L02
S4G2@
H4G@
JS2G@
JM2G@
JH2G@
5
PCH SM Bus address
DDR_JDIMM 1
C C
D D
SMBUS Control Table
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
PCH_SMBCLK
PCH_SMBDATA
PCH_SML0CLK
PCH_SML0DATA
SML1CLK
SML1DATA
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
AddressDevice
1010 000x A0h
1
SOURCE
NECP388
+3VALW
NECP388
+3VS
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW
SIGNAL
BATT
GPU
V
X X
+3VALW
X
V
+3VGS
X
X
XX
X X
V
+3VGS
SLP_S1#
LOW
LOW
LOW LOW LOW
SLP_S4#SLP_S3# +V( RAM)+VALWSLP_S5# Clo ck+VS
HIGH HIGH HIGH
LOW
LOWLOW
HIGHHIGHHIGH
HIGH
X
X
X
V
+3VS
HIGH
HIGH
HIGH
LOWLOW
SODIMMNECP388
+3VS
X
V
XX
X
ONONON
ON
ON
ON
ON
SOC
X
V
+3VALW
X
X
ON
OFF
OFF
2
ON
OFF
OFF
OFF
ONON
LOW
OFF
OFF
OFF
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
UC1
CPU1@
CPU i7 6500U
SA000092P60
UC1
CPU8@
CPU i7-7500U
SA0000A3430
ZZZ
14@
PCB
DA6001KC320
UV1
M1@
VGA
SA000087TA0
ZZZ
S4G@
4G SAMSUNG 2133
X7667538L01
2011/06/24 2012/07/12
2011/06/24 2012/07/12
2011/06/24 2012/07/12
UC1
CPU2@
CPU i5 6200U
SA000092OA0
UC1
CPU9@
CPU i5-7200U
SA0000A3730
ZZZ
15@
PCB
DA6001KC220
UV1
M2@
VGA
SA000098VA0
ZZZ
M4G@
4G MICRON 2133
X7667538L02
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
4
CPU3@
CPU 4405U
SA000094250
CPU10@
CPU i3-7100U
SA0000A3870
M4G2@
4G MICRON 2400
X7667538L06
UC1
UC1
ZZZ
UC1
CPU4@
CPU 3855U
SA000093780
ZZZ
S4G2@
4G Samsung 2400
X7672938L04
UC1
CPU5@
CPU i5 6198DU
SA00009QZ10
ZZZ
H4G@
4G Hynix 2400
X7672938L05
Title
Title
Title
Notes List
Notes List
Notes List
Size
Size
Size
Document Number Re v
Document Number Re v
Document Number Re v
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
UC1
CPU6@
CPU i7 6498DU
SA00009QX10
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-D562P
LA-D562P
LA-D562P
5
UC1
CPU7@
CPU i3-6006U
SA0000ACL40
3 52Monday, April 10, 2017
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3
2
1
M1-70 VRAM STRAP
Vendor
UV3, UV4, UV5, UV6
D D
C C
JS2 G@
X7667538L03
JM2 G@
X7667538L04
JH2 G@
X7667538L05
Samsung 4096Mbits
SA000076 P80
256MX16 K4W4G1646E-BC1A
Micron 4096Mbits
SA00009H F00
256Mx16 MT41J256M16LY-091G:N
Hynix 4096Mbits
SA00008D N00
256MX16 H5TC4G63CFR-N0C
ZZZ
JH2G@
2G HYNIX
X7667538L05
ZZZ
JM2G@
2G MICRON
X7667538L04
2GBy tes
2GBy tes
2GBy tes
JS2G@
2G SAMSUNG
X7667538L03
ID
0 0
0
1
2
4
5 11 0 3.2 4K 5.6 2K
6 10K3.4 K011
ZZZ
PS_3[ 1 ]PS_3[ 2 ]PS_3[ 3 ]
0
10 0
00 1
001 4.9 9K4.5 3K
X76@X76@
R_pd
R_pu
RV21 RV24
NC 4.7 5K
8.4 5K 2K
4.5 3K 2K
Power-Up/Down Sequence
"M1" has the following requirements with regards to power-supply
sequencing to avoid damaging the ASIC:
‧
All the ASIC supplies must reach their respective nominal voltages within 20ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.
The maximum slew rate on all rails is 50 mV/μ s.
‧
It is recommended that the 3.3-V rail ramp up frist.
‧
It is recommended that the 0.95-V rail reach at least 90% of its nominal value no later
than 2ms from the start of VDDC ramping up.
‧
The power rails that are shared with other components on the system should be gated for
the dGPU so that when dGPU is powered down (for example AMD PowerXpressTM idle state),
all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as 50mV/us)
‧
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.
‧
≦
VDDR3(+3VGS)
PCIE_VDDC(+0.95VGS)
VDD_CT(+1.8VGS)
VDDR1(+1.35VGS)
VDDC/VDDCI(+VGA_CORE)
DGPU_PWROK
PERSTb
REFCLK
Straps Reset
B B
Straps Valid
Global ASIC Reset
A A
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL E LECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED B Y OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2015/01/07 2016/01/07
2015/01/07 2016/01/07
2015/01/07 2016/01/07
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size
Size
Size
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
VGA Notes List
VGA Notes List
Document Number Re v
Document Number Re v
Document Number Re v
VGA Notes List
LA-D562P
LA-D562P
LA-D562P
1
4 52Monday, April 10, 2017
4 52Monday, April 10, 2017
4 52Monday, April 10, 2017
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B
C
D
E
DDI
DISPLAY SIDEBANDS
CPU MISC
SKL-U
1 OF 20
SKL-U
JTAG
4 OF 20
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
Rev_1.0
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
JTAGX
Rev_1.0
RSVD
RSVD
CPU_XDP_TCK 0
SOC_XDP_TDI
SOC_XDP_TDO
SOC_XDP_TMS
SOC_XDP_TRST #
PCH_JTAG_TC K1
SOC_XDP_TDI
SOC_XDP_TDO
SOC_XDP_TMS
PCH_XDP_TRS T#
CPU_XDP_TCK 0
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
T116 TP@
EDP_TXN0 [27]
EDP_TXP0 [27]
EDP_TXN1 [27]
EDP_TXP1 [27]
EDP_AUXN [27]
EDP_AUXP [27 ]
TMDS_B_HPD [28]
EC_SCI# [9,33]
EDP_HPD [27]
ENBKL [27,33]
INVPWM [27]
PCH_ENVDD [27]
<eDP>
From HDMI
From eDP
< PU/PD for CMC Debug >
SOC_XDP_TMS
SOC_XDP_TDI
SOC_XDP_TDO
CPU_XDP_TCK 0
PCH_JTAG_TC K1
SOC_XDP_TRST #
1 2
RC11 51_0402_5 %@
1 2
RC12 51_0402_5 %@
1 2
RC13 51_0402_5 %@
1 2
RC14 51_0402_5 %@
1 2
RC15 51_0402_5 %@
1 2
RC23 51_0402_5 %
+1.0VS_VCCIO
UC1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
HDMI_TX2-_CK[28]
HDMI_TX2+_CK[28 ]
HDMI_TX1-_CK[28]
<HDMI >
HDMI DDC (Port C)
2 2
+1.0VS_VCCIO
+1.0VS_VCCIO
H_PROCHOT#[3 3]
+1.0V_VCCST
3 3
< Compensat i on P U For eDP >
EDP_COMP
1 2
RC3 24.9_0402_1 %
Trace width=20 mils, Spacing=25mil, Max length=100mils
12
RC4
1K_0402_5%
H_PROCHOT# _R
1 2
RC6 499_0402_ 1%
H_THERMT RIP#
1 2
RC5 1K_0402_5%
HDMI_TX1+_CK[28 ]
HDMI_TX0-_CK[28]
HDMI_TX0+_CK[28 ]
HDMI_CLK-_CK[28]
HDMI_CLK+_CK[28]
HDMICLK_NB[28]
HDMIDAT_NB[28]
H_PECI[33]
RC7 49.9_0402_1 %
RC8 49.9_0402_1 %
RC9 49.9_0402_1 %
RC10 49.9_0402_1 %
EDP_COMP
H_PECI
H_PROCHOT# _R
H_THERMT RIP#
12
12
12
12
T99 TP@
T100 TP@
T103 TP@
T105 TP@
T107 TP@
T109 TP@
T111 TP@
T115 TP@
CPU_POPIRCOMP
PCH_OPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
C50
D50
C52
D52
A50
B50
D51
C51
L13
L12
N7
N8
N11
N12
E52
SOC_CATERR#
SOC_OCC#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
SOC_GPIOE3
SOC_GPIOB4
DDI2_TXN[0]
DDI2_TXP[0]
DDI2_TXN[1]
DDI2_TXP[1]
DDI2_TXN[2]
DDI2_TXP[2]
DDI2_TXN[3]
DDI2_TXP[3]
GPP_E18/DDPB_CTRLCLK
GPP_E19/DDPB_CTRLDATA
GPP_E20/DDPC_CTRLCLK
GPP_E21/DDPC_CTRLDATA
GPP_E22
GPP_E23
EDP_RCOMP
SKL-U_BGA1356
@
UC1D
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
SKL-U_BGA1356
@
4 4
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2014/05/19 2015/12/31
2014/05/19 2015/12/31
2014/05/19 2015/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size D ocument Number Re v
Size D ocument Number Re v
Size D ocument Number Re v
Date : Sheet of
Date : Sheet of
D
Date : Sheet of
Compal Electronics, Inc.
SKL-U(1/12)DDI,EDP,MISC,CMC
SKL-U(1/12)DDI,EDP,MISC,CMC
SKL-U(1/12)DDI,EDP,MISC,CMC
Custom
Custom
Custom
LA-D562P
LA-D562P
LA-D562P
E
2.0
2.0
5 52Monday, April 10, 2017
5 52Monday, April 10, 2017
5 52Monday, April 10, 2017
2.0
5
Aditya11ttt
Aditya11ttt
4
3
2
1
Interleaved Memory
D D
DDR_A_D[0..15][17]
DDR_A_D[16..31][17]
C C
DDR_A_D[32..47][17]
DDR_A_D[48..63][17]
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
UC1B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
Interleave / Non-Interleaved
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKL-U_BGA1356
@
SKL-U
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA [14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
2 OF 20
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR3L / LPDDR3 / DDR4
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
Interleave / Non-Interleaved
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_ALERT#
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
DDR0_MA[3]
DDR0_MA[4]
DDR0_PAR
Rev_1.0
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_CKE0
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1
DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_BG0
DDR_A_MA12
DDR_A_MA11
M_A_ACT#
DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA16
DDR_A_BA0
DDR_A_MA2
DDR_A_BA1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA4
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7
+0.6V_VREFCA
+0.6V_B_VREFDQ
DDR_PG_CTRL
DDR_A_CLK#0 [17]
DDR_A_CLK0 [17]
T20@
T19@
DDR_A_CKE0 [17,19]
T21@
DDR_A_CS#0 [17,19]
T23@
DDR_A_ODT0 [17,19]
T22@
DDR_A_MA5 [17,19]
DDR_A_MA9 [17,19]
DDR_A_MA6 [17,19]
DDR_A_MA8 [17,19]
DDR_A_MA7 [17,19]
DDR_A_BG0 [17,19]
DDR_A_MA12 [17,19]
DDR_A_MA11 [17,19]
M_A_ACT# [17,19]
T16@
DDR_A_MA13 [17,19]
DDR_A_MA15 [17,19]
DDR_A_MA14 [17,19]
DDR_A_MA16 [17,19]
DDR_A_BA0 [17,19]
DDR_A_MA2 [17,19]
DDR_A_BA1 [17,19]
DDR_A_MA10 [17,19]
DDR_A_MA1 [17,19]
DDR_A_MA0 [17,19]
DDR_A_MA3 [17,19]
DDR_A_MA4 [17,19]
DDR_A_DQS#0 [17]
DDR_A_DQS0 [17]
DDR_A_DQS#1 [17]
DDR_A_DQS1 [17]
DDR_A_DQS#2 [17]
DDR_A_DQS2 [17]
DDR_A_DQS#3 [17]
DDR_A_DQS3 [17]
DDR_A_DQS#4 [17]
DDR_A_DQS4 [17]
DDR_A_DQS#5 [17]
DDR_A_DQS5 [17]
DDR_A_DQS#6 [17]
DDR_A_DQS6 [17]
DDR_A_DQS#7 [17]
DDR_A_DQS7 [17]
DDR_A_ALERT# [17]
DDR_A_PARITY [17,19]
+0.6V_VREFCA [17]
T25@
+0.6V_B_VREFDQ [18]
DDR_B_D[0..15][18]
DDR_B_D[16..31][18]
DDR_B_D[32..47][18]
DDR_B_D[48..63][18]
Trace width/Spacing >= 20mils
Place componment near SODIMM
#543016 PDG0.9 P.163 RC place near SODIMM
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
UC1C
Interleave / Non-Interleaved
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL-U_BGA1356
@
1
CC1
0.1U_0201_10V6K
2
+3VS+1.2V +3VALW
12
CRB ORB
RC132
220K_0402_5%
12
RC19
100K_0402_5%
@
DDR_VTT_PG_CTRL [42]
< For ODT & VTT Power Control >
DDR_VTT_CNTL to DDR
VTT supplied ramped
<35u S
(tCPU 18)
DDR_PG_CTRL
A A
NC1VCC
2
A
3
GND
74AUP1G07GW_TSSOP5
SA00007WE00
UC2
5
4
Y
SKL-U
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA [14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR CH - B
3 OF 20
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR3L / LPDDR3 / DDR4
DDR1_MA[3]
DDR1_MA[4]
Interleave / Non-Interleaved
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
Rev_1.0
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1
DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0
DDR_B_ODT1
DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
M_B_ACT#
DDR_B_BG1
DDR_B_MA13
DDR_B_MA15
DDR_B_MA14
DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
#543016 PDG0.9 P.117
W=12-15 Space= 20/25 L=500mil
DDR_DRAMRST#
RC16 121_0402_1%
RC17 80.6_0402_1%
RC18 100_0402_1%
+1.2V
12
RC20
470_0402_5%
@
DDR_B_CLK#0 [18]
DDR_B_CLK#1 [18]
DDR_B_CLK0 [18]
DDR_B_CLK1 [18]
DDR_B_CKE0 [18]
DDR_B_CKE1 [18]
DDR_B_CS#0 [18]
DDR_B_CS#1 [18]
DDR_B_ODT0 [18]
DDR_B_ODT1 [18]
DDR_B_MA5 [18]
DDR_B_MA9 [18]
DDR_B_MA6 [18]
DDR_B_MA8 [18]
DDR_B_MA7 [18]
DDR_B_BG0 [18]
DDR_B_MA12 [18]
DDR_B_MA11 [18]
M_B_ACT# [18]
DDR_B_BG1 [18]
DDR_B_MA13 [18]
DDR_B_MA15 [18]
DDR_B_MA14 [18]
DDR_B_MA16 [18]
DDR_B_BA0 [18]
DDR_B_MA2 [18]
DDR_B_BA1 [18]
DDR_B_MA10 [18]
DDR_B_MA1 [18]
DDR_B_MA0 [18]
DDR_B_MA3 [18]
DDR_B_MA4 [18]
DDR_B_DQS#0 [18]
DDR_B_DQS0 [18]
DDR_B_DQS#1 [18]
DDR_B_DQS1 [18]
DDR_B_DQS#2 [18]
DDR_B_DQS2 [18]
DDR_B_DQS#3 [18]
DDR_B_DQS3 [18]
DDR_B_DQS#4 [18]
DDR_B_DQS4 [18]
DDR_B_DQS#5 [18]
DDR_B_DQS5 [18]
DDR_B_DQS#6 [18]
DDR_B_DQS6 [18]
DDR_B_DQS#7 [18]
DDR_B_DQS7 [18]
DDR_B_ALERT# [18]
DDR_B_PARITY [18]
DDR_DRAMRST# [17,18]
1 2
1 2
1 2
5
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2015/01/29 2016/01/29
2015/01/29 2016/01/29
2015/01/29 2016/01/29
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SKL-U(2/12)DDR3L
SKL-U(2/12)DDR3L
SKL-U(2/12)DDR3L
Size Documen t Number Re v
Size Documen t Number Re v
Size Documen t Number Re v
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Monday, April 10, 2017
Monday, April 10, 2017
Monday, April 10, 2017
1
LA-D562P
LA-D562P
LA-D562P
52
52
52
of
of
of
6
6
6
2.0
2.0
2.0
5
Aditya11ttt
Aditya11ttt
4
3
2
1
SMBALERT# (Internal Pull Down):
0 = Disable Intel ME TLS function ==> Default
1 = Enable Intel ME TLS function
SKL-U
LPC
SMBUS, SMLINK
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
5 OF 20
Rev_1.0
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
SOC_SMB CLK
SOC_SMB DATA
SOC_SMB ALERT#
SOC_SML 0CLK
SOC_SML 0DATA
SOC_SML 0ALERT#
EC_SMB_ CK2
EC_SMB_ DA2
SOC_SML 1ALERT#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRA ME#
LPC_CLK 0
RC26 22_0402 _5%E MI@
PM_CLKR UN#
T124TP@
T125TP@
1 2
SOC_SMB CLK [18]
SOC_SMB DATA [18]
EC_SMB_ CK2 [21,33]
EC_SMB_ DA2 [21,33]
LPC_AD0 [33]
LPC_AD1 [33]
LPC_AD2 [33]
LPC_AD3 [33]
LPC_FRA ME# [33]
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
AW13
AY11
M2
M3
J4
V1
V2
M1
G3
G2
G1
UC1E
SKL-U_BG A1356
@
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
D D
C C
+3VALW
1 2
RC126 10K_040 2_5%
1 2
RC21 1K_0402_5%@
1 2
RC22 1K_0402_5%@
+1.8VS_3 VS_PGPPA
1 2
RC25 8.2K_0402_5 %
KB_RST#
SOC_SPI_IO2
SOC_SPI_IO3
SERIRQ
SOC_SPI_C LK
SOC_SPI_S O
SOC_SPI_S I
SOC_SPI_IO2
SOC_SPI_IO3
SOC_SPI_C S#0
KB_RST#[33]
SERIRQ[33 ]
KB_RST#
SERIRQ
SML0ALERT# (Internal Pull Down):
eSPI or LPC
0 = LPC is selected for EC ==> Default
1 = eSPI is selected for EC
SMB
(Link to DDR)
SML1
(Link to EC,DGPU)
CK_LPC_ KBC [3 3]
+3VS
RPC1, RPC3 and RC30 are close to UC3
SOC_SPI_S O
SOC_SPI_S I
From CPU
B B
EC_SPI_CLK[33]
From EC
EC_SPI_MO SI[33]
EC_SPI_CS 0#[33 ]
EC_SPI_MISO[33]
SOC_SPI_IO3
EC_SPI_CL K
EC_SPI_MO SI SOC_SP I_SI_0_R
EC_SPI_CS 0#
EC_SPI_MISO
RPC1
1 8
2 7
3 6
4 5
33_0804 _8P4R_5%
EMI@
1 2
RC30 33_0402 _5%EMI@
RPC3
1 8
2 7
3 6
4 5
33_0804 _8P4R_5%
EMI@
SOC_SPI_S O_0_R
SOC_SPI_IO2_ 0_RSOC_SPI_IO2
SOC_SPI_S I_0_R
SOC_SPI_IO3_ 0_R
SOC_SPI_C LK_0_RSOC_SPI_C LK
SOC_SPI_C LK_0_R
SOC_SPI_C S#0
SOC_SPI_S O_0_R
< SPI ROM - 8M >
SOC_SPI_C S#0
SOC_SPI_IO2_ 0_R
UC3
1
/CS
2
DO(IO1)
3
/WP(IO2)
4
GND
W25 Q64FVSSIQ_SO8
/HOLD(IO3)
VCC
CLK
DI(IO0)
+3VALW
@
1 2
CC2 0.1U_020 1_10V6K
8
SOC_SPI_IO3_ 0_RSOC_SPI_S O_0_R
7
SOC_SPI_C LK_0_R
6
SOC_SPI_S I_0_R
5
1
CC3
10P_040 2_50V8J
2
@EMI@
SOC_SML 1ALERT#
SOC_SML 0CLK
SOC_SML 0DATA
SOC_SMB CLK
SOC_SMB DATA
EC_SMB_ CK2
EC_SMB_ DA2
PM_CLKR UN#
RC54 150K_0402_ 5%@
1 2
RC28 499_0402_1 %
1 2
RC29 499_0402_1 %
RPC2
1 8
2 7
3 6
4 5
1K_0804 _8P4R_5%
1 2
@
RC31 8.2K_0402_5 %
Follow 543016_SKL_U_Y_PDG_0_9
12
+1.8VS_3 VS_PGPPA
A A
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Custom
Custom
Custom
Date : Sheet
Date : Sheet
2
Date : Sheet
Compal Electronics, Inc.
SKL-U(3/12)SPI,SMB,LPC,ESPI
SKL-U(3/12)SPI,SMB,LPC,ESPI
SKL-U(3/12)SPI,SMB,LPC,ESPI
LA-D562P
LA-D562P
LA-D562P
7 52Monday, April 10, 201 7
7 52Monday, April 10, 201 7
7 52Monday, April 10, 201 7
o f
o f
1
o f
2.0
2.0
2.0
5
Aditya11ttt
Aditya11ttt
4
3
2
1
< HD AUDIO >
HDA_BITCL K_AUDIO[35]
HDA_SYNC_A UDIO[3 5]
HDA_SDO UT_AUDIO[35]
D D
C C
HDA_RST _AUDIO#[35]
RPC4
1 8
2 7
3 6
4 5
33_0804 _8P4R_5%
EMI@
HDA_BIT_C LK
HDA_SYNC
ME_EN
HDA_RST #
< To Enable ME Override >
UC1G
HDA_SYNC
HDA_BIT_C LK
ME_EN[33]
HDA_SDIN0[35]
HDA_SPK R[35]
ME_EN
HDA_RST #
HDA_SPK R
BA22
AY22
BB22
BA21
AY21
AW22
AY20
AW20
AK7
AK6
AK9
AK10
AW5
J5
H5
D7
D8
C8
AUDIO
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
SKL-U_BG A1356
@
SKL-U
7 OF 20
Rev_1.0
SDIO / SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
RC109 200_040 2_1%@
12
+3VS
1 2
RC33 2.2K_0402_5 %
SPKR (Internal Pull Down):
B B
TOP Swap Override
0 = Disable TOP Swap mode. ==> Default
1 = Enable TOP Swap Mode.
HDA_SPK R
@
UC1I
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
SKL-U_BG A1356
@
CSI-2
SKL-U
9 OF 20
Rev_1.0
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
RC117 100_040 2_1%@
RC116 200_040 2_1%@
12
12
A A
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Custom
Custom
Custom
Date : Sheet
Date : Sheet
2
Date : Sheet
Compal Electronics, Inc.
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
LA-D562P
LA-D562P
Monday, April 10, 201 7
Monday, April 10, 201 7
Monday, April 10, 201 7
LA-D562P
8
8
8
1
52
52
52
o f
o f
o f
2.0
2.0
2.0
5
Aditya11ttt
Aditya11ttt
+3VS
RPC6
EC_SCI#
18
WLANCLK_R EQ#
27
36
LANCLK_REQ#
D D
RC61 10K_0402_5 %UMA@
RC55 10K_0402_5 %
+3VL_RTC
C C
+3VALW
ESD
B B
+3VALW
45
10K_0804_8 P4R_5%
1 2
1 2
ESD@
CC97 100P_0402_ 50V8J
ESD@
CC94 100P_0402_ 50V8J
ESD@
CC95 100P_0402_ 50V8J
RC47 1K_0402_5%
GPUCLK_REQ#
PX@
1 2
RC36 20K_0201_5 %
1 2
CC6 1U_0402_6 .3V6K
1 2
RC37 20K_0402_5 %
1 2
CC7 1U_0402_6 .3V6K
1 2
CLRP2 SHORT PADS
1 2
RC39 1M_0402_ 5%
RPC7
PCH_PWR OK
18
EC_RSMRST#
27
LAN_WAKE#
36
SYS_RESET#
45
10K_0804_8 P4R_5%
1 2
1 2
1 2
1 2
SYS_RESET#
EC_RSMRST#
SYS_PWROK
WAKE#
EC_SCI# [5,33]
SOC_SRTCRS T#
SOC_RTCRST #
CLR CMOS
SM_INTRUDER#
RC38
1 2
0_0402_5%
RS@
EC_RSMRST# PCH_D PWROK
Only For Power Sequence Debug
4
DGPU
LAN
NGFF WL+BT(KEY E)
EC_CLEAR_CMOS # [33]
1 2
RC115 0_0402_ 5%@
3
UC1J
SOC_PLTRST #
TC7SH08FU F_SSOP5
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKL-U_BGA1356
@
1 2
RC42 0_0402_5%RS@
+3VS
5
UC4
1
P
B
2
A
G
3
@
CLK_PCIE_GPU#[20]
CLK_PCIE_GPU[20]
GPUCLK_REQ#[21]
CLK_PCIE_LAN#[34]
CLK_PCIE_LAN[34]
LANCLK_REQ#[34]
CLK_PCIE_WL AN#[30]
CLK_PCIE_WL AN[30]
WLANCLK_R EQ#[30 ]
GPUCLK_REQ#
LANCLK_REQ#
WLANCLK_R EQ#
< PCH PLTRST Buf f er >
SKL-U
CLOCK SIGNALS
10 OF 20
4
Y
12
RC44
100K_0402_5%
12
CC8
100P_0402_ 50V8J
ESD@
PCIRST# [2 0,30,33,34]
Rev_1.0
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
2
SUSCLK
SOC_XTAL24_IN
SOC_XTAL24_OUT
XCLK_BIASREF
SOC_RTCX1
SOC_RTCX2
SOC_SRTCRS T#
SOC_RTCRST #
SUSCLK [30]
1
SOC_XTAL24_IN
SOC_XTAL24_OUT
YC1 need to be replaced by
38.4MHz (30ohm ESR) XTAL for Cannonlake-U
XCLK_BIASREF
Follow 546765_2014WW48_Skylake_MOW_R ev_1_0
Stuff 2.7k ohm(RC35) PU for Skylake-U
Stuff 60.4 ohm(RC110) PD for Cannonlake-U
1 2
RC34 1M_0402_ 5%
YC1
24MHZ_12PF_7 V24000020
3
15P_0402_50V8J
3
GND
CC4
4
1 2
RC35 2.7K_0402_1 %
1 2
@
RC110 60.4_040 2_1%
SOC_RTCX2
SOC_RTCX1
1 2
RC41 10M_0402_5%
1 2
32.768KHZ 9PF 20 PPM 9H03280012
1
CC9
4.7P_0402_5 0V8B
2
YC2
GND
2
1
1
+1.0V_CLK5_F2 4NS
1
2
15P_0402_50V8J
CC10
4.7P_0402_5 0V8B
CC5
SKL-U
11 OF 20
Rev_1.0
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
PM_SLP_S0#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
SLP_WLAN#
PM_SLP_A#
PBTN_OUT#
AC_PRESENT
PM_BATLOW#
SM_INTRUDER#
SOC_VRALERT#
T130TP@
PM_SLP_S3# [33]
PM_SLP_S4# [33,40 ,42]
T135TP@
T133TP@
T134TP@
1 2
RC103 0_0402_ 5%@
DVT delete 10K PU for DDR layout
PBTN_OUT# [33]
VCIN1_AC_IN [21,33,40]
PM_BATLOW#
RC46 8.2K_0402_5 %
SOC_VRALERT#
RC50 10K_0402_5 %
1 2
1 2
@
+3VALW
EC_RSMRST#[33]
PCH_PWR OK[33]
SYS_PWROK[33]
T132 TP@
T138 TP@
SOC_PLTRST #
SYS_RESET#
EC_RSMRST#
H_CPUPW RGD
EC_VCCST_PG
SYS_PWROK
PCH_PWR OK
PCH_DPW ROK
SUSWARN#
WAKE#
LAN_WAKE#
AN10
AY17
A68
B65
BA20
BB20
AR13
AP11
BB15
AM15
AW17
AT15
UC1K
SYSTEM POWER MANAGEMENT
GPP_B13/PLTRST#
B5
SYS_RESET#
RSMRST#
PROCPWRGD
VCCST_PWRGD
B6
SYS_PWROK
PCH_PWROK
DSW_PWROK
GPP_A13/SUSWARN#/SUSPWRDNACK
GPP_A15/SUSACK#
WAKE#
GPD2/LAN_WAKE#
GPD11/LANPHYPC
GPD7/RSVD
SKL-U_BGA1356
@
From EC (Open-Drain)
A A
VCCST_PWR GD[33]
+1.0V_VCCST
12
RC52
1K_0402_5%
1 2
RC53 60.4_0402_1 %
EC_VCCST_PG
5
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2014/05/19 2015/12/31
2014/05/19 2015/12/31
2014/05/19 2015/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SKL-U(5/12)CLK,PM,GPIO
SKL-U(5/12)CLK,PM,GPIO
SKL-U(5/12)CLK,PM,GPIO
Size D ocument Number Re v
Size D ocument Number Re v
Size D ocument Number Re v
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
Date : Sheet of
LA-D562P
LA-D562P
LA-D562P
1
9 52Monday, April 10, 2017
9 52Monday, April 10, 2017
9 52Monday, April 10, 2017
2.0
2.0
2.0
5
Aditya11ttt
Aditya11ttt
4
3
2
1
SKL KBL
Micron MT40A512M16HA-083E:A
Micron MT40A512M16JY-083E:B
D D
GSPI0_MOSI (Internal Pull Down):
No Reboot
0 = Disab le No Reboot mode. ==> Default
1 = Enab le No Reboot Mode. (PCH will dis able the TCO
Timer system reboot feature). This func tion is useful
when running ITP/XDP.
GSPI1_MOSI (Internal Pull Down):
Boot BIOS Stra p Bit
0 = SPI Mode ==> Default
+3VS
C C
B B
1 = LPC Mode
1 2
@
RC59 2.2K_0402_5%
1 2
@
RC60 2.2K_0402_5%
1 2
RC67 49.9K_0402_1%
1 2
RC66 49.9K_0402_1%
UART_2_CT XD_DRXD
GSPI0_MOSI
GSPI1_MOSI
RAM vender
Samsung K4A8G165WB-BCPB
WLBT_OFF#[30]
UART_2_CRXD_ DTXD[30]
UART_2_CT XD_DRXD[30]
OBRAM_ID0
OBRAM_ID1
0 0
0
1 1
OBRAM_ID0
OBRAM_ID1
GSPI0_MOSI
GSPI1_MOSI
WLBT_OFF#
UART_2_CRXD_ DTXDUART_2_CRXD_ DTXD
UART_2_CT XD_DRXD
1
01
AM5
AN7
AP5
AN5
AB1
AB2
AB3
AD1
AD2
AD3
AD4
AH9
AH10
AH11
AH12
AF11
AF12
Samsung K4A8G165WB-BCRC
Micron MT40A512M16JY-083E:B
Hynix H5AN8G6NAFR-UHC
+3VS +3VS
RC135
10K_0402_5 %
X76RAM@
RC136
10K_0402_5 %
X76RAM@
UC1F
AN8
AP7
AP8
AR7
W4
U7
U6
U8
U9
LPSS ISH
GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
SKL-U_BGA1356
@
RAM vender
12
12
12
RC133
10K_0402_5 %
X76RAM@
12
RC134
10K_0402_5 %
X76RAM@
OBRAM_ID0
OBRAM_ID1OBRAM_ID0
SKL-U
Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
6 OF 20
OBRAM_ID1
0 0
0
1 1
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
1
01
Rev_1.0
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
DGPU_PWR _EN
AC1
DGPU_HOLD_R ST#
AC2
DGPU_PWR OK
AC3
DGPU_PRSNT #
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
DGPU_PWR _EN [22,33,48]
DGPU_HOLD_R ST# [20]
DGPU_PWR OK [48 ]
Funct i on
UMA
DIS
+3VS
1 2
RC128 10K_0402_ 5%UMA@
1 2
RC129 10K_0402_ 5%
GPPA12
PX@
1
0
DGPU_PWR _EN
DGPU_HOLD_R ST#
DGPU_PWR OK
WLBT_OFF#
DGPU_PRSNT# PD for DIS SKU
DGPU_PRSNT #
1 8
2 7
3 6
4 5
+3VS
RPC8
10K_0804_8 P4R_5%
A A
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2014/05/19 2015/12/31
2014/05/19 2015/12/31
2014/05/19 2015/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size D ocument Number Re v
Size D ocument Number Re v
Size D ocument Number Re v
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
2
Date : Sheet of
Compal Electronics, Inc.
SKL-U(6/12)GPIO,I2C,GSPI
SKL-U(6/12)GPIO,I2C,GSPI
SKL-U(6/12)GPIO,I2C,GSPI
LA-D562P
LA-D562P
LA-D562P
1
10 52Monday, April 10, 2017
10 52Monday, April 10, 2017
10 52Monday, April 10, 2017
2.0
2.0
2.0
5
Aditya11ttt
Aditya11ttt
4
3
2
1
UC1H
D D
PCIE_CRX_GTX_N1[20]
PCIE_CRX_GTX_P1[20]
PCIE_CTX_ C_GRX_N1[20]
PCIE_CTX_ C_GRX_P1[20]
PCIE_CRX_GTX_N2[20]
PCIE_CRX_GTX_P2[20]
PCIE_CTX_ C_GRX_N2[20]
dGPU
LAN
C C
NGFF WLAN+BT
HDD
ODD
When PCIE8/SATA1A is used
B B
as SATA Port 1 (ODD), then
PCIE11/SATA1B (M.2 SSD)
cannot be used as SATA
Port 1.
PCIE_CTX_ C_GRX_P2[2 0]
PCIE_CRX_GTX_N3[20]
PCIE_CRX_GTX_P3[20]
PCIE_CTX_ C_GRX_N3[20]
PCIE_CTX_ C_GRX_P3[2 0]
PCIE_CRX_GTX_N4[20]
PCIE_CRX_GTX_P4[20]
PCIE_CTX_ C_GRX_N4[20]
PCIE_CTX_ C_GRX_P4[20]
PCIE_CRX_ DTX_N5[34]
PCIE_CRX_ DTX_P5[34]
PCIE_CTX_ C_DRX_N5[3 4]
PCIE_CTX_ C_DRX_P5[34]
PCIE_CRX_ DTX_N6[30]
PCIE_CRX_ DTX_P6[30]
PCIE_CTX_ DRX_N6[30]
PCIE_CTX_ DRX_P6[30]
SATA_CR X_DTX_N0[2 9]
SATA_CR X_DTX_P0[29]
SATA_CT X_DRX_N0[2 9]
SATA_CT X_DRX_P0[29]
SATA_CR X_DTX_N1[2 9]
SATA_CR X_DTX_P1[29]
SATA_CT X_DRX_N1[2 9]
SATA_CT X_DRX_P1[29]
1 2
CC11 0.1U_020 1_10V6KPX@
1 2
CC14 0.1U_020 1_10V6KPX@
1 2
CC15 0.1U_020 1_10V6KPX@
1 2
CC16 0.1U_020 1_10V6KPX@
1 2
CC17 0.1U_020 1_10V6KPX@
1 2
CC18 0.1U_020 1_10V6KPX@
1 2
CC101 0.1U_020 1_10V6KPX@
1 2
CC102 0.1U_020 1_10V6KPX@
1 2
CC19 0.1U_0201_10V6 K
1 2
CC20 0.1U_0201_10V6 K
1 2
RC71 100_0402_1 %
T147 TP@
T148 TP@
PCIE_CRX_ GTX_N1
PCIE_CRX_ GTX_P1
PCIE_CTX_ GRX_N1
PCIE_CTX_ GRX_P1
PCIE_CRX_ GTX_N2
PCIE_CRX_ GTX_P2
PCIE_CTX_ GRX_N2
PCIE_CTX_ GRX_P2
PCIE_CRX_ GTX_N3
PCIE_CRX_ GTX_P3
PCIE_CTX_ GRX_N3
PCIE_CTX_ GRX_P3
PCIE_CRX_ GTX_N4
PCIE_CRX_ GTX_P4
PCIE_CTX_ GRX_N4
PCIE_CTX_ GRX_P4
PCIE_CRX_ DTX_N5
PCIE_CRX_ DTX_P5
PCIE_CTX_ DRX_N5
PCIE_CTX_ DRX_P5
PCIE_CRX_ DTX_N6
PCIE_CRX_ DTX_P6
PCIE_CTX_ DRX_N6
PCIE_CTX_ DRX_P6
PCIE_RCOM PN
PCIE_RCOM PP
XDP_PRD Y#
XDP_PRE Q#
PCIE / USB3 / SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKL-U_BG A1356
@
SKL-U
USB2
8 OF 20
SSIC / USB3
USB3_2_RXN / SSIC_RXN
USB3_2_RXP / SSIC_RXP
USB3_2_TXN / SSIC_TXN
USB3_2_TXP / SSIC_TXP
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
Rev_1.0
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_3_RXN
USB3_3_RXP
USB3_3_TXN
USB3_3_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USB20_N 2
USB20_P 2
USB20_N 4
USB20_P 4
USB20_N 5
USB20_P 5
USB20_N 6
USB20_P 6
USB20_N 7
USB20_P 7
USB2_CO MP
USB2_ID
USB2_VB USSENSE
USB_OC0 #
USB_OC1 #
USB_OC2 #
USB_OC3 #
PCH_SAT ALED#
USB3_RX _N2 [32]
USB3_RX _P2 [32 ]
USB3_TX _N2 [32]
USB3_TX _P2 [32]
USB2/3 MB(Left)
USB20_N 2 [32]
USB20_P 2 [32 ]
USB20_N 4 [32]
USB20_P 4 [32 ]
USB20_N 5 [27]
USB20_P 5 [27 ]
USB20_N 6 [36]
USB20_P 6 [36 ]
USB20_N 7 [30]
USB20_P 7 [30 ]
1 2
RC70 113_040 2_1%
1 2
RC62 1K_0402 _5%
1 2
RC63 1K_0402 _5%
USB_OC0 # [32]
EC_W L_OFF# [30]
EC pin 72 change to PCH GPP_E5
need to check with BIOS
USB 3.0
USB 2.0
Camera
Card Reader
NGFF WLAN+BT
USB_OC3 #
USB_OC0 #
USB_OC1 #
USB_OC2 #
RPC9
10K_080 4_8P4R_5%
+3VALW
18
27
36
45
+3VS
A A
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
SKL-U(7/12)PCIE,USB,SATA
SKL-U(7/12)PCIE,USB,SATA
SKL-U(7/12)PCIE,USB,SATA
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Custom
Custom
Custom
Date : Sheet
Date : Sheet
2
Date : Sheet
PCH_SAT ALED#
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1 2
RC112 10K_0402_5%
LA-D562P
LA-D562P
LA-D562P
1
2.0
2.0
2.0
11 52Monday, April 10, 2017
11 52Monday, April 10, 2017
11 52Monday, April 10, 2017
o f
o f
o f
5
Aditya11ttt
Aditya11ttt
4
3
2
1
+1.2V
+5VALW
+1.0VALW TO +1.0V_VCCST
D D
1 2
SYSON[33,37,42]
SUSP#[33,37 ,42]
RC74 0_0402_5%RS@
1 2
RC75 0_0402_5%RS@
0.1U_0402_25V6
12
@
+1.8VALW TO +1.8VS
C C
+1.0VALW
1 2
1 2
+1.0V_VC CST
0.1U_0201_10V6K
CC23
1
2
Follow 543977_SKL_PDDG_Rev0_91
CC24 10PF ->22us(Spe c:<= 65us)
+1.8VS
0.1U_0201_10V6K
CC27
1
2
+1.0VS_V CCIO
+1.0V_VC CST
1U_0402_6.3V6K
CC21
1
2
0.1U_0402_25V6
CC89
CC88
12
@
@
+1.8VALW
@
1U_0402_6.3V6K
I(Max) : 0.16 A(+1.0V_VCCST)
CC22
1
RON(Max) : 25 mohm
V drop : 0.004 V
2
UC5
1
VIN1
2
EN_1.0V_ VCCSTU
EN_1.8VS
1U_0402_6.3V6K
CC26
1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
EM5209V F_DFN14_2X3
I(Max) : 0.2 A(+1.8VS)
RON(Max) : 25 mohm
V drop : 0.005 V
VOUT1
VOUT1
CT1
GND
CT2
VOUT2
VOUT2
GPAD
14
13
12
11
10
9
1000P_0 402_50V7K
8
15
CC24
10P_040 2_50V8J
CC25
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
AL23
A18
A22
K20
K21
SKL-U
UC1N
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20
VCCPLL_K21
SKL-U_BG A1356
@
CPU POWER 3 OF 4
VCCIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20
VSSIO_SENSE
Rev_1.0
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
+1.0VS_V CCIO
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
+VCCSA
VSSSA_S ENSE
VCCSA_S ENSE
Trace Lengt h Match < 25 mils
VSSSA_S ENSE [45]
VCCSA_S ENSE [45]
+1.0VALW TO +1.0VS_VCCIO
+5VALW
@
B B
SUSP#
1 2
RC81 0_0402_5%RS@
+1.0VALW
0.1U_0201_10V6K
CC30
1
2
1U_0402_6.3V6K
CC32
1
2
12
@
I(Max) : 3.04 A(+1.0VS_VCCIO)
RON(Max) : 6.2 mohm
V drop : 0.019 V
UC6
1
VIN1
2
VIN2
7
VIN thermal
3
VBIAS
4
CC90
ON
TPS2296 1DNYR_WSON8
0.1U_0402_25V6
VOUT
GND
+1.0VS_V CCIO_STG
6
5
1 2
RC79 0_0805_5%RS@
+1.0VS_V CCIO
1
CC33
@
0.1U_020 1_10V6K
2
+1.0V_VC CST
1U_0402_6.3V6K
1
2
Close to A18 Close to K20 Close to A22
1U_0402_6.3V6K
1
CC34
CC28
2
+1.0VS_V CCIO
BSC SidePSC Side
1U_0402_6.3V6K
1
@
2
CC35
+1.0VS_V CCIO
PSC SideBSC Side BSC SidePSC Side
1U_0402_6.3V6K
10U_0603_6.3V6M
1
1
CC36
@
@
A A
2
2
CC37
1U_0402_6.3V6K
CC38
1
@
2
1U_0402_6.3V6K
1
CC39
2
1U_0402_6.3V6K
1
2
Close to CPUUnderneath CPU
5
4
1U_0402_6.3V6K
1
CC40
2
1U_0402_6.3V6K
1
CC41
CC42
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
3
+1.2V
BSC Side
1U_0402_6.3V6K
1
2
1
CC29
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1U_0402_6.3V6K
10U_0603_6.3V6M
1
CC43
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
CC45
CC44
2
2
Close to CPUClose to AM40 Underneath CPUClose to AL23
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC47
CC46
@
2
2
1U_0402_6.3V6K
10U_0603_6.3V6M
1
CC48
@
2
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Custom
Custom
Custom
Date : Sheet
Date : Sheet
Date : Sheet
CC50
CC49
1
@
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SKL-U(8/12)Power
SKL-U(8/12)Power
SKL-U(8/12)Power
LA-D562P
LA-D562P
LA-D562P
1
12 52Monday, April 10, 2017
12 52Monday, April 10, 2017
12 52Monday, April 10, 2017
o f
o f
o f
2.0
2.0
2.0
5
Saf t y s uggest i on r e move EE s i de , Keep PWR si de
Aditya11ttt
Aditya11ttt
4
3
2
1
D D
C C
B B
Follow 543016_SKL_U_Y_PDG_1_0
+1.0VALW
LC1
MURATA BLM15EG22 1SN1D
1 2
SM01000HC 00
RF@
R_0402
Follow 543016_SKL_U_Y_PDG_1_0
1 2
LC2 0_0 603_5%RS@
Follow 543016_SKL_U_Y_PDG_1_0
1 2
RC85 0_0603_5%RS@
Follow 543016_SKL_U_Y_PDG_1_0
1 2
RC87 0_0603_5%RS@
Follow 543016_SKL_U_Y_PDG_1_0
1 2
RC91 0_0603_5%RS@
+1.0V_APLL
1
CC52
0.1U_0201_ 10V K X5R
2
+1.0V_AMPHYPLL
1U_0402_6.3V6K
22U_0603_6.3V6M
CC58
1
1
@
@
2
2
+1.0V_CLK5_F2 4NS
22U_0603_6.3V6M
1
@
2
+1.0V_CLK4_F1 00OC
22U_0603_6.3V6M
1
@
2
+1.0V_CLK6_24 TBT
22U_0603_6.3V6M
1U_0402_6.3V6K
1
1
CC84
@
@
2
2
2
1
1U_0402_6.3V6K
22U_0603_6.3V6M
CC76
1
2
+1.0VALW
DCPDSW
UC1O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB_1P0
SKL-U_BGA1356
@
Delete CC77 , CC78 for DDR layout modify
+3VALW
1U_0402_6.3V6K
1
CC80
@
2
SKL-U
CPU POWER 4 OF 4
15 OF 20
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
1U_0402_6.3V6K
1
CC81
2
Close to AK17Close to T16Close to Y1 6Close to AG15
Rev_1.0
AK15
AG15
Y16
Y15
T16
AF16
VCCPGPPF
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
DCPRTC
A14
VCCCLK1
K19
VCCCLK2
L21
VCCCLK3
N20
VCCCLK4
L19
VCCCLK5
A10
VCCCLK6
AN11
AN13
0.1U_0201_10V6K
1
CC79
2
+1.8VALW
+3VALW
+3V_1.8V_PGPPA
VCCPGPPF support 1.8V only
+1.0VALW
1 2
CC57 1U_0402_ 6.3V6K
+3VL_RTC
DCPRTC
1 2
CC62 0.1U_0201 _10V6K
+1.0V_CLK6_24 TBT
+1.0V_APLL
+1.0V_CLK4_F1 00OC
+1.0V_CLK5_F2 4NS
+1.0V_CLK6_24 TBT
RTC Bat t er y
+3VL_RTC +RTCBATT
1 2
RC90 0_0402_5%RS@
1
CC82
1U_0402_6 .3V6K
2
W=20mi ls
+1.0VALW
1 2
RC83 0_0805_5%RS@
RC84 0_0805_5%RS@
+3VALW
+1.8VALW
RC88 0_0402_5%@
+3VALW
RC89 0_0402_5%RS@
+1.8VS
RC92 0_0402_5%@
+3VS
RC93 0_0402_5%RS@
Imax : 2.57A
1 2
Imax : 3.5A
RF@
RC86
MURATA BLM15EG22 1SN1D
1 2
SM01000HC 00
R_0402
1 2
LPC 3.3V
1 2
1 2
LPC 3.3V
1 2
RF@
CC59
CC63
CC70
CC85
+1.0V_PRIM_CORE
1
2
@
+1.8V_HDA
0.1U_0201_10V K X5R
1
2
+3V_1.8V_PGPPA
+1.8VS_3VS_PGPPA
CC51 1U_0402_6 .3V6K
1U_0402_6.3V6K
1
CC54
@
2
+1.0V_MPHYGT
22U_0603_6.3V6M
1U_0402_6.3V6K
CC60
CC61
1
2
HD Audio : 3.3V or 1.5V
CC66
RF@
I2S : 1.8V or 3.3V
+3VALW
2
@
CC67
1
1U_0402_6.3V6K
Close to AJ21
Follow 543016_SKL_U_Y_PDG_1_0
+1.0VALW +3VALW + 1.8VALW
22U_0603_6.3V6M
22U_0603_6.3V6M
CC71
CC72
1
1
@
@
2
2
CC55 1U_0402_6 .3V6K
CC56 1U_0402_6 .3V6K
+1.0VALW
2
@
CC65
1
Close to AF20 Close to N18
22U_0603_6.3V6M
22U_0603_6.3V6M
CC73
1
1
@
@
2
2
1 2
@
+1.0V_PRIM_CORE
1 2
1 2
+1.0V_AMPHYPLL
1U_0402_6.3V6K
CC74
1
@
2
Close to K17
+1.0V_MPHYGT
+1.0V_APLL
+3VALW
+1.8V_HDA
+3VALW
CC68
22U_0603_6.3V6M
CC75
@
A A
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2014/05/19 2015/12/31
2014/05/19 2015/12/31
2014/05/19 2015/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SKL-U(9/12)Power
SKL-U(9/12)Power
SKL-U(9/12)Power
Size D ocument Number Re v
Size D ocument Number Re v
Size D ocument Number Re v
Custom
Custom
Custom
Date : Sheet of
Date : Sheet of
2
Date : Sheet
LA-D562P
LA-D562P
LA-D562P
13 52M onday, April 10, 2017
13 52M onday, April 10, 2017
1
13 52M onday, April 10, 2017
2.0
2.0
2.0
of
5
Aditya11ttt
Aditya11ttt
4
3
2
1
UC1L
A30
VCC_A30
A34
VCC_A34
D D
Delete GT3 Power trace
For GT3 SKU
C C
T157 TP@
T158 TP@
VCCOPC_ SENSE
VSSOPC_ SENSE
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
AK32
AB62
G61
AC63
AE63
AE62
AG62
AL63
AJ62
A39
A44
K32
P62
V62
H63
SKL-U_BG A1356
@
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD
RSVD
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
SKL-U
CPU POWER 1 OF 4
12 OF 20
Rev_1.0
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
Trace Lengt h Match < 25 mils
VCCCORE _SENSE [45]
SOC_SVID_ ALERT#
VR_SVID_C LK
VR_SVID_D ATA
ALERT sig nal must be routed between CLK and DATA sign als
VSSCORE _SENSE [45]
VR_SVID_C LK [45]
+1.0VS_V CCIO
+VCCGT +VCCGT+VCCCOR E +V CCCORE
SVID ALERT
B B
+1.0V_VC CST
12
RC94
56_0402 _5%
Place the PU
resistors close to CPU
VCCGT_S ENSE[4 5]
VSSGT_S ENSE[45]
Trace Lengt h Match < 25 mils
VCCGT_S ENSE
VSSGT_S ENSE
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
UC1M
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
SKL-U_BG A1356
@
SKL-U
CPU POWER 2 OF 4
13 OF 20
Rev_1.0
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
VCCGTX_ SENSE
VSSGTX_ SENSE
For GT3 SKU
T161 T P@
T162 T P@
SOC_SVID_ ALERT#
1 2
RC95 220_0402_5%
VR_ALER T# [45]
(To VR )
+1.0V_VC CST
SVID DATA
Place the PU
resistors close to CPU
12
RC96
100_040 2_5%
VR_SVID_D ATA
A A
5
VR_SVID_D ATA [45]
4
(To VR )
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Custom
Custom
Custom
Date : Sheet
Date : Sheet
2
Date : Sheet
SKL-U(10/12)Power,SVID
SKL-U(10/12)Power,SVID
SKL-U(10/12)Power,SVID
LA-D562P
LA-D562P
LA-D562P
1
2.0
2.0
2.0
14 52Monday, April 10, 2017
14 52Monday, April 10, 2017
14 52Monday, April 10, 2017
o f
o f
o f
5
Aditya11ttt
Aditya11ttt
4
3
2
1
D D
C C
B B
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A67
A70
AJ4
AL2
AL4
A5
UC1P
SKL-U_BG A1356
@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U
GND 1 OF 3
16 OF 20
Rev_1.0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
UC1Q
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
SKL-U_BG A1356
@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL-U
GND 2 OF 3
17 OF 20
Rev_1.0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
UC1R
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
SKL-U_BG A1356
@
SKL-U
GND 3 OF 3
18 OF 20
Rev_1.0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
A A
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
2014/05/ 19 2015/12/ 31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Re v
Size Document N umber Re v
Size Document N umber Re v
Custom
Custom
Custom
Date : Sheet
Date : Sheet
2
Date : Sheet
SKL-U(11/12)GND
SKL-U(11/12)GND
SKL-U(11/12)GND
LA-D562P
LA-D562P
LA-D562P
1
2.0
2.0
2.0
15 52Monday, April 10, 2017
15 52Monday, April 10, 2017
15 52Monday, April 10, 2017
o f
o f
o f
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