LeCroy LC684DM, LC684DL, LC684D, LC684DXL Service manual

1. Warranty and Product Support

It is recommended that you thoroughly inspect the contents of the oscilloscope
packaging immediately upon receipt. Check all contents against the packing
list/invoice copy shipped with the instrument. Unless LeCroy is notified promptly of
any missing or damaged item, responsibility for its replacement cannot be accepted.
Contact your nearest LeCroy Customer Service Center or national distributor
immediately (see chapter 2 for contact numbers).

1.1 Warranty

LeCroy warrants its oscilloscope products for normal use and operation within
specifications for a period of three years from the date of shipment. Calibration each
year is recommended to ensure in-spec. performance. Spares, replacement parts
and repairs are warranted for 90 days. The instrument's firmware has been
thoroughly tested and is thought to be functional, but is supplied without warranty of
any kind covering detailed performance. Products not made by LeCroy are covered
solely by the warranty of the original equipment manufacturer.

Under the LeCroy warranty, LeCroy will repair or, at its option, replace any product
returned within the warranty period to a LeCroy authorized service center. However,
this will be done only if the product is determined after examination by LeCroy to be
defective due to workmanship or materials, and not to have been caused by misuse,
neglect or accident, or by abnormal conditions or operation.

1.2 Product Assistance

Note: This warranty replaces all other warranties, expressed or implied, including
but not limited to any implied warranty of merchantability, fitness, or adequacy for any
particular purpose or use. LeCroy shall not be liable for any special, incidental, or
consequential damages, whether in contract or otherwise. The client will be
responsible for the transportation and insurance charges for the return of products to
the service facility. LeCroy will return all products under warranty with transport
prepaid.

Help on installation, calibration, and the use of LeCroy equipment is available from
the LeCroy Customer Service Center in your country.

1.3 Maintenance Agreements

LeCroy provides a variety of customer support services under Maintenance Agreements.
Such agreements give extended warranty and allow clients to budget maintenance costs
after the initial three-year warranty has expired. Other services such as installation,
training, enhancements and on-site repairs are available through special supplemental
support agreements.

Read this First 1-1

1.4 Stay i n g Up t o D a t e

LeCroy is dedicated to offering state-of-the-art instruments, by continually refining and
improving the performance of LeCroy products. Because of the speed with which
physical modifications may be implemented, this manual and related documentation may
not agree in every detail with the products they describe. For example, there might be
small discrepancies in the values of components affecting pulse shape, timing or offset,
and — infrequently — minor logic changes. However, be assured the scope itself is in full
order and incorporates the most up-to-date circuitry. LeCroy frequently updates
firmware and software during servicing to improve scope performance, free of
charge during warranty. You will be kept informed of such changes, through new or
revised manuals and other publications.

Nevertheless, you should retain this, the original manual, for future reference
to your scope’s unchanged hardware specifications.

1.5 Service and Repair

Please return products requiring maintenance to the Customer Service Department in
your country or to an authorized service facility. The customer is responsible for
transportation charges to the factory, whereas all in-warranty products will be returned to
you with transportation prepaid. Outside the warranty period, you will need to provide us
with a purchase order number before we can repair your LeCroy product. You will be
billed for parts and labor related to the repair work, and for shipping.

1.6 How to return a Product

Contact the nearest LeCroy Service Center or office to find out where to return the
product. All returned products should be identified by model and serial number. You
should describe the defect or failure, and provide your name and contact number. In the
case of a product returned to the factory, a Return Authorization Number (RAN) should
be used.

Return shipments should be made prepaid. We cannot accept COD (Cash On
Delivery) or Collect Return shipments. We recommend air-freighting.

It is important that the RAN be clearly shown on the outside of the shipping package
for prompt redirection to the appropriate LeCroy department.

1.7 What Comes with Your Scope

1-2 Read this First

The following items are shipped together with the standard configuration of this
oscilloscope:

• Front Scope Cover

• 10:1 10 MΩ PP005 Passive Probe — one per channel

• PP096 8GS/s adapter

• Two 250 V Fuses, AC Power Cord and Plug

• Operator’s Manual , Remote Control Manual, Hands-On Guide

• Performance Certificate or Calibration Certificate, Declaration of Conformity

Note: Wherever possible, please use the original shipping carton. If a substitute
carton is used, it should be rigid and packed so that that the product is surrounded
by a minimum of four inches or 10 cm of shock-absorbent material.

2. General Information

2.1 Product Assistance

Help on installation, calibration, and the use of LeCroy equipment is available from your
local LeCroy office, or from LeCroy’s

• Customer Care Center, 700 Chestnut Ridge Road, Chestnut Ridge,

New York 10977–6499, U.S.A., tel. [phone]

• European Service Center, 2, rue du Pré-de-la-Fontaine, 1217 Meyrin 1,
Geneva Switzerland, tel. [phone].

• LeCroy Japan Corporation, Sasazuka Center Bldg – 6
Sasazuka, Shibuya-ku, Tokyo Japan 151-0073, tel. [phone]

2.2 Installation for Safe and Efficient Operation
Operating Environment

th

floor, 1-6, 2-Chome,

The oscilloscope will operate to its specifications if the environment is maintained within
the following parameters:

Temperature................5 to 40 °C (41 to 104 °F) rated.

Humidity.......................Maximum relative humidity 80 % RH (non-condensing) for

temperatures up to 31 °C decreasing linearly to 50 % relative humidity
at 40 °C

Altitude.........................2000 m (6560 ft)

The oscilloscope has been qualified to the following EN61010-1 category:

Installation (Overvoltage) CategoryII

Pollution Degree.............................2

Safety Symbols

manual, they have the following meanings

Where these symbols or indications appear on the front or rear panels, and in this

:

General Information 2-1

.............................CAUTION: Refer to accompanying documents (for Safety-related

information). See elsewhere in this manual wherever the symbol is
present,as indicated in the Table of Contents.

.............................CAUTION: Risk of electric shock

..............................On (Supply)

[ Off (Supply)

.............................. Earth (Ground) Terminal

............................Protective Conductor Terminal

...............................Earth (Ground) Terminal on BNC Connectors

WARNING...................Denotes a hazard. If a WARNING is indicated on the instrument, do

not proceed until its conditions are understood and met.

Any use of this instrument in a

WARNING

body. Users who connect a LeCroy oscilloscope directly to a person do so at their own
risk.

The oscilloscope has not been designed to make direct measurements on the human

manner not specified by the
manufacturer may impair the
instrument’s safety protection.

2-2 General Information

Power Requirements

The oscilloscope operates from a 115 V (90 to 132 V) or 220 V (180 to 250 V) AC
power source at 45 Hz to 66 Hz. No voltage selection is required, since the instrument
automatically adapts to the line voltage present.

The power supply of the oscilloscope is protected against short-circuit and
overload by means of two 6.3 A/250 V AC, “T” rated fuses (size: 5 X 20 mm),
located above the mains plug. Disconnect the power cord before inspecting or
replacing a fuse. Open the fuse box by inserting a small screwdriver under the
plastic cover and prying it open.

For continued fire protection at all line voltages, replace only with fuses of the
specified type and rating (T 6.3 A/250 V).

Maintain the ground line to avoid an electric shock.
None of the current-carrying conductors may exceed 250 V rms with respect to ground

potential. The oscilloscope is provided with a three-wire electrical cord containing a
three-terminal polarized plug for mains voltage and safety ground connection.

The plug's ground terminal is connected directly to the frame of the unit. For adequate
protection against electrical hazard, this plug must be inserted into a mating outlet
containing a safety ground contact.

Cleaning And Maintenance

Maintenance and repairs should be carried out exclusively by a LeCroy technician (see
Chapter 2). Cleaning should be limited to the exterior of the instrument only, using a
damp, soft cloth. Do not use chemicals or abrasive elements. Under no circumstances
should moisture be allowed to penetrate the oscilloscope. To avoid electric shocks,
disconnect the instrument from the power supply before cleaning.

Risk of electrical shock:

CAUTION

Power On
Connect the oscilloscope to the power outlet and switch it on by pressing the power

switch located on the rear panel. After the instrument is switched on, auto-calibration is
performed and a test of the oscilloscope's ADCs and memories is carried out. The full
testing procedure takes approximately 10 seconds, after which time a display will
appear on the screen.

No user serviceable parts
inside. Leave repair to
qualified personnel.

General Information 2-3

2-4 General Information

3. LC684D, DM, DL & DXL Specifications

3.1 Signal Capture

Acquisition System
Bandwidth (-3 dB):

@ 50Ω: DC to 1.5 GHz
@ 1 MΩ DC: Bandwidth dependant on probe used
No. of Channels: 4
Sample Rate: LC684D/M/L/XL: 2 GS/s (4 ch), 4 GS/s (2 ch), 8GS/s (1 ch)
Sensitivity:
50Ω : 2 mV/div to 1 V/div
1MΩ : 2 mV/div to 2 V/div
Scale factors: Choice of over 12 probe attenuation factors selectable via front
panel menus.
Offset Range:

2.0 - 4.99 mV/div: ±400 mV

5.0 - 99 mV/div (50Ω only) : ±1 V

5.0 - 100 mV/div (1 MΩ only) : ±1 V

0.1 - 1.0V/div (50Ω only): ±10 V

102 mv - 2.0V/div (1 MΩ only): ±100 V
±20 V across the whole sensitivity range when using the AP020/AP022 FET probe.
DC Accuracy: typical ± 2% of full scale + 1% offset setting.
Vertical Resolution: 8 bits.
Bandwidth Limiter: 25 MHz, or 200MHz user selectable
Input Coupling: AC ( > 10Hz typ.), DC, GND.
Input Impedance: 10MΩ//11pF (system capacitance using PP005) or 50 Ω ±1.25%.
Max Input: 50Ω: ±5V DC (500mW) or 5V RMS.
1MΩ: 100 V (DC+ peak AC ≤10 kHz).

Acquisition System Configuration

Active

Channels

4
2
1

Maximum

Sample

Rate

2 GS/s 100 K 500 K 2 M 4 M
4 GS/s 250 K 1 M 4 M 8 M
8 GS/s 500 K 2 M 8 M 16 M

LC684D LC684DM LC684DL LC684DXL

Maximum Record Length

Specifications 3-1

3.2 Acquisition Modes

Random Interleaved Sampling (RIS): 25GS/s.
For repetitive signals from 200 ps/div to 1 µs/div.

Single shot: For transient and repetitive signals from 0.5 ns/div (1 channels).
1 ns/div (2 Ch), 2 ns/div (4Ch)

Sequence: Stores multiple events- each of them time stamped- in segmented
acquisition memories.

Dead Time Sequence mode: Typically 30 µs
Number of segments available: LC684D: 2-1000,
LC684DM: 2-1000
LC684DL/XL: 2-6000

3.3 Timebase System

Timebases: Main and up to 4 Zoom Traces.

Time/Div Range: 500 ps/div (at 8GS/s), 1ns/div (at 4 GS/s), 2ns/div (at 2 GS/s)

to 1,000 s/div.

Clock Accuracy: ≤10 ppm.
Interpolator resolution: 10 ps.
Roll Mode in normal trigger mode: 500 ms to 1,000 s/div.

External Clock: Optional (CKTRIG) Zero crossing level DC to 500 MHz rear panel
fixed frequency clock input (<20 ns rise/falltime)

External Reference: Optional (CKTRIG) 10 MHz rear-panel input.

3.4 Triggering System

Trigger Modes: Normal, Auto, Single, and Stop.

Trigger Sources: CH1, CH2, CH3, CH4, Line, Ext, Ext/5. Slope.

Level and Coupling are unique for each source.

Slope: Positive, Negative, Bi-Slope (Window in & out)
Coupling: AC (-3db at <10Hz), DC, HF (175 MHz to 1GHz), LFREJ (>50KHz),
HFREJ (<100MHz).
Pre-trigger recording: 0 to 100% of full scale (adjustable in 1% increments).
Post-trigger delay: 0 to 10,000 divisions (adjustable in 0.1 div increments).
Holdoff by time: 2 ns to 20 s.
Holdoff by events: 1 to 99,999,999.
Internal Trigger Range: ±5 div.
Maximum Trigger Frequency: 1 GHz (DC, AC), > 1.5 GHz (HF)

EXT Trigger Max Input: 1MΩ//20pF: 100V (DC + peak AC≤ 10kHz)

50Ω ±3%: ±5 V DC (500 mW) or 5 V RMS.
EXT Trigger Range: ±0.5 V (±2.5 V with Ext/5).
Trigger Output: Optional ECL rear panel output (option CKTRIG). The calibrator
output can provide a trigger status or a Pass/Fail test output.

3-2 Specifications

3.5 Smart Trigger Types

Pattern: Trigger on the logic combination of 5 inputs - CH1, CH2, CH3, CH4 and

EXT Trigger, where each source can be defined as High, Low or Don't Care.
The Trigger can be defined as the beginning or end of the specified pattern
Signal or Pattern Width: Trigger on glitches as short as 600 ps or on pulse widths
Within/outside two limits selectable from 600 ps to 20 s.
Slew Rate: Trigger on rising, falling edges within/outside two time limits selectable
from 600 ps to 20 s.
Signal or Pattern Interval: Trigger on an interval between two limits selectable from
2ns to 20s.

Dropout: Trigger if the signal drops out for longer than a time-out from 2 ns to 20s.
Runt: Trigger on positive or negative Runts within/outside two limits selectable
from 600 ps to 20 s.
State/Edge Qualified: Trigger on any source only if a given state (or transition) has
occurred on another source. The delay between these events can be defined as a
number of events on the trigger channel or as a time interval.

TV: Allows selection of up to 1500 lines and field synchronization for PAL,
SECAM, NTSC or non-standard video
Exclusion Triggering: Trigger on intermittent faults by specifying the normal width,
period, risetime or amplitude of a signal.
The oscilloscope will trigger only on aberrations.

3.6 Autosetup

Automatically sets sensitivity, vertical offset and timebase on all display channels.
Autosetup Time: Approximately 3 seconds.

Vertical Find: Automatically sets sensitivity and offset for selected channel.

Probes

3.7

Model: One PP005 probe is supplied per channel. DC to 500 MHz typical at

probe tip, 500 V max.
Optional Probes: 2.5 Ghz FET probe AP022, 1 GHz FET probe (AP020); 1 GHz
active differential probe (AP034), 500 MHz active differential probe (AP033).

Probe calibration: Max 1 V into 1 MΩ, 500 mV into 50 Ω, frequency and amplitude
programmable, pulse or square wave selectable, rise and fall time 1 ns typical.
Alternatively, the Calibrator output can provide a trigger output or a Pass/Fail test
output.

Specifications 3-3

3.8 Display

Resolution: VGA (640X480 pixels)

waveforms. Selectable blending of grid with displayed traces.

Real-time Clock: Date, hours, minutes, seconds.

Type: Color 10.4" TFT-LCD.
Display Area: 212mm x 160mm

Controls: Menu controls for brightness and color selection.
Grid Styles: Single, Dual, Octal, XY, Single+XY, Dual+XY, and Full Screen

An enlarged view of each grid style.

Graticules: Internally generated; separate intensity control for grids and
Waveform Style: Dot-joint with optional sample point highlight or Dots-only.

Persistence Modes: Color-graded persistence and Analog Persistence, infinite or

variable with decay over time. In color-graded persistence, a color spectrum from
red through violet is used to map signal intensity. With Analog Persistence, the
brightness level of a single color denotes signal intensity. Each trace's persistence
data is stored in 64K levels.

Trace Display: Opaque or transparent mode, with overlap management.
Number of Traces: 8 (supports a mix of channels, memories or math functions).

External Monitor: Rear panel 15-pin socket for VGA compatible monitor.
Vertical Zoom: Up to 5x Vertical Expansion (50x with averaging, up to 40 µV/div

sensitivity).

Horizontal Zoom: Waveforms can be expanded to 0.4 points/division.
Auto Scroll: Use Auto Scroll to automatically "Play" the captured signal to identify

anomalies quickly and easily. With a selectable zoom expansion and scrolling
speed, you can set up Auto Scroll to match your signal viewing needs.
The scrolling speed can be adjusted during the scan to focus on the more interesting
characteristics of the signal.
"REVERSE" enables you to quickly review any part of the signal.

3.9 Rapid Signal Processing

Microprocessor: 96 MHz PowerPC 603e (LC684D, DM & DL)

192 MHz Power PC 603e (LC684DXL)

System RAM: 16 to 64 Mbytes – See table below.
Video Memory: 1 Mbyte
Persistence Data Map Memory: 16 bits per displayed pixel (64k levels).

System Memory Configurations

LC684D 16 Mbytes
LC684DM 16 Mbytes
LC684DL/DXL 64 Mbytes

3-4 Specifications

3.10 Waveform Processing

Up to four processing functions may be performed simultaneously. Functions
available are: Add, Subtract, Multiply, Divide, Negate, Identity, Summation
Averaging, Sine x/x, Integral, Derivative, Square Root, Ratio, Absolute Value and the
advanced functions listed below.

Average: Summed averaging up to one million sweeps.
Extrema: Roof, Floor, or Envelope values up to one million sweeps.
ERES: Low-Pass digital filters provide up to 11-bit vertical resolution.

Sampled data is always available, even when a trace is turned off.

FFT: Spectral Analysis with four windowing functions and FFT averaging.
Statistical Diagnostics: The Parameter Analysis package permits

in-depth diagnostics on waveform parameters. Live histogramming and trending of
any waveform parameter measurement is possible. The histogram can be
autoscaled to display the center and width of the distribution. This package is only
standard on the LC584 Series.

Internal Memory
Waveform Memory: Up to four 16-bit memories (M1, M2, M3, M4).

Zoom & Math Memory: Up to four 16-bit Waveform Processing memories

(A,B,C,D), whose length corresponds to the length of the channel acquisition
memory.
Setup Memory: Four non-volatile memories. The floppy drive and optional cards or
disks may also be used for high-capacity waveform and setup storage.

Cursor Measurements
Relative Time: A pair of arrow cursors measures time differences and voltage

differences relative to each other.
Relative Voltage: A pair of line cursors measures voltage differences relative to
each other.
Absolute Time: A cross-hair marker measures time relative to the trigger and
voltage with respect to ground.

Absolute Voltage: A reference bar measures voltage with respect to ground.
PASS/FAIL:

Pass/Fail testing allows any five items (parameters and/or masks) to be tested
against selectable thresholds. Waveform Limit Testing is performed using Masks
which may be defined either inside the instrument or by downloading templates
created on a PC. Any failure will cause pre-programmed actions, such as Hardcopy,
Save to Internal Memory, Save to mass storage device (card or disk), GPIB SRQ or
Pulse Out.

Specifications 3-5

3.11 Interfacing

Remote Control: All front-panel controls as well as all internal functions are possible

by GPIB and RS-232-C.
RS-232-C Port (Standard): Asynchronous up to 115.2 kBaud for computer/terminal
control or printer/plotter connection.
GPIB Port (Standard): (IEEE-488.2) Configurable as talker/listener for computer
control and fast data transfer.

Centronics Port (Standard): Hard copy parallel interface.
Hard copy: Screen dumps are activated by a front-panel button or via remote

control.

Supported printers:
B/W: LaserJet, DeskJet, Epson
Color: DeskJet 550C, Epson Stylus, Canon 200/600/800 series.

An optional, internal high-resolution graphics printer is also available for screen
dumps; stripchart output formats up to 2 m/div are achievable.
Hard Copy Formats: TIFF b/w, TIFF color, BMP color and
BMP compressed.
Output Formats:
The ASCII waveform output and is compatible with spreadsheets, MATLAB,
MathCad. Binary output is also available.

3.12 General

Auto-calibration Ensures specified DC and timing accuracy.
Recommended Factory Calibration Interval: 1 year
Temperature: 5° to 40°C rated accuracy (41° to 104°F).

0° to 45°C operating (32° to 113°F).

Humidity: <80% non-condensing.
Altitude: Up to 2000 m (operating), 12,000 m (non-operating).
Shock and Vibration: Conforms to selected sections of MIL-PRF-28800F,Class 3.
Power: 90-250 V AC, 45-66 Hz, 350 VA
Battery Backup: Front-panel settings maintained for two years.
Dimensions:(HWD) 10.4" x 15.65" x 17.85", 264 mm x 397 mm x 453 mm
Weight: Typ. 16 kg (35 lbs) net, typ. 24 kg (53 lbs) shipping.
Warranty: Three years.

3.13 CE Approval

EMC: Conforms to EN50081-1 (Emissions) and EN50082-1 (Immunity)
Safety: The oscilloscope has been designed to comply with EN61010-1 Installation

Category (Over-voltage category) II, 300V, Pollution degree 2.
UL and cUL approval: UL Standard: UL 3111-1; cUL Canadian Standard
CSA-C22.2 No. 1010. 1-92.

3-6 Specifications

4. Theory of Operation

4.1 Processor Board : F9601-11-16, F9601-11-64, F9602-1-64

MPC603e Processor
This processor board is based on the Power MPC603e processor.

It is a 64-bit RISC processor with 2x32kbyte cache. It features high speed
processing and fast memory accesses.

The F9601-11-x processor is set to an internal clock of 96MHz and the F9602-1-64
is set to an internal clock speed of 200 MHz. They are both used in a 32-bit mode.

There are two “worlds” on the board:

• the 32-bit world, including the main PowerPC processor, the dynamic RAM

modules and the VGA interface;

• the 8 or 16-bit world, including all other on-board peripherals, external small

peripherals and acquisition board.

A MC68150 dynamic bus sizer is used as an interface between the two worlds.

Power Supplies

The board uses three power supplies from the main acquisition board: Vcc, +15V
and -15V. Vee is wired on a connector for board test purposes.
The +15V supply OP-amps on the 9601-11 board, and +15V and -15V supply small
peripherals.
The current processor needs a 3.3V power supply, all the rest of the logic needs
5V. All signals are TTL compatible.

The PLL circuit (88916) generates a PLL_LOCK signal, which is used to clamp
the 3.3V and 2.5V references as long as the 32MHz clock is not stable. The
processor also needs to be protected against too big voltage differences between

2.5V and 3.3V (diodes on the reference).

An OP-amp and a MOSFET transistor for each power supply are used. The
reference voltages are taken directly from the 5V power supply by a resistive
divider.
Capacitors and a few diodes ensure that the supplies do not exceed dangerous
levels at power-up, nor rise too fast.

32-bit Peripherals

There are only three devices hooked up on to the processors 32-bit data bus:

• the VGA video controller

• the DRAM system

• the bus sizer, bridge to the 68k-like world

Theory of Operation 4-1

Processor Block Diagram

9601-1-x CPU board
Block diagram
RA 10.95

PowerPC 603e CPU

32

VGA video

VGA65545

WRITE PROTECT

1

MB

PCMCIA I / II

Flash PROM

max.2MB

NVRAM

32kB

interrupt controller

uPD71059

32

Dynamic bus sizer

MC68150

8

8

8

8

8

16

32

DRAM

max.2x128MB

Small peripherals

8

RS232 & GPIB

8

PCMCIA III

8

9300-4

170

MB

9300-8

4-2 Theory of Operation

floppy controller

MCS3201

Centronics

Fig 4-1: 9601-11 Block diagram

8

8

8

Serial peripherals

Real Time Clock

CLExxx

Option GAL

Front panel

16

Acquisition board

93xx-3

DRAM

The DRAM consists of two SIMM modules from 4 MB up to 32 MB each.
By interleaving two SIMMs, the access time is dramatically reduced (one beat every

30ns, while the other module “recovers” from the previous access).

The DRAM control logic, including refresh control, is built around several GALs and

a few gates.

RAMEUR (A44) is the main sequencer. It inserts refresh cycles whenever needed,

and drives row and column addressing timing.

RASADE (A39) controls the row address select lines of the memory modules, and

generates the addresses for double beat or burst accesses.

OCCASE (A37) generates the column address select lines of the SIMMs.
DRAME (A57) holds some glue logic, and a state machine that counts the number

of beats, inserting pauses in the access if necessary (single SIMM support).

Four multiplexers (A40, 42, 46 and 47) switch between odd and even addresses to

be sent to the address lines of the modules. One more multiplexer (A38) switches
low order address bits, routing them either directly to the processor, or to the DRAM
address generator in RASADE.

Normal Access Timing

This is the simplest access possible: the processor puts an address onto the
address bus, and reads back or writes one long word (32-bit wide) to DRAM.
Depending on the address (odd or even), bank A or bank B is selected in a dual
SIMM configuration.

A burst access on a 603e configured as a 32-bit device, consists of either two
(“double beat”) or eight (“burst”) successive reads in DRAM. The idea is to put a
start address onto the address bus, and read back or write several data’s from or to
DRAM every clock cycle, without the processor incrementing the address (this is
done by the external logic). To increase system performance, the memory has
been interleaved, allowing each module to access a memory location every 60ns,
but with a delay of 30ns between the modules.
A burst access is signaled by an active low _TBST signal and a 32-bit access
(SIZ2..0= 011), a double-beat access is indicated by a high _TBST but an access
size of 64 bits (SIZ2..0= 100). The double-beat case is decoded by a GAL
(VIADUC), and the signal is named _DBEAT (active low).

Refresh Timing

Burst Access Timing

The 32 kHz clock from the real time clock chip is used to refresh periodically the
DRAM.
The GAL RAMEUR generates the refresh cycles, as well as the sequencing of
_RAS and _CAS. Depending on the operating mode, it chooses to access slot A or
selects alternately slots A and B.

Theory of Operation 4-3

Memory Mapping

By default, the board is set to the biggest memory size possible. The software
checks out for “holes” in the addressing space, and sets accordingly two
configuration lines, MAP1 and MAP0.

MAP1..0 meaning
00 2x4, single sided SIMMs
01 2x8 MB SIMMs
10 2x32 MB SIMMs

VGA

The VGA 65545 controller chip (A27) includes its own address decoding logic.
It generates all video signals (red, green and blue video, horizontal and vertical
syncs, and all control lines to drive a flat panel) and controls its associated 1 MB
video dynamic RAM (reads, write and refresh cycles).
All timings are extracted from the 16 MHz bus clock, so no external crystal or
timebase is needed.

The horizontal and vertical sync. signals are sent to both the internal and the
external video connector (high density DB15 on the 9601-2 board). The external
syncs are direct, the internal syncs pass through the GAL VIADUC (A32), allowing
to force these two lines to ground. This puts the internal display in power down
mode (standby mode).
The chip can support several bus interfaces (PCI, ISA, VL,), it is configured as
VL-bus.

The 65545 chip generates red, green and blue video signals. These are controlled­ impedance lines (37.5 Ohm approximately, which corresponds to two 75 Ohm
loads in parallel). A low-pass filter is implemented right at the outputs from the VGA
controller, and another low-pass filter is located at each video connector on the
9601-2 board (just after the “active” load).

9601-2 Board: VGA proper termination (auto termination)

The 9601-2 board is a complement to the 9601-11 main processor board. It holds

the external Centronics connector (female DB-25) with its EMI filters, both internal
and external VGA connectors (female mini DB-15), and line termination for R, G and
B signals.

The VGA controller is able to drive a load of 37.5 Ohms on its Red, Green and Blue
outputs (two 75 Ohms loads in parallel). The line impedance of these signals on the
processor board is therefore close to 37.5 Ohms. The 9601-2 board includes a
special termination circuit that keeps the loads on the R, G and B lines at 37.5
Ohms, no matter if one or two 75 Ohms loads are connected. The circuit assumes
that a 75 Ohms load is present on each output.

4-4 Theory of Operation

Bus Sizer

The MPC603e processor does not support dynamic bus sizing, as did the 68k
family. Many parts of the software and the hardware rely on that feature. A Motorola
MC68150 chip ‘translates’ the PowerPC 32-bit data bus to a 68030 8 or 16-bit bus.
Except DRAM and VGA controller, all peripherals work on this 68k-type bus. Full
compatibility is therefore ensured with current acquisition boards and small
peripherals.

16 and 8-bit Peripherals

The only 16-bit peripheral hooked on the bus is the acquisition board.
RETINE (A36) generates wait state timings and is used to switch between cold boot
(return to default state) and warm boot (do a RESET, but keep current scope
settings), and generates a bus error if max. access time is out and no peripheral
has acknowledged the access.
ASSISE (A21) generates chip select signals for the bus sizer, BUDGET (A28)
creates typical 68k signals (_BAS, _BDS, 16MHz clock).
The peripheral address decoding is done by a set of GALs (GRANDS (A20),
PETITS (A29)) and a few multiplexers (A30, A22). GRANDS selects between main
peripheral categories (VGA, DRAM, memory card, flash PROM, acquisition board
or other peripherals), PETITS generates chip select signals for 8-bit peripherals
(flash PROM, memory card, non-volatile RAM, Centronics and “others”). It also
determines how many wait states are needed for peripherals not able to
acknowledge a bus access. This is done by pulling low _DSACK0 after having
sensed the corresponding number of wait states trough _BWT1 and _BWT3, which
ends the current access.
The multiplexer A30 does a finer decoding between “others” decoded in PETITS,
namely interrupt controller, small peripherals, serial interface, flash PROM chip 1 or
2, and status registers.

PCMCIA type I / II interface

This interface consists mainly of buffers for both data and address busses.
An OP amp (A10) and a MOS transistor (Q3) allow to switch off the memory card
power supply while no card is plugged in, and turn it on slowly when plugged in.
The GAL CARDAN (A11) handles the card format and generates several control
signals accordingly.
A16 (an hex D-type flip-flop) holds control bits for 12Vpp (flash programming
voltage), DRAM memory mapping and memory card type. All bits of this register
reset to zero when the _RESET signal goes active low, which means that their state
is also guaranteed at power-up.
A9 and A12 are the read registers for several status bits.
Several EXOR gates (A17 and A18) invert the most significant address bits of the
memory card whenever the SWAP jumper is plugged in, so that the first bytes are
always located at 0xFFF00000, regardless of the size of the memory card. This
allows to boot directly from a PCMCIA memory card.

Theory of Operation 4-5

Flash PROM

Two Intel 28F008-compatible 1MB PROMs (A24 and A25), are used.
From a hardware point of view, a flash PROM is the same as an EPROM in read
mode. To write to it, however, a programming voltage (Vpp) needs to be applied to
a pin. The 12V voltage is generated by a switching regulator (A26), controlled by a
logic level (_EPPP).

NVRAM

This chip is powered through the lithium battery (VCT) when power is off. The chip
select is held high through a pull-up resistor to VCT to avoid accidental overwriting
while power is off.

Interrupt Controller

In order to keep compatibility with both 68k hardware and software, it is necessary
to use a chip that prioritizes several interrupt sources. This is done by a NEC chip,
an uPD71059. It scans eight interrupt pins and sends a unique interrupt to the
processor when a (non-masked) interrupt appears.

Interrupt levels are assigned the following:
level 0 (lowest priority) acquisition board

level 1 small peripherals, unused
level 2 RS232
level 3 GPIB
level 4 small peripherals and acquisition board, unused
level 5 real time clock
level 6 time base (acquisition board)
level 7 (highest priority) only for test purposes. Linked to level 2 for
debugging.
Floppy Controller

The floppy controller chip directly interfaces to a double or high-density disk drive.
The floppy controller has a digital 8-bit input/output register, which is used to read
several status lines from the drive (disk inserted, etc.).
In principle, the controller is able to provide an interrupt when accesses are
completed. As these accesses are performed in non-time critical paths of the
program, The interrupt line has been wired to the input register, so that the program
has to poll this register until the interrupt line goes active.
The controller has it’s own timebase, a 24MHz crystal.

Centronics

Both external and internal Centronics ports are write-only. The data get latched in a
74HCT374 register (A45 for internal Centronics, A55 for external).

4-6 Theory of Operation

Small Peripheral Interface

This 8-bit interface is intended to allow external expansion to the processor board.
A56 and A53 (74HCT541 tri-state buffers) buffer the address and control lines, and
A62 (74HCT245, bi-directional tri-state buffers) buffer the data lines.
The address decoding is done on each peripheral board. The acknowledge for
each access is also done by the peripheral device, so that there is no restriction on
wait-states. The bus clock runs at 16mhz, and a reset line reinitializes the boards at
the same time as the CPU.
Four interrupt lines are also included in this interface, so that interrupt-driven
boards can be used (a good example is the 9300-4 GPIB/RS232 board, which uses
interrupts 2 and 3).

Serial Interface for on-board Peripherals

Two GALs (SEVERE and SAVEUR) are used to access serial on-board devices,
like the real time clock, option GAL, front panel and some parts of the acquisition
board. The principle of such a serial access is the following:
every write or read to the serial interface allows to write or read one bit (the MSB of
the byte). To write a byte to a serial device, you need eight accesses to the serial
interface.
Many serial devices need the same protocol: you first send a command byte (read,
write, clear, etc.), and then read or write one or several data (if required).
Depending on the address the serial interface is been accessed, the corresponding
device gets selected (_SSER, _SFPR, _SLED or SRTC lines). A clock (_SCKA), a
read data (SDRA or SDRD) and a write data (SDWA or SDWD) constitute the serial
interface itself (the D suffix on read and write data lines means Digital, i.e. devices
on the CPU board; an A suffix means devices on the Acquisition board).

RTC

The 68HC68T1 real time clock has several functions:

• keep a time-of-the-day and current-date information while the DSO is not

powered on.

• generate a 32kHz clock for DRAM refreshment.

• generate a 128Hz periodic interrupt to force bus accesses from the processor

(otherwise the watchdog timer would time out and reset the board) and allow

periodic update of the time display (“scope alive”).
The chip uses it’s own 32.768kHz crystal to keep the time and derive all timings. A
few discrete components around it leave the chip powered by the backup lithium
battery while the rest of the board is not powered, and charge the battery when the
power is on again.

Front Panel

The front panel LED can be controlled by a serial write access. The LED (write
only) shares the same address as the option GAL (read only).
The LED is driven by the less significant bit (LSB) of the control register.

Watchdog and Reset Generation

Theory of Operation 4-7

The power supply is monitored by a TL7770-5 chip. Whenever the Vcc voltage
goes below 4.8V (even for a short time !), a reset pulse is generated, whose width
is determined by an RC time constant (33uF and internal resistor).
The second half of this chip serves as watchdog circuit. The processor needs to
poll a sense line on that chip from time to time (typically a few ms). By doing this, a
capacitor (33uF) is discharged. When not polled, it gets charged by a constant
current, and when a given threshold is exceeded, a reset pulse is generated.
The LED connected goes off whenever the _RESET line is low, so a blinking LED
indicates either no bus access for longer than a few hundreds of ms, or a problem
(glitch) on the Vcc power supply.

Bus Error Generation

A bus error exception is generated when the _TEA pin is pulled low on the
processor. The 603e expects a _TA signal as an acknowledge to the current data
transaction, and inserts wait states as long as _TA has not been pulled low at the
correct timing (refer to the MPC603e documentation for exact timing information’s).
An external circuit is required to break the pending cycle if no device responds after
a given time-out.
This is the job of the GAL RETINE (A36), which counts the number of wait states
already passed (4 bit Gray counter). An external 4-bit counter (A59) extends the
count to 160 (tbd) wait cycles before triggering a bus error.
An acknowledge (_DSACK1..0 lines) aborts the time-out count and finishes
successfully the current cycle.

I/O Structure and GALs Involved

The following bloc diagram describes the peripheral decoding flow, and what GAL
is involved in the decoding. The three frames group the peripherals into 8, 16 or 32­ bit devices. The simple 3D-blocs represent an on-board device. The 3D-blocks with
an arrow represent external devices (more generally: accessed through a
connector).
GRANDS does the main decoding of peripherals and the 93xx-3 acquisition board.
PETITS does the sub-decoding for all 8-bit peripherals.
VIADUC handles the Motorola to Intel format decoding for the VGA controller.
CARDAN takes care of the PCMCIA interface timings.
PROFIL dispatches 8-bit data to the Centronics or the Floppy controller.
SAVEUR and SEVERE generate the serial clock and routes the data to the right

serial device, including CLExxx, which is the option PAL.

4-8 Theory of Operation

Fig 4-2: Peripheral Decoding and Data Bus Size

Not shown in Fig.4-2, are a few GALs for miscellaneous functions (like DRAM
refreshing).
RASADE generates the RAS signals and the lower addresses for DRAM. It also
supports the signals needed for interleaved burst mode.
OCCASE generates the CAS signals for DRAM.
RAMEUR is the main sequencer for the DRAM , and handles the access precharge
and the refresh system.
BUDGET translates a 680x0 bus cycle into a PPC cycle, and handles fast cycles,
like accesses to DRAM or VGA.
RETINE counts the wait states and generates a bus error if no response after too
many (153) wait states. It also generates the system reset.
ASSISE decodes CPU space cycles and controls the bus sizer.

Theory of Operation 4-9

4.2 F9615-3 Main Board

4.2.1 Introduction

The board is divided into five sections :

• Microprocessor control based on the MTC428 EPLD pair.

• Front-end based on the Hybrid HFE444 & HSY430 switchyard board to combine

the input channel.

• Trigger based on the Hybrids HTR420 discriminator & MST429A smart trigger

• Analog Converter based on the HAM435 Sample&Hold and A/D converter

and MNX427 min/max to pre-compute the data.

• Digital Acquisition based on the HMM434 Acquisition memory and SIMM DRAM
module for buffer memory.

• Time base based on the MCG426 clock generator & MTB411A controller

4.2.2 Front End

The front-end system provides the signal conditioning for the ADC system.

All channel are identical, thus only one channel will be described here.
The main functions of the Front end without the amplifier (HFE444) are:

• Four channels operation, calibration with Software control

• Input protection (clamp + thermal detection) and coupling (AC, DC, 1 MΩ, 50 Ω).

• Attenuator by 10 in the 50Ω path and attenuator by 20 in 1MΩ path.

• Offset control and CAL control.

The main functions of HFE444 are:

• Amplitude normalisation for the ADC system : at the BNC the dynamic range is
16 mV to 8V FS at 50Ω and to 16V FS (full scale) at 1 MOhm in a 1-2-5 step
sequence and the ADC system input is 500 mV differential.

• Fine gain control to fill in the fixed vertical sensitivities.

• Bandwidth limit filter at 25 MHz and 200 MHz.

4-10 Theory of Operation

LowZ
offset

RL1

Offset

HiZ/LowZ

Power off State : 1 MΩ input

Cal

RL0

RL3

÷20

RL2

20 db

Used during

Cal

÷10

AC/DC

RL4RL6

Fig 4-3: Front End Power off State

• Relay RL1 selects the input and offset voltage between the Hi-Z (1 MΩ) and the
50Ω path.

• The 50Ω path is then disconnected by RL0 and the signal will be in the

1 Mohm input.

• Relay RL2 selects the input between divide-by-10 or direct for the signal in the
50Ω path.

• Relay RL3 selects the input between direct or divide-by-20 for the signal in the
HiZ path.

• Relay RL4 sets the AC/DC coupling in HiZ.

• Relay RL5 is only used during calibration.

• Relay RL6 clamps the HiZ amplifier when not selected..

• Bias_HiZ and Bias_LoZ is used to bias transistors Qx003 and Qx004 to select

between the HiZ path or LowZ path as input to the HFE through the DC amplifier.

• There is no AC/DC coupling in the 50Ω path.

RL5

- 1.4V

+ 1.4V

signal

L on

board

+

buffer

HiZ

- 1.4V

50

+ 1.4V

x1

HiZ/LowZ

DC

Amp

LowZ
offset

HFE444

Variable

Gain

-

A

To trigger

B

C

Theory of Operation 4-11

50Ω input : Direct Path

RL2

20 db

Used during

Cal

÷10

Offset

LowZ
offset

RL1

HiZ/LowZ

RL0

RL3

÷20

50Ω input : Divide-by-10 Path

RL2

20 db

Used during

Cal

÷10

Offset

LowZ
offset

RL1

HiZ/LowZ

RL0

RL3

÷20

Cal

AC/DC

RL4RL6

RL5

- 1.4V

+ 1.4V

signal

L on

board

+

buffer

- 1.4V

50

+ 1.4V

x1

HiZ

-

Fig 4-4: 50Ω input direct path

Cal

AC/DC

RL4RL6

RL5

- 1.4V

+ 1.4V

signal

L on

board

+

buffer

HiZ

-

- 1.4V

50

+ 1.4V

x1

HiZ/LowZ

DC

Amp

HiZ/LowZ

DC

Amp

LowZ
offset

LowZ
offset

HFE444

Variable

Gain

HFE444

Variable

Gain

A

To trigger

B

C

A

To trigger

B

C

4-12 Theory of Operation

Fig 4-5: 50Ω divide by 10 path

Offset

1MΩ input : Direct Path

RL2

20 db

Used during

Cal

÷10

RL5

- 1.4V

+ 1.4V

AC/DC

RL4RL6

LowZ
offset

RL1

HiZ/LowZ

RL0

RL3

÷20

Fig 4-6: 1MΩ direct path

1MΩ divide by 10 AC coupled path

RL2

20 db

Used during

Cal

÷10

RL5

AC/DC

RL4RL6

Offset

LowZ
offset

RL1

HiZ/LowZ

RL0

RL3

÷20

Cal

signal

- 1.4V

+ 1.4V

+

-

signal

L on

board

buffer

HiZ

Cal

+

-

L on

board

buffer

HiZ

- 1.4V

50

+ 1.4V

x1

- 1.4V

50

+ 1.4V

x1

HiZ/LowZ

LowZ
offset

A

HFE444

DC

Amp

Variable

Gain

HiZ/LowZ

DC

Amp

LowZ
offset

B

C

HFE444

Variable

Gain

To trigger

A

To trigger

B

C

Fig 4-7: 1MΩ divide by 10 AC coupled path

Front End Analog controls

• One precision DAC with an associate circular memory (µP system) drives and

refreshes a multiple sample-and-hold system. The DC calibration control is
common to all four channels. Each channel has two analog controls.

Theory of Operation 4-13

4.2.3 F9615-3 Acquisition Block Diagram

MST

429A

426

MCG

TIME BASE

MTB

411A

Time Base Control

8-bit

8-bit

424

MAM

MAM424

424

MAM

Memory

424

MAM

HMM436 Acquisition

424

MAM

1, 2 or 4 x 256K x 8-bit

424

MAM

MAM424

424

MAM

Memory

424

MAM

HMM436 Acquisition

424

1, 2 or 4 256K x 8-bit

MAM

418

MTR

HTR420

5x

Trigger Comparator

HAM435

Converter

4x500 MS/s

Sample/Hold

Analog to Digital

HAM435

Converter

4x500 MS/s

Sample/Hold

Analog to Digital

2ns/8-bit data

2ns/8-bit data

TRIGGER

EXTERNAL

HSY430

437

MFE

HFE444

FRONT END D

437

MFE

HFE444

FRONT END C

4-14 Theory of Operation

424

MAM

MAM424

424

8-bit

MAM

Memory

MAM

HMM436 Acquisition

1, 2 or 4 256K x 8-bit

MAM

HAM435

424

424

Converter

4x500 MS/s

2ns/8-bit data

Sample/Hold

Analog to Digital

437

MFE

HFE444

FRONT END B

HSY430

424

MAM

MAM424

424

8-bit

MAM

HAM435

Memory

424

MAM

HMM436 Acquisition

424

MAM

1, 2 or 4 x 256K x 8-bit

4x500 MS/s

Converter

2ns/8-bit data

Sample/Hold

Analog to Digital

437

MFE

HFE444

FRONT END A

Fig 4.8: Front End, Trigger, Sample&Hold, Analog to Digital, Memory

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

4.2.4 One, Two and Four Channel mode

Four channel mode

• All BNC inputs are active

HFE428

A
B
C

A1003

FE output A: 8 (C if trigg e r sou rc e )

HFE428

A
B
C

A2003

FE output B: 2 (6 if trigger source)

HFE428

A
B
C

A3003

FE output C: 8 (C if trigger source)

HFE428

A
B
C

A4003

FE output D: 2 (6 if trigger source)

MTR

MTR

MTR

MTR

JSY1000

JSY2000

JSY3000

JSY4000

J8

11, 1 4

3, 6

J7

11, 1 4

3, 6

HSY430

J6

11, 1 4

3, 6

J5

11, 1 4

3, 6

HSY430

JSY1500
J4
3, 6

11, 1 4

JSY2500
J3
3, 6

11, 1 4

JSY3500
J2
3, 6

11, 1 4

JSY4500
J1
3, 6

11, 1 4

B

A

HAM421

A1500

B

A

HAM421

A2500

B

A

HAM421

A3500

B

A

HAM421

A4500

DC 1

A
B

SEL

INSEL1_A

DC 2

B

SEL

INSEL2_A

DC 1

A
B

SEL

INSEL1_B

DC 2

B

SEL

INSEL2_B

DC 1

A
B

SEL

INSEL1_C

DC 2

B

SEL

INSEL2_C

DC 1

A
B

SEL

INSEL1_D

DC 2

B

SEL

INSEL2_D

MSB LSB

01100110

66digitizerInSel

Figure 4-9 Four Channel Mode Signal Routing

One and Two channel mode

• Two channel mode, BNC inputs for channel 2 and 3 are active, ADC's for channel 1 & 2
are used for signal on channel 2 input, ADC's for channel 3& 4 are used for signal on
channel 3 input.

• One channel mode, PP096 adapter must be connected between channel 2 and 3 BNC
inputs, all 4 ADC's are used for signal input to PP096

HFE428

A
B
C

A1003

FE output A: 0 (4 if trigger source)

HFE428

A
B
C

A2003

FE output B: A (E if trigger source)

HFE428

A
B
C

A3003

FE output C: A (E if trigger source)

HFE428

A
B
C

A4003

FE output D: 0 (4 if trigger source)

MTR

MTR

MTR

MTR

JSY1000

JSY2000

JSY3000

JSY4000

JSY1500

J8

11, 1 4

3, 6

J7

11, 1 4

3, 6

HSY430

J6

11, 1 4

3, 6

J5

11, 1 4

3, 6

HSY430

J4
3, 6

11, 1 4

JSY2500
J3
3, 6

11, 1 4

JSY3500
J2
3, 6

11, 1 4

JSY4500
J1
3, 6

11, 1 4

B

A

HAM421

A1500

B

A

HAM421

A2500

B

A

HAM421

A3500

B

A

HAM421

A4500

DC 1

A
B

SEL

DC 2

B

SEL

DC 1

A
B

SEL

DC 2

B

SEL

DC 1

A
B

SEL

DC 2

B

SEL

DC 1

A
B

SEL

DC 2

B

SEL

INSEL1_A

INSEL2_A

INSEL1_B

INSEL2_B

INSEL1_C

INSEL2_C

INSEL1_D

INSEL2_D

MSB LSB

10100101

5digitizerInSel

Figure 4-10 One and Two Channel Mode Signal Routing

Theory of Operation 4-15

4.2.5 F9615-3 Control & Transfer Block Diagram

16-Bit

Sizer

Dynamic Bus

System

Memory

CPU Board PPC603E

8-256Mbytes

96-240 Mhz

8-bit

MTC 428

Transfer Controller

8-bit

TIME BASE

MST

MCG

MTB

429A

426

411A

16-bit

B

MNX 427 Control/Monitor bus

16-bit CPU Data bus

16-bit

B

16-bit

B

C

Min/Max

Histogram

Transitions

MNX 427

7-bit7-bit

C

Min/Max

Histogram

Transitions

MNX 427

Min/Max

Histogram

Transitions

MNX 427

C

Buffer Memory Control

A

A

A

8-bit

16-bit

8-bit

2x (4x) SIMM DRAM

Buffer Memory

Time Base Control

424

MAM

MAM424

8-bit

2x 8(16) bit

8-bit

8-bit

424

MAM

Memory

424

MAM

HMM436 Acquisition

424

MAM

1, 2 or 4 x 256K x 8-bit

424

MAM

MAM424

424

MAM

Memory

424

MAM

HMM436 Acquisition

424

1, 2 or 4 256K x 8-bit

MAM

424

MAM

MAM424

424

MAM

Memory

424

MAM

HMM436 Acquisition

424

1, 2 or 4 256K x 8-bit

MAM

4-16 Theory of Operation

2x 8(16) bit

2x (4x) SIMM DRAM

Buffer Memory

C

16-bit

B

Min/Max

Histogram

Transitions

MNX 427

A

16-bit

8-bit

424

MAM

MAM424

424

MAM

Memory

424

MAM

HMM436 Acquisition

424

MAM

1, 2 or 4 x 256K x 8-bit

Fig 4.11: Processor Control, Min/Max, Buffer Memory, Transfer

4.2.5 Trigger

The different trigger couplings are :

• DC

• AC : cut off frequency is almost 10 Hz.

• LF REJ : single pole high pass filter with a cut off frequency at50 kHz.

• HF REJ : single pole low pass filter with a cut off frequency at 50 kHz.

• TBWL : single pole low pass filter at 25 MHz.

A sample and hold fed by the precision DAC provides the threshold level.
The addresses are :

Each channel has a pick-off after the HFE428 or after the high impedance buffer for
external trigger. The TV trigger source is selected via bit TVS and drives a times 10
amplifier with complementary outputs. These outputs are selected ( _TVINV)
depending on the state of the selected HFE428 gain.
The TV trigger uses a commercial chip (LM1881) and provides two outputs,
TV1 & TV2. This circuit is able to trigger on different TV line number standards.

Analog Controls

TV Trigger

4.2.6 Analog to Digital Converter

The analog to digital converter system does the signal conversion to 8 bits, using

the following circuits:

MAD422: Analog to Digital converter, maximum clock speed of 500 Ms/s

Introduction

• HAM435: Hybrid Acquisition Module, Sample&Hold plus ADC
MSH437: Monolithic Sample and Hold. performs the track&hold before the ADC.

• HMM436: Hybrid Memory module, up to 4 Mbytes per Channel
MAM 424: Monolithic Access Memory

• MNX427: Monolithic MIN-MAX

• Buffer Memory : 16Mbytes

• HSY430: Interleaving Channel

Theory of Operation 4-17

4.2.7 Time Base

A

_

The time base includes three circuits:

Trigger circuitry
Frequency divider

Block Diagram

Introduction

• MCG426: generates sampling clocks: 12.5 MHz up to 2GHz

generates clocks for the MTB411

interleaves sampling clocks to increase sampling rate and memory

depth.

• MTB411A: Time Base System

TDC interpolator and Real Time computation

• MST429A: Single source trigger, Standard trigger, Hold off, Pulse width & interval

Multiple source trigger, State qualified, Edge qualified

ENABLE

QQD

CONTROL
from uP

to trigger selec t i o n

enable
clock 10MHz

DIO(7:0) +
A(1:0) +
control

EXTCK

EXTREF

Vcc

10 MHz
Reference

MST 429

2

TRIG

2

TRIG

S2EDGE

EN10MHZ

10MHZclock 10MHz

500MHZclock 500MHz

TRTTRT

EXTCK

EXTREF

INTREF
PHDET

2

2

RAMPST

MCG 426

VCO

BCK

R

IT

RT

TR

C

C

IG

M

D

PS

FDCK
FDEND

MACQ

TSCK
TBCK

SHCK_A
SHCK_B
SHCK_C
SHCK_D

MCLR CLR

VCO2G PDCK

2

TRIGEN

ITBUSY

TRIGD

ITCK

MTB 411

RTCK

INT

FDCK

SHCK_A
SHCK_B
SHCK_C
SHCK_D

Peak

2

Detect
MPD

TSCK TBCK

2

2

2

2

MACQ

FDEND

HSH & ADC

MCK

to uP

ITMB

MEMORY

MCK
DIN[7..0]

4-18 Theory of Operation

Fig 4.12: Time Base Block Diagram

4.3 F9301-4 GPIB and RS 232 Interface

4.3.1 Block Diagram

Peripheral
Bus
Connector

Address
Decoding and
Logic Control

Address Bus

TNT4882
GPIB Controller
100-pins QFP

40 Mhz
CMOS

8-bit Data Bus

UART 16C650
Serial Controller
44-pins PLCC

Max232A
RS-232C
Interface
16-Pins SO

Fig 4.13: GPIB & RS232 Interface Block Diagram

1.8432Mhz
TTL/CMOS

This board is connected to the processor through a flat cable.
Data bus is 8 bits, address bus: 12 bits.
Address 0180 000 to 0180 00FF.

4.3.2 F9301-4 RS 232 Serial Interface

Based on the ST16650 from EXAR or Startech.

• Clock frequency 1.8432 MHz.

• RTC/CTS signals are connected

• DCD input is biased and the DTR output is not wired

• Asynchronous communication up to 1Mbits/sec

• 32 bytes receive and transmit FIFOs buffer

• Connector compatible with a DB9-P (9 pin male).

4.3.3 F9301-4 GPIB Interface

Based on the circuit TNT4882 from National Instruments.

• Clock frequency 40 MHz.

• Up to 1.5 Mbytes/sec using interlocked IEEE 488.1 handshake

The GPIB address is set by software and stored in non-volatile memory.

• Two 8-bit 16-deep FIFOs buffer data between GPIB and CPU

GPIB
Connector
24-Pins
Female

RS-232C
DB-9 Male
Connector

Theory of Operation 4-19

4.4 LCDFP9615 Front Panel

The front panel assy is connected to the processor board with a flat cable. Power
supply and control signals are supplied from the processor. The front panel is
divided into several sections:

• Display using 10.4inch TFT color LCD Module

• F9601-61 Floppy disk drive assy

• S9615-21 Buffer board which interfaces the digital signals from the processor to

the TFT display unit

• S9615-52 board with Motorola 68HC05C4 processor, encoders, and serial data
interface.

• F9615-5 matrix keypad with push buttons.

4.5 F9300-7 Printer Controller Option

• Based on the Internal graphic printer LPT5446, and LPT5000 series control chip
set from Seiko instrument Inc (Technical reference 39019-2234-01)

• PT501P01 CPU

• PT500GA1 Gate array

• Address 0130 0100

• Interrupt level 2

4.6 PS9611 Power Supply

The PS9611 is a nine output 300 W AC-DC switching mode power supply.

4.6.1 Specifications

Input Frequency: AC input Frequency range of 47 Hz to 63 Hz.
Inrush Current: less than 30 A over full line voltage ranges and input frequency

AC Input Voltage

85-132VAC and 170-264VAC, auto-ranging universal input, provides automatic
sensing of 115 or 230VAC input voltage. Power factor correction for compliance with
EN61000-3-2: 1995 standard (harmonic current emissions) under all conditions of
input voltage, input frequency, loads and temperature ranges.
AC power enters the DSO chassis thru an IEC320 input receptacle, fuses and an
EMI line filter. The filter high frequency noise generated by the DSO from getting out
on to the AC line.

4-20 Theory of Operation

DC Output Specifications

Output Adjustment

Range

+5 (1) +4.8 to +5.4V 15A 20A
+3 (1) +2.9 to +3.5V 10A 20A

-2 (1) -1.9 to –2.6V 5A 15A

-5 (1) -4.8 to -5.4V 15A 20A
+6 (1) +5.6 to +6.2V 2.5A 4A

-6 (1) -5.6 to -6.2V 2.5A 4A
+15 +14.8 to +15.4V 2.5A 4A

-15 -14.8 to -15.4V 2A 3A / 8A

-12 -11.5 to -14.0V 0.5A 1A

Note:(1) with remote sense.
Output power: 300W
Ripple and Noise: less than 25 mV
Hold up Time: 25 mV at full load
Transient response: recovery time <1.2 msec to within 50 mV of its final value
Protections: over current, over voltage, over temperature
Cooling: PS9611 is cooled by a forced airflow provided by a fan that is integrated

inside the unit.
Environmental: Operating temperature range 0 °C to + 55 °C

Storage temperature range - 55 °C to + 85 °C
Operating humidity from 5% to 95% RH.
Operating Altitude (max) 5000m or 15000 feet

Safety Standards: CE, UL, CSA, TUV
EN61010-1:1993 (IEC1010-1:1995), UL3111-1,
CSA-C22.2 No.61010-1.
Protection class I, pollution degree 2, installation category II.

EMI: EN50081-1:1992, EN55022:1987 Class B, EN61000-3-2&3:1995 Class D
Immunity: EN50082-1:1994, EN61000-4-2,4,5,8&11:1995,

IEC1000-4-2,3,4,5,6,8&11

Nominal
Load

Maximum
Load

Theory of Operation 4-21

4.6.2 Power Supply Block Diagram

4-22 Theory of Operation

5. Performance Verification

5.1 Introduction

This chapter contains procedures suitable for determining if the LC684D/M/L/XL
Digital Storage Oscilloscope performs correctly and as warranted.

They check all the characteristics listed in subsection 5.1.1.
Because they require time and suitable test equipment, you may not need to

perform all of these procedures, depending on what you want to accomplish.
In the absence of the computer automated calibration system based on LeCroy

Calibration Software (LeCalsoft), this manual performance verification procedure
can be followed to establish a traceable calibration.
It is the calibrating entities’ responsibility to ensure that all laboratory standards
used to perform this procedure are operating within their specifications and
traceable to required standards if a traceable calibration certificate is to be issued
for the LC684D/M/L/XL Digital Storage Oscilloscope.

5.1.1 List of Tested Characteristics

This subsection lists the characteristics that are tested in terms of quantifiable
performance limits.

• Input Impedance

• Leakage Current

• Peak to Peak and RMS Average noise level

• Positive and Negative DC linearity

• Positive and Negative Offset

• Bandwidth

• Trigger Level

• Smart Trigger

• Time Base Accuracy

• Overshoot and Rise Time –Not required for traceable calibration

5.1.2 Calibration Cycle

The LC684D/M/L/XL Digital Storage Oscilloscope requires periodic verification of
performance. Under normal use ( 2,000 hours of use per year ) and environmental
conditions, this instrument should be calibrated once a year.

Rev. B Performance Verification 5-1

5.2 Test Equipment Required

These procedures use external, traceable signal generators, DC precision power
supply, step generator and digital multimeter, to directly check specifications.

Instrument Specifications Recommended
Signal Generator

Radio Frequency
Signal Generator
Audio Frequency

Voltage Generator
DC Power Supply
Power Meter +
Sensor
Digital Multimeter
Volt & Ohm
Coaxial Cable, 1 ns

Coaxial Cable, 5 ns
2 Attenuators, 20 dB
Attenuator, 6 dB
Terminator, 2 W
T adapter

Table 5-1 : Test Equipment

Frequency : .5 MHz to 2 GHz
Frequency Accuracy : 1 PPM
Frequency : 0 to 5 kHz
Amplitude : 8 V peak to peak

Range of 0 to 20 V, in
steps of no more than 15 mV

Accuracy ±1 %
Keithley 2000

50Ω, BNC, length 20 cm,
50Ω, BNC, length 100 cm,
50Ω, BNC, 1 % accuracy
50Ω, BNC, 1 % accuracy
50Ω, BNC, Feed-Through
50Ω, BNC T adapter

HP8648B
or equivalent
LeCroy LW420
or HP33120A or
equivalent
HP6633A
or equivalent
HP437B + 8482A or
equivalent

or equivalent

5.2.1 Test Records

The last pages of this document contain LC684D/M/L/XL test records in the format
tables. Keep them as masters and use a photocopy for each calibration.

5.3 Turn On

If you are not familiar with operating the LC684D, read the operator's manual.
 Switch on the power using the power switch.
 Wait for about 20 minutes for the scope to reach a stable operating

temperature, and verify :

- the display turns on after about 10 seconds and is stable.

- the range of intensity and grid intensity is reasonable.

5-2 Performance Verification Rev. B

5.4 Input Impedance

DC 1.00 MΩ ±1 %
AC 1.027 MΩ ±2 %
DC 50Ω ±1.25 %
EXT DC 50Ω ±3%
EXT DC 1.00 MΩ ±2%

If tested in a lower range some readings may not be within specifications.

Specifications

The impedance values for 50Ω, 1MΩ and Gnd couplings are measured with a

high precision digital multimeter. The DMM is connected to the DSO in 4 wire
configuration (input and sense), allowing for accurate measurements. Check that
the DMM used is measuring the 1 MΩ inputs in at least a 3 MΩ range.

5.4.1 Channel Input Impedance
a. DC 1MΩ

 Recall LC684P001.PNL or configure the DSO :
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace OFF Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 1MΩ on all 4 Channels
Input gain : 50 mV/div. on all 4 Channels
Time base : 50 µsec/div.
Trigger mode : Auto

Rev. B

Performance Verification 5-3

 Set the DMM with Ohms and Ohms sense to provide a 4 wire measurement.
 Connect it to Channel 1.
 Measure the input impedance. Record it in Table 2, and compare it to the limits.
 Repeat the above test for all input channels.
 Recall LC684P002.PNL or Set Input gain to 200 mV/div. on all 4 Channels
 Repeat the test for all input channels.
 Record the measurements in Table 2, and compare the test results to the

limits in the test record.

b. AC 1MΩ

 Recall LC684P003.PNL or configure the DSO as shown in 5.4.1.a,

and for each Channel make the following change :
Input Coupling : AC 1MΩ

5-4 Performance Verification Rev. B

 For all input channels measure the input impedance.
 Record the input impedance in Table 2, and compare it to the limits.

 Recall LC684P004.PNL or Set Input gain to 200 mV/div on all 4 Channels.
 Repeat the test for all input channels.
 Record the measurements in Table 2, and compare the results to the limits in

the test record.

c. DC 50Ω

 Recall LC684P005.PNL or configure the DSO as shown in 5.4.1.a,
and for each Channel make the following change:

Input Coupling : DC 50Ω

 For all input Channels, measure the input impedance.
 Record the input impedance in Table 2, and compare it to the limits.
 Recall LC684P006.PNL or set Input gain to 200 mV/div. on all 4 Channels

 Repeat the test for all input channels. Record the measurements in Table 2,

and compare the results to the limits in the test record.

Rev. B

Performance Verification 5-5

5.4.2 External Trigger Input Impedance

a. DC 1MΩ

 Recall LC684P007.PNL or configure the DSO :
Trigger mode : Auto

Select Setup trigger
Trigger on : EXT
Cplg Ext : DC
External : DC 1MΩ
Time base : 50 µsec/div.

 Connect the DMM to External, and measure the input impedance.
 Record the input impedance in Table 2, and compare it to the limits.
 Recall LC684P008.PNL or set trigger to Ext/5
 Measure the input impedance.
 Record the test result in Table 2, and compare the result to the limits in

the test record.

5-6 Performance Verification Rev. B

b. DC 50Ω
 Recall LC684P009.PNL or configure the DSO :
Select Setup trigger
Trigger on : EXT
External : DC 50Ω

 Connect the DMM to External, and measure the input impedance.
 Record the input impedance in Table 2, and compare the result to the limit in

the test record.
 Recall LC684P010.PNL or configure the DSO:
Trigger on : EXT/5

Rev. B

Performance Verification 5-7

 Measure the input impedance.

 Record the input impedance in Table 2, and compare the result to the limit in
the test record.

5.4.3 Ground

 Recall LC684P011.PNL or configure the DSO as shown in 5.4.1.a,
and for each Channel make the following changes :

Input Coupling : Grounded

 Connect the DMM to Channel 1, and measure the input impedance.
 Record the input impedance in Table 2, and compare the result to the limit in

the test record.
 Repeat the test for all input channels.

 Record the measurements in Table 2, and compare the results to the limits in
the test record.

5-8 Performance Verification Rev. B

5.5 Leakage Current

Specifications

DC 1MΩ, AC 1MΩ, DC 50Ω, EXT DC 50Ω : ±1 mV

EXT DC1MΩ : ±2 mV
The leakage current is tested by measuring the voltage across the input channel.

5.5.1 Channel Leakage Current
a. DC 1MΩ

 Recall LC684P012.PNL or configure the DSO :

Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 1MΩ on all 4 Channels

Input gain : 50 mV/div. on all 4 Channels
Trigger mode : Auto
Time base : 10 µsec/div.

 Set the DMM to measure Volts, and connect it to Channel 1.

Rev. B

Performance Verification 5-9

 Measure the voltage and enter it in Table 3. Compare it to the limits.
 Repeat the test for all input channels.
 Recall LC684P013.PNL or set Input gain to 200 mV/div. on all 4 Channels

 Repeat the test for all input channels. Record the measurements in Table 3,
and compare the results to the limits in the test record.

b. DC 50Ω

 Recall LC684P014.PNL or configure the DSO as shown in 5.5.1.a
and for each Channel make the following changes :

Set Input Coupling : DC 50Ω

 Connect the DMM to Channel 1.

 Measure the voltage and enter it in Table 3. Compare it to the limits.

 Recall LC684P015.PNL or set Input gain to 200 mV/div. on all 4 Channels

 Repeat the test for all input channels.
 Record the measurements in Table 3, and compare the results to the limits in

the test record.

5.5.2 External Trigger Leakage Current

a. DC 50Ω

 Recall LC684P016.PNL or configure the DSO as shown in 5.5.1.a
and make the following changes :

Select Setup trigger
Set Trigger on : EXT

External : DC 50Ω

 Connect the DMM to External.

 Measure the voltage and enter it in Table 3. Compare it to the limits.

5-10 Performance Verification Rev. B

b. DC 50Ω EXT/5

 Recall LC684P017.PNL or configure the DSO as shown in 5.5.1.a
and make the following changes :

Select Setup trigger
Set Trigger on : EXT/5

External : DC 50Ω

 Connect the DMM to External.

 Measure the voltage and enter it in Table 3. Compare it to the limits.

5.6 Average Noise Level

Description

impedance, with AC and DC input coupling, 0 mV offset, at a gain setting of 10 mV/div.,
and different Time base settings.
The scope parameters functions are used to measure the Peak and RMS amplitude

Noise tests with open inputs are executed on all channels for both 1MΩ and 50Ω input

5.6.1 Peak to Peak Noise

Specifications
9 % of full scale or 7.2 mV Peak-Peak at 10 mV/div.

a. DC 1MΩ

With no signal connected to the inputs

 Recall LC684P018.PNL or configure the DSO :
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 1MΩ on all 4 Channels
Input gain : 10 mV/div. on all 4 Channels
Input offset : 0.0 mV on all 4 Channels
Trigger setup : Edge
Trigger on : 1
Coupling 1 : DC
Trigger Mode : Auto

Time base : 20 msec/div.
Channel use : 4

Rev. B

Performance Verification 5-11

Record up to : 50 k Samples

Press : Cursors/Measure

Measure : Parameters
Mode : Custom
Statistics : On
Change parameters
Category : All
On line 1 : Measure pkpk of Ch1
On line 2 : Measure pkpk of Ch2
On line 3 : Measure pkpk of Ch3
On line 4 : Measure pkpk of Ch4

On line 5 : no parameter selected for line 5

5-12 Performance Verification Rev. B

Rev. B

Performance Verification 5-13

 Press Clear Sweeps.
 Measure for at least 50 sweeps, then press Stop to halt the acquisition.
 Record the four high pkpk parameter values in Table 4, and compare the test

results to the limits in the test record.
 Repeat the test for Time base : 1 msec/div.
 Record the measurements (high pkpk of 1,2,3,4) in Table 4, and compare the

results to the limits in the test record.

b. AC 1MΩ

 Recall LC684P019.PNL or configure the DSO as shown in 5.6.1.a,
and for each Channel make the following changes :

Input Coupling : AC 1MΩ on all 4 Channels
Time base : 2 µsec/div
 Press Clear Sweeps.
 Measure for at least 50 sweeps, then press Stop to halt the acquisition.
 Record the four high pkpk parameter values in Table 4, and compare the test

results to the limits in the test record.

5-14 Performance Verification Rev. B

c. DC 50Ω

 Recall LC684P020.PNL or configure the DSO as shown in 5.6.1.a,
and for each Channel make the following changes :

Input Coupling : DC 50Ω on all 4 Channels
Time base : 2 µsec/div

 Press Clear Sweeps.

 Measure for at least 50 sweeps, then press Stop to halt the acquisition.

 Record the four high pkpk parameter values in Table 4, and compare the test
results to the limits in the test record.

 Repeat the test for Time base : 20 µsec/div.
 Record the measurements (high pkpk of 1,2,3,4) in Table 4, and compare the

results to the limits in the test record.

Rev. B

Performance Verification 5-15

d. DC 50Ω, 2 Channel Mode

Channel 2 & Channel 3
 Recall LC684P021.PNL or configure the DSO as shown in 5.6.1.a.

and make the following changes :
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 10 mV/div. on all 4 Channels
Channels Trace ON Channel 2, Channel 3

Channels Trace OFF Channel 1, Channel 4
Time base : 1 µsec/div.

Select Time base Setup
Channel use : 2
Press : Cursors/Measure

Change parameters

On line 1 : Measure pkpk of Ch2
On line 2 : Measure pkpk of Ch3

5-16 Performance Verification Rev. B

 Check that the Sampling rate is 4 GS/s

 Press Clear Sweeps.

 Measure for at least 50 sweeps, then press Stop to halt the acquisition.
 Record the two high pkpk of Ch2 & Ch3 in Table 4, and compare the test

results to the limits in the test record.

e. LC684D, LC684DM, LC684DL & LC684DXL 1 Channel Mode

Channel 2 :

 Recall LC684P023.PNL or configure the DSO as shown in 5.6.1.a.

and make the following changes :

Channels Trace ON Channel 2
Channels Trace OFF Channel 1, Channel 3, Channel 4

Time base : 0.5 µsec/div.
Press : Cursors/Measure

Input Coupling : DC 50Ω on all 4 Channels

Rev. B

Performance Verification 5-17

Change parameters
On line 1 : Measure pkpk of Ch2

 Connect PP096 adapter to channel 2 & 3
 Check that the Sampling rate is 8GS/s

 Measure for at least 50 sweeps, then press Stop to halt the acquisition.

limits in the test record.

5-18 Performance Verification Rev. B

 Press Clear Sweeps.

 Record the high pkpk of Ch2 in Table 4, and compare the test result to the

5.6.2

Rms Noise

Specifications

0.9 % of full scale or 0.72 mV at 10 mV/div.

a. DC 1MΩ

With no signal connected to the inputs
 Recall LC684P024.PNL or configure the DSO :
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 1MΩ on all 4 Channels
Input gain : 10 mV/div. on all 4 Channels
Input Offset : 0mv on all 4 Channels

Trigger setup : Edge
Trigger on : 1
Coupling 1 : DC
Trigger Mode : Auto

Time base : 20 msec/div.
Channel use : 4

Record up to : 50 k Samples

Press : Cursors/Measure

Measure : Parameters
Mode : Custom
Statistics : On

Change parameters
Category : All
On line 1 : Measure sdev of Ch1

On line 2 : Measure sdev of Ch2
On line 3 : Measure sdev of Ch3
On line 4 : Measure sdev of Ch4

On line 5 : no parameter selected for line 5

Procedure

Rev. B

Performance Verification 5-19

 Press Clear Sweeps.
 Measure for at least 50 sweeps, then press Stop to halt the acquisition.
 Record the four high sdev parameter values in Table 5, and compare the test

results to the limits in the test record.
 Repeat the test for Time base : 1 msec/div.
 Record the measurements (high sdev of 1,2,3,4) in Table 5, and compare the

results to the limits in the test record.

b. AC 1MΩ

 Recall LC684P025.PNL or configure the DSO as shown in 5.6.2.a.
and for each Channel make the following change :

Input Coupling : AC 1MΩ on all 4 Channels
Time base : 2 µsec/div.

 Press Clear Sweeps.
 Measure for at least 50 sweeps, then press Stop to halt the acquisition.

5-20 Performance Verification Rev. B

 Record the four high sdev parameter values in Table 5, and compare the test
results to the limits in the test record.

c. DC 50Ω

 Recall LC684P026.PNL or configure the DSO as shown in 5.6.2.a
and make the following changes :

Input Coupling : DC 50Ω on all 4 Channels
Time base : 2 µsec/div.

 Press Clear Sweeps.
 Measure for at least 50 sweeps, then press Stop to halt the acquisition.

Rev. B

Performance Verification 5-21

 Record the four high sdev parameter values in Table 5, and compare the test
results to the limits in the test record.

 Repeat the test for Time base : 20 µsec/div.

 Record the measurements (high sdev of 1,2,3,4) in Table 5, and compare the
results to the limits in the test record.

d. DC 50Ω, 2 Channel Mode

Channel 2 & Channel 3
 Recall LC684P027.PNL or configure the DSO as shown in 5.6.2.a.

and make the following changes :
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 10 mV/div. on all 4 Channels
Channels Trace ON Channel 2, Channel 3

Channels Trace OFF Channel 1, Channel 4
Time base : 1 µsec/div.

5-22 Performance Verification Rev. B

Select Time base Setup
Channel use : 2

Press : Cursors/Measure

Change parameters
On line 1 : Measure sdev of Ch2

On line 2 : Measure sdev of Ch3

 Check that the Sampling rate is 4 GS/s

 Press Clear Sweeps.

 Measure for at least 50 sweeps, then press Stop to halt the acquisition.
 Record the two high sdev of Ch2 & Ch3 in Table 5, and compare the test

results to the limits in the test record.

Rev. B

Performance Verification 5-23

e. LC684D, LC684DM, LC684DL & LC684DXL 1 Channel Mode

Channel 2 :

 Recall LC684P028.PNL or configure the DSO as shown in 5.6.2.a.

and make the following changes :

Channels Trace ON Channel 2
Channels Trace OFF Channel 1, Channel 3, Channel 4

Time base : 0.5 µsec/div.
Press : Cursors/Measure

Change parameters
On line 1 : Measure sdev of Ch1

 Connect PP096 to channels 2 & 3
 Check that the Sampling rate is 8GS/s

Input Coupling : DC 50Ω on all 4 Channels

5-24 Performance Verification Rev. B

 Press Clear Sweeps.
 Measure for at least 50 sweeps, then press Stop to halt the acquisition.

 Record the high sdev of Ch1 in Table 5, and compare the test result to the
limits in the test record.

5.6.3 Ground Line Test

Specifications

±5 % of full scale at 2 mV/div.

±

3 % of full scale at 5 mV/div.

±2 % of full scale at 10 mV/div. and above.
Procedure

The stability of the ground line is verified for each channel at each fixed gain.
The measured average values are checked against the desired limits.

a. DC 1MΩ

With no signal connected to the inputs
 Recall LC684P029.PNL or configure the DSO :
Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4

Input Coupling : DC 1MΩ on all 4 Channels
Input gain : from 2mV/div to 1 V/div. (see Table 6) on all 4 Ch
Offset : Zero on all 4 Channels

Trigger on : Channel 1, DC
Trigger mode : Auto
Time base : 0.5 µsec/div.

Channel use : 4
Record up to : 50 k
Channels Trace OFF Channel 1, Channel 2, Channel 3 & Channel 4

Zoom+Math Trace ON A, B, C & D
Select Math Setup
For Math : Use at most 5000 points
Redefine A, B, C, D Channel 1, Channel 2, Channel 3 & Channel 4
Use Math ? : Yes
Math Type : Average
Avg. Type : Summed
For : 100 sweeps

Press : Cursors/Measure
Select : Parameters
Mode : Custom
Statistics : off

Rev. B

Performance Verification 5-25

5-26 Performance Verification Rev. B

Change parameters
On line 1 : Measure mean of A

On line 2 : Measure mean of B
On line 3 : Measure mean of C
On line 4 : Measure mean of D

 Press Clear Sweeps.
 After 100 sweeps record the mean value of A, B, C & D in Table 6, and

compare the test results to the limits in the test record.
 Repeat step 5.6.3.a. for all vertical scale settings listed in Table 6, and check

that the test results (mean value of A, B, C, D) are within the limits specified.
 Record the measurements in Table 6.

Rev. B

Performance Verification 5-27

b. DC 50Ω

 Recall LC684P030.PNL or configure the DSO as shown in 5.6.3.a.

and for each Channel make the following change:
Input Coupling : DC 50Ω on all 4 Channels

Input gain : from 2mV/div to .2 V/div. (see Table 7) on all 4 Ch

 Press Clear Sweeps.
 After 100 sweeps record the mean value of A, B, C & D in Table 7, and

compare the test results to the limits in the test record.
 Repeat step 5.6.3.b. for all vertical scale settings listed in Table 7, and check

that the test results (mean value of A, B, C, D) are within the limits specified.

 Record the measurements in Table 7.

5-28 Performance Verification Rev. B

c. DC 50Ω, 2 Channel Mode

Channel 2 & Channel 3

 Recall LC684P031.PNL or configure the DSO as shown in 5.6.3.a.
and make the following change :

Input Coupling : DC 50Ω on all 4 Channels
Input gain : 0.2 V/div. on all 4 Channels
Trace ON : A:Average of (2), C:Average of (3)
Trace OFF : B:Average of (1), D:Average of (4)
Time base : 0.2 µsec/div.

Select Time base Setup
Channel use : 2

Press : Cursors/Measure
Change parameters
On line 1 : Mean of B
On line 2 : Mean of C
On line 3, 4, 5 : No parameter selected

 Check that the Sampling rate is 4 GS/s

 Press Clear Sweeps.

 After 100 sweeps record the mean value of B & C in Table 7, and compare the
test results to the limits in the test record.

Rev. B

Performance Verification 5-29

d. LC684D, LC684DM, LC684DL & LC684DXL 1 Channel Mode

Channel 2

 Recall LC684P032.PNL or make the following changes :

Trace ON : A:Average of (2)
Trace OFF : B:Average of (1), C:Average of (3), D:Average of (4)

Time base : 0.1 µsec/div.

Press : Cursors/Measure

Change parameters

On line 1 : Measure Mean of B

On line 2, 3, 4, 5 : No parameter selected

 Connect PP096 to channel 2 & 3

 Check that the Sampling rate is 8 GS/s

 Press Clear Sweeps.

 After 100 sweeps record the mean value of A in Table 7, and compare the test

result to the limits in the test record.

5-30 Performance Verification Rev. B

5.6.4 Erroneous Read / Write Test

Specifications

±2,5 % of full scale at 50 mV/div.

Procedure

a. Channel 1, Channel 2, Channel 3 and Channel 4

 For LC684D recall LC684P033.PNL, for LC684DM recall LC684P034.PNL, for

LC684DL recall LC684P035.PNL or for LC684DXL recall LC684P036.PNLor

configure the DSO :

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Zoom+Math Trace ON D
Input Coupling : DC 50Ω on all 4 Channels
Global BWL ON : 25MHz
Input gain : 50 mV/div. on all 4 Channels
Offset : Zero on all 4 Channels

Trigger on : Line
Trigger mode : Normal
Time base : 5 µsec/div for LC684D
20 µsec/div for LC684DM

0.1 mS for LC684DL

0.2 mS for LC684DXL

Select Setup timebase
Channel use : 4

Record up to : 100K samples for LC684D
500K samples for LC684DM

2.5M samples for LC684DL
4M samples for LC684DXL

Select Math Setup
For Math : Use at most 500 points

Redefine A : A=1-1
Use Math? : Yes
Math Type : Arithmetic
Difference :

Redefine B : B=2
Use Math? : No

Trace B is Zoom of 2
Redefine D : D=M1

Use Math? : No
Trace D is Zoom of M1

1 minus 1

Rev. B

Performance Verification 5-31

 Press Reset Zoom+Math

 Select Cursors/Measure

Measure : Parameters
Mode : Pass
Testing : On
Select : Change Test Conditions

On line : Action
If : Fail
Then : Stop Yes
Store No
Dump No
Beep Yes
Pulse No
On line 1 : Test on Mask
True if all points of 1 are inside mask D
On line 2 : Test on Mask
True if all points of 2 are inside mask D
On line 3 : Test on Mask
True if all points of 3 are inside mask D
On line 4 : Test on Mask
True if all points of 4 are inside mask D

5-32 Performance Verification Rev. B

Rev. B

Performance Verification 5-33

 Select Modify Mask

From : W'form

Into : M1
Use W'form : A
Delta V : 0.20 div
Delta T : 0.00 div

 To start the test, select Cursors/Measure, Change Test Conditions,

Modify Mask and press Make Mask M1

 After 10000 sweeps for LC684D, or after 2500 sweeps for
LC684DM, or after 500 sweeps for LC684DL or LC684DXL check that the
number of Passed equals the number of Sweeps on all 4 Channels.

 Record the test result in Table 8.

5-34 Performance Verification Rev. B

b. Channel 1, Channel 2, Expand A:1 and Expand B:2

 For LC684D recall LC684P037.PNL, for LC684DM recall

LC684P038.PNL, for LC684DL recall LC684P039.PNL or for LC684DXLrecall
LC684P040.PNL or make the following changes :

Channels Trace ON Channel 1, Channel 2
Zoom+Math Trace ON A, B, D

Select Math Setup

Redefine A : A=1
Use Math? : No
Trace A is Zoom of 1
Redefine C : C=1-1
Use Math? : Yes
Math Type : Arithmetic
Difference : 1 minus 1

 Press Reset Zoom+Math

 Press Cursors/Measure

Select : Change Test Conditions

Rev. B

Performance Verification 5-35

On line 3 : Test on Mask
True if all points of A are inside mask D
On line 4 : Test on Mask
True if all points of B are inside mask D

 Select Modify Mask

From : W'form

Into : M1
Use W'form : C

 To start the test, select Cursors/Measure, Change Test Conditions,

Modify Mask and press Make Mask M1

 After 200 sweeps for LC684D, or after 50 sweeps for LC684DM, or after

10 sweeps for LC684DL or LC684DXL check that the number of Passed equals
the number of Sweeps on Ch1, Ch2, A:1 and B:2.

 Record the test result in Table 8.

5-36 Performance Verification Rev. B

c. Channel 3, Channel 4, Expand A:3 and Expand B:4

 For LC684D recall LC684P041.PNL, for LC684DM recall

LC684P042.PNL, for LC684DL recall LC684P043.PNL or for LC684DXL recall
LC684P044.PNL or make the following changes :

Channels Trace ON Channel 3, Channel 4
Select Math Setup

Redefine A : A=3
Use Math? : No
Trace A is Zoom of 3
Redefine B : B=4
Use Math? : No
Trace A is Zoom of 4

 Press Reset Zoom+Math

 Press Cursors/Measure

Select : Change Test Conditions

Rev. B

Performance Verification 5-37

On line 1 : Test on Mask
True if all points of 3 are inside mask D
On line 2 : Test on Mask
True if all points of 4 are inside mask D

 To start the test, select Cursors/Measure, Change Test Conditions,

Modify Mask and press Make Mask M1

 After 200 sweeps for LC684D, or after 50 sweeps for

LC684DM, or 10 sweeps for LC684DL or LC684DXL check that the number of
Passed equals the number of Sweeps on Ch3, Ch4, A:3 and B:4.

 Record the test result in Table 8.

5-38 Performance Verification Rev. B

5.7 DC Accuracy

≤ ±5 % of full scale at 2mV/div, with 0 mV offset.
≤ ±3 % of full scale at 5mV/div, with 0 mV offset.
≤ ±2 % of full scale at 10mV/div and above, with 0 mV offset.

Specification

Description

It requires a DC source with a voltage range of 0 V to 20 V adjustable in steps of no
more than 15 mV, and a calibrated DMM that can measure voltage to 0.1 %.

This test measures the DC Accuracy within the gain range specified.

Measurements are made using voltage values applied by the external

voltage reference source, measured by the DMM, and in the oscilloscope using the
parameters Std voltage.
For each known input voltage, the deviation is checked against the tolerance.

5.7.1 Positive DC Accuracy
a. DC 50Ω

Procedure

 Recall LC684P045.PNL or configure the DSO :
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input offset : 0.0 mV on all 4 Channels
Input gain : from 2mV/div to 1 V/div. (see Table 9) on all 4 Ch
Trigger setup : Edge
Trigger on : Line
Slope line : Positive
Mode : Auto
Time base : 2 msec/div.
Channel use : 4
Record up to : 25 k
Channels Trace OFF Channel 1, Channel 2, Channel 3 & Channel 4
Zoom+Math Trace ON A, B, C & D
Select Math Setup
For Math : Use at most 5000 points
Redefine A, B, C, D Channel 1, Channel 2, Channel 3 & Channel 4
Use Math ? : Yes
Math Type : Average
Avg. Type : Summed
For : 100 sweeps
Cursors/Measure : Parameters

Rev. B

Performance Verification 5-39

Mode : Custom
Statistics : off

Change parameters
On line 1 : Measure mean of A

On line 2 : Measure mean of B
On line 3 : Measure mean of C
On line 4 : Measure mean of D

 For the low sensitivities: 2 mV, 5 mV, 10 mV and 20 mV/div., connect the test
equipment as shown in Figure 5-1.

LC584AL 1GHzOscilloscope

Figure 5-1 : DC 50Ω Accuracy Equipment Setup for 2, 5, 10 and 20 mV/div

 For the sensitivities : 50 mV and 100 mV/div, connect the test equipment as
shown in Figure 5-2.

 For the range 1 V/div no attenuator is required, connect the test equipment as
shown in Figure 5-3.

5-40 Performance Verification Rev. B

LC584AL 1GHz Oscilloscope

Figure 5-2 : DC 50Ω Accuracy Equipment Setup for 50 and 100 mV/div

LC584AL 1GHz Oscilloscope

Rev. B

Figure 5-3 : DC 50Ω Accuracy Equipment Setup for 1 V/div.

Performance Verification 5-41

 For each DSO Volts/div, set the output of the external DC voltage reference
source as shown in Table 9, column PS output.

1) Connect the DMM and record the voltage reading in Table 9, column DMM.

2) Disconnect the DMM from the BNC T connector.

3) Press Clear Sweeps

4) After 100 sweeps, read off the DSO mean parameter, and record the
measurement in Table 9, column Mean.

 For each DC voltage applied to the DSO input, repeat parts 1), 2), 3) and 4).
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 9, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

 Repeat step 5.7.1.a. for the other channels, substituting channel controls and
input connector.

5-42 Performance Verification Rev. B

b. DC 1MΩ

Procedure

5.7.1.a. and make the following change :

 Recall LC684P046.PNL or configure the DSO as shown in

 For 5 mV/div., connect the test equipment as shown in Figure 5-4.

Input gain : 5mV/div, 0.1 V/div, and 5V/dv (see Table 10) on all 4 Ch
Input Coupling : DC 1MΩ on all 4 Channels

LC584AL 1GHz Oscilloscope

Figure 5-4: DC 1MΩ Accuracy Equipment Setup for 5 mV/div.

 For 100 mV/div, connect the test equipment as shown in Figure 5-5.
 For 5V/div no attenuator is required, connect the test equipment as shown in

Figure 5-6.

Rev. B

Performance Verification 5-43

LC584AL 1GHz Oscilloscope

Figure 5-5 : DC 1MΩ Accuracy Equipment Setup for 100 mV/div

LC584AL 1GHzOscilloscope

Figure 5-6 : DC 1MΩ Accuracy Equipment Setup for 5V/div.

5-44 Performance Verification Rev. B

 For each DSO Volts/div, set the output of the external DC voltage reference
source as shown in Table 10, column PS output.

1) Connect the DMM and record the voltage reading in Table 10, column DMM.

2) Disconnect the DMM from the BNC T connector.

3) Press Clear Sweeps

4) After 100 sweeps, read off the DSO mean parameter, and record the
measurement in Table 10, column Mean.

 For each DC voltage applied to the DSO input, repeat parts 1), 2), 3) and 4).
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 10, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

 Repeat step 5.7.1.b. for the other channels, substituting channel controls and
input connector.

Rev. B

Performance Verification 5-45

5.7.2 Negative DC Accuracy
a. DC 50Ω

 Recall LC684P045.PNL or configure the DSO as shown in 5.7.1.a.
 Connect the test equipment as shown in either Figure 5-1 or 5-2 or 5-3.

 For each DSO Volts/div, set the output of the external DC voltage reference
source as shown in Table 11, column PS output. (if a banana-BNC adapter is

being used it can simply be turned to get the opposite polarity)

1) Connect the DMM and record the voltage reading in Table 11, column DMM.

2) Disconnect the DMM from the BNC T connector.

3) Press Clear Sweeps

4) After 100 sweeps, read off the DSO mean parameter, and record the
measurement in Table 11, column Mean.

 For each DC voltage applied to the DSO input, repeat parts 1), 2), 3) and 4).
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 11, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

 Repeat step 5.7.2.a. for the other channels, substituting channel controls and
input connector.

5-46 Performance Verification Rev. B

b. DC 1 MΩ

5.7.1.a. and make the following change :

 Recall LC684P046.PNL or configure the DSO as shown in

Input gain : 5mV/div, 0.1 V/div, and 5V/dv (see Table 12) on all 4 Ch

 Connect the test equipment as shown in either Figure 5-4 or 5-5 or 5-6.
 For each DSO Volts/div, set the output of the external DC voltage reference

source as shown in Table 12, column PS output.

 For each DC voltage applied to the DSO input, repeat parts 1), 2), 3) and 4).
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 12, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

 Repeat step 5.7.2.b. for the other channels, substituting channel controls and
input connector.

Input Coupling : DC 1 MΩ on all 4 Channels

1) Connect the DMM and record the voltage reading in Table 12, column DMM.

2) Disconnect the DMM from the BNC T connector.

3) Press Clear Sweeps

4) After 100 sweeps, read off the DSO mean parameter, and record the
measurement in Table 12, column Mean.

Rev. B

Performance Verification 5-47

5.8 Offset Accuracy

Offset range at 2 mV/div: ±0.4Volt, Accuracy ≤ ±4.8 mV (5% of FS + 1% of offset).
Offset range at 5 mV/div: ±1Volt, Accuracy ≤ ±11.2 mV (3% of FS +1% of offset).

Specifications

Description

The offset test is done at 2 mV/div and 5 mV/div for 50Ω and at 5 mV/div for 1MΩ
coupling, with a signal of ±0.4 Volt or ±1 Volt cancelled by an offset of the other
polarity.

5.8.1 Positive Offset Accuracy

a. DC 50Ω

Procedure

 Recall LC684P047.PNL or configure the DSO:
Panel Setups : Recall FROM DEFAULT SETUP

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 2mV/div on all 4 Channels
Input offset : +0.4 Volt on all 4 Channels
Trigger setup : Edge
Trigger on : Line
Coupling 1 : DC
Mode : Auto
Time base : 2 msec/div.
Channel use : 4

Record up to : 25 k
Channels Trace OFF Channel 1, Channel 2, Channel 3 & Channel 4

Zoom+Math Trace ON A, B, C & D
Select Math Setup
For Math : Use at most 5000 points
Redefine A, B, C, D Channel 1, Channel 2, Channel 3 & Channel 4
Use Math ? : Yes
Math Type : Average
Avg. Type : Summed
For : 100 sweeps

Cursors/Measure : Parameters
Mode : Custom
Statistics : off

Change parameters

5-48 Performance Verification Rev. B

On line 1 : Measure mean of A
On line 2 : Measure mean of B
On line 3 : Measure mean of C
On line 4 : Measure mean of D

 Connect the test equipment as shown in Figure 5-7.

LC584AL 1GHzOscilloscope

Figure 5-7 : Offset Accuracy Equipment Setup

 Set the output of the external DC voltage reference source to −0.4 Volt.

1) Verify that the displayed trace A : Average (1) is on the screen, near the center

horizontal graticule line. If the trace is not visible, modify the DC voltage

reference source output until the trace is within ± 2 divisions of center.

2) Connect the DMM and record the voltage reading in Table 13, column DMM.

3) Disconnect the DMM from the BNC T connector.

4) Press Clear Sweeps

5) After 100 sweeps, Read off the DSO Mean parameter voltage, and record the
measurement in Table 13, column Mean.

 Repeat the test for the other channels, substituting channel controls and input
connector. Record the measurements in Table 13.

Rev. B

Performance Verification 5-49

 Set DSO input gain to 5 mv/div and DSO Offset to +1 Volt on all 4

Channels.

 Set the output of the external DC voltage reference source to −1 Volt.
 Repeat steps 1), 2), 3), 4) and 5) on all 4 Channels.
 Record the measurements in Table 13.

 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading.

 Record the test result in Table 13, and compare the Difference ( ∆ ) to the

corresponding limit in the test record.

5-50 Performance Verification Rev. B

b. DC 1MΩ

Procedure

for each Channel make the following change :

 Recall LC684P048.PNL or configure the DSO as shown in 5.8.1.a. and

Input Coupling : DC 1MΩ on all 4 Channels

Input gain : 5mV/div on all 4 Channels
Input offset : +1 Volt on all 4 Channels
 Connect the test equipment as shown in Figure 5-7.

 Set the output of the external DC voltage reference source to −1 Volt.

1) Verify that the displayed trace A : Average (1) is on the screen, near the center

horizontal graticule line. If the trace is not visible, modify the DC voltage

reference source output until the trace is within ± 2 divisions of center.

2) Connect the DMM and record the voltage reading in Table 13, column DMM.

3) Disconnect the DMM from the BNC T connector.

4) Press Clear Sweeps

5) After 100 sweeps, Read off the DSO Mean parameter voltage, and record the

measurement in Table 13, column Mean.

 Repeat the test for the other channels, substituting channel controls and input
connector. Record the measurements in Table 13.

 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading.

 Record the test result in Table 13, and compare the Difference ( ∆ ) to the

corresponding limit in the test record.

Rev. B

Performance Verification 5-51

5.8.2 Negative Offset Accuracy

a. DC 50Ω

Procedure

 Recall LC684P049.PNL or configure the DSO as shown in 5.8.1.a. and
for each Channel make the following change :

Input offset : −0.4 Volt on all 4 Channels

 Connect the test equipment as shown in Figure 5-7.
 Set the output of the external DC voltage reference source to +0.4 Volt.

5-52 Performance Verification Rev. B

1) Verify that the displayed trace A : Average (1) is on the screen, near the center

horizontal graticule line. If the trace is not visible, modify the DC voltage

reference source output until the trace is within ± 2 divisions of center.

2) Connect the DMM and record the voltage reading in Table 14, column DMM.

3) Disconnect the DMM from the BNC T connector.

4) Press Clear Sweeps

5) After 100 sweeps, Read off the DSO Mean parameter voltage, and record the

measurement in Table 14, column Mean.

 Repeat the test for the other channels, substituting channel controls and input
connector. Record the measurements in Table 14.

 Set DSO input gain to 5 mv/div and DSO Offset to −1 Volt on all 4

Channels.

 Set the output of the external DC voltage reference source to +1 Volt.
 Repeat steps 1), 2), 3), 4) and 5) on all 4 Channels.
 Record the measurements in Table 14.

 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the
DSO mean voltage reading. Record the test result in Table 14, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

b. DC 1MΩ

for each Channel make the following changes :

 Recall LC684P050.PNL or configure the DSO as shown in 5.8.1.a. and

Input Coupling : DC 1MΩ on all 4 Channels

Input Gain : 5 mV/div on all 4 Channels
Input offset : −1 Volt on all 4 Channels

 Connect the test equipment as shown in Figure 5-7.

 Set the output of the external DC voltage reference source to +1 Volt.

1) Verify that the displayed trace A : Average (1) is on the screen, near the center

horizontal graticule line. If the trace is not visible, modify the DC voltage

reference source output until the trace is within ± 2 divisions of center.

2) Connect the DMM and record the voltage reading in Table 14, column DMM.

3) Disconnect the DMM from the BNC T connector.

Rev. B

Performance Verification 5-53

4) Press Clear Sweeps

5) After 100 sweeps, Read off the DSO Mean parameter voltage, and record the

measurement in Table 14, column Mean.

connector. Record the measurements in Table 14.
 Calculate the Difference ( ∆ ) by subtracting the DMM voltage reading from the

DSO mean voltage reading. Record the test result in Table 14, and
compare the Difference ( ∆ ) to the corresponding limit in the test record.

5-54 Performance Verification Rev. B

 Repeat the test for the other channels, substituting channel controls and input

5.9 Bandwidth

5.9.1 Description

The purpose of this test is to ensure that the entire system has a bandwidth of at
least 1.5 GHz. An external source is used as the reference to provide a signal
where amplitude and frequency are well controlled.
The amplitude of the generator as a function of frequency and power is calibrated
using an HP8482A sensor on an HP437B power meter or equivalent.

50Ω : DC to at least 1.5 GHz (−3 dB) at 10 mV/div. and above.
1MΩ : DC to 500 MHz typical at 100 mV/div.

Specifications

a. DC 50Ω

 Recall LC684P051.PNL or configure the DSO :

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 50 mV/div on all 4 Channels
Input offset : 0 mV on all 4 Channels
Trigger setup : Edge
Trigger on : Line
Slope line : Pos
Mode : Auto
Time base : 1 µsec/div.
Channel use : 4
Record up to : 25 k
Cursors/Measure : Parameters
Mode : Custom
Statistics : On
Change parameters
On line 1 : Sdev of 1
On line 2 : Sdev of 2
On line 3 : Sdev of 3
On line 4 : Sdev of 4

Panel Setups : Recall FROM DEFAULT SETUP

 Zero and calibrate the HP8482A power sensor using the power meter Power
Ref output.

 Connect a BNC adapter to the HP8482A power sensor.

 Connect the HP8482A power sensor to the power meter.

Rev. B

Performance Verification 5-55

 Connect a 5ns 50Ω BNC cable to the RF output of the HP8648B

generator and then through a 6dB attenuator and the necessary adapters to the
power sensor.

Figure 5-8 : Power Meter Equipment Setup

 Set the generator frequency to 300 kHz

 Read the displayed generator output amplitude, and record it in the third
column of Table 15.

 Repeat the above measurement for 1.1 MHz, 30.1 MHz, 300.1 MHz, 700.1 MHz,

 Disconnect the RF output of the HP8648B generator from the HP8482A power
sensor.

5ns 50 Ohm BNC cable and a 6 dB attenuator into Channel 1.
 Set the generator frequency to 300 kHz.
 From the generator, apply the recorded generator signal amplitude to

Channel 1.
 Press Clear Sweeps.

 Set the generator amplitude to measure 0.200 mW on the power meter.

1000.1 MHz. & 1500.1 MHz Record the generator output amplitude readout in the

third column of Table 15.

 Connect the RF output of the HP8648B generator through a

5-56 Performance Verification Rev. B

LC584AL 1GHz Oscilloscope

Figure 5-9 : 50Ω Bandwidth Equipment Setup

 Measure for at least 100 sweeps, record the average value of sdev(1) inTable15
 Repeat the above 3 steps for Channel 2, Channel 3 & Channel 4 substituting

channel controls and input connector. Record the measurements in Table 15.
 Repeat the above measurement for all channels for 1.1 MHz, 30.1 MHz,

300.1 MHz, 700.1 MHz, 1000.1 MHz and 1500.1 MHz and record the values in

Table 15.

 Calculate the ratio to .3 MHz for each frequency, sdev1.1/sdev0.3, sdev30.1/sdev0.3

...

sdev1500.1/sdev0.3, and compare the results to the limits in the test record.

Rev. B

Performance Verification 5-57

 Recall LC684P052.PNL or configure the DSO as shown in 5.9.1.a. and

for each Channel make the following change :
Input gain : 100mV/div
 Connect the test equipment as shown in Figure 5-8.
 Set the generator frequency to 300 kHz

 Set the generator amplitude to measure 0.800 mW on the power meter.

 Read the displayed generator output amplitude, and record it in the third
column of Table 16.

 Repeat the above measurement for 1.1 MHz, 30.1 MHz, 300.1 MHz, 700.1

MHz,1000.1 MHz & 1500.1 MHz. Record the generator output amplitude readout

in the third column of Table 16.

 Disconnect the RF output of the HP8648B generator from the HP8482A power
sensor.

 Connect the test equipment as shown in Figure 5-9.
 Set the generator frequency to 300 kHz.
 From the generator, apply the recorded generator signal amplitude to

Channel 1.
 Press Clear Sweeps.

 Repeat the above 3 steps for Channel 2, Channel 3 & Channel 4 substituting
channel controls and input connector. Record the measurements in Table 16.

 Repeat the above measurement for all channels for 1.1 MHz, 30.1 MHz,

 Calculate the ratio to .3 MHz for each frequency, sdev

...

 Measure for at least 100 sweeps, record the average value of sdev(1) inTable16

300.1 MHz, 700.1 MHz, 1000.1 MHz , 1500.1 MHz and record the values in Table

16.

1.1/sdev0.3, sdev30.1/sdev0.3

sdev1500.1/sdev0.3, and compare the results to the limits in the test record.

5-58 Performance Verification Rev. B

b. DC 50Ω with Bandwidth Limiter On

Panel Setups : Recall FROM DEFAULT SETUP
Channels Trace ON Channel 1
Input Coupling : DC 50Ω
Global BWL : 25 MHz
Input gain : 100 mV/div.
Input offset : 0 mV
Trigger setup : Edge
Trigger on : 1
Slope line : Pos
Mode : Auto
Time base : 1 µsec/div.
Channel use : 4
Record up to : 25 k
Cursors/Measure : Parameters
Mode : Custom
Statistics : Off
Change parameters
On line 1 : Sdev of 1
On line 2 : Freq of 1

 Connect the test equipment as shown in Figure 5-9.
 Set the generator frequency to 300 kHz.
 Adjust the generator signal amplitude to measure sdev(1) = 200 mV.
 Set Time base : 50 nsec/div.
 Increase the generator frequency until sdev(1) = 140 mV. (typically 25 MHz)
 Press Clear Sweeps
 When sdev(1) = 140 mV, record Freq(1) in Table 17.
 Check that the frequency is within the limits specified in Table 17.

 Recall LC684P053.PNL or configure the DSO

Rev. B

Performance Verification 5-59

5-60 Performance Verification Rev. B

 Set Global BWL : 200 MHz
 Set Timebase : 5 nsec/div.

 Increase the generator frequency until sdev(1) = 140 mV. (typically 200 MHz)

 Press Clear Sweeps

 Repeat the 25 MHz and 200 MHz Bandwidth limiter tests for the other channels,
substituting channel controls and input connector.

 Recall LC684P054.PNL for Channel 2, LC684P055.PNL for Channel3
LC684P056.PNL for Channel 4, or configure the DSO as shown in 5.9.1.b. and
make the necessary changes.

 Record the test results in Table 17, and compare the results to the limits.

 When sdev(1) = 140 mV, record Freq(1) in Table 17.

Rev. B

Performance Verification 5-61

5.9.2 DC 1MΩ

 Recall LC684P057.PNL or configure the DSO :

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 1MΩ on all 4 Channels
Input gain : 100 mV/div. on all 4 Channels
Input offset : 0 mV on all 4 Channels
Trigger setup : Edge
Trigger on : Line
Slope line : Pos
Mode : Auto
Time base : 1 µsec/div.
Channel use : 4
Record up to : 25 k

Cursors/Measure : Parameters
Mode : Custom
Statistics : On
Change parameters
On line 1 : Sdev of 1
On line 2 : Sdev of 2
On line 3 : Sdev of 3
On line 4 : Sdev of 4

Panel Setups : Recall FROM DEFAULT SETUP

 Connect the test equipment as shown in Figure 5-10.

Figure 5-10 : 1MΩ Bandwidth Equipment Setup

 Set the generator frequency to 300 kHz.

5-62 Performance Verification Rev. B

 Adjust the generator signal amplitude to measure sdev(1) = 200 mV.

 Disconnect the coaxial cable from the 4962-10 adapter. Connect the test
equipment as shown in Figure 5-11.

Power Sensor

Figure 5-11 : Power Meter Equipment Setup

Rev. B

Performance Verification 5-63

 Record the displayed power meter value in mW.

 Set the generator frequency to 500.1 MHz.

 Now fine adjust the generator amplitude output until the power meter readout

indicates the value measured just above at 300 kHz.

 Reconnect the signal generator to DSO Channel 1, as shown in Figure 5-10.
 Press Clear Sweeps.

in Table 18.
 Repeat the above steps for Channel 2, Channel 3 & Channel 4, substituting

channel controls and input connector.
 Record the sdev measurements in Table 18.
 Calculate the ratio sdev

against the limits shown in the test record.

 Measure for at least 100 sweeps, record the average value of sdev(1)

500.1/sdev0.3 for each Channel, and test each value

5-64 Performance Verification Rev. B

5.10 Trigger Level

5.10.1 Description

The trigger capabilities are tested for several cases of the standard edge trigger:

 Channel (internal), and External Trigger sources
 Three DC levels: −3, 0, +3 major screen divisions
 DC, HFREJ coupling
 Positive and negative slopes

5.10.2 Channel Trigger at 0 Division Threshold
a. DC Coupling

Recall LC684P058.PNL or configure the DSO:

Channels Trace ON Channel 1, Channel 2, Channel 3 & Channel 4
Input Coupling : DC 50Ω on all 4 Channels
Input gain : 100 mV/div. on all 4 Channels
Input offset : 0 mV on all 4 Channels (use show status to verify)

Trigger setup : Edge
Trigger on : 1
Slope 1 : Pos
Coupling : DC
Mode : Auto
Set Trigger level : DC 0.0 mV
Pre-Trigger Delay : 50 %

Time base : 0.1 msec/div.
Record up to : 50 k samples

Channels Trace OFF Channel 1, Channel 2, Channel 3 & Channel 4
Zoom+Math Trace ON A, B, C & D

Select Math Setup
For Math : Use at most 5000 points
Redefine A, B, C, D Channel 1, Channel 2, Channel 3 & Channel 4
Use Math ? : Yes
Math Type : Average
Avg. Type : Summed
For : 10 sweeps

 Set the output of the LeCroy LW420 or equivalent audio frequency signal
generator to 1 kHz.

Panel Setups : Recall FROM DEFAULT SETUP

Rev. B

Performance Verification 5-65

 Connect the output of the generator to Channel 1 through a 50 Ohm coaxial
cable and adjust the sine wave output amplitude to get 8 divisions peak to

peak .
 Select Cursors/Measure : Cursors, Time, Absolute
 Use the "cursor position" knob, to move the Time marker at 0.0 µs

 Press Clear Sweeps,

 Acquire 10 sweeps and record in Table 19 the level readout displayed below
100 mV in the icon 1, at top left.

 Compare the test results to the corresponding limit in the test record.

 Set Trigger Slope 1 : Neg
 Acquire 10 sweeps and record in Table 19 the level readout displayed below

100 mV in the icon 1, at top left.

5-66 Performance Verification Rev. B