Lattice Semiconductor Corporation MACH445-20YC, MACH445-15YC Datasheet

FINAL

COM’L: -12/15/20

MACH445-12/15/20

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

■ 100-pin version of the MACH435 in PQFP

■ 5 V, in-circuit programmable

■ JTAG, IEEE 1149.1 JTAG testing capability

■ 128 macrocells

■ 12 ns t

■ 83 MHz f

■ 70 inputs with pull-up resistors

■ 64 outputs

■ 192 flip-flops

— 128 macrocell flip-flops
— 64 input flip-flops

PD

CNT

GENERAL DESCRIPTION

The MACH445 is a member of the high-performance
EE CMOS MACH 4 family. This device has approxi­mately twelve times the macrocell capability of the
popular PAL22V10, with significant density and func­tional features that the PAL22V10 does not provide. It is
architecturally identical to the MACH435, with the
addition of JTAG and 5-V programming features.

The MACH445 consists of eight PAL blocks intercon­nected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to I/O pins.

The MACH445 has macrocells that can be configured
as synchronous or asynchronous. This allows
designers to implement both synchronous and

■ Up to 20 product terms per function, with XOR

■ Flexible clocking

— Four global clock pins with selectable edges
— Asynchronous mode available for each

■ 8 “PAL33V16” blocks

■ Input and output switch matrices for high

routability

■ Fixed, predictable, deterministic delays

■ JEDEC-file compatible with MACH435

■ Zero-hold-time input register option

asynchronous logic together on the same device. The
two types of design can be mixed in any proportion,
since the selection on each macrocell affects only that
macrocell.

Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.

The MACH445 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.

All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.

Lattice Semiconductor

macrocell

Publication# 17468 Rev. E Amendment/0
Issue Date: May 1995

BLOCK DIAGRAM

I2, I5

2

8

8

I/O Cells

I/O Cells

16

Matrix

8

Output Switch

8

4

Clock Generator

16

Matrix

8

Output Switch

8

4

Clock Generator

16

16

16

4

16

16

4

16

Input Switch

16

Macrocells

OE

Input Switch

16

Macrocells

OE

Input Switch

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

24

33

24

33

24

33

33

Central Switch Matrix

Input Switch

Matrix

24

66 X 90

Input Switch

Matrix

24

66 X 90

Input Switch

Matrix

24

16

AND Logic Array

and Logic Allocator

OE

4

16

AND Logic Array

and Logic Allocator

OE

4

16

16

16

Macrocells

8

4

Clock Generator

16

16

16

Macrocells

8

4

Clock Generator

16

16

Matrix

8

Output Switch

4

Matrix

8

Output Switch

4

8

I/O Cells

8

I/O Cells

I/O32–I/O39I/O40–I/O47I/O48–I/O55I/O56–I/O63

Block A Block B Block C Block D

I/O0–I/O7 I/O8–I/O15 I/O16–I/O23 I/O24–I/031

8

8

8

I/O Cells

4

Clock Generator

8

I/O Cells

4

Clock Generator

Matrix

16

Output Switch

8

4

16

16

Matrix

16

Output Switch

8

4

16

Macrocells

OE

Input Switch

16

Macrocells

OE

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

33

24

33

4

4

CLK0/I0, CLK1/I1, 

CLK2/I3, CLK3/I4

33

Input Switch

24

33

66 X 90

AND Logic Array

and Logic Allocator

OE

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

OE

4

16

16

16

Macrocells

4

Clock Generator

16

16

16

Macrocells

4

Clock Generator

Matrix

8

Output Switch

8

4

Matrix

8

Output Switch

8

4

8

I/O Cells

8

I/O Cells

17468E-1

Block H Block G Block F Block E

2 MACH445-12/15/20

CONNECTION DIAGRAM MACH445 (MACH435)
Top View

PQFP

BLOCK A

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

VCC

GND

GND

99

98

97969594939291908988878685

100

GND
GND

TDI

I/O8
I/O9

I/O10

BLOCK B

I/O11
I/O12
I/O13
I/O14
I/O15

I0/CLK0

VCC
VCC

GND
GND

I1/CLK1

I/O16
I/O17
I/O18
I/O19
I/O20
I/O21

BLOCK C

I/O22
I/O23

TMS

TCK
GND
GND

I5

1

(9)

(8)

(7)

(6)

(5)

(4)

(10)

2

(3)

3

(83)

4

(12)

5

(13)

6

(14)

7

(15)

8

(16)

9

(17)

10

(18)

11

(19)

12

(20)

13
14

15
16

17

(23)

18

(24)

19

(25)

20

(26)

21

(27)

22

(28)

23

(29)

24

(30)

25

(31)

26
27
28
29
30

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

31323334353637383940414243444546474849

VCC

(82)

(45)

I/O63

BLOCK H

I/O62

I/O61

I/O60

I/O59

84

(81)

(80)

(79)

(78)

(46)

(47)

(48)

(49)

I/O58

I/O57

828183

(77)

(76)

(73)
(72)
(71)
(70)
(69)

(68)
(67)
(66)
(65)

(62)
(61)
(60)
(59)

(58)
(57)
(56)
(55)
(54)

(41)

(50)

(51)

I/O56

80

(75)

79
78
77
76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60

59
58
57
56
55
54
53
52
51

(52)

50

GND
GND
TD0
TRST*
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND

VCC
VCC

I3/CLK2
I/O47
I/O46
I/O45

I/O44
I/O43
I/O42
I/O41
I/O40
I2
ENABLE*
GND
GND

BLOCK G

BLOCK F

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage

I/O24

I/O25

I/O26

BLOCK D

I/O28

I/O27

I/O29

I/O30

VCC

I/O31

GND

GND

VCC

I/O32

I/O33

I/O34

I/O35

I/O36

BLOCK E

I/O37

I/O38

I/O39

17468E-2

3MACH445-12/15/20

ORDERING INFORMATION
Commercial Products

Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:

MACH 445 -12 Y C

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

DEVICE NUMBER

445 = 2nd Generation, 128 Macrocells, 100 Pins

SPEED

-12 = 12 ns t

-15 = 15 ns t

-20 = 20 ns t

PD
PD
PD

Valid Combinations

MACH445-12
MACH445-15
MACH445-20

YC

OPTIONAL PROCESSING

Blank = Shipped in Trays

OPERATING CONDITIONS

C = Commercial (0

PACKAGE TYPE

Y = 100-Pin Plastic Quad Flat Pack

(PQR100)

Valid Combinations

The Valid Combinations table lists configurations
planned to be supported in volume for this device. Con­sult your local sales office to confirm availability of
specific valid combinations and to check on newly re­leased combinations.

°C to +70°C)

4 MACH445-12/15/20

FUNCTIONAL DESCRIPTION

The MACH445 consists of eight PAL blocks connected
by a central switch matrix. There are 64 I/O pins and 6
dedicated input pins feeding the central switch matrix.
These signals are distributed to the eight PAL blocks for
efficient design implementation. There are 4 global
clock pins that can also be used as dedicated inputs.

All inputs and I/O pins have built-in pull-up resistors.
While it is always good design practice to tie unused
pins high, the pull-up resistors provide design security
and stability in the event that unused pins are left
disconnected.

The PAL Blocks

Each PAL block in the MACH445 (Figure 1) contains a
clock generator, a 90-product-term logic array, a logic
allocator, 16 macrocells, an output switch matrix, 8 I/O
cells, and an input switch matrix. The central switch
matrix feeds each PAL block with 33 inputs. This makes
the PAL block look effectively like an independent
“PAL33V16” with 8 to 16 buried macrocells.

In addition to the logic product terms, individual output
enable product terms and two PAL block initialization
product terms are provided. Each I/O pin can be
individually enabled. All flip-flops that are in the
synchronous mode within a PAL block are initialized
together by either of the PAL block nitialization
product terms.

The Central Switch Matrix and Input
Switch Matrix

The MACH445 central switch matrix is fed by the input
switch matrices in each PAL block. Each PAL block
provides 16 internal feedback signals, 8 registered input
signals, and 8 I/O pin signals to the input switch matrix.
Of these 32 signals, 24 decoded signals are provided to
the central switch matrix by the input switch matrix. The
central switch matrix distributes these signals back to
the PAL blocks in a very efficient manner that provides
for high performance. The design software automati­cally configures the input and central switch matrices
when fitting a design into the device.

The Clock Generator

Each PAL block has a clock generator that can generate
four clock signals for use throughout the PAL block.
These four signals are available to all macrocells and
I/O cells in the PAL block, whether in synchronous or
asynchronous mode. The clock generator chooses the
four signals from the eight possible signals given by the
true and complement versions of the four global clock
pin signals.

The Product-Term Array

The MACH445 product-term array consists of 80
product terms for logic use, eight product terms for
output enable use, and two product terms for global PAL
block initialization. Each macrocell has a nominal
allocation of 5 product terms for logic, although the logic
allocator allows for logic redistribution. Each I/O pin has
its own individual output enable term. The initialization
product terms provide asynchronous reset or preset to
synchronous-mode macrocells in the PAL block.

The Logic Allocator

The logic allocator in the MACH445 takes the 80 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 20
product terms in synchronous mode, or 18 product
terms in asynchronous mode. When product terms are
routed away from a macrocell, all 5 product terms may
be redirected, which precludes the use of the macrocell
for logic generation. It is possible to redirect only 4
product terms, leaving one for simple function genera­tion. The design software automatically configures the
logic allocator when fitting the design into the device.

The logic allocator also provides an exclusive-OR gate.
This gate allows generation of combinatorial exclusive­OR logic, such as comparison or addition. It allows
registered exclusive-OR functions, such as CRC gen­eration, to be implemented more efficiently. Emulating
all flip-flop types with a D-type flip-flop is also made
possible. Register type emulation is automatically
handled by the design software.

Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.

5MACH445-12/15/20

Table 9. Logic Allocation

Macrocell Available Clusters

M0 C0, C1, C2
M1 C0, C1, C2, C3
M2 C1, C2, C3, C4
M3 C2, C3, C4, C5
M4 C3, C4, C5, C6
M5 C4, C5, C6, C7
M6 C5, C6, C7, C8
M7 C6, C7, C8, C9
M8 C7, C8, C9, C10
M9 C8, C9, C10, C11
M10 C9, C10, C11, C12
M11 C10, C11, C12, C13
M12 C11, C12, C13, C14
M13 C12, C13, C14, C15
M14 C13, C14, C15
M15 C14, C15

The Macrocell and Output Switch Matrix

The MACH445 has 16 macrocells, half of which can
drive I/O pins; this selection is made by the output switch
matrix. Each macrocell can drive one of four I/O cells.
The allowed combinations are shown in Table 2. Please
refer to Figure 1 for macrocell and I/O pin
numbers.

Table 2. Output Switch Matrix Combinations

Macrocell Routable to I/O Pins

M0, M1 I/O5, I/O6, I/O7, I/O0
M2, M3 I/O6, I/O7, I/O0, I/O1
M4, M5 I/O7, I/O0, I/O1, I/O2
M6, M7 I/O0, I/O1, I/O2, I/O3
M8, M9 I/O1, I/O2, I/O3, I/O4
M10, M11 I/O2, I/O3, I/O4, I/O5
M12, M13 I/O3, I/O4, I/O5, I/O6
M14, M15 I/O4, I/O5, I/O6, I/O7

I/O Pin Available Macrocells

I/O0 M0, M1, M2, M3, M4, M5, M6, M7

I/O1 M2, M3, M4, M5, M6, M7, M8, M9
I/O2 M4, M5, M6, M7, M8, M9, M10, M11
I/O3 M6, M7, M8, M9, M10, M11, M12, M13
I/O4 M8, M9, M10, M11, M12, M13, M14, M15
I/O5 M10, M11, M12, M13, M14, M15, M0, M1
I/O6 M12, M13, M14, M15, M0, M1, M2, M3
I/O7 M14, M15, M0, M1, M2, M3, M4, M5

The macrocells can be configured as registered,
latched, or combinatorial. In combination with the logic
allocator, the registered configuration can be any of the
standard flip-flop types. The macrocell provides internal
feedback whether configured with or without the flip­flop, and whether or not the macrocell drives an I/O cell.

The flip-flop clock depends on the mode selected for
the macrocell. In synchronous mode, any of the PAL
block clocks generated by the Clock Generator can be
used. In asynchronous mode, the additional choice of
either edge of an individual product-term clock is
available.

Initialization can be handled as part of a bank of
macrocells via the PAL block initialization terms if in
synchronous mode, or individually if in asynchronous
mode. In synchronous mode, one of the PAL block
product terms is available each for preset and reset. The
swap function determines which product term drives
which function. This allows initialization polarity com­patibility with the MACH 1 and 2 series. In asynchronous
mode, one product term can be used either to drive reset
or preset.

The I/O Cell

The I/O cell in the MACH445 consists of a three-state
buffer and an input flip-flop. The I/O cell is driven by one
of the macrocells, as selected by the output switch
matrix. Each I/O cell can take its input from one of eight
macrocells. The three-state buffer is controlled by an
individual product term. The input flip-flop can be
configured as a register or latch. Both the direct I/O
signal and the registered/latched signal are available to
the input switch matrix, and can be used simultaneously
if desired.

JTAG Testing

JTAG is the commonly used acronym for the IEEE
Standard 1149.1–1990. The JTAG standard defines
input and output pins, logic control functions, and
instructions. Lattice/Vantis has incorporated this stan­dard into the MACH445device.

The JTAG standard was developed as a means of
providing both board-level and device-level testing.

6 MACH445-12/15/20

Five-Volt Programming

Another benefit from the JTAG circuitry that we have
derived is the ability to use the JTAG port for five-volt
programming. This allows the device to be soldered to
the board before programming. Once the device is
attached, the delicate Plastic Quad Flat Pack, or PQFP,
leads are protected from programming and testing
operations that could potentially damage them. Pro­gramming and verification of the device is done serially
which is ideal for on-board programming since it only
requires the use of the Test Access Port. Use of the
programming Enable Pin (ENABLE*) is optional.

Zero-Hold-Time Input Register

The MACH445 device has a zero-hold time (ZHT) fuse.
This fuse controls the time delay associated with loading
data into all I/O cell registers and latches in the
MACH445 device.

When programmed, the ZHT fuse increases the data
path setup delays to input storage elements, matching
equivalent delays in the clock path. When the fuse is
erased, the setup time to the input storage element is
minimized and the device timing is compatible with the
MACH435 device.

This feature facilitates doing worst-case designs for
which data is loaded from sources which have low (or
zero) minimum output propagation delays from clock
edges.

7MACH445-12/15/20

16

CLK0/I0

CLK1/I1

Clock

Generator

4

CLK2/I3

CLK3/I4

Central Switch Matrix

C0

M0

C1

M1

C2

M2

C3

M3

C4

M4

C5

M5

C6

M6

C7

M7

C8

M8

Logic Allocator

C9

M9

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

M0

M1

M2

M3

M4

M5

M6

M7

M8

Output Switch Matrix

M9

I/O

O0

Cell

I/O

O1

Cell

I/O

O2

Cell

I/O

O3

Cell

I/O

O4

Cell

I/O0

I/O1

I/O2

I/O3

I/O4

17

24

Input

Switch

Matrix

C10

M10

C11

M11

C12

M12

C13

M13

C14

M14

C15

M15

16

16

Figure 1. MACH445 PAL Block

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

M10

M11

M12

M13

M14

M15

I/O

O5

Cell

I/O

O6

Cell

I/O

O7

Cell

I/O5

I/O6

I/O7

17468E-3

8 MACH445-12/15/20

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

CC

+0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the
functionality of the device is guaranteed.

) Operating

A

) with

CC

I/O Pin Voltage –0.5 V to VCC +0.5 V. . . . . . . . . . . . .

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current
(T

= 0°C to +70°C) 200 mA. . . . . . . . . . . . . . . . . . . .

A

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

IN = VIH or VIL

V

V

V

V

I

I

I
I

OL

I

IH

I

IL

OZH

OZL

SC

CC

IH

IL

Output LOW Voltage IOL = 24 mA, VCC = Min 0.5 V

V

= VIH or V

IN

(Note 1)

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 2)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 2)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA
Input LOW Leakage Current VIN = 0 V, V
Off-State Output Leakage V

= 5.25 V, VCC = Max

OUT

Current HIGH VIN = V
Off-State Output Leakage V

Current LOW V
Output Short-Circuit Current V
Supply Current V

= 0 V, VCC = Max

OUT

= V

IN

= 0.5 V, VCC = Max (Note 4) –30 –160 mA

OUT

= 0 V, Outputs Open (I

IN

V

= 5.0 V, f =25 MHz, TA = 25°C (Note 5)

CC

= Max (Note 3) –100 µA

CC

or VIL (Note 3)

IH

or VIL (Note 3)

IH

= 0 mA) 255 mA

OUT

10

–100

µA

µA

CAPACITANCE (Note 6)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

Notes:

1. Total I

for one PAL block should not exceed 128 mA.

OL

2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

3. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,

enabled, and reset.

6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where capacitance may be affected.

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

).

OZH

9MACH445-12 (Com’l)