Lattice Semiconductor Corporation MACH435Q-25JC, MACH435Q-20JC, MACH435-20JC, MACH435-15JC, MACH435-12JC Datasheet

FINAL

COM’L: -12/15/20, Q-20/25

MACH435-12/15/20, Q-20/25

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

■ 84 Pins in PLCC

■ 128 Macrocells

■ 12 ns tPD

■ 83.3 MHz fCNT

■ 70 Inputs with pull-up resistors

■ 64 Outputs

■ 192 Flip-flops

— 128 Macrocell flip-flops
— 64 Input flip-flops

■ Up to 20 product terms per function, with XOR

GENERAL DESCRIPTION

The MACH435 is a member of our high-performance
EE CMOS MACH 4 family. This device has approxi­mately twelve times the macrocell capability of the
popular PAL22V10, with significant density and func­tional features that the PAL22V10 does not provide.

The MACH435 consists of eight PAL blocks intercon­nected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to I/O pins.

The MACH435 has macrocells that can be configured
as synchronous or asynchronous. This allows designers
to implement both synchronous and asynchronous logic

■ Flexible clocking

— Four global clock pins with selectable edges
— Asynchronous mode available for each

macrocell

■ 8 “PAL33V16” blocks

■ Input and output switch matrices for high

routability

■ Fixed, predictable, deterministic delays

■ Pin compatible with MACH130, MACH131,

MACH230, and MACH231

together on the same device. The two types of design
can be mixed in any proportion, since the selection on
each macrocell affects only that macrocell.

Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.

The MACH435 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.

All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.

Lattice Semiconductor

Publication# 17469 Rev. E Amendment/0
Issue Date: May 1995

BLOCK DIAGRAM

I2, I5

2

8

8

I/O Cells

I/O Cells

16

Matrix

8

Output Switch

8

4

Clock Generator

16

Matrix

8

Output Switch

8

4

Clock Generator

16

16

16

4

16

16

4

16

Input Switch

16

Macrocells

OE

Input Switch

16

Macrocells

OE

Input Switch

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

24

33

24

33

24

33

33

Central Switch Matrix

Input Switch

Matrix

24

66 X 90

Input Switch

Matrix

24

66 X 90

Input Switch

Matrix

24

16

AND Logic Array

and Logic Allocator

OE

4

16

AND Logic Array

and Logic Allocator

OE

4

16

16

16

Macrocells

8

4

Clock Generator

16

16

16

Macrocells

8

4

Clock Generator

16

16

Matrix

8

Output Switch

4

Matrix

8

Output Switch

4

8

I/O Cells

8

I/O Cells



I/O32–I/O39I/O40–I/O47I/O48–I/O55I/O56–I/O63

I/O0–I/O7 I/O8–I/O15 I/O16–I/O23 I/O24–I/031

8

8

8

I/O Cells

4

Clock Generator

8

I/O Cells

4

Clock Generator

Matrix

16

Output Switch

8

4

16

16

Matrix

16

Output Switch

8

4

16

Macrocells

OE

Input Switch

16

Macrocells

OE

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

33

24

33

4

4

CLK0/I0, CLK1/I1, 

CLK2/I3, CLK3/I4

33

Input Switch

24

33

66 X 90

AND Logic Array

and Logic Allocator

OE

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

OE

4

16

16

16

Macrocells

4

Clock Generator

16

16

16

Macrocells

4

Clock Generator

Matrix

8

Output Switch

8

4

Matrix

8

Output Switch

8

4

8

I/O Cells

8

I/O Cells

17469E-1

2 MACH435-12/15/20, Q-20/25

CONNECTION DIAGRAM
Top View

CC

11
12
13
14
15
16
17
18

19
20
21
22
23
24

25

26

27
28
29
30
31
32

33

I/O10
I/O11
I/O12
I/O13
I/O14
I/O15

CLK

CLK

I/O16

I/O17

I/O18

I/O19
I/O20
I/O21
I/O22
I/O23



I/O8
I/O9

0/I0

V

GND

1/I1

GND

GND

10

34

I/O7

9

35

I/O6

8

36

I/O5

7

37

I/O4

6

38

I/O3

5

39

I/O2

4

40

I/O1

3

41

PLCC

CC

V

GND

I/O0

2

1

42

43

84

44

V

CC

83

45

I

5

82

46

I/O62

I/O63

81

47

I/O61

80

48

79

49

I/O60

I/O59

78

50

I/O58

77

51

I/O57

76

52

75

53

I/O56

74
73
72
71
70
69
68
67

66
65
64
63
62

61

60

59
58
57

56

55
54

GND
I/O55
I/O54

I/O53
I/O52
I/O51
I/O50

I/O49
I/O48
CLK

3/I4

GND
V

CC

CLK2/I

I/O47

I/O46

I/O45
I/O44
I/O43
I/O42
I/O41
I/O40

3

Note:
Pin-compatible with MACH130, MACH131, MACH230, and MACH231

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

2

I

CC

CC

V

V

GND

I/O33

I/O32

I/O34

I/O35

I/O36

I/O37

I/O39

I/O38

GND

17469E-2

3MACH435-12/15/20, Q-20/25

ORDERING INFORMATION
Commercial Products

Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:

MACH -12 J C

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

DEVICE NUMBER

435 = 2nd Generation, 128 Macrocells, 84 Pins
435Q = 2nd Generation, 128 Macrocells, 84 Pins,

SPEED

-12 = 12 ns t

-15 = 15 ns t

-20 = 20 ns t

-25 = 25 ns t

Quarter Power

PD
PD
PD
PD

Valid Combinations

MACH435-12
MACH435-15
MACH435-20
MACH435Q-20
MACH435Q-25

JC

435

OPTIONAL PROCESSING

Blank = Standard Processing

OPERATING CONDITIONS

C = Commercial (0

PACKAGE TYPE

J = 84-Pin Plastic Leaded

Chip Carrier (PL 084)

Valid Combinations

The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult your local sales office to confirm availabil­ity of specific valid combinations and to check on newly
released combinations.

°C to +70°C)

4 MACH435-12/15/20, Q-20/25

FUNCTIONAL DESCRIPTION

The MACH435 consists of eight PAL blocks connected
by a central switch matrix. There are 64 I/O pins and 6
dedicated input pins feeding the central switch matrix.
These signals are distributed to the eight PAL blocks for
efficient design implementation. There are 4 global
clock pins that can also be used as dedicated inputs.

All inputs and I/O pins have built-in pull-up resistors.
While it is always good design practice to tie unused
pins high, the pull-up resistors provide design security
and stability in the event that unused pins are left
disconnected.

The PAL Blocks

Each PAL block in the MACH435 (Figure 1) contains a
clock generator, a 90-product-term logic array, a logic
allocator, 16 macrocells, an output switch matrix, 8 I/O
cells, and an input switch matrix. The central switch
matrix feeds each PAL block with 33 inputs. This makes
the PAL block look effectively like an independent
“PAL33V16” with 8 to 16 buried macrocells.

In addition to the logic product terms, individual output
enable product terms and two PAL block initialization
product term are provided. Each I/O pin can be
individually enabled. All flip-flops that are in the
synchronous mode within a PAL block are initialized
together by either of the PAL block initialization product
terms.

The Central Switch Matrix and Input
Switch Matrix

The MACH435 central switch matrix is fed by the input
switch matrices in each PAL block. Each PAL block
provides 16 internal feedback signals, 8 registered input
signals, and 8 I/O pin signals to the input switch matrix.
Of these 32 signals, 24 decoded signals are provided to
the central switch matrix by the input switch matrix. The
central switch matrix distributes these signals back to
the PAL blocks in a very efficient manner that provides
for high performance. The design software automati­cally configures the input and central switch matrices
when fitting a design into the device.

The Product-Term Array

The MACH435 product-term array consists of 80
product terms for logic use, eight product terms for
output enable use, and two product terms for global PAL
block initialization. Each macrocell has a nominal
allocation of 5 product terms for logic, although the logic
allocator allows for logic redistribution. Each I/O pin has
its own individual output enable term. The initialization
product terms provide asynchronous reset or preset to
synchronous-mode macrocells in the PAL block.

The Logic Allocator

The logic allocator in the MACH435 takes the 80 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 20
product terms if in synchronous mode, or 18 product
terms if in asynchronous mode. When product terms are
routed away from a macrocell, it is possible to route all 5
product terms away, which precludes the use of the
macrocell for logic generation; or it is possible to route
only 4 product terms away, leaving one for simple
function generation. The design software automatically
configures the logic allocator when fitting the design into
the device.

The logic allocator also provides an exclusive-OR gate.
This gate allows generation of combinatorial exclusive­OR logic, such as comparison or addition. It allows
registered exclusive-OR functions, such as CRC gen­eration, to be implemented more efficiently. It also
makes in possible to emulate all flip-flop types with a
D-type flip-flop. Register type emulation is automatically
handled by the design software.

Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.

The Clock Generator

Each PAL block has a clock generator that can generate
four clock signals for use throughout the PAL block.
These four signals are available to all macrocells and
I/O cells in the PAL block, whether in synchronous or
asynchronous mode. The clock generator chooses the
four signals from the eight possible signals given by the
true and complement versions of the four global clock
pin signals.

5MACH435-12/15/20, Q-20/25

Table 1. Logic Allocation

Macrocell Available Clusters

M0 C0, C1, C2
M1 C0, C1, C2, C3
M2 C1, C2, C3, C4
M3 C2, C3, C4, C5
M4 C3, C4, C5, C6
M5 C4, C5, C6, C7
M6 C5, C6, C7, C8
M7 C6, C7, C8, C9
M8 C7, C8, C9, C10
M9 C8, C9, C10, C11
M10 C9, C10, C11, C12
M11 C10, C11, C12, C13
M12 C11, C12, C13, C14
M13 C12, C13, C14, C15
M14 C13, C14, C15
M15 C14, C15

The Macrocell and Output Switch Matrix

The MACH435 has 16 macrocells, half of which can
drive I/O pins; this selection is made by the output switch
matrix. Each macrocell can drive one of four I/O cells.
The allowed combinations are shown in Table 2. Please
refer to Figure 1 for macrocell and I/O pin numbers.

Table 2. Output Switch Matrix Combinations

Macrocell Routable to I/O Pins

M0, M1 I/O5, I/O6, I/O7, I/O0
M2, M3 I/O6, I/O7, I/O0, I/O1
M4, M5 I/O7, I/O0, I/O1, I/O2
M6, M7 I/O0, I/O1, I/O2, I/O3
M8, M9 I/O1, I/O2, I/O3, I/O4
M10, M11 I/O2, I/O3, I/O4, I/O5
M12, M13 I/O3, I/O4, I/O5, I/O6
M14, M15 I/O4, I/O5, I/O6, I/O7

I/O Pin Available Macrocells

I/O0 M0, M1, M2, M3, M4, M5, M6, M7

I/O1 M2, M3, M4, M5, M6, M7, M8, M9
I/O2 M4, M5, M6, M7, M8, M9, M10, M11
I/O3 M6, M7, M8, M9, M10, M11, M12, M13
I/O4 M8, M9, M10, M11, M12, M13, M14, M15
I/O5 M10, M11, M12, M13, M14, M15, M0, M1
I/O6 M12, M13, M14, M15, M0, M1, M2, M3
I/O7 M14, M15, M0, M1, M2, M3, M4, M5

The macrocells can be configured as registered,
latched, or combinatorial. In combination with the logic
allocator, the registered configuration can be any of the
standard flip-flop types. The macrocell provides internal
feedback whether configured with or without the flip­flop, and whether or not the macrocell drives an I/O cell.

The flip-flop clock depends on the mode selected for
the macrocell. In synchronous mode, any of the PAL
block clocks generated by the Clock Generator can be
used. In asynchronous mode, the additional choice of
either edge of an individual product-term clock is
available.

Initialization can be handled as part of a bank of
macrocells via the PAL block initialization terms if in
synchronous mode, or individually if in asynchronous
mode. In synchronous mode, one of the PAL block
product terms is available each for preset and reset. The
swap function determines which product term drives
which function. This allows initialization polarity com­patibility with the MACH 1 and 2 series. In asynchronous
mode, one product term can be used either to drive reset
or preset.

The I/O Cell

The I/O cell in the MACH435 consists of a three-state
buffer and an input flip-flop. The I/O cell is driven by one
of the macrocells, as selected by the output switch
matrix. Each I/O cell can take its input from one of eight
macrocells. The three-state buffer is controlled by an
individual product term. The input flip-flop can be
configured as a register or latch. Both the direct I/O
signal and the registered/latched signal are available to
the input switch matrix, and can be used simultaneously
if desired.

6 MACH435-12/15/20, Q-20/25

16

CLK0/I0

CLK1/I1

Clock

Generator

4

CLK2/I3

CLK3/I4

Central Switch Matrix

C0

M0

C1

M1

C2

M2

C3

M3

C4

M4

C5

M5

C6

M6

C7

M7

C8

M8

Logic Allocator

C9

M9

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

M0

M1

M2

M3

M4

M5

M6

M7

M8

Output Switch Matrix

M9

I/O

O0

Cell

I/O

O1

Cell

I/O

O2

Cell

I/O

O3

Cell

I/O

O4

Cell

I/O0

I/O1

I/O2

I/O3

I/O4

17

24

Input

Switch

Matrix

C10

M10

C11

M11

C12

M12

C13

M13

C14

M14

C15

M15

16

16

Figure 1. MACH435 PAL Block

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

M10

M11

M12

M13

M14

M15

I/O

O5

Cell

I/O

O6

Cell

I/O

O7

Cell

I/O5

I/O6

I/O7

17469E-3

7MACH435-12/15/20, Q-20/25

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

CC

+0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the
functionality of the device is guaranteed.

) Operating

A

) with

CC

I/O Pin Voltage –0.5 V to VCC +0.5 V. . . . . . . . . . . . .

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current
(T

= 0°C to +70°C) 200 mA. . . . . . . . . . . . . . . . . . . .

A

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

IN = VIH or VIL

V

V

V

V

I
I

I

OZH

I

OZL

I
I

OL

IH

IL

IH

IL

SC

CC

Output LOW Voltage IOL = 24 mA, VCC = Min 0.5 V

V

= VIH or V

IN

(Note 1)

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 2)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 2)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA
Input LOW Leakage Current VIN = 0 V, V
Off-State Output Leakage V

= 5.25 V, VCC = Max

OUT

Current HIGH VIN = V
Off-State Output Leakage V

Current LOW V
Output Short-Circuit Current V
Supply Current (Typical) V

= 0 V, VCC = Max

OUT

= V

IN

= 0.5 V, VCC = Max (Note 4) –30 –160 mA

OUT

= 0 V, Outputs Open (I

IN

V

= 5.0 V, f =25 MHz, TA = 25°C (Note 5)

CC

= Max (Note 3) –100 µA

CC

or VIL (Note 3)

IH

or VIL (Note 3)

IH

= 0 mA) 255 mA

OUT

10

–100

µA

µA

CAPACITANCE (Note 6)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

Notes:

1. Total I

for one PAL block should not exceed 128 mA.

OL

2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

3. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,

enabled, and reset.

6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where capacitance may be affected.

8 MACH435-12 (Com’l)

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

).

OZH

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)

Parameter

-12

Symbol Parameter Description Min Max Unit

t
t

t

t

COA

t

WLA

t

WHA

f

MAXA

t

t

t

COS

t

WLS

t

WHS

f

MAXS

t

PD

SA

HA

SS

HS

SLA

Input, I/O, or Feedback to Combinatorial Output 3 12 ns
Setup Time from Input, I/O, or D-type 5 ns

Feedback to Product Term Clock

T-type 6 ns
Register Data Hold Time Using Product Term Clock 5 ns
Product Term Clock to Output 4 14 ns

Product Term, Clock Width

LOW 8 ns

HIGH 8 ns

External Feedback

Maximum Frequency

D-type 58.8 MHz

Using Product Term
Clock (Note 2)

Internal Feedback (f

CNTA

)

No Feedback (Note 3)

Setup Time from Input, I/O, or Feedback
to Global Clock

D-type 52.6 MHz

T-type 50 MHz

T-type 55.6 MHz

62.5 MHz
D-type 7 ns
T-type 8 ns

Register Data Hold Time Using Global Clock 0 ns
Global Clock to Output 2 8 ns

Global Clock Width

LOW 6 ns
HIGH 6 ns

D-type 66.7 MHz

Maximum Frequency

D-type 83.3 MHz

Using Global
Clock (Note 2)

83.3 MHz

External Feedback

Internal Feedback (f

No Feedback (Note 3)

CNTA

T-type 62.5 MHz

)

T-type 76.9 MHz

Setup Time from Input, I/O, or Feedback to 5 ns
Product Term Clock

t

t

t

HLA

GOA

GWA

Latch Data Hold Time Using Product Term Clock 5 ns
Product Term Gate to Output 16 ns
Product Term Gate Width LOW (for LOW transparent) 6 ns

or HIGH (for HIGH transparent)
t
t

t

t

SLS

HLS

GOS

GWS

Setup Time from Input, I/O, or Feedback to Global Gate 8 ns

Latch Data Hold Time Using Global Gate 0 ns

Gate to Output 10 ns

Global Gate Width LOW (for LOW transparent) 6 ns

or HIGH (for HIGH transparent)
t

PDL

Input, I/O, or Feedback to Output Through

Transparent Input or Output Latch 14 ns
t
t
t

SIR

HIR

ICO

Input Register Setup Time 2 ns

Input Register Hold Time 3 ns

Input Register Clock to Combinatorial Output 18 ns

9MACH435-12 (Com’l)