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High Voltage Safety Instructions
Warning!
All operations on this device must be carried out by sufficiently skilled
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Caution, Electric Shock!
Before installing your new PEP product into a system always ensure
that your mains power is switched off. This applies also to the installation of piggybacks.
Serious electrical shock hazards can exist during all installation,
repair and maintenance operations with this product. Therefore,
always unplug the power cable and any other cables which provide
external voltages before performing work.
Special Handling and Unpacking Instructions
ESD Sensitive Device!
Electronic boards and their components are sensitive to static elec-
tricity. Therefore, care must be taken during all handling operations
and inspections of this product, in order to ensure product integrity at
all times.
•Do not handle this product out of its protective enclosure while it is not used for operational purposes unless it is otherwise protected.
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HARDWARE
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The VMP2 is a comprehensive computing platform which brings togethor the latest
advances in computing technology in a board designed for maximum performance, flexibility and versatility within a rugged compact format.
The design centered on realizing a board which addresses the need for increased computing capacity while at the same time reducing the size and number of system components in order to reduce space requirement s and optimize power dissipation.
The VMP2 is based on the MPC8245, a highly integrated microprocessor containing a
PowerPC MPC603e core. This is the 330 MHz version with a Floating Point Unit (FPU).
One of the prime advantages of utilizing the established and proven MPC603e core is
the associated broad infrastructure of support that has built up around it . All of the noteworthy third-party software tool vendors provide tools for the MPC8245.
An important feature of the board is the integration of a PCI bus within a VME-CPU
board. This connects the MPC8245 with the Fast Ethernet controller and the Tundra
Universe II PCI/VME bridge and also to the onboard 100-pin PCI expansion connector,
enabling the connection of the full range of PCI peripherals.
The VMP2 employs an OS-independent boot loader that enables the loading of any
operating system. This boot loader makes an update of the Flash content s and automatically downloads from Flash to SDRAM before booting the OS. For performance reasons the OS is started from the SDRAM.
The power of the board is greatly enhanced by means of the PCI expansion connector
which makes it possible to cascade one or two additional IO1 modules onto the board
resulting in a total package of either 8HP or 12HP. Both IO1 modules may be used to
carry PMC modules. Given the wide range of PMC modules now available, this feature
affords the user a very wide range of options. Additionally, one can substitute a module
designed to provide an even greater range of PCI peripherals in place of either of the
IO1 modules. These features enable, for example, the connection of the widest range of
system I/O components such as various field busses, Fast Ethernet and Ultra 2 SCSI, to
name just a few . The complete range of expansion possibilities is thus mad e available to
the user by the VMP2.
The VMP2 is a VME PowerPC-based single-board computer specifically designed for
use in highly integrated platforms with solid mechanical interfacing for a wide range of
industrial environment applications.
Some of the VMP2’s outstanding features are:
•PowerPC MPC8245 Kahlua II (603E core with an integrated FPU,
combined with PCI interface and memory controller)
•16 kB data cache
•16 kB instruction cache
•up to 256 MB SDRAM (132 MHz) with optional ECC support
•up to 8 MB onboard Flash
•Fast Ethernet interface
•two serial I/O’s (RS232 / ESD protected and EMI compliant)
•Memory Expansion Socket e.g. Flash memory (up to 144 MB) or SRAM
•onboard PCI bus with expansion connector
•four counter/timers
•programmable watchdog timer
•real-time clock
•double-width version for PCI expansion
•Tundra Universe II VME-to-PCI Bridge
•compliance with VITA VME-S pecification ANSI / IEEE STD1014-1987 / IEC 821 and 297
The VMP2 is a 3U VME CPU board featuring a powerful CPU (number cruncher). The
design is based on the new highly integrated Motorola PowerPC processor MPC8245,
which integrates a PCI interface and several peripherals inside one Chip.
Four standard memory configurations (32 MB, 64 MB, 128 MB and 256 MB SDRAM)
are available. Flash memory for integrating the initial bootloader and ROMable operating systems are provided . Additionally, NV SRAM or a Disk-On-Chip (by M-Systems)
can be placed on a DIL socket for special purposes.
The board controls the VMEbus through the Tundra UNIVERSE II PCI-VME bridge
which is an industrial standard for connecting the PCI bus to the VME. Improved VMEbus master and VMEbus slave performance with an increase of FIFO depth and optimized DMA transfer are some of the outstanding features of this device.
The VMP2 is also able to communicate with the environment through a Fast Ethernet
interface and two serial interfaces at the front side of the board. One of the serial interfaces is a RS232 full modem interface while the other is a software-configurable
RS232/RS485 port. These UARTS support baud rates up to 1.5 Mbps and are software
compatible with the 16550 UART from National Semiconductor. They contain 128 Byte
Transmit FIFO and 128 Byte Receive FIFO for reducing the bandwidth requirement of
the CPU.
The Ethernet is realized with the Intel 82559 with full duplex support at both 10/100
Mbps possible. This Fast Ethernet controller with an integrated 10/100 Mbps physical
layer device is the foremost solution for PCI board LAN designs. It combines low power
consumption with a small package design which is ideal for power and space constrained environments.
Anticipating the VMP2's use in data critical applications, the memory data path contains
a selectable in-line ECC controller which can provide SDRAM single-bit error correct or
double-bit error detect.
For mass data transmission a dual channel DMA controller is provided. It can be
programmed directly or through the use of descriptor chains located in memory. Data
can thus be moved from PCI to memory or vice versa, memory to memory, or PCI to
PCI.
The MPC8245 supports processor control and visibility through the JTAG/COP
(common on-chip processor) interface that is available on the VMP2. Utilizing third party
tools, the developer can access and control the processor. It also has standard IEEE
1149.1a-1993 compliant boundary scan capability. The ECC data path has a mechanism to manually inject errors into memory for use with maintenance and diagnostic
utilities. Furthermore a watch point and capture register on the internal bus and a set of
address attributes on the external memory and PCI buses facilitate debugging analysis.
VME interface
In addition to the standard functionality required by a VME CPU, the VMEbus interface
(Tundra Universe 2) provides:
•automatic First-Slot detection
•integral FIFO buffers for multiple transactions in both directions
•programmable DMA controller with linked list support.
The following descriptions provide an overview of the main features of the principa l functional blocks of the VMP2.
2.4.1CPU
The VMP2 is based on the Motorola PowerPC processor MPC8245 which integrates a
large number of peripherals, such as a PCI interface, PCI arbiter, Interrupt Controller,
Memory Controller and multiple Timers. CPU speed is 330 MHz.
2.4.1.1 MPC8245 (Kahlua II) Features
Important features of the MPC8245 implemented on the VMP2 are as follows:
Peripheral logic
Memory interface
•Programmable timing supporting SDRAM (The VMP2 uses SDRAM at 132
MHz)
•High bandwidth bus (64-bit data bus) to SDRAM
•2 memory banks with up to 128 MByte each
•Supports 64, 128 and 256 Mbit SDRAM
•Contiguous memory mapping
•8-bit ROM interface
•Write buffering for PCI and processor accesses
•Supports ECC
•SDRAM data path buffer
•Low voltage transistor-to-transistor logic (LVTTL)
•Port X: 8-bit general-purpose I/O port using ROM controller
interface with address strobe
32-bit PCI interface operating up to 33 MHz on the VMP2
•PCI Specification Revision 2.1 compatible
•PCI 5.0-V tolerance
•Support for PCI-locked accesses to memory
•Support for accesses to all PCI address spaces
•Selectable big- or little-endian operation
•Store gathering of processor-to-PCI write and PCI-to-memory write accesses
•Memory prefetching of PCI read accesses
•Selectable hardware-enforced coherency
•PCI bus arbitration unit (five request/grant pairs)
•Internal configuration registers accessible from PCI
•Two-channel integrated DMA controller
•Supports direct mode or chaining mode (automatic linking of DMA transfers)
•Supports scatter gathering - read or write discontinuous memory
•Interrupt on completed segment, chain, and error
•Local-to-local memory
•PCI-to-PCI memory
•PCI-to-local memory
•Local-to-PCI memory
Message unit
•I2O message controller
•Two door-bell registers
•In-bound and out-bound messaging registers
I2C controller with full master/slave support
Embedded programmable interrupt controller (EPIC)
•Five hardware interrupts (IRQs) or 16 serial interrupts
•Four programmable timers
Integrated PCI bus and SDRAM clock generation
Programmable memory and PCI bus output drivers
Debug features
•Watchpoint monitor
•Address attribute and PCI attribute signals
•JTAG/COP - common onboard processor for in-circuit hardware debugging
•Performance monitor
603e core
High performance, superscalar 603e core
627 Dhrystone (2.1) MIPS
Integer unit (IU), floating point unit (FPU) (user enabled or disabled), load/store unit
(LSU), system register unit (SRU), and a branch processing unit (BPU)
16 kB instruction cache
16 kB data cache
Lockable L1 cache - entire cache or on a per-way basis
Dynamic power management
The main memory of the VMP2 consists of SDRAM, ranging from 64 up to 256 MByte,
soldered onto the board for mechanical stability.
The VMP2 provides ECC support (optional) and a maximum memory speed of 132 MHz.
2.4.2.2 Flash
4 or 8 MB of soldered Flash memory accommodate the bootstrap loader software and
can be used to store ROMable operating systems or user data. This Flash memory is 8bit wide and windowed with window sizes of 512 kB.
2.4.2.3 EEPROM
A serial EEPROM is provided, organised into 8 blocks with 256 bytes per block
(24LC16). This EEPROM is connected to the I2C bus provided by the MPC8245.
2.4.2.4 Memory Expansion Socket (DIL600)
The VMP2 provides one 32-pin DIL socket on which to place SRAM, non-volatile SRAM
or other DIL600 devices on the board. Access to this Memory is controlled by the
onboard logic.
The following devices may be added to the VMP2 via the 32-pin DIL600 socket:
•Standard Flash memory of up to 512 kB, for example, the AMD29F010 and
AMD29F040
•The NV SRAM from Dallas Semiconductor. These devices are available in the
temperature range –40°C to +85°C for the industrial environment and guarantee
a minimum data retention of 10 years (e.g. DS1250Y-100).
•Disk-on-chip Flash memory. In order to achieve flexibility with low cost, the VMP2
Flash disk is not soldered but connected via a special module from M-Systems
(Disk-on-Chip 2000) which comes in the following sizes:
2 - 24 MB (dimensions 41.7 x 17.9 x 5.6mm);
4 - 144 MB (dimensions 42.0 x 18.3 x 11.8mm).
Two serial ports (RS-232) are provided by means of two 8pin RJ45 connectors.
8
The RS-232 serial interfaces named TERM and SER are 16C550 compliant and have
128-byte transmit and receive buffers. In addition to their other uses, the TERM port is
usedto interface with the bootstrap loader and the SER port is used to download software.
Electrically, the two serial ports are identical and they provide a complete set of handshaking and modem control signals, maskable interrupt generation and data transfer of
up to 115.2 KBaud.
The upper serial interface (SER) can also be configured to act as an RS-485 interface.
The configuration of the interface is achieved by setting the RS_CTL bit in the Control
Register. Please refer to Table 4-14 in chapter 4.
Additionally, a module is available from PEP which provides an optoisolated half/full
duplex RS-485 interface. For this reason the onboard SER connector on the VMP2
baseboard is not equipped. Please contact PEP Support department for more information.
2.5.3.1 Pinouts of Serial Ports (RJ45 Connectors)
Table 2-3: Serial Port Connectors CON6 and CON7 Pin Assignment
The PCI Expansion Connector provides the possibility to mount several transition
boards above the VMP2 for adding special functionality which is not provided on the
VMP2 main board or on the VME bus. All the PCI signals of the on board PCI bu s will be
routed to this connector, so that a complete PCI bus is provided on this connector. In
addition, almost the same number of ground and power pins (3.3V and 5V) as are on a
CPCI P1 or PMC connector are provided. Examples of transition boards are:
•PMC carrier
•PC-MIP carrier
•IO board with Graphic interface, second Ethernet interface, SCSI etc.
99
100
A table showing the pinout of the PCI Expansion Connector
appears on the following page.
2.5.5Serial Interface Expansion Connector and Pinout
The serial interface expansion connector provides the capability to add different front
end interfaces to the UART B signals. For example, an opto-isolated RS422/485 module
(currently under development) may be plugged onto this connector.
2.5.5.1 Serial Interface Expansion Connector CON3 Pinout
Table 2-5: Serial Interface Expansion Connector (CON3) Pinout
A 32-pin DIL600 socket is provided in order to make possible the addition
of various memory expansion devices (with access time <120ns). The
devices which have been tested and approved for this connector are as follows:-
DIL type Flash memory (up to 512 kB)
DIL SRAM (up to 512 kB) e.g. Samsung KM684000BLP-7
NVSRAM (up to 512 kB) e.g. DALLAS DS1250Y-100)
Eprom (up to 512 kB) e.g. 27C040
M-Systems DiskOnChip 2000 (up to 288 MB)
Note:
For the pinout of this connector please see Chapter 4,
section 4.2.1
A JTAG/BDM interface is provided on the VMP2 for software
debugging. The pinout of this connector is in accordance
with the pinout of the most commonly used emulator probes.
Note:
As shipped, only the Altera onboard logic may be detected by
means of the JTAG interface. If the JTAG interface requires to be
re-configured for software debugging, please contact Support at
PEP Modular Computers for assistance.
TDO12NC
TDI34TRST#
NC563.3V
TCK78NC
TMS910NC
SRESET#1112NC
HRESET#1314KEY (no pin)
CHKSTP#1516GND
2.5.8Digital Temperature Sensor (LM75)
The VMP2 also provides an onboard digital temperature sensor with a thermal watchdog functionality (National Semiconductor LM75). This has various uses including, for
example, calibration of the onboard RTC over a wider temperature range.
A watchdog timer is available which (when enabled) on timeout forces either a nonmaskable interrupt (NMI) to be generated or causes a system reset to occur (refer to
chapter 4 for configuration details). It is also possible to generate , as a first step , an NMI
and then, as a second step, a system reset (in Cascade mode).The watchdog timing
has four possible settings: 0.5, 1.0, 1.5, and 2.0 seconds. After selecting the timeout
value and routing (NMI or reset) the watchdog can be enabled. Once enabled, the
watchdog must be continuously retriggered or a timeout will occur. When the watchdog
timer is enabled, it cannot be stopped or reprogrammed except by resetting the system.
The yellow watchdog LED (W) indicates the enabling status of the watchdog. Prior to
the watchdog being enabled it is off. After enabling it comes on and remains on until a
system reset occurs.
2.6.2RTC (STC M41T56)
The Real Time Clock provides the following features:
•counters for seconds, minutes, hours, day, date, month and year.
•clock calibration by software
•low supply current for buffering with Gold Caps
•alternatively a battery may be placed on the board to buffer the RTC for a longer
time
•it is also possible to buffer the power supply for the RTC via the VME-5V-Standby
power line
•automatic leap year compensation
•precision: 35 ppm
•for greater precision or for temperature compensation the RTC can be adjusted in
in steps of +4.068 or –2.034 ppm
•for temperature compensation, the onboard temperature sensor (LM75) may be
used
2.6.3Reset/Abort
There are also 2 push button switches with the function ABORT and RESET. The
RESET button reinitializes the board via hardware.
The ABORT button initiates the NMI. In addition it is latched into a bit in the System
Logic, the purpose of this is to differentiate between the NMI initiated from the ABORT
Button and the NMI initiated from the watchdog.
buttons on the Front Panel may be viewed in Figure 2-2.
Three LED’s with the colors red, green and yellow are provided on the front panel
(please see Figure 2-2 on page 2-4) to give a quick indication of several key operating
conditions:
•The red LED (H) is general purpose.
•The yellow LED (W) indicates WATCHDOG ACTIVE
•The green LED (U) has been preset to light on initialisation of the board. After-
wards it is available for general purposes
The general purpose LED’s are programmable via a register in the System Logic.
3 additional LED’s, all green, are provided to indicate Ethernet working conditions:
The VMP2 has been designed for easy installation. However, the following importantstandard precautions must be observed. Some other important information is also set
out below.
3.1 Board Installation
Slot Selection
The VMP2 is designed so that it may be used in any free slot of a 3U VME Backplane.
It has an automatic first slot detection mechanism which configures it as a System Controller when placed in the far left slot.
When configured as the System Controller, it enables its system clock and arbiter in
order to control the entire VME bus.
Default setting of the serial Interfaces: 9600 Baud, 8N1
On initial startup a message of greeting comes up.
When the VMP2 is invoked for the first time, a Bootstrap loader startup messag e comes
up on the “term” serial port, which will provide you with some configuration information
on the system and a command prompt for entering bootstrap loader commands. For a
detailed description of these commands please see chapter 5 Bootstrap loader.
Caution!
Please switch off the VME system before installing the board in a
free slot. Failure to do so could endanger your life/health and may
damage your board or system.
Note:
Certain VME boards require bus master capability. If you are in
doubt whether such features are required for the board you intend
to install, please check your specific board and/or system documentation to make sure your system is provided with an appropriate free slot to insert the board.
Please see Figures 2-3 and 2-4 in Chapter 2 to view the positions of the jumpers and
resistors on the board.
4.1.1Bootstrap Loader / Socket Jumper J1
The Jumper J1 is used to select the memory position from which the VMP2 fetches its
boot code. It determines the address position of the onboard Flash window and the
Flash/SRAM expansion socket (DIL600, 32-pin).
Frequency test output is used for calibration of the onboard RTC. The RTC provides a
512 Hz frequency test signal for calibration purposes. Please refer to the datasheet of
the ST M41T56 for detailed information (for position of J2 on the board please see figure
2-3).
4.1.3Resistor Setting for Non-standard Socket Devices
The default pinout of this socket is designed for use with standard DIL Flashes and MSystems DiskOnChip. As some devices have a different pinout, resistors must be set
accordingly (please see figure 2-4 for an illustration of these resistors on the board)
Table 4-2: Resistor Setting for Various Non-standard Socket Devices
When the VMP2 is using the onboard RS485 interface and is the last on the RS485 bus,
then the RS485 interface must provide termination resistance. The purpose of J3 is to
enable this line termination resistor (130 R).
Table 4-3: Jumper Settings for RS485 Termination
TerminationJ3
ONSet
OFFOpen
Additionally, the correct idle line potential must be provided at one location within the
RS485 bus. J4 and J5 are used for this purpose. Pullup/Pulldown resistors are 380 Ohm
each.
Note:
Ensure that the reference potential for the RS485 signals are set
in one location only on the bus.
The following figures illustrate the address mapping of the VMP2. Where the first figure
describes the overall map, the second figure provides a more detailed map of the uppermost address area. The upper area address map depends on the configuration of the
VMP2 memory expansion sockets and the requirements of the application.
VME bus slave address and VME IRQ mask are programmable inside the TUNDRA
UNIVERSE II. Please refer to the VME slave manual chapter in the TUNDRA UNIVERSE II manual and the BSP documentation.
• For write access to this address area (0xFFE0 0000-0xFFFF
FFFF), it is only possible to use byte-wide write commands.
• When the memory expansion socket is used for NVSRAM, byte
0xFFF0 0000 (J1 installed) or byte 0xFFF8 0000 (J1 removed)
is reserved for the output of post codes to the VMP1-Post. Data
should not be stored at either of these locations.
The Software Compatibility ID will signal to the software when differences in hardware
require different handling by the software. This register is READ ONLY. It starts with the
value 0x00 and will be incremented with each change in hardware (software sensitive
only).
The Memory Configuration register provides basic information concerning the amount of
installed main memory, whether or not ECC is enabled, and the location from which the
operating system is to access the bootstrap loader.
Table 4-9: Memory Configuration Register
REGISTER NAME
ADDRESS
BIT POSITION
CONTENT
DEFAULT
76543210
MSB
BJres.res.ECCres.res.SZ1SZ0
n/an/an/an/an/an/an/an/a
MEMORY CONFIGURATION
0xFFE0 0014R
BITNAMEVALDESCRIPTION
0SZ0
1SZ1
2res.
3res.
4Res.
5Res.
6Res.
7BJ
0Settings:
1
0
1
0
1
0
1
0
1
0
1
0
1
0Boot Jumper J1 closed (VMP2 fetches boot code from onboard Flash)
1Boot Jumper J1 open (VMP2 fetches boot code from socket)
The Flash bank select register is used to select the appropriate Flash bank. As 8-bit
wide Flash memory may only be accessed through a 512 kB window; this is the only
way to address a larger size Flash memory . Using bit s FB0..FB3, 16 Flash banks can be
selected (16x512 kB = 8 MB). The default value on startup of the VMP2 is 0x00.
The Watchdog Control register is the interface between applications and the operating
system for controlling the functioning of the W atchd og. Together with the Event Register,
bit 0 (WD) and bit 2 (PB2), the possibility is provided for either hardware (Abort switch)
or software (Watchdog timer) intervention in the execution of the application.
Table 4-11: Watchdog Control Register
REGISTER NAME
ADDRESS
BIT POSITION
CONTENT
DEFAULT
76543210
MSB
WD_ENWD_RWD_CCD WD_TRGres.res.WDT1WDT0
0000n/an/an/an/a
WATCHDOG CONTROL
0xFFE0 0018RW
BITNAMEVALDESCRIPTION
0WDT0
1WDT1
2
3
4WD_TRG
5WD_CCD
6WD_R
0Settings: WDT1 WDT0
1
0
1
0
Reserved
1
0
Reserved
1
When WD-EN (bit 7) set to 1, indicates that Watchdog timer has not been
0
retriggered.
Causes the Watchdog to be retriggered
1
(Resets Watchdog timer to value indicated by bits 0 and 1, and WD_TRG
(bit 4) to 0)
Normal watchdog functionality
0
Cascade mode: when watchdog timout occurs, an NMI will be generated,
1
the watchdog timer resets, a further timeout will result in a system reset
0Causes hardware reset of system upon Watchdog timeout
1Causes generation of a non-maskable interrupt upon Watchdog timeout
0Watchdog timer disabled
Watchdog timer enabled
000.5 seconds Watchdog timeout time
011.0 seconds Watchdog timeout time
101.5 seconds Watchdog timeout time
112.0 seconds Watchdog timeout time
ACCESS
LSB
Note...
7WD_EN
1
Once the Watchdog timer is enabled it
cannot be disabled except by resetting the
system.
The Control register provides access to the front panel general purpose LED’s (LED1/
Green and LED2/Red), allows for the generation of a software reset of the system, and
is used to control the configuration of the SER either for RS-232 or RS-485 operation.
Table 4-12: Control Register
REGISTER NAME
ADDRESS
BIT POSITION
CONTENT
DEFAULT
76543210
MSB
RS_CTLRes.Res.S_RSTRes.Res.GPLED2 GPLED1
n/an/a0n/a0000
CONTROL
0xFFE0 001ARW
BITNAMEVALDESCRIPTION
Indicator
0
1
2Res.
3Res.
4S_RST
5Res.
6Res.
7RS_CTL
LED1/
Green
Indicator
LED2/Red
0GPLED1 LED1G (green) off
GPLED1 LED1G (green) on
1
0GPLED2 (optional, red) off
GPLED2 (optional, red) on
1
0
Reserved
1
0
Reserved
1
0No operation
1Causes a software reset (S_RST) to be initiated
0
Reserved
1
0
Reserved
1
SER connector configured to act as an RS232 interface (default)
0
SER connector configured to act as an RS485 interface
1
ACCESS
LSB
!
Warning:
When setting bit 7 the user must ensure that the corresponding
interface is also an RS485. A mismatch will risk damage to the
VMP2 and/or the application.
The Event register is used to indicate the origin of the generation of the non-maskable
interrupts caused either by a Watchdog timeout or the pressing of the Abort switch.
Table 4-13: Event Register
REGISTER NAME
ADDRESS
BIT POSITION
CONTENT
DEFAULT
76543210
MSB
NLRSTRes.Res.Res.Res.PB2Res.WD
n/an/an/an/an/a0n/a0
EVENT
0xFFE0 001CRW
BITNAMEVALDESCRIPTION
0WD
1
2PB2
3
4
5
6
7
0Indicates that no Watchdog timeout has occurred
Indicates that a Watchdog timeout has occurred
1
0
Reserved
1
Indicates that the Abort switch has not been pressed
0
1Indicates that the Abort switch has been pressed
0
The Board Revision Register may be used to identify the hardware (BRn) and logic status of the board by the software (LRn). It is set at the factory and starts with the value
0x00 for the initial board prototypes and will be incremented with each redesign / logic
release.
--Interrupt Enable Register0xFFE0 0009
Interrupt Status registerFIFO Control Register0xFFE0 000A
--Line Control Register0xFFE0 000B
--Modem Control Register0xFFE0 000C
Line Status register--0xFFE0 000D
Modem Status register--0xFFE0 000E
Scratchpad registerScratchpad Register0xFFE0 000F
Table 4-19: Baud Rate Register Set (DLL/DLM)
Read ModeWrite M od eAddress
LSB of divisor latchLSB of divisor latch0xFFE0 0008
MSB of divisor latchMSB of divisor latch0xFFE0 0009
FT= Frequency test bit
OUT= Output level
ST= Stop bit
S= Sign bit
Note:
When the RTC has once been stopped due to low voltage, it is
necessary to re-initialize the “Seconds” “Minutes” and “Hours” registers before it will run again.
The CPU board is delivered with the NetBootLoader software already programmed into the onboard soldered Flash memory . The NetBootLoader it self is a software utility which initializes the
CPU board for operation before turning control over to either an application or to an operator.
This software also provides the capability to monitor and control the operation of the NetBootLoader itself, display system status information, to program executable code and data to the
Flash memory, and to load and start application software.
To attain full operational capability, the NetBootLoader FLASH must be programmed by the
user with application software. Once the application has been programmed to Flash memory,
the NetBootLoader will support the complete boot operation. The following chapters describe
the functioning of the NetBootLoader and how to program the Flash memory.
5.1General Operation
Upon power on or a system reset, the NetBootLoader is started. The CPU board is configured
for operation and control is either passed to an application or an operator. In the event a valid
application has been programmed into the Flash memory and no operator intervention takes
place, the application is copied from FLASH into SDRAM and control is p assed to the application. If the NetBootLoader does not find a valid application or operator intervention has occurred, control is passed to the operator . The operator now has control to determine the system
status, make configuration changes, read or program the Flash memory, or to restart or shut
down the system.
The operator command interfacing with the NetBootLoader is accomplished either via the
TERM serial port or the Ethernet port. During the boot operation a command interpreter is st arted which allows the operator to input commands to the NetBootLoader. Prior to interfacing via
the Ethernet port the network must be configured. This is done via the TERM port.
5.2NetBootLoader Interfaces
There are four possibilities to interface with the NetBootLoader:
• Via the ABT (Abort) switch
• Via the TERM serial interface
• Via the SER0 serial interface
• Via the Ethernet interface
Gaining access to the NetBootLoader is a function of the contents of the Flash memory and the
“BootWaitT ime ” setting. If there is no valid application progra mmed into the Flash memory, the
boot operation automatically terminates after the CPU board has been initialized and control is
passed to the command interpreter. If there is a valid application in the Flash memory the boot
operation is delayed according to the setting of the boot wait time. The green user LED (U) on
the front panel flashes indicating that the boot operation is in a wait state. During this time the
operator may intervene in the boot operation either by pressing the ABT (Abort) switch, entering the “abort” command via the TERM interface, or by performing a su ccessful telnet login via
the Ethernet interface. If the operator does not intervene, the boot operation is continued after
the boot wait time has been exceeded.
The ABT switch, located on the CPU board front panel, provides the operator with the ability to
directly terminate the boot operation during the boot wait time which is indicated by the “U” LED
blinking. This is the sole purpose of the ABT switch during the NetBootLoader operation.
5.2.2TERM Serial Interface
The TERM serial port is used to provide direct operator interfacing to the NetBootLoader. As
soon as the CPU board has been initialized this port is activated and the operator may input
commands. During the boot wait time the operator may terminate the boot operation and take
control of the NetBootLoader. Once the boot wait time is exceeded the command interpreter is
deactivated and the operator no longer has access to the NetBootLoader.
The TERM serial interface may either be directly connected to a terminal device or may interface with a terminal emulator.
5.2.3SER0 Serial Interface
The SER0 serial port is used to provide the NetBootLoader with the ability to access Motorola
S-Records for programming an application to FLASH. No command interpreter is available for
this interface.
5.2.4Ethernet Interface
The Ethernet interface provides the capability of remotely interfacing with the NetBootLoader.
Prior to using this interface it is necessary to configure the NetBootLoader network settings.
This is accomplished via the TERM interface. Once the network settings have been made, the
remote operator has the same capabilities as with the TERM interface. During the boot wait
time the operator gains control of the NetBootLoader by logging into it via the Ethernet interface. This causes the boot operation to be terminated and gives control to the remote operat or .
The Ethernet interface uses the telnet protocol for operator interfacing with the NetBootLoader.
In addition to the operator interface via Ethernet, the NetBootLoade r also uses the Ethernet interface for ftp server access.
5.3NetBootLoader Functions
In addition to initializing the CPU board for operation and the loading and starting of applications, the NetBootLoader provides the following operator monitor and control functions:
• NetBootLoader control
• system status monitoring
• ftp server access
• FLASH reading and programming operations
• Motorola S-Record acquisition
These functions are described in detail in the following chapters.
NOTE ...
The command title (CMD TITLE) is expressed in capital letters and is not the
same as the syntax of the command. The command syntax is always written
using small letters
The NetBootLoader provides various functions for controlling the operation of the NetBootLoader itself as well as the setting of operational parameters. The following table provides an
overview of available NetBootLoader control functions.
Table 5-1: NetBootLoader Control Commands
CMD TITLEALIASFUNCTIONREMARKS
ABORT-Terminate boot wait
BWBoot WaitSet or display BootWaitTime
HELP or ?-Display online HELP pages
LOGOUT-Terminate telnet session
NET-Set network parametersMust be set before attempting telnet login
PASSWDPasswordSet telnet password
PFPort FormatSet serial port parametersUsed for both TERM and SER0 ports
RSResetResets sy stem
5.3.2System Status Monitoring
The NetBootLoader provides various functions for monitoring the overall status of the system
during the operation of the NetBootLoader. The following table provides an overview of available system status monitoring functions.
Table 5-2: System Status Monitoring Commands
CMD TITLEALIASFUNCTIONREMARKS
CHECK-Application validationVerifies validity of user image programmed
to FLASH
INFO-Display system information
MDMemory
Display
Display memory contentsApplies to all visible memory
PCI-Display PCI device information
PING-Verify network status
VERVersionDisplay version number of
The NetBootLoader provides various functions for interfacing with an ftp server. The following
table provides an overview of available ftp server functions.
Table 5-3: ftp Server Commands
CMD TITLEALIASFUNCTIONREMARKS
BYE-Terminate session with ftp server
CDChange
Directory
GET-Download a file from ftp serverOnly for executable applications.
LOGIN-Login to ftp server
LSList DirectoryList ftp server directoryLists contents of directory.
PUT-Upload a file to ftp serverData buffer is source.
PWDPrint Working
Directory
Change ftp server directory
Data buffer is target.
Display current ftp server directoryLists name of directory
5.3.4FLASH Operation
The NetBootLoader provides various functions for performing operations with Flash memory.
The following table provides an overview of available FLASH operation functions.
Table 5-4: FLASH Operation Commands
CMD TITLEALIASFUNCTIONREMARKS
CLONE-P rogram NetBootLoader to FLASHUses data buffer or socket as source
LFLoad FLASHProgram application to FLASHUses data buffer as source
SFStore FLASHReads FLASH to data bufferUses data buffer as target
5.3.5Motorola S-Records
The NetBootLoader provides one function for acquiring Motorola S-Records. The follo wing table provides an overview of this function.
Table 5-5: Motorola S-Records Commands
CMD TITLEALIASFUNCTIONREMARKS
SLSLoadDownload Motorola S-RecordsUses data buffer as target
The CPU board is delivered with the NetBootLoader already installed in the onboard soldered
FLASH and is ready for operation. However , in order for the CPU board to be used in a system,
application software must be made available for use. This is accomplished by programming the
application also to the onboard soldered Flash memory where the NetBootLoader is located.
Upon initial power up the NetBootLoader is started automatically. As soon as the NetBootLoader has completed initialization of the CPU board, it checks to see if there is a valid application
programmed in FLASH and at the same time initiates a command interpreter which the operator can access either via the TERM or telnet interfaces. If there is no valid ap plication in memory, the NetBootLoader terminates the boot operation, and waits for operator intervention. As
this is the case when the CPU board is first powered up, the operator now ha s t he o pportun ity
to program an application.
Prior to programming an application it may be necessary to configure the NetBootLoader or
perform other functions depending on the user’s application development environment or application requirements. Once this has be accomplished and the application has been programmed, the CPU board is ready for operation.
The following chapters provide information on how to set up and operate the NetBootLoader
itself, initiation of the telnet interface, and how to program an application to FLASH.
5.4.2Accessing the NetBootLoader
Initial access to the NetBootLoader can only be achieved via the TERM interface. Prior to using
the telnet interface, the Ethernet parameters must be set and this can only be accomplished
initially via the TERM interface. Once valid Ethernet parameters and the telnet log in password
have be set, the telnet interface is available for operation.
Use of the TERM interface requires either a terminal or a terminal emulator. Use of the telnet
interface requires a remote telnet login to the NetBootLoader.
Availability of the command interpreter depends on the system st atus. If there is no valid application programmed, the command interpreter is available as long as the operator requires it. If
a valid application is programmed, the command interpreter is only available for the duration of
the boot wait time. If the operator requires the command interpreter for a longer time he must
terminate the boot operation before the boot wait time is exceeded.
Upon initiation of the command interpreter, a prompt is sent to the TERM interface and commands may be entered. To gain access to the NetBootLoader from a remote location via Ethernet a telnet login must be performed. If the boot wait time has not been exceeded, a telnet login
automatically terminates the boot operation and a command prompt is sent to the telnet remote
interface.
Once the operator has control of the NetBootLoader, he may perform any required action. To
continue with the operation of the CPU board, the system must either be cold started or the
operator must issue a “reset” command. In either event, the NetBootLoader is restarted and
the boot operation begins anew.
There are several NetBootLoader commands which provide the operator with the capability to
configure specific parameters which are used by the NetBootLoader for interfacing operations.
These commands are:
• BW (BootWait)
•NET
• PASSWD
• PF (Port Format)
Default settings are available for all the above commands except for “net” which is dependent
on the application environment.
5.4.3.1BW
This command is used to display or set the actual boot wait time used by the NetBootLoader
to delay the boot operation before proceeding with the loading and starting of an application. If
this time is set too short it may only be possible to gain access to the NetBootLoader via the
“ABT” switch.
The BootWaitTime value is stored in the boot section of the serial EEPROM. This section is
validated with a CRC code to avoid the setting of random parameters.
Note ...
If the CRC of the boot section is not valid, changing the BootWaitTime will have
no effect because the “bw” command does not validate an invalid CRC. In this
case, a default timing of 5 seconds is always used.
To validate an invalid CRC, an operating system utility must be used, or, alternatively, the “-f”
option of the “bw” command must be issued.
Warning !!!
Using the “bw -f” command to validate invalid entries may adversely impact the
operation of the operating system.
5.4.3.2NET
This command is used to set or display the parameters for the configuration of the Ethernet interface of the CPU board. The Ethernet interface is only available after these settings have
been made. Once these settings have been made, the system must be cold started or reset for
them to take effect.
5.4.3.3PASSWD
This command is used to set the password used by the NetBo otLoader for the operation of the
telnet interface. No password is required for access from the TERM interface.
This command is used to set the port parameters for the TERM a nd SER0 serial interfaces only
for the current operator session. The next system restart will cause these settings to revert to
the default settings of: 9600 Baud, 8 bits per character, 1 stop bit, and no parity. This is done
to preclude a system lockout when restarting due to incompatible settings.
5.4.4telnet Login
A telnet login to the NetBootLoader is only possible during the boot wait time and only af ter the
Ethernet network parameters have been set.
T o ef fect a telnet login the operator performs the standard telnet log in procedure during the boot
wait time. The NetBootLoader responds by suspending the boot wait and requests a login
password. The operator then enters a password. If the password is valid, the boot wait is terminated and the operator can now access the NetBootLoader. If the password is invalid, the
telnet login procedure is terminated and the boot operation continues.
In the case of an invalid password, the login procedure may be repeated as often as required
within the boot wait time. Once the boot wait time is exceeded, a telnet login is no longer possible.
5.4.5FLASH Operations
To achieve an operable system for an application, the application software must be programmed to FLASH. The NetBootLoader supports the programming of the application to
FLASH. In addition to this, it also supports the updating of the NetBootLoader itself as well as
data transfer from the FLASH to the data buffer and from the data buffer to an ftp server. The
following chapters provide information on performing the various types of FLASH operations.
5.4.5.1FLASH Offsets
All FLASH is treated as one uniform FLASH, regardless of the physical addresses of the devices involved. If a DIL FLASH is plugged in the Memory Expansion socket, it is added to the
FLASH area as well. All offsets are based from the beginning of the FLASH area. This means
that 0x0 is the beginning of the first FLASH bank. The NetBootLoader itself is located at the
beginning of the FLASH area and for this reason this area cannot be used for application image
programming. To display an overview of the current FLASH organization use the “info” command.
If the application image is an operating system (which is the default case), it must be programmed without an offset. When such an image is programmed to FLASH, the image length
and CRC information is also programmed along with the image to FLASH. This information is
used by the NetBootLoader to determine the validity of the image during the boot operation.
During system startup, a valid image is copied to SDRAM address 0x0 and started at offset
0x100 after the boot wait time is exceeded.
If an offset is specified, the image will be programmed exactly at this offset without adding
length or CRC information. This option is intended for the storing of configuration information
which is required to be located in FLASH.
The application image itself must be compiled and linked to run from the SDRAM base a ddress
0x0 of the CPU. The image must contain executable PPC code at offset 0x100 which is the
usual case with ROM/Flash images.
Gaining access to the image for programming to FLASH depends on where it is located. The
NetBootLoader can access three different sources for images:
• ftp server
• Motorola S-Records
• memory within the visible address range of the CPU board
The NetBootLoader uses a single data buffer for downloading an image from an ftp server or
an image as Motorola S-Records. These images must first be downloaded to the data buffer
prior to being programmed to FLASH. An image located within the visible address range of the
CPU board is directly accessible for programming.
To access an image located on an ftp server, the “get” command is used. To perform Motorola
S-Record acquisition, the “sl” (SLoad) command is used. Once the image is in the data buffer,
the FLASH is programmed using the “lf” (Load Flash) command. For an image within visible
memory, the “lf” (LoadFlash) command is used to program directly to FLASH.
5.4.5.3ftp Server Access
To gain access to an application image file stored on an ftp server the Ethernet interface is
used. Images are downloaded to the data buffer using the f tp protocol. To use this interface the
Ethernet parameters must first be set and then the system must be rest a rted. During boot wait
the operator must gain control of the NetBootLoader and perform an ftp server login. After a
successful login, the operator then locates the image file required and downloads it to the dat a
buffer. As with any type of server session, the operator should logout when the session is finished.
Note ...
The commands “get” and “ls” use the same data buffer. Therefore if an “ls” command is issued after a “get” command the dat a buffer will be overwritten. If an “lf”
command follows the “ls” the NetBootLoader refuses to program the overwritten
data buffer to the FLASH.
5.4.5.4Motorola S-Records
The NetBootLoader will also accept Motorola S-Records as an application image. The “sl”’
command accepts S1, S2 and S3 records. Operation is terminated by the appropriate S9, S8
or S7 record. Other types of records are ignored.
The checksum of every record except end records is checked. Bad records are rejected by the
NetBootLoader. The address range of every record is also checked. Records which fall outside
of the internal buffer are rejected.
The records must be 0-based. This means that it’s address must correspond to the address
where they will be loaded in the data buffer relative to its start. If necessary, the base address
can be modified with the -o option of the “sl” command.
If the data buffer is programmed to FLASH without the -o option (program a startable image) the downloaded image is copied to RAM during startup and is executed there. For this reason application images which require to be programmed
must start at the address 0x0.
The image must start at the absolute address 0x0 and must contain executable PPC code at
the absolute address 0x100. If S1 or S2 record input is preferred, please note that these
records only include 16 and 24-bit wide addresses. If no switch to another record type is included it must be ensured that the code is not larger than the address range covered.
Note ...
Neither the “sl” nor “If” command can be used to program Motorola S-Records to
RAM areas.
For accessing the Motorola S-Records, both the TERM and SER0 interfaces can be used. The
user LED (“U”) flashes slowly while downloading indicating that the transfe r is in progress. The
transfer itself may take several minutes to complete.
Ensure that the XON/XOFF protocol is used on the host side. This is a fixed setting and cannot
be changed. Additionally, ensure that the host does not stop transmission after a number of
lines (e.g. OS-9: use the ‘nopause’ attribute).
The TERM and SER0 serial interface parameters can be modified with the “pf” command.
5.4.6Updating the NetBootLoader
In addition to programming an application to FLASH, the NetBootLoader it self can be up dated.
The new version of the image can be made available in one of two ways:
• Via an ftp server
• Via a DIL FLASH device
5.4.6.1Updating With an Image Loaded Via an ftp Server
The image is downloaded in the same way as an application image (refer to chapter 5.4.5.3).
The new version of NetBootLoader image is then programmed using the “clone -n” command.
5.4.6.2Updating Via a Separate DIL FLASH
The new version of the NetBootLoader image must be programmed to a separate DIL FLASH
device (e.g. AM29F040) with an external programmer and then plugged on the Memory Exp ansion socket of the CPU board. The NetBootLoader must be started and operator must gain control of the NetBootLoader. Either the current NetBootLoader (Boot Jumper removed) or the new
NetBootLoader version (BootJumper inserted) may be used for this operation.
The “clone” command is then used to program the new NetBootLoader version to FLASH.
If for some reason the NetBootLoader programmed in the soldered FLASH has been improp-
erly modified (e.g. by a program which accidentally erases or overwrites the chips), this is the
only method to reprogram the onboard soldered FLASH. In this case, the boot operation must
be started with the Boot Jumper inserted (boot from DIL FLASH).
The NetBootLoader also has the possibility to upload certain areas of the FLASH to a host using the Ethernet interface. To use this interface the Ethernet parameters must first be set and
then the system must be restarted. During boot wait the op erator must gain control of the NetBootLoader and perform an ftp server login. After a successful login, the operator then stores
the FLASH area to be uploaded to the local data bu ffer using the “sf” comma nd. Using the “put”
command transfers the contents of the data buffer to the ftp server. As with any type of server
session, the operator should logout when the session is finished.
5.5Plug and Play
On the CPU board the NetBootLoader includes “Plug and Play” functionality . This ensures that
the board is completely initialized and that all resources necessary for PCI devices (addresses,
interrupts etc.) are assigned automatically. This important feature has the advantage that conflicts do not arise when PCI devices are a dded or removed. Furthermore, the operating system
itself does not include the board initialization code.
5.6Porting an Operating System to the CPU Board
The image for the absolute address 0x0 should be linked with an entry point at the absolute
address 0x100.
One should not attempt to reassign the PCI BAR registers. The assigned values should be read
back and these should always be used in the drivers.
The “interrupt line” field in the PCI configuration header is initialized with the IRQ line number
to which the INTA of the device is routed.
It is not necessary to rewrite the “EUMBBAR” field in the KAHLUA (MPC 8240) configuration
space as this has already been done by the NetBootLoader. The existing value should be used.
Downloaded images are never executed from the FLASH due to the fact t hat on the CPU board
it is paged. The programmed image is always downloaded to SDRAM, the absolute address
0x0 being downloaded first. There is no configuration option available to amend this process.
If it is necessary to relocate the image to another address after download, simply add a small
assembly routine at the beginning of the code which will move the image to the correct address.
The following commands are available with the NetBootLoader. Where an ellipsis (…) appears
in the command syntax it means that the command is continued from the previous line. Observe any spaces that may be between the ellipsis and the remainder of the command.
ABORT
FUNCTION:Terminate the NetBootLoader boot operation
SYNTAX:
DESCRIPTION:This command is used by the operator to to terminate the boot
abort
operation during the boot wait time to allow the operator to perform
other NetBootLoader operations. To be asserted it must be issued
during the boot wait time which is indicated by the flashing green
user LED (U) on the CPU board front panel.
BW
FUNCTION:Set or display the parameters of the boot wait function of the
NetBootLoader
SYNTAX:
bw [<time>| -f]
where:
bwcommand
<time>parameter: value: seconds
1, 2, 5, 10, 20, 50
-foption:
force CRC update
DESCRIPTION:The command “bw” displays the parameter “<time>” setting.
The parameter “<time>” stipulates the waiting time in seconds that
the boot operation is delayed before the application is loaded and
started. No values other than these are supported.
Bear in mind when setting the boot wait time that the green user LED
(U) flashes at the rate of two times a second. Therefore, if the boot
wait is set to 1 second the LED will only flash two times.
DESCRIPTION:If an ftp server session has been established with the “login”
cd <new-path>
where:
cdcommand
<new-path>parameter: string
new directory path
command, the command “cd” is used to change the current ftp server
directory.
The argument “<new-path>” may be an absolute or relative path. The
format depends on what the server accepts. For example, UNIX
hosts require that the directory names must be entere d exactly in the
same case.
CHECK
FUNCTION:Verify validity of application programmed to FLASH
SYNTAX:
DESCRIPTION:When an application is programmed to FLASH, a CRC is performed
USAGE:Veriy valid application is stored in FLASH
check
and the results are stored in FLASH along with the application. The
“check” command is used to verify that the current application image
in FLASH is valid.
DESCRIPTION:To update the NetBootLoader itself, the command “clone” is used.
DESCRIPTION:DIL FLASH it is programmed directly to the onboard soldered
clone [-n]
where:
clonecommand
-noption:
program from data buffer
The application image source for programming may either be the
data buffer or a DIL FLASH installed in the Memory Expansion
socket. If the source is the data buffer, the image must first be
downloaded to the data buffer from an ftp server. If the image is in the
FLASH.
To program directly from the DIL FLASH, the command “clone” is
used without the “-n” option. The update will be programmed even if
the CPU board has been initialized from the DIL FLASH (Boot jumper
installed) with the new image.
To program from the data buffer, the command “clone -n” is used.
In both cases, the new image is checked for validity. If an image is
invalid, the update is aborted. Additionally, the operation must be
confirmed by typing the word “yes”. Any other or no input will cancel
the operation.
DESCRIPTION:To download a file from the ftp server to the local data buffer, the
command “get” is used. A successful ftp server login must be carried
out before a file can be downloaded and the file must be in binary
format.
The argument “<filename>” must refer to an existing and accessible
file on the server and the syntax must follow the requirement s on the
server, e.g. case sensitiveness. The argument may also include a
path specification, if the server supports this.
HELP or ?
FUNCTION:Display online help pages
SYNTAX:
help
?
DESCRIPTION:This command displays the online help pages. The display of the
help text varies between the different CPU’s reflecting their
differences.
The syntax of every command and a brief description is shown. The
display output pauses after every page. The output can be continued
with any key. Entering a “.” (period) aborts the help function.
INFO
FUNCTION:Display system information
SYNTAX:
info
DESCRIPTION:The command “info” is used to display an information summary for
the running system. The CPU type, the board type, and the detected
FLASH layout are displayed.
DESCRIPTION:If no offset option (“-o”) is specified the image is considered to be
valid and is therefore added along with CRC and length information.
If the CRC is determined to be valid during the next startup, the
image is copied to the absolute address 0x0 and started at 0x100
after the boot wait time has been exceeded.
Normally, the local data buffer holds the image to be programmed.
However, if the “-m” and “-l” parameters are specified, the image is
programmed from the absolute address specified.
If “<offset>” is specified, the contents are programmed exactly at this
offset in FLASH. No length and no CRC information is added.
The “-k” option can be specified to prevent deletion of the
surrounding FLASH contents.
FLASH memory can only be erased sector-wise. If an image is
programmed to a certain offset with the “-o” option, at least this
sector (and maybe one or more of the following sectors depending
on the size of the image) will be erased. The “-k” option can be used
to retain the surrounding data, however, this slows down the
operation significantly.
To achieve fast programming of parameter images without
destroying other FLASH contents, the data should be placed at a
sector boundary and the sector(s) must not contain any ot her data or
executable images. If organized this way, use of the “-k” option can
be avoided.
Note: The “lf” command cannot be used to program the NetBootLoa der.
USAGE:Program FLASH from data buffer and add CRC and image length
COMMAND / RESPONSE (none):
lf
Program FLASH from data buffer to offset 0xF4240
COMMAND / RESPONSE (none):
lf -o=f4240
Program FLASH from visible address at 0x87000000 for length of
0x123456
Program FLASH from data buffer to offset 0xF4240 and retain adjacent
FLASH contents
COMMAND / RESPONSE (none):
lf -o=f4240 -k
login <ip-of-host> <username> [<password>]
where:
logincommand
<ip-of-host>parameter: value: numerical string
IP address of host: nnn.nnn.nnn.nnn
<username>parameter: value: string
ftp server “username”
<password>parameter: value: string
user’s password
DESCRIPTION:The command “login” is used to establish an ftp server session. The
“<ip-of-host>” must be specified as four numbers separated by single
dots. The “<password>” parameter is not necessary if the server does
not request one.
USAGE:Initiate ftp server session
COMMAND / RESPONSE:
login 192.168.47.12 johndoe mypassword
(Response is dependent on the server accessed)
LOGOUT
FUNCTION:Terminate telnet session with NetBootLoader
DESCRIPTION:A remote telnet session will be terminated with the command
logout
“logout”. No application is loaded and started if the session is
terminated with “logout”. The NetBootLoader waits fo r a new session
to be initiated or for a command entry from the serial console.
LS
FUNCTION:Display listing of the current ftp server directory
SYNTAX:
DESCRIPTION:To display a listing of the current ftp server directory the command
ls
“ls” is used. This command downloads the listing to the data buffer
and then the listing is displayed. Any previously loaded image in the
data buffer is overwritten. If an attempt is then made to program the
FLASH after the “ls” command has been issued it will fail.
MD
FUNCTION:Display visible memory
SYNTAX:
DESCRIPTION:To display a visible memory area the command “md” is used. The
md [<adr>]
where:
mdcommand
<adr>parameter: value: hexadecimal
starting address of a visible memory area
first time the command “md” is issued, visible memory contents
starting at the address 0x0 are displayed if no “<adr>” parameter is
used. If issued again without the “<adr>” parameter , the display st arts
with the end address of the previous display. Data is displayed as
hexadecimal 32-bit words and as ASCII dump.
FUNCTION:Set or display the parameters for the Ethernet interface
SYNTAX:
net [<ip-addr>][-netmask <netmask>]
…[-gw <gateway>][-f]
where:
netcommand
<ip-addr>parameter: value: numerical string
IP address of CPU board: nnn.nnn.nnn.nnn
-netmaskoption: netmask
<netmask>parameter: value: numerical string
netmask of CPU board: nnn.nnn.nnn.nnn
-gwoption: gateway
<gateway>parameter: value: numerical string
gateway address for network: nnn.nnn.nnn.nnn
-foption:
force CRC update
DESCRIPTION:To set or display the parameters of the Ethernet interface the
command “net” is used.
Initially the CPU board does not have a valid Ethernet interface
configuration, and, therefore, this interface is inoperable. The initial
configuration must be done from the TERM interface using the
command “net ... -f”.
Using the “-f” option forces a CRC to be performed and stored along
with the other configuration parameters in the serial EEPROM.
Once the initialization of the Ethernet interface is done, the CPU
board must be restarted for the parameters to take effect. Later
changes to the parameters do not require the use of the “-f” option to
force a CRC. This is done automatically. Only in the event that the
Ethernet interface does not properly initialize, may it be necessary to
re-enter the parameters using the “-f” option.
command “passwd” is used. This command is interactive, meaning
that after it is issued, the NetBootLoader responds with an
appropriate request to the operator which must be properly
acknowledged or the operation fails (refer to USAGE below).
To set the password in the event it is unknown, use the option “-f”.
This is can only be accomplished from the TERM interface and not
from the Ethernet interface.
With the option “-d”, the remote telnet login can be disabled by
invalidating the password.
USAGE:Set password
COMMAND / RESPONSE:
NetBtLd> passwd
Old Password: *****
New Password: *****
Type again: *****
NetBtLd>
(The old password must be known)
Set password when the old password is not known
COMMAND / RESPONSE:
NetBtLd> passwd
New Password: *****
Type again: *****
NetBtLd>
DESCRIPTION:The command “pci” is used to display detailed information on all
pci
detected PCI devices. The bus number, device number, function
number, vendor, and device ID’s are displayed together with the
configured base addresses and the assigned IRQ number.
PF
FUNCTION:Set or display the serial port parameters (format)
DESCRIPTION:T o set or display the operational paramete rs for the available serial in-
terfaces the command “pf” is used.
At startup the settings for the “TERM” and “SER0” interfaces are al-
ways set to the default values (9600/8/n/1). This is to avoid a possible
system lockout. If other settings are required during operation of the
NetBootLoader they may be made. If changes are made, it must be
ensured that corresponding parameters are used for th e operator consle.
Issuing this command without parameters being spe cif ied will display
the current serial port settings.
Syntax-wise, no spaces are permitted between the parameters and
they must be separated with a slash. Not all parameters must be
specified, but the “/” characters must be present to distinguish the
different parameters from each other. The sequence can be aborted
after every option.
USAGE:Set “TERM” to 300 Baud, 7 Bits/char, odd parity, and 2 stop bits
COMMAND / RESPONSE (none):
pf term 300/7/o/2
Set the bits per character parameter of “SER0” to 7
COMMAND / RESPONSE (none):
pf ser0 //7
Set the stop bits parameter of “SER0” to 2
COMMAND / RESPONSE (none):