This PepCard product is carefully designed for a long and fault-free life; nonetheless, its life expectancy can be drastically
reduced by improper treatment during unpacking and installation.
Observe standard anti-static precautions when changing piggybacks, ROM devices, jumper settings, etc. If the product
contains batteries for RTC or memory back-up, ensure that the board is not placed on conductive surfaces, including antistatic plastics or sponges. These can cause shorts and damage to the batteries or tracks on the board.
When installing the board, switch off the power mains to the chassis. Do not disconnect the mains as the ground
connection prevents the chassis from static voltages, which can damage the board as it is inserted.
Furthermore, do not exceed the specified operational temperature ranges of the board version ordered. If batteries are
present, their temperature restrictions must be taken into account.
Keep all of the original packaging material for future storage or warranty shipments. If it is necessary to store or ship the
board, re-pack it as it was originally packed.
IssueBrief Description of ChangesPCB IndexDate of Issue
1Issue 101-01/2March, 1995
2General Corrections throughout Manual01-01/4June, 1995
2.0.1Correction of Figure 3.2.0.1 (Jumper Layout Solder Side)01-01/4July, 1995
3Updated for board index 0202December, 1995
This document contains proprietary information of PEP Modular Computers. It may not be copied or transmitted by
any means, passed to others, or stored in any retrieval system or media, without the prior consent of PEP ModularComputers or its authorized agents.
The information in this document is, to the best of our knowledge, entirely correct. However, PEP ModularComputers cannot accept liability for any inaccuracies, or the consequences thereof, nor for any liability arising from
the use or application of any circuit, product, or example shown in this document.
PEP Modular Computers reserve the right to change, modify, or improve this document or the product described
herein, as seen fit by PEP Modular Computers without further notice.
We grant the original purchaser of PEP products the following hardware and system warranty. No other warranties that
may be granted or implied by anyone on behalf of PEP are valid unless the consumer has the express written consent of
PEP Modular Computers.
PEP Modular Computers warrants their own products (excluding software) to be free from defects in workmanship
and materials for a period of 24 consecutive months from the date of purchase. This warranty is not transferable nor
extendible to cover any other consumers or long term storage of the product.
This warranty does not cover products which have been modified, altered, or repaired by any other party than
PEP Modular Computers or their authorized agents. Furthermore, any product which has been, or is suspected of
being damaged as a result of negligence, misuse, incorrect handling, servicing or maintenance; or has been damaged as a
result of excessive current/voltage or temperature; or has had its serial number(s), any other markings, or parts thereof
altered, defaced, or removed will also be excluded from this warranty.
A customer who has not excluded his eligibility for this warranty may, in the event of any claim, return the product at
the earliest possible convenience, together with a copy of the original proof of purchase, a full description of the
application it is used on, and a description of the defect; to the original place of purchase. Pack the product in such a way
as to ensure safe transportation (we recommend the original packing materials), whereby PEP undertakes to repair or
replace any part, assembly or sub-assembly at our discretion; or, to refund the original cost of purchase, if appropriate.
In the event of repair, refund, or replacement of any part, the ownership of the removed or replaced parts reverts to
PEP Modular Computers, and the remaining part of the original guarantee, or any new guarantee to cover the
repaired or replaced items, will be transferred to cover the new or repaired items. Any extensions to the original guarantee
are considered gestures of goodwill, and will be defined in the "Repair Report" returned from PEP with the repaired or
replaced item.
Other than the repair, replacement, or refund specified above, PEP Modular Computers will not accept any liability
for any further claims which result directly or indirectly from any warranty claim. We specifically exclude any claim for
damage to any system or process in which the product was employed, or any loss incurred as a result of the product not
functioning at any given time. The extent of PEP Modular Computers liability to the customer shall not be greater
than the original purchase price of the item for which any claim exists.
PEP Modular Computers makes no warranty or representation, either express or implied, with respect to its
products, reliability, fitness, quality, marketability or ability to fulfill any particular application or purpose. As a result,
the products are sold "as is," and the responsibility to ensure their suitability for any given task remains the purchaser's.
In no event will PEP be liable for direct, indirect, or consequential damages resulting from the use of our hardware or
software products, or documentation; even if we were advised of the possibility of such claims prior to the purchase of, or
during any period since the purchase of the product.
Please remember that no PEP Modular Computers employee, dealer, or agent are authorized to make any
modification or addition to the above terms, either verbally or in any other form written or electronically transmitted,
without consent.
The computer user today requires high performance to meet high expectations. At the same time, the mass of data that
has to be processed is dramatically increasing, for instance the data that a modern graphic user interface generates.
Additionally, there is a further demand on the communications ability and multi-functionality of the computer.
The VM62(A)/VM42(A) meets all the above requirements, combining high computational performance with excellent
communication ability via the AutoBahn™ Spanceiver™ chip.
A combination of the high performance CPU (Motorola MC68060 or 68040) and the Quad Integrated Communications
Controller chip, the Motorola MC68EN360 or QUICC, not only enables a pure computation performance from
approximately 35 MIPS to over 100 MIPS, but dispenses with the usual restrictions associated with communications
over serial interfaces. Communication tasks are dealt with by the QUICC chip, freeing the CPU from such timeconsuming chores. Fieldbus protocol, such as PROFIBUS, are also handled by the QUICC. In addition, the QUICC,
used together with PEP’s expanding CXC interface is ideally suited for communication tasks extending from 6 serial
interfaces over LAN to WAN (X.25, ISDN) applications. The ‘EN’ version of the QUICC also supports Ethernet on 2
channels (only one usable on the VM42(A)/VM62(A) using PEP standard software).
The various I/O interfaces are realised using piggybacks attached to the main board. Five options are at the moment
available. They are:
PEP’s AutoBahn technology has solved one of the major problems that exist in information technology - data transfer
over the various bus systems. Normally the data transfer rate over a bus system is below the data transfer capability of a
modern CPU chip. The AutoBahn chip (the Spanceiver MC100SX1451) allows transfer rates of up to 100 Mbyte/sec
over the VMEbus using the VMEbus lines SERA and SERB.
PEP has also developed a cost-effective VMEbus backplane series that support AutoBahn, called VBP4A, in 7, 12 and 15
slot options. These backplanes allow direct connection of the main power supply, hence reducing cabling costs
dramatically.
A CXM-SIO3 module is available in order to make all three serial interfaces that are available on the CXC accessible on
the VM62(A)/VM42(A). This is achieved by using RS232, SC-xxx or SI-xxx interfaces. For more details, please refer to
the CXM-SIO3 user’s manual.
AutoBahn ™ and Spanceiver ™ are trademarks of PEP Modular Computers.
VM62-BASEVMEbus single board computer comprising MC68060 @ 50 MHz,
MC68EN360 @ 25 MHz, 256 kByte dual-ported SRAM (with Gold Cap for
backup), configured for use with the AutoBahn interface piggyback, up to 6
serial interfaces (2 available on the front panel as RS232 and an additional 4
divided between the CXC interface and SI-Interface), CXC Interface, PEPbug.
VM62-BASESame as order no. 12349 but with 1 MByte dual-ported SRAM12350
VM42-BASEVMEbus single board computer comprising MC68040 @ 33 MHz,
MC68EN360 @ 33 MHz, 256 kByte dual-ported SRAM (with Gold Cap for
backup), configured for use with the AutoBahn interface piggyback, 6 serial
interfaces (2 available on the front panel as RS232 and an additional 4 divided
between the CXC interface and SI-Interface), CXC Interface, PEPbug.
VM42-BASESame as order no. 12344 but with 1 MByte dual-ported SRAM12345
VM42-BASESame as order no. 12344 but with MC68040V @ 33 MHz (3.3-V technology)12346
VM42-BASESame as order no. 12346 but with 1 MByte dual-ported SRAM12347
DM600Memory piggyback with 4 MByte DRAM and 1 MByte Flash EPROM11852
DM600Memory piggyback with 4 MByte DRAM and 4 MByte Flash EPROM11853
DM601Memory piggyback with 16 MByte DRAM and 1 MByte Flash EPROM11854
DM601Memory piggyback with 16 MByte DRAM and 4 MByte Flash EPROM11855
DM602Memory piggyback with 1 MByte DRAM and 1 MByte Flash EPROM12765
12349
12344
DM603Memory piggyback with 32 MByte DRAM and 512 kByte Flash EPROM13027
DM603Memory piggyback with 32 MByte DRAM and 2 MByte Flash EPROM13627
SI-10B210Base2 (Thin) Ethernet (cheapernet) interface with RG58 (coax) connector9925
SI-10B510Base5 (AUI) Ethernet interface piggyback with 15-pin D-Sub connector9924
SI-10BT10BaseT (Twisted pair) Ethernet interface piggyback with RJ45 connector9926
SI-DUMMYFront panel only fitted when no SI piggyback required12351
SI-PB232Serial interface piggyback for 2 RS232 connections (Modem interface) with 2
RJ45 connectors
SI-PB232-ISOSerial interface piggyback for 1 RS232 optoisolated connection with 1 RJ45
connector (Available in 1996 if requested)
SI-PBPRORS485 optoisolated interface piggyback for 2 wire half-duplex (PROFIBUS)
connection with 9-pin D-Sub connector
MP-AB100AutoBahn interface piggyback complete with all control logic, 128 kByte 32-
bit fast SRAM as buffer for AutoBahn data transfer with Spanceiver MC
100SX1451 of 50/100 MByte/s
CABLE-VM42-
232
3 meter RS232 Serial Interface cable for VM42(A) / VM62(A) with 9-pin
CXM-SIO3-1CXM module with 3 RJ45 connected RS232 ports for use with a CXC
backplane
CXM-SIO3-1CXM module with 3 RJ45 connected RS232 ports, compatible for direct
connection to a CPU board
CXM-SIO3-2CXM module with 2 RJ45 connected SC piggyback ports and one SI
piggyback interface, no front panel (delivered with SC piggyback) for use with
a CXC backplane
CXM-SIO3-2CXM module with 2 RJ45 connected SC piggyback ports and one SI
piggyback interface, no front panel (delivered with SC piggyback), compatible
for direct connection to a CPU board
CXM-SIO3-3CXM module with 3 RJ45 connected SC piggyback ports for use with a CXC
backplane
CXM-SIO3-3CXM module with 3 RJ45 connected SC piggyback ports, compatible for direct
connection to a CPU board
CXM-SIO3-4CXM module with 3 15-pin D-Sub connected SC piggyback ports, 8TE front
panel for use with a CXC backplane
CXM-SIO3-4CXM module with 3 15-pin D-Sub connected SC piggyback ports, 8TE front
panel, compatible for direct connection to a CPU board
TBD
13692
TBD
13693
TBD
13694
TBD
13695
Each VM62(A)/VM42(A) comes complete with 2 RS232 serial interfaces situated on the lower half of the front panelThese interfaces are provided with TxD and RxD signals by the SMC1 and SMC2 channels of the ‘QUICC’ controller.
The SCC1 channel of the ‘QUICC’ provides the interface to one of the available SI-xxx piggybacks. All other channels
(SCC2, SCC3 and SCC4) of the ‘QUICC’ are ported to the CXC interface except for the SI-PB232 piggyback which has
on-board additional control provided by the SCC4 channel through the SI Interface.
As mentioned above, a CXM-SIO3 module is available in order to make all the serial interfaces accessible on the
VM62(A)/VM42(A). For more details, please refer to the CXM-SIO3 user’s manual.
Important: The VM62(A)/VM42(A) must be ordered with a memory module (DM60x) and a front
MC6806066 or 50 MHz(3.3V)
MC6804033 or 25 MHz
MC68040V33 or 25 MHz(3.3V)
MC68LC04033 or 25 MHz
MC68EN360, 25 or 33MHz used in companion mode
1, 4, 16 or 32 Mbyte
0.5, 1, 2, or 4 MByte
1 MByte or 256 kByte (dual-ported, backed-up using Gold-Caps)
2 kbit (serial); 1 kbit available for applications
Master and slave with optional AutoBahn Interface (100 MBytes/sec)
Single level (BR3*), release-when-done daisy-chain
Standard Superv./User Prog./DataHEX 39/3A/3D/3E
User DefinedHEX 10-17/18-1F
Short I/OHEX 29/2D
System controller functions
•Automatic First Slot Detection (FSD)
•SYSRES*(disabled by jumper)
•SYSCLK*(disabled by jumper)
•ACFAIL*
•SYSFAIL*
•Power monitor
•Bus monitor(programmable)
•VME IRQ mask register
A24:D16
Dual-port SRAM
1 Mailbox IRQ
Interrupt Control
7 Level VME IRQ Handler,
maskable via VME IRQ mask
register
System vectors
* Available for Index 02 boards or later.
Slave
1 Mbyte window, software programmable base (1 out of 16 addresses)
Lower 8kBytes of the SRAM area
RISC controller (in the 68EN360) with 14 dedicated DMA channels
4*multiprotocol SCCs up to 8 MBaud
with one (two) supporting IEEE 802.3/Ethernet up to 10 Mbit/s
10Base5, 10Base2 or 10BaseT
2*UARTs RS232 (XON/XOFF) RS232 up to 120 kBaud
4 independent baud rate generators
CXC Interface
- 16 bit asyncronous data transfer with 4 IRQs,
independent DMA channel
- 3 serial interfaces
TICK
General Purpose
Watchdog
Special Functions
Real-time clock (backed-up)
Serial EEPROM
DMA
Front Panel Functions
Data Retention
Short term backup for RTC and
SRAM via on-board Gold-Cap
Periodic Interrupt Timer, programmable
4*16 bit or 2*32 bit, programmable
512 ms time-out for reset, programmable
Date (year, month, week, day)
Time (hour, minute, second)
1 kbit for board specific data (serial number, Internet address, etc.)
+ 1 kbit for application purposes
2 independent channels (supports single and dual address transfers
between all offboard locations including DRAM, FLASH,
AutoBahn memory, CXC and VME)
RESET button
ABORT button
HALT LED (red)
Watchdog LED (yellow)
General purpose LED (green)
The Table below illustrates the capabilities of the available CPUs. The 68060 processors operating at 50 MHz deliver up
to 100 MIPs while the 68040 processors operating at 33 MHz give performances up to 35 MIPs.
25/33 MHz - the ‘QUICC’ chip used in ‘companion mode’ is tightly coupled to the CPU. Working as an I/O and system
controller, it provides all the necessary interfaces, timers and clocks etc. in addition to the DRAM memory controller.
Serial Channels
Six are provided by the ‘QUICC’ - Two SMC channels are ported to the front panel and the remaining four SCC channels
may be optionally configured as shown below.
Three different piggybacks complete with all the associated control logic are available providing 10Base5, 10Base2 or
10BaseT interfaces.
Note
The SI-10B5 piggyback requires an external +12V power source to operate.
Fieldbus Interface (SI-PBPRO)
This is a fully optoisolated RS485 (PROFIBUS) interface piggyback with a 9-pin D-Sub connector.
RS232 Serial Interface
Two piggybacks are available with RJ45 connectors for MODEM compatible communication.
AutoBahn Interface (MP-AB100)
This is realised via a piggyback containing all the necessary control logic, 128 kByte high speed SRAM (10 ns) as a
memory buffer between the processor and the AutoBahn chip (MC 100SX1451) for communication on the high speed
serial data lines over pins b21 and b22 of the VMEbus.
DMA Channels
2 independent channels are provided by the ‘QUICC’ chip and can be used by applications requiring data transfer between
CXC-modules, DRAM, FLASH memory, dual-ported SRAM and AutoBahn memory buffers. This memory can be
configured with different memory options allowing tremendous flexibility when customising memory requirements for
real-time applications.
DRAM/FLASH
This memory, complete with a 32 bit data wide access bus is placed on a piggyback with addressing capability for up to
two memory banks of 64 MByte each. On-board +5V FLASH memory provides the latest ROM technology allowing the
user to take advantage of the on-board programming facility to produce low cost upgrades by simply overwriting existing
stored data.
SRAM
This is a dual-ported battery-backed (Gold-Cap) memory area with a 16 bit data wide access bus. Users of the VMEbus
and the on-board CPU both have access to this memory. The lower 8 kByte are reserved for the location monitor.
EEPROM
Although a 2 kbit EEPROM is provided on-board, 1 kbit has been pre-programmed with PEP production data (boot info,
Ethernet registration, etc) leaving the remaining 1 kbit for user application code. A write protect jumper prevents
accidental erasure.
Motorola’s MC68EN360 is a 32 bit high performance communication controller, combining powerful peripheral
functions with system integration functions and an on-chip microprocessor core (CPU32+).
On the VM62(A) / VM42(A), the on-chip CPU core is disabled and replaced with a more powerful external CPU, the
MC68040 or MC68060. The 68EN360 operates as a slave to the CPU in so-called ‘Companion Mode’. In this mode, the
68EN360 provides complete I/O functionality. The DMA channels can still obtain ownership of the CPU’s system bus
and therefore all on-chip DMA channels can address the whole of the address space. Moreover, important functions for
system integration, such as memory controller, clock generation, interrupt controller etc. are available in this mode,
meeting the requirements for the initialisation of the 68EN360, described later in this manual.
The programming of the 68EN360 begins by determining the block of on-chip RAM and registers via the MBAR
register. This register is located at a fixed address and can only be accessed in CPU space.
2.2 Address Decoder
2.2.1 Basic Structure
The address decoder of the VM62(A) / VM42(A) consists of two basic parts. A primary address decoder pre-decodes the
select signals for the processor data bus (in front of the bussizer) and for the I/O data bus (behind the bussizer). With
reference to initial boot cycles, the primary address decoder passes or enables a secondary address decoder stage. The
secondary address decoder stage is realised using the programmable chip slect logic of the MC68EN360. The 8 outputs of
the 68EN360 chip select logic are used for the base addresses of the various memory and I/O address ranges.
2.2.2 Boot Decoding
Due to the fact that the default boot memory used by the VM62(A) / VM42(A) is FLASH memory, which is completely
reprogrammable, a special boot decoder is provided. The boot memory is jumper selectable, the user having the choice
between FLASH (default), VMEbus memory or the on-board AutoBahn Interface. The boot decoder redirects the physical
address range 0H to 1000000H from either FLASH (DM60x), VMEbus or MP piggyback, providing the selected boot
memory is initially accessed.
Note
VMEbus boot memory must be located at VME base address 0H in Standard Supervisor Program/Data
address space.
The primary address decoder generates the following select signals.
CS_360Secondary address decoder (68EN360, DRAM, FLASH)
CS_VMEVMEbus address range
CS_AUTAutoBahn Interface address range
CS_BSSBussizer address range (VME, SRAM, AutoBahn, I/O)
BERR_0Reserved address range (Bus Error)
EN_BSS68EN360 DMA address range
IACKInterrupt Acknowledge Cycle
2.2.4 Secondary Address Decoder
The secondary address decoder is built by the 68EN360 chip select logic and is therefore programmable. The outputs are
used as base address selects, as shown below.
68EN360 Chip SelectConnected to
CS0FLASH
CS1DRAM
CS2VME via 68EN360 DMA
CS3AutoBahn Interface
CS4SRAM
CS5CXC
CS6RTC
CS7Control / Status Registers
00 xx xx xx
04 xx xx xx
07 00 0x xx
09 xx xx xx
0A xx xx xx
0B xx xx xx
0C xx xx xx
0D xx xx xx
1x xx xx xx
2x xx xx xx
3x xx xx xx
4x xx xx xx
5x xx xx xx
6x xx xx xx
82 xx xx xx
83 xx xx xx
85 00 xx xx
87 xx xx xx
87 xx xx xx
9x xx xx xx
Ax xx xx xx
Bx xx xx xx
C0 xx xx xx
C4 xx xx xx
C7 xx xx xx
CA xx xx xx
CB F7 0x xx
CC xx xx xx
CD 00 00 01
CD 00 00 05
CD 00 00 07
Dx xx xx xx
Ex xx xx xx
Fx xx xx xx
The following address area is non-cachable serialised.
VMEbus (CS_VME), user-defined AM code
VMEbus (CS_VME), user-defined AM code
VMEbus (CS_VME), short I/O AM code
VMEbus (CS_VME), user-defined AM code
DMA-VME, 68EN360’s CS2
In order to determine the base of the 68EN360’s internal memory map, the module base address register
(MBAR) must be set. The location of this register is fixed in the address area Supervisor CPU Space at
3FF00H. For more information, please refer to the Software Configuration chapter in this manual.
Memory to memory transfers with the 68EN360 DMAs are possible with any combination of on-board and VME
addresses. In order to achieve address compatibility between CPU/VME and DMA/VME transfers, it is recommended that
the initialisation of CS2 be initialised to the standard VME address space as described in the Software Configuration
chapter in this manual.
2.3 VMEbus Interface
The VM62(A) / VM42(A) has a complete master interface for the P1, J1 VMEbus connector. It consists of a VMEbus
arbiter, requester, system controller and buffers for data/address/control signals. In addition, the VM62(A) / VM42(A)
provides a VMEbus slave interface which consists of a programmable board address decoder, a dual-ported RAM and a
mailbox interrupt controller.
2.3.1 System Controller
The VM62(A) / VM42(A) can act as a VME system controller with arbiter, system clock driver, power monitor with
system reset driver, IACK daisy chain driver and 7-level VMEbus interrupt controller.
Arbitration is single level FAIR1 on BR3*. If the VM62(A) / VM42(A) is used as system controller it has to be placed
in slot 1 of the VMEbus backplane (furthermost left slot). There is no jumper setting necessary, as the board provides a
‘first slot detection’ function which is also readable within the VME control / status register. The IACK daisy chain
driver is supplied by connecting the IACKIN* and IACKOUT* line. IACK* is connected via the VMEbus backplane for
IACKIN* of slot 1.
VME SYSCLK* and SYSRES* can be routed from on-board using jumpers, leaving the choice of generating these
signals by the system controller to the user. SYSFAIL* generates a maskable on-board autovectored interrupt (see also
External Autovector Requests). ACFAIL* generates a non-maskable autovector level 7 interrupt (NMI) in the same way
as the ABORT button. When an ACFAIL* NMI is detected, it can be differentiated from an ABORT by reading bit 1 of
the Board Control/Status Register (bit 1 is set to ‘1’ for ACFAIL*). If this is the case, the CPU should stay in the IRQ
service routine and save any important data to non-volatile memory.
The VM62(A) / VM42(A) also provides a bus monitor for the VMEbus. A 128µs timeout timer monitors VMEbus data
transfer cycle lengths and generates a VMEbus BERR* signal for error termination. This timer is enabled/disabled via the
VME control / status register which also supplies a timeout status bit in order to identify bus errors generated by the bus
monitor.
2.3.2 Dual-Ported SRAM
The VM62(A) / VM42(A) provides on-board SRAM of either 256 kByte or 1 Mbyte. The SRAM is 16- bit wide and
dual-ported between the CPU/DMA and VME, accessible through an on-board arbiter. Read-Modify-Write cycles (TAS
instruction used for semaphores) are supported in any direction. The location of the dual-ported SRAM as seen from the
VME is programmable via the VME control / status register. There are 16 different base addresses possible that are all
located in the VME standard supervisor / user data space. Enable / disable is selected using a separate bit.
Note
The lower 8 kBytes of dual-ported SRAM should not be accessed from the VME because this area is
reserved for mailbox interrupts.
1
FAIR according to VME 64 Specifications, Rule 3.14 and Observation 3.17.
An external VMEbus master may interrupt the VM62(A) / VM42(A) by setting P_IRQ5 (pending mailbox IRQ) in the
VME control / status register. The address of this dual-ported register seen from VME is identical to the base address of
the dual-ported SRAM, occupying the lower 8 kBytes (odd byte addresses) of the dual-ported SRAM.
Setting P_IRQ5 generates an autovector 5 interrupt on the CPU. Typically, the on-board CPU resets P_IRQ5 during the
processing of the corresponding interrupt service routine.
Note
Although every odd address of the 8k block of the VME control / status register can be accessed from
VME, only the P_IRQ5 bit can be set. All other bits are write protected from the VME. As the
P_IRQ5 bit is located at bit 7 within the register, it can be directly used as a semaphore because readmodify-write (TAS instruction) is supported.
2.3.4 VMEbus Control / Status Register
Address:CS7 + $5PEP Default Address $CD 00 00 05
Format:Byte
Access:read / write
Value after HW reset:see table
CS7 + $5
P_IRQ5FSDEN_BERR2EN_DPR
BADR2BADR3BADR1BADR0
Register Description
NameValueReset (HW)Reset PEP (SW)Description
Slot 1OtherSlot 1Other
P_IRQ5
10000Pending mailbox IRQ
bit 7
EN_DPR
bit 6
100
Value
stored in
EEPROM
Value
stored in
EEPROM
Dual-port RAM (including mailbox
IRQ) for VME requester enabled. Base
address fixed through BADRx bits
EN_BERR2
bit 5
FSD
bit 4
BADR3
- BADR0
bits 3 - 0
10010Enable bus monitor timer, all VME
cycles, timeout after 128µs
11010VMEbus ‘First Slot Detection’ flag,
system controller
00
Value
stored in
EEPROM
Value
stored in
EEPROM
VME address location of dual-ported
RAM. Equivalent to VME address lines
A23 - A20, programmable from $0 - $F
in 1 Mbyte windows, enabled with
EN_DPR. See Table on next page.
The interrupt control logic processes internal interrupt requests (68EN360), together with external requests (VME) and
external autovectored interrupt requests. The interrupt control logic is built up using the 68EN360 internal interrupt
controlling and a 7-level VMEbus interrupt handler with the corresponding mask register.
2.4.1 Internal Requests
Internal requests are related to all interrupt requests caused by the 68EN360 sources, including the 68EN360 system
integration functions (watchdog timer, periodic interrupt timer) and the communication processor module (RISC
controller, timers, DMAs, SCCs and so on). For more information, please refer to the 68EN360 User’s Manual.
In order to avoid conflicts regarding interrupt levels, it is recommended to use IRQ level 4 for 68EN360 CPU internal
requests and IRQ level 6 for 68EN360 SIM60 internal requests.
Note
The 4 IRQ lines specified by CXC are supplied by the 68EN360 Port C lines and are therefore also
processed as internal requests (PC0, 1, 2, 3).
2.4.2 External Autovector Requests
Some 68EN360 external interrupt sources are routed to the IRQ lines of the 68EN360 and generated as autovectored
interrupts. Care must be taken that the relevant 68EN360 register is initialised with respect to the wiring (see also the
Software Configuration chapter in this manual).
Address:CS7 + $1PEP Default Address $CD 00 00 01
Format:Byte
Access:read / write
Value after HW reset:0
Value after PEP SW initialization: Value of EEPROM
01234567
CS7 + $1
Register Description
NameValueDescription
EN_IRQx1Enable VME IRQx where x = 1 to 7
SYSFAIL1Enable VME SYSFAIL IRQ autovector 3
The MC68EN360 is specified to support a full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel
interface functions. Since the 68EN360 requires an external interface adapter and transceiver function, the Ethernet port
can be adapted to all standard Ethernet functions, such as 10BaseT, 10Base5 and 10Base2 via a piggyback connected to the
SI Interface on the VM62(A) / VM42(A).
2.5.2 Serial Ports
The VM62(A) / VM42(A) provides 6 serial ports based on the 68EN360 communications processor. The ports can be
configured in the following way:
•2 * service / debug ports (SMC port / RxD / TxD only RS232);
•4 * full MODEM ports / multiprotocol channels (SCC ports).
The service / debug ports are configured as default on the VM62(A) / VM42(A). These ports supply RxD/TxD RS232
Interfaces software handshake (XON/XOFF) capability. The full MODEM ports supply RxD, TxD, RTS, CTS, CD,
DTR and RCLK/TCLK. Two of the full MODEM ports can be configured on the SI Interface with a variety of SI
Modules (RS232/RS485, isolated/non-isolated and so on). Together with the two service/debug ports, a maximum of
three (four) completely configured serial ports are available for the base board. Three (two) serial ports may be configured
via the CXC where three of the four full MODEM Interfaces are routed.
The Ethernet port can be configured via the SI Interface with 10BaseT, 10Base5 or 10Base2 SI Modules. The following
configurations are therefore possible for the serial ports.
Versions with Ethernet Port
Port68EN360 ResourceConfigured via
Service/Debug 1SMC1Base board, upper RJ12
Service/Debug 2SMC2Base board, lower RJ12
EthernetSCC1Base board, SI Module
Full MODEM 2SCC2CXC Module
Full MODEM 3SCC3CXC Module
Full MODEM 4SCC4CXC Module
*
The 10BaseX Modules do not make use of SCC4 and, therefore, can be used on the CXC.
Versions without Ethernet Port
Port68EN360 ResourceConfigured via
*
Service/Debug 1SMC1Base board, upper RJ12
Service/Debug 2SMC2Base board, lower RJ12
Full MODEM 1SCC1Base board, SI Module
Full MODEM 2SCC2CXC Module
Full MODEM 3SCC3CXC Module
Full MODEM 4SCC4Base board, SI Module or CXC Module
*
Can only be used once.
*
2.5.3 CXC Interface
The Controller Extension Connector (CXC) is a local mezzanine interface. The CXC contains a 16-bit data bus, 7 address
lines and 8 decoded chip select lines. In total, there are 8 control signals. The base address of the CXC can be programmed
via the CS5 line of the 68EN360. The 8 CXC chip selects (CXC_CS0 - CXC_CS7) occupy 256 Bytes each and have an
address length of 400H (512 Bytes).
Furthermore, the CXC contains 4 IRQ capability (4 edge sensitive IRQs), DMA capability (1 channel, DREQ + DACK),
serial ports (3 channels, Full MODEM) and a set of parallel port signals. These special CXC functions are based on the
68EN360 resources.
For general CXC information, including generic pinouts and a comparison of the 68(EN)360 and 68302 CPU pinouts on
the CXC, please refer to the CXC Specification User’s Manual and the CXC Appendix attached to this manual.
1)On a standard VM62(A)/VM42(A) board, these signals are already used for UART ports at BU7 and BU8.
2)On a standard VM62(A)/VM42(A) board, these signals are used for SPI to which the EEPROM is already
connected. PB0 is chip select of the EEPROM.
3)On PA13, a 24 MHz clock signal is routed via jumper J6. This signal is always needed for PEP standard
software (serial drivers).
Dual Functioning Signal Pins
4)These signals are routed both to the base board SI Interface connector (ST5C) and the CXC connector and can
only be used by one or the other and not both at the same time.
Due to this, a conflict exists if the SCC4 port is to be used with the SI232 piggyback and CXC boards (such as
CXM-SIO3), as both boards access this port. The SCC4 port can, therefore, not be used at the same time by SI
piggybacks and CXC boards.
The CXC ports SER1, SER2 and SER3 are equivalent to ports SCC2, SCC3 and SCC4 resp. on the 68xx360.
With regard to special CXC capabilities, the CXC pinout on the VM62(A) / VM42(A) has been developed to provide
maximum compatibility between the standard CXC functions. In addition, all signals are available in order to configure 2
time division multiplexed channels via the CXC (ISDN, PCM, GCI and so on). Multi-function pins with incompatible
functions with regard to the 68302 and 68EN360 (called user defined in the generic CXC specification) are not part of the
VM42(A) / VM62(A) CXC specification.
Although the SMCs are configured on the base board, these ports are also integrated on the CXC. This is because of
possible ISDN applications where SMCs can be integrated and other protocols supported by the 68EN360.
Note
If the RCLK2 signal (CXM pin c16) is required, jumper J6 (24 MHz clock) must be opened and the
serial drivers delivered by PEP modified.
The RTC (V3021 3-wire serial interface) is a 1-bit device which is accessible over the CS6 of the 68EN360. Its
timekeeping features include :-
• seconds, minutes, hours, day of month, month, year, week day and week number in BCD format.
• leap year and week number correction
• standby supply smaller than 1µA
See also the Software Configuration chapter in this manual and the V3021 data sheet.
2.6.2 EEPROM
The serial EEPROM is a 1-bit device which is accessible over the SPI Interface (3-wire Interchip) of the 68EN360. The
first half of the EEPROM (1 kbit) is reserved for factory data, including Board ID codes, Internet/Ethernet addresses, boot
information etc. The second half of the EEPROM is available for the user. See also the Software Configuration chapter in
this manual.
For more information on the EEPROM, please refer to the XICOR X25C02 data sheet.
2.6.3 TICK Generator
The 68EN360 internal Periodic Interrupt Timer is used by the PEP real-time operating system as TICK generator.
For more information please refer to the 68EN360 User’s Manual.
2.6.4 On-board Bus Error Timer
The VM62(A) / VM62(A) provides an on-board bus error timer. An 8µs timeout timer monitors the cycle lengths of data
transfers to and from locations beyond the bussizer, including on-board I/O, CXC, SRAM, AutoBahn and some VME.
After a timeout occurs, it generates an on-board BERR signal for error termination. This timer is enabled/disabled via the
board control/status register, which also supplies a timeout status bit in order to identify bus errors generated by the onboard bus error timer.
During VMEbus cycles, the on-board bus error timer is reset as soon as the VM62(A) / VM42(A) gains
VMEbus ownership. This means that the time gap between a VMEbus request and the starting of the
VMEbus cycle is monitored by the on-board BERR timer. VMEbus cycles themselves are monitored
by the separate VMEbus BERR timer (BUS monitor).
2.6.5 VME Bus Error Timer
The VM62(A) / VM42(A) also provides a bus monitor for the VMEbus. A 128µs timeout timer monitors VMEbus data
transfer cycle lengths and generates a VMEbus BERR* signal for error termination. This timer is enabled/disabled via the
VME control/status register which also supplies a timeout status bit in order to identify bus errors generated by the bus
monitor.
2.6.6 Watchdog Timer
A 512ms watchdog timer triggers the on-board and VME system reset generator at timeout. Once enabled via the board
control/status register, the watchdog timer cannot be reset by software. It must be re-triggered via the corresponding bit in
the board control/status register periodically within the timeout period. ‘Watchdog timer running’ is a status that is
displayed by the yellow front panel LED.
Figure 2.6.6.1: Watchdog LED Location
Watchdog LED
Yellow
W
2.6.7 First Slot Detection (FSD)
The VM62(A)/VM62(A) detects during power-up whether the CPU in use is positioned in the far left slot of the system.
This is achieved using a 100k pull-down resistor at the BG3IN* pin.
BG3IN* low = system controller (far left slot)
BG3IN* high = no system controller
This information can be read from the VMEbus Control/Status register and is valid until the next power down of the
system.
Push buttonNo
SYSRES* VMENo
WatchdogWDG bit on-board (Board Control/Status Register)
Power monitor (4.65V)Inside the 68EN360
2.7 Front Panel Functions
Figure 2.7.0.1: LED Port and Button Location
Watchdog LED
Yellow
General Purpose
Green
W
UH
RESET SwitchABORT Switch
RST AB
CPU HALT or RESET
Red
2.7.1 RESET Button
A RESET button is fitted to the front panel to avoid false operation. The RESET button triggers the on-board system reset
generator, as well as the VME if jumper J2 is set.
2.7.2 ABORT Button
Together with the RESET button, an ABORT button is also fitted to the front panel. The ABORT button generates a level
7 IRQ (non-maskable interrupt) which is used for debugging purposes. In this case, bit 1 of the Board Control/Status
Register is not set (remains ‘0’).
2.7.3 LED Port
The front panel LED port consists of three LEDs with the following functions:
Red LEDCPU in HALT or RESET status
Yellow LEDWatchdog timer running status
Green LEDGeneral purpose, set via board control/status register
The green LED is free to be used by the customer. It is set by the software during startup when the 68EN360 is initialized.
Short term data retention for RTC and SRAM is gained with two Gold-Caps, each with a value of 0.22 Farad. In contrast
to Lithium cells, Gold-Caps do not require servicing. This short term backup is intended for short power failures or for
reconfiguring systems. An empty Gold-Cap needs approximately three hours to charge up, with backup times dependant on
the temperature, memory size and memory manufacturer tolerances. A well charged Gold-Cap provides a minimum of 10
hours backup time.
Laboratory tests at PEP indicate a typical backup time of 1 week for both 256kB and 1MByte SRAM plus RTC (typical
onboard backup current is 2µA.
Long term data retention is made via the VMEbus 5V Stby line. With respect to the VM62(A) / VM42(A), this voltage
can drop to 2.5V, with the typical current via the 5V Stby being 30µA at 3V.
Note
The VM42(A) / VM62(A) board can be removed from the system and then plugged in again without
losing any information. Data retention switches from the VME 5V Stby to the on-board Gold-Caps
automatically.
The on-board Gold-Caps are continuously reloaded via the 5V Stby line. The 5V Stby current is
typically 7mA for a few minutes when the Gold-Caps are at the beginning of the loading phase (fully
empty).
Address:CS7 + $1PEP Default Address $CD 00 00 01
Format:Byte
Access:read / write
Value after HW reset:0
Value after PEP SW initialization:Value of EEPROM
01234567
CS7 + $1
VMEbus Control / Status Register (page 2-6)
Address:CS7 + $5PEP Default Address $CD 00 00 05
Format:Byte
Access:read / write
Value after HW reset:see table on page 2-6
CS7 + $5
Board Control/Status Register (page 2-14)
Address:CS7 + $7PEP Default Address $CD 00 00 07
Format:Byte
Access:read / write
Value after HW reset:0
The DM600 is a memory piggyback fitted with 4MByte DRAM and either 1 or 4MByte Flash EPROM. Two
configurable jumpers are present on the board, indicating if write protection is enabled or disabled and whether 1MBit or
4MBit Flash EPROM chips are fitted.
The DM601 is a memory piggyback fitted with 16MByte DRAM and either 1 or 4MByte Flash EPROM. Two
configurable jumpers are present on the board, indicating if write protection is enabled or disabled and whether 1MBit or
4MBit Flash EPROM chips are fitted.
The DM603 is a memory piggyback fitted with 32MByte DRAM and 0.5MByte Flash EPROM. A version of the
DM603 with 2MByte Flash EPROM fitted will soon be available. One configurable jumper is located on the board,
indicating whether the Flash EPROMs are write protected.
Many components of the VM62(A) / VM42(A) are controlled by the MC68EN360. Due to this fact, this chip requires a
special initialization sequence before any other software can be started.
The following list describes how the initialization must be performed on the VM62(A) / VM42(A).
WARNING!
The order of the initialization listed below must not be changed, otherwise erratic
behaviour of the board may result.
1)Set DPRBASE to 0x0000000x7000001.L -> MBAR (in CPU space!)
Example
move.l#7,d1select CPU space
move.l#$7000001,d0value to write to MBAR
movecd1,dfcselect CPU space
moves.ld0,MBARset MBAR
2)Clear reset status register0xFF.B -> RSR
3)Set system protection register
• bus monitor enabled, 128 system clocks timeout0x7.B -> SYPCR
4)Set module configuration register
• bus request MC68040 arbitration ID: 3
• arbitration synchronous timing mode
• bus clear out arbitration ID: 3
• SIM60 registers are Supervisor Data
• BusClear in arbitration ID: 3
• interrupt arbitration: 30x60008CB3.L -> MCR
5)Set PLL enabled and lock access0xC000.W -> PLLCR
6)Lock access to clock divider control register0x8000.W -> CDVCR
12) The system software normally determines the real sizes of the DRAM and SRAM installed and re-programs the CS
lines accordingly. The simplest way to achieve this is to write a pattern to the first location and then search for that
pattern at meaningful distances (e.g. 256kB, 512 kB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB). If the pattern is found at
such an address, the original pattern must be altered and then checked to see if the mirrored pattern changes in the
same way. If not, the search must be contined or, if yes, the memory size is found.
Note
The MC68040 normally operates in non-serialised mode, meaning that read accesses can occur before
write accesses, even if they are programmed in the opposite way. It is therefore recommended that
especially when changing the patterns, a ‘nop’ instruction should be inserted, as this forces all pending
cycles to be completed.
13) Set vector and IRQ level for internal IRQ requester
• vector base = 0x40
• level = 40x8040.L -> CICR
14) Set SDMA configuration register0x770.W -> SDCR
15) If the card is in the first slot, enable the VMEbus monitor
If bit 4 in VCSR is set then set bit 5 in VCSR
16) Enable on-board I/O bus error timerSet bit 2 in BCSR
Before the system enables any cache present, they should be invalidated using:
cinva bc
Furthermore, the complete address range should not be cachable, as caching only makes sense on DRAM and FLASH
EPROM. Other areas should never be cached and must be switched to serialised in order to prevent the
MC68040/MC68060 from mixing up read and write cycles.
The easiest way of doing this is to make use of the DTT0 register, in the following way:
move.l#$807FE040,d1
movecd1,dtt0
The code above sets all addresses below $80000000 to cacheable and non-serialised, whereas all addresses above are set to
non-cacheable and serialised.
Accesses to the DRAM and FLASH should be made at $0 and $4000000. All other components addressed by the
MC68EN360 should always be accessed over the mirrored area with $Cxxxxxxx, as described in Section 2.2.5 AddressMap.