Kontron VM62 User Manual

VM62(A) / VM42(A) User’s Manual Preface

VM62(A) / VM42(A)

Intelligent Universal Controller Modules

for Stand-Alone and VMEbus

Manual Order No. 3368

User’s Manual

Issue 3

Unpacking and Special Handling Instructions

This PepCard product is carefully designed for a long and fault-free life; nonetheless, its life expectancy can be drastically reduced by improper treatment during unpacking and installation.

Observe standard anti-static precautions when changing piggybacks, ROM devices, jumper settings, etc. If the product contains batteries for RTC or memory back-up, ensure that the board is not placed on conductive surfaces, including antistatic plastics or sponges. These can cause shorts and damage to the batteries or tracks on the board.

When installing the board, switch off the power mains to the chassis. Do not disconnect the mains as the ground connection prevents the chassis from static voltages, which can damage the board as it is inserted.

Furthermore, do not exceed the specified operational temperature ranges of the board version ordered. If batteries are present, their temperature restrictions must be taken into account.

Keep all of the original packaging material for future storage or warranty shipments. If it is necessary to store or ship the board, re-pack it as it was originally packed.

Preface VM62(A) / VM42(A) User’s Manual

R EVISION HISTORY

VM62(A) / VM42(A) User’s Manual

Issue Brief Description of Changes PCB Index Date of Issue

1 Issue 1 01-01/2 March, 1995 2 General Corrections throughout Manual 01-01/4 June, 1995

2.0.1 Correction of Figure 3.2.0.1 (Jumper Layout Solder Side) 01-01/4 July, 1995 3 Updated for board index 02 02 December, 1995

This document contains proprietary information of PEP Modular Computers. It may not be copied or transmitted by any means, passed to others, or stored in any retrieval system or media, without the prior consent of PEP Modular Computers or its authorized agents.

The information in this document is, to the best of our knowledge, entirely correct. However, PEP Modular Computers cannot accept liability for any inaccuracies, or the consequences thereof, nor for any liability arising from the use or application of any circuit, product, or example shown in this document.

PEP Modular Computers reserve the right to change, modify, or improve this document or the product described herein, as seen fit by PEP Modular Computers without further notice.

VM62(A) / VM42(A) User’s Manual Preface

PEP Modular Computers® Two Year Limited Warranty

We grant the original purchaser of PEP products the following hardware and system warranty. No other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the consumer has the express written consent of

PEP Modular Computers.

PEP Modular Computers warrants their own products (excluding software) to be free from defects in workmanship

and materials for a period of 24 consecutive months from the date of purchase. This warranty is not transferable nor extendible to cover any other consumers or long term storage of the product.

This warranty does not cover products which have been modified, altered, or repaired by any other party than PEP Modular Computers or their authorized agents. Furthermore, any product which has been, or is suspected of being damaged as a result of negligence, misuse, incorrect handling, servicing or maintenance; or has been damaged as a result of excessive current/voltage or temperature; or has had its serial number(s), any other markings, or parts thereof altered, defaced, or removed will also be excluded from this warranty.

A customer who has not excluded his eligibility for this warranty may, in the event of any claim, return the product at the earliest possible convenience, together with a copy of the original proof of purchase, a full description of the application it is used on, and a description of the defect; to the original place of purchase. Pack the product in such a way as to ensure safe transportation (we recommend the original packing materials), whereby PEP undertakes to repair or replace any part, assembly or sub-assembly at our discretion; or, to refund the original cost of purchase, if appropriate.

In the event of repair, refund, or replacement of any part, the ownership of the removed or replaced parts reverts to PEP Modular Computers, and the remaining part of the original guarantee, or any new guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired items. Any extensions to the original guarantee are considered gestures of goodwill, and will be defined in the "Repair Report" returned from PEP with the repaired or replaced item.

Other than the repair, replacement, or refund specified above, PEP Modular Computers will not accept any liability for any further claims which result directly or indirectly from any warranty claim. We specifically exclude any claim for damage to any system or process in which the product was employed, or any loss incurred as a result of the product not functioning at any given time. The extent of PEP Modular Computers liability to the customer shall not be greater than the original purchase price of the item for which any claim exists.

PEP Modular Computers makes no warranty or representation, either express or implied, with respect to its products, reliability, fitness, quality, marketability or ability to fulfill any particular application or purpose. As a result, the products are sold "as is," and the responsibility to ensure their suitability for any given task remains the purchaser's.

In no event will PEP be liable for direct, indirect, or consequential damages resulting from the use of our hardware or software products, or documentation; even if we were advised of the possibility of such claims prior to the purchase of, or during any period since the purchase of the product.

Please remember that no PEP Modular Computers employee, dealer, or agent are authorized to make any modification or addition to the above terms, either verbally or in any other form written or electronically transmitted, without consent.

Preface VM62(A) / VM42(A) User’s Manual

TABLE OF CONTENTS

Page

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 1.2.0.1: VM62(A)/VM42(A) Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1.4.0.1: CPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 1.4.0.2: MC68EN360 Intelligent Controller Schematic . . . . . . . . . . . . . . . . . . . . . . . 7

1.5 Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Figure 2.0.0.1: VM62(A) / VM42(A) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 The 68EN360 (QUICC) on the VM62(A) / VM42(A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2.1 Basic Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2.2 Boot Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2.3 Primary Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2.4 Secondary Address Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2.5 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2.2.5.1: VM62(A) / VM42(A) Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2.6 DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3.1 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3.2 Dual-Ported SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3.3 Mailbox Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3.4 VMEbus Control / Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4.1 Internal Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4.2 External Autovector Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4.3 VME Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5.1 Ethernet Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5.2 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2.5.2.1: MC68EN360 Intelligent Controller Schematic . . . . . . . . . . . . . . . . . . . . . . . 9

2.5.3 CXC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2.5.3.1: CXC Pinouts using the 68(EN)360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2.5.3.2: Further Explanation of 68(EN)360 Mnemonics . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.4 AutoBahn Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.1 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.3 TICK Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.4 On-board Bus Error Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.5 VME Bus Error Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

2.6.6 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2.6.6.1: Watchdog LED Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.7 First Slot Detection (FSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.8 Board Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6.9 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

VM62(A) / VM42(A) User’s Manual Preface

2.7 Front Panel Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 2.7.0.1: LED Port and Button Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7.1 RESET Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7.2 ABORT Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7.3 LED Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.8 Data Retention for RTC and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.9 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3. Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Table 3.0.0.1: VM62(A) / VM42(A) Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3.1 Jumper Description (Component Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 3.1.0.1: VM62(A) / VM42(A) Jumper Layout (Component Side) . . . . . . . . . . . . . . . . 2

3.1.1 Jumper J1: VME-SYSCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1.2 Jumper J2: VME-SYSRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1.3 Jumper J8: VME Boot (VBOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1.4 Jumper J9: AutoBahn Boot (ABOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1.5 Jumper J14: Connection of Protective and Signal GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.2 Jumper Description (Solder Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3.2.0.1: VM62(A) / VM42(A) Jumper Layout (Solder Side) . . . . . . . . . . . . . . . . . . . . 4

3.2.1 Jumpers J3, J4 and J5: CPU (Bus) Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2.2 Jumper J6: 24 MHz Clock (Communications Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2.3 Jumper J7: CPU Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2.4 Jumper J10: Serial EEPROM Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2.5 Jumpers J11 and J12: SRAM Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2.6 Jumpers J131 - J134: Processor Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4. Memory Piggybacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 DM600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4.1.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 4.1.1.1: DM600 Jumper Layout (Component Side) . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4.2 DM601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4.2.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 4.2.1.1: DM601 Jumper Layout (Component Side) . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4.3 DM602 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4.4 DM603 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4.4.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 4.4.1.1: DM603 Jumper Layout (Component Side) . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Preface VM62(A) / VM42(A) User’s Manual

5. Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 Main Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 5.1.0.1: Main Board Connector Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

5.1.1 VMEbus Connector (ST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.1.2 CXC Connector (ST3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2.1 Standard RS232 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 5.2.1.1: Standard Front Panel Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2.2 Ethernet 10Base2 (SI-10B2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5.2.2.1: SI-10B2 Front Panel Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2.3 Ethernet AUI / 10Base5 (SI-10B5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5.2.3.1: SI-10B5 Front Panel Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5.2.4 Serial RS232 Interface (SI-PB232) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5.2.4.1: SI-PB232 Front Panel Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.2.5 Ethernet 10BaseT (SI-10BT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5.2.5.1: SI-10BT Front Panel Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.2.6 PROFIBUS Interface (SI-PBPRO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5.2.6.1: SI-PBPRO Front Panel Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6. Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1 Initializing the 68EN360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

6.2 Initialising the Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Appendix Controller eXtension Connector

Appendix OS-9 Cabling

VM62(A) / VM42(A) User’s Manual Chapter 1 Introduction

1. INTRODUCTION

1.1 Product Overview

The computer user today requires high performance to meet high expectations. At the same time, the mass of data that has to be processed is dramatically increasing, for instance the data that a modern graphic user interface generates. Additionally, there is a further demand on the communications ability and multi-functionality of the computer.

The VM62(A)/VM42(A) meets all the above requirements, combining high computational performance with excellent communication ability via the AutoBahn™ Spanceiver™ chip.

A combination of the high performance CPU (Motorola MC68060 or 68040) and the Quad Integrated Communications Controller chip, the Motorola MC68EN360 or QUICC, not only enables a pure computation performance from approximately 35 MIPS to over 100 MIPS, but dispenses with the usual restrictions associated with communications over serial interfaces. Communication tasks are dealt with by the QUICC chip, freeing the CPU from such timeconsuming chores. Fieldbus protocol, such as PROFIBUS, are also handled by the QUICC. In addition, the QUICC, used together with PEP’s expanding CXC interface is ideally suited for communication tasks extending from 6 serial interfaces over LAN to WAN (X.25, ISDN) applications. The ‘EN’ version of the QUICC also supports Ethernet on 2 channels (only one usable on the VM42(A)/VM62(A) using PEP standard software).

The various I/O interfaces are realised using piggybacks attached to the main board. Five options are at the moment available. They are:

• Ethernet 10Base 2;

• Ethernet 10Base 5 (AUI);

• Ethernet 10BaseT;

• 2 * RS232 serial interfaces;

• PROFIBUS interface (RS485, isolated, half duplex, 2 wires).

PEP’s AutoBahn technology has solved one of the major problems that exist in information technology - data transfer over the various bus systems. Normally the data transfer rate over a bus system is below the data transfer capability of a modern CPU chip. The AutoBahn chip (the Spanceiver MC100SX1451) allows transfer rates of up to 100 Mbyte/sec over the VMEbus using the VMEbus lines SERA and SERB.

PEP has also developed a cost-effective VMEbus backplane series that support AutoBahn, called VBP4A, in 7, 12 and 15 slot options. These backplanes allow direct connection of the main power supply, hence reducing cabling costs dramatically.

A CXM-SIO3 module is available in order to make all three serial interfaces that are available on the CXC accessible on the VM62(A)/VM42(A). This is achieved by using RS232, SC-xxx or SI-xxx interfaces. For more details, please refer to

the CXM-SIO3 user’s manual.

AutoBahn ™ and Spanceiver ™ are trademarks of PEP Modular Computers.

Chapter 1 Introduction VM62(A) / VM42(A) User’s Manual

1.2 Ordering Information

Name Description Order No

VM62-BASE VMEbus single board computer comprising MC68060 @ 50 MHz,

MC68EN360 @ 25 MHz, 256 kByte dual-ported SRAM (with Gold Cap for backup), configured for use with the AutoBahn interface piggyback, up to 6 serial interfaces (2 available on the front panel as RS232 and an additional 4

divided between the CXC interface and SI-Interface), CXC Interface, PEPbug. VM62-BASE Same as order no. 12349 but with 1 MByte dual-ported SRAM 12350 VM42-BASE VMEbus single board computer comprising MC68040 @ 33 MHz,

MC68EN360 @ 33 MHz, 256 kByte dual-ported SRAM (with Gold Cap for

backup), configured for use with the AutoBahn interface piggyback, 6 serial

interfaces (2 available on the front panel as RS232 and an additional 4 divided

between the CXC interface and SI-Interface), CXC Interface, PEPbug. VM42-BASE Same as order no. 12344 but with 1 MByte dual-ported SRAM 12345 VM42-BASE Same as order no. 12344 but with MC68040V @ 33 MHz (3.3-V technology) 12346 VM42-BASE Same as order no. 12346 but with 1 MByte dual-ported SRAM 12347

DM600 Memory piggyback with 4 MByte DRAM and 1 MByte Flash EPROM 11852 DM600 Memory piggyback with 4 MByte DRAM and 4 MByte Flash EPROM 11853 DM601 Memory piggyback with 16 MByte DRAM and 1 MByte Flash EPROM 11854 DM601 Memory piggyback with 16 MByte DRAM and 4 MByte Flash EPROM 11855

DM602 Memory piggyback with 1 MByte DRAM and 1 MByte Flash EPROM 12765

12349

12344

DM603 Memory piggyback with 32 MByte DRAM and 512 kByte Flash EPROM 13027 DM603 Memory piggyback with 32 MByte DRAM and 2 MByte Flash EPROM 13627 SI-10B2 10Base2 (Thin) Ethernet (cheapernet) interface with RG58 (coax) connector 9925

SI-10B5 10Base5 (AUI) Ethernet interface piggyback with 15-pin D-Sub connector 9924 SI-10BT 10BaseT (Twisted pair) Ethernet interface piggyback with RJ45 connector 9926 SI-DUMMY Front panel only fitted when no SI piggyback required 12351 SI-PB232 Serial interface piggyback for 2 RS232 connections (Modem interface) with 2

RJ45 connectors SI-PB232-ISO Serial interface piggyback for 1 RS232 optoisolated connection with 1 RJ45

connector (Available in 1996 if requested) SI-PBPRO RS485 optoisolated interface piggyback for 2 wire half-duplex (PROFIBUS)

connection with 9-pin D-Sub connector MP-AB100 AutoBahn interface piggyback complete with all control logic, 128 kByte 32-

bit fast SRAM as buffer for AutoBahn data transfer with Spanceiver MC

100SX1451 of 50/100 MByte/s CABLE-VM42-

232

3 meter RS232 Serial Interface cable for VM42(A) / VM62(A) with 9-pin

female D-Sub (PC pinout) to RJ12 connector

11850

11851

9927

9923

12383

VM62(A) / VM42(A) User’s Manual Chapter 1 Introduction

Name Description Order No

CXM-SIO3-1 CXM module with 3 RJ45 connected RS232 ports for use with a CXC

backplane CXM-SIO3-1 CXM module with 3 RJ45 connected RS232 ports, compatible for direct

connection to a CPU board CXM-SIO3-2 CXM module with 2 RJ45 connected SC piggyback ports and one SI

piggyback interface, no front panel (delivered with SC piggyback) for use with

a CXC backplane CXM-SIO3-2 CXM module with 2 RJ45 connected SC piggyback ports and one SI

piggyback interface, no front panel (delivered with SC piggyback), compatible

for direct connection to a CPU board CXM-SIO3-3 CXM module with 3 RJ45 connected SC piggyback ports for use with a CXC

backplane CXM-SIO3-3 CXM module with 3 RJ45 connected SC piggyback ports, compatible for direct

connection to a CPU board CXM-SIO3-4 CXM module with 3 15-pin D-Sub connected SC piggyback ports, 8TE front

panel for use with a CXC backplane CXM-SIO3-4 CXM module with 3 15-pin D-Sub connected SC piggyback ports, 8TE front

panel, compatible for direct connection to a CPU board

TBD

13692

TBD

13693

TBD

13694

TBD

13695

Each VM62(A)/VM42(A) comes complete with 2 RS232 serial interfaces situated on the lower half of the front panelThese interfaces are provided with TxD and RxD signals by the SMC1 and SMC2 channels of the ‘QUICC’ controller. The SCC1 channel of the ‘QUICC’ provides the interface to one of the available SI-xxx piggybacks. All other channels (SCC2, SCC3 and SCC4) of the ‘QUICC’ are ported to the CXC interface except for the SI-PB232 piggyback which has on-board additional control provided by the SCC4 channel through the SI Interface.

As mentioned above, a CXM-SIO3 module is available in order to make all the serial interfaces accessible on the VM62(A)/VM42(A). For more details, please refer to the CXM-SIO3 user’s manual.

Important: The VM62(A)/VM42(A) must be ordered with a memory module (DM60x) and a front

panel interface piggyback module (SI-xxx).

Chapter 1 Introduction VM62(A) / VM42(A) User’s Manual

Figure 1.2.0.1: VM62(A)/VM42(A) Configuration Options

SRAM

VM42(A)

MC68040

@ 33 MHz

MC68EN360

@ 33 MHz

VM42(A)

MC68040V

@ 33 MHz

MC68EN360

@ 33 MHz

256 kByte

SRAM

1 MByte

SRAM

256 kByte

SRAM

1 MByte

68EN360

* Ethernet * 6 serial I/O * Timers * Watchdog

Companion Mode

VM62(A)

MC68060

@ 50 / 66MHz

VM42(A)

MC68040(V)

MC68040

@ 33 MHz

RTC

dual-ported

SRAM

DRAM

FLASH

1 kbit EEPROM

interface

(optional)

Spanciever

CXC Interface

Dual-ported

SRAM

128 kByte

VMEbus * System controller * Master/slave interface

VMEbus

Optional MP

Interface Piggyback

VM62(A)

MC68060

@ 50/66 MHz

MC68EN360

@ 25 /33MHz

CPU Options

SRAM

256 kByte

SRAM

1 MByte

Optional Memory Piggyback

with

1 MByte DRAM

1 MByte FLASH

Optional Memory Piggyback

with

16 MByte DRAM

1 or 4 MByte FLASH

Memory Piggybacks

Optional Memory Piggyback

with

4 MByte DRAM

1 or 4 MByte FLASH

Optional Memory Piggyback

with

32 MByte DRAM

512 kByte or 2 MByte FLASH

VM62(A) / VM42(A) User’s Manual Chapter 1 Introduction

1.3 Specifications

Main CPU

I/O Controller

Memory

DRAM FLASH SRAM EEPROM

VMEbus Interface

A24:D16/D8 Arbitration AM Codes

MC68060 66 or 50 MHz (3.3V) MC68040 33 or 25 MHz MC68040V 33 or 25 MHz (3.3V) MC68LC040 33 or 25 MHz

MC68EN360, 25 or 33MHz used in companion mode

1, 4, 16 or 32 Mbyte

0.5, 1, 2, or 4 MByte 1 MByte or 256 kByte (dual-ported, backed-up using Gold-Caps) 2 kbit (serial); 1 kbit available for applications

Master and slave with optional AutoBahn Interface (100 MBytes/sec) Single level (BR3*), release-when-done daisy-chain Standard Superv./User Prog./Data HEX 39/3A/3D/3E User Defined HEX 10-17/18-1F Short I/O HEX 29/2D System controller functions

• Automatic First Slot Detection (FSD)

• SYSRES* (disabled by jumper)

• SYSCLK* (disabled by jumper)

• ACFAIL*

• SYSFAIL*

• Power monitor

• Bus monitor (programmable)

• VME IRQ mask register

A24:D16 Dual-port SRAM 1 Mailbox IRQ

Interrupt Control

7 Level VME IRQ Handler, maskable via VME IRQ mask register System vectors

* Available for Index 02 boards or later.

Slave 1 Mbyte window, software programmable base (1 out of 16 addresses) Lower 8kBytes of the SRAM area

ACFAIL* -> Level 7 autovectored ABORT -> Level 7 autovectored TICK -> Level 6 autovectored SYSFAIL* -> Level 3 autovectored (maskable) Mailbox IRQ -> Level 5 autovectored AutoBahn IRQ 2 -> Level 2 autovectored AutoBahn IRQ 1 -> Level 1 autovectored 16 on-board Interrupters, Levels / Vectors programmable

Chapter 1 Introduction VM62(A) / VM42(A) User’s Manual

I/O Ports

Serial

Mezzanine Interface

Timers

RISC controller (in the 68EN360) with 14 dedicated DMA channels 4*multiprotocol SCCs up to 8 MBaud with one (two) supporting IEEE 802.3/Ethernet up to 10 Mbit/s

10Base5, 10Base2 or 10BaseT 2*UARTs RS232 (XON/XOFF) RS232 up to 120 kBaud 4 independent baud rate generators CXC Interface

- 16 bit asyncronous data transfer with 4 IRQs,

independent DMA channel

- 3 serial interfaces

TICK General Purpose Watchdog

Special Functions

Real-time clock (backed-up)

Serial EEPROM

DMA

Front Panel Functions

Data Retention

Short term backup for RTC and SRAM via on-board Gold-Cap

Periodic Interrupt Timer, programmable 4*16 bit or 2*32 bit, programmable 512 ms time-out for reset, programmable

Date (year, month, week, day) Time (hour, minute, second)

1 kbit for board specific data (serial number, Internet address, etc.) + 1 kbit for application purposes

2 independent channels (supports single and dual address transfers between all offboard locations including DRAM, FLASH, AutoBahn memory, CXC and VME)

RESET button ABORT button HALT LED (red) Watchdog LED (yellow) General purpose LED (green)

Typ. 2µA/3V -> 50 hours

Long term backup via VME 5V Stby line

Power Requirements

VM62 /66 MHz VM62 /50 MHz VM42 /33 MHz (68040) VM42 /25 MHz 3.3V (68040V)

Temperature Range

Operating Humidity

Board Size

VMEbus Connector

Front panel width

Dependent on the battery installed on the system 5V Stby. Automatic switching between 5V Stby and internal Gold-Cap Typ. 30µA/3V

To be defined

5 W with DM600 and SITB5 fitted 7W with DM600 and SITB5 fitted 4 W with DM600 and SITB5 fitted

Standard 0 - 70˚C Optionally E2 -40˚C to +85˚C

0 to 95% non-condensing

Single height Eurocard 100*160 mm

DIN 41612 style C, 96 contacts, P1 connector

4 TE, 1 slot

VM62(A) / VM42(A) User’s Manual Chapter 1 Introduction

1.4 Features

CPU Options

The Table below illustrates the capabilities of the available CPUs. The 68060 processors operating at 50 MHz deliver up to 100 MIPs while the 68040 processors operating at 33 MHz give performances up to 35 MIPs.

Table 1.4.0.1: CPU Configuration

Processor Product CPU MMU FPU Supply

MC68040 VM42(A) √ √ √ 5V MC68LC040 MC68040V VM42(A) √ √ 3.3V MC68060 VM62(A) √ √ √ 3.3V

VM42(A) √ √ 5V

MC68EC060 planned project

68EN360

25/33 MHz - the ‘QUICC’ chip used in ‘companion mode’ is tightly coupled to the CPU. Working as an I/O and system controller, it provides all the necessary interfaces, timers and clocks etc. in addition to the DRAM memory controller.

Serial Channels

Six are provided by the ‘QUICC’ - Two SMC channels are ported to the front panel and the remaining four SCC channels may be optionally configured as shown below.

Figure 1.4.0.2: MC68EN360 Intelligent Controller Schematic

Mask E71M required.

MC68EN360

VM62(A)

SCC2 SCC3 SCC4

SCC1

}

√

SI-Interface

3.3V

CXC Interface

SI-Piggyback

Interface

}

SMC2SMC1

2x RS232 with

Rx and Tx only

Memory

Piggyback

Chapter 1 Introduction VM62(A) / VM42(A) User’s Manual

Ethernet Interface (SI-10B2, SI-10B5, SI-10BT)

Three different piggybacks complete with all the associated control logic are available providing 10Base5, 10Base2 or 10BaseT interfaces.

Note

The SI-10B5 piggyback requires an external +12V power source to operate.

Fieldbus Interface (SI-PBPRO)

This is a fully optoisolated RS485 (PROFIBUS) interface piggyback with a 9-pin D-Sub connector.

RS232 Serial Interface

Two piggybacks are available with RJ45 connectors for MODEM compatible communication.

AutoBahn Interface (MP-AB100)

This is realised via a piggyback containing all the necessary control logic, 128 kByte high speed SRAM (10 ns) as a memory buffer between the processor and the AutoBahn chip (MC 100SX1451) for communication on the high speed serial data lines over pins b21 and b22 of the VMEbus.

DMA Channels

2 independent channels are provided by the ‘QUICC’ chip and can be used by applications requiring data transfer between CXC-modules, DRAM, FLASH memory, dual-ported SRAM and AutoBahn memory buffers. This memory can be configured with different memory options allowing tremendous flexibility when customising memory requirements for real-time applications.

DRAM/FLASH

This memory, complete with a 32 bit data wide access bus is placed on a piggyback with addressing capability for up to two memory banks of 64 MByte each. On-board +5V FLASH memory provides the latest ROM technology allowing the user to take advantage of the on-board programming facility to produce low cost upgrades by simply overwriting existing stored data.

SRAM

This is a dual-ported battery-backed (Gold-Cap) memory area with a 16 bit data wide access bus. Users of the VMEbus and the on-board CPU both have access to this memory. The lower 8 kByte are reserved for the location monitor.

EEPROM

Although a 2 kbit EEPROM is provided on-board, 1 kbit has been pre-programmed with PEP production data (boot info, Ethernet registration, etc) leaving the remaining 1 kbit for user application code. A write protect jumper prevents accidental erasure.

VM62(A) / VM42(A) User’s Manual Chapter 1 Introduction

1.5 Related Publications

VITA

VMEbus Specifications Revision C1 MPI: Modpack and CXC Specification from PEP (Version 1.5 or later)

Motorola

M68060 Microprocessors User’s Manual M68040 Microprocessors User’s Manual MC68EN360 Quad Integrated Communications Controller User’s Manual AutoBahn Spanceiver Data Sheet

EM Microelectronic

V3021 1 Bit Real Time Clock Data Sheet

XICOR

X25C02 SPI Serial EEPROM Data Sheet

VM62(A) / VM42(A) User’s Manual Chapter 2 Functional Description

2. FUNCTIONAL DESCRIPTION

Figure 2.0.0.1: VM62(A) / VM42(A) Block Diagram

CPU 68(LC)040 68040V 33 / (40) MHz 68060 50 / 66 / (80) MHz

3.3V

Serial EEPROM

Real-Time Clock

Address/ Data/ Control

BUSSIZER

SPI

1 Bit

32 Bit 32 Bit

DRAM

1/4/16/32 MB

IRQ Handler

CXC (Serial / Parallel / DMA Port)

16 Bit

FLASH

0.5/1/2/4 MB

Clock Logic

Status/ Control Logic

8 Bit

68EN360 Companion Mode 25/33/(40) MHz

Reset Logic

Watchdog

optional

On board Gold-Cap

VME 5V Stdby

b21 b22

Backup Logic

Dual-Port SRAM

256/1MB 70ns

optional

AutoBahn Interface

autoswitchover

16 Bit

32 Bit

VMEbus Interface Master / Slave

Serial I/O User Spec

SCC2

Serial I/O RS232

SMC1

16 Bit

Serial I/O User Spec

SCC3

Serial I/O RS232

SMC2

Standard I/O Additional I/O

Serial I/O User Spec

SCC4

Front Panel

10Base2/5/T RS485 RS232 ISo 2*RS232

SCC1 SCC4

SCSI (DMA)

LED Functions

Chapter 2 Functional Description VM62(A) / VM42(A) User’s Manual

2.1 The 68EN360 (QUICC) on the VM62(A) / VM42(A)

Motorola’s MC68EN360 is a 32 bit high performance communication controller, combining powerful peripheral functions with system integration functions and an on-chip microprocessor core (CPU32+).

On the VM62(A) / VM42(A), the on-chip CPU core is disabled and replaced with a more powerful external CPU, the MC68040 or MC68060. The 68EN360 operates as a slave to the CPU in so-called ‘Companion Mode’. In this mode, the 68EN360 provides complete I/O functionality. The DMA channels can still obtain ownership of the CPU’s system bus and therefore all on-chip DMA channels can address the whole of the address space. Moreover, important functions for system integration, such as memory controller, clock generation, interrupt controller etc. are available in this mode, meeting the requirements for the initialisation of the 68EN360, described later in this manual.

The programming of the 68EN360 begins by determining the block of on-chip RAM and registers via the MBAR register. This register is located at a fixed address and can only be accessed in CPU space.

2.2 Address Decoder

2.2.1 Basic Structure

The address decoder of the VM62(A) / VM42(A) consists of two basic parts. A primary address decoder pre-decodes the select signals for the processor data bus (in front of the bussizer) and for the I/O data bus (behind the bussizer). With reference to initial boot cycles, the primary address decoder passes or enables a secondary address decoder stage. The secondary address decoder stage is realised using the programmable chip slect logic of the MC68EN360. The 8 outputs of the 68EN360 chip select logic are used for the base addresses of the various memory and I/O address ranges.

2.2.2 Boot Decoding

Due to the fact that the default boot memory used by the VM62(A) / VM42(A) is FLASH memory, which is completely reprogrammable, a special boot decoder is provided. The boot memory is jumper selectable, the user having the choice between FLASH (default), VMEbus memory or the on-board AutoBahn Interface. The boot decoder redirects the physical address range 0H to 1000000H from either FLASH (DM60x), VMEbus or MP piggyback, providing the selected boot memory is initially accessed.

Note

VMEbus boot memory must be located at VME base address 0H in Standard Supervisor Program/Data address space.

VM62(A) / VM42(A) User’s Manual Chapter 2 Functional Description

2.2.3 Primary Address Decoder

The primary address decoder generates the following select signals.

CS_360 Secondary address decoder (68EN360, DRAM, FLASH) CS_VME VMEbus address range CS_AUT AutoBahn Interface address range CS_BSS Bussizer address range (VME, SRAM, AutoBahn, I/O) BERR_0 Reserved address range (Bus Error) EN_BSS 68EN360 DMA address range IACK Interrupt Acknowledge Cycle

2.2.4 Secondary Address Decoder

The secondary address decoder is built by the 68EN360 chip select logic and is therefore programmable. The outputs are used as base address selects, as shown below.

68EN360 Chip Select Connected to

CS0 FLASH CS1 DRAM CS2 VME via 68EN360 DMA CS3 AutoBahn Interface CS4 SRAM CS5 CXC CS6 RTC CS7 Control / Status Registers

Chapter 2 Functional Description VM62(A) / VM42(A) User’s Manual

2.2.5 Address Map

The VM62(A) / VM42(A) address map shown in the Table below is based on the recommended default initialisation of the 68EN360 chip select logic.

Figure 2.2.5.1: VM62(A) / VM42(A) Address Map (PEP Default)

Address (Hex) Device

00 xx xx xx 04 xx xx xx 07 00 0x xx 09 xx xx xx 0A xx xx xx 0B xx xx xx 0C xx xx xx 0D xx xx xx 1x xx xx xx 2x xx xx xx 3x xx xx xx 4x xx xx xx 5x xx xx xx 6x xx xx xx

82 xx xx xx 83 xx xx xx 85 00 xx xx 87 xx xx xx 87 xx xx xx 9x xx xx xx Ax xx xx xx Bx xx xx xx C0 xx xx xx C4 xx xx xx C7 xx xx xx CA xx xx xx CB F7 0x xx CC xx xx xx CD 00 00 01 CD 00 00 05 CD 00 00 07 Dx xx xx xx Ex xx xx xx Fx xx xx xx

DRAM (68EN360’s CS1) FLASH (68EN360’s CS0)

Reserved, 68EN360 internal RAM / register

DMA AutoBahn (CS3)

Reserved, mirrored 68EN360’s CS4 Reserved, mirrored 68EN360’s CS5 Reserved, mirrored 68EN360’s CS6 Reserved, mirrored 68EN360’s CS7 Reserved (BERR_0) Reserved (BERR_0) Reserved (BERR_0)

MP interface (CS_AUT)

Reserved (BERR_0) Reserved (BERR_0)

The following address area is non-cachable serialised.

VMEbus (CS_VME), user-defined AM code VMEbus (CS_VME), user-defined AM code VMEbus (CS_VME), short I/O AM code VMEbus (CS_VME), user-defined AM code DMA-VME, 68EN360’s CS2

Reserved (BERR_0) Reserved (BERR_0) Reserved (BERR_0) Reserved, mirrored DRAM Reserved, mirrored FLASH

Reserved, 68EN360 internal RAM / register 68EN360’s CS4, SRAM 68EN360’s CS5, CXC 68EN360’s CS6, RTC 68EN360’s CS7+1, VME IRQ MASK register 68EN360’s CS7+5, VME control / status register 68EN360’s CS7+7, board control / status register

Reserved (BERR_0) Reserved (BERR_0) Reserved (BERR_0)

Note

In order to determine the base of the 68EN360’s internal memory map, the module base address register (MBAR) must be set. The location of this register is fixed in the address area Supervisor CPU Space at 3FF00H. For more information, please refer to the Software Configuration chapter in this manual.

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