This document provides information about products from Kontron AG and/or its subsidiaries. No warranty of
suitability, purpose, or fitness is implied. While every attempt has been made to ensure that the information in this
document is accurate, the information contained within is supplied "as-is" and is subject to change without notice.
For the circuits, descriptions and tables indicated, Kontron assumes no responsibility as far as patents or other rights
of third parties are concerned.
All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval
system, or translated into any language or computer language, in any form or by any means (electronic, mechanical,
photocopying, recording, or otherwise), without the express written permission of Kontron AG.
DIMM-PC®, PISA®, ETX®, ETXexpress®, microETXexpress™, X-board®, DIMM-IO® and DIMM-BUS® are trademarks or
registered trademarks of Kontron AG. Kontron is trademark or registered trademark of Kontron AG.
1.3 Trademarks
The following lists the trademarks of components used in this product.
» IBM, XT, AT, PS/2 and Personal System/2 are trademarks of International Business Machines Corp.
» Microsoft is a registered trademark of Microsoft Corp.
» Intel is a registered trademark of Intel Corp.
» All other products and trademarks mentioned in this manual are trademarks of their respective owners.
1.4 Standards
Kontron AG is certified to ISO 9000 standards.
1.5 Warranty
This Kontron AG product is warranted against defects in material and workmanship for the warranty period from the
date of shipment. During the warranty period, Kontron AG will, at its discretion, decide to repair or replace defective
products.
Within the warranty period, the repair of products is free of charge as long as warranty conditions are observed.
The warranty does not apply to defects resulting from improper or inadequate maintenance or handling by the buyer,
unauthorized modification or misuse, operation outside of the product’s environmental specifications or improper
installation or maintenance.
Kontron AG will not be responsible for any defects or damages to other products not supplied by Kontron AG that are
caused by a faulty Kontron AG product.
www.kontron.com 6
MSM800BEV/ User Information
1.6 Technical Support
Technicians and engineers from Kontron AG and/or its subsidiaries are available for technical support. We are
committed to making our products easy to use and will help you use our products in your systems.
Please consult our Web site at http://www.kontron.com/support for the latest product documentation, utilities,
drivers and support contacts. Consult our customer section http://emdcustomersection.kontron.com for the latest
BIOS downloads, Product Change Notifications and additional tools and software. In any case, you can always contact
your product supplier for technical support.
1.7 Environmental Protection Statement
This product has been manufactured to satisfy environmental protection requirements wherever possible. Many of the
components used (structural parts, printed circuit boards, connectors, batteries, etc.) are capable of being recycled.
Final disposal of this product after its service life must be accomplished in accordance with applicable country, state,
or local laws or regulations. All components within this product fulfill the requirements of the RoHS (Restriction of
Hazardous Substances Directive). The product is soldered with a lead free process.
1.8 RoHS Commitment
Kontron Compact Computers AG (Switzerland) is committed to develop and produce environmentally friendly products
according to the Restriction of Hazardous Substances (RoHS) Directive (2002/95/EC) and the Waste Electrical and
Electronic Equipment (WEEE) Directive (2002/96/EC) established by the European Union. The RoHS directive was
adopted in February 2003 by the European Union and came into effect on July 1, 2006. It is not a law but a directive,
which restricts the use of six hazardous materials in the manufacturing of various types of electronic and electrical
equipment. It is closely linked with the Waste Electrical and Electronic Equipment Directive (WEEE) 2002/96/EC,
which has set targets for collection, recycling and recovery of electrical goods and is part of a legislative initiative to
solve the problem of huge amounts of toxic e-waste.
Each European Union member state is adopting its own enforcement and implementation policies using the directive
as a guide. Therefore, there could be as many different versions of the law as there are states in the EU. Additionally,
non-EU countries like China, Japan, or states in the U.S. such as California may have their own regulations for green
products, which are similar, but not identical, to the RoHS directive.
RoHS is often referred to as the "lead-free" directive but it restricts the use of the following substances:
» Lead
» Mercury
» Cadmium
» Chromium VI
» PBB and PBDE
The maximum allowable concentration of any of the above mentioned substances is 0.1% (except for Cadmium, which
is limited to 0.01%) by weight of homogeneous material. This means that the limits do not apply to the weight of the
finished product, or even to a component but to any single substance that could (theoretically) be separated
mechanically.
www.kontron.com 7
MSM800BEV/ User Information
1.8.1 RoHS Compatible Product Design
All Kontron Compact Computers (KCC) AG standard products comply with RoHS legislation.
Since July 1, 2006, there has been a strict adherence to the use of RoHS compliant electronic and mechanical
components during the design-in phase of all KCC AG standard products.
1.8.2 RoHS Compliant Production Process
Kontron Compact Computers AG selects external suppliers that are capable of producing RoHS compliant devices.
These capabilities are verified by:
» A confirmation from the supplier indicating that their production processes and resulting devices are RoHS
compliant.
» If there is any doubt of the RoHS compliancy, the concentration of the previously mentioned substances in a
produced device will be measured. These measurements are carried out by an accredited laboratory.
1.8.3 WEEE Application
The WEEE directive is closely related to the RoHS directive and applies to the following devices:
» Large and small household appliances
» IT equipment
» Telecommunications equipment (although infrastructure equipment is exempt in some countries)
» Consumer equipment
» Lighting equipment – including light bulbs
» Electronic and electrical tools
» Toys, leisure and sports equipment
» Automatic dispensers
It does not apply to fixed industrial plants and tools. The compliance is the responsibility of the company that brings
the product to market, as defined in the directive. Components and sub-assemblies are not subject to product
compliance. In other words, since Kontron Compact Computers AG does not deliver ready-made products to end users
the WEEE directive is not applicable for KCC AG. Users are nevertheless encouraged to properly recycle all electronic
products that have reached the end of their life cycle.
1.9 Swiss Quality
» 100% Made in Switzerland
» This product was not manufactured by employees earning piecework wages
» This product was manufactured in humane work conditions
» All employees who worked on this product are paid customary Swiss market wages and are insured
» ISO 9000:2001 (quality management system)
www.kontron.com 8
MSM800BEV/ User Information
1.10 The Swiss Association for Quality and Management Systems
The Swiss Association for Quality and Management Systems (SQS) provides certification and assessment services for
all types of industries and services. SQS certificates are accepted worldwide thanks to accreditation by the Swiss
Accreditation Service (SAS), active membership in the International Certification Network, IQNet, and co-operation
contracts/agreements with accredited partners.
www.sqs.ch
The SQS Certificate ISO 9001:2000 has been issued to Kontron Compact Computers AG in the field of development,
manufacturing and sales of embedded computer boards, embedded computer modules and computer systems. The
certification is valid for three years at which time an audit is performed for recertification.
www.kontron.com 9
MSM800BEV/ Introduction
2 Introduction
2.1 MSM800BEV Ordering Information
Part / Option Part Nr. Description
MSM800BEV 802110 Standard version with: full ISA-16bit support and PCI-ISA-bridge
Option -P+ 807005 PC/104-Plus with short connector
Option -L+ 807006 PC/104-Plus with long connector
Option -CF 807007 CompactFlash socket (not with 807006)
MSM800-CKCON 803035 MSM800 PC/104-cable kit
MSFLOPPY 891001 3.5" Micro-floppy drive (26pin)
MSFDCK 802600 Micro-floppy cable (26pin)
MSM800-LANCON 803046 LAN cable with PCB
MSM800-DVICON 803042 DVI-D interface
MSM800-LVDSCON 803044 LVDS interface
MSM800 Small Cooler 807041 For -25°C to +70°C temperatures
MSM800 Large Cooler 807042 For -40°C to +85°C temperatures (not with 802100, 802105)
MSM800 Thermojunction 807043 Direct thermal coupling, -40°C to +85°C temperatures (not with 802100, 802105)
MSM800DK 802118 Development Kit
Note: These are only examples; for current ordering codes, please see the current price list.
2.2 MSM800BEV Applications
» Information terminals
» Control of interactive devices
» Play systems with music output
» Measuring instruments
» Telecommunication devices
» Use in vehicles
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MSM800BEV/ Introduction
2.3 MSM800BEV Features
The MICROSPACE® MSM800 is a miniaturized modular device incorporating major elements of a standard PC/AT
compatible computer such as:
» Powerful Geode LX-800 500MHz
» BIOS ROM
» Timers, DMA
» Real-time clock with CMOS-RAM and battery buffer (external/onboard)
» LPT1 parallel port
» COM1-, COM2-RS2332 serial port
» Speaker interface
» AT keyboard interface or PS/2 keyboard interface
» Floppy disk interface
» AT IDE hard disk interface
» VGA/LCD video interface
» PC/104 ISA bus
» PC104+ PCI bus (option)
» PS/2 mouse interface
» 4 channel USB 2.0
» Optional: onboard CF socket Type II
» Single 5V supply
» EEPROM for setup and configuration
» UL approved parts
» Watchdog
The 8W power consumption permits passive cooling within a very broad ambient temperature range. Cooling options
must always be ordered separately.
The PC/104-Plus bus (ISA and PCI) and 4 USB interfaces are available as functional extensions.
This product complies with the PC/104 Consortium form factor 3.55 × 3.775 inches (90.17 × 95.89 mm) and is
available in "stack through" versions. The MSM800 is PCI/104-Express, version 1.0, compliant.
2.3.1 The MSM800BEV Model
» LAN Ethernet, INTEL 82551ER (V2.1 and later – or on request [optional] 82551QM)
» PCI to ISA bridge for full ISA support. Needs one PCI load/resource.
» SODIMM DDR-Memory holder (128-1024MByte)
» Sound controller
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2.4 Block Diagram
2.4.1 MSM800BEV
MSM800BEV/ Introduction
2.5 MICROSPACE® Documentation
This manual is written for the original equipment manufacturer (OEM) who plans to build computer systems based on
the single board MICROSPACE-PC. It is for integrators and programmers of systems based on the MICROSPACEComputer family. This manual provides instructions for installing and configuring the board and describes the system
and setup requirements. This document contains information on hardware requirements, interconnections, and
details of how to program the system. Please check the Product CD for further information and manuals.
www.kontron.com 12
2.6 Product Photo
2.6.1 MSM800BEV
Top View, with Option 807041 (small cooler):
MSM800BEV/ Introduction
Bottom View:
www.kontron.com 13
3 Specifications
Note: All information is subject to change without notice.
CPU
CPU Geode LX800
CPU Core Supply 1.8V very low powered
Mode Real/Protected
Compatibility 8086 – P5
Word Size 32bits
Secondary Cache –
Physical Addressing 32 lines
Virtual Addressing 16GBytes
Clock Rates 500MHz
Socket Standard Soldered BGA
Chipset
Northbridge AMD LX800
Southbridge AMD 5536
LAN 10/100Mbit Intel 82C551ER
Audio AC97 – V2.3
Firewire IEEE1394 Not onboard
Video 16MByte Video-DDRAM
MSM800BEV/ Specifications
Power Management
The LX800/900 supports ACPI and APM Version 1.2.
The following ACPI Sleep States are supported:
» S1 Sleep with CPU content.
» S4 Hibernation (LED is blinking) with transition to S5.
Available since V2.0
» S5-G2 Power Off (LED is blinking).
The device can be switched on by the Main Button (or with WOL if available).
Controller MSM800BEV
Bus 32bit high speed 33MHz PCI bus
Enhanced BIOS VGA/LCD BIOS
Memory 2-254MByte shared RAM
CRT-Monitor VGA, SVGA up to 1920x1440
Flat Panel TFT 3.3V18/24bit up to 1600x1200
Controller Modes CRT only; flat panel only; or simultaneous CRT and flat panel
Video Input No
Drivers WIN2000, XP
Mass Storage
FD Floppy disk interface, for max. 1 floppy with 26pin connector
HD
E-IDE interface, AT-type, for max. 2 hard disks, 44pin connector, for 1.3, 1.8 and 2.5" hard
disks with 44 pins IDE
Standard AT Interfaces
Name FIFO IRQs Address Standard Option
Serial
Parallel LPT1 printer interface mode: SPP(output), EPP (bidirectional) (Centronics)
Keyboard AT or PS/2 –keyboard
Mouse PS/2
Speaker 0.1 W output drive
RTC Integrated into the chipset, RTC with CMOS-RAM 256Byte
Backup Current
Non-chargeable Battery MSM800BEV: 3.6V lithium 400mAh internally or externally connected
COM1
COM2
(Baud rates: 50-115 KBaud programmable)
<5 µA
yes
yes
IRQ4
IRQ3
3F8
2F8
RS232C
RS232C
Bus
PC/104 ISA
Clock 8MHz defined by the Geode
IEEE-996 standard ISA bus, buffered
MSM800BEV: full 16bit ISA support
USB
USB 2.0
Transfer Rate 400MBps, 12.5MBps/1.5MBps
Channels 4
Peripheral Extension
ISA
PCI
With PC/104 bus
MSM800BEV: no ISA limitation
With PC/104-Plus bus
MSM800BEV: 4 slots – max. 4 master devices
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MSM800BEV/ Specifications
Power Supply
Working
Power Rise Time Unspecified
Power Consumption MSM800SEV V2.1 with HD, MS/KB (PS/2), CRT monitor, WindowsXP Desktop: typ. 7.5-10W
Standby Power Consumption
5 Volts ± 5%
MSM800BEV:
Windows Standby: 2.5W (without MS/KB wake-up function)
Windows Standby: 4.5W (with PS/2 wake-up function)
Physical Characteristics
Length: 90mm
Dimensions
Weight 90-170gr depending on model and cooler option
PCB Thickness 1.6mm / 0.0625 inches nominal
PCB Layer Multilayer
Depth: 96/99mm
Height: 17-25mm
Operating Environment
Relative Humidity 5-90% non-condensing
Vibration 5 to 2000Hz, 0.1G
Shock 1 g
Temperature
Storage All models: -55°C to +85°C
Operating Temperature without Cooler All models: 0°C to +60°C
Operating Temperature with 807041 All models: -25°C to +70°C
Extended Operating Temperature with 807042 Model BEV with E48: -40°C to +85°C
Extended Operating Temp. with 807043 and E48 Model BEV: -40°C to +85°C
EMI / EMC (IEC1131-2 refer MIL 461/462)
IEC 801-2, EN55101-2, VDE 0843/0847 Part 2
ESD Electro Static Discharge
REF Radiated Electromagnetic Field IEC 801-3, VDE 0843 Part 3, IEC770 6.2.9. (not tested)
EFT Electric Fast Transient (Burst)
SIR Surge Immunity Requirements
High-frequency Radiation EN55022
Metallic protection needed
Separate ground layer included
15 kV single peak
Mechanically compatible to Kontron Compact Computers MSMx86 boards and to
all other PC/104 boards.
Note: All information is subject to change without notice.
www.kontron.com 16
MSM800BEV/ Quick Start Guide
4 Quick Start Guide
Warning: ESD Sensitive Device! Place the embedded computer board on an isolated, ESD-protected surface.
Ensure that all equipment, tools and people are fully protected against ESD.
4.1 Print Manuals from the Product CD
Place the Product CD into the CD drive of a personal computer with a connected printer.
Open the CD; open the directory Manuals/MSM800.
Print out the required manuals (for example the BIOS manual or the User's Guide).
4.2 The MSM800CON, Part Nr. 803036
The MSM800CON must be ordered separately.
www.kontron.com 17
The MSM800CON connected to an MSM800BEV board:
MSM800BEV/ Quick Start Guide
4.3 The LANCON, Part Nr. 803046
www.kontron.com 18
4.4 The DVICON, Part Nr. 803042
The DVICON connected to an MSM800BEV board:
MSM800BEV/ Quick Start Guide
www.kontron.com 19
MSM800BEV/ Quick Start Guide
4.5 Connect Peripherals to the Board
Prepare the following peripherals:
» VGA monitor (LCD or CRT) with a resolution up to 1024x768 pixel
» PS2 keyboard
» USB mouse
» LAN cable, if available
» Hard disk or CompactFlash
» USB CD drive or floppy drive
» Power supply with 5 Volts and min. 30 Watts
Make sure the polarity is correct. Otherwise the hard disk and/or electronic board may be destroyed.
1. Connect the VGA monitor to the 15pin high density DSub-connector.
2. Connect the keyboard to the PS/2 connector.
3. Connect the USB mouse to one of the USB connectors.
4. Connect the hard disk with a 44pin cable to the IDE connector.
Alternatively to the hard disk, the CompactFlash card may be inserted into the CF socket.
Pin1 of the cable must go to Pin1 of the connector, which has a red mark next to it (not visible in the photo).
5. Connect a USB CD-Drive or a USB Floppy drive to one of the USB connectors.
6. Insert a boot device: USB stick, floppy, hard disk or bootable CF.
www.kontron.com 20
MSM800SEV with the contents of the Cable Kit (CKCON):
MSM800BEV/ Quick Start Guide
All of the above cables and PCB connectors are included in the MSM800CKCON, Part Nr. 803035 (the MSM800 board is
not included).
4.6 The Development Kit, Part Nr. 802118
The Development Kit (DK) allows for an immediate start-up with the embedded system. The hard disk includes a DOS
and a LINUX kernel V2.6 boot partition.
The following material is included in the current MSM800DK:
Item Part Number
1x MSM800BEV 802110
1x MSM800CKCON 803035
1x MSM800DVICON 803042
1x 256MB DRAM 890670
1x 3.5" floppy drive 891001
1x 2.5" hard disk 890003
www.kontron.com 21
4.7 Power Up the Board
1. Check that the voltage is regulated to +5Volt and that the polarity is correct.
Attention! The supply voltage must be in the range of 4.9Volt to maximum 5.25Volt.
2. Switch on the connected monitor.
3. Switch on the external 5V power supply.
Attention! Jumper J1 determines the mode of the CompactFlash disk.
J1 – CF Master
MSM800BEV/ Quick Start Guide
www.kontron.com 22
Attention! Jumper J2 determines the behavior after power-on.
J2 – Autostart
MSM800BEV/ Quick Start Guide
In autostart mode the board will automatically enter the boot sequence and the green "Power LED" will turn on.
In non-autostart mode the board will remain in standby mode until the power button is pressed.
www.kontron.com 23
After a few seconds the screen should display the BIOS initial message/picture:
MSM800BEV/ Quick Start Guide
www.kontron.com 24
MSM800BEV/ Quick Start Guide
4.8 BIOS Setup
Since the BIOS is auto-configuring during the start-up procedure, the user normally does not enter the BIOS setup.
Manual setup is needed only to change the default settings. Please refer to the driver/software/BIOS manual printed
from the Product CD for the BIOS setup details.
4.9 Boot Up the Operating System and Install the Drivers
Depending on which boot drive is available, boot up the operating system from the CompactFlash, hard disk, or floppy
disk.
To install the drivers, see the BIOS/Driver/Software/ manual on the Product CD.
www.kontron.com 25
5 Connectors & Jumpers
5.1 Connectors
The following pages describe the connector pin-out for all current MSM800 boards.
Flat cable
44pin IDE is: IDT Terminal for Dual Row (2.00mm grid) and 1.00mm flat cable
All others are: IDT Terminal for Dual Row 0.1" (2.54mm grid) and 1.27mm flat cable
NC: not connected
Connector Structure Pin Remarks
X1 Power 2x4 2.54mm
X10 VGA 2x5 2.54mm
X15 LCD 2x22 2mm
X29 Sound Audio I/O 2x15 2.00mm
X30 LPT1 2x13 2.54mm
X31 Keyboard, mouse, utility 2x5 2.54mm
X33 LAN / Battery 2x5 2.00mm
X38 COM1 2x5 2.54mm
X39 COM2 2x5 2.54mm
X44 IrDA 4 2.54mm
X50 USB 1 4 2.54mm
X51 USB 2 4 2.54mm
X52 USB 3 4 2.54mm
X53 USB 4 4 2.54mm
X60 IDE 2x22 2mm
X70 Floppy 26 FCC micro
X71 CompactFlash Holder
X101 PC104+ 120 2mm
X102 PC104 104 2.54mm
X110 POD Port 2x7 2mm
X230 JTAG-Port 4 2.54mm
X300 SODIMM 144 0.8mm
MSM800BEV/ Connectors & Jumpers
www.kontron.com 26
5.1.1 Top Side of the MSM800BEV V2.1
MSM800BEV/ Connectors & Jumpers
www.kontron.com 27
5.1.2 Bottom Side of the MSM800BEV V2.1
With CompactFlash (Option 807007, connector X71).
MSM800BEV/ Connectors & Jumpers
www.kontron.com 28
MSM800BEV/ Connectors & Jumpers
1 3 5 7
2 4 6 8
5.1.3 X1 Power Supply
Pin Signal Pin Signal
1 GND 2 VCCSUS +5Volt Input Supply
3 NC 4 (+12V input)
5 NC 6 Main_SW (Push button to switch on the board if J2 is open)
7 GND 8 VCCSUS +5Volt Input Supply
VCCSUS = 5Volt Main Supply Input
Pin placement:
5.1.4 X10 VGA Monitor (CRT-signals)
X10 Header 15 pins HiDensity DSUB
10 Pin -M Signal Pin Signal
2 VGA red 1 Red
4 VGA green 2 Green
6 VGA blue 3 Blue
8 Horizontal Synch 13 H-Synch
9 Vertical Synch 14 V-Synch 5 + 11 Bridged
1 Ground 5, 6, 7, 8 Ground
3 NC
5 NC
7 Serial_Data 12 DDC-SDA
10 Serial_Clock 15 DDC-SCL
The VGA-CRT signals from X10 must be wired to a standard VGA HiDensity DSub connector (female):
The LCD signals must be wired panel specific.
Solder-side view of the female 15pin HiDSub
www.kontron.com 29
MSM800BEV/ Connectors & Jumpers
5V
5.1.5 X15 LCD TFT Interface (flat panel signals)
Pin Signal TFT 18bit TFT 24bit
1 FPM (out) LDE LDE
2 CRT-Vert.Synch VSYNC VSYNC
3 Backlight Supply output (5/12V)
4 CRT-Horiz.Synch HSYNC HSYNC
5 VCC 3.3V
6 Ground
7 NC
8 Shift Clock CKL CKL
9 VDD Supply output (3/5V) ENLVDD ENLVDD
10 FP0 Blue 0
11 FP1 Blue 1
12 FP2 Blue 0 Blue 2
13 FP3 Blue 1 Blue 3
14 FP4 Blue 2 Blue 4
15 FP5 Blue 3 Blue 5
16 FP6 Blue 4 Blue 6
17 FP7 Blue 5 Blue 7
18 FP8 Green 0
19 FP9 Green 1
20 FP10 Green 0 Green 2
21 FP11 Green 1 Green 3
22 FP12 Green 2 Green 4
23 FP13 Green 3 Green 5
24 FP14 Green 4 Green 6
25 FP15 Green 5 Green 7
26 Ground
27 FP16 Red 0
28 FP17 Red 1
29 FP18 Red 0 Red 2
30 FP19 Red 1 Red 3
31 FP20 Red 2 Red 4
32 FP21 Red 3 Red 5
33 FP22 Red 4 Red 6
34 FP23 Red 5 Red 7
35 NC
36 Reserved PICR
37 Reserved VPIC
38 Reserved PIC_DAT
39 Reserved PIC_CLK
40 Reserved PIC_OSC1
41 Ground
42 NC
43 +5Volt Supply (out)
44 +12Volt Supply (out)
1 VCC +5Volt
2 IDX Index Pulse in
3 VCC +5Volt
4 DS2 Drive Select 2 out
5 VCC +5Volt
6 DCHG Disk Change in
7 NC
8 NC
9 NC
10 M02 Motor On 2 out
11 NC
12 DIRC Direction Select out
13 NC
14 STEP Step out
15 GND
16 WD Write Data out
17 GND Signal grounds
18 WE Write Enable out
19 GND Signal grounds
20 TRKO Track 0 in
21 GND Signal grounds
22 WP Write Protect in
23 GND Signal grounds
24 RDD Read Data in
25 GND Signal grounds
26 HS Head Select out
The KEY pins are to guarantee proper module installation. PinA1 will be removed and the female side
plugged for 5.0V I/O signals and PinD30 will be modified in the same manner for 3.3V I/O. It is
recommended that both KEY pins (A1 and D30) be electrically connected to GND for shielding.
KCC boards have them as NC (not connected).
For more information please see the Section on BIOS Diagnostics – Post Codes in the BIOS/Driver/Software manual
"Geode LX800 / LX900" found on the Product CD or in the download area of Kontron Compact Computers' website.
The following table shows the location of all jumper blocks on the MSM800 board. The numbers shown in this figure
are silk screened on the board so that the pins can easily be located. This section refers to the individual pins for these
jumpers. The default jumper settings are written in bold.
Attention! Some jumpers are soldering bridges; you will need a miniature soldering station with a vacuum pump.
5.2.1 The Jumpers on the MSM800BEV
Settings written in bold are defaults!
Jumper Structure 1-2 / open 2-3 / closed Remarks
J1 Compact Flash select
J2 Power On Switch Connect push button to X1 pin 6
J5 LCD VDD
J6 LCD BKL (Backlight)
J7 CMOS/EEPROM reset
J8 WOL (Wake on LAN)
Refer to Section 9.4 for important information!
Before Version 2.1, Jumpers 5 and 6 were located on the top of the board.
Slave
3.3V
5V
Normal function
Enable
Master Top
always on
5V Bottom
12V Bottom
Reset Top
Disable Bottom, since V2.1
Top
The 12V will not be generated on the board but must be supplied from an external PSU through connector
X1Pin4.
www.kontron.com 37
MSM800BEV/ Detailed System Description
6 Detailed System Description
This system's configuration is based on the ISA architecture. Check the I/O and the Memory maps in this Chapter.
6.1 Incompatibilities to a Standard PC/AT
6.1.1 PC104 BUS / ISA BUS
An onboard LPC to ISA-bridge makes it possible to expand the functionality of the board with additional PC/104 cards.
Unfortunately, because of the transformation from LPC to ISA it is not possible to realize a 16bit access. This does not
mean that these cards cannot be used, but that the 16bit access is divided into two. Therefore the access to these
cards is a little bit slower.
Attention! With the BEV version, this limitation is solved by using a PCI-ISA bridge. The disadvantage is that now 2
PCI devices are onboard and there are only 2 external PCI slots available.
6.1.2 Keyboard versus NUM-Lock
Without a connected keyboard, the NUM-Lock ON field in the BIOS setup must not be activated. Otherwise the timeout noticeably slows down the reaction speed of the computer as soon as the keyboard is not connected. The PS2
peripherals (KB and MS) are not hot-plug compatible.
6.2 Related Application Notes
Application Notes are available at http://support.kcc-ag.ch/ or on any KCC Application CD.
6.3 High Frequency Radiation (to meet EN55022)
Since the PC/104 CPU modules are very highly integrated embedded computers, peripheral lines are not protected
against radiation from the high frequency spectrum. To meet a typical EN55022 requirement, all peripherals that go
outside of the computer case must be externally filtered.
Typical signals that must be filtered:
Keyboard: KBCLK, KBDATA and VCC
Mouse: MSCLK, MSDATA and VCC
COM1/2/3/4: All serial signals must be filtered
LPT: All parallel signals must be filtered
CRT: Red, blue, green, hsynch and vsynch must be filtered
Typical signals that must not be filtered, since they are used internally:
IDE: Connected to the hard disk
Floppy: Connected to the floppy
LCD: Connected to the internal LCD
6.3.1 For Peripheral Cables
Use a filtered version for all DSUB connectors. Select the filter specifications carefully. Place the filtered DSUB
connector directly on the front side and be sure that the shielding makes good contact with the case.
9pin DSUB connector from AMPHENOL FCC17E09P 820pF
25pin DSUB connector from AMPHENOL FCC17B25P 820pF
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MSM800BEV/ Detailed System Description
6.3.2 For Stack-Through Applications
On each peripheral signal line that goes outside the computer case, place a serial inductivity followed by a grounded
capacitor of 100pF to 1000pF. In this case, no filtered connectors are needed. Place the filter directly under or behind
the onboard connector.
Serial Inductivity TDK HF50ACB321611-T 100MHz, 500mA, 1206 Case
Ground Capacitor Ceramic Capacitor with 1000pF
6.3.3 Power Supply
Use a current-compensated dual inductor on the 5V supply.
SIEMENS B82721-K2362-N1 with 3.6A, 0.4mH
6.4 Battery Lifetime
Note: The RTC back-up battery is only assembled onboard the MSM800SEV/BEV/XEV systems.
Battery Specifications
Manufacturer pba
Type ER10280
Capacity versus Temp. 10uA 430mAh 400mAh 300mAh
Voltage versus Temp. 10uA 3.6V 3.6V Ca. 3.6V
Nominal Values 3.6V / 400mAh @ 0.5mA / -55°C...~+85°C
Lowest Temp.
-40°C
Nominal Temp.
+20°C
Highest Temp.
+85°C
Information is taken from the datasheet of the battery manufacturer.
Product
Battery Current +25°C 3.6 < 1 < 4
Battery Lifetime +25°C > 5 years > 5 years
Temperature
°C
Battery Voltage
V
VCC (+5)
switched ON
µA
VCC (+5V)
switched off
µA
6.4.1 External Battery Assembly:
The external battery must be a lithium 3.6Volt with a capacity from 400-800mAh.
If the customer wants to connect an external battery (check for the appropriate connector in Chapter 5), some
precautions must be taken:
» Do not use a rechargeable battery – the battery is prohibited from charging.
» The RTC device defines a voltage level of 3-3.6V, so use an external battery within this range (inclusive of the
diode which is already assembled onboard).
Attention: For systems that already have an onboard battery (MSM800SEV/BEV/XEV): if an external battery is
to be connected, then the onboard battery must be removed first.
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MSM800BEV/ Detailed System Description
6.5 Power Requirements
The power is connected through the PC/104 power connector; or the separate power connector on the board. The
supply uses only +5Volts and a ground connection.
Attention: Be sure the power plug is wired correctly before supplying power to the board! A built-in diode protects
the board against reverse polarity.
Tolerance of the 5V supply:5Volt ±5%; the power-fail signal starts at ±10% of the 5V norm and generates a reset
status for the MICROSPACE PC.
Test environment for the power consumption measurement:
Peripherals:
Hard disk Hitachi Mod-HTS424020M9AT00 20GB
Monitor Eizo Flexscan F340i.W
PS/2-KB Logitech Mod-iTouch Keyboard
PS/2-MS Logitech Mod-M-CAA43
Floppy TEAC Mod-FD-05HF
Software:
MS-DOS V6.22
WinXP
Current consumption @ 5Volt supply at -40°C/+25°C/+85°C:
Boot from Hard disk to "Starting MS-DOS"-Prompt - 17
Boot from Hard disk to XP desktop - 45
Booting without a storage device (only BIOS) 10
6.7 CPU, Boards and RAMs
6.7.1 CPUs of this MICROSPACE Product
Processor Type Clock
GEODE LX800 National 500MHz
6.7.2 Numeric Coprocessor
The numeric coprocessor is always integrated into the Pentium CPUs.
www.kontron.com 40
6.7.3 DDRAM Memory on MSM800BEV
Speed 333
Size
Bits 64bit
Capacity
Bank 1
DDR-SODIMM
DDRDIMM 200pin
256-1024 MByte
DDR-SODIMM
6.8 Interfaces
6.8.1 AT Compatible Keyboard & PS/2 Mouse X31
Pin Signal
1 Speaker out
2 GND
3 External reset input
4 VCC
5 Keyboard Data
6 Keyboard Clock
7 GND
8 Battery
9 Mouse Clock (PS/2)
10 Mouse Data (PS/2)
BAT input 3.0-3.6V, external lithium battery (see also Section 6.4.1).
MSM800BEV/ Detailed System Description
6.8.2 Line Printer Port LPT1
A standard bi-directional LPT port is integrated into the MICROSPACE PC.
Further information about these signals is available in numerous publications, including the IBM technical reference
manuals for the PC and AT computers and from other reference documents.
The current is: IOH = 12mA IOL = 24mA
6.8.3 Serial Ports COM1-COM2
The serial channels are fully compatible with 16C550 UARTS. COM1 is the primary serial port and is supported by the
board's ROM-BIOS as the PC-DOS 'COM1' device. The secondary serial port is COM2; it is supported as the 'COM2'
device.
Standard: COM 1/2: National PC87317VUL: 2 x 16C550 compatible serial interfaces
Serial Port Connectors COM1, COM2:
Pin Signal Function in/out DB25 Pin DB9 Pin
1 CD Data Carrier Detect in 8 1
2 DSR Data Set Ready in 6 6
3 RXD Receive Data in 3 2
4 RTS Request To Send out 4 7
5 TXD Transmit Data out 2 3
6 CTS Clear to Send in 5 8
7 DTR Data Terminal Ready out 20 4
8 RI Ring Indicator in 22 9
9 GND Signal Ground 7 5
The serial port signals are compatible with the RS232C specifications.
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MSM800BEV/ Detailed System Description
6.8.4 Floppy Disk Interface
The onboard floppy disk controller and ROM-BIOS support one or two floppy disk drives in any of the standard PC-DOS
and MS-DOS formats shown in the table.
The desired configuration of floppy drives (number and type) must be properly initialized in the board's CMOS configuration memory. This is generally done by using DEL or F2 at boot up time.
Floppy Interface Connector
The table shows the pin-out and signal definitions of the board's floppy disk interface connector. It is identical in pinout to the floppy connector of a standard AT. Note that, as in a standard PC or AT, both floppy drives are jumpered to
the same drive select: as the 'second' drive. The drives are uniquely selected as a result of a swapping of a group of
seven wires (conductors 10-16) that must be in the cable between the two drives. The seven-wire swap goes between
the computer board and drive 'A'; the wires to drive 'B' are unswapped (or swapped a second time). The 26pin high
density (1mm pitch FCC) connector has only one drive and motor select. The onboard jumper defines the drive A: or
B:. Default is always A:.
Floppy Disk Interface Technology
Only CMOS drives are supported. This means the termination resistors are 1K Ohm and 5¼" drives are not
recommended (TTL interface).
1 VCC +5Volt
2 IDX Index pulse in
3 VCC +5Volt
4 DS2 Drive select 2 out
5 VCC +5Volt
6 DCHG Disk change in
10 M02 Motor on 2 out
12 DIRC Direction select out
14 STEP Step out
16 WD Write data out
17 GND Signal ground
18 WE Write enable out
19 GND Signal ground
20 TRKO Track 0 in
21 GND Signal grounds
22 WP Write protect in
23 GND Signal ground
24 RDD Read data in
25 GND Signal ground
26 HS Head select out
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MSM800BEV/ Detailed System Description
6.8.5 Speaker Interface
One of the board's CPU devices provides the logic for a PC compatible speaker port. The speaker logic signal is
buffered by a transistor amplifier, and provides approximately 0.1 Watt of audio power to an external 8 Ohm speaker.
Connect the speaker between VCC and speaker output to have no quiescent current.
6.9 Controllers
6.9.1 Interrupt Controllers
An 8259A compatible interrupt controller, within the chipset, provides seven prioritized interrupt levels. Of these,
several are normally associated with the board's onboard device interfaces and controllers, and several are available
on the AT expansion bus.
Interrupt Sources Used Onboard
IRQ0 ROM-BIOS clock tick function, from timer 0 yes
IRQ1 Keyboard controller output buffer full yes
IRQ2 Used for cascade 2. 8259 yes
IRQ3 COM2 serial port yes
IRQ4 COM1 serial port yes
IRQ5 LPT2 parallel printer (if present) no
IRQ6 Floppy controller yes
IRQ7 LPT1 parallel printer yes
IRQ8 Battery backed clock yes
IRQ9 Free for user no
IRQ10 Free for user no
IRQ11 Free for user no
IRQ12 PS/2 mouse yes
IRQ13 Math. coprocessor yes
IRQ14 Hard disk IDE yes
IRQ15 Free for user no
May depend on the LAN configuration.
6.10 Timers and Counters
6.10.1 Programmable Timers
An 8253 compatible timer/counter device is also included in the board's ASIC device. This device is utilized in
precisely the same manner as in a standard AT implementation. Each channel of the 8253 is driven by a 1.190MHz
clock, derived from a 14.318MHz oscillator, which can be internally divided in order to provide a variety of
frequencies.
Timer 2 can also be used as a general purpose timer if the speaker function is not required.
Timer Assignment:
Timer Function
0 ROM-BIOS clock tick (18.2Hz)
1 DRAM refresh request timing (15µs)
2 Speaker tone generation time base
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MSM800BEV/ Detailed System Description
6.10.2 RTC (Real Time Clock)
An AT compatible date/time clock is located within the chipset. The device also contains a CMOS static RAM,
compatible with that in standard ATs. System configuration data is normally stored in the clock chip's CMOS RAM in a
manner consistent with the convention used in other AT compatible computers.
Connect an external lithium battery to X33 pin6 (or use the mounted battery). Be sure to use the correct polarity!
The battery-backed clock can be set by using the Kontron Compact Computers AG setup at boot-time.
Note: On all MSM800SEL/XEL boards – the battery must be connected externally! There is no battery assembled
onboard.
Attention: For systems that already have an onboard battery (MSM800SEV/BEV/XEV): if an external battery is to be
connected, then the onboard battery must be removed first.
6.10.3 Watchdog
The watchdog timer detects a system crash and performs a hardware reset. After power up, the watchdog is always
disabled as the BIOS does not send strobes to the watchdog. In case the user wants to take advantage of the
watchdog, the application must produce a strobe at least every 800 ms. If no strobe occurs within the 800 ms, the
watchdog resets the system.
For more information, please refer to the BIOS/Driver/Software manual “GEODE_LX800-LX900” on the Product CD.
The watchdog feature is integrated in the INT15 function.
Some programming examples are available:
Product CD-Rom or customer download area: \TOOLS\DL-INT15_Tool\…
6.11 CMOS RAM Map
Systems based on the industry-standard specification include a battery backed Real Time Clock chip. This clock
contains at least 64Bytes of non-volatile RAM. The system BIOS uses this area to store information including system
configuration and initialization parameters, system diagnostics, and the time and date. This information remains
intact even when the system is powered down.
The BIOS supports 128Bytes of CMOS RAM. This information is accessible through I/O ports 70h and 71h. CMOS RAM
can be divided into several segments:
» Locations 00h - 0Fh contain the real time clock (RTC) and status information
» Locations 10h - 2Fh contain system configuration data
» Locations 30h - 3Fh contain system BIOS-specific configuration data as well as chipset-specific information
» Locations 40h - 7Fh contain chipset-specific information as well as power management configuration
parameters
The following table provides a summary of how these areas may be further divided.
Beginning Ending Checksum Description
00h 0Fh No RTC and Checksum
10h 2Dh Yes System Configuration
2Eh 2Fh No Checksum Value of 10h - 2Dh
30h 33h No Standard CMOS
34h 3Fh No Standard CMOS - SystemSoft Reserved
40h 5Bh Yes Extended CMOS - Chipset Specific
5Ch 5Dh No Checksum Value of 40h - 5Bh
5Eh 6Eh No Extended CMOS - Chipset Specific
6Fh 7Dh Yes Extended CMOS - Power Management
7Eh 7Fh No Checksum Value of 6Fh - 7Dh
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6.11.1 CMOS Map
Location Description
00h Time of day (seconds) specified in BCD
01h Alarm (seconds) specified in BCD
02h Time of day (minutes) specified in BCD
03h Alarm (minutes) specified in BCD
04h Time of day (hours) specified in BCD
05h Alarm (hours) specified in BCD
06h Day of week specified in BCD
07h Day of month specified in BCD
08h Month specified in BCD
09h Year specified in BCD
Status Register A
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh Shutdown Code
Bit 7 = Update in progress
Bits 6-4 = Time based frequency divider
Bits 3-0 = Rate selection bits that define the periodic interrupt rate and output frequency.
Status Register B
Bit 7 = Run/Halt
0 = Run
1 = Halt
Bit 6 = Periodic Timer
0 = Disable
1 = Enable
Bit 5 = Alarm Interrupt
0 = Disable
1 = Enable
Bit 4 = Update Ended Interrupt
0 = Disable
1 = Enable
Bit 3 = Square Wave Interrupt
0 = Disable
1 = Enable
Bit 2 = Calendar Format
0 = BCD
1 = Binary
Bit 1 = Time Format
0 = 12-Hour
1 = 24-Hour
Bit 0 = Daylight Savings Time
0 = Disable
1 = Enable
Status Register C
Bit 7 = Interrupt Flag
Bit 6 = Periodic Interrupt Flag
Bit 5 = Alarm Interrupt Flag
Bit 4 = Update Interrupt Flag
Bits 3-0 = Reserved
Status Register D
Bit 7 = Real Time Clock
0 = Lost Power
1 = Power
CMOS Location for Bad CMOS and Checksum Flags
Bit 7 = Flag for CMOS Lost Power
0 = Power OK
1 = Lost Power
Bit 6 = Flag for CMOS checksum bad
0 = Checksum is valid
1 = Checksum is bad
MSM800BEV/ Detailed System Description
www.kontron.com 45
Location Description
Diskette Drives
Bits 7-4 = Diskette Drive A
0000 = Not installed
0001 = Drive A = 360 kB
0010 = Drive A = 1.2MB
0011 = Drive A = 720 kB
0100 = Drive A = 1.44MB
10h
0101 = Drive A = 2.88MB
Bits 3-0 = Diskette Drive B
0000 = Not installed
0001 = Drive B = 360 kB
0010 = Drive B = 1.2MB
0011 = Drive B = 720 kB
0100 = Drive B = 1.44MB
0101 = Drive B = 2.88MB
11h Reserved
Fixed (Hard) Drives
Bits 7-4 = Hard Drive 0, AT Type
0000 = Not installed
0001-1110 = Types 1-14
1111 = Extended drive types 16-44.
12h
See location 19h.
Bits 3-0 = Hard Drive 1, AT Type
0000 = Not installed
0001-1110 = Types 1-14
1111 = Extended drive types 16-44.
See location 2Ah.
13h Reserved
Equipment
Bits 7-6 = Number of Diskette Drives
00 = One diskette drive
01 = Two diskette drives
10, 11 = Reserved
Bits 5-4 = Primary Display Type
00 = Adapter with option ROM
01 = CGA in 40 column mode
14h
10 = CGA in 80 column mode
11 = Monochrome
Bits 3-2 = Reserved
Bit 1 = Math Coprocessor Presence
0 = Not installed
1 = Installed
Bit 0 = Bootable Diskette Drive
0 = Not installed
1 = Installed
15h Base Memory Size (in kB) - Low Byte
16h Base Memory Size (in kB) - High Byte
17h Extended Memory Size (in kB) - Low Byte
18h Extended Memory Size (in kB) - High Byte
19h Extended Drive Type - Hard Drive 0
1Ah Extended Drive Type - Hard Drive 1
These 6 Bytes (48 bits) contain the following data:
Cylinders 10bits range 0-1023
1Fh - 24h
Landing Zone 10bits range 0-1023
Write Precompensation 10bits range 0-1023
Heads 08bits range 0-15
Sectors/Track 8bits range 0-254
1Fh
Byte 0
Bits 7-0 = Lower 8 bits of Cylinders
Byte 1
20h
Bits 7-2 = Lower 6 bits of Landing Zone
Bits 1-0 = Upper 2 bits of Cylinders
Byte 2
21h
Bits 7-4 = Lower 4 bits of Write Precompensation
Bits 3-0 = Upper 4 bits of Landing Zone
Byte 3
22h
Bits 7-6 = Reserved
Bits 5-0 = Upper 6 bits of Write Precompensation
23h
24h
Byte 4
Bits 7-0 = Number of Heads
Byte 5
Bits 7-0 = Sectors Per Track
Custom Drive Table 1
These 6 Bytes (48 bits) contain the following data:
Cylinders 10bits range 0-1023
25h - 2Ah
Landing Zone 10bits range 0-1023
Write Precompensation 10bits range 0-1023
Heads 08bits range 0-15
Sectors/Track 08bits range 0-254
25h
Byte 0
Bits 7-0 = Lower 8 bits of Cylinders
Byte 1
26h
Bits 7-2 = Lower 6 bits of Landing Zone
Bits 1-0 = Upper 2 bits of Cylinders
Byte 2
27h
Bits 7-4 = Lower 4 bits of Write Precompensation
Bits 3-0 = Upper 4 bits of Landing Zone
Byte 3
28h
Bits 7-6 = Reserved
Bits 5-0 = Upper 6 bits of Write Precompensation
29h
Byte 4
Bits 7-0 = Number of Heads
MSM800BEV/ Detailed System Description
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Location Description
2Ah
2Bh
2Ch
2Dh Reserved
2Eh High Byte of Checksum - Locations 10h to 2Dh
2Fh Low Byte of Checksum - Locations 10h to 2Dh
30h Extended RAM (kB) detected by POST - Low Byte
31h Extended RAM (kB) detected by POST - High Byte
32h BCD Value for Century
33h
34h
35h
36h
40h-7Fh Definitions for these locations vary depending on the chipset.
Byte 5
Bits 7-0 = Sectors Per Track
Boot Password
Bit 7 = Enable/Disable Password
0 = Disable Password
1 = Enable Password
Bits 6-0 = Calculated Password
SCU Password
Bit 7 = Enable/Disable Password
0 = Disable Password
1 = Enable Password
Bits 6-0 = Calculated Password
Base Memory Installed
Bit 7 = Flag for Memory Size
0 = 640kB
1 = 512kB
Bits 6-0 = Reserved
Minor CPU Revision
Differentiates CPUs within a CPU type (i.e., 486SX vs 486 DX, vs 486 DX/2). This is crucial for correctly
determining CPU input clock frequency. During a power-on reset, Reg DL holds minor CPU revision.
Major CPU Revision
Differentiates between different CPUs (i.e., 386, 486, Pentium). This is crucial for correctly determining CPU
input clock frequency. During a power-on reset, Reg DH holds major CPU revision.
Hotkey Usage
Bits 7-6 = Reserved
Bit 5 = Semaphore for Completed POST
Bit 4 = Semaphore for 0 Volt POST (not currently used)
Bit 3 = Semaphore for already in SCU menu
Bit 2 = Semaphore for already in PM menu
Bit 1 = Semaphore for SCU menu call pending
Bit 0 = Semaphore for PM menu call pending
MSM800BEV/ Detailed System Description
6.12 EEPROM saved CMOS Setup
The EEPROM has different functions, as listed below:
» Backup of the CMOS-Setup values
» Storing system information (i.e., version, production date, customization of the board, CPU type)
» Storing user/application values
The EEPROM updates automatically after exiting the BIOS setup menu. The system will also operate without any CMOS
battery. While booting, the CMOS is automatically updated with the EEPROM values.
Press the ESC-key while powering on the system before the video shows the BIOS message and the CMOS will not be
updated. This is helpful, if wrong parameters have been stored in the EEPROM and the BIOS setup does not start.
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MSM800BEV/ Detailed System Description
If the system hangs or a problem appears, the following steps must be performed:
1. Reset the CMOS-Setup (disconnect the battery for at least 10 minutes).
2. Press ESC until the system starts up.
3. Enter the BIOS Setup:
a. load DEFAULT values
b. enter the settings for the environment
c. exit the setup
4. Restart the system.
The user may access the EEPROM through the INT15 special functions. Refer to that chapter in the GEODE LX800-LX900
manual on the Product CD.
The system information is read-only and uses the SFI functions. Refer to the GEODE LX800-LX900 manual.
6.12.1 EEPROM Memory for Setup
The EEPROM is used for setup and configuration data, stored as an alternative to the CMOS-RTC. Optionally, the
EEPROM setup driver may update the CMOS RTC, if the battery is running down and the checksum error would appear
and stop the system. The capacity of the EEPROM is 2 kByte.
Organization of the 2048Byte EEPROMs:
Address Map Function
0000h CMOS-Setup valid (01=valid)
0001h Reserved
0003h Flag for KCC-Message (FF=no message)
0010h-007Fh Copy of CMOS-Setup data
0080h-00FFh Reserved for AUX-CMOS-Setup
0100h-010Fh Serial-Number
0110h-0113h Production date (year/day/month)
0114h-0117h 1. Service date (year/day/month)
0118h-011Bh 2. Service date (year/day/month)
011Ch-011Fh 3. Service date (year/day/month)
0120h-0122h Boot errors (Auto incremented if any boot error occurs)
0123h-0125h Setup entries (Auto incremented on every Setup entry)
0126h-0128h Low battery (Auto incremented every time the battery is low, EEPROM -> CMOS)
0129h-012Bh Startup (Auto incremented on every power-on start)
0130h Reserved
0131h Reserved
0132h/0133h BIOS Version (V1.4 => [0132h]:= 4, [0133h]:=1)
0134h/0135h Board Version (V1.5 => [0124h]:=5, [0125h]:=1)
0136h Board type (‘M’=PC/104, ‘E’=Euro, ‘W’=MSWS, ‘S’=Slot, ‘C’=Custom, ‘X’= smartCore or smartModule)
0137h CPU type: (01h=ELAN300/310, 02h=ELAN400, 05h=P5, 08h=P3, 09h=ELAN520, 10h=P-M).
0200h-03FFh Reserved
0200h-027Fh Reserved
0400h-07FFh Free for Customer use
6.13 Memory & I/O Map
6.13.1 System Memory Map
The X86 CPU, used as a central processing unit on the MICROSPACE, has a memory address space which is defined by
32 address bits. Therefore, it can address 1GByte of memory. The memory address map is as follows:
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MSM800BEV/ Detailed System Description
CPU GEODE:
Address Size Function / Comments
000000 - 09FFFFh 640kByte Onboard DRAM for DOS applications
0A0000 - 0BFFFFh 128kByte CGA, EGA, LCD Video RAM 128kB
0C0000 - 0C7FFFh
0C8000 - 0CFFFFh
0D0000 - 0DFFFFh 64kByte Free for user
0E0000 - 0EBFFFh
0EC000 - 0EFFFFh
0F0000 - 0FFFFFh 64kByte Core BIOS
100000 - 1FFFFFFh 31MByte DRAM for extended onboard memory
32kByte
32kByte
32kByte
16kByte
VGA BIOS
Free for user
BIOS
BIOS extensions
6.13.2 System I/O Map
The following table details the legacy I/O range for 000h through 4FFh. Each I/O location has a read/write (R/W)
capability.6565656565
Note the following abbreviations:
--- Unknown or cannot be determined.
Yes Read and write the register at the indicated location. No shadow required.
WO Write only. Value written can not be read back. Reads do not contain any useful information.
RO Read only. Writes have no effect.
Shw The value written to the register can not be read back via the same I/O location. Read back is accomplished via
a "Shadow" register located in MSR space.
Shw@ Reads of the location return a constant or meaningless value.
Shw$ Reads of the location return a status or some other meaningful information.
Rec Writes to the location are “recorded” and written to the LPC. Reads to the location return the recorded value.
The LPC is not read.
I/O Map:
I/O Address Function Size R/W Comment
000h Slave DMA Address - Channel 0 8bit Yes 16bit values in two transfers.
001h Slave DMA Counter - Channel 0 8bit Yes 16bit values in two transfers.
002h Slave DMA Address - Channel 1 8bit Yes 16bit values in two transfers.
003h Slave DMA Counter - Channel 1 8bit Yes 16bit values in two transfers.
004h Slave DMA Address - Channel 2 8bit Yes 16bit values in two transfers.
005h Slave DMA Counter - Channel 2 8bit Yes 16bit values in two transfers.
006h Slave DMA Address - Channel 3 8bit Yes 16bit values in two transfers.
007h Slave DMA Counter - Channel 3 8bit Yes 16bit values in two transfers.
008h Slave DMA Command/Status - Channels [3:0] 8bit Shw$
009h Slave DMA Request - Channels [3:0] 8bit WO Reads return value B2h.
00Ah Slave DMA Mask - Channels [3:0] 8bit Shw@ Reads return value B2h.
00Bh Slave DMA Mode - Channels [3:0] 8bit Shw@ Reads return value B2h.
00Ch Slave DMA Clear Pointer - Channels [3:0] 8bit WO Reads return value B2h.
00Dh Slave DMA Reset - Channels [3:0] 8bit WO Reads return value B2h.
00Eh Slave DMA Reset Mask - Channels [3:0] 8bit Shw@ Reads return value B2h.
00Fh Slave DMA General Mask - Channels [3:0] 8bit Shw@ Reads return value B2h.
010h-01Fh No specific usage --- ---
020h PIC Master - Command/Status 8bit Shw$
021h PIC Master - Command/Status 8bit Shw$
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MSM800BEV/ Detailed System Description
I/O Address Function Size R/W Comment
022h-03Fh No specific usage --- ---
040h PIT – System Timer 8bit Shw$
041h PIT – Refresh Timer 8bit Shw$
042h PIT – Speaker Timer 8bit Shw$
043h PIT – Control 8bit Shw$
044h-05Fh No specific usage --- ---
If KEL Memory Offset 100h[0] = 1
(Emulation-enabled bit).
060h Keyboard/Mouse - Data Port 8bit Yes
061h Port B Control 8bit Yes
062h-063h No specific usage --- ---
064h Keyboard/Mouse - Command/ Status 8bit Yes
065h-06Fh No specific usage --- ---
070h-071h RTC RAM Address/Data Port 8bit Yes Options per MSR 51400014h[0].
072h-073h High RTC RAM Address/Data Port 8bit Yes Options per MSR 51400014h[1].
074-077h No specific usage --- ---
078h-07Fh No specific usage --- ---
080h Post Code Display 8bit Rec Write LPC and DMA. Read only DMA.
081h DMA Channel 2 Low Page
082h DMA Channel 3 Low Page
8bit Rec
083h DMA Channel 1 Low Page
084h-086h No specific usage 8bit Rec Write LPC and DMA. Read only DMA.
087h DMA Channel 0 Low Page 8bit Rec
088h No specific usage 8bit Rec Write LPC and DMA. Read only DMA.
089h DMA Channel 6 Low Page
08Ah DMA Channel 7 Low Page
8bit Rec
08B DMA Channel 5 Low Page
08Ch-08Dh No specific usage 8bit Rec Write LPC and DMA. Read only
08Eh DMA
08Fh DMA C4 Low Page 8bit Rec
090h-091h No specific usage --- ---
092h Port A 8bit Yes
093h-09Fh No specific usage --- ---
0A0h PIC Slave - Command/Status 8bit Shw$
0A1h PIC Slave - Command/Status 8bit Shw$
0A2h-0BFh No specific usage 8bit ---
0C0h Master DMA Address - Channel 4 8bit Yes 16bit values in two transfers.
0C1h No specific usage 8bit ---
0C2h Master DMA Counter - Channel 4 8bit Yes 16bit values in two transfers.
0C3h No specific usage 8bit ---
0C4h Master DMA Address - Channel 5 8bit Yes 16bit values in two transfers.
0C6h Master DMA Counter - Channel 5 8bit Yes 16bit values in two transfers.
0C7h No specific usage 8bit ---
0C8h Master DMA Address - Channel 6 8bit Yes 16bit values in two transfers.
0CAh Master DMA Counter - Channel 6 8bit Yes 16bit values in two transfers.
0CBh No specific usage 8bit ---
0CCh Master DMA Address - Channel 7 8bit Yes 16bit values in two transfers.
If MSR 5140001Fh[0] = 1 (SNOOP bit) and
KEL Memory Offset 100h[0] = 0 (Emulationenabled bit).
If KEL Memory Offset 100h[0] = 1
(Emulation-enabled bit).
If MSR 5140001Fh[0] = 1 (SNOOP bit) and
KEL Memory Offset 100h[0] = 0 (Emulationenabled bit)
Upper addr bits [23:16]. Write LPC and DMA.
Read only DMA.
Upper addr bits [23:16]. Write LPC and DMA.
Read only DMA.
Upper addr bits [23:16]. Write LPC and DMA.
Read only DMA.
Upper addr bits [23:16]. See comment at
080h.
If kel_porta_en is enabled, then access Port
A; else access LPC.
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MSM800BEV/ Detailed System Description
I/O Address Function Size R/W Comment
0CDh No specific usage 8bit ---
0CEh Master DMA Counter - Channel 7 8bit Yes 16bit values in two transfers.
0CFh No specific usage 8bit ---
0D0h Master DMA Command/Status – Channels [7:4] 8bit Shw$
0D1h No specific usage 8bit ---
0D2h Master DMA Request - Channels [7:4] 8bit WO
0D3h No specific usage 8bit ---
0D4h Master DMA Mask - Channels [7:4] 8bit Yes
0D5h No specific usage 8bit ---
0D6h Master DMA Mode - Channels [7:4] 8bit Shw@
0D7h No specific usage 8bit ---
0D8h Master DMA Clear Pointer - Channels [7:4] 8bit WO
0D9h No specific usage 8bit ---
0DAh Master DMA Reset - Channels [7:4] 8bit WO
0DBh No specific usage 8bit ---
0DCh Master DMA Reset Mask - Channels [7:4] 8bit WO
0DDh No specific usage 8bit ---
0DEh Master DMA General Mask - Channels [7:4] 8bit Shw@
0DFh No specific usage 8bit ---
0E0h-2E7h No specific usage --- ---
MSR bit enables/disables into I/O 2EFh
2E8h-2EFh UART/IR - COM4 8bit ---
2F0h-2F7h No specific usage --- ---
2F8h-2FFh UART/IR - COM2 8bit ---
300h- 36Fh No specific usage --- ---
370h Floppy Status R A 8bit RO Second Floppy.
371h Floppy Status R B 8bit RO Second Floppy.
372h Floppy Digital Out 8bit Shw@ Second Floppy.
373h No specific usage 8bit ---
374h Floppy Cntrl Status 8bit RO Second Floppy.
375h Floppy Data 8bit Yes Second Floppy.
376h No specific usage 8bit ---
377h Floppy Conf Reg 8bit Shw$ Second Floppy.
378h-3E7h No specific usage --- ---
3E8h-3EFh UART/IR - COM3 8bit ---
3F0h Floppy Status R A 8bit RO First Floppy.
3F1h Floppy Status R B 8bit RO First Floppy.
3F2h Floppy Digital Out 8bit Shw@ First Floppy.
3F3h No specific usage 8bit ---
3F4h Floppy Cntrl Status 8bit RO First Floppy.
3F5h Floppy Data 8bit Yes First Floppy.
3F6h No specific usage 8bit ---
3F7h Floppy Conf Reg 8bit Shw$ First Floppy.
3F8h-3FFh UART/IR - COM1 8bit ---
480h No specific usage 8bit WO Write LPC and DMA. Read only DMA.
space. (UART1 MSR 51400014h[18:16],
UART2 MSR 51400014h[22:20]). Defaults to
LPC.
MSR bit enables/disables into I/O 2FFh
space. (UART1 MSR 51400014h[18:16],
UART2 MSR 51400014h[22:20]). Defaults to
LPC.
MSR bit enables/disables into I/O 3EFh
space. (UART1 MSR 51400014h[18:16],
UART2 MSR 51400014h[22:20]). Defaults to
LPC.
MSR bit enables/disables into I/O 3FFh
space. (UART1 MSR 51400014h[18:16],
UART2 MSR 51400014h[22:20]). Defaults to
LPC.
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MSM800BEV/ Detailed System Description
I/O Address Function Size R/W Comment
481h DMA Channel 2 High Page 8bit Rec
Upper addr bits [31:24]. Write LPC and DMA.
Read only DMA.
482h DMA Channel 3 High Page
483h DMA Channel 1 High Page
484h-486h No specific usage 8bit WO Write LPC and DMA. Read only DMA.
487h DMA Channel 0 High Page 8bit Rec
489h DMA Channel 6 High Page 8bit Rec
Upper addr bits [31:24]. Write LPC and DMA.
Read only DMA.
Upper addr bits [31:24]. Write LPC and DMA.
Read only DMA.
48Ah DMA Channel 7 High Page
48Bh DMA Channel 5 High Page
48Ch-48Eh No specific usage 8bit WO Write LPC and DMA. Read only DMA.
48Fh DMA Channel 4 High Page 8bit Rec
Upper addr bits [31:24]. Write LPC and DMA.
Read only DMA.
490h-4CFh No specific usage --- ---
4D0h PIC Level/Edge 8bit Yes IRQ0-IRQ 7.
4D1h PIC Level/Edge 8bit Yes IRQ8-IRQ15.
4D2h-4FFh No specific usage --- ---
070h-071h The Diverse Device Snoops writes to this port and maintains the MSB as NMI enabled. When low,
NMI is enabled. When high, NMI is disabled. This bit defaults high. Reads of this port return bits
[6:0] from the on-chip or off-chip target, while Bit 7 is returned from the "maintained" value.
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MSM800BEV/ System Resources
7 System Resources
7.1 Bus Signals
7.1.1 PC104 Bus
Note: Not all of the signals are available on this board (please see Chapter 5 for a description of the connectors).
AEN, output
Address Enable: used to degate the microprocessor and other devices from the I/O channel to allow DMA
transfers to take place. low = CPU Cycle, high = DMA Cycle
BALE, output
Address Latch Enable: provided by the bus controller and used on the system board to latch valid addresses
and memory decodes from the microprocessor. This signal is used so that devices on the bus can latch LA17-
23. The SA0-19 address lines latch internally according to this signal. BALE is forced high during DMA cycles.
/DACK[0-3, 5-7], output
DMA Acknowledge: 0 to 3 and 5 to 7 are used to acknowledge DMA requests (DRQ0 through DRQ7). They are
active low. This signal indicates that the DMA operation can begin.
DRQ[0-3, 5-7], input
DMA Requests: 0 through 3 and 5 through 7 are asynchronous channel requests used by peripheral devices and
the I/O channel microprocessors to gain DMA service (or control of the system). A request is generated by
bringing a DRQ line to an active level. A DRQ line must be held high until the corresponding DMA Request
Acknowledge (DACK/) line goes active. DRQ0 through DRQ3 will perform 8bit DMA transfers; DRQ5-7 are used
for 16 accesses.
/IOCHCK, input
IOCHCK/: provides the system board with parity (error) information about memory or devices on the I/O
channel. low = parity error, high = normal operation
IOCHRDY, input
I/O Channel Ready: pulled low (not ready) by a memory or I/O device to lengthen I/O or memory cycles. Any
slow device using this line should drive it low immediately upon detecting its valid address and a Read or Write
command. Machine cycles are extended by an integral number of one clock cycle (67 nanoseconds). This signal
should be held in the range of 125-15600nS. low = wait, high = normal operation
/IOCS16, input
I/O 16 Bit Chip Select: signals the system board that the present data transfer is a 16bit, 1 wait-state, I/O
cycle. It is derived from an address decode. /IOCS16 is active low and should be driven with an open collector
(300 ohm pull-up) or tri-state driver capable of sinking 20mA. The signal is driven based only on SA0-SA15
(not /IOR or /IOW) when AEN is not asserted. In the 8bit I/O transfer, the default transfers a 4 wait-state cycle.
/IOR, input/output
I/O Read: instructs an I/O device to drive its data onto the data bus. It may be driven by the system
microprocessor or DMA controller, or by a microprocessor or DMA controller resident on the I/O channel. This
signal is active low.
/IOW, input/output
I/O Write: instructs an I/O device to read the data on the data bus. It may be driven by any microprocessor or
DMA controller in the system. This signal is active low.
IRQ [3-7, 9-12, 14, 15], input
These signals are used to tell the microprocessor that an I/O device needs attention. An interrupt request is
generated when an IRQ line is raised from low to high. The line must be held high until the microprocessor
acknowledges the interrupt request.
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MSM800BEV/ System Resources
/Master, input
This signal is used with a DRQ line to gain control of the system. A processor or DMA controller on the I/O
channel may issue a DRQ to a DMA channel in cascade mode and receive a /DACK.
/MEMCS16, input
MEMCS16 Chip Select: signals the system board if the present data transfer is a 1 wait-state, 16bit, memory
cycle. It must be derived from the decode of LA17 through LA23. /MEMCS16 should be driven with an open
collector (300 Ohm pull-up) or tri-state driver capable of sinking 20mA.
/MEMR, input/output
These signals instruct the memory devices to drive data onto the data bus. /MEMR is active on all memory read
cycles. /MEMR may be driven by any microprocessor or DMA controller in the system. When a microprocessor
on the I/O channel wishes to drive /MEMR, it must have the address lines valid on the bus for one system clock
period before driving /MEMR active. These signals are active low.
/MEMW, input/output
These signals instruct the memory devices to store the data present on the data bus. /MEMW is active in all
memory read cycles. /MEMW may be driven by any microprocessor or DMA controller in the system. When a
microprocessor on the I/O channel wishes to drive /MEMW, it must have the address lines valid on the bus for
one system clock period before driving /MEMW active. Both signals are active low.
OSC, output
Oscillator (OSC): a high-speed clock with a 70 nanosecond period (14.31818 MHz). This signal is not
synchronous with the system clock. It has a 50% duty cycle. OSC starts 100µs after reset is inactive.
RESETDRV, output
Reset Drive: used to reset or initiate system logic at power-up time or during a low line-voltage outage. This
signal is active high. When the signal is active all adapters should turn off or tri-state all drivers connected to
the I/O channel. This signal is driven by the permanent Master.
/REFRESH, input/output
These signals are used to indicate a refresh cycle and can be driven by a microprocessor on the I/O channel.
These signals are active low.
SA0-SA19, LA17-LA23 input/output
Address bits 0 through 19 are used to address memory and I/O devices within the system. These 20 address
lines allow access of up to 1MByte of memory. SA0 through SA19 are gated on the system bus when BALE is
high and are latched on the falling edge of BALE. LA17 to LA23 are not latched and addresses the full 16MByte
range. These signals are generated by the microprocessors or DMA controllers. They may also be driven by
other microprocessor or DMA controllers that reside on the I/O channel. The SA17-SA23 are always LA17-LA23
address timings for use with the MSCS16 signal. This is advanced AT96 design. The timing is selectable with
jumpers LAxx or SAxx.
/SBHE, input/output
Bus High Enable (system): indicates a transfer of data on the upper byte of the data bus, XD8 through XD15.
Sixteen-bit devices use /SBHE to condition data-bus buffers tied to XD8 through XD15.
SD[0-15], input/output
These signals provide bus bits 0 through 15 for the microprocessor, memory, and I/O devices. D0 is the least
significant bit and D15 is the most significant bit. All 8bit devices on the I/O channel should use D0 through D7
for communications to the microprocessor. The 16bit devices will use D0 through D15. To support 8bit devices,
the data on D8 through D15 will be gated to D0 through D7 during 8bit transfers to these devices; 16bit
microprocessor transfers to 8bit devices will be converted to two 8bit transfers.
/SMEMR, input/output
These signals instruct the memory devices to drive data onto the data bus for the first MByte. /SMEMR is active
on all memory read cycles. /SMEMR may be driven by any microprocessor or DMA controller in the system.
When a microprocessor on the I/O channel wishes to drive /SMEMR, it must have the address lines valid on the
bus for one system clock period before driving /SMEMR active. The signal is active low.
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MSM800BEV/ System Resources
/SMEMW, input/output
These signals instruct the memory devices to store the data present on the data bus for the first MByte.
/SMEMW is active in all memory read cycles. /SMEMW may be driven by any microprocessor or DMA controller in
the system. When a microprocessor on the I/O channel wishes to drive /SMEMW, it must have the address lines
valid on the bus for one system clock period before driving /SMEMW active. Both signals are active low.
SYSCLK, output
This is an 8MHz system clock. It is a synchronous microprocessor cycle clock with a cycle time of 167
nanoseconds. The clock has a 66% duty cycle. This signal should only be used for synchronization.
TC, output
Terminal Count: provides a pulse when the terminal count for any DMA channel is reached. The TC completes a
DMA-Transfer. This signal is expected by the onboard floppy disk controller. Do not use this signal because it is
internally connected to the floppy controller.
/0WS, input
The Zero Wait State (/0WS) signal tells the microprocessor that it can complete the present bus cycle without
inserting any additional wait cycles. In order to run a memory cycle to a 16bit device without wait cycles, /0WS
is derived from an address decode gated with a Read or Write command. In order to run a memory cycle to an
8bit device with a minimum of one-wait states, /0WS should be driven active one system clock after the Read
or Write command is active, gated with the address decode for the device. Memory Read and Write commands
to an 8bit device are active on the falling edge of the system clock. /0WS is active low and should be driven
with an open collector or tri-state driver capable of sinking 20mA.
12V, +/- 5%
This signal is used only for the flat panel supply.
GROUND = 0V
This is used for the entire system.
VCC, +5V +/- 0.25V
This signal is used to supply other PC/104 peripheral cards. Maximum current is 2Amp.
7.1.2 PC104+ Bus
AD[31:00]
Address and Data are multiplexed. A bus transaction consists of an address cycle followed by one or more data
cycles.
C/BE[3:0]*
Bus Command/Byte Enables are multiplexed. During the address cycle, the command is defined. During the
Data cycle, they define the byte enables.
PAR
Parity is even on AD[31:00] and C/BE[3:0]* and is required.
FRAME*
Frame is driven by the current master to indicate the start of a transaction and will remain active until the final
data cycle.
TRDY*
IRDY*
STOP*
Target Ready indicates the selected device’s ability to complete the current data cycle of the traansaction.
Both IRDY* and TRDY* must be asserted to terminate a data cycle.
Initiator Ready indicates the master’s ability to complete the current data cycle of the transaction.
Stop indicates the current selected device is requesting the master to stop the current transaction.
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DEVSEL*
Device Select is driven by the target device when its address is decoded.
IDSEL
Initialization Device Select is used as a chip-select during configuration.
LOCK*
Lock indicates an operation that may require multiple transactions to complete.
PERR*
Parity Error is for reporting data parity errors.
SERR*
System Error is for reporting address parity errors.
REQ*
Request indicates to the arbitrator that this device desires use of the bus.
GNT*
Grant indicates to the requesting device that access has been granted.
MSM800BEV/ System Resources
CLK
Clock provides timing for all transactions opn the PCI bus.
RST*
Reset is used to bring PCI-specific registers to a known state.
INTA*
Interrupt A is used to request Interrupts.
INTB*
Interrupt B is used to request Interrupts only for multi-function devices.
INTC*
Interrupt C is used to request Interrupts only for multi-function devices.
INTD*
Interrupt D is used to request Interrupts only for multi-function devices.
7.1.3 Expansion Bus
The bus currents are as follows:
Output Signals IOH IOL
D0-D16 8 mA 8 mA
A0-A23 8 mA 8 mA
MR, MW, IOR, IOW, RES, ALE, AEN, C14 8 mA 8 mA
DACKx, DRQx, INTx, PSx, OPW 8 mA 8 mA
Input Signals Logic Family Voltage
ABT-Logic
ViH (min.) = 2.15 V
ABT-Logic
Vil (max.) = 0.85 V
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MSM800BEV/ System Resources
7.1.4 Addressing PCI Devices
MSM800BEV
(4 PCI slots available)
DEVICE IDSEL PIRQ #REG #GNT Remarks
SLOT 1 AD20 A / B / C / D 3 3 For additional cards (peripheral boards)
SLOT 2 AD21 B / C / D / A 4 4 For additional cards (peripheral boards)
SLOT 3 AD22 C / D / A / B 5 5 For additional cards (peripheral boards)
SLOT 4 AD23 D / A / B / C 6 6 For additional cards (peripheral boards)
LAN AD29 A 7 7 Onboard devices
PCI-ISA-Bridge AD24 8 8
The FP connects to the RGB port of the video mixer.
LCD Interface:
The FP interfaces directly to industry standard 18 or 24bit active matrix thin-film-transistor (TFT).
The digital RGB or video data that is supplied by the video logic is converted into a suitable format to drive a
wide variety range of panels with variable bits.
The LCD interface includes dithering logic to increase the apparent number of colors displayed for use on
panels with less than 6bits per color. The LCD interface also supports automatic power sequence off panel
power supplies.
Mode Selection:
The FP can be configured for operation with most standard TFT panels in the BIOS setup:
» Supports TFT panels with 18 or 24bit interface with 320x240, 640x480, 800x600, 1024x768, 1280x1024,
and 1600x1200 pixel resolutions. Either one or two pixels per clock is supported for all resolutions.
» For TFT panel support, the output from the dither block is directly fed onto the panel data pins (DRGBx).
The data that is being sent onto the panel data pins is in sync with the TFT timing signals such as HSYNC,
VSYNC, and LDE.
» One pixel (or two pixels in 2pix/clk mode) is shifted on every positive edge of the clock as long as
DISP_ENA is active.
Enter the BIOS with F1
» Select C (Motherboard Device Configuration)
» Select F (Video and Flat Panel Configuration
» Output Display = Flat Panel
o Flat Panel Configuration
TYPE = TFT
•Resolution = 320x240, 640x480, 800x600, 1024x768, 1280x1024, or 1600x1200 pixel
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MSM800BEV/ System Resources
c d
7.3 Cable Interfaces
7.3.1 The Hard Disk Cable 44pin
IDT Terminal for Dual Row (2.00mm grid) and 1.00mm flat cable; 44pins = 40pins signal and 4pins power.
11 2
2
3939
4040
43434444
Maximum length for the IDE cable is 30cm.
Attention: Check the Pin1 marking on the cable and the connector before powering-on. Refer to the technical
manual of the installed drives because a wrong cable will immediately destroy the drive and/or the
MICROSPACE MSM800 board. In this case the warranty is void! Without the technical manual you may
not connect this type of drive.
The 44pin IDE connector on the drives is normally composed of the 44 pins, 2 open pins and 4 test pins,
50 pins in total. Leave the 4 test pins unconnected.
1343a b
Testpin
open pin
44pin IDE Interface with integrated power lines
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7.3.2 The COM 1/2 Serial Cable
DT terminal for dual row 0.1" (2.54 mm grid) and 1.27 mm flat cable.
MSM800BEV/ System Resources
Line of pin 1
2 1
COM1/2
Attention: Do not short circuit these signal lines.
Never connect any pins on the same plug or to any other plug on the MICROSPACE MSM800. The +/10Volts will destroy the MICROSPACE core logic immediately. In this case the warranty is void!
Do not overload the output; the maximum output current converters: 10mA
9 10
7.3.3 The Printer Cable
IDT terminal for dual row 0.1" (2.54mm grid) and 1.27 mm flat cable
1
6
2
7
3
8
COM1
9pin D-Sub
male
4
9
5
Parallelport Cable LPT1
Attention: Maximum length of this cable is 6 meters.
Prevent short-circuits.
Never apply power to these signals, the MICROSPACE MSM800 will be destroyed.
1
14
2
15
24
12
25
13
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7.3.4 The Micro-Floppy Cable
MSM800BEV/ System Resources
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MSM800BEV/ System Resources
7.3.5 The LAN Cable (RJ45)
Attention: Early board versions use the MSM855-LANCON. Later versions must use the MSM800-LANCON, because
the LAN transformer (pulse) is integrated on the MSM800 product. See below for the version numbers.
Use the MSM800-LANCON starting with the
following versions:
The temperature is specified by 90°C for the BGA case. The table shows the allowable ambient temperature at various
airflows and with different heat sink configurations.
CPU: LX800 / T (case) = 90°C / Power consumption: 5W
Photo of heat sink
Part Nr.
Heat sink type
No
heat sink
Small
807041
Large
807042
Product
All
MSM800s
All
MSM800s
BEV 500 85°C
XEV
XEL
CPU
[MHz]
MSM800…
Frequency
Air Temperature
500 60°C 90°C
500 70°C 100°C 90°C 80°C
500 85°C
T case:
(ambient)
T case:
0m/sec
No Airflow
Airflow
3m/sec
T case:
Airflow
6m/sec
Thermojunction
(see Notes
807043
below)
BEV
XEV
XEL
500 85°C - - -
500 85°C - - -
Two PC104 mounting holes are used for the large cooler.
The thermojunction has been specifically designed by KCC to have 2 almost separate parts to provide distinct
heat dissipation for the CPU and the other onboard chips. The holes in the thermojunction are for ø2mm screws. The
holes in the casing/housing that will be attached to the thermojunction should be ø2.5 or 3mm.
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MSM800BEV/ Design Considerations
Cooling Option Assembly Example on an MSM800BEV
Part-Nr. 807041
Screening E47 (-25°C to 70°C)
Heat sink, small (35x37.5x6mm)
Available on all MSM800 models
Part-Nr. 807042
Screening E48 (-40°C to +85°C)
Heat sink, large (79x79.5x8.5mm)
Available on MSM800BEV/XEV/XEL models
Not possible with MSM800SEV/SEL
Part-Nr. 807043
Screening E48 (-40°C to +85°C)
Thermojunction (64x50x13mm)
Available on MSM800BEV/XEV/XEL models
Not possible with MSM800SEV/SEL
Two PC104 mounting holes are used for the large cooler.
The thermojunction has been specifically designed by KCC to have 2 almost separate parts to provide distinct
heat dissipation for the CPU and the other onboard chips. The holes in the thermojunction are for ø2mm screws. The
holes in the casing/housing that will be attached to the thermojunction should be ø2.5 or 3mm.
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MSM800BEV/ BIOS
9 BIOS
9.1 BIOS History
Please consult the BIOS/Driver/Software manual "Geode LX800-LX900" for a detailed BIOS history.
9.2 Core BIOS Download
9.2.1 Before downloading a BIOS
Please read through this section carefully and prepare for the download.
Make a bootable diskette which includes the following files:
Flashrom.com
core BIOS xxxxxxxx.yyy
Attention: Do not use boot disks created in a Windows operating system. If you do not have an MSDOS 6.22 disk
available, you can download a boot disk from www.bootdisk.com.
Note:
» Select the SHADOW option in the BIOS, for a BIOS and VGA (if this option is available).
» Disable the EMM386 or other memory managers in the CONFIG.SYS of your boot disk.
» Make sure that the Flashrom.com program and the BIOS to download are on the same path and directory!
» Boot the DOS without config.sys and autoexec.bat press F5 while starting the DOS boot.
» Check, where the Flashrom.com is located, that the available disk space is larger than 64kB (for safe storage).
» Make sure the floppy disk is not write-protected.
9.2.2 Start the download
1. Start the system with the bootable diskette. If you do not have a bootable diskette or floppy drive, you can
start in DOS mode by pressing the F5 key to disable autoexec.bat and config.sys.
2. Run Flashrom.com.
(In some cases you have to try the following: FLASHROM /D /sFFFC0000 biosname.xxx)
3. Power off the system.
After powering on the system, press F1 to enter setup and set the default values; then “save and leave” the
setup.
4. Switch off the system after the download is finished.
9.2.3 If the download does not work
» Check, if the EMM386 is not loaded.
» Check if there is a peripheral card in the system, which would occupy the same memory range. If one is
present, disconnect it.
» If the download stopped or did not finish, make a warm boot* and repeat the steps or download another file.
(* As the video is shadowed, everything is visible and a cold boot would clear the screen so nothing would be
visible afterwards.)
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MSM800BEV/ BIOS
Attention! Never update a BIOS with a USB memory stick! The system will crash during the download!
Only use a USB or a standard floppy.
Also, if you have two IDE devices attached to the board (e.g., HDD and CD-ROM), disconnect the CD-ROM before
downloading the BIOS.
9.3 ROM-BIOS Sockets
An EPROM socket with 8bit wide data access normally contains the board's AT compatible ROM-BIOS. The socket takes
a 29F020 EPROM (or equivalent) device. The board's wait-state control logic automatically inserts four memory wait
states in all CPU accesses to this socket. The ROM-BIOS sockets occupy the memory area from C0000H through FFFFFh;
however, the board's ASIC logic reserves the entire area from C0000h through FFFFFh for onboard devices, so that this
area is already usable for ROM-DOS and BIOS expansion modules. Consult the appropriate address map for the
MICROSPACE PC-Product ROM-BIOS sockets.
9.3.1 Standard BIOS ROM
Device FWH
E0000 - FFFFFh Core BIOS 128k
Map
C0000 - C7FFFh VGA BIOS 32k
CC000 - CFFFFh FREE
9.4 BIOS CMOS Setup
If wrong setups are memorized in the CMOS-RAM, the default values will be loaded after resetting the RTC/CMOS-RAM
by de-soldering the battery.
If the battery is down, it is always possible to start the system with the default values from the BIOS.
Note: For the MSM800BEV/XEV/XEL: Should the product have an inaccurate BIOS setup and won't boot up,
proceed as follows. (The installed BIOS must be V1.20 or newer.)
1. Set J7
2. Turn the power on
3. Press F1 to enter the BIOS setup
4. Select "L" to load the BIOS default settings
5. Remove J7
6. Select "X" to save and exit the BIOS setup
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10 Previous Product Versions
10.1 Board Dimensions – Versions 1.0 / 1.1 / 1.2
MSM800BEV/ Previous Product Versions
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10.2 Assembly Views
10.2.1 Top Side of the MSM800BEV V1.1
MSM800BEV/ Previous Product Versions
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10.2.2 Bottom Side of the MSM800BEV V1.1
MSM800BEV/ Previous Product Versions
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MSM800BEV/ Previous Product Versions
10.3 Connectors and Jumpers of Previous Product Versions
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MSM800BEV/ Previous Product Versions
10.3.1 Description of the Connectors for V1.0 /V1.1 /V1.2
Flat cable
44pin IDE is: IDT Terminal for Dual Row (2.00mm grid) and 1.00mm flat cable
All others are: IDT Terminal for Dual Row 0.1" (2.54mm grid) and 1.27mm flat cable
NC: not connected
You must enable the UART A of the GeodeLX in the BIOS setup:
» F1Mother board device configurationI/O configuration:
» UART port A = enabled
» UART mode = SIR/CIR
Warning: Never set the UART A mode to "Serial-16550 compatible" or "Extended" when an IrDA diode is connected
to the J12 or the diode will be destroyed!
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J13 Printer Port (Centronics)
The printer connector provides an interface for 8bit Centronics printers.
Header onboard D-SUB connector Signal
Pin 1 Pin 1 Strobe
Pin 3 Pin 2 Data 0
Pin 5 Pin 3 Data 1
Pin 7 Pin 4 Data 2
Pin 9 Pin 5 Data 3
Pin 11 Pin 6 Data 4
Pin 13 Pin 7 Data 5
Pin 15 Pin 8 Data 6
Pin 17 Pin 9 Data 7
Pin 19 Pin 10 Acknowledge
Pin 21 Pin 11 Busy
Pin 23 Pin 12 Paper end
Pin 25 Pin 13 Select
Pin 2 Pin 14 Autofeed
Pin 4 Pin 15 Error
Pin 6 Pin 16 Init printer
Pin 8 Pin 17 Shift in (SI)
Pins 10, 12, 14, 16, 18 Pin 18-22 Left open
Pins 20, 22, 24 Pin 23-25 GND
MSM800BEV/ Previous Product Versions
J14 Floppy Disk Interface Connector
FD26 Signal Name Function in/out
Pin 1 VCC +5Volt
Pin 2 IDX Index Pulse in
Pin 3 VCC +5Volt
Pin 4 DS2 Drive Select 2 out
Pin 5 VCC +5Volt
Pin 6 DCHG Disk Change in
Pin 10 M02 Motor On 2 out
Pin 12 DIRC Direction Select out
Pin 14 STEP Step out
Pin 16 WD Write Data out
Pin 17 GND Signal grounds
Pin 18 WE Write Enable out
Pin 19 GND Signal grounds
Pin 20 TRKO Track 0 in
Pin 21 GND Signal grounds
Pin 22 WP Write Protect in
Pin 23 GND Signal grounds
Pin 24 RDD Read Data in
Pin 25 GND Signal grounds
Pin 26 HS Head Select out
The KEY pins are to guarantee proper module installation. PinA1 will be removed and the female side plugged
for 5.0V I/O signals and PinD30 will be modified in the same manner for 3.3V I/O. It is recommended that both KEY
pins (A1 and D30) be electrically connected to GND for shielding.
KCC boards have them as NC (not connected).
1 FPM (out) LDE LDE
2 CRT-Vert.Synch VSYNC VSYNC
3 Enable BKL (TTL out)
4 CRT-Horiz.Synch HSYNC HSYNC
5 VCC 3.3V
6 Ground
7 NC
8 Shift Clock CKL CKL
9 Enable VDD (TTL out) ENLVDD ENLVDD
10 FP0 Blue 0
11 FP1 Blue 1
12 FP2 Blue 0 Blue 2
13 FP3 Blue 1 Blue 3
14 FP4 Blue 2 Blue 4
15 FP5 Blue 3 Blue 5
16 FP6 Blue 4 Blue 6
17 FP7 Blue 5 Blue 7
18 FP8 Green 0
19 FP9 Green 1
20 FP10 Green 0 Green 2
21 FP11 Green 1 Green 3
22 FP12 Green 2 Green 4
23 FP13 Green 3 Green 5
24 FP14 Green 4 Green 6
25 FP15 Green 5 Green 7
26 Ground
27 FP16 Red 0
28 FP17 Red 1
29 FP18 Red 0 Red 2
30 FP19 Red 1 Red 3
31 FP20 Red 2 Red 4
32 FP21 Red 3 Red 5
33 FP22 Red 4 Red 6
34 FP23 Red 5 Red 7
35 NC
36 NC
37 NC
38 NC
39 NC
40 NC
41 Ground
42 NC
43 +5Volt Output
44 +12Volt Output
MSM800BEV/ Previous Product Versions
www.kontron.com 92
MSM800BEV/ Appendix A: Architecture Information
11 Appendix A: Architecture Information
The following sources of information can help you better understand PC architecture.
11.1 Buses
11.1.1 ISA, Standard PS/2 – Connectors
» AT Bus Design: Eight and Sixteen-Bit ISA, E-ISA and EISA Design, Edward Solari, Annabooks, 1990, ISBN 0-
929392-08-6
» AT IBM Technical Reference, Volumes 1&2, 1985
» ISA & EISA Theory and Operation, Edward Solari, Annabooks, 1992, ISBN 0929392159
» ISA Bus Specifications and Application Notes, Jan. 30, 1990, Intel
» ISA System Architecture, Third Edition, Tom Shanley and Don Anderson, Addison-Wesley Publishing
Company, 1995, ISBN 0-201-40996-8
» Personal Computer Bus Standard P996, Draft D2.00, Jan. 18, 1990, IEEE Inc
» Technical Reference Guide, Extended Industry Standard Architecture Expansion Bus, Compaq 1989
11.1.2 PCI/104
» Embedded PC 104 Consortium
» The consortium provides information about PC/104 and PC/104-Plus technology. You can search for
information about the consortium on the Web.
» PCI SIG
» The PCI-SIG provides a forum for its ~900 member companies, who develop PCI products based on the
specifications that are created by the PCI-SIG. You can search for information about the SIG on the Web.
» PCI & PCI-X Hardware and Software Architecture & Design, Fifth Edition, Edward Solari and George Willse,
Annabooks, 2001, ISBN 0-929392-63-9.
» PCI System Architecture, Tom Shanley and Don Anderson, Addison-Wesley, 2000, ISBN 0-201-30974-2.
11.2 General PC Architecture
» Embedded PCs, Markt&Technik GmbH, ISBN 3-8272-5314-4 (German)
» Hardware Bible, Winn L. Rosch, SAMS, 1997, 0-672-30954-8
» Interfacing to the IBM Personal Computer, Second Edition, Lewis C. Eggebrecht, SAMS, 1990, ISBN 0-672-
22722-3
» The Indispensable PC Hardware Book, Hans-Peter Messmer, Addison-Wesley, 1994, ISBN 0-201-62424-9
» The PC Handbook: For Engineers, Programmers, and Other Serious PC Users, Sixth Edition, John P. Choisser
and John O. Foster, Annabooks, 1997, ISBN 0-929392-36-1
www.kontron.com 93
MSM800BEV/ Appendix A: Architecture Information
11.3 Ports
11.3.1 RS-232 Serial
» EIA232E standard
» The EIA-232-E standard specifies the interface between (for example) a modem and a computer so that they
can exchange data. The computer can then send data to the modem, which then sends the data over a
telephone line. The data that the modem receives from the telephone line can then be sent to the computer.
You can search for information about the standard on the Web.
» RS-232 Made Easy: Connecting Computers, Printers, Terminals, and Modems, Martin D. Seyer, Prentice Hall,
1991, ISBN 0-13-749854-3
» National Semiconductor: The Interface Data Book includes application notes. Type “232” as search criteria to
obtain a list of application notes. You can search for information about the data book on National
Semiconductor’s Web site.
11.3.2 Serial ATA
Serial AT Attachment (ATA) Working Group. This X3T10 standard defines an integrated bus interface between disk
drives and host processors. It provides a common point of attachment for systems manufacturers and the system. You
can search for information about the working group on the Web. We recommend you also search the Web for
information on 4.2 I/O cables, if you use hard disks in a DMA3 or PIO4 mode.
11.3.3 USB
USB Specification
USB Implementers Forum, Inc. is a non-profit corporation founded by the group of companies that developed the
Universal Serial Bus specification. The USB-IF was formed to provide a support organization and forum for the
advancement and adoption of Universal Serial Bus technology. You can search for information about the standard on
the Web.
11.4 Programming
» C Programmer’s Guide to Serial Communications, Second Edition, Joe Campbell, SAMS, 1987, ISBN 0-672-
22584-0
» Programmer’s Guide to the EGA, VGA, and Super VGA Cards, Third Edition, Richard Ferraro, Addison-Wesley,
1990, ISBN 0-201-57025-4
» The Programmer’s PC Sourcebook, Second Edition, Thom Hogan, Microsoft Press, 1991, ISBN 1-55615-321-X
» Undocumented PC, A Programmer’s Guide to I/O, CPUs, and Fixed Memory Areas, Frank van Gilluwe, Second
Edition, Addison-Wesley, 1997, ISBN 0-201-47950-8
www.kontron.com 94
MSM800BEV/ Appendix B: Document Revision History
12 Appendix B: Document Revision History
Revision Date Edited by Changes
100 2.Sep.2010 WAS/MEG
Changed to new Kontron Corporate Design from DLAG Condensed V1.5C & Detailed V1.7A
including title photo; separate manual for each type of MSM800.