If it’s embedded, it’s Kontron.
KTUS15/mITX Users Guide
KTD-00774-G
KTD-00774-G KTUS15/mITX Page 2 of 84
Revision
Date
By
Comment
G
Feb. 17th 2014
MLA
Misspell correction. Updated chapter 3.6.1 Power Budget.
Chapter 4.12.1. USB0/2 swapped and USB4/5 swapped. Status LED info
correction.
Minor correction (using PCI Graphics card). Note for TPM BIOS setting.
boot order”.
RAID info corrected. Info on max video memory added. Wake on USB
connector pin 4 corrected to PSUP_OFF signal.
C
Oct. 13th 2009
MLA
Added “mounting the board to chassis”. Minor changes.
B
Sep. 22nd 2009
MLA
Added SDRAM PN available. Minor changes. Improved drawings.
A
Jun. 19th 2009
MLA
First complete version
0
May 27th 2009
MLA
Initial release
Document revision history.
F Feb. 13th 2012 MLA
E Nov. 10th 2010 MLA
D Jan. 12th 2010 MLA
Added note for Headless Mode. Added Status LED info. EXT_ISAIRQ#
corrected to NC. Added BIOS settings: “Remote Access” and “Default init
support corrected. PWR_OK on Feature connector corrected to
POWER_UP and related info corrected. Added OS support. Feature
Copyright Notice:
Copyright 2007, KONTRON Technology A/S, ALL RIGHTS RESERVED.
No part of this document may be reproduced or transmitted in any form or by any means, electronically or
mechanically, for any purpose, without the express written permission of KONTRON Technology A/S.
Trademark Acknowledgement:
Brand and product names are trademarks or registered trademarks of their respective owners.
Disclaimer:
KONTRON Technology A/S reserves the right to make changes, without notice, to any product, including
circuits and/or software described or contained in this manual in order to improve design and/or
performance.
Specifications listed in this manual are subject to change without notice. KONTRON Technology assumes no
responsibility or liability for the use of the described product(s), conveys no license or title under any patent,
copyright, or mask work rights to these products, and makes no representations or warranties that these
products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Applications that are described in this manual are for illustration purposes only. KONTRON Technology A/S
makes no representation or warranty that such application will be suitable for the specified use without
further testing or modification.
KTD-00774-G KTUS15/mITX Page 3 of 84
Life Support Policy
KONTRON Technology’s PRODUCTS ARE NOT FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL OF THE GENERAL
MANAGER OF KONTRON Technology A/S.
As used herein:
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
body, or (b) support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labelling, can be reasonably expected to result in significant injury to the
user.
A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
KONTRON Technology Technical Support and Services
If you have questions about installing or using your KONTRON Technology Product, check this User’s
Manual first – you will find answers to most questions here. To obtain support, please contact your local
Distributor or Field Application Engineer (FAE).
Before Contacting Support: Please be prepared to provide as much information as possible:
1. CPU Board
1. Type.
2. Part Number (find PN on label)
3. Serial Number if available (find SN on label)
2. Configuration
1. DRAM Type and Size.
2. BIOS Revision (Find the Version Info in the BIOS Setup).
3. BIOS Settings different than Default Settings (Refer to the BIOS Setup Section).
3. System
1. O/S Make and Version.
2. Driver Version numbers (Graphics, Network, and Audio).
3. Attached Hardware: Harddisks, CD-rom, LCD Panels etc.
KTD-00774-G KTUS15/mITX Page 4 of 84
» Table of Contents «
1 Introduction ...................................................................................... 7
2 Installation procedure ...................................................................... 8
2.1 Installing the board ........................................................................................................................ 8
2.2 Requirement according to EN60950 ............................................................................................. 9
3 System specification ...................................................................... 10
3.1 Component main data ................................................................................................................. 10
3.2 System overview ......................................................................................................................... 13
3.3 KTUS15/mITX Board configurations ........................................................................................... 14
3.4 System Memory support ............................................................................................................. 15
3.5 KTUS15 Graphics Subsystem .................................................................................................... 16
3.5.1 Intel® Graphics Media Accelerator 500 ..................................................................................... 16
3.5.2 Dual Independent/Mirror/Single Display support ....................................................................... 17
3.6 KTUS15 Power ........................................................................................................................... 18
3.6.1 Power Budget ............................................................................................................................ 18
3.6.2 Power Consumption .................................................................................................................. 18
3.7 KTUS15 Clock Distribution ......................................................................................................... 19
4 Connector Definitions .................................................................... 20
4.1 Connector layout ......................................................................................................................... 21
4.1.1 KTUS15/mITX – Top side .......................................................................................................... 21
4.1.2 KTUS15/mITX - IO Bracket side ................................................................................................ 22
4.1.3 KTUS15/mITX – Back side ........................................................................................................ 22
4.2 Power Connector (PWR) ............................................................................................................ 23
4.3 Power Out Connector (PWR-OUT) ............................................................................................. 24
4.4 Keyboard and Mouse connectors ............................................................................................... 25
4.4.1 MINI-DIN Keyboard and Mouse Connector (KBD) .................................................................... 25
4.4.2 Keyboard and Mouse pinrow Connector (KBDMSE) ................................................................ 25
4.5 Display connector ........................................................................................................................ 26
4.5.1 DVI Connector (DVI-A), Analogue output .................................................................................. 26
4.5.2 DVI Connector (DVI-D), Digital output ....................................................................................... 27
4.5.3 LVDS Flat Panel Connector (LVDS) .......................................................................................... 28
4.6 PCI-Express connectors ............................................................................................................. 29
4.6.1 PCI-Express x1 Connector (PCIe x1 Slot 1 and Slot 2) ............................................................ 29
KTD-00774-G KTUS15/mITX Page 5 of 84
4.7 Serial ATA Hard Disk interface ................................................................................................... 30
4.7.1 SATA Hard Disk Connector (SATA0, SATA1) ........................................................................... 30
4.8 Parallel ATA Hard Disk interface ................................................................................................ 31
4.8.1 IDE Hard Disk Connector (PATA).............................................................................................. 32
4.8.2 Compact Flash Connector (CF) ................................................................................................. 33
4.9 Printer Port Connector (PRINTER) ............................................................................................. 34
4.10 Serial Ports .................................................................................................................................. 35
4.10.1 COM1, COM2, COM3 and COM4 Pin Header Connectors ...................................................... 35
4.11 Ethernet Connectors ................................................................................................................... 36
4.11.1 Ethernet Connector (LAN) ......................................................................................................... 36
4.12 USB Connectors (USB) .............................................................................................................. 37
4.12.1 USB Connector 0/2 (USB0/2) .................................................................................................... 38
4.12.2 USB Connector 4/5 (USB4/5) .................................................................................................... 38
4.12.3 USB Connector 6/7 (USB6/7) .................................................................................................... 39
4.13 Audio Connectors ........................................................................................................................ 40
4.13.1 Audio Line-In, Line-Out and Microphone ................................................................................... 40
4.13.2 CDROM Audio Input (CDROM) ................................................................................................. 40
4.13.3 Audio Header (AUDIO_HEAD) .................................................................................................. 41
4.14 Fan Connector (FAN_CPU) ........................................................................................................ 42
4.15 Boot ROM Selection Jumper (BOOT ROM) ............................................................................... 43
4.16 Clear CMOS Jumper (Clr-CMOS) ............................................................................................... 43
4.17 TPM Connector (TPM) ................................................................................................................ 44
4.18 Front Panel Connector (FRONTPNL) ......................................................................................... 45
4.19 Feature Connector (FEATURE) .................................................................................................. 46
4.20 PCI Slot Connector (PCI Slot) ..................................................................................................... 47
4.20.1 Signal Description – PCI Slot Connector ................................................................................... 48
4.20.2 KTUS15 PCI IRQ & INT routing ................................................................................................ 49
5 Onboard connectors and Mating connectors ................................. 50
6 System Resources ........................................................................ 51
6.1 Memory Map ............................................................................................................................... 51
6.2 PCI Devices ................................................................................................................................ 52
6.3 Interrupt Usage ........................................................................................................................... 53
6.4 IO Map ........................................................................................................................................ 54
Overview of BIOS Features .................................................................. 55
KTD-00774-G KTUS15/mITX Page 6 of 84
6.5 System Management BIOS (SMBIOS/DMI) ............................................................................... 55
6.6 Legacy USB Support................................................................................................................... 55
7 BIOS Configuration/Setup ............................................................. 56
7.1 Introduction ................................................................................................................................. 56
7.2 Main Menu .................................................................................................................................. 56
7.3 Advanced Menu .......................................................................................................................... 57
7.3.1 Advanced settings – CPU Configuration ................................................................................... 58
7.3.2 Advanced settings – IDE Configuration ..................................................................................... 59
7.3.3 Advanced settings – LAN Configuration .................................................................................... 61
7.3.4 Advanced settings – Configure Win627DHG Super IO Chipset................................................ 62
7.3.5 Advanced settings – Hardware Health Configuration ................................................................ 64
7.3.6 Advanced settings – Voltage Monitor ........................................................................................ 65
7.3.7 Advanced settings – ACPI Settings ........................................................................................... 66
7.3.8 Advanced settings – PCI Express Configuration ....................................................................... 67
7.3.9 Advanced settings – Smbios Configuration ............................................................................... 67
7.3.10 Advanced settings – Remote Access Configuration ................................................................. 68
7.3.11 Advanced settings – Trusted Support ....................................................................................... 69
7.3.12 Advanced settings – USB Configuration ................................................................................... 70
7.3.13 Advanced settings – USB Mass Storage Device Configuration ................................................ 71
7.3.14 Advanced settings – Spread Spectrum Clock ........................................................................... 71
7.4 PCIPnP Menu ............................................................................................................................. 72
7.5 Boot Menu ................................................................................................................................... 73
7.5.1 Boot – Boot Settings Configuration ........................................................................................... 74
7.5.2 Boot – Boot Device Priority ........................................................................................................ 76
7.6 Security Menu ............................................................................................................................. 77
7.7 Chipset Menu .............................................................................................................................. 79
7.7.1 Advanced Chipset Settings – North Bridge Chipset Configuration ........................................... 79
7.7.2 Advanced Chipset … – North Bridge … – Boot Display Configuration ..................................... 80
7.7.3 Advanced Chipset Settings – South Bridge Chipset Configuration ........................................... 81
7.8 Exit Menu .................................................................................................................................... 82
8 AMI BIOS Beep Codes .................................................................. 83
9 OS Setup ....................................................................................... 84
10 Warranty ........................................................................................ 84
KTD-00774-G KTUS15/mITX Page 7 of 84
KTUS15 configuration
HT
1GBE
PCI
SAT A
TPM
COM ports
DVI
CRT
KTUS15/mITX 1.1GHz Basic
+ 2 +
KTUS15/mITX 1.1GHz Std
+ + + 4 + KTUS15/mITX 1.6GHz Std
+ + + + 2 + KTUS15/mITX 1.6GHz Plus
+ + + + + 4 +
1 Introduction
This manual describes the KTUS15/mITX family of boards made by KONTRON Technology A/S.
All boards have included Intel Atom Processors (BGA) processors, either 1.1GHz or 1.6GHz Ultra Low
Power, depending on actual board configuration. The Intel® US15W chipset is used on all configurations.
Available configurations are:
Use of this manual implies a basic knowledge of PC-AT hardware and software. This manual is focused on
describing the KTUS15 board’s special features and is not intended to be a standard PC-AT textbook.
New users are recommended to study the short installation procedure stated in chapter 2 before switchingon the power.
All configuration and setup of the CPU board is either done automatically or by the user in the CMOS setup
menus. Except for the CMOS Clear jumper and the Boot BIOS ROM Selection jumper, no jumper
configuration is required.
KTD-00774-G KTUS15/mITX Page 8 of 84
!
Warning: When mounting the board to chassis etc. please notice that the board contains
without reasonable care. A damaged component can result in malfunction or no function at all.
Note: To clear all CMOS settings, including Password protection, move the Clr-CMOS jumper (with or
correctly when reinserted.
2 Installation procedure
2.1 Installing the board
To get the board running, follow these steps. In some cases the board shipped from KONTRON Technology
has DDR2 DRAM mounted. In this case Step 2 can be skipped.
1. Turn off the PSU (power supply unit)
2. Insert the DDR2 SODIMM 200pin DRAM module
See guidelines below for assembling / disassembling memory module.
For a list of approved DDR2 DIMM modules contact your Distributor or FAE.
DDR2-400 and DDR2-533 SODIMM 200pin DRAM modules (PC3200, PC4200) are supported.
3. Connect Interfaces
Insert all external cables for hard disk, keyboard etc. A CRT or DVI monitor (depending on actual
KTUS15 version) must be connected in order to change CMOS settings for flat panel support.
4. Connect the PSU and turn on the power to the PSU
Connect power supply to the board by the 6x2pin PWR connector.
Note: the board is a single-supply board, accepting input voltages from 5V to 25V (DC). Power cables for
connecting the KTUS15 family boards to a ATX power supply (+5V or +12V) are available from Kontron
(P/N 1022-6309).
5. Power Button
The PWRBTN_IN may be required to start the board; this is done by momentarily connecting together pins
16 (PWRBTN_IN) and pin 18 (GND) on the FRONTPNL connector (see Connector description), to provide
a pulse on the PWRBTN_IN pin. A “normally open” switch can be connected via the FRONTPNL
connector.
6. BIOS Setup
Enter the BIOS setup by pressing the <Del> key during boot up. Refer to the “BIOS Configuration / Setup“
section of this manual for details on BIOS setup.
without power) for approximately 1 minute. This will also disable any Secure CMOS setup on the board.
Alternatively, turn off power and remove the battery for 1 minute, but be careful to orientate the battery
7. Mounting the board to chassis
When fixing the Motherboard on a chassis it is recommended using screws with integrated washer and
having diameter of ~7mm.
Note: Do not use washers with teeth, as they can damage the PCB mounting hole and may cause short
circuits.
components on both sides of the PCB which can easily be damaged if board is handled
KTD-00774-G KTUS15/mITX Page 9 of 84
When an interface/connector has a VCC (or other power) pin, which is directly connected to a power
2.2 Requirement according to EN60950
Users of KTUS15 family boards should take care when designing chassis interface connectors in order to
fulfill the EN60950 standard:
plane like the VCC plane:
To protect the external power lines of the peripheral devices, the customer has to take care about:
• That the wires have suitable rating to withstand the maximum available power.
• That the enclosure of the peripheral device fulfils the fire protecting requirements of IEC/EN 60950.
Lithium Battery precautions:
CAUTION!
Danger of explosion if battery is incorrectly
replaced.
Replace only with same or equivalent type
recommended by manufacturer.
Dispose of used batteries according
to the manufacturer’s instructions.
ADVARSEL!
Lithiumbatteri – Eksplosionsfare ved fejlagtig
håndtering.
Udskiftning må kun ske med batteri
af samme fabrikat og type.
Levér det brugte batteri tilbage til leverandøren.
VARNING
Explosionsfara vid felaktigt batteribyte.
Använd samma batterityp eller en ekvivalent
typ som rekommenderas av apparattillverkaren.
Kassera använt batteri enligt fabrikantens
instruktion.
VORSICHT!
Explosionsgefahr bei unsachgemäßem Austausch
der Batterie.
Ersatz nur durch den selben oder einen vom
Hersteller empfohlenen gleichwertigen Typ.
Entsorgung gebrauchter Batterien nach
Angaben des Herstellers.
ADVARSEL
Eksplosjonsfare ved feilaktig skifte av batteri.
Benytt samme batteritype eller en tilsvarende
type anbefalt av apparatfabrikanten.
Brukte batterier kasseres i henhold til fabrikantens
instruksjoner.
VAROITUS
Paristo voi räjähtää, jos se on virheellisesti
asennettu.
Vaihda paristo ainoastaan laltevalmistajan
suosittelemaan
tyyppiin. Hävitä käytetty paristo valmistajan
ohjeiden
mukaisesti.
KTD-00774-G KTUS15/mITX Page 10 of 84
Form factor
KTUS15/mITX: mini ITX (170.18millimeters by 170.18millimeters)
Audio, 7.1 and 7.2 Channel High Definition Audio Codec using the Realtek ALC888 codec
Onboard speaker
3 System specification
3.1 Component main data
The table below summarizes the features of the KTUS15/mITX embedded motherboards.
• Intel® Atom™ BGA processors 1.1GHz (Z510) or 1.6GHz (Z530) depending on board
configuration.
• On die, primary 32kB instructions cache, 24kB write-back data cache, and 512kB, 8-
Processor
Memory
way L2 cache.
• 533MHz (Z530) / 400MHz (Z510) Source-Synchronous front side bus speed (FSB)
• Supports Hyper-Threading Technology 2-threads (Z530 only)
• Supports C0/C1(e)/C2(e)/C4(e) and Intel® Deep Power-Down Technology (C6)
• Thermal Design Power (TDP) of 2W for Intel® Atom™ processors Z510 and Z530
• DDR2 SODIMM 200pin DRAM socket
• Supports 1.8V DDR2 SDRAM
• Supports 400MT/s (Mega Transfer per second) and 533MT/s data rates
• Support system memory from 512MB and up to 2GB
• ECC not supported
Chipset
Video
Audio
• Intel® System Controller Hub US15W
• Intel® Graphics Media Accelerator 500
• Ultra Low Power Integrated 3D Graphics core
• Graphics controller core frequency of 200MHz
• Full hardware acceleration of video decode standards, such as H.264, MPEG2,
MPEG4, VC1, and WMV9
• Video memory up to 256MB (Dynamic Video Memory). (Only up to 8MB can be
reserved in BIOS).
• Analog Display CRT output (depending on configuration) with support for analogue
monitors up to 1600x1200 at 60Hz.
• Digital Visual Interface digital output (DVI-D) (depending on configuration) with
support for digital monitors up to 1600x1200 at 60Hz.
• Single channel 18/24bit LVDS panel support (OpenLDI/ SPWG) up to Wide XGA
(1366x768 @ 85Hz) panel resolution. With external 1-to-2 pixel per clock converter,
LVDS panels up to 1280x1024 are supported.
• Dual independent pipe support, Mirror and Dual independent display support.
• Line-out
• Line-in
• Surround output: SIDE, LFE, CEN, BACK and FRONT
• Microphone: MIC1, MIC2
• CDROM in
• SPDIF Interface
(Continues)
KTD-00774-G KTUS15/mITX Page 11 of 84
I/O Control
Winbond W83627DHG LPC Bus I/O Controller
• Four USB 2.0 ports on I/O area
• PS/2 keyboard and mouse ports
LAN
Support
• 10/100/1000Mbits/s LAN using Intel ® 82574L controllers
• RPL/PXE netboot supported. Wake On LAN (WOL) supported (S3 only).
• Kontron Technology / AMI BIOS (core version 8.00)
• TPM version 1.2 support
• PCI Bus routed to 1 PCI slot (PCI Local Bus Specification Revision 2.3)
• 8 x GPIOs (General Purpose I/Os) routed to FEATURE connector
• Smart Fan control system, support Thermal® and Speed® cruise for two onboard Fan
• SMI violations (BIOS) on HW monitor not supported. Supported by API (Windows).
• WinXP Professional
* = Limitations may apply (not all functions, drivers and features are tested).
• Four USB 2.0 ports on internal pinrows
• Two / Four Serial ports (RS232C) (depending on board configuration)
• One Parallel port, SPP/EPP/ECP
Peripheral
interfaces
BIOS
• Two Serial ATA-150/300 IDE AHCI (depending on board configuration) w. RAID
support.
• One PATA 33/66/100 interface with support for 2 devices
• CF (Compact Flash) interface supporting CF type I and II. (UDMA2 max.). Note that
only one PATA device is supported when CF is used and only by use of 40-wire cable
(not 80-wire cable). Optionally, use SATA devices.
• Support for Advanced Configuration and Power Interface (ACPI 3.0), Plug and Play
o Suspend To Ram
o Suspend To Disk
o Intel Speed Step
• Secure CMOS/ OEM Setup Defaults
• “Always On” BIOS power setting
• System Locked Pre-Activation (SLP) key support
• Boot-Logo / Long splash support
• Setup for Forced Boot device
• Desktop Management Interface (DMI) with user-configurable setup
Expansion
Capabilities
Hardware
Monitor
Subsystem
Operating
Systems
Support
• PCI-Express bus routed to 2 (x1)PCI Express slots (PCI Express 1.0a)
• Two Secure Digital I/O (SDIO) card slots (backside)
• SMBus routed to TPM header, Feature connector, PCI, and PCI Express Slot
connectors
• LPC Bus routed to TPM connector
• DDC Bus routed to LVDS and CRT /DVI connector
control connectors: FAN_CPU and FEATURE
• Three thermal inputs: CPU die temperature, System temperature and External
temperature input routed to FEATURE connector. (Precision +/- 3ºC)
• Voltage monitoring
• Intrusion detect input
• Windows Vista
• Windows 7 *
• WinXP Embedded *
• Linux: Fedora Core 9 *, Fedora Core 10 *, Moblin *, Suse 11.1 *, Ubunty Jaunty (alpha
version) *
(Continues)
KTD-00774-G KTUS15/mITX Page 12 of 84
Only Japanese brand Aluminum capacitors rated for 100º Celsius used onboard
Operating:
0°C – 60°C operating temperature (forced cooling). It is the customer’s responsibility
to provide sufficient airflow around each of the components to keep them within
allowed temperature range.
10% - 90% relative humidity (non-condensing)
Storage:
-20°C – 70°C
5% - 95% relative humidity (non-condensing)
Electro Static Discharge (ESD) / Radiated Emissions (EMI):
All Peripheral interfaces intended for connection to external equipment are ESD/ EMI
protected.
EN 61000-4-2:2000 ESD Immunity
EN55022:1998 class B Generic Emission Standard.
Environmental
Conditions
Safety:
UL/IEC 60950-1 2nd edition - 2007-03-27.
CSA C22.2 No. 60950-1-03 2nd edition - 2007-03-01.
IEC 60950-1:2005+A1
Product Category: Information Technology Equipment Including Electrical Business
Equipment
Product Category CCN: NWGQ2, NWGQ8
File number: E194252
Theoretical MTBF:
353.685 hours @ 40ºC, 170.050 hours @ 60ºC.
Restriction of Hazardeous Substances (RoHS):
All boards in the KTUS15 board family are RoHS compliant.
Capacitor utilization:
No Tantalum capacitors onboard
Battery
Exchangeable 3.0V Lithium battery for onboard Real Time Clock and CMOS RAM.
Manufacturer Panasonic / PN CR2032NL/LE, CR-2032L/BN or CR-2032L/BE.
Expected minimum 5 years retention varies depending on temperature, actual
application on/off rate and variation within chipset and other components.
Approximately current draw is 3-4 µA (no PSU connected).
CAUTION: Danger of explosion if the battery is incorrectly replaced. Replace
only with the same or equivalent type recommended by the manufacturer.
Dispose of used batteries according to the manufacturer’s instructions.
KTD-00774-G KTUS15/mITX Page 13 of 84
3.2 System overview
The block diagram below shows the architecture and main components of the KTUS15 family boards.
Components shown shaded are optional depending on variants of the board.
KTD-00774-G KTUS15/mITX Page 14 of 84
P/N 810290
1.6GHz Std
P/N 810291
1.1GHz Basic
P/N 810292
1.6GHz Plus
P/N 810293
1.1GHz Std
Processor
Z530, 1.6GHz
Z510, 1.1GHz
Z530, 1.6GHz
Z510, 1.1GHz
FSB speed
533MHz
400MHz
533MHz
400MHz
Memory, DDR2 SODIMM
Up to 2GB
Up to 2GB
Up to 2GB
Up to 2GB
Video output
CRT (DVI-A)
Yes
No
No
Yes
DVI (DVI-D)
No
Yes
Yes
No
LVDS
Yes
Yes
Yes
Yes
LAN
Yes
Yes
Yes
Yes
HD Audio
Yes
Yes
Yes
Yes
SATA port
Yes, 2 ports
No
Yes, 2 ports
Yes, 2 ports
PATA port
Yes, 1 port
Yes, 1 port
Yes, 1 port
Yes, 1 port
Compact Flash slot
Yes
Yes
Yes
Yes
SDIO slot
Yes, 2 slots
Yes, 2 slots
Yes, 2 slots
Yes, 2 slots
USB port
Yes, 8 ports
Yes, 8 ports
Yes, 8 ports
Yes, 8 ports
Serial port
Yes, 2 ports
Yes, 2 ports
Yes, 4 ports
Yes, 4 ports
Parallel / Printer port
Yes, 1 port
Yes, 1 port
Yes, 1 port
Yes, 1 port
Mse / Kbd interface
Yes
Yes
Yes
Yes
Feature connector
Yes
Yes
Yes
Yes
Frontpanel connector
Yes
Yes
Yes
Yes
FAN CPU connector
Yes
Yes
Yes
Yes
PCI slot
Yes, 1 slot
No
Yes, 1 slot
Yes, 1 slot
PCI express slot
Yes, 2 PCIe x1
slots
Yes, 2 PCIe x1
slots
Yes, 2 PCIe x1
slots
Yes, 2 PCIe x1
slots
TPM chip onboard
No
No
Yes
No
3.3 KTUS15/mITX Board configurations
Function
KTUS15/mITX
KTUS15/mITX
KTUS15/mITX
KTUS15/mITX
KTD-00774-G KTUS15/mITX Page 15 of 84
CPU
FSB Speed
DRAM Clock
DRAM Data Rate
DRAM Type
Peak Bandwidth
Z510, 1.1GHz
400MHz
200MHz
400MT/s
DDR2
3.2GB/s
Z530, 1.6GHz
533MHz
266MHz
533MT/s
DDR2
4.2GB/s
3.4 System Memory support
The KTUS15 boards have one 200-pin DDR2 Small Outline Dual Inline Memory Module (SO-DIMM) socket.
The socket can be populated with up to 2GB of unbuffered DDR2 SO-DIMM modules.
Memory speeds up to 533MT/s (PC-4200) are supported.
• Supports 1.8-V DDR2 SDRAM with gold-plated contacts
• SDRAM Organisation of x16 supported only, up to 2 ranks, 8 loads only
• Supports 400 MT/s and 533 MT/s data rates
• Single 64-bit wide single-channel
• Support system memory from 512MB and up to 2GB
• Device density support for 512Mb and 1024Mb devices
• ECC not supported
• Serial Presence Detect required
The installed DDR2 SDRAM should support the Serial Presence Detect (SPD) data structure. This allows the
BIOS to read and configure the memory controller for optimal performance. If non-SPD memory is used, the
BIOS will attempt to configure the memory settings, but performance and reliability may be impacted.
Memory Operating Frequencies
The KTUS15/mITX maintains a fixed relationship between DRAM to FSB clock frequency. The FSB
frequency can be 400MHz or 533MHz, resulting in support of the following clock frequencies and data rates
for the DRAM.
Note: Kontron offers the following memory modules:
P/N 825551, DDR2, 512MB, 200p, 667MZ, PC5300, SODIMM
P/N 825552, DDR2, 1GB, 200p, 667MZ, PC5300, SODIMM
P/N 825553, DDR2, 2GB, 200p, 667MZ, PC5300, SODIMM
KTD-00774-G KTUS15/mITX Page 16 of 84
3.5 KTUS15 Graphics Subsystem
The KTUS15 boards use the Intel ® US15W chipset for graphical control by the embedded Intel® Graphics
Media Accelerator 500.
The Intel Graphics Media Adapter includes LVDS and Serial DVO display ports permitting simultaneous
independent operation of two displays.
If more independent displays are required then PCI Graphic Card can be added.
Using PEG (PCI Express Graphics) card will make the internal graphics device, LVDS and SDVO ports not
function.
The KTUS15 board supports a Low-Voltage Differential Signaling interface that allows the Intel Graphics
Media Adapter to communicate directly to an on-board flat-panel display. The LVDS interface supports pixel
color depths of 18 and 24 bits, one-pixel per clock displays.
The Intel ® US15W chipset Serial DVO port either connects to a Serial DVO Digital DVI (DVI-D) or a
Serial DVO Analogue DVI (DVI-A) controller depending on the board configuration (refer to KTUS15/mITX
Board configurations section).
3.5.1 Intel® Graphics Media Accelerator 500
Features of the Intel® Graphics Media Accelerator 500.graphics controller includes:
• Integrated graphics (2D and 3D) and high-definition video decode capabilities with minimal power
consumption
o 200MHz core frequency
o UMA memory architecture.
o Max video memory: 256MB. (Dynamic Video Memory). (Max. 8MB can be reserved in BIOS).
• 3D Core Key Features
o Direct3D version 10.1 and OpenGL 2.0 compliant (TBD)
o Two pipe scalable unified shader implementation.
3D Peak Performance
Fill Rate: 2 Pixels per clock
Vertex Rate: One Triangle 15 clocks (Transform Only)
Vertex / Triangle Ratio average = 1 vtx/tri, peak 0.5 vtx/tri
o Texture max size = 2048 x 2048
o Programmable 4x multi-sampling anti-aliasing (MSAA)
o Rotated grid
o Optimized memory efficiency using multi-level cache architecture
• Video
o Full hardware acceleration of video decode standards, such as H.264, MPEG2, MPEG4, VC1,
and WMV9.
o MPEG2 hardware acceleration: VLD + iDCT + MC
o VC-1 hardware acceleration: VLD + iMDCT + MC + LDF
• Display
o Analog Display CRT output (DVI-A) (depending on configuration) with support for analogue
monitors up to 1600x1200 at 60Hz.
o Digital Visual Interface digital output (DVI-D) (depending on configuration) with support for digital
monitors up to 1600x1200 at 60Hz.
o Single channel 18/ 24bit LVDS panel support (OpenLDI/ SPWG) up to Wide XGA (1366x768 at
85Hz) panel resolution. With external 1-to-2 pixel per clock converter, LVDS panels up to
1280x1024 are supported.
o Dual independent pipe support, Mirror and Dual independent display support.
KTD-00774-G KTUS15/mITX Page 17 of 84
LVDS Interface
No Display
N/A
DID
DID
DID
DID
SD
SD
SD
SD
640x480
DID
DID
DID
DID
DID
800x480
DID
DID
DID
DID
DID
800x600
DID
DID
DID
DID
DID
1024x600
SD
1024x768
SD
1280x768
SD
1366x768
SD
1280x1024
SD
1600x1200
SD
1600x1200
SD
3.5.2 Dual Independent/Mirror/Single Display support
The table below shows the supported display configurations for the KTUS15 boards.
Mem. Freq. 533MT/s
Color depth 32bit
Refresh rate 60Hz
No Display
640x480
sDVO interface
DID = Dual Independent or Mirror Displays
SD = Single Display
800x480
800x600
1024x600
1024x768
1280x768
1366x768
1280x1024
KTD-00774-G KTUS15/mITX Page 18 of 84
Supply
Min
Max
Note
+VIN
4.75V
26.2V
Same as 5 – 25V +/-5%
Power requirements (max)
+12V
+5V
+3V3
LVDS outlet
2A
1.5A
1A
PCI outlet
0.5A
5A
6.67A
PCIe outlet
0.5A
-
3A
USB outlet
-
4A
-
Total maximum
2A
5A
6.7A
Available power
@ 12V Input and 25ºC (*)
2A
5A
6.7A
@ 12V Input and 40ºC (*)
1.5V
3A
3A
@ 24V Input and 40ºC (*)
1A
1A
1A
@ 24V Input and 60ºC (*)
0.5A
0.5A
0.5A
@ 24V Input and 60ºC (**)
2A
3A
3A
Windows XP Idle, No external load (C6 enabled)
Input Voltage [V]
5
10
15
20
25
Average Power [W]
9
9.5
10
11.5
13
Ripple Current [A]
0.2
1.7
2.4
3.1
2.4
DOS Idle, No external load
Input Voltage [V]
5
10
15
20
25
Average Power [W]
11
11
12
13
14
Ripple Current [A]
0.2
1.6
2.5
3.2
2.2
Windows XP Idle, No external load (C6 enabled)
Input Voltage [V]
5
10
15
20
25
Average Power [W]
10
10
11
12
13
Ripple Current [A]
0.7
1.4
1.6
1.9
2
DOS Idle, No external load
Input Voltage [V]
5
10
15
20
25
Average Power [W]
12.5
13
13.5
14
15
Ripple Current [A]
0.2 2 2.4
3.1
3.4
S5
Input Voltage [V]
5
10
15
20
25
Average Power [W]
1 2 2.5 3 3.5
Ripple Current [A]
0.5
1.8
1.5
3.2
3.2
Power NET
Efficiency
@
+3V3
~90%
3A
+5V
~80%
1A
+12V
~75%
1A
3.6 KTUS15 Power
3.6.1 Power Budget
The KTUS15 has several outlets for supplying power to external devices. Each power rail is independent of
other power rails, and the power budget for a single power rail can be shared among the interfaces that
utilize it. The maximum load for each rail should however not be exceeded, hence it is not possible to apply
full load to all external interfaces at the same time. The total power budgets for the individual rails are listed
below. Power output pins for the interfaces can be found in chapter 4.
(*) Board Batch # 19000000 and
previous revisions up to R19.
(**) Board Batch # from 20000000.
3.6.2 Power Consumption
The KTUS15/mITX board is powered through the PWR connector by a single supply DC voltage.
KTUS15/mITX 1.1GHz normal operation:
KTUS15/mITX 1.6GHz normal operation:
Power down mode: External load additional power consumption:
Notes:
The onboard PSU efficiency varies depending on actual load, input voltage and temperature.
The above mentioned power consumptions are typical values and varies ~+/- 25% from system to system.
KTD-00774-G KTUS15/mITX Page 19 of 84
3.7 KTUS15 Clock Distribution
KTD-00774-G KTUS15/mITX Page 20 of 84
4 Connector Definitions
The following sections provide pin definitions and detailed description of all on-board connectors.
The connector definitions follow the following notation:
Column
name
Pin Shows the pin-numbers in the connector. The graphical layout of the connector definition
Signal The mnemonic name of the signal at the current pin. The notation “XX#” states that the signal
Type AI: Analog Input.
Ioh: Typical current in mA flowing out of an output pin through a grounded load, while the
Pull U/D On-board pull-up or pull-down resistors on input pins or open-collector output pins.
Note Special remarks concerning the signal.
The abbreviation TBD is used for specifications which are not available yet or which are not sufficiently
specified by the component vendors.
Description
tables is made similar to the physical connectors.
“XX” is active low.
AO: Analog Output.
I: Input, TTL compatible if nothing else stated.
IO: Input / Output. TTL compatible if nothing else stated.
IOT: Bi-directional tristate IO pin.
IS: Schmitt-trigger input, TTL compatible.
IOC: Input / open-collector Output, TTL compatible.
NC: Pin not connected.
O: Output, TTL compatible.
OC: Output, open-collector or open-drain, TTL compatible.
OT: Output with tri-state capability, TTL compatible.
LVDS: Low Voltage Differential Signal.
PWR : Power supply or ground reference pins.
output voltage is > 2.4 V DC (if nothing else stated).
Iol: Typical current in mA flowing into an output pin from a VCC connected load, while the
output voltage is < 0.4 V DC (if nothing else stated).
KTD-00774-G KTUS15/mITX Page 21 of 84
Colour combination
(D52 / D51/ D50)
Power
State
Green / Green / Green
S0
Running
Red / Green / Off
S3
Standby with RAM maintained
Red / Red / Off
S4/S5
Sleep
Yellow / Yellow / Don’t care
-
Failure if stuck in this combination.
Red / Yellow / Don’t care
-
Failure if stuck in this combination.
Yellow / Red / Don’t care
-
Failure if stuck in this combination.
Notes:
All connector except ”DDR2 SLOT”, “SDIO1” and “SDIO2” will be described in more details later in this chapter.
SATA1
SATA0
PWR
FRONTPNL
PATA
COMPACT FLASH
DDR2 SLOT
FAN CPU
COM3
TPM
Boot ROM
FEATURE
COM1
PRINTER
USB6/7
PWR-OUT
COM2
COM4
CDROM
Clr-CMOS
PCI Slot
KBDMSE
AUDIO-HEAD
PCIe x1 Slot 1
PCIe x1 Slot 2
LVDS
Status LED’s
4.1 Connector layout
4.1.1 KTUS15/mITX – Top side
Status LED’s:
Notes
Note: The color coding of the LED’s was different on EFT samples and first batches. The most significant
digit of the two digit “PCB ID” code (BIOS Main Menu) indicates the firmware version which is responsible for
the LED colors. This digit must be 4 (or above) otherwise don’t use the LED for anything.
KTD-00774-G KTUS15/mITX Page 22 of 84
DVI-A
KBD/MSE
LINE-OUT
USB2
MIC-IN
LINE-IN
USB4
USB5
LAN
SDIO1
SDIO2
Note:
All connector except ”DDR2 SLOT”, “SDIO1” and “SDIO2” will be described in more details later in this chapter.
4.1.2 KTUS15/mITX - IO Bracket side
4.1.3 KTUS15/mITX – Back side
KTD-00774-G KTUS15/mITX Page 23 of 84
1022-6309 Cable ATX Power for KTUS15 Part A
The PN 1022-6309 Adapter cables can be used as standard ATX PSU (for prototyping etc). The ATX
1022-6309 Cable ATX Power for KTUS15 Part B
Note
Type
Signal
PIN
Signal
Type
Note
PWR
GND
7 1
+Vin
PWR
PWR
GND
8 2
+Vin
PWR
PWR
GND
9 3
+Vin
PWR
PWR
GND
10 4 +Vin
PWR
PWR
GND
11 5 +Vin
PWR
PWR
GND
12 6 +Vin
PWR
4.2 Power Connector (PWR)
The KTUS15 boards shall be supplied by a single supply DC voltage in the range 5-25V DC +/-5%.
The board will power on when the VIN voltage raises above 4.75V DC.
Notes:
The POWER_UP signal input (available on the FEATURE connector) can be used to externally control the
power on of the board. The signal has a 100kOhm onboard pull-up to Vin. The positive threshold of the
signal is ~1.5V DC with some hysteresis. Applying a resistor between POWER_UP and GND can make the
board power up as a function of Vin. E.g. it can be used if a single voltage PSU is used and it has slow
ramping power up or it can be used if voltage must be at a certain minimum level before Motherboard turns
on in order not to overload the PSU until it is ready.
The PSUP_OFF signal (available on the FEATURE connector) is open collector output signal which can
optionally be used as PSON input to an ATX PSU to keep it turned on until this signal gets inactive (Windows
Shutdown etc.)
connector part can be cut of so that cable kit can be used for small batches as well.
1. 5A (max.) per wire is allowed.
2. Recommend using 12V input if 12V is already needed for devices like backlight inverter, HDD etc.
3. If 12V is not needed then 5V input will reduce power loss to a minimum.
4. Customised Power Cable kit is possible (MOQ is 500).
KTD-00774-G KTUS15/mITX Page 24 of 84
PIN Signal
Type
Ioh/Iol
Pull U/D
Note
1 +5V
PWR - -
4A max
2 GND
PWR - - 3 GND
PWR - - 4 +12V
PWR - -
2A max
4.3 Power Out Connector (PWR-OUT)
External devices like HDD, CDROM etc. can be power sourced via the PWR-OUT connector.
Note:
The PN 1027-3669 “Cable Power Out KTUS15” fits the PWR-OUT connector, and it has commonly used
plugs in order to source power to different types of devices like PATA HDD, SATA devices, CDROM etc.
Connector P1 fits KTUS15 (P1 pin 1-4 will be connected to PWR-OUT pin 4-1)
Connector P2 is standard SATA power connector
Connector P3 is standard Hard Disk power connector
Connector P4 is standard Floppy Disk power connector
KTD-00774-G KTUS15/mITX Page 25 of 84
Pull
U/D
Pull
U/D
1 2K7
TBD
IOC
MSCLK
6 5
KBDCLK
IOC
TBD
2K7 - - PWR
5V/SB5V
4 3
GND
PWR - - 1
2K7
TBD
IOC
MSDAT
2 1
KBDDAT
IOC
TBD
2K7
Pull
U/D
1 KBDCLK
IOC
TBD
2K7
2 KBDDAT
IOC
TBD
2K7
3 MSCLK
IOC
TBD
2K7
4 MSDAT
IOC
TBD
2K7
5 5V/SB5V
PWR
- -
6
GND
PWR
- -
MSDAT
Bi-directional serial data line used to transfer data from or commands to the PS/2 mouse.
KDBCLK
Bi-directional clock signal used to strobe data/commands from/to the PC-AT keyboard.
KBDDAT
Bi-directional serial data line used to transfer data from or commands to the PC-AT keyboard.
4.4 Keyboard and Mouse connectors
Attachment of a keyboard or PS/2 mouse adapter can be done through the MINI-DIN (KBD) connector or via
the pinrow (KBDMSE) connector. All interfaces utilize open-drain signaling with on-board pull-up.
Note: PN 821091 Keyboard/Mouse cable splitter cable kit is available for connecting Keyboard and Mouse
via KBD connector.
The mouse and keyboard is supplied from SB5V when in standby mode in order to via keyboard or mouse to
make the system wake up from power saving states. The supply is provided through a 1.1A reset-able fuse.
4.4.1 MINI-DIN Keyboard and Mouse Connector (KBD)
Note
Note 1: To use the PS/2 mouse in the KBD connector an adapter cable is required.
Signal Description – Keyboard & and mouse Connector (MSE & KBD), see below.
Ioh/Iol Type Signal PIN# Signal Type Ioh/Iol
4.4.2 Keyboard and Mouse pinrow Connector (KBDMSE)
PIN#
Signal Type Ioh/Iol
Note
Note
Signal Description – Keyboard & and mouse Connector (KBDMSE).
Signal Description
MSCLK Bi-directional clock signal used to strobe data/commands from/to the PS/2 mouse.
KTD-00774-G KTUS15/mITX Page 26 of 84
Pin
Signal
Description
Type
Pull Up
Note
1-5
N.C.
-
2
6
DDC Clock
DDC Clock
IO
2K2 7
DDC Data
DDC Data
IO
2K2 8
ANALOG VSYNC
CRT vertical synchronization output.
-
9-13
N.C.
- 2 14
+5V
Power for monitor when in standby
PWR 1
15
GND
PWR
16
Hot Plug Detect
Hot Plug Detect
I
17-24
N.C.
2 C1
ANALOG RED
Analog output carrying the red color signal
O
/75R
C2
ANALOG GREEN
Analog output carrying the green color signal
O
/75R
C3
ANALOG BLUE
Analog output carrying the blue color signal
O
/75R
C4
ANALOG HSYNC
CRT horizontal synchronization output.
O
C5
ANALOG GND
Ground reference for RED, GREEN, and BLUE
PWR
4.5 Display connector
The Intel ® US15W chipset onboard the KTUS15 boards have:
• SDVO channel for display interface
o SDVO to Analogue / DVI-A (CRT)
o SDVO to Digital / DVI-D
• LVDS Single channel 18/ 24bit interface
Depending on the KTUS15/mITX board configuration (refer to section KTUS15/mITX Board configurations),
the board is either configured for analogue (DVI-A) or digital display (DVI-D) output on the onboard DVI
connector which is of the type DVI-I. In other words, even though onboard DVI connector is a type DVI-I
simultaneous analogue and digital output is not possible on the DVI-I connector and it is not possible to
change configuration from Analogue to Digital output or vice versa.
4.5.1 DVI Connector (DVI-A), Analogue output
The DVI-A connector only support DVI Analog output. For connecting a standard CRT (analogue) monitor to
the DVI-A connector a DVI-CRT adapter can be used (Kontron P/N 822001).
Female socket, front view
Signal Description - DVI Connector:
Note 1: The 5V supply is fused by a 1.1A reset-able fuse
Note 2: DVI digital signals are not supported
KTD-00774-G KTUS15/mITX Page 27 of 84
Pin
Signal
Description
Type
Pull Up
1
TMDS Data 2-
Digital Red – (Link 1)
LVDS OUT
2 TMDS Data 2+
Digital Red + (Link 1)
LVDS OUT
3 TMDS Data 2/4 Shield
PWR
4
N.C.
- 5
N.C.
- 6
DDC Clock
DDC Clock
IO
2K2 7 DDC Data
DDC Data
IO
2K2 8 N.C.
- 9
TMDS Data 1-
Digital Green – (Link 1)
LVDS OUT
10
TMDS Data 1+
Digital Green + (Link 1)
LVDS OUT
11
TMDS Data 1/3 Shield
PWR
12
N.C.
-
13
N.C.
-
14
+5V
Power for monitor when in standby
PWR
1
15
GND
PWR
16
Hot Plug Detect
Hot Plug Detect
I
17
TMDS Data 0-
Digital Blue – (Link 1) / Digital sync
LVDS OUT
18
TMDS Data 0+
Digital Blue + (Link 1) / Digital sync
LVDS OUT
19
TMDS Data 0/5 Shield
PWR
20
N.C.
-
21
N.C.
-
22
TMDS Clock Shield
PWR
23
TMDS Clock+
Digital clock + (Link 1)
LVDS OUT
24
TMDS Clock-
Digital clock - (Link 1)
LVDS OUT
C1 - C5
N.C.
-
2
4.5.2 DVI Connector (DVI-D), Digital output
The DVI-D connector only support DVI Digital output.
Female socket, front view
Signal Description - DVI Connector:
Note 1: The 5V supply in the CRT connector is fused by a 1.1A resettable fuse
Note 2: DVI analogue signals are not supported
KTD-00774-G KTUS15/mITX Page 28 of 84
Note
Type
Signal
PIN
Signal
Type
Note
Max. 0.5A
PWR
+12V
1 2 +12V
PWR
Max. 0.5A
Max. 0.5A
PWR
+12V
3 4 +12V
PWR
Max. 0.5A
Max. 0.5A
PWR
+12V
5 6 GND
PWR
Max. 0.5A
Max. 0.5A
PWR
+5V
7 8 GND
PWR
Max. 0.5A
Max. 0.5A
PWR
LCDVCC
9 10 LCDVCC
PWR
Max. 0.5A
2K2Ω, 3.3V
OT
DDC CLK
11
12 DDC DATA
OT
2K2Ω, 3.3V
3.3V level
OT
BKLTCTL
13
14 VDD ENABLE
OT
3.3V level
3.3V level
OT
BKLTEN#
15
16 GND
PWR
Max. 0.5A
LVDS
LVDS A0-
17
18 LVDS A0+
LVDS
LVDS
LVDS A1-
19
20 LVDS A1+
LVDS
LVDS
LVDS A2-
21
22 LVDS A2+
LVDS
LVDS
LVDS ACLK-
23
24 LVDS ACLK+
LVDS
LVDS
LVDS A3-
25
26 LVDS A3+
LVDS
Max. 0.5A
PWR
GND
27
28 GND
PWR
Max. 0.5A
LVDS
N.C.
29
30 N.C.
LVDS
LVDS
N.C.
31
32 N.C.
LVDS
LVDS
N.C.
33
34 N.C.
LVDS
LVDS
N.C.
35
36 N.C.
LVDS
LVDS
N.C.
37
38 N.C.
LVDS
Max. 0.5A
PWR
GND
39
40 GND
PWR
Max. 0.5A
Signal
Description
LVDS A0..A3
LVDS A Channel data
LVDS ACLK
LVDS A Channel clock
BKLTCTL
Backlight control (1), PWM signal to implement voltage in the range 0-3.3V
BKLTEN#
Backlight Enable signal (active low) (2)
VDD ENABLE
Output Display Enable.
VCC supply to the flat panel. This supply includes power-on/off sequencing.
configuration. Maximum load is 1A at both voltages.
DDC CLK
DDC Channel Clock
4.5.3 LVDS Flat Panel Connector (LVDS)
Note 1: The KTUS15 board supports single channel, 18/24bit OpenLDI/ SPWG panels on the LVDS
interface up to Wide XGA (1366x768 @ 85Hz) panel resolution. With an external 1-to-2 pixel per clock
converter, LVDS panels up to 1280x1024 are supported.
Signal Description – LVDS Flat Panel Connector:
LCDVCC
Note 1: Windows API will be available to operate the BKLTCTL signal. Some Inverters have a limited voltage
range 0- 2.5V for this signal: If voltage is > 2.5V the Inverter might latch up. Some Inverters
generates noise on the BKLTCTL signal, resulting in making the LVDS transmission failing
(corrupted picture on the display). By adding a 1Kohm resistor in series with this signal, mounted in
the Inverter end of the cable kit, the noise is limited and the picture is stable.
Note 2: If the Backlight Enable is required to be active high then, check the following BIOS Chipset setting:
Backlight Signal Inversion = Enabled.
The flat panel supply may be either 5V DC or 3.3V DC depending on the CMOS
KTD-00774-G KTUS15/mITX Page 29 of 84
Note
Type
Signal
PIN#
Signal
Type
Note
+12V
B1
A1
NC
+12V
B2
A2
+12V
+12V
B3
A3
+12V
GND
B4
A4
GND
SMB_CLK
B5
A5
NC
SMB_DATA
B6
A6
NC
GND
B7
A7
NC
+3V3
B8
A8
NC
NC
B9
A9
+3V3
SB3V3
B10
A10
+3V3
WAKE#
B11
A11
RST#
NC
B12
A12
GND
GND
B13
A13
PCIE CLK
PCIE_TXP
B14
A14
PCIE CLK#
PCIE_TXN
B15
A15
GND
GND
B16
A16
PCIE_RXP
NC
B17
A17
PCIE_RXN
GND
B18
A18
GND
4.6 PCI-Express connectors
The KT boards contains two 1-lane (x1) PCI Express ports intended for external PCI Express cards.
The PCI Express port is compliant to the PCI Express Base Specification revision 1.1.
The two 1-lane (x1) PCI Express ports are supplied through an onboard 5-Lane/5-port PCI express switch.
4.6.1 PCI-Express x1 Connector (PCIe x1 Slot 1 and Slot 2)
The KTUS15 boards support two 1-lane PCI Express (x1) ports.
KTD-00774-G KTUS15/mITX Page 30 of 84
Pull
U/D
1
GND
PWR - - 2
SATA* TX+
3
SATA* TX-
4
GND
PWR - - 5
SATA* RX-
6
SATA* RX+
7
GND
PWR - -
Host receiver differential signal pair
4.7 Serial ATA Hard Disk interface
The KTUS15 boards includes an onboard SATA interface depending on the configuration (refer to section
KTUS15/mITX Board configurations).
The SATA Host controller supports 2-port SATA II interface with data transfer rates of up to 3.0Gb/s
(300MB/s). The SATA controller supports AHCI mode and has integrated RAID functionality with support for
RAID modes 0 and 1.
The board provides two Serial ATA (SATA) connectors, which support one device per connector.
A point-to-point interface is used for host to device connections, unlike Parallel ATA IDE which supports a
master/slave configuration and two devices per channel.
The KTUS15 supports the following RAID (Redundant Array of Independent Drives) levels:
• RAID 0 - data striping
• RAID 1 - data mirroring
Limitations depending on Target Operating System apply.
4.7.1 SATA Hard Disk Connector (SATA0, SATA1)
SAT A:
PIN# Signal Type Ioh/Iol
The signals used for the primary Serial ATA hard disk interface are the following:
Signal Description
SATA* RX+
SATA* RX-
SATA* TX+
SATA* TX-
“*” specifies 0, 1 depending on SATA port.
Host transmitter differential signal pair
Note
KTD-00774-G KTUS15/mITX Page 31 of 84
Signal
Description
4.8 Parallel ATA Hard Disk interface
The PATA Host Controller supports three types of data transfers:
• Programmed I/O (PIO): Processor is in control of the data transfer.
• Multi-word DMA (ATA-5): DMA protocol that resembles the DMA on the ISA bus. Allows transfer rates of
up to 66MB/s.
• Ultra DMA: Synchronous DMA protocol that redefines signals on the PATA cable to allow both host and
target throttling of data and transfer rates up to 100MB/s. Ultra DMA 100/66/33 are supported, a 80-wire
cable is required.
One parallel ATA hard disk controller is available on the board – a primary controller. Standard 3½” hard
disks or CD-ROM drives may be attached to the primary controller by means of the 40 pin IDC connector,
PATA.
The parallel ATA hard disk controller is shared between the PATA connector and the CF connector.
If the CF connector is not used then two devices (a primary and a secondary device) are supported on the
PATA interface.
If the CF connector is used then only one PATA device is supported and only by use of 40-wire cable (not
80-wire cable). Optionally use SATA device(s).
The signals used for the hard disk interface are the following:
DAA2..0 Address lines, used to address the I/O registers in the IDE hard disk.
HDCSA1..0# Hard Disk Chip-Select. HDCS0# selects the primary hard disk.
DA15..8 High part of data bus.
DA7..0 Low part of data bus.
IORA# I/O Read.
IOWA# I/O Write.
IORDYA# This signal may be driven by the hard disk to extend the current I/O cycle.
RESETA# Reset signal to the hard disk.
HDIRQA Interrupt line from hard disk.
CBLIDA This input signal (CaBLe ID) is used to detect the type of attached cable: 80-wire cable
when low input, and 40-wire cable when 5V via 10Kohm (pull-up resistor).
DDREQA Disk DMA Request might be driven by the IDE hard disk to request bus master access to
the PCI bus. The signal is used in conjunction with the PCI bus master IDE function and is
not associated with any PC-AT bus compatible DMA channel.
DDACKA# Disk DMA Acknowledge. Active low signal grants IDE bus master access to the PCI bus.
HDACTA# Signal from hard disk indicating hard disk activity. The signal level depends on the hard
disk type, normally active low. The signals from primary and secondary controller are
routed together through diodes and passed to the connector FEATURE.
The pinout of the connectors is defined in the following sections.
KTD-00774-G KTUS15/mITX Page 32 of 84
Pull
U/D
Ioh/
Iol
Ioh/
Iol
Pull
U/D
- TBD
O
RESET_P#
1 2 GND
PWR - - - TBD
IO
DA7
3 4 DA8
IO
TBD - -
TBD
IO
DA6
5 6 DA9
IO
TBD - -
TBD
IO
DA5
7 8 DA10
IO
TBD - -
TBD
IO
DA4
9 10 DA11
IO
TBD - -
TBD
IO
DA3
11
12 DA12
IO
TBD - -
TBD
IO
DA2
13
14 DA13
IO
TBD - -
TBD
IO
DA1
15
16 DA14
IO
TBD - -
TBD
IO
DA0
17
18 DA15
IO
TBD - - - PWR
GND
19
20 KEY
- - - - - I DDRQA
21
22 GND
PWR - - - TBD O IOWA#
23
24 GND
PWR - - - TBD O IORA#
25
26 GND
PWR - -
4K7 - I
IORDYA
27
28 GND
PWR - - - - O DDACKA#
29
30 GND
PWR - -
10K - I
HDIRQA
31
32 NC
- - - - TBD O DAA1
33
34 CBLIDA#
I - - TBD O DAA0
35
36 DAA2
O
TBD - -
TBD
O
HDCSA0#
37
38 HDCSA1#
O
TBD - - - I
HDACTA#
39
40 GND
PWR - -
4.8.1 IDE Hard Disk Connector (PATA)
This connector can be used for connection of two primary IDE drives.
Note
Type Signal PIN# Signal Type
Note
KTD-00774-G KTUS15/mITX Page 33 of 84
Pull
U/D
Pull
U/D
2 - - - NC
26 1 GND
PWR - - 1 - TBD
IO
DA11
27 2 DB3
IO
TBD - -
TBD
IO
DA12
28 3 DB4
IO
TBD - -
TBD
IO
DA13
29 4 DB5
IO
TBD - -
TBD
IO
DA14
30 5 DB6
IO
TBD - -
TBD
IO
DA15
31 6 DB7
IO
TBD - -
TBD
O
HDCSA1#
32 7 HDCSA0#
O
TBD - - - -
NC
33 8 GND
PWR - - - TBD O IORA#
34 9 GND
PWR - - - TBD O IOWA#
35
10
GND
PWR - - - -
PWR
5V
36
11
GND
PWR - -
8K2 - I
HDIRQA
37
12
GND
PWR - - - -
PWR
5V
38
13
5V
PWR - - - -
PWR
GND
39
14
GND
PWR - -
- - - NC
40
15
GND
PWR - - - TBD
O
RESET_C#
41
16
GND
PWR - -
4K7 - I
IORDYA
42
17
GND
PWR - - - - I DDRQA
43
18
DAA2
O - - - - O DDACKA#
44
19
DAA1
O - - - - I HDACTA#
45
20
DAA0
O - - - - I CBLIDA#
46
21
DB0
IO
TBD - -
TBD
IO
DB8
47
22
DB1
IO
TBD - -
TBD
IO
DB9
48
23
DB2
IO
TBD - -
TBD
IO
DB10
49
24
NC 1 - - PWR
GND
50
25
NC - - - 2
4.8.2 Compact Flash Connector (CF)
This connector is mounted on the topside of the KTUS15/mITX.
The CF socket support DMA/UDMA modules up to UDMA2.
Note: If the CF connector is used then only one PATA device is supported and only by use of 40-wire cable
(not 80-wire cable). Optionally use SATA device(s). Normally CF is Master and then possible PATA device
must be Slave.
Note
Ioh/Iol Type Signal PIN Signal Type Ioh/Iol
Note
Note 1: Pin is longer than the average length of the other pins.
Note 2: Pin is shorter than the average length of the other pins.
KTD-00774-G KTUS15/mITX Page 34 of 84
Pull
U/D
Pull
U/D
2K2
(24)/24
OC(O)
STB#
1 2 AFD#
OC(O)
(24)/24
2K2
2K2
24/24
IO
PD0
3 4 ERR# I -
2K2
2K2
24/24
IO
PD1
5 6 INIT#
OC(O)
(24)/24
2K2
2K2
24/24
IO
PD2
7 8 SLIN#
OC(O)
(24)/24
2K2
2K2
24/24
IO
PD3
9 10 GND
PWR
- - 2K2
24/24
IO
PD4
11
12 GND
PWR
- - 2K2
24/24
IO
PD5
13
14 GND
PWR
- - 2K2
24/24
IO
PD6
15
16 GND
PWR
- - 2K2
24/24
IO
PD7
17
18 GND
PWR
- - 2K2 - I
ACK#
19
20 GND
PWR
- - 2K2 - I
BUSY
21
22 GND
PWR
- - 2K2 - I
PE
23
24 GND
PWR
- - 2K2 - I
SLCT
25
26 GND
PWR
- -
4.9 Printer Port Connector (PRINTER)
The signal definition in standard printer port mode is as follows:
Note
The definition of the signals in standard Centronics mode (SPP) with a printer attached is as follows:
Signal Description
PD7..0 Parallel data bus from PC board to printer. The data lines are able to operate in PS/2
compatible bi-directional mode.
SLIN# Signal to select the printer sent from CPU board to printer.
SLCT Signal from printer to indicate that the printer is selected.
STB# This signal indicates to the printer that data at PD7..0 are valid.
BUSY Signal from printer indicating that the printer cannot accept further data.
ACK# Signal from printer indicating that the printer has received the data and is ready to accept
further data.
INIT# This active low output initializes (resets) the printer.
AFD# This active low output causes the printer to add a line feed after each line printed.
ERR# Signal from printer indicating that an error has been detected.
PE# Signal from printer indicating that the printer is out of paper.
The printer port additionally supports operation in the EPP and ECP mode.
Ioh/Iol Type Signal PIN# Signal Type Ioh/Iol
Note
KTD-00774-G KTUS15/mITX Page 35 of 84
Signal
Description
Pull
U/D
Pull
U/D
- I DCD
1 2 DSR I - - I
RxD
3 4 RTS O - - O
TxD
5 6 CTS I - - O
DTR
7 8 RI I - - - PWR
GND
9 10 5V
PWR - -
1
4.10 Serial Ports
Two or four RS232 serial ports are available on the KTUS15 boards depending on the configuration (refer to
section KTUS15/mITX Board configurations).
The typical definition of the signals in the COM ports is as follows:
TxD Transmitted Data, sends serial data to the communications link. The signal is set to the marking
state (-12V) on hardware reset when the transmitter is empty or when loop mode operation is
initiated.
RxD Received Data, receives serial data from the communications link.
DTR Data Terminal Ready, indicates to the modem or data set that the on-board UART is ready to
establish a communication link.
DSR Data Set Ready, indicates that the modem or data set is ready to establish a communications
link.
RTS Request To Send, indicates to the modem or data set that the on-board UART is ready to
exchange data.
CTS Clear To Send, indicates that the modem or data set is ready to exchange data.
DCD Data Carrier Detect, indicates that the modem or data set has detected the data carrier.
RI Ring Indicator, indicates that the modem has received a ringing signal from the telephone line.
The connector pinout for each operation mode is defined in the following sections.
4.10.1 COM1, COM2, COM3 and COM4 Pin Header Connectors
The pinout of Serial ports Com1, 2, 3 and 4 is as follows:
Note
Note 1: The COM 1, 2, 3 and 4 header 5V supply is fused with individual 1.1A resettable fuses for each
connector.
A DB9 adapter (ribbon cable) is available for connecting the COM ports to I/O front panel.
Ioh/Iol Type Signal PIN# Signal Type Ioh/Iol
Note
KTD-00774-G KTUS15/mITX Page 36 of 84
Signal
Description
Signal
PIN#
Type
Ioh/Iol
Note
MDI0+
MDI0-
MDI1+
MDI2+
MDI2-
MDI1-
MDI3+
MDI3-
8 7 6 5 4 3 2 1
4.11 Ethernet Connectors
The KTUS15 board support 1 channel of 10/100/1000Mb Ethernet using the Intel® 82574L PCI express LAN
controller.
In order to achieve the specified performance of the Ethernet port, Category 5 twistedpair cables must be
used with 10/100MB and Category 5E, 6 or 6E with 1Gb LAN networks.
The signals for the Ethernet ports are as follows:
MDI[0]+ / MDI[0]- In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is the
transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair
in 10Base-T and 100Base-TX.
MDI[1]+ / MDI[1]- In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and is
the receive pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit
pair in 10Base-T and 100Base-TX.
MDI[2]+ / MDI[2]-
In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
MDI[3]+ / MDI[3]-
Note: MDI = Media Dependent Interface.
In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
4.11.1 Ethernet Connector (LAN)
The pinout of the RJ45 connector is as follows:
KTD-00774-G KTUS15/mITX Page 37 of 84
4.12 USB Connectors (USB)
The KTUS15 boards contain three Universal Host Controller Interface (UHCI) USB1.1 controllers and an
Enhanced Host Controller Interface (EHCI) USB2.0 controller.
A total of eight USB ports are supported. All eight of these ports are capable of high speed data transfers up
to 480MB/s, and six of the ports are also capable of FullSpeed and low-speed signaling (USB Ports 0, 1, 2,
3, 4, 5).
The KTUS15 boards support USB client functionality on port 2 of the USB interface. This permits the
platform to attach to a separate USB host as a peripheral mass storage volume or RNDIS device.
USB Legacy mode is supported. Over-current detection on all eight USB ports is supported.
USB Port 0 and 2 are supplied on the combined USB0, USB2 connector.
USB Ports 1 and 3 are supplied on the internal FRONTPNL connector (See FRONTPNL connector
description).
USB Port 4 and 5 are supplied on the combined USB4, USB5 connector.
USB Port 6 and 7 are supplied on the USB6, USB7 internal pinrow connector.
Note: It is required to use only HiSpeed USB cable, specified in USB2.0 standard:
KTD-00774-G KTUS15/mITX Page 38 of 84
Pull
U/D
Pull
U/D
1 - -
PWR
USB5V
1 2 3 4 GND
PWR - -
/15K
0.25/2
IO
USB2-
USB2+
IO
0.25/2
/15K 1 - -
PWR
USB5V
1 2 3 4 GND
PWR - -
/15K
0.25/2
IO
USB0-
USB0+
IO
0.25/2
/15K
Pull
U/D
Pull
U/D
1 - -
PWR
USB5V
1 2 3 4 GND
PWR - -
/15K
0.25/2
IO
USB4-
USB4+
IO
0.25/2
/15K 1 - -
PWR
USB5V
1 2 3 4 GND
PWR - -
/15K
0.25/2
IO
USB5-
USB5+
IO
0.25/2
/15K
Differential pair works as Data/Address/Command Bus.
Signal
Description
Differential pair works as Data/Address/Command Bus.
4.12.1 USB Connector 0/2 (USB0/2)
Note
Note 1: The 5V supply for the USB devices is fused onboard with a 2.0A resettable fuse. The supply is
common to both channels. USB5V is supplied during powerdown to allow wakeup on USB device activity.
USB0+ USB0USB2+ USB2-
USB5V 5V supply for external devices. Fused with 2.0A resettable fuse.
Ioh/Iol Type Signal PIN# Signal Type Ioh/Iol
Note
4.12.2 USB Connector 4/5 (USB4/5)
Note
Ioh/Iol Type Signal PIN# Signal Type Ioh/Iol
Note
Note 1: The 5V supply for the USB devices is fused onboard with a 2.0A resettable fuse. The supply is
common to both channels. USB5V is supplied during powerdown to allow wakeup on USB device activity.
Signal Description
USB4+ USB4USB5+ USB5-
USB5V 5V supply for external devices. Fused with 2.0A resettable fuse.
KTD-00774-G KTUS15/mITX Page 39 of 84
Pull
U/D
Pull
U/D
1 -
PWR
USB5V
1 2 USB5V
PWR - 1 -
IO
USB6-
3 4 USB7-
IO - -
IO
USB6+
5 6 USB7+
IO - -
PWR
GND
7 8 GND
PWR - - - KEY
9 10 NC - -
Differential pair works as Data/Address/Command Bus.
4.12.3 USB Connector 6/7 (USB6/7)
USB Ports 6 and 7 are supplied on the internal USB6, USB7 pinrow connector. USB6/7 are controlled only
by the EHCI USB 2.0 controller and therefore they can only run USB2.0 HiSpeed (480Mbps).
Note: If a USB device is not compatible with USB2.0 High Speed, it will not work if connected to USB6/7.
Note
Signal Description
USB6+ USB6USB7+ USB7-
USB5V 5V supply for external devices. Fused with 2.0A resettable fuse.
Note 1: The 5V supply for the USB devices is fused onboard with a 2.0A resettable fuse. The supply is
common to both channels. USB5V is supplied during powerdown to allow wakeup on USB device activity.
Ioh/Iol Type Signal PIN# Signal Type Ioh/Iol
Note
KTD-00774-G KTUS15/mITX Page 40 of 84
Signal
Type
Note
TIP
LINE1-IN-L
IA RING
LINE1-IN-R
IA SLEEVE
GND
PWR
Signal
Type
Note
TIP
MIC1-L
IA RING
MIC1-R
IA SLEEVE
GND
PWR
Signal
Type
Note
TIP
LINE-OUT-L
OA RING
LINE-OUT-R
OA SLEEVE
GND
PWR
Signal
Description
Note
LINE-OUT / FRONT
Line out / Front Speakers
MIC1
MIC Input 1
LINE1-IN
Line in 1 signals
Pull
U/D
1 CD_Left
IA - - 1 2 CD_GND
IA - - 3 CD_GND
IA - - 4 CD_Right
IA - -
1
4.13 Audio Connectors
The onboard Audio circuit implements 7.1+2 Channel High Definition Audio, featuring ten 24-bit stereo DACs
and two 20-bit stereo ADCs. The Audio signals are made available on the Frontpanel connectors (Line in /
Line out / MIC) and the onboard AUDIO_HEAD and CDROM Audio input connectors.
4.13.1 Audio Line-In, Line-Out and Microphone
Audio Line-in, Line-out and Microphone are available in the audiojack connectors.
4.13.2 CDROM Audio Input (CDROM)
CD-ROM audio input may be connected to this connector. It may also be used as a secondary line-in signal.
PIN# Signal Type Ioh/Iol
Note 1: The definition of which pins are use for the Left and Right channels is not a worldwide accepted
standard. Some CDROM cable kits expect reverse pin order.
Signal Description
CD_Left
CD_Right
CD_GND Analogue GND for Left and Right CD.
Left and right CD audio input lines or secondary Line-in.
(This analogue GND is not shorted to the general digital GND on the board).
Note
KTD-00774-G KTUS15/mITX Page 41 of 84
Pull
U/D
Ioh/
Iol
Ioh/
Iol
Pull
U/D
LFE-OUT
1 2 CEN-OUT
AAGND
3 4 AAGND
FRONT-OUT-L
5 6 FRONT-OUT-R
AAGND
7 8 AAGND
REAR-OUT-L
9 10 REAR-OUT-R
SIDE-OUT-L
11
12 SIDE-OUT-R
AAGND
13
14 AAGND
MIC1-L
15
16 MIC1-R
AAGND
17
18 AAGND
LINE1-IN-L
19
20 LINE1-IN-R
NC
21
22 AAGND
- -
PWR
GND
23
24 SPDIF-IN
SPDIF-OUT
25
26 GND
PWR - -
4.13.3 Audio Header (AUDIO_HEAD)
Note
Signal Description Note
FRONT-OUT-L Front Speakers (Speaker Out Left).
FRONT-OUT-R Front Speakers (Speaker Out Right).
REAR-OUT-L Rear Speakers (Surround Out Left).
REAR-OUT-R
SIDE-OUT-L Side speakers (Surround Out Left)
SIDE-OUT-R Side speakers (Surround Out Right)
CEN-OUT Center Speaker (Center Out channel).
LFE-OUT
NC No connection
MIC1 MIC Input 1
LINE1-IN Line in 1 signals
F-SPDIF-IN S/PDIF Input
F-SPDIF-OUT S/PDIF Output
AAGND Audio Analogue ground
Type Signal PIN# Signal Type
Rear Speakers (Surround Out Right).
Subwoofer Speaker (Low Freq. Effect Out).
Note
KTD-00774-G KTUS15/mITX Page 42 of 84
Pull
U/D
1 CONTROL
O - - 2 SENSE
I
-
4K7 3 +12V
PWR
- -
4 GND
PWR
- -
Pull
U/D
-
2 SENSE
I
-
4K7 3 +12V
PWR
- -
4 GND
PWR
- -
Signal
Description
+12V supply for fan, can be turned on/off or modulated (PWM) by the chipset.
A maximum of 2000mA can be supplied from this pin.
4.14 Fan Connector (FAN_CPU)
The FAN_CPU is used for the connection of the FAN for the CPU or the System.
The 4pin header supports connection of 3-pin FAN, but it is recommended to use the 4-pin type for optimized
FAN speed control. The 3- or 4-pin mode is set in the BIOS setup menu.
4-pin Mode:
PIN# Signal Type Ioh/Iol
Signal Description
CONTROL PWM signal for FAN speed control
SENSE Tacho signal from the fan for supervision. The signals shall be generated by an open
collector transistor or similar. Onboard is a pull-up resistor 4K7 to +12V. The signal has to
be pulsed, typically twice per rotation.
12V +12V supply for fan. A maximum of 2000mA can be supplied from this pin.
GND Power Supply GND signal
3-pin Mode:
PIN# Signal Type Ioh/Iol
Note
Note
SENSE Tacho signal from the fan for supervision. The signals shall be generated by an open
collector transistor or similar. Onboard is a pull-up resistor 4K7 to +12V. The signal has to
be pulsed, typically twice per rotation.
12V
GND Power Supply GND signal
KTD-00774-G KTUS15/mITX Page 43 of 84
Boot BIOS Recovery Module
•
<-- pin 1
Boot onboard BIOS (Normal)
•
Jumper in Clear CMOS position
• (Only for 10 – 30 seconds)
Jumper normal position
•
<-- pin 1
4.15 Boot ROM Selection Jumper (BOOT ROM)
The Boot ROM Selection Jumper shall only be moved from the Normal position (Boot onboard BIOS) in case
the BIOS is corrupted and has to be recovered by use of the KT-BIOS-Recovery-Module.
PWR connector
4.16 Clear CMOS Jumper (Clr-CMOS)
The Clr-CMOS Jumper is used to clear the CMOS content. (Not supported on KTUS15 boards having PN
6172xxxx or below, instead turnoff power and remove Battery for a minimum of 10 seconds).
LAN connector
To clear all CMOS settings, including Password protection, turn off power and move the CMOS_CLR jumper to
pin 2-3 for 10 – 30 seconds.
WARNING: Don’t leave the jumper in Clear CMOS position, otherwise the battery will fully depleted within a
few days.
KTD-00774-G KTUS15/mITX Page 44 of 84
Pull
U/D
Pull
U/D
- -
PWR
LPC CLK
1 2 GND
- -
PWR
LPC FRAME#
3 KEY
LPC RST#
5 6 +5V
LPC AD3
7 8 LPC AD2
+3V3
9
10
LPC AD1
LPC AD0
11
12
GND
SMB_CLK
13
14
SMB_DATA
SB3V3
15
16
LPC SERIRQ
GND
17
18
CLKRUN#
SUS_STAT#
19
20
NC
4.17 TPM Connector (TPM)
Note
The TPM connector is only used in case the onboard BIOS is corrupted and has to be recovered by use of a
KT-BIOS-Recovery-Module.
Ioh/Iol Type Signal PIN Signal Type Ioh/Iol
Note
KTD-00774-G KTUS15/mITX Page 45 of 84
Pull
U/D
Ioh/
Iol
Ioh/
Iol
Pull
U/D
USB10/11_5V
1 2 USB10/11_5V
USB1-
3 4 USB3-
USB1+
5 6 USB3+
- -
PWR
GND
7 8 GND
PWR - - - - - NC
9 10 LINE2-IN-L
- - - - -
PWR
+5V
11
12 +5V
PWR - -
OC
HD_LED
13
14 SUS_LED
- -
PWR
GND
15
16 PWRBTN_IN#
RSTIN#
17
18 GND
PWR - - SB3V3
19
20 LINE2-IN-R
- - - AGND
21
22 AGND
1 MIC2-L
23
24 MIC2-R
1
5V supply for external devices. SB5V is supplied during powerdown to allow wakeup
on USB device activity. Protected by resettable 1.1A fuse covering both USB ports.
4.18 Front Panel Connector (FRONTPNL)
Note
Note 1: Unsupported input, leave it unconnected.
Signal Description
USB10/11_5V
USB1+
USB1-
USB3+
USB3-
+5V
HD_LED Hard Disk Activity LED (active low signal). Output is via 475Ω to OC.
SUS_LED Suspend Mode LED (active high signal). Output is via 475Ω.
PWRBTN_IN# Power Button In. Toggle this signal low to start the ATX / BTX PSU and boot the board.
RSTIN#
LINE2-IN Line in 2 signals
MIC2
SB3V3 Standby 3.3V voltage
AGND Analogue Ground for Audio
Type
Universal Serial Bus Port 1 Differentials: Bus Data/Address/Command Bus.
Universal Serial Bus Port 3 Differentials: Bus Data/Address/Command Bus.
Maximum load is 1A or 2A per pin if using IDC connector flat cable or crimp terminals
respectively.
Reset Input. When pulled low for a minimum 16ms, the reset process will be initiated.
The reset process continues even though the Reset Input is kept low.
MIC2-L and MIC2-R are unsupported. Leave these terminals unconnected.
Signal PIN# Signal Type
Note
KTD-00774-G KTUS15/mITX Page 46 of 84
Pull
U/D
Ioh/
Iol
Ioh/
Iol
Pull
U/D
2
2M/ - I
INTRUDER#
1 2 GND
PWR - - NC
3 4 PSUP_OFF
OC -
100K I
POWER_UP
5 6 SB5V
PWR - - - -
PWR
SB3V3
7 8 EXT_BAT
PWR - - - -
PWR
+5V
9 10 GND
PWR - - 1
4K7/
/12mA
IOT
GPIO0
11
12 GPIO1
IOT
/12mA
4K7/ 1 1
4K7/
/12mA
IOT
GPIO2
13
14 GPIO3
IOT
/12mA
4K7/ 1 1
4K7/
/12mA
IOT
GPIO4
15
16 GPIO5
IOT
/12mA
4K7/ 1 1
4K7/
/12mA
IOT
GPIO6
17
18 GPIO7
IOT
/12mA
4K7/ 1 - -
PWR
GND
19
20 FAN3OUT
O 4K7 3 FAN3IN
21
22 +12V
PWR - - TEMP3IN
23
24 VREF
- -
PWR
GND
25
26 IRRX
IRTX
27
28 GND
PWR - - 1
4K7/
SMBC
29
30 SMBD
4K7/
1
INTRUDER, may be used to detect if the system case has been opened. This signal’s
status is readable, so it may be used like a GPI when the Intruder switch is not required.
POWER UP, input signal has pull-up resistor to Vin. By adding resistor to ground
(PWR)”.
(EXTernal BATtery) option for connecting + terminal of an external primary cell battery
against charging and can be used with or without the onboard battery installed.
General Purpose Inputs / Output. These Signals may be controlled or monitored through
the use of the KT-API-V2 (Application Programming Interface).
Temperature sensor 3 input. (Recommended: Transistor 2N3904, having emitter
a resistor 30K/1% shall be connected between pin 23 - 24. (Precision +/- 3ºC).
4.19 Feature Connector (FEATURE)
Note
Note 1: Pull-up to +3V3Dual (+3V3 or SB3V3). Note 2: Pull-up to onboard Battery. Note 3: Pull-up to +3V3.
Signal Description
INTRUDER#
NC No Connection
PSUP_OFF
Power SUpply OFF open collector output signal can be used as PSON input to an ATX
PSU to keep it turned on until this signal gets inactive (Windows Shutdown etc.)
Type Signal PIN# Signal Type
Note
POWER_UP
SB5V StandBy +5V supply.
SB3V3 Max. load is 0.75A (1.5A < 1 sec.)
EXT_BAT
+5V Max. load is 0.75A (1.5A < 1 sec.)
GPIO0..7
FAN3OUT
FAN3IN FAN3 Input. 0V to +3V3 amplitude Fan 3 tachometer input.
+12V Max. load is 0.75A (1.5A < 1 sec.)
TEMP3IN
VREF Voltage REFerence, reference voltage to be used with TEMP3IN input.
IRRX IR Receive input (IrDA 1.0, SIR up to 1.152K bps)
IRTX IR Transmit output (IrDA 1.0, SIR up to 1.152K bps)
SMBC SMBus Clock signal
SMBD SMBus Data signal
(threshold voltage ~1.5V) the minimum Vin can be programmed. If the input is lower than
threshold voltage the board does not turn on. See also note in chapter “Power Connector
(2.5 - 4.0 V) ( – terminal connected to GND etc. pin 10). The external battery is protected
FAN 3 speed control OUTput. This 3.3V PWM signal can be used as Fan control voltage
(0–3.3V DC in 128 steps) via a Fan Driver Circuit (not included) to program Fan voltage.
For more info, see W83627 datasheet. Default PMW output is 127 (100% = 3.3V).
connected to GND (pin 25), collector and basis shorted and connected to pin 23. Further
KTD-00774-G KTUS15/mITX Page 47 of 84
Terminal
S C
PWR
-12V
F01
E01
TRST#
O
O TCK
F02
E02
+12V
PWR
PWR
GND
F03
E03
TMS
O I TDO
F04
E04
TDI O PWR
+5V
F05
E05
+5V
PWR
PWR
+5V
F06
E06
INTA#
I
I INTB#
F07
E07
INTC#
I
I INTD#
F08
E08
+5V
PWR I REQ2#
F09
E09
CLKC
O I REQ3#
F10
E10
+5V (I/O)
PWR
OT
GNT2#
F11
E11
CLKD
O
PWR
GND
F12
E12
GND
PWR
PWR
GND
F13
E13
GND
PWR
O CLKA
F14
E14
GNT3#
OT
PWR
GND
F15
E15
RST#
O O CLKB
F16
E16
+5V (I/O)
PWR
PWR
GND
F17
E17
GNT0#
OT I REQ0#
F18
E18
GND
PWR
PWR
+5V (I/O)
F19
E19
REQ1#
I
IOT
AD31
F20
E20
AD30
IOT
IOT
AD29
F21
E21
+3.3V
PWR
PWR
GND
F22
E22
AD28
IOT
IOT
AD27
F23
E23
AD26
IOT
IOT
AD25
F24
E24
GND
PWR
PWR
+3.3V
F25
E25
AD24
IOT
IOT
C/BE3#
F26
E26
GNT1#
OT
IOT
AD23
F27
E27
+3.3V
PWR
PWR
GND
F28
E28
AD22
IOT
IOT
AD21
F29
E29
AD20
IOT
IOT
AD19
F30
E30
GND
PWR
PWR
+3.3V
F31
E31
AD18
IOT
IOT
AD17
F32
E32
AD16
IOT
IOT
C/BE2#
F33
E33
+3.3V
PWR
PWR
GND
F34
E34
FRAME#
IOT
IOT
IRDY#
F35
E35
GND
PWR
PWR
+3.3V
F36
E36
TRDY#
IOT
IOT
DEVSEL#
F37
E37
GND
PWR
PWR
GND
F38
E38
STOP#
IOT
IOT
LOCK#
F39
E39
+3.3V
PWR
IOT
PERR#
F40
E40
SDONE
IO
PWR
+3.3V
F41
E41
SB0#
IO
IOC
SERR#
F42
E42
GND
PWR
PWR
+3.3V
F43
E43
PAR
IOT
IOT
C/BE1#
F44
E44
AD15
IOT
IOT
AD14
F45
E45
+3.3V
PWR
PWR
GND
F46
E46
AD13
IOT
IOT
AD12
F47
E47
AD11
IOT
IOT
AD10
F48
E48
GND
PWR
PWR
GND
F49
E49
AD09
IOT
SOLDER SIDE
COMPONENT SIDE
IOT
AD08
F52
E52
C/BE0#
IOT
IOT
AD07
F53
E53
+3.3V
PWR
PWR
+3.3V
F54
E54
AD06
IOT
IOT
AD05
F55
E55
AD04
IOT
IOT
AD03
F56
F56
GND
PWR
PWR
GND
F57
E57
AD02
IOT
IOT
AD01
F58
E58
AD00
IOT
PWR
+5V (I/O)
F59
E59
+5V (I/O)
PWR
IOT
ACK64#
F60
E60
REQ64#
IOT
PWR
+5V
F61
E61
+5V
PWR
PWR
+5V
F62
E62
+5V
PWR
4.20 PCI Slot Connector (PCI Slot)
Note Type Signal
Signal Type Note
KTD-00774-G KTUS15/mITX Page 48 of 84
SYSTEM PINS
Clock provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals,
timing parameters are defined with respect to this edge. PCI operates at 33MHz.
Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state. What effect
required to boot the system will respond after reset.
ADDRESS AND DATA
Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase
IRDY# and TRDY# are asserted.
Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a
meaningful data. C/BE[0]# applies to byte 0 (lsb) and C/BE[3]# applies to byte 3 (msb).
Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents.
has the same timing as AD[31::00], but it is delayed by one clock.) The master drives PAR for address and
write data phases; the target drives PAR for read data phases.
INTERFACE CONTROL PINS
Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME#
When FRAME# is deasserted, the transaction is in the final data phase or has completed.
Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data phase of
both IRDY# and TRDY# are asserted together.
Target Ready indicates the target agent’s (selected device’s) ability to complete the current data phase of
both IRDY# and TRDY# are asserted together.
Stop indicates the current target is requesting the master to stop the current transaction.
Lock indicates an atomic operation that may require multiple transactions to complete. When LOCK# is
retains ownership of LOCK#. If a device implements Executable Memory, it should also implement LOCK#
must provide exclusion to a minimum of 16 bytes (aligned). Host bridges that have system memory behind
them should implement LOCK# as a target from the PCI bus point of view and optionally as a master.
Initialization Device Select is used as a chip select during configuration read and write transactions.
Device Select, when actively driven, indicates the driving device has decoded its address as the target of
the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.
4.20.1 Signal Description – PCI Slot Connector
CLK
RST#
AD[31::00]
C/BE[3::0]#
PAR
except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on the risingedge of CLK and all other
RST# has on a device beyond the PCI sequencer is beyond the scope of this specification, except for
reset states of required PCI configuration registers. Anytime RST# is asserted, all PCI output signals must
be driven to their benign state. In general, this means they must be asynchronously tri-stated. SERR#
(open drain) is floated. REQ# and GNT# must both be tri-stated (they cannot be driven low or high during
reset). To prevent AD, C/BE#, and PAR signals from floating during reset, the central resource may drive
these lines during reset (bus parking) but only to a logic low level–they may not be driven high.
RST# may be asynchronous to CLK when asserted or deasserted. Although asynchronous, deassertion is
guaranteed to be a clean, bounce-free edge. Except for configuration accesses, only devices that are
followed by one or more data phases. PCI supports both read and write bursts.
The address phase is the clock cycle in which FRAME# is asserted. During the address phase AD[31::00]
contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a
DWORD address. During data phases AD[07::00] contain the least significant byte (lsb) and AD[31::24]
contain the most significant byte (msb). Write data is stable and valid when IRDY# is asserted and read
data is stable and valid when TRDY# is asserted. Data is transferred during those clocks where both
transaction, C/BE[3::0]# define the bus command. During the data phase C/BE[3::0]# are used as Byte
Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry
PAR is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one
clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction.
Once PAR is valid, it remains valid until one clock after the completion of the current data phase. (PAR
FRAME#
is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue.
IRDY#
the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both
IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on
AD[31::00]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until
TRDY#
the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock both
TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that valid data is present on
AD[31::00]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until
STOP#
LOCK#
asserted, non-exclusive transactions may proceed to an address that is not currently locked. A grant to
start a transaction on PCI does not guarantee control of LOCK#. Control of LOCK# is obtained under its
own protocol in conjunction with GNT#. It is possible for different agents to use PCI while a single master
and guarantee complete access exclusion in that memory. A target of an access that supports LOCK#
IDSEL
DEVSEL#
(Continues)
KTD-00774-G KTUS15/mITX Page 49 of 84
ARBITRATION PINS (BUS MASTERS ONLY)
Request indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. Every
master has its own REQ# which must be tri-stated while RST# is asserted.
Grant indicates to the agent that access to the bus has been granted. This is a point to point signal. Every
buffer.
ERROR REPORTING PINS.
The error reporting pins are required by all devices and maybe asserted when enabled
Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special
when a data parity error may be lost or when reporting of an error may be delayed. An agent cannot report
or is the master of the current transaction.
System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or
system does so anytime SERR# is sampled asserted.
INTERRUPT PINS (OPTIONAL).
drivers. The assertion and deassertion of INTx# is asynchronous to CLK. A device asserts its INTx# line when requesting
only INTA# may be used while the other three interrupt lines have no meaning.
Interrupt A is used to request an interrupt.
Interrupt B is used to request an interrupt and only has meaning on a multi-function device.
Interrupt C is used to request an interrupt and only has meaning on a multi-function device.
Interrupt D is used to request an interrupt and only has meaning on a multi-function device.
Board type
Slot
IDSEL
INTA
INTB
INTC
INTD
KTUS15/mITX
1
AD16
INT_PIRQ#A
INT_PIRQ#B
INT_PIRQ#C
INT_PIRQ#D
REQ#
GNT#
PERR#
SERR#
master has its own GNT# which must be ignored while RST# is asserted.
While RST# is asserted, the arbiter must ignore all REQ# lines since they are tri-stated and do not contain
a valid request. The arbiter can only perform arbitration after RST# is deasserted. A master must ignore
its GNT# while RST# is asserted. REQ# and GNT# are tri-state signals due to power sequencing
requirements when 3.3V or 5.0V only add-in boards are used with add-in boards that use a universal I/O
Cycle. The PERR# pin is sustained tri-state and must be driven active by the agent receiving data two
clocks following the data when a data parity error is detected. The minimum duration of PERR# is one
clock for each data phase that a data parity error is detected. (If sequential data phases each have a data
parity error, the PERR# signal will be asserted for more than a single clock.) PERR# must be driven high
for one clock before being tri-stated as with all sustained tri-state signals. There are no special conditions
a PERR# until it has claimed the access by asserting DEVSEL# (for a target) and completed a data phase
any other system error where the result will be catastrophic. If an agent does not want a non-maskable
interrupt (NMI) to be generated, a different reporting mechanism is required. SERR# is pure open drain
and is actively driven for a single PCI clock by the agent reporting the error. The assertion of SERR# is
synchronous to the clock and meets the setup and hold times of all bused signals. However, the restoring
of SERR# to the deasserted state is accomplished by a weak pullup (same value as used for s/t/s) which
is provided by the system designer and not by the signaling agent or central resource. This pull-up may
take two to three clock periods to fully restore SERR#. The agent that reports SERR#s to the operating
Interrupts on PCI are optional and defined as “level sensitive,” asserted low (negative true), using open drain output
attention from its device driver. Once the INTx# signal is asserted, it remains asserted until the device driver clears the
pending request. When the request is cleared, the device deasserts its INTx# signal. PCI defines one interrupt line for a
single function device and up to four interrupt lines for a multi-function device or connector. For a single function device,
INTA#
INTB#
INTC#
INTD#
4.20.2 KTUS15 PCI IRQ & INT routing
When using the 820982 “PCI Riser - Flex - 2slot w. arbiter” the lower slot has IDSEL / IRQs routed straight
through and the top slot has the routing: IDSEL=AD30, INT_PIRQ#D, INT_PIRQ#A, INT_PIRQ#B,
INT_PIRQ#C.
KTD-00774-G KTUS15/mITX Page 50 of 84
Onboard Connectors
Mating Connectors
Manufacturer
Type no.
Manufacturer
Type no.
FAN_CPU
Foxconn
HF2704E-M1
AMP
1375820-4 (4-pole)
AMP
1470947-1
AMP
1375820-3 (3-pole)
KBDMSE
Molex
22-23-2061
Molex
22-01-2065
CDROM
Foxconn
HF1104E
Molex
50-57-9404
Molex
70543-0038
SATA0-1
Molex
47155-4001
Molex
67489-8005
Kontron
KT 821035 (cable kit)
PWR
Molex
43045-1201
Molex
43025-1200
KT 1022-6309 (cable kit
for ATX PSU)
PWR-OUT
Molex
22-23-2041
Molex
22-01-2046
Kontron
KT 1027-3669 (cable kit)
COM1, 2, 3, 4
Wuerth
61201020621
Molex
90635-1103
Kontron
KT 821016 (cable kit)
Kontron
KT 821017 (cable kit)
USB1/USB3 (*)
(FRONTPNL)
-
Kontron
KT 821401 (cable kit)
PRINTER
Foxconn
HL2213F
Molex
90635-1263
Kontron
KT 821031 (cable kit)
AUDIO_HEAD
Molex
87831-2620
Molex
51110-2651
Kontron
KT 821043 (cable kit)
FRONTPNL
Pinrex
512-90-24GBB3
Molex
90635-1243
Kontron
KT 821042 (cable kit)
FEATURE
Molex
87831-3020
Molex
51110-3051
Kontron
KT 821041 (cable kit)
LVDS
Don Connex
C44-40BSB1-G
Don Connex
A32-40-C-G-B-1
Kontron
KT 821515 (cable kit)
Kontron
KT 821155 (cable kit)
5 Onboard connectors and Mating connectors
Connector
Kontron
* USB1/USB3 are located in FRONTPNL connector. Depending on application the KT821401 can be used.
Note: Only one connector will be mentioned for each type of onboard connector even though several types
with same fit, form and function are approved and could be used as alternative. Please also notice that
standard connectors like DVI, PCIe, PCI, CF, Ethernet and USB is not included in the list.
KTD-00774-G KTUS15/mITX Page 51 of 84
Address (hex)
Size
Description
00000000
0009FFFF
655360
System board
000A0000
000BFFFF
131072
PCI-bus
000A0000
000BFFFF
131072
Intel(R) Graphics Media Accelerator 500
000C0000
000CFFFF
65536
System board
000D0000
000DFFFF
65536
PCI-bus
000E0000
000FFFFF
131072
System board
00100000
3F7FFFFF
1064304640
System board
3F800000
3FFFFFFF
8388608
Motherboard resources
3F800000
DFFFFFFF
2692743168
PCI-bus
40000000
7FFFFFFF
1073741824
Motherboard resources
CFB00000
CFBFFFFF
1048576
PCI standard PCI to PCI-bridge
CFB00000
CFCFFFFF
2097152
PCI standard PCI to PCI-bridge
CFB00000
CFDFFFFF
3145728
Intel(R) SCH Family PCI Express Root Port 1 - 8110
CFBFE000
CFBFFFFF
8192
Standard Dual Channel PCI IDE-controller
CFC00000
CFCFFFFF
1048576
PCI standard PCI to PCI-bridge
CFCDC000
CFCDFFFF
16384
Intel(R) 82574L Gigabit Network Connection
CFCE0000
CFCFFFFF
131072
Intel(R) 82574L Gigabit Network Connection
CFDE0000
CFDFFFFF
131072
PCI standard PCI to PCI-bridge
D0000000
D7FFFFFF
134217728
Intel(R) Graphics Media Accelerator 500
DFF5B000
DFF5B0FF
256
SDA Standard Compliant SD Host Controller
DFF5B400
DFF5B4FF
256
SDA Standard Compliant SD Host Controller
DFF5B800
DFF5B8FF
256
SDA Standard Compliant SD Host Controller
DFF5BC00
DFF5BFFF
1024
Intel(R) SCH Family USB2 Enhanced Host Controller - 8117
DFF5C000
DFF5FFFF
16384
Microsoft UAA-bus driver for High Definition Audio
DFF60000
DFF7FFFF
131072
Intel(R) Graphics Media Accelerator 500
DFF80000
DFFFFFFF
524288
Intel(R) Graphics Media Accelerator 500
E0000000
EFFFFFFF
268435456
Motherboard resources
F0000000
F0003FFF
16384
Motherboard resources
F0000000
FFFFFFFF
268435456
PCI Bus
FEC00000
FEC00FFF
4096
Motherboard resources
FED00000
FED003FF
1024
High Precision Event Timer
FEE00000
FEE00FFF
4096
Motherboard resources
FF800000
FFBFFFFF
4194304
Intel(R) 82802 Firmware Hub Device
FFC00000
FFFFFFFF
4194304
Intel(R) 82802 Firmware Hub Device
6 System Resources
6.1 Memory Map
KTD-00774-G KTUS15/mITX Page 52 of 84
Bus
#
Device
#
Function
#
Vendor
ID
Device
ID
Chip
Device Function
4 0 0
8086
10D3
82574L
Gigabit Network Connection
0
29 7 8086
8117
US15W
Enhanced USB2 Controller
0
27 0 8086
811B
US15W
High Definition Audio Controller
0 0 0
8686
8100
US15W
Host Bridge
0 2 0
8086
8108
US15W
Integrated 3D Graphics
0
31 0 8086
8119
US15W
LPC Interface
0
31 1 8086
811A
US15W
Parallel ATA Controller
0
28 0 8086
8110
US15W
PCI Express Port 1
0
28 1 8086
8112
US15W
PCI Express Port 3
0
30 0 8086
811C
US15W
SDIO/MMC Controller 3
0
30 1 8086
811D
US15W
SDIO/MMC Controller 3
0
30 2 8086
811E
US15W
SDIO/MMC Controller 3
0
29 0 8086
8114
US15W
USB Universal Host Controller
0
29 1 8086
8115
US15W
USB Universal Host Controller
0
29 2 8086
8116
US15W
USB Universal Host Controller
3 0 0
197B
2363
JMB363
SATA-II RAID Controller
7 0 0
10B5
8112
PEX 8112
PCI Express-to-PCI Bridge
1 0 0
10B5
8505
PEX 8505
5-Lane 5-Port PCI Express 1.1 Switch
2 1 0
10B5
8505
PEX 8505
5-Lane 5-Port PCI Express 1.1 Switch
2 2 0
10B5
8505
PEX 8505
5-Lane 5-Port PCI Express 1.1 Switch
2 3 0
10B5
8505
PEX 8505
5-Lane 5-Port PCI Express 1.1 Switch
2 4 0
10B5
8505
PEX 8505
5-Lane 5-Port PCI Express 1.1 Switch
6.2 PCI Devices
KTD-00774-G KTUS15/mITX Page 53 of 84
IRQ
Notes
NMI
IRQ0
X IRQ1
X IRQ2
IRQ3
X X IRQ4
X X IRQ5
IRQ6
IRQ7
X
manual OS selection
IRQ8
X IRQ9
X IRQ10
X IRQ11
X IRQ12
IRQ13
X IRQ14
IRQ15
IRQ16
X X X X IRQ17
X X X X X IRQ18
X X X X IRQ19
X X IRQ20
X IRQ21
IRQ22
IRQ23
IRQ24
IRQ25
IRQ26
6.3 Interrupt Usage
System timer
Keyboard
Communications port (COM2)
Communications port (COM1)
System CMOS/real-time watch
Microsoft ACPI-compatible system
Numerical Data Processor
SDA Standard Compliant SD Host Controller (x 3)
Intel(R) SCH Family USB Universal Host Controller - 8114
Intel(R) SCH Family PCI Express Root Port 1 - 8110
Microsoft UAA-bus driver for High Definition Audio
PCI standard PCIfor PCI-bro (X 5)
Intel(R) Graphics Media Accelerator 500
Intel(R) 82574L Gigabit Network Connection
Standard Dual Channel PCI IDE-controller
Intel(R) SCH Family USB Universal Host Controller - 8115
Intel(R) SCH Family PCI Express Root Port 3 - 8112
Intel(R) SCH Family USB2 Enhanced Host Controller - 8117
Selectable in BIOS
KTD-00774-G KTUS15/mITX Page 54 of 84
Address range (hex)
Size
Description
0
cf7
3320
PCI-bus
10
001f
16
Motherboard resources
20
21
2
Programmable interrupt controller
22
3f
30
Motherboard resources
40
43
4
System timer
44
5f
28
Motherboard resources
60
60
1
Standard Keyboard
61
61
1
System Speaker
63
63
1
Motherboard resources
64
64
1
Standard Keyboard
65
65
1
Motherboard resources
67
6f
9
Motherboard resources
70
71
2
System CMOS/Real time clock
72
7f
14
Motherboard resources
80
80
1
Motherboard resources
84
86
3
Motherboard resources
88
88
1
Motherboard resources
8c
8e
3
Motherboard resources
90
9f
16
Motherboard resources
a0
a1
2
Programmable interrupt controller
a2
bf
30
Motherboard resources
e0
ef
16
Motherboard resources
f0
ff
16
Numeric data processor
170
177
8
Secondary IDE-canal
1f0
1f7
8
Primary IDE-canal
274
277
4
ISAPNP read data port
279
279
1
ISAPNP read data port
2f8
2ff
8
Communications port (COM2)
376
376
1
Secondary IDE-canal
378
37f
8
Printer port (LPT1)
3b0
3bb
12
Intel(R) Graphics Media Accelerator 500
3c0
3df
32
Intel(R) Graphics Media Accelerator 500
3f6
3f6
1
Primary IDE-canal
3f8
3ff
8
Communications port (COM1)
400
43f
64
Motherboard resources
480
4BF
64
Motherboard resources
04D0
04D1
2
Motherboard resources
900
09F3
244
Motherboard resources
0A00
0A0F
16
Motherboard resources
0A10
0A1F
16
Motherboard resources
0A79
0A79
1
ISAPNP read data port
0D00
FFFF
62208
PCI-bus
C000
DFFF
8192
PCI standard PCI to PCI-bridge
C000
DFFF
8192
Intel(R) SCH Family PCI Express Root Port 1 - 8110
C000
DFFF
8192
PCI standard PCI to PCI-bridge
C080
C087
8
Standard Dual Channel PCI IDE
C480
C483
4
Standard Dual Channel PCI IDE
C880
C887
8
Standard Dual Channel PCI IDE
CE80
CE8F
16
Standard Dual Channel PCI IDE
CF00
CF03
4
Standard Dual Channel PCI IDE
D000
DFFF
4096
PCI standard PCI to PCI-bridge
D880
D89F
32
Intel(R) 82574L Gigabit Network Connection
E080
E09F
32
Intel(R) SCH Family USB Universal Host Controller - 8115
E480
E49F
32
Intel(R) SCH Family USB Universal Host Controller - 8114
E880
E887
8
Intel(R) Graphics Media Accelerator 500
EF00
EF1F
32
Intel(R) SCH Family USB Universal Host Controller - 8116
FFA0
FFAF
16
Standard Dual Channel PCI IDE-controller
6.4 IO Map
KTD-00774-G KTUS15/mITX Page 55 of 84
Overview of BIOS Features
This section details specific BIOS features for the KTUS15 board.
The KTUS15 board is based on the AMI BIOS core version 8.10 with Kontron BIOS extensions.
6.5 System Management BIOS (SMBIOS/DMI)
SMBIOS is a Desktop Management Interface (DMI) compliant method for managing computers in a
managed network.
The main component of SMBIOS is the Management Information Format (MIF) database, which contains
information about the computing system and its components. Using SMBIOS, a system administrator can
obtain the system types, capabilities, operational status, and installation dates for system components.
The MIF database defines the data and provides the method for accessing this information. The BIOS
enables applications such as third-party management software to use SMBIOS.
The BIOS stores and reports the following SMBIOS information:
• BIOS data, such as the BIOS revision level
• Fixed-system data, such as peripherals, serial numbers, and asset tags
• Resource data, such as memory size, cache size, and processor speed
• Dynamic data, such as event detection and error logging
Non-Plug and Play operating systems, such as Windows NT*, require an additional interface for obtaining
the SMBIOS information. The BIOS supports an SMBIOS table interface for such operating systems. Using
this support, an SMBIOS service-level application running on a non-Plug and Play operating system can
obtain the SMBIOS information.
6.6 Legacy USB Support
Legacy USB support enables USB devices such as keyboards, mice, and hubs to be used even when the
operating system’s USB drivers are not yet available. Legacy USB support is used to access the BIOS Setup
program, and to install an operating system that supports USB. By default, Legacy USB support is set to
Enabled.
Legacy USB support operates as follows:
1. When you apply power to the computer, legacy support is disabled.
2. POST begins.
3. Legacy USB support is enabled by the BIOS allowing you to use a USB keyboard to enter and
configure the BIOS Setup program and the maintenance menu.
4. POST completes.
5. The operating system loads. While the operating system is loading, USB keyboards and mice are
recognized and may be used to configure the operating system. (Keyboards and mice are not
recognized during this period if Legacy USB support was set to Disabled in the BIOS Setup
program.)
6. After the operating system loads the USB drivers, all legacy and non-legacy USB devices are
recognized by the operating system, and Legacy USB support from the BIOS is no longer used.
To install an operating system that supports USB, verify that Legacy USB support in the BIOS Setup
program is set to Enabled and follow the operating system’s installation instructions.
KTD-00774-G KTUS15/mITX Page 56 of 84
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Security
Chipset
Exit
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Security
Chipset
Exit
System Overview
Use [ENTER], [TAB] or
v02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
System Time
HH:MM:SS
Set the system time.
System Date
MM/DD/YYYY
Set the system date.
7 BIOS Configuration/Setup
7.1 Introduction
The BIOS Setup is used to view and configure BIOS settings for the KTUS15 board. The BIOS Setup is
accessed by pressing the DEL key after the Power-On Self-Test (POST) memory test begins and before the
operating system boot begins. The Menu bar looks like this:
The available keys for the Menu screens are:
Select Menu: <←> or <→>
Select Item: <↑> or <↓>
Select Field: <Tab>
Change Field: <+> or <->
Help: <F1>
Save and Exit: <F10>
Exits the Menu: <Esc>
Please note that in the following the different BIOS Features will be described as having some options.
These options will be selected automatically when loading either Failsafe Defaults or Optimal Defaults. The
Default options will be indicated by the option in bold, but please notice that when Failsafe Defaults are
loaded a few of the options, marked with “*”, are now the default option.
7.2 Main Menu
AMIBIOS
Version : 08.00.15
Build Date: 07/21/11
ID : KTUS1519
PCB ID : 45
Serial # : 00760891
Part # : 61750200
Processor
Intel® Atom ™ CPU Z530 @ 1.6GHz
Speed : 1600MHz
System Memory
Size : 1015MB
System Time [10:18:15]
System Date [Mon 13/02/2012]
[SHIFT-TAB] to select a
field.
Use [+] or [-] to
configure system Time.
<-> Select Screen
|| Select Item
+- Change Field
Tab Select Field
F1 General Help
F10 Save and Exit
ESC Exit
KTD-00774-G KTUS15/mITX Page 57 of 84
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Security
Chipset
Exit
Advanced Settings
Configure CPU.
v02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
7.3 Advanced Menu
Warning: Setting wrong values in below sections
may cause system to malfunction.
► CPU Configuration
► IDE Configuration
► LAN Configuration
► SuperIO Configuration
► Hardware Health Configuration
► Voltage Monitor
► ACPI Configuration
► PCI Express Configuration
► Smbios Configuration
► Remote Access Configuration
► Trusted Computing
► USB Configuration
Spread Spectrum Clock [Disabled]
<- Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
KTD-00774-G KTUS15/mITX Page 58 of 84
BIOS SETUP UTILITY
Advanced
Configure advanced CPU settings
Module Version: 3F.12
Disabled for WindowsXP
Disable Bit Capability [Enabled]
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Max CPUID Value Limit
Enabled
Disabled
Disabled for WindowsXP
Intel® Virtualization Tech
Enabled
Disabled
Execute-Disable Bit Capability
Enabled
Disabled
When disabled, force the XD feature flag to always
return 0.
Hyper Threading Technology
Disabled
Enabled for Windows XP and Linux4(OS optimized
Technology)
Intel® SpeedStep™ tech
Disabled
Disabled: Disable GV3
Intel® C-STATE tech
Disabled
Enabled
CState: CPU idle is set to C2 C3 C4 State
Enhanced C-States
Disabled
Enabled
CState: CPU idle is set to Enhanced C-States.
7.3.1 Advanced settings – CPU Configuration
Manufacturer: Intel
Intel® Atom™ CPU Z530 @ 1.60Ghz
Frequency : 1.59Ghz
FSB Speed : 533Mhz
Cache L1 : 24 KB
Cache L2 : 512 KB
Speed : 1600MHz
Ratio Actual Value:12
Max CPUID Value Limit [Disabled]
Intel® Virtualization Tech [Enabled]
ExecuteHyper Threading Technology [Enabled]
Intel® SpeedStep™ tech [Enabled]
Intel® C-STATE tech [Enabled]
Enhanced C-States [Enabled]
<-> Select Screen
|| Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
Enabled
Enabled
for Hyper Threading Technology) and disabled for
other OS (OS not optimized for Hyper-Threading
Enabled: Enable GV3
KTD-00774-G KTUS15/mITX Page 59 of 84
BIOS SETUP UTILITY
Advanced
IDE Configuration
Options
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
ATA/IDE Configuration
Disabled
Compatible
Disabled
Compatible
Feature
Options
Description
Hard Disk Write Protect
Disabled
Enabled
Disable/Enable device write protection. This will be
effective only if device is accessed through BIOS
IDE Detect Time Out (Sec)
0
35
Select the timeout value for detecting ATA/ATAPI
ATA(PI) 80Pin Cable
Host & Device
Device
Select the mechanism for detecting 80Pin ATA(PI)
JMicron SATA Controller
Disabled
AHCI Mode
Select ATA Controller Operation Mode
7.3.2 Advanced settings – IDE Configuration
ATA/IDE Configuration [Compatible]
► Primary IDE Master [Hard Disk]
► Primary IDE Slave [Not Detected]
► Third IDE Master [Not Detected]
► Third IDE Slave [Not Detected]
Hard Disk Write Protect [Disabled]
IDE Detect Time Out (Sec) [35]
ATA(PI) 80Pin Cable Detection [Device]
JMicron SATA Controller [IDE Mode]
Disabled
Compatible
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Detection
5
10
15
20
25
30
Host
IDE Mode
RAID Mode
device(s)
Cable
KTD-00774-G KTUS15/mITX Page 60 of 84
BIOS SETUP UTILITY
Advanced
Primary IDE Master
Select the type of
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Type
Not Installed
ARMD
Select the type of device connected.
LBA/Large Mode
Disabled
Auto: Enabling LBA mode if device supports LBA
Mode disabled
Block (Multi-Sector Transfer)
Disabled
Disabled: The Data transfer to and from device
multiple sectors at a time if supported by device.
PIO Mode
Auto
Selects PIO Mode
DMA Mode
Auto
UDMA6
Selects DMA mode:
S.M.A.R.T.
Auto
Enabled
Select if the Device should be monitoring itself (Self-
System)
32Bit Data Transfer
Disabled
Enabled
Select if the Device should be using 32Bit data
Transfer
devices connected to the
Device :Hard Disk
Vendor :ST340014A
Size :40.0GB
LBA Mode :Supported
Block Mode :16Sectors
PIO Mode :4
Async DMA :MultiWord DMA-2
Ultra DMA :Ultra DMA-5
S.M.A.R.T. :Supported
Type [Auto]
LBA/Large Mode [Auto]
Block (Multi-Sector Transfer) [Auto]
PIO Mode [Auto]
DMA Mode [Auto]
S.M.A.R.T. [Auto]
32Bit Data Transfer [Disabled]
system
<-> Select Screen
|| Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
Auto
CD/DVD
Auto
Auto
0, 1, 2, 3, 4
SWDMA0
SWDMA1
SWDMA2
MWDMA0
MWDMA1
MWDMA2
UDMA0
UDMA1
UDMA2
UDMA3
UDMA4
UDMA5
(Feature only present on Primary IDE)
and if the device is not already formatted with LBA
occurs one sector at a time.
Auto: The Data transfer to and from device occurs
Auto: Auto detection
SWDMAn: Single Word DMA n
MWDMAn: Multi Word DMA n
UDMAn: Ultra DMA n
Disabled
Monitoring, Analysis and Reporting Technology
KTD-00774-G KTUS15/mITX Page 61 of 84
BIOS SETUP UTILITY
Advanced
LAN Configuration
Control of Ethernet
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
ETH1 Configuration
Disabled
With RPL/PXE boot
Disable/enable LAN or enabled with RPL/PXE boot
7.3.3 Advanced settings – LAN Configuration
Devices and PXE boot
ETH1 Configuration [Enabled]
MAC Address & Link status : 00E0F41E24A4 1GB
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Note: The link status is “–“ if no LAN is connected otherwise it is 10MB, 100MB or 1GB depending on the
detected speed.
Enabled
KTD-00774-G KTUS15/mITX Page 62 of 84
BIOS SETUP UTILITY
Advanced
Configure Win627DHG Super IO Chipset
Allows BIOS to Enable
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Serial Port1 Address
Disabled
2E8/IRQ3
Select the BASE I/O address and IRQ.
Serial Port2 Address
Disabled
2E8/IRQ3
Select the BASE I/O address and IRQ.
Serial Port2 Mode
Normal
ASK IR
Select Mode for Serial Port2
Parallel Port Address
Disabled *
3BC
Select the I/O address for the Parallel Port.
Parallel Port Mode
Normal
ECP & EEP
Select the mode of operation for the Parallel Port
ECP Mode DMA Channel
DMA0
DMA3
Select a DMA channel in ECP mode of operation
EPP Version
1.9
1.7
Select version of EPP in the EPP mode of operation
Parallel Port IRQ
IRQ5
IRQ7
Select a IRQ for the Parallel Port
7.3.4 Advanced settings – Configure Win627DHG Super IO Chipset
or Disable Floppy
Serial Port1 Address [3F8/IRQ4]
Serial Port2 Address [2F8/IRQ3]
Serial Port2 Mode [Normal]
Parallel Port Address [378]
Parallel Port Mode [Normal]
Parallel Port IRQ [IRQ7]
Serial Port4 Address [3E8]
Serial Port3 IRQ [IRQ11]
Serial Port4 Address [2E8]
Serial Port4 IRQ [IRQ10]
Controller.
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
3F8/IRQ4
2F8/IRQ3
3E8/IRQ4
3F8/IRQ4
2F8/IRQ3
3E8/IRQ4
IRDA
378
278
Bi-Directional
ECP
EPP
(The available options depend on the setup for the
other Serial Ports).
(The available options depend on the setup for the
other Serial Ports).
DMA1
(Continues)
KTD-00774-G KTUS15/mITX Page 63 of 84
Feature
Options
Description
Serial Port3 Address
Disabled
2E8
Allows BIOS to select Serial Port3 Base Addresses
Serial Port3 IRQ
IRQ3
IRQ11
Allows BIOS to select Serial Port3 IRQ.
other Serial Ports).
Disabled
2E8
Allows BIOS to select Serial Port4 Base Addresses
other Serial Ports).
Serial Port4 IRQ
IRQ3
IRQ11
Allows BIOS to select Serial Port4 IRQ.
other Serial Ports).
Serial Port4 Address
3F8
2F8
3E8
IRQ4
IRQ10
3F8
2F8
3E8
IRQ4
IRQ10
(The available options depend on the setup for the
other Serial Ports).
(The available options depend on the setup for the
(The available options depend on the setup for the
(The available options depend on the setup for the
KTD-00774-G KTUS15/mITX Page 64 of 84
BIOS SETUP UTILITY
Advanced
Hardware Health Configuration
Disable = Full Speed
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Fan Cruise Control
Disabled
Select how the Fan shall operate.
speed set below.
Fan Settings
1406-5625 RPM
30°-60°C
The fan can operate in Thermal mode or in a fixed
fan speed mode
Fan Type
4 wire
Select the electrical interface for the fan:
4 Wire = 12VDC always PWM on control signal
Watchdog
Disabled
10 minutes
To be serviced via API.
7.3.5 Advanced settings – Hardware Health Configuration
System Temperature :48ºC/118ºF
CPU Temperature :56ºC/132ºF
VTIN Temperature :N/A
CPUFAN0 Speed :2537 RPM
Fan Cruise Control [Thermal]
Fan Setting [45°C/113°F]
Fan Type [4 Wire]
AUXFAN Speed :2164
Fan Cruise Control [Speed]
Fan Setting [2177 RPM]
Watchdog Function [Disabled]
Thermal: Does regulate
fan speed according to
specified temperature
Speed: Does regulate
according to specified
RPM
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Thermal
Speed
3 wire
15 seconds
30 seconds
1 minute
2 minutes
5 minutes
When set to Thermal, the Fan will start to run at the
CPU die temperature set below.
When set to Speed, the Fan will run at the fixed
(Only for CPUFAN)
3 Wire = PWM output to fan power line. RPM reading
and speed regulation at lower speed might be poor.
Note: The AUXFAN is available via Feature Connector.
KTD-00774-G KTUS15/mITX Page 65 of 84
BIOS SETUP UTILITY
Advanced
Voltage Monitor
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
7.3.6 Advanced settings – Voltage Monitor
Requested Core CPU :1.100 V
Vcore :1.096 V
AVCC :3.248 V
3VCC :3.248 V
+12V :12.029 V
+5V :5.016 V
Core 1.8 V :1.800 V
Vin board supply :4.824 V
VSB :3.264 V
VBAT :3.072 V
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
KTD-00774-G KTUS15/mITX Page 66 of 84
BIOS SETUP UTILITY
Advanced
ACPI Settings
General ACPI
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Suspend mode
S3 (STR)
Auto
Select the ACPI state used for System Suspend
Repost Video on S3 Resume
No
Yes
Determines whether to invoke VGA BIOS post on
S3/STR resume
Feature
Options
Description
ACPI Version Features
ACPI v1.0
ACPI v3.0
Enable RSDP pointers to 64-bit Fixed System
ACPI APIC support
Disabled
Enabled
Include ACPI APIC table pointer to RSDT pointer list.
AMI OEMB table
Disabled
Enabled
Include OEMB table pointer to R(X)SDT pointer lists
Headless mode
Disabled
Enabled
Headless operation mode through ACPI. See note
below.
Feature
Options
Description
PS/2 kbd/mouse S4/S5 Wake
Disabled
Enabled: The system can also be waked from S4 or
Disabled: The system can still be waked from S3.
Keyboard Wake Hotkey
Anykey
“Sleep button”
Select special key or all keys to wakeup the system
USB Device Wakeup From S3
Disabled *
Enabled
Enable/Disable USB Device wakeup from S3
7.3.7 Advanced settings – ACPI Settings
Configuration settings
► General ACPI Configuration
► Advanced ACPI Configuration
PS/2 Kbd/Mouse S4/S5 Wake [Disabled]
Keyboard Wake Hotkey [Any key]
USB Device Wakeup From S3 [Disabled]
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
General ACPI Configuration
Advanced ACPI Configuration
ACPI v2.0
Description Tables. Di ACPI version has some.
Enabled
“SPACE”
“ENTER”
Note: When Headless Mode is enabled, the BIOS will update the FACP (Fixed ACPI Description Table) to
indicate support for headless operation. Operating systems that support headless operation (operates
without a keyboard, monitor or mouse) can proceed to boot in headless mode. Some OS might require that
the BIOS setting “Boot Display Device” is different from Auto.
S5.
KTD-00774-G KTUS15/mITX Page 67 of 84
BIOS SETUP UTILITY
Advanced
PCI Express Configuration
Enable/Disable
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Active State Power-Management
Enabled
Disabled
Enable/Disable
PCI Express L0s and L1 link power States.
Smbios Configuration Screen
Advanced
Smbios Configuration
SMBIOS SMI Wrapper
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Smbios Smi Support
Enabled
Disabled
SMBIOS SMI Wrapper support for PnP Func.
50h-54h
7.3.8 Advanced settings – PCI Express Configuration
PCI Express L0s and L1
Active State Power-Management [Enabled]
link power States.
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
7.3.9 Advanced settings – Smbios Configuration
Smbios Smi Support [Enabled]
support for PnP Func.
50h-54h
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
KTD-00774-G KTUS15/mITX Page 68 of 84
BIOS SETUP UTILITY
Advanced
Configure Remote Access type and parameters
Select Remote Access
v02.67+ (C)Copyright 1985-2009, American Megatrends, Inc.
Feature
Options
Description
Remote Access
Disabled
When Enabled then a remote PC can via one of the
program the Windows Hyperterminal can be used.
Serial port number
COM1
COM2
Setup which comport that should be used for
communication
Serial Port Mode
115200 8 n 1
9600 8 n 1
Select the serial port speed
Flow Control
None
Software
Select Flow Control for serial port
Redirection After BIOS POST
Disabled
Always
How long shall the BIOS send the picture over the
Terminal Type
ANSI
VT-UTF8
Select the target terminal type
VT.UTF8 Combo Key Support
Enabled
Disabled
Enable VT-UTF8 Combination Key Support for
ANSI/VT100 terminals
Sredir Memory Display Delay
No Delay
Delay 4 Sec
Gives the delay in seconds to display memory
BIOS setup
7.3.10 Advanced settings – Remote Access Configuration
type.
Remote Access [Enabled]
Serial port number [COM1]
Base Address, IRQ [2F8h, 3]
Serial Port Mode [115200 8,n,1]
Flow Control [None]
Redirection After BIOS POST [Always]
Terminal Type [ANSI]
VT-UTF8 Combo Key Support [Enabled]
Sredir Memory Display Delay [No Delay]
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Enabled
57600 8 n 1
38400 8 n 1
19200 8 n 1
Hardware
Boot Loader
VT100
serial ports behave like a TTY terminal, so that
keyboard and monitor (in a terminal window) is
emulated by the remote PC. As remote PC terminal
serial port
Delay 1 Sec
Delay 2 Sec
information
KTD-00774-G KTUS15/mITX Page 69 of 84
BIOS SETUP UTILITY
Advanced
Trusted Computing
Enables/Disable TPM TCG
TCG/TPM Support [No]
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
TCG/TPM Support
No
Yes
Enables/Disable TPM TCG (TPM 1.1/1.2) Support.
See note below.
7.3.11 Advanced settings – Trusted Support
(Tpm 1.1/1.2) Support in
Bios
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Note: It is only possible to change this setting right after a complete power interruption. When the BIOS has
passed the first time after a complete power interruption the TCG/TPM setting will be locked and software
reset will not open up the option.
KTD-00774-G KTUS15/mITX Page 70 of 84
BIOS SETUP UTILITY
Advanced
USB Configuration
Enables support for
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Legacy USB Support
Disabled
Auto
Support for legacy USB Keyboard
USB 2.0 Controller Mode
FullSpeed
Configure the USB 2.0 controller in HiSpeed
disabled as default.
BIOS EHCI Hand-Off
Enabled
This is a workaround for OSes without EHCI hand-off
by EHCI driver.
7.3.12 Advanced settings – USB Configuration
legacy USB. AUTO option
Module Version – 2.24.2-13.4
USB Devices Enabled :
1 Drive
Legacy USB Support [Enabled]
USB 2.0 Controller Mode [HiSpeed]
BIOS EHCI Hand-Off [Enabled]
USB Mass Storage Device Configuration
disables legacy support
if no USB Devices are
connected.
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Enabled
HiSpeed
Disabled
(480Mbps) or FullSpeed (12Mbps).
Note: This feature is not available when Failsafe
Defaults are loaded, because USB2.0 controller is
support. The EHCI Ownership change should claim
KTD-00774-G KTUS15/mITX Page 71 of 84
BIOS SETUP UTILITY
Advanced
USB Mass Storage Device Configuration
Number of seconds POST
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
USB Mass Storage Reset
10 Sec
40 Sec
Number of seconds POST waits for the USB mass
Emulation Type
Auto
CDROM
If Auto, USB devices less than 530MB will be
Feature
Options
Description
Spread Spectrum
Disabled
Enabled
7.3.13 Advanced settings – USB Mass Storage Device Configuration
waits for the USB mass
USB Mass Storage Reset Delay [20 Sec]
Device #1 JetFlash TS256MJF2L
Emulation Type [Auto]
storage device after
start unit command.
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Delay
20 Sec
30 Sec
Floppy
Forced FDD
Hard Disk
storage device after start unit command.
emulated as Floppy otherwise as hard drive. Forced
FDD option can be used to force a HDD formatted
drive to boot as FDD (Ex. ZIP drive).
7.3.14 Advanced settings – Spread Spectrum Clock
KTD-00774-G KTUS15/mITX Page 72 of 84
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Security
Chipset
Exit
Advanced PCI/PnP Settings
Clear NVRAM during
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Clear NVRAM
No
Yes
Clear NVRAM during System Boot.
Plug & Play O/S
No
No: lets the BIOS configure all the devices in the
system has a Plug and Play operating system.
PCI Latency Timer
32, 64, 96, 128,
160, 192, 224, 248
Value in units of PCI clocks for PCI device latency
timer register.
Allocate IRQ to PCI VGA
Yes
Yes: Assigns IRQ to PCI VGA card if card requests
card requests an IRQ
Palette Snooping
Disabled
Enabled: informs the PCI devices that an ISA
will function correctly.
PCI IDE BusMaster
Disabled *
Enabled
Enabled: Bios uses PCI busmastering for reading /
writing to IDE drivers.
OffBoard PCI/ISA IDE Card
Auto
PCI Slot6
Some PCI IDE cards may require this to be set to the
Reserved Memory Size
Disabled
64K
Size of memory block to reserve for legacy ISA
7.4 PCIPnP Menu
System Boot.
Warning: Setting wrong values in below sections
May cause system to malfunction.
Clear NVRAM [No]
Plug & Play O/S [No]
PCI Latency Timer [64]
Allocate IRQ to PCI VGA [Yes]
Palette Snooping [Disabled]
PCI IDE BusMaster [Disabled]
OffBoard PCI/ISA IDE Card [Auto]
Reserved Memory Size [Disabled]
<-> Select Screen
|| Select Item
+- change option
F1 General Help
F10 Save and Exit
ESC Exit
Yes
No
Enabled
PCI Slot1
PCI Slot2
PCI Slot3
PCI Slot4
PCI Slot5
system.
Yes: lets the operating system configure Plug and
Play (PnP) devices not required for boot if your
IRQ.
No: Does not assign IRQ to PCI VGA card even if
graphics device is installed in the system so the card
PCI slot number that is holding the card.
Auto: Works for most PCI IDE cards.
16K
32K
devices.
KTD-00774-G KTUS15/mITX Page 73 of 84
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Security
Chipset
Exit
Boot Settings
Configure Settings
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
7.5 Boot Menu
during System Boot.
► Boot Settings Configuration
► Boot Device Priority
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
KTD-00774-G KTUS15/mITX Page 74 of 84
BIOS SETUP UTILITY
Boot
Boot Settings Configuration
Allows BIOS to skip
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Quick Boot
Enabled
Disabled
Allows BIOS to skip certain tests while booting in
order to decrease boot time.
Quiet Boot
Disabled
White Screen
Disabled: Displays normal POST messages.
White Screen: White picture.
AddOn ROM Display Mode
Force BIOS
Keep current
Set display mode for Option ROM.
Bootup Num-Lock
Off
On
Select Power-on state for numlock
PS/2 Mouse Support
Disabled
Auto
Select support for PS/2 Mouse.
Wait for ‘F1’ If Error
(see note)
Disabled
Enabled
Wait for F1 key to be pressed if error occurs.
Hit ‘DEL’ Message Display
Disabled
Enabled
Displays “Press DEL to run Setup” in POST.
Interrupt 19 Capture
Disabled
Enabled
Enabled: Allows option ROMs to trap interrupt 19
PC Speaker/Beep
Disabled
Control the default beeps during boot of the system.
enumeration and (un)plug of USB.
Default init boot Order
0->4->3->5->2->1
Control how devices will be placed in the Boot
5 = “External LAN”
Force boot Device
Disabled
Network
Overrides current boot setting. Device must be in the
7.5.1 Boot – Boot Settings Configuration
certain tests while
Quick Boot [Enabled]
Quiet Boot [Disabled]
AddOn ROM Display Mode [Force BIOS]
Bootup Num-Lock [On]
PS/2 Mouse Support [Auto]
Wait for ‘F1’ If Error [Enabled]
Hit ‘DEL’ Message Display [Enabled]
Interrupt 19 Capture [Disabled]
PC Speaker/Beep [Enabled]
Force boot Device [Disabled]
booting. This will
decrease the time needed
to boot the system.
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Enabled
Black Screen
Enabled
Enabled
Enabled: Displays OEM Logo (no POST messages).
Black Screen: No picture.
This setting will also control the beep during
0->4->3->5->1->2
1->2->3->5->0->4
3->5->1->2->0->4
3->0->4->1->2->5
2->1->0->4->3->5
2->0->4->3->1->5
3->1->0->4->2->5
Primary IDE Master
Primary IDE Slave
Third IDE Master
Third IDE Slave
Device Priority Menu:
0 = “Removables”
1 = “Hard disk”
2 = “Atapi cdrom”
3 = “BEV/onboard LAN” (see note)
4 = “USB”
boot priority menu, though. If the device fails to boot,
the system will NOT try other devices.
KTD-00774-G KTUS15/mITX Page 75 of 84
<INS> Pressed
Primary Master Hard Disk Error
PCI I/O conflict
Timer Error
S.M.A.R.T HDD Error
PCI ROM conflict
Interrupt Controller-1 error
Cache Memory Error
PCI IRQ conflict
Keyboard/Interface Error
DMA Controller Error
PCI IRQ routing table error
Halt on Invalid Time/Date
Resource Conflict
NVRAM Bad
Static Resource Conflict
Notes:
List of errors:
BEV (Bootstrap Entry Vector) list of devices (except External LAN) with bootable ROM. Included is onboard
LAN.
KTD-00774-G KTUS15/mITX Page 76 of 84
BIOS SETUP UTILITY
Boot
Boot Device Priority
Specifies the boot
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
7.5.2 Boot – Boot Device Priority
sequence from the
1st Boot Device [ESS-ST380811AS]
available devices.
A device enclosed in
parenthesis has been
disabled in the
corresponding type menu.
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Note: When pressing <F11> while booting it is possible manually to select boot device.
KTD-00774-G KTUS15/mITX Page 77 of 84
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Security
Chipset
Exit
Security Settings
Install or Change the
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Change Supervisor Password
Password
When not cleared the advanced Supervisor
when entering BIOS as Supervisor.
User Access Level
Full Access
Only visible if Supervisor Password is installed.
allow boot.
Change User Password
Password
Change the User Password
Password Check
Setup
Only visible if Password is installed.
Always: Protects both BIOS settings and Boot.
Boot Sector Virus Protection
Enabled
Disabled
Will write protect the MBR when the BIOS is used to
access the harddrive
7.6 Security Menu
password.
Supervisor Password :Not Installed
User Password :Not Installed
Change Supervisor Password
Change User Password
Boot Sector Virus Protection [Disabled]
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
View Only
Limited
No Access
Always
Password protection system is enabled (see below
diagram). Hereafter setting can only be accessed
Full Access: User can change all BIOS settings.
View Only: User can only read BIOS settings.
Limited: User can only read settings except: Date &
Time, Quick Boot, Quiet Boot, Repost Video on S3
Resume, Active State Power-Management and
Remote Access.
No Access: User can not enter BIOS, but if
Password Check = Always then User password will
Setup: Protects only BIOS settings.
KTD-00774-G KTUS15/mITX Page 78 of 84
CMOS (most)
BIOS User
None
Date&Time *
Supervisor PSW
PSW
User
PSW
Super-
Supervisor Password protection (setup Supervisor before User)
PSW
User
User Password protection only (no Supervisor Password used)
CMOS
* = also:
Quick Boot
visor
Access control
Full
View
Limit
Quiet Boot
Repost Video on S3 Resume
Active State Power-Management
KTD-00774-G KTUS15/mITX Page 79 of 84
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Security
Chipset
Exit
Advanced Chipset Settings
Configures North Bridge
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
BIOS SETUP UTILITY
Chipset
North Bridge Adapter Priority Configuration
Select which graphics
Primary Graphics Adaptor [PCIe/IGD]
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Primary Graphics Adaptor
IGD
Select which graphics controller to use as the
card in combination with onboard graphics.
Integrated Graphics Mode
Disabled
Enabled, 8MB
Select the amount of system memory used by the
video.
7.7 Chipset Menu
features.
Warning: Setting wrong values in below sections
may cause system to malfunction.
► North Bridge Configuration
► South Bridge Configuration
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
7.7.1 Advanced Chipset Settings – North Bridge Chipset Configuration
controller to use as the
Integrated Graphics Mode Select [Enabled,8MB]
► Boot Display Configuration
primary boot device.
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Select
PCIe/IGD
Enabled, 1MB
Enabled, 4MB
primary boot device. Select IGD if using PCI Graphic
Integrated Graphic Device. (For DOS etc.)
Note: OS driver can dynamically use up to 256MB for
KTD-00774-G KTUS15/mITX Page 80 of 84
BIOS SETUP UTILITY
Chipset
Boot Display Configuration
Options
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Boot Display Device
Auto
External LVDS
Auto
External LVDS
Local Flat Panel Scaling
Auto
Disabled
Auto
Disabled
DPST Control
VBIOS-Default
DPST Enabled at Level 5
VBIOS-Default
DPST Enabled at Level 5
TV Standard
VBIOS-Default
CEA 7703
VBIOS-Default
CEA 7703
Backlight Signal Inversion
Disabled
Enabled
Disabled
Enabled
LCDVCC Voltage
3.3V
5V
3.3V
5V
LVDS
(see description ->)
Select Resolution, Manufacturer and Type no.
for the actual LVDS display.
7.7.2 Advanced Chipset … – North Bridge … – Boot Display Configuration
Boot Display Device [Auto]
Local Flat Panel Scaling [Auto]
DPST Control [VBIOS-Default]
TV Standard [VBIOS-Default]
Backlight Signal Inversion [Disabled]
LCDVCC Voltage [3.3V]
LVDS [640x480]
Auto
Integrated LVDS
External DVI/HDMI
External TV
External CRT
External LVDS
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Integrated LVDS
External DVI/HDMI
External TV
External CRT
Forced Scaling
DPST Disabled
DPST Enabled at Level 1
DPST Enabled at Level 2
DPST Enabled at Level 3
DPST Enabled at Level 4
NTSC
PAL
SECAM
SMPTE240M
ITU-R television
SMPTE295M
SMPTE296M
CEA 7702
Integrated LVDS
External DVI/HDMI
External TV
External CRT
Forced Scaling
DPST Disabled
DPST Enabled at Level 1
DPST Enabled at Level 2
DPST Enabled at Level 3
DPST Enabled at Level 4
NTSC
PAL
SECAM
SMPTE240M
ITU-R television
SMPTE295M
SMPTE296M
CEA 7702
KTD-00774-G KTUS15/mITX Page 81 of 84
BIOS SETUP UTILITY
Chipset
South Bridge Chipset Configuration
Number of UCHI
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
USB Functions
Disabled
6 USB Ports
Disabled: covers all USB ports inclusive USB6/7
6 USB Ports: (USB0/1/2/3/4/5)
USB 2.0 Controller
Disabled
(This setting only available if USB Function is not
(480Mbps)
USB Client Controller
Disabled
Enabled
Disabled
Enabled
SDIO Controller
Disabled
Enabled
Disabled
Enabled
Audio Controller Codec
Auto
Disabled
Auto
Disabled
Audio Jack Sensing
Auto
Auto: The insertion of audiojacks are auto
(useful when using the Audio pinrow)
Restore on AC Power Loss
Power Off
Last State
Power Off
Last State
7.7.3 Advanced Chipset Settings – South Bridge Chipset Configuration
Ports in system ECHI
USB Functions [6 USB Ports]
USB 2.0 Controller [Enabled]
USB Client Controller [Disabled]
SDIO Controller [Enabled]
Audio Controller Codec [Auto]
Audio Jack Sensing [Auto]
Restore on AC Power Loss [Power on]
ONLY is automatically
Added.
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
2 USB Ports
4 USB Ports
Enabled
Azalia
Disabled
Power On
2 USB Ports: (USB0/1)
4 USB Ports: (USB0/1/2/3)
disabled)
Disabled: Disable USB6/7
Enabled: Enable USB6/7
Note: USB6/7 supports only USB2.0 HiSpeed
Azalia
determined.
Disabled: Driver Assumes that all jacks are inserted
Power On
KTD-00774-G KTUS15/mITX Page 82 of 84
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Security
Chipset
Exit
Exit Options
Exit system setup after
V02.63+ (C)Copyright 1985-2008, American Megatrends, Inc.
Feature
Options
Description
Save Changes and Exit
Ok
Cancel
Exit system setup after saving the changes
Discard Changes and Exit
Ok
Cancel
Exit system setup without saving any changes
Discard Changes
Ok
Cancel
Discards changes done so far to any of the setup
questions
Load Optimal Defaults
Ok
Cancel
Load Optimal Default values for all the setup
questions
Load Failsafe Defaults
Ok
Cancel
Load Failsafe Default values for all the setup
questions
Halt on invalid Time/Date
Enabled
Disabled
Enabled: System halt if incorrect Date & Time.
Secure CMOS
Enabled
Enable will store current CMOS in non volatile ram.
failure etc.)
7.8 Exit Menu
saving the changes.
Save Changes and Exit
Discard Changes and Exit
Discard Changes
Load Optimal Defaults
Load Failsafe Defaults
Halt on invalid Time/Date [Enabled]
Secure CMOS [Disabled]
F10 Key can be used for
this operation.
<-> Select Screen
|| Select Item
Enter Go to Sub Screen
F1 General Help
F10 Save and Exit
ESC Exit
Disabled
(For protection of CMOS data in case of battery
KTD-00774-G KTUS15/mITX Page 83 of 84
Number of
Beeps
1
Insert diskette in floppy drive A:
2
‘AMIBOOT.ROM’ file not found in root directory of diskette in A:
3
Base Memory error
4
Flash Programming successful
5
Floppy read error
6
Keyboard controller BAT command failed
7
No Flash EPROM detected
8
Floppy controller failure
9
Boot Block BIOS checksum error
10
Flash Erase error
11
Flash Program error
12
‘AMIBOOT.ROM’ file size error
13
BIOS ROM image mismatch (file layout does not match image present in flash device)
Number of
Beeps
1
Memory refresh timer error.
2
Parity error in base memory (first 64KB block)
3
Base memory read/write test error
4
Motherboard timer not operational
5
Processor error
6
8042 Gate A20 test error (cannot switch to protected mode)
7
General exception error (processor exception interrupt error)
8
Display memory error (system video adapter)
9
AMIBIOS ROM checksum error
10
CMOS shutdown register read/write error
11
Cache memory test failed
Number of
Beeps
1, 2 or 3
Reset the memory, or replace with known good modules.
4-7, 9-11
Fatal error indicating a serious problem with the system. Consult your system manufacturer.
the problem happens again. This will reveal the malfunctioning card.
8
If the system video adapter is an add-in card, replace or reset the video adapter. If the video
adapter is an integrated part of the system board, the board may be faulty.
8 AMI BIOS Beep Codes
Boot Block Beep Codes:
Description
POST BIOS Beep Codes:
Description
Troubleshooting POST BIOS Beep Codes:
Troubleshooting Action
Before declaring the motherboard beyond “all hope”, eliminate the possibility of interference
due to a malfunctioning add-in card. Remove all expansion cards, except the video adapter.
• If beep codes are generated when all other expansion cards are absent, consult your
system manufacturer’s technical support.
• If beep codes are not generated when all other expansion cards are absent, one of the addin cards is causing the malfunction. Insert the cards back into the system one at a time until
KTD-00774-G KTUS15/mITX Page 84 of 84
9 OS Setup
Use the Setup.exe files for all relevant drivers. The drivers can be found on KTUS15 Driver CD or they can
be downloaded from the homepage http://www.kontron.com/
Note: When installing Intel ® Graphics drivers it is possible for the OS to start up without any connected
display(s) active. If you are able to pass on possible "Log On” etc. by entering User and Password etc.
without actually seeing the picture on the display and if the Hot Keys have not been disabled in the Intel
Graphic driver, then the following key combinations you can select a connected display:
<Ctrl><Alt><F1> enables the sDVO channel which controls the DVI-D or DVI-A display output depending on
board configuration. Refer to configuration overview: KTUS15/mITX Board configurations for details.
10 Warranty
KONTRON Technology warrants its products to be free from defects in material and workmanship during the
warranty period. If a product proves to be defective in material or workmanship during the warranty period,
KONTRON Technology will, at its sole option, repair or replace the product with a similar product.
Replacement Product or parts may include remanufactured or refurbished parts or components.
The warranty does not cover:
1. Damage, deterioration or malfunction resulting from:
A. Accident, misuse, neglect, fire, water, lightning, or other acts of nature, unauthorized product
modification, or failure to follow instructions supplied with the product.
B. Repair or attempted repair by anyone not authorized by KONTRON Technology.
C. Causes external to the product, such as electric power fluctuations or failure.
D. Normal wear and tear.
E. Any other causes which does not relate to a product defect.
2. Removal, installation, and set-up service charges.
Exclusion of damages:
KONTRON TECHNOLOGY LIABILITY IS LIMITED TO THE COST OF REPAIR OR REPLACEMENT OF
THE PRODUCT. KONTRON TECHNOLOGY SHALL NOT BE LIABLE FOR:
1. DAMAGE TO OTHER PROPERTY CAUSED BY ANY DEFECTS IN THE PRODUCT, DAMAGES
BASED UPON INCONVENIENCE, LOSS OF USE OF THE PRODUCT, LOSS OF TIME, LOSS OF
PROFITS, LOSS OF BUSINESS OPPORTUNITY, LOSS OF GOODWILL, INTERFERENCE WITH
BUSINESS RELATIONSHIPS, OR OTHER COMMERCIAL LOSS, EVEN IF ADVISED OF THEIR
POSSIBILITY OF SUCH DAMAGES.
2. ANY OTHER DAMAGES, WHETHER INCIDENTAL, CONSEQUENTIAL OR OTHERWISE.
3. ANY CLAIM AGAINST THE CUSTOMER BY ANY OTHER PARTY.
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