Kontron cPCI-MXS64GX Technical Reference Manual

www.kontron.com

Note: The latest releases of the Technical Reference Manuals are available at:

cPCI-MXS64GX

6U CompactPCI 64-BIT System Processor

Technical Reference Manual

Version 1.4, May 2002

ftp://ftp.kontron.ca/Support/Product_Manuals/

Ref. : M6004_TECH

Historical

Rel. Date Comments

1.0 Jul-2001 Initial document release.

1.1 Aug-2001 N.A.

1.2 Dec-2001

Cover page Version 1.2 , December 2001-12-18
Page 1.2, 3.9 and 3.15 Added 700MHz processor speed

Page 1.2 32-bit AGP SVGA CRT controlle r

Replaced with :

64-bit AGP SV GA CRT controller
16-bit Ultra Wide up to 40Mbps, 8-bit Fa s t SC SI-2 up

to 10Mbps, 8-bit Ultra SCSI up to 20M bps (Adaptec
AIC7880).

Replaced with :

16-bit Ultra Wide LVD SCSI up to 80M bps (Sy mbios
SYM53C895)

Page 2.8 Section 2.9 – In table, line 2:

Serial port 2 - changed J3 for J5
Serial port 3 - changed J5 for J3
In table, signal path description
Changed J3 for J5.

Added line :
The infrared COM2 signals (COM2_ I RRX and
COM2_IRTX) are available at J3 connector.

Page 2.11 In table, signal path description

Removed the line :
In Infrared mode, signals are availabl e through the J3
CPCI I/O connector.

J3 Connector description :
Page 3.11 Changed “2/3/4” for “3 and 4”
Page 3.14 Removed “2” from J3 connector description
Page 3.32 In section 3.5.2.2 0- SCSI Int erface table:

Row 1 : Changed SCD for SD
Page 3.34 In section 3.5.2.6 – IDE 1 Interface

Row 2 : Changed “SDD 0-15” for IDE1_0-15
PART 4 title Section 2 : Removed UPDATING OR RESTORING

Added the note : UPDATING OR RESTORING THE

Page E.5 J4 Row A, pin 5 - DS4- changed for SD4-

J4 Row A, pin 10 - R_SYNC changed for R_HSYNC

THE BIOS IN FLASH

Replaced by : VT100 MODE

BIOS IN FLASH (see the Kontron
WEB site and select the “support”
section)

Historical (continued)

1.3 May 13, 2002 - Replace all occurrences of Teknor Applicom Inc or Teknor by

Kontron, Inc.

- Replace all occurrences of Adaptec and Symbios with LSI.

- Replace in section 3.3.3.1 "...from "8MB to 1.5GB of..." by
"... from 32MB to 1.5GB of...

- Correct COM port assignation & locat i on:
J5= COM1 & 2, J3= COM 3 & 4 + Infrared.

- Replace in section E.4 connector J3 RowD Pin14 " SD8" by "
SD8+".

- Remove BMC/IPMI support and references:

Replace in section E.2 / J1 : (BMC+Xlinx)

C17: “IPMB0_SDA” by “I2C_SDA” (From Xlinx)
B17: “IPMB0_SCL” by “I2C_SCL” (From Xlinx)
C17: “IPMB0_PWR” by “Reseved”

Replace in section E.3 / J2 : (BMC)

D19: “IPMB1_SDA” by “Reseved”
C19: “IPMB1_SCL” by “Reseved”
E19: “IPMB1_ALERT” by “Reseved”

Note: Only I2C support is still available instead of IPMI.

Updated Copywright to 2002

FCC COMPLIANCE STATEMENT

Warning

Changes or modifications to this unit not expressly approved by the party responsible for
the compliance could void the user’s authority to operate this equipment.

This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to Part 15 of the FCC rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a
commercial environment. This equipment generates, uses and can radiate radio frequency
energy and, if not installed and used in accordance with the instruction manual, may cause
harmful interference to radio communications. Operation of this equipment in a residential
area is likely to cause harmful interference, in which case the user will be required to
correct the interference at his or her own expense.

European Statement

Warning

This is a class A product. In a domestic environment this product may cause radio
interference in which case the user may be required to take adequate measures.

Safety Standard

UL Recognized Component, File # E186339 vol. 1 section 2

Care and handling precautions for Lithium batteries

• Do not short circuit

• Do not heat or incinerate

• Do not charge

• Do not deform or disassemble

• Do not apply solder directly

• Do not mix different types or partially used batteries together

• Always observe proper polarities

FOREWORD

The information in this document is provided for reference purposes only. Kontron does
not assume any liability for the application of information or the use of pro ducts described
herein.

This document may contain information or refer to products protected by the copyrights or
patents of others and does not convey any license under the patent rights of Kontron, nor
the rights of others.

Printed in Canada.
Copyright 2002 by Kontron Communications, Inc., Boisbriand, Qc J7G 2A7.

READ ME FIRST

Your computer board has a standard non-rechargeable lithium battery. To preserve the
battery lifetime, the battery enable jumper is removed when you receive the board. If
you do not have any jumper cap, we suggest you to use t he Watchdog Timer jumper cap.

EXERCISE CAUTION WHILE REPLACING LITHIUM BATTERY

! WARNING

Danger of explosion if battery is incorrectly replaced. Replace only with the
same or equivalent type recommended by the manufacturer. Dispose of
used batteries according to the manufacturer's instructions.

! ATTENTION

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.
Remplacer uniquement avec une batterie du même type ou d’un type

équivalent recommandé par le constructeur. Mettre au rebut les batteries
usagées conformément aux instructions du fabriquant.

! ACHTUNG

Explosionsgefahr bei falschem Batteriewechsel.
Verwenden Sie nur die empfohlenen Batterietypen des Herstellers.

Entsorgen Sie die verbrauchten Batterien laut Gebr auchsanweisung des
Herstellers.

! ATENCION

Puede explotar si la pila no este bien reemplazada.
Solo reemplazca la pila con tipas equivalentes segun las instrucciones del

manifacturo. Vote las pilas usadas segun las instrucciones del manifacturo.

! IMPORTANT

J1 and J2 are de-facto industry standard as defined by PICMG

J3, J4 and J5 are user-defined connectors and will vary from various
manufacturers. Contact our Technical Support to verify pinout

compatibility with other chassis backplane vendors.

! POWERING-UP THE SYSTEM

If you should encounter a problem, verify the following items:

Make sure that all connectors are properly connected.
Verify your boot diskette.
If the system still does not start up properly, you should try booting your

system with only the power cord and video monitor connected to the board
this is the minimum required to see if the board is working).

If you still are not able to start up your system, please refer to the
emergency Procedure in the Appendix Section.

If you still are not able to get your board up and running, contact our
technical Support department for assistance.

! PREVENTING VIRUSES

Kontron Communications, Inc takes every precaution against computer
viruses.

To safeguard against co mputer viruses in general, d o not freely lend your
diskettes and regularly perform virus scans on all your computer
systems.

! ADAPTER CABLES

While adapter cables are provided from various sources, the pinout is often
different. The direct crimp design offered by Kontron allows the simplest
cable assembly. All cables are available from Kontron Sales Department.

UNPACKING AND SAFETY PRECAUTIONS

Static Electricity

Since static electricity can damage the board, the following precautions should be taken:

1. Keep the board in its antistatic package, until you are ready to install it.

2. Touch a grounded surface or wear a grounding wrist strap before removing the board

from its package; this will discharge any static electricity that may have built up in
your body.

3. Handle the board by the edges.

Storage Environment

Electronic boards are sensitive devices. Do not handle or store devices near strong
electrostatic, electromagnetic, magnetic or radioactive fields.

Power Supply

Before any installation or setup, ensure that the board is unplugged from power sources or
subsystems.

Unpacking

Follow these recommendations while unpacking:

1. After opening the box, save it and the packing material for possible future shipment.

2. Remove the board from its antistatic wrapping and place it on a grounded surface.

3. Inspect the board for damage. If there is any damage, or items are missing, notify

Kontron immediatel y.

When unpacking you will find:

®

1. 6U CompactPCI

2. One Quick Reference sheet

3. One CDROM containing drivers.

64-bit System Processor board

TABLE OF CONTENTS

1. PRODUCT DESCRIPTION

1.1. Product OVERVIEW........................................................................................................1.1

1.2. Product Specifications......................................................................................................1.2

1.3. Hot Swap capability.........................................................................................................1.4

1.4. Interfacing with the Environment......................................................................................1.6

1.4.1. CPCI...................................................................................................................1.6

1.4.2. Mezzanine ...........................................................................................................1.6

1.5. Compatibility with other KONTRON Products...................................................................1.7

1.6. Mezzanine Card Concept.................................................................................................1.8

1.6.1. Kontron’s Mezzanine Concept.............................................................................1.9

1.6.2. PMC Concept......................................................................................................1.9

1.6.3. CompactFlash Feature........................................................................................1.9

2. ONBOARD FEATURES

2.1. CompactFlash Interface...................................................................................................2.1

2.1.1. Setups.................................................................................................................2.1

2.2. Enhanced IDE Interfaces.................................................................................................2.2

2.3. Etherne t In te rfaces...........................................................................................................2.3

2.3.1. Front Plate Configuration.....................................................................................2.3

2.3.2. CPCI I/O Configur a tio n........................................................................................2.4

i

2.4. Floppy Disk Interface.......................................................................................................2.4

2.5. PS/2 Keyboard / PS/2 Mouse Interface............................................................................2.5

2.6. Parallel Po r t.....................................................................................................................2.5

2.6.1. Standard Mode....................................................................................................2.6

2.6.2. EPP Mode...........................................................................................................2.6

2.6.3. ECP Mode...........................................................................................................2.7

2.7. Power Management.........................................................................................................2.7

2.8. SCSI Interface.................................................................................................................2.7

2.9. Serial Po r ts......................................................................................................................2.8

2.9.1. SERIAL PORT 1..................................................................................................2.9

2.9.1.1. Remote Reset .......................................................................................2.9

2.9.1.2. Front Plate Configuration.....................................................................2.10

2.9.2. Serial Port 2......................................................................................................2.10

2.9.3. Serial Port 3......................................................................................................2.10

2.9.3.1. Infrared Mode:.....................................................................................2.11

2.9.3.2. RS-232 Protocol:.................................................................................2.12

2.9.3.3. RS-422 Protocol:.................................................................................2.12

2.9.3.4. RS-485 Protocol:.................................................................................2.12

2.9.4. Serial Port 4......................................................................................................2.13

2.10. Thermal Management....................................................................................................2.13

2.11. USB Interfaces...............................................................................................................2.14

2.12. Video Interface...............................................................................................................2.15

2.12.1. Supported Resolutions......................................................................................2.16

2.12.2. Major Features Description................................................................................2.16

ii

3. INSTALLING THE BOARD

3.1. Setting Jumpers...............................................................................................................3.1

3.1.1. Jumper Description for the CPCI-MXS64GX.......................................................3.1

3.1.2. CPCI-MXS64GX – Jumper Settings....................................................................3.2

3.1.3. Register’s description RS232/RS485...................................................................3.3

3.1.4. History and monitor status...................................................................................3.3

3.1.5. Multimedia, History status ...................................................................................3.4

3.1.6. Monitoring status and I/O access.........................................................................3.4

3.1.7. Uart 3 PnP configuration.....................................................................................3.4

3.1.8. Uart 4 PnP configuration.....................................................................................3.5

3.1.9. Digital watchdog..................................................................................................3.5

3.1.10. NMI control..........................................................................................................3.6

3.1.11. 0Register BITs description (summary).................................................................3.7

3.2. Onboard Interconnectivity................................................................................................3.8

3.2.1. cPCI-MXS64GX Block Diagram ..........................................................................3.8

3.2.2. Mobile Penti um

®

II / III processor.........................................................................3.9

3.2.3. North Bridge Chipset...........................................................................................3.9

3.2.4. 21154 PCI-to-PCI Bridge.....................................................................................3.9

3.2.5. 82371AB PCI-to-ISA Bridge / IDE Xcelerator (PIIX4).........................................3.10

3.2.6. Onboard Connectors and Headers....................................................................3.11

3.2.7. Front Plate Connectors and Indicators...............................................................3.12

3.2.8. FACEPLATE OPTIO N S....................................................................................3.13

3.2.9. CompactPCI Connectors...................................................................................3.14

iii

3.3. Customizing the Board...................................................................................................3.15

3.3.1. Processor and Fan............................................................................................3.15

3.3.2. Backup Battery..................................................................................................3.16

3.3.3. Memory .............................................................................................................3.17

3.3.3.1. SDRAM System Memory.....................................................................3.17

3.3.3.2. DIMM Installation.................................................................................3.18

3.3.4. Supervision Features ........................................................................................3.19

3.3.4.1. Power Fail Monitoring..........................................................................3.19

3.3.4.2. Watchdog............................................................................................3.20

3.3.4.3. Thermal Management .........................................................................3.22

3.4. Building a CPCI System.................................................................................................3.23

3.4.1. Backplane.........................................................................................................3.24

3.4.2. Rear-Panel I/O..................................................................................................3.25

3.4.3. Storage Devices................................................................................................3.27

3.4.4. Power Supply....................................................................................................3.27

3.4.5. Fan Tray............................................................................................................3.27

3.4.6. Installing the Boa r d into a Bay...........................................................................3.27

3.4.7. Connector Keying..............................................................................................3.28

3.4.8. Bus Mastering................................................................................................... 3.29

3.4.9. Connection........................................................................................................3.29

iv

3.5. CPCI I/O Signals............................................................................................................3.30

3.5.1. J3 Signal Specification ......................................................................................3.30

3.5.1.1. Ethernet LEDS ....................................................................................3.30

3.5.1.2. Ethernet 1............................................................................................3.30

3.5.1.3. Serial Port 3........................................................................................3.30

3.5.1.4. Serial Port 4........................................................................................3.31

3.5.1.5. IDE LED Signals..................................................................................3.31

3.5.1.6. IR Serial Port 2....................................................................................3.31

3.5.1.7. Hot Swap HA (High Availability) signals...............................................3.31

3.5.1.8. Miscellaneous Signals.........................................................................3.31

3.5.2. J4 Signal Specification ......................................................................................3.32

3.5.2.1. Power Management ............................................................................3.32

3.5.2.2. SCSI Interface.....................................................................................3.32

3.5.2.3. Video Interface....................................................................................3.33

3.5.2.4. Ethernet 1 Interface.............................................................................3.33

3.5.2.5. Hot Swap HA (High Availability) signals...............................................3.33

3.5.2.6. IDE 1 Interface....................................................................................3.34

3.5.3. J5 Signal Specification ......................................................................................3.35

3.5.3.1. IDE 0 Interface....................................................................................3.35

3.5.3.2. USB 0 and 1 Interfaces.......................................................................3.35

3.5.3.3. Floppy Disk Interface...........................................................................3.36

3.5.3.4. Serial Port 2........................................................................................3.36

3.5.3.5. Serial Port 2........................................................................................3.36

3.5.3.6. Parallel Port.........................................................................................3.37

3.5.3.7. Miscellaneous Signals.........................................................................3.37

3.5.3.8. Keyboard Interface..............................................................................3.37

3.5.3.9. Mouse Interface...................................................................................3.37

v

4. SOFTWARE SETUPS

4.1. BIOS Setup Pr ogram.......................................................................................................4.1

4.1.1 Accessing the BIOS setup program.....................................................................4.1

4.1.2 Main Menu..........................................................................................................4.3

4.1.3 Setups.................................................................................................................4.4

4.1.4 Standard CMOS Setups......................................................................................4.5

4.1.5 Saving & Exiting Operations................................................................................4.5

4.1.6 BIOS Features Setup..........................................................................................4.6

4.1.7 Chipset Fea tu res Setup.......................................................................................4.8

4.1.8 Power Management Setup................................................................................4.10

4.1.9 PnP/PCI Configuration......................................................................................4.12

4.1.10 CPU/Board Featu res Setup...............................................................................4.13

4.1.11 Integrated Peripherals.......................................................................................4.14

4.2. VT100 Mode..................................................................................................................4.15

4.2.1 Requirements......................................................................................................4.15

4.2.2 Setup & Configuration .........................................................................................4.15

4.2.3 Running Without a Terminal ................................................................................4.16

vi

PART FIVE.– Installation and Settings

A. BOARD SPECIFICATIONS........................................................................................A-1

B. MEMORY & I/O MAPS...............................................................................................B-1

B.1 Memory Mapping............................................................................................................B-1

B.2 I/O Mapping....................................................................................................................B-2

C. INTERRUPT LINES................................................................................................... C-1

C.1 IRQ Lines........................................................................................................................C-1

C.2 DMA Channels ................................................................................................................C-1

D. BOARD DIAGRAMS.................................................................................................. D-1

D.1 Top Devices Surface Mount............................................................................................D-1

D.2 Assembly Bottom Diagram .............................................................................................D-2

D.3 Mounting Holes...............................................................................................................D-3

D.4 Connector Holes.............................................................................................................D-4

E. CONNECTOR PINOUTS............................................................................................E-1

E.1 cPCI-MXS64GX Connectors and Headers......................................................................E-1

E.2 J1 CPCI Bus................................................................................................................... E-2

E.3 J2 CPCI Bus................................................................................................................... E-3

E.4 J3 CPCI Bus................................................................................................................... E-4

vii

E.5 J4 CPCI Bus................................................................................................................... E-5

E.6 J5 CPCI Bus................................................................................................................... E-6

E.7 J12, Video (VGA)............................................................................................................E-6

E.8 J13, Serial Port 1 - RS-232............................................................................................. E-7

E.9 J14, mezzanine PCI........................................................................................................E-7

E.10 J15/J16, Ethernet 1 and 2............................................................................................... E-8

E.11 J17, PS/2 Keyboard/Mouse............................................................................................E-8

E.12 J18, CompactFlash Disk..................................................................................................E-8

E.13 J19, Storage mezzanine................................................................................................. E-9

E.14 J20, PMC......................................................................................................................E-10

E.15 J21, PMC......................................................................................................................E-11

E.16 Hot Swap Switch...........................................................................................................E-12

E.17 S1 – Reset Switch ........................................................................................................E-12

E.18 BT1, CMOS Battery Backup Connector........................................................................E-12

F. BIOS SETUP ERROR CODES ..................................................................................F-1

F.1 POST Beep....................................................................................................................F-1

F.2 POST Messages.............................................................................................................F-1

F.3 Error Messages .............................................................................................................. F-2

F.4 POST Codes...................................................................................................................F-3

G. EMERGENCY PROCEDURE.................................................................................... G-1

G.1 How to run Emergency Procedure..................................................................................G-1

G.2 Generate an Emergency Floppy Diskette :......................................................................G-2

H. GETTING HELP........................................................................................................ H-1

viii

1. PRODUCT DESCRIPTION

P

A

R

T

1. PRODUCT OVERVIEW

2. SPECIFICATIONS

3. HOT SWAP CAPABILITY

4. INTERFACING WITH THE ENVIRONMENT

5. COMPATIBILITY WITH KONTRON PRODUCTS

6. MEZZANINE CONCEPTS

1

1.1. PRODUCT OVERVI E W

Kontron’s 6U CompactPCI® system processor is ideal for data/telecommunication, CTI,
and industrial control/monitoring markets.

The cPCI-MXS64GX 6U CompactPCI system processor brings scalable multiprocessing
capability to the telecom and industrial automation markets. It is designed to operate as a
“system” processor and must be installed in CompactPCI system slot.

Fully hot swappable, the cPCI-MXS64GX communicates with other processor boards
using the CompactPCI backplane as the physical layer of a 1 Gb/s Ethernet.

To provide the necessary interconnect, support local versions of the following OSs:
Microsoft Windows NT, Microsoft Windows 2000, Linux, VxWorks and pSOS.

Multi-level PCI-to-PCI bridging is fully supported. Based on Intel’s 21154 PCI-to–PCI ­transparent bridge, the feature set of the cPCI-MXS64GX includes a rich selection of
standard peripherals.

The cPCI-MXS64GX offers a natural growth path to high performance, high availability as
well as hot swap and scalable multiprocessing technology.

The cPCI-MXS64GX can be ordered in either front I/O interfacing (video, serial port,
2xEthernet, all available on the face plate) or rear I/O interfacing through CPCI I/O
connectors J3, J4 and J5 (no interconnection capability on the face plate).

CompactPCI Connectors

Rear I/O CPCI connectors are PICMG 2.0 Rev 3.0 compliant. CompactPCI connectors are
located at the rear edge of the processor board. The complete CPCI connector configuration
of the cPCI-MXS64GX is composed of four connectors referred to as J1, J2, J3, J4, and J5.

Their function is described below:

J1 32 bit PCI signaling, power
J2 64 bit extension, arbitration, clocks, reset and. power
J3, J4, J5 Handle I/O sign als.



CompactPCI

connectors are also known as 2mm Hard Metric connectors.

1.1

cPCI-MXS64GX Technical Reference manual

1.2. PRODUCT SPECIFICATIONS

The cPCI-MXS64GX industrial system processor features:

• Intel’s enhanced performance Pentium

Low power Mobile Pentium®III 500 and 700MHz, 256KB on- die L2 pipeline d
burst cache.

• 440GX AGP set.

• Supporting up to 1.5GB SD RAM w ith pari ty or ECC .

• PCI Ultra DMA/33 IDE, SCSI-2 .

• 64-bit AGP SVGA CRT controller.

• CompactFlash™ Disk interfacing on primary EIDE channel, user upgradable,

master/slave.

• Ports available

• Two Universal Serial Bus (USB).

• Two 10/100Mbps Ethernet.

• Four serial ports (three RS-232 only: Serial Port 1, 2 and 4; one RS-

232/422/485: Serial Port 3).

• One Parallel port, bi-directional with all IEEE 1284 protocols su pport ed with

BIOS selectable IRQs and addressing.

• Mouse and keyboard available through front plate or Rear Transition Module.

• SCSI, supports 16-bit Ultra Wide LVD SCS I up to 80Mbps (L SI 53C 895)

• Floppy interface (360KB to 1.44MB).

• Optional hard disk/floppy mezzanine module for high level of integration.

• High availability controller capable to detect the insertion or removal of HA CPCI

peripheral boards.

• J3/J4/J5 connectors to handle I/O signals such as serial, parallel, and USB ports,

Ethernet and video, SCSI, and IDE interfaces, keyboard, speaker, mouse, and
reset signals, SMBus.

®

processor.

1.2

Product Description

Software:

• Enable/disable of Ethernet and SCSI ports by software.

• Enable/disable of video by hardware.

• Serial/parallel port mapping/disable by software

• Remote operation/monitoring (VT-100 s erial port cons ole redirection),

• Programmable two-stage watchdog timer by s oftware

• Fully compatible with existing application software using platforms PC and MS-



, Windows 3.1, Windows 95, Windows NT, Windows® 2000, OS/2

DOS



Warp, QNX, NOVELL, and UnixWare.

• Supports: Advanced Configuration and Power Interface (ACPI 1.0), Advanced

Power Management (APM 1.2), advanced thermal management (resume, overheat
alarm and auto slow down) and Green support.

• Hardware monitor (voltages, temperature, and fan speed),

• Power failure circuit

• Two year warranty.

The cPCI-MXS64GX can be purchased either for front plate I/O interfacing (video serial
port, Ethernet) or RTM (Rear Transition Module) I/O interfacing (no interconnection
capability available on the front plate) through CPCI I/O connectors and backplane.

" CompactPCI Connectors

Rear panel CPCI connectors are PICMG 2.0 Rev2.1 CompactPCI
CompactPCI connectors are located at the rear edge of the board. The complete CPCI
connector configuration is composed of five connectors referred to as J1, J2, J3, J4, and J5.



specification compliant.

Their function is described below:

J1/J2 carry out arbitration and PCI bus signals, and power.
J3/J4/J5 handle I/O signals.

CompactPCI



connector is also known as 2mm Hard Metric connector.

1.3

cPCI-MXS64GX Technical Reference manual

1.3. HOT SWAP CAPABILITY

The cPCI-MXS64GX supports Hot Swap capability which means that hot swappable
boards can be removed from or installed in the system while online (without powering­down the system).

Hot Swap consists of board hardware with the Hot Swap additions to the Hardware
Connection Layer, and the Hot-Plug Service. Upon insertion of the board (any hot
swappable board but the system host, cPCI-MXS64GX, the hardware connection layer will
initialize the board and the Hot-Plug Service provides the means for reconfiguring the
system.

High Availability is an attribute of a system designed to keep running (maintain
availability) in the event of a system component failure. To provide a high degree of
availability, a system requires a higher degree of control.

High Availability (HA) uses a higher degree of control than just indicating insertion a nd
extraction. HA systems are able to control the Hardware Connection Process. To do this,
the capabilities of the system are extended to allow software control of a board’s hardware
connection state. A hardware connection sequence is made possible through the use of
different pin lengths and the process ends with the mating of the shortest pin (BD_SEL#).

The platform adds hardware to provide more control of each board’s Hardware Connection
Layer. The signals: BD_SEL#, HEALTHY#, and PCI_RST# are used to individually
control each slot of the system.

BD_SEL# is one of the shortest pins. This pin is the last to mate and the first

to break contact. This ensures that the sensing of its connection
takes place at a time when all other pins are reliably connected. It is
driven low to enable power on. For systems not implementing
hardware connection control, it is grounded on the backplane.

HEALTHY# is used to acknowledge the health of the board. It signals that a

board is suitable to be released from reset and allowed onto the PCI
bus. In an HA system, the software can detect a faulty board when
it fails to assert HEALTHY# a fter BD_SEL# has been asserted . A
running board can also become not healthy at any time.

PCI_RST# as defined by the CompactPCI

®

Specification, is a signal on the
backplane, driven by the system host. Platforms may implement
this signal as a radial signal from the Hot Swap Controller to
further control the electrical connection process. Platforms that do
this must OR the system host’s reset signal with the slot specific
signal to maintain the bussed signal’s function.

1.4

Product Description

The Software Connection Control resources on the board provide a signal (ENUM#) for
system host notification and a switch and LED to interface with the operator.

Full Hot Swap boards drive the ENUM# signal to the system host to indicate a service
request. This signal is provided to notify the system host that either a board has been
freshly inserted or is about to be extracted. This signal informs the system host that the
configuration of the system has changed. The system host then performs any necessary
maintenance such as installing a device driver upon board insertion, or unloading drivers
for hot swap boards that are about to be extracted. The application that is using the board is
also notified that the resource will no longer be available.

The Hot Swap Switch allows the operator to indicate desire to extract the board. A blue
LED, located on the front of the board, is illuminated when it is safe to extract the board.
This LED indicates that system software has been placed in a state for orderly extraction of
the board. The hardware connection layer provides protection only for the hardware during
insertions and extractions. This method allows the operator to insert or extract boards
without the extra step of reconfiguring the system at the console.

All actions are initiated by the operator, and must be performed in the correct
sequence for proper system operation.

Full Hot Swap boards present the following resources to software executing on the syste m
host (nominally implementing the Hot-Plug Service and Hot-Plug System Driver)

" An ENUM# signal, which is an open collector (open drain) bussed signal, to

signal a change in status for the board.

" A switch actuated with the lower ejector handle, indicating the beginning of

the extraction process or end of the insertion process.

" A LED to indicate the status of the software connection process.
" A set of four control and status bits on each board allows the system host’s

software to determine the source of the ENUM# signal and control the LED.
Full Hot Swap boards allow the full range of system capabilities.

1.5

cPCI-MXS64GX Technical Reference manual

1.4. INTERFACING WITH THE ENVIRONMENT

1.4.1. CPCI

The cPCI-MXS64GX system processor is provided for rack-mounted systems to offer the
highest modularity. Through the J1/J2 segment, the board can drive up to seven external
CompactPCI slots, supporting individual REQ/GNT arbitrat i on pair sign als and cl ock.

✎ NOTE

All I/O signals are available in front I/O and rear I/O configuration.
A. In front I/O configuration, the following I/Os signals are available on

the faceplate: SVGA, Serial Port 1, Ethernet 1 and 2, keyboard and
mouse. All other I/Os are connected to J3-J5.

B. In Rear I/O configuration, all I/O signals are connected to J3-J5

A backplane dedicated to the cPCI-MXS64GX is provided by Kontron
and is referred to as cBP08R, CPCI Passive Backplane.

1.4.2. Mezzanine

The mezzanine is a hardware interface concept introduced by Kontron to increase t he I/O
connectivity of the cPCI-MXS64GX, but respecting the dual slot 6U form factor restrictions.

The onboard mezzanine connector features PCI bus, IDE, floppy, keyboard and mouse
signals, for potential mezzanine applications: Kontron provides an optional storage
mezzanine composed with a hard drive, a floppy disk drive.

✎ Note

A bridge can be added on the mezzanine to support 7 extra slots. These slots
support HA CPCI I/O boards

A complete CompactPCI development system CxP-0816 is also available from Kontron.

1.6

Product Description

1.5. COMPATIBILITY WITH OTHER KONTRON PRODUCTS

The cPCI-MXS64GX System Processor is a member of the Kontron’s CompactPCI
product family.

The boards are fully compliant with the PICMG 2.0 Rev.2.1 and PICMG 2.1 CompactPCI
specifications.

When building a basic environment around the cPCI-MXS64GX, the platform may be
composed of any of the following devices:

• cPCI-MXS64GX 6U System Processor

• cMC Mezzanine card with hard disk and floppy disk drive

• cMCB Mezzanine card with bridge, hard disk and floppy disk

• cSM-DVDHD Storage module with DVD and Hard Disk

• cSM-DVD Storage module with DVD only

• CxP0816 including

• 8U 19-inch enclosure

• Front loaded hot swappable 2U fan tray

• Power supply (300W ATX or 350W AC or DC in single or red unda nt

configuration)

• One of the following backplanes:

cBP-08R : 8 slots CompactPCI (PICMG 2.1)
cBP-16R, 16 slots CompactPCI (PICMG 2.1)
cTBP-08R, Telephony 8 slots HA CompactPCI

(PICMG 2.5)
cTBP-16R 16 slots Telephony HA CompactPCI

(PICMG 2.5)

• cTM80-STD2S 6Ux8HPx80mm Rear Transition Module, standard pinout.

1.7

cPCI-MXS64GX Technical Reference manual

1.6. MEZZANINE CARD CONCEPT

The capability of the cPCI-MXS64GX to connect with other devices is enforced by PCI
Mezzanine Cards (PMC). A fully equipped cPCI-MXS64GX board may appear as follows:

1.8

Product Description

1.6.1. Kontron’s Mezzanine Concept

This is Kontron’s concept to expand the I/O capability of the board. It is built around t wo
connectors:

• Mezzanine connector handling IDE and floppy disk drive signals.

• Mezzanine connector handling a complete PCI signal set (primary bus)

including the REQ/GNT arbitration signal pair.

These two connectors represent an open door for future development of expansion and I/O
mezzanine cards.

A Mezzanine Card referred to as cMC and cMCB are available from Kontron.

1.6.2. PMC Concept

PCI Mezzanine Card (PMC) is a standard specification that allows PCI I/O devices to be
connected to the PCI bus. It conforms to the ANSI/IEEE P1386.1 specification that defines
Standard Physical and Environmental Layers for PMC devices.

The cPCI-MXS64GX features the PMC concept onboard to provide an extra method to
support the 32-bit I/O devices available on the market.

PMC devices connect directly to standard PMC connectors. A mechanical cutout (with its
EMI proof cap) is provided to allow integrated connectors and indicators to be available
directly on the front plate through PMC card.

1.6.3. CompactFlash Feature

The cPCI-MXS64GX board also supports standard CompactFlash disk through a
CompactFlash module.

CompactFlash disk is a method of storing and transferring data. It is supported on the board
as a standard IDE drive and connects to the secondary EIDE interface.

The CompactFlash drive can be set as a Master or Slave device and combined with any
standard hard disk drive by setting the jumper W3 (see Section 3.1, setting jumpers).

CompactFlash is installed on J18 connector. For more information on CompactFlash
installation and setups, please refer to Section 2.1 – CompactFlash Interface.

1.9

2. ONBOARD FEATURES

P

A

R

T

1. COMPACTFLASH INTERFACE

2. ENHANCED IDE INTERFACES

3. ETHERNET INTERFACES

4. FLOPPY DISK INTERFACE

5. PS/2 KEYBOARD AND MOUSE INTERFACE

6. PARALLEL PORT

7. POWER MANAGEMENT

8. SCSI INTERFACE

9. SERIAL PORTS

10. THERMAL MANAGEMENT

2

11. USB INTERFACES

12. VIDEO INTERFACES

Onboard Features

2.1. COMPACTFLASH INTERFACE

The board supports an IDE compatible flash disk by using a CompactFlash module.
CompactFlash (C-Flash) disks are the resident industry-standard ATA/IDE subsystem for
application, data, image, and audio storage. They have the same functionality and
capabilities as intelligent disk drives, but with the advantages of being very compact,
rugged (typical M.T.B.F. is 1,000,000 hours) and low power. The cPCI-MXS64GX
supports all CompactFlash sizes presently available and future sizes when available.

The C-Flash disk connects on the cPCI-MXS64GX via the onboard Flash Disk connector.

Related Jumpers

cPCI-MXS64GX: W3 to set the CompactFlash disk as master or slave.

BIOS Settings

Section 4.1.2 Main Menu: Hard Disk autodetect to set the type of hard disk.

2.1.1. Setups

The CompactFlash disk connects directly on the Secondary EIDE interface. It must be
declared the same way as a standard hard disk using the BIOS setup program (Autodetect
function).

To setup the CompactFlash disk for Master or Slave configuration, use the CompactFlash
jumper located on the system processor.

To locate and install this jumper, please refer to Section 3.1, Setting Jumpers.

✎ NOTE

Since device use ATA/IDE interface, no specific flash disk driver is
required for various operating systems.

2.1

cPCI-MXS64GX Technical Reference Manual

2.2. ENHANCED IDE INTERFACES

The board features two channel Bus Master PCI EIDE dedicated to Primary and Secondary
IDE logical interfaces. Each channel supports up to two IDE devices (including CD-ROMs,
hard disks, plus CompactFlash on the secondary IDE interface) with independent timings,
in Master/Slave combination.

Signal Paths

The primary IDE interface is available through both the CPCI I/O connector and the
Mezzanine connector.

The secondary IDE interface is only available through the CPCI I/O connector.

Related Jumpers

None

BIOS Settings

Section 4.1.11 Integrated Peripherals.

The IDE interfaces supports PIO mode 4 transfers up to 16.6MB/sec and Bus Master IDE
transfer up to 33MB/sec (Ultra-DMA 33). It does not consume any ISA DMA resources
and integrates 16x32-bit buffers for optimal transfers.

CAUTION

When connecting IDE devices to the Primary IDE interface, Master and
Slave devices must be shared in respect of the device allocation on both
the CPCI I/O connector and the mezzanine

Two Master devices (or two Slave devices) must not be installed on the
same interface at the same time.

2.2

Onboard Features

2.3. ETHERNET INTERFACES

Both Ethernet controllers reside on the Primary PC I bus.
Each interface supports 10Base-T and 100Base-TX specifications: 10Mbps and 100Mbps

network speeds are automatically detected and switched.

Signal Path

See note on page 1.5.

Related Jumpers

None.

BIOS Settings

Section 4.1.11 Integrated Peripherals: Enable/Disable Ethernet Controller.

2.3.1. Front Plate Configuration

Ethernet 1 and 2 signals are available on front plate connectors only when the board is
ordered for front access.

Activity and link indicators are built in the connector.

2.3

cPCI-MXS64GX Technical Reference Manual

2.3.2. CPCI I/O Configurati on

Ethernet 1 and 2 signals are available on CPCI I/O connectors only when the board is ordered
for rear access.

CAUTION
The combination of both front and rear panel configurations is not supported.

The Boot from LAN capa bility is supported. To enable the optio n, use the BIOS Setup
program. Please refer to Section 4.1 BIOS Setu p Prog ram .

A diskette entitled “Network Drivers for Intel 82559 is included with the cPCI-MXS64GX.
It contains network drivers for most common operating systems.

2.4. FLOPPY DISK INTERFACE

The onboard floppy disk controller is IBM PC XT/AT compatible. It handles 3.5” and

5.25”, low and high density disks. Up to two drives can be supported in any combination.

Signal Paths

The Floppy Disk Controller interface is available through the CPCI I/O connector and
through the Mezzanine connector (see section 1.4.1)

Related Jumpers

None.

BIOS Settings

Section 4.1.4 Standard CMOS: Select type of floppy.
Section 4.1.11 Integrated Peripherals: Enable/Disable onboard FDC Controller.

2.4

Onboard Features

2.5. PS / 2 KEYBOARD / PS/2 MOUSE INTERFACE

The onboard keyboard controller is 8042 software compatible. PS/2 Keyboard and mouse
signals are available through an output that supports direct connection to the interface.
Since signals of both devices are combined on the same connector, a Y-cable is required to
split the signals and feed a standard AT keyboard and a PS/2 mouse.

Signal Path

PS/2 keyboard and PS/2 mouse signals are available through J5 CPCI I/O connector
and J14 Mezzanine connector.

Related Jumpers

None.

BIOS Settings

11.3.7 Integrated Peripherals : USB Keyboard Support; PS/2 Mouse Function Control

2.6. P ARALLEL PORT

The cPCI-MXS64GX features one multi-mode parallel port. It is compatible with Standard
Mode IBM PC/XT, PC/AT, and PS/2 compatible bi-directional parallel port, Enhanced
Parallel Port (EPP), and Enhanced Capabilities Port (ECP).

Signal Path

The Parallel Port interface is only available through J5 CPCI I/O connector.

Related Jumpers

None

BIOS Settings

Section 4.1.11 Integrated Peripherals: Onboard Parallel Port; Parallel Port Mode

2.5

cPCI-MXS64GX Technical Reference Manual

The differences between Standard, EPP, and ECP modes appear in the signal assignation of

the pins on the connector. Differences are described as follows:

Pin Number (J5)

A15 SLCT
B15 PE
C15 BUSY
D15 /ACK
E16 /SLCTIN
B17 /INIT
D17 /ERR
A18 ALF
E17 PD0 PD0 PD0

C17 PD1 PD1 PD1
A17 PD2 PD2 PD2
D16 PD3 PD3 PD3
C16 PD4 PD4 PD4
B16 PD5 PD5 PD5
A16 PD6 PD6 PD6
E15 PD7 PD7 PD7

1

Compatible mode

2

High Speed Mode

Standard Mode EPP Mode ECP Mode

-

- PERROR
WAIT BUSY
/INTR /ACK
/ADDRSTRB /SLCTIN

- /INIT

- /FAULT
DATASTB ALF

SLCT

1

, PERIPHACK

1

, /REVERSERQST

1

, HOSTACK

✎ NOTE

To operate in EPP or ECP mode, ensure the peripheral is designed to work in
this mode and the BIOS setup is configured to support it.

1

, ACKREVERS

1

, /PERIPHRQST

2

2

2

2

2

2.6.1. Standard Mode

The Standard mode is unidirectional. It is supported to maintain the compatibility with the
IBM PC standard.

2.6.2. EPP Mode

The EPP (Enhanced Parallel Port) mode consists of a hardware independent method of
accessing a parallel port configured as EPP. It provides support for single I/O cycle as well
as the high performance block I/O transfers. The EPP mode always uses the most optimum
method for I/O transfers. For example, if the hardware supports it, EPP mode will perform
32-bit I/O block transfers.

2.6

Onboard Features

EPP mode assumes that the parallel port can be used to connect more than one peripheral
device using multiplexor or dais y cha in configurations.

A multiplexor is an external device that permits up to eight parallel port devices to share a
single parallel port.

A daisy chain device has two ports: input and output. The input port is connected either to
the host parallel port or the daisy chain device in front of it. The output is used to co nnect
the next peripheral device to the daisy chain. The last device, however, can be one without
daisy chain support.

2.6.3. ECP Mode

ECP (Extended Capabilities Port) works the same as EPP mode, but it will ta ke pr ecedence
over the EPP mode when addressing multiple logical devices in a single physical product.
While the EPP mode may intermix read and write operations without any overhead or
protoco l handshaking, the ECP mode negotiates data transfers using a re quest from the host
and an acknowledgment from the peripheral.

✎ NOTE

For more information on the ECP protocol, please refer to the
Extended Capabilities Port Protocol and ISA Interface Standard (available
from Microsoft Corporation) or contact our Technical Support department.

2.7. POWER MANAGEMENT

Power Management features are supported at the BIOS level. All Power Management
options are described in Section 4.1.8 – Power Management Setup.

2.8. SCSI INTERFACE

The boards feature SYM53C895 PCI to Ultra2 SCSI I/O Processor. Supports Ultra2
SCSI synchronous transfer rates up to 80 Mbytes/s on a 16-bit, LVD SCSI bus..

Signals are available through J3-J4 CPCI I/O connector.

2.7

cPCI-MXS64GX Technical Reference Manual

Signal Path

SCSI interface signals are only available through the J3-J4 CPCI I/O connector or
through RTM (Rear Transition Module).

Related Jumpers

W6 – To determine the SCSI termination (hardware, software or disabled)

BIOS Settings

11.3.7 Integrated Peripherals: Enable/Disable the Onboard PCI SCSI Chip.

To operate with SCSI devices the onboard SCSI controller must enabled through the
AWARD BIOS setup program

.

2.9. SERIAL PORTS

Four full function serial ports are provided on the board for asynchronous serial
communications. They are 16C550 high-speed UART compatible and support 16-byte FIFO
buffers for transfer rates from 50bps to 115Kbps .

Each serial port is specified as follows:

Designation Communication Mode Output Path

Serial Port 1 RS-232 Front Plate DB-9, CPCI J5
Serial Port 2 RS-232 CPCI J5
Serial Port 3 RS-232, RS-422, RS-485 CPCI J3
Serial Port 4 RS-232 CPCI J3
Serial Port 3 Infrared CPCI-J3

UART registers are individually addressable and fully programmable.

2.8

Onboard Features

2.9.1. SERIAL PORT 1

Serial Port 1 is buffered directly for RS-232 operation. Sign als include the complete signal set
for hands haking, modem con trol, interrupt ge neration, and dat a transfer. When as signed as
Serial Port 1, the port is 100% compatible with the IBM-AT serial port in RS-232 mode.

Signal Path

Serial Port 1 signal path depends on the output configuration you hav e ordered for the

board

Related Jumpers

W5 – Remote reset on Serial Port 1 or Ser ial Port 2 or disabled

BIOS Settings

Section 4.1.11 Integrated Peripherals : Enable/Disable Onboard FDC Controller;

Select Com Port Address of Serial Port 1

2.9.1.1. Remote Reset

A remote hardware reset of the cPCI-MXS64GX is possible by sending a break on the Serial
Port 1 or Serial Port 2 (see section 3.1 for Remote Reset jumper setting). A break is simple an
abnormally long start bit (100ms or more) on the incoming data line. A break signal is
embedded in the data, so no special wire is required.

Related Jumpers

W5– Remote reset on Serial Port 1 or Serial Port 2 or disabled to select whether the

serial port 1 or 2 is used to control the remote reset

Bios Settings

None

2.9

cPCI-MXS64GX Technical Reference Manual

The remote reset will work in RS-232 and RS-422 modes. It will also work with a modem,
since the modem will repeat the break signal over the telephone network. All major
telecommunication software have the capability of sending a break signal, usually by pressing
the CTRL-B keys or the ALT-B keys on the keyboard. Only a standard telephone line and a
modem in auto-answer mode are needed. The only limitation is that the communication speed
must be 1200bps or more. If the communication speed is to slow, a false reset can occur.

The break signal is entirely detected by hardware. For truly remote operation, use the VT-100
mode, which allows remote BIOS setup and console redirection.

2.9.1.2. Front Plate Configuration

The Serial Port 1 signals are available through a DB -9 connector located on the front plate.
CPCI I/O Configuration

The complete signal set is tied to the J5 CPCI I/O connector to be used through the Rear
Transition M o dule (R TM ) .

2.9.2. Serial Port 2

Serial Port 2 is buffered directly for RS-232 operations and is 16C550 PC-Compatible. The
interface includes the complete signal set for handshaking, modem control, interrupt
generation, and data transfer.

The Serial Port 2 port is 100% compatible with the IBM-AT serial port.

Signal Path

Serial Port 2 signals are available through the J5 CPCI I/O connector. The infrared
COM2 signals (COM2_IRRX and COM2_IRTX) are available at J3 connector.

Related Jumpers

None

BIOS Settings

Section 4.1.11 Integrated Peripherals: Onboard Serial Port 2

2.9.3. Serial Port 3

The Serial Port 3 supports Infrared, RS-232, RS-422, and RS-485 operation modes. When
assigned as Serial Port 3, the port is 100% compatible with the IBM-AT serial port in RS-232
mode.

2.10

Onboard Features

RS-422 and RS-485 modes allow communication using differential signals through one pair
of wires (RS-485) or two (RS-422) to increase th e noise immunity during data transfers.

RS-422 and RS-485 protocols offer advantages such as increased speed over longer distances
or improved reliability over similar RS-232 setups.

Signal Path

In RS-232, RS-422, and RS-485 operation modes Serial Port 3 signals are only
available through the J3 CPCI I/O connector.

Related Jumpers

W8 & W9 to connect/disconnect
RS-422/RS-485 termination resistors (see Section 3.1, Setting Jumpers)

BIOS Settings

11.3.7 Integrated Peripherals: Onboard Serial Port 3; Serial Port 3 Mode.

Upon a power-up or reset, the Serial Port 3 interface circuits are a utomaticall y configured for
the operation mode setup in the BIOS. The Serial Port 3 signal assignation on the J3 CPCI
I/O connector depends on the operation mode (RS-232, RS-422, or RS- 485) i t has been s e t:

Pin Number (J3)

A11 /JDCD2
C11 JRXD2
D11 /JDSR2
E11 JTXD2
A12 /JRTS2
B12 /JCTS2
C12 /JRI2
E12 /JDTR2

RS-232 RS-422 RS-485

/DCD /DCD
RX(-) RX/TX(-)
DSR DSR
TX(-) ­RX(+) RX/TX(+)
TX(+) ­/RI /RI
/DTR /DTR

2.9.3.1. Infrared Mode:

Infrared (IR) interface signals are provided to drive IR module for remote operations through
Serial Port 3. When set in IR mode, the IR interface supports multi-protocol infrared
operations. The IR interface is IrDA 1.1 compliant, and supports TEMIC/HP modules,
SHARP ASK IR, and consumer IR.

2.11

cPCI-MXS64GX Technical Reference Manual

2.9.3.2. RS-232 Protocol:

When configured for RS-232 operation mode, the Serial Port 3 is 100% compatible with the
IBM-AT serial port signals.

2.9.3.3. RS-422 Protocol:

The RS-422 protocol (Full Duplex) uses both RX and TX lines during a communication
session.

CAUTION

In RS-422 mode, W8 and W9 jumper caps must be installed to connect the
120 ohms termination resistors (See Section 3.1 Jumper Settings)

2.9.3.4. RS-485 Protocol:

The RS-485 protocol (Half Duplex) also uses differential signals during a communication
session. It differs from the RS-422 mode as it offers the ability to transmit and receive over
the same pair of wires, and allows the sharing of t he communication line by multiple stations.
This configuration (also known as Party Line) allows only one system to take control of the
communication line at the time.

In RS-485 mode, the RX lines are used as the transceiver lines, and the RTS signal is used
to control the direction of the RS-485 buffer.

When set for RS-485 mode in the BIOS, upon power-up or reset, the transceiver is by
default in receiver mode to prevent unwanted perturbation on the line. Party line operation
mode requires termination resistors to be installed at both ends of the network.

2.12

Onboard Features

CAUTION
When installing the cPCI-MXS64GX at one end of the network, W8 and W9

jumper caps must be installed to connect the 120 ohms termination resistors

(See Section 3.1 – Setting Jumpers).

2.9.4. Serial Port 4

The Serial Port 4 is buffered directly for RS-232 operations and is 16C550 PC-Compatible.
The interface includes the complete signal set for handshaking, modem control, interrupt
generation, and data transfer.

When assigned as Serial Port 4 logical port, the port is 100% compatible with the IBM-AT
serial port.

Signal Path

Serial Port 4 signals are only available through the J 3 CPCI I/ O connector.

Related Jumpers

None

BIOS Settings

11.3.7 Integrated Peripherals: Onboard Serial Port 4; IRQ Line for Serial Port 4.

2.10. THERMAL MANAGEMENT

Two temperature sensors are provided to supervise the thermal environment. One is used to
monitor the CPU die temperature, while the second one, located on the CPU casing, allows
the monitoring of the ambient temperature around the CPU.

The temperature is controlled according to two temperature levels, the Low temperature
limit, which indicates normal operating conditions, and the High temperature limit, which
indicates an overheating condition.

2.13

cPCI-MXS64GX Technical Reference Manual

The temperature management consists in reducing the CPU clock speed throttling when the
temperature goes over the high limit (overheating condition) and suspending the throttling
operation as soon as the temperature returns under the low temperature limit (normal
condition).

The clock speed may be throttled by a CPU overheating due to the fan failure. In such a
case, the temperature control is triggered as soon as the temperature reaches the high
temperature limit of the die.

The ambient temperature of the CPU generally raises up due to an augmentation of the
temperature in the casing. In that case, the clock speed will be slowed down as soon as the
ambient temperature reaches the high ambient temperature value.

Thermal management operations are controlled by the GX chipset, and settings are
provided through the BIOS setup program interface, Thermal Management Setup option
(See Section 4.1.10 CPU Board Feature Setup, Thermal management Options).

2.11. USB INTERFACES

Signals for two USB ports are available through the CPCI I/O connector J5.
The USB strengths are as follows: capability to daisy chain as many as 127 devices per

interface, fast bi-directional, isochronous/asynchronous interface, 12Mbps transfer rate, and
standardization of peripheral interfaces into a single format.

Signal Paths

Both USB 0 and USB 1 interface signals are available through the CPCI I/O connector
(J5).

Related Jumpers

None

BIOS Settings

4.1.9 PnP/PCI Configuration: Assign IRQ For USB

2.14

Onboard Features

USB supports Plug and Play and hot swapping operations (OS level). These user-friendly
features allow USB devices to be automatically attached, configured and detached, without
reboot or running setup.

The cPCI-MXS64GX board fully supports the standard universal host controller interface
(UHCI) and uses standard software drivers that are UHCI-compatible.

2.12. VIDEO INTERFACE

The high-performance video capability of the board is based on Accelerated Graphics Port
(AGP) technology. The video controller, Intel 69000, with its integrated 2Meg of high
performance SDRAM is capable of CRT resolutions up to 1024 x 768 x 64K colors or
1280 x 1024 x 256 colors.

The video interface features 64-bit 2D graphics engine, 64-bit GUI accelerator engine with
multiple window video acceleration.

Signal Path

The VGA video signal path depends on the output configuration you have ordered for
the board.

Related Jumpers

W7 to enable or disable onboard VGA feature.
See section 3.1 – Jumper Settings

BIOS Settings

4.1.9 PnP/PCI Configuration: Init Display First; Assign IRQ for VGA

" Front Plate Configuration

VGA interface signals are available on J12, standard VGA connector, located on the
front plate of the board, only when the board is ordered for front access operations. This
configuration allows direct connection of CRT display onto the board.

" CPCI I/O Configuration

VGA interface signals are available on J4 CPCI I/O connector only when the board is
ordered for rear panel output operations.

2.15

cPCI-MXS64GX Technical Reference Manual

2.12.1. Supported Resolutions

The maximum video resolution and performance depend directly on the drivers running
with your software application. Resolution and number of colors specification are listed
below:

Resolution Number of Colors

640x480, 800x600, 1024x768, 1280x1024 256 (8 bits)
640x480, 800x600, 1024x768 65,536 (16 bits)
640x480, 800x600 16.8 million (24 bits)
640x480, 800x600 16.8 million (32 bits)

2.12.2. Major Features Description

" VGA Compatibility

The video controller includes all registers and data paths required for VG A controller
and supports extensions to VGA, including resolutions up to 800x600x16.8 million
colors non-interlaced. The 16-bit images are displayed at up to 1024x768 resolution.

" 2D Graphics Engine

The 2D graphics engine is an advanced 32-bit three-operand engine that accelerates
BitBLTs as line draws, polygon draw, and polygon fill. T he 2D graphics engine also
performs video and bitmap scaling, and data overlay.

2.16

3. I NSTALLING THE BOARD

P

A

R

T

1. SETTING JUMPERS

2. REGISTER’S DESCRIPTION

3. ONBOARD INTERCONNECTIVITY

4. CUSTOMIZING THE BOARD

5. BUILDING A CPCI SYSTEM

6. CPCI I/O SIGNALS

3

3.1. SETTING JUMPERS

3.1.1. Jumper Description for the CPCI-MXS64GX

Description

VT-100 Mode (1-2) When enabled, allows VT100 or ANSI terminal

connection

Download Mode (3-4) When enabled, allows data serial download from

a remote computer.

Board Configuration Defines if used with Front Access or Rear

Access

CompactFlash Setting Use this connector to setup the CompactFlash

device in Master or Slave configuration.

Onboard Battery Connects or Disconnects the battery to/from the

board circuitry.

Remote Reset To select Serial Port 1 or Serial Port 2 as a

source for the remote hardware reset.

SCSI Termination Use this jumper to disable SCSI termination or

select the termination control method from
Software Controlled and Hardware Controlled
options.

Onboard Video Use this jumper to enable or disable the onboard

video feature.

Serial Port 2 Termination Use these j umpers to connect or disconnect the

termination resistors on/from Serial Port 3 when
set for RS-422/RS-485 operation mode 0.

W1

W2

W3

W4

W5

W6

W7

W8, W9

3.1

cPCI-MXS64GX Technical Reference Manual

3.1.2. CPCI-MXS64GX – Jumper Setti ngs

J12

DS1

J13

J17

J15

J16

S1

7

1

7

1

11

W4W3

W4 Battery

Connected
Disconnected

*

in

out

W1

W2

1

4

123

W3 Compact Flash Disk

Master
Slave

*

in

out

W2 Board Configuration

Rear Access
Front Access

W1 VT-100 / Download Mod e

Enable VT-100 mode
Reserved

1

2

in

out

8HP Configuration

1-2
3-4

4HP Configuration

* Default Setting

8

2

40

8

2

39

CompactFlash

W8, W9 COM2 Terminations

RS-422/485 modes only
With termination
Without termination

*

W5 Remote Reset

Reset by COM1
Reset by COM2
Disabled

*

W8 W9
in in
out out

1-2
2-3
none

J20 J21

Mezzanine

PMC

J24

W7 Onboard Video

Disabled in
Enabled out

*

W6 SCSI Active Termination

Software controlled 1-3
Hardware controlled 2-4

*

Always disabled None

123

3.2

W6

1111

3

4 2

W7

W8

W9

Installing the Board

3.1.3. Register’s description RS232/RS485

CPLD Address D7 D6 D5 D4 D3 D2 D1 D0

READ n90h* NU NU NU RS485 RS232 ST1 NU NU

WRITE n90h* NU NU NU RS485 RS232 ST1 NU NU

Power-up Default 0 1 0

ST1 : Enable RTS2 to be used as 485TX ENABLE when in 485 mode
RS232 : Enable UART2 RS232 operation
RS485 : Enable UART2 RS422 and 485 operation

The serial port 2 mode can be controlled by setting three bits. Here are the possibilities.

Mode Bit RS485 Bit RS232 Bit ST1

RS232 0 1 X
RS422 1 0 0
RS485 10 1

X : Don’t care

3.1.4. History and monitor status

CPLD Address D7 D6 D5 D4 D3 D2 D1 D0

READ n91h* PBRST NU WDO NU NU NU NU PFO
WRITE n91h* NU NU NU NU NU NU NU NU
Power-up Default

PFO : Read the external power fail flag
PBRST : When high, indicate that the last system reset was caused by push button reset

WDO : When high, indicate that the last system reset was caused by watchdog time out

switch

3.3

cPCI-MXS64GX Technical Reference Manual

3.1.5. Multimedia, History status

CPLD Address D7 D6 D5 D4 D3 D2 D1 D0

READ n92h* NU NU NU NU NU WD_LOCK NU CLRHIS

WRITE n92h* NU NU NU NU NU WD_LOCK NU CLRHIS

Power-up Default 1 1

CLRHIS : When low, clear all history bits. Put this bit to 1 to enable history logging.
WD_LOCK : When high, lock the state of the enable bit for the digital watchdog

3.1.6. Monitoring status and I/O access

CPLD Address D7 D6 D5 D4 D3 D2 D1 D0

READ n93h* NU NU NU NU IDCHIP NU I2C_CLK I2C_DATA

WRITE n93*h NU NU NU NU IDCHIP NU I2C_CLK I2C_DATA

Power-up Default 0 0 0

I2C_DATA : I2C data
I2C_CLK : I2C Clock
IDCHIP : One-wire clock/data for silicon ID chip

3.1.7. Uart 3 PnP configuration

CPLD Address D7 D6 D5 D4 D3 D2 D1 D0

READ n94*h CND3 CIS3_1 CIS3_0 CBAS3_1CBAS3_0 ReservedReservedReserve
WRITE n94*h CND3 CIS3_1 CIS3_0 CBAS3_1CBAS3_0 ReservedReservedReserve
Power-up Default 0 0 0 0 1 0 0 1

CND3 : When low, decode the base address.
CIS3_[1..0] : COM port interrupt select.
CBAS3_[1..0] : COM base address select.

3.4

d
d

Installing the Board

The serial port 3 & 4 interrupt can be controlled in the following way.

CIS Bit 1 Bit 0

IRQ 3 0 0
IRQ 4 0 1
IRQ 5 1 0
IRQ 7 11

The serial port 3 & 4 base address can be controlled in the following way.

CBAS Bit 1 Bit 0

3F8 0 0

2F8 0 1
3E8 10
2E8 11

3.1.8. Uart 4 PnP configuration

CPLD Address D7 D6 D5 D4 D3 D2 D1 D0

READ n95* CND4 CIS4_1 CIS4_0 CBAS4_1CBAS4_0

WRITE n95* CND4 CIS4_1 CIS4_0 CBAS4_1CBAS4_0 NU

Power-up Default 0 0 0 1 1

CND4 : When low, decode the base address
CIS4_ : [1..0] COM port interrupt select.
CBAS4_ : [1..0] COM base address select.

3.1.9. Digital watchdog

CPLD Address D7 D6 D5 D4 D3 D2 D1 D0

READ n96* WDEN WDD2 WDD1 WDD0 NU NU NU NU

WRITE n96* WDEN WDD2 WDD1 WDD0 NU NU NU NU

Power-up Default 0 0 0 1

WDEN : Enable/disable digital watchdog.
WDD[2..0] : Durat i on of digital watch dog.

3.5

cPCI-MXS64GX Technical Reference Manual

The digital watchdog duration can be controlled in the following way.

WDD[2..0] NMI(T) RESET(T)

000 16T NMI(T)+8T

001 64T NMI(T)+8T

010 256T NMI(T)+8T

011 1024T NMI(T)+8T

100 4096T NMI(T)+8T

101 16384T NMI(T)+8T

110 65536T NMI(T)+8T

111 262144T NMI(T)+8T

Time-out selection with T = 1.08ms (TBC)

3.1.10. NMI control

CPLD Address D7 D6 D5 D4 D3 D2 D1 D0

READ n97* BATFEN BATFLT NU NU NU NU WDNMIEN WDNMI

WRITE n97* BATFEN NU NU NU NU NU WDNMIEN NU

Power-up Default

WDNMI : When high, signal NMI from watchdog time-out.
WDNMIEN : Enable NMI generation from digital watchdog
BATFLT : When high, signal NMI from local RTC battery monitor
BATFEN : Enable NMI generation for bat fault.

0 0

3.6

3.1.11. 0Register BITs description (summary)

Installing the Board

Address

n90*

n91*

n92*

n93*

n94*

n95*

n96*

n97*

n98*

n99*

n9A*

n9B*

CPLD D7 D6 D5 D4 D3 D2 D1 D0

READ

WRITE

READ PBRST WDO PFO

WRITE NU

READ

WRITE

READ

WRITE

READ

WRITE

READ RESERV.

WRITE

READ

WRITE

READ BATFLT WDNMI

WRITE

READ

WRITE

READ

WRITE

READ RESERVED

WRITE

READ RESERVED

WRITE

_CND3 CIS3_1 CIS3_0 CBAS3_1 CBAS3_0 RESERVED

_CND4 CIS4_1 CIS4_0 CBAS4_1 CBAS4_0 NU

WDEN WDD2 WDD1 WDD0 NU

BATFEN

NU

NU RS485 RS232 ST1 NU

NU

NU

NU

NU

NU

NU IDCHIP NU

NU

RESERVED

RESERVED

NU

NU

WD_LOCK

NU

NU _CLRHIS

I2C_CLK

WDNMIEN

I2C_DATA

NU

NU

NU

The base address for the Supervisor I/O Register, which is used for such functions as power fail
detection and the watchdog timer can be set to 190h, 290h, and 390h (see Chipset Features Setup).

3.7

cPCI-MXS64GX Technical Reference Manual

A

A

A

A

3.2. ONBOARD INTERCONNECTIVITY

3.2.1. cPCI-MXS64GX Block Diagram

Lithium

3.6V

2 Stage

Watchdog

IDE2
on J5

4

6
2
1

35

Mouse
& Keyboard

System Clock

J20 J21

Mezzanine

PMC

Intel

82371AB

PCI-ISA

324PBGA

CPCI J4/J5

Mouse
Keyboard
Com 1 & 2
Floppy
Printer

PIIX4

Bridge

IDE1 on

J4

Compact

Flash

Mezzanine

CPCI J4/J5

SMBus

SYM53C895

LVD

CPCI J3/J4

SMC

Super

I/O

Controler

FDC37C672

+

Prog WD

XTAL

Clocks

Synthes. &

Buffers

3.3V, 33MHz Primary PCI Bus

XTAL

SCSI

EEPROM

Term

PCI Kontron’s Mezzanine

XTAL

COM3

16C550

Com1

RS-232 Buffer

Part of CPCI J3

Intel C uM ine PIII

GP

EEPROM

RJ-45

CompactPCI J3/

J4 Connectors

BIOS

Block

512K

256KB

L2 Cache

Thermal

Sensor

XTAL

BOOT

MPIII Core

MPIII Core

500Mhz

500MHz

82443BX

North Bridge

492PBG

COM3

16C550

100Base-T

GTL+

Intel

82559

Ethernet

#1

3.3V, 16 Bit ISA Bus

69000
Video

Controller

rbiter

Flash

82559

100Base-T

Ethernet

#2

Glue Logic

I2C

EEPROM

ITP Test

Connector

SVG

RJ-45

FPGA

XTAL

EEPROM

64 Bit
Serial

ID

5V

Switching
Regulators

V Cores

Back End

Power

21154

PCI-

PCI

Bridge

&

Clocks

Drivers

CLK

Early Power

Hot Swap
Controller

CompactPCI J2

Connector

CompactPCI J1

Connector

3.8

Installing the Board

The cPCI-MXS64GX is not only a matter of computation power. The boards also provide a
high capability to interface with peripherals through three integrated chips:

" Host-to-PCI bridge for. 443GX from Intel: interface with the processor (host),

system memory, video controller, and Primary PCI bus (3.3V / 33MHz).

" PCI-to-PCI bridge - 21154 from Intel: manage the PCI bus signals on J1 and J2

CPCI connectors. When used with a CompactPCI backplane drives 7 CPCI slots.

" PCI-to-ISA bridge - 82371AB PIIX4 from Intel: interface the ISA bus to the

Primary PCI bus.

3.2.2. Mobile Pentium® II / III processor

The cPCI-MXS64GX system board supports the Intel’s Low Power 500 and 700MHz
Pentium III processor (Higher clock speeds will be available when Intel will release the
corresponding parts).

It consists of a Pentium
(on-die, full CPU speed, ECC capable) and a 64-bit high performance 100MHz front side
bus

The processor interfaces to the 440GX AGPset through the 64-bit low power GTL + data
bus interface.

®

III processor core with an integrated second level cache of 256KB

3.2.3. North Bridge Chipset

This chipset consist of 443GX AGPset, 64/72-bit SDRAM data interface with ECC
support, Low Power GTL Bus, five PCI arbitration channels, PCI bus rev. 2.1, Accelerated
Graphics Port Interface (AGP). The bus is optimized for 100MHz operation.

3.2.4. 21154 PCI-to-PCI Bridge

The 21154 is configure as a 32/64-bit 33MHz PCI-to-PCI bridge that allows the board to
support up to 7 CPCI slot on its secondary PCI bus through a passive backplane. The
bridge is fully compliant with the PCI Local Bus Specification, Rev. 2.1. It provides full
support for delayed transactions, which enables the buffering of memory read, I/O and
configuration transactions. The 21154 have separate posted write, read data and delayed
transaction queues with a high buffering capability.

In addition, it supports buffering of simultaneous multiple posted writes and delayed
transactions in both directions.

3.9

cPCI-MXS64GX Technical Reference Manual

The PCI-to-PCI bridge allows the Primary and Secondary PCI buses to operate
concurrently. This means that a master and a target on the same PCI bus can communicate
while the other PCI bus is busy. This traffic isolation may increase system performance in
applications where system resources are highly used.

3.2.5. 82371AB PCI-to-ISA Bridge / IDE Xcelerator (PIIX4)

The PCI-to-ISA bridge is configured to support signals to directly drive IDE interfaces,
USB ports, extra communication ports (Serial Ports 3 and 4), and standard Serial Ports (1
and 2), floppy disk drives, mouse and keyboard through a super I/O controller
(FDC37C672).

3.10

3.2.6. Onboard Connectors and Headers

Installing the Board

Description

CompactPCI Bus J1/J2

Connect

or

Comments

J1- CPCI bus signals and power.
J2 – Additional system slot signals.

CompactPCI I/O J3 Serial Ports 3 and 4, Ethernet 1, power.

Supports PS/2 mouse, serial ports 1 and 2, first IDE

CompactPCI I/O J4/J5

channel, parallel port, keyboard, speaker, floppy
disk, reset, USB, SMBus, and power signals.

DIMM Sockets J6, J7, J8

Processor Socket J9

Supports 168-pin 64/72-bit DIMMs, up to 1.5GB of
RAM.

MXS64GX : Mobile Pentium II / III connector

VGA J12 Supports standard 15-pin DSUB female connector.

Serial Port 1 J13

Kontron’s

Mezzanine

J14, J19

Ethernet 1, 2 J16/J15

Keyboard/Mouse J17

CompactFlash J18

Storage Mezzanine J19

PMC J20, J21

Supports standard 9-pin DSUB male connector.

This connector handles PCI bus signals to the mezzanine.

RJ-45 connectors with built-in activity and link
indicators.

Mouse and keyboard signals are combined on a
standard 6-pin DSUB female connector.

This connector is dedicated to the Kontron’s
CompactFlash module to support CompactFlash disk.

This connector is implemented to support floppy drive
and hard disk signals.

The PCI Mezzanine Card (PMC) connectors support one
standard PMC device .

Battery BT1 CMOS backup battery connector.

3.11

cPCI-MXS64GX Technical Reference Manual

3.2.7. Front Plate Connectors and Indicators

Name Description Comments

J12 Video Connector Standard 15-pin DSUB

S1 Reset Button Use a small tool to press the

DS1
DS2

J13 Com Port 1 Standard 9-pin DSUB male

J16, J15 Ethernet 1 and 2 RJ-45 connectors with built-

J17 Keyboard and

IDE/SCSI LEDs
HOT SWAP

Mouse

female connector

button and proceed to a
hardware reset of the board
Indicates an activity on
IDE/SCSI devices
Indicate a board failure/ready
to swap

connector

in activity and link indicators
To connect a keyboard
and/or a mouse through this
connector, you need a Y
shaped splitter cable
(Kontron part number 150-

381)

6-pin Mini-Din, fema le

6-pin Mini-Din, male

Keyboard

Mouse

The front plate supports a PMC cutout and a cap that also act as an
EMI shield when there are no PMC device installed.

3.12

3.2.8. FACEPLATE OPTIONS

Installing the Board

1

15

1

6

9

5

4

6

2

1

5

3

4HP

Front Access

1

4HP

Rear Access

1

15

1

6

9

5

426

1

35

8HP

Front Access

1

15

1

6

9

5

426

1

35

8HP

Front Access

with Floppy

8HP

Rear Access

8HP

Rear Access

with Floppy

3.13

cPCI-MXS64GX Technical Reference Manual

3.2.9. CompactPCI Connectors

" CPCI J5 Connector

Supports PS/2 mouse, serial ports 1 and 3, primary IDE channel,
parallel port, keyboard, speaker, floppy disk, reset, USB, SMBus
and power signals.

" CPCI J4 Connector

Supports Ethernet1, secondary IDE channel, SCSI, VGA, and
power signals.

" CPCI J3 Connector

Supports serial ports 3, 4 & Infrared, V-Port, Ethernet1, and
power signals.

" CPCI J2 Connector (P2 on the cPCI-MXS64GX)

Supports additional system slot signals, PCI 64-Bit extension,
and power.

" CPCI J1 Connector (P1 on the cPCI-MXS64GX)

Supports CPCI bus signals, and power.

3.14

Installing the Board

3.3. CUSTOMIZING THE BOARD

3.3.1. Processor and Fan

cPCI-MXS64GX

Your board will be installed with the Mobile Pentium III processor, Low Power 500 or

700MHz and its adequate cooling system.
Since CPUs are very sensitive components, particular attention should be given while

installing a processor on the board. Improper installation may damage the board and/or the
CPU.

CAUTION

Since CPUs are very sensitive components, particular attention should be
given while installing a processor on the board. Improper installation may
damage the board and/or the CPU

Before installing a processor on your board, you must contact our
technical support for the installation procedure

3.15

cPCI-MXS64GX Technical Reference Manual

3.3.2. Backup Battery

An onboard 3.6V lithium battery is provided to backup BIOS setup values and the real time
lock (RTC).

When replacing, the battery must be connected as follows:

3.6V

Lithium Battery

Positive Pin

(Center)

Negative Pin

(outer)

Onboard

Battery Connector

Negative
Contact

Positive
Contract

! WARNING

Danger of explosion if battery is incorrectly replaced

Replace only with the same or equivalent type recommended by the
manufacturer. Dispose of used batteries according to the manufacturer's
instructions. When you receive a board, remove the onboard battery
jumper to enable the battery (See section 3 for jumper settings)

3.16

Installing the Board

3.3.3. Memory

3.3.3.1. SDRAM System Memory

The cPCI-MXS64GX supports three 168-pin DIMM (Dual In-Line Memory Module)
sockets for memory configuration from 32MB to 1.5GB of Synchronous DRAM.

The memory characteristics must conform to the following:

" 1.15 inch height, 168-pin DIMM.
" Standard 3.3V only.
" 64-bit and 72-bit modules, single-sided or double-sided.
" Unbuffered 100MHz (SDRAM).
" Serial Presence Detect (SPD) EEPROM.
" Errors Checking and Correction (ECC) capabilities or parity bit with 72-bit

modules.

" Compliant with Intel’s PC SDRAM Unbuffered DIMM Specification (100MHz)

Rev. 1.0.

At least 32MB of memory must be installed on the board for proper operation. Modules
can be installed in any socket and order. The total system memory is equal to the sum of
the memory module size installed in the three DIMM sockets.

✎ NOTE

When populating with more than one memory module, each socket must be
installed with the same memory type (64/72-bit), however the capacity of
each module may be different from the other.

3.17

cPCI-MXS64GX Technical Reference Manual

The recommended DIMM devices are listed in the table below.

Vendor’s part number DIMM’s description Vendor’s Name

CTK32M/P100S ECC SDRAM 32MB 4M*72 PC100 1.15"HT CENTON
4X72CQ2X8S4E ECC SDRAM 32MB 4M*72 PC100 1.15"HT ROCKY MOUNTAIN RAM
DIM-200472V2S08G1 ECC SDRAM 32MB 4M*72 PC100 1.15"HT SHIKATRONICS
DIM200472V5S08G ECC SDRAM 32MB 4M*72 PC100 1.15"HT SHIKATRONICS
CTK64M/P100S ECC SDRAM 64MB 8M*72 PC100 1.15"HT CENTON
8X72PC8X8S4E ECC SDRAM 64MB 8M*72 PC100 1.15"HT ROCKY MOUNTAIN RAM
DIM200872V4S8G1 ECC SDRAM 64MB 8M*72 PC100 1.15"HT SHIKATRONICS
CTK128M/P100S ECC SDRAM 128MB 16M* 72 PC1 00 1.1 5" CENTON
DIM-201672V4S08G1 ECC SDRAM 128MB 16M*72 PC100 1.15" SHIKATRONICS
VM374S1723-GL ECC SDR A M 128 MB 16 M* 72 PC1 00 1.1 5" VIRTIUM
CFHKQARV4VU420G ECC SDRAM 256MB 32M*72 PC100 1.15" CENTON
CTK256M/P100S ECC SDRAM 256MB 32M* 72 PC1 00 1.1 5" CENTON
DIM203272VDS08 GS ECC SDRAM 256MB 32M*72 PC100 1.1 5" SHIKATRONIC S
VM374S3323-GL ECC SDR A M 256 MB 32 M* 72 PC1 00 1.1 5" VIRTIUM

3.3.3.2. DIMM Installation

✎ NOTE

If a Mezzanine card is insta lled, it must be re moved before i nstallation of
DIMMs.

To install the DIMMs in the sockets, proceed as follows:

1. With the board flat on the table, turn it so that the front plate is facing you.

2. Hold the module vertically so that the bottom connecto r key is at right. Install the

DIMM straight down into the DI MM socket. The socket’s keys will ensure a correct
mating.

3. Press firmly on the top edge of the memory module to engage it into the socket. The

module is fully inserted when the retaining clips snap into notches located at each

end of the module.
If necessary, work your way by inserting the other modules, one by one.
To remove the DIMMs from the sockets, pull simultaneously on the retaining clips located on

each side of the socket. Once the module has snapped out, pull gently on it.

3.18

Installing the Board

3.3.4. Supervision Features

The cPCI-MXS64GX provides a set of programmable I/O registers to setup the Intel PIIX4
(I/O addresses 4030h to 4037h) and the XILINX FPGA (I/O addresses programmable at
190h-193h, 290h-293h or 390h-393h using the AWARD Chipset Features Setup).

Only register bits needed to program the power fail detection and watchdog functions are
described below.

3.3.4.1. Power Fail Monitoring

The power failure detector status can be readout from one bit of the system register located
at the address 4031h (See table below). The detection conforms to the following conditions
(* = active low signal):

It always monitors the +5V power supply. When it drops below 4.65V (typical), the system
is reset.

It can monitor the onboard battery. When the battery is in a low condition (below 2.9V
typical), the PFO* (power fail output) signal goes low. The status of the PFO* signal can
be read at I/O address 4031h, bit 1 (0 = failed, 1 = good). An interrupt hand ler can then
service the interrupt. If you choose not to generate an NMI, you can use an algorithm to
detect a low battery condition and respond accordingly.

Register Bit # Function Software Programming

4030h
4031h

4032h

4034h
4035h

4036h
4037h

0-7 Reserved Reserved

0, 2-7 Reserved Reserved

1 P ower Fail Out put (Internal/External

Battery or External Power Source)

0, 2-7 Reserved Reserved

1 Watchdog Stage 1 Status Read: 0 = Timed out, 1 = Normal

0-7 Reserved Reserved

0-1, 4-7 Reserved Reserved

2 Watchdog enable Write: 1 = Disable, 0 = Enable
3 Watchdog reset Write: 1-0-1 (toggle) to activate

0-7 Reserved Reserved
0-7 Reserved Reserved

Read: 0 = Failed, 1 = Good

the watchdog (when enabled)

For more information, contact the Technical Support department

3.19

cPCI-MXS64GX Technical Reference Manual

3.3.4.2. Watchdog

The function of a watchdog is to reset the CPU board if the processor is not able to
generate a trigger for longer than the watchd og time-out period. This feature is useful in
embedded systems where human supervision is not required or impossible.

The cPCI-MXS64GX provides a two-stage digital watchdog with software programmable
time-out period.

Following a reset of any source, the watchdog is disabled. The watchdog can be enabled by
software.

Dual Stage Watchdog

Enabling the Programmable Watchdog

To enable the programmable watchdog, first unlock the enable bit by clearing the lock bit
in register 0x92h (bit 2), then set th4e bit WDEN (bit 7) in register n92h and relock it by
setting the lock bit in register 0x92 (bit 2). The following is an example in C language :

#define TekReg 0x190 // define base address (0x190, 0x290 or 0x390

void ArmWatchdog(void)

{

outp{TekReg+2, inp(TekReg+2) & 0xFB); // unlock watchdog enable bit
outp{TekReg+6, inp(TekReg+6) | 0xF0); // enable and trigger at max time-out
outp{TekReg+2, inp(TekReg+2) | 0x04); // lock watchdog enable bit

}

Triggering the Programmable Watchdog

To trigger the programmable watchdog, the processor wr ites to register n92h (n=1, 2 or 3).
The action of writing to the register is the trigger and the value written to the register tells
the watchdog the current time-out to use (see register n92h description). For a fixed time­out, the software simply writes a constant in register x92h.

3.20

A variable refresh is possible as shown below:

Write to Register n96h with WDS[2,0] having the value below

000

16ms

8.6ms

001 000

WatchDog internal counter valu e

Installing the Board

000

NMI

8.6 ms

RESET

The programmable watchdog can be viewed as a decrementing counter that is initialized by
a write to register n92h. The processor must initialize the counter to prevent it from
reaching count 0 (timeout).

The following C language procedure can be used t o trigger the p rogrammable watchdog.

#define TekReg 0x190 // define base address (0x190, 0x290 or 0x390)
void TrigWatchdog(timeout) // select timeout at runtime: 0x80 = 0.016s,

// 0x90 = 0.065s, 0xA0 = 0.261s, ...

{

outp(TekReg+6,(in p(TekReg+ 6) & 0x0F) | (timeout & 0xF0));

}

3.21

cPCI-MXS64GX Technical Reference Manual

TIME-OUT

The programmable watchdog has two stages: the first stage has a variable time-out while
the second stage has a fixed one.

The first stage time-out is chosen at runtime from eight preset values (see table below). The
first stage time-out generates an NMI interrupt (if enabled in register n92h). An appropriate
NMI handler must be written, otherwise this will be treated as a parity error by the default
BIOS NMI handler; see register n92h description fo r a suggestion on how to do this.

The second stage times-out 8.6ms ±10% (depending on the temp erature) after the first one
and generates a master reset.

WDS[2,0] NMI Timeout RESET Timeout

000 0.016s 0.016s + 1ms
001 0.065s 0.065s + 1ms
010 0.261s 0.261s + 1ms
011 1.044s 1.044s + 1ms
100 4.174s 4.174s + 1ms
101 16.69s 16.69s + 1ms
110 66.79s 66.79s + 1ms
111 267.1s 267.1s + 1ms

A reset from the programmable watchdog is latched for reset source identification; see
reset history description in Section 4.3.

3.3.4.3. Thermal Management

The thermal management is built around two digital temperature sensors and a thermal
watchdog. Both devices can be programmed to set their outputs when the temperature of
the processor or the ambient temperature exceeds a programmable high limit, and reset its
output when the temperature is under a programmable low limit. A special routine is
implemented to throttle the CPU clock until the temperature falls belo w the programmed
low limit.

Please refer to Section 4.1.10 CPU/Board Features Setup– Thermal Management Options
for a complete information on thermal management setups.

3.22

Installing the Board

3.4. BUILDING A CPCI SYSTEM

When building a CompactPCI system, a minimum requirement consists in: a chassis, a
CompactPCI backplane, a storage module, a power supply unit, and a ventilation system.

The main AC power is drawn to the chassis compone nts through an IEC power plug with a
2-stage filter, fuse holder and power switch. All power features are provided at the rear of
the chassis.

The chassis may be used either as a desktop system or a rack-mount bay.

Chassis Cover

Single Board Computer
(System)

Fan Tray

Storage

Power Supply

CxP0816

3.23

cPCI-MXS64GX Technical Reference Manual

3.4.1. Backplane

An entry-level backplane is provided by Kontron. It is referred to as cBP-08R. It features 8
CPCI slots (one PCI I/O segment), and includes J3-J5 I/O connectors on all slots.

A 16-CPCI-slot backplane (cBP-16R) is also available from Kontron. It supports two PCI
I/O segment: one is driven directly by the system processor while the other is managed
through a PCI-to-PCI bridge implemented on the cMCB-2RC mezzanine card
(Storage/PCI-to-PCI mezzanine).

All Kontron’s CompactPCI backplanes feature pass-through connectors (J3-J5) to support
Rear Panel I/O connections.

! IMPORTANT

J1 and J2 are de-facto industry standard as defined by PICMG.

J3, J4 and J5 are user-defined connectors and will vary from various
manufacturers. Contact our Technical Support to verify pinout
compatibility with other chassis backplane vendors.

3.24

Installing the Board

3.4.2. Rear-Panel I/O

This feature is intended to issue the I/O capabilities of the system processor to the rear of
the enclosure using a Rear I/O Transition module (cTM80-STD2S).

The Rear I/O Transition module gathers all the I/O signals of the CPU board and makes
them easily accessible through standard headers and connectors located at the rear of
enclosure. The cTM80-STD Transition Module is illustrated below.

Type ABType A

J5

J4

Type AB

J3

3.25

cPCI-MXS64GX Technical Reference Manual

1Rev.

3.26

Installing the Board

3.4.3. Storage Devices

A mezzanine card (cMC or cMCB-2RC) attaches directly to the system processor. 6U form
factor storage modules are supported when using the cBP-08R backplane.

There are two ways of supplying data storage with Kontron’s product line.

1. cMC : Mezzanine Card that is installed directly onto the processor board.

2. cSM-DVD : 6U form factor storage module that is front loaded into the

CxP0816 chassis.

3.4.4. Power Supply

6U power supply modules featuring load sharing redundant mode and hot-swap capabilities
allow on-site replacements of defective module while the system remains powered.

A standard ATX power supply unit is also supported.

3.4.5. Fan Tray

The ventilation unit of the enclosure conforms to the global require ment of the system in
fully loaded configuration.

3.4.6. Installing the Board into a Bay

The cPCI-MXS6 4GX is mechan ical Eurocard form factor boards. It takes advantages of the
IEEE1101.10 specifications that ensure a mechanical interchange capability between
different plug-in elements in sub-rack s.

Due to the high-density pinout of the Hard Metric connector, some precautions must be taken
when connecting or disconnecting a board to/from a backplane:

1. Rail guides must be installed on the enclosure to slide the board to the backplane.

2. Do not use force if there is any mechanical resistance while inserting the board.

3. Screw the front plate to the enclosure to firmly attach the board to its enclosure.

4. Use the extractor handles to disconnect and extract the board from its enclosure.

3.27

cPCI-MXS64GX Technical Reference Manual

3.4.7. Connector Keying

CompactPCI connector support guide lugs to ensure a correct polarized mating. A proper
mating is enhanced by the use of color coded keys for 3.3V and 5V operation.

Color coded keys prevent inadvertent installation of a 5V peripheral board in a 3.3V slot.
The cPCI-MXS64GX is universal. It does not support coding key. The PCI bus does not
require to be keyed. Backplane connectors must always be keyed according to the signaling
(VIO) level.

Coding Key Colors are defined as follows:

Signaling Voltage Key Color

3.3V Cadmium Yellow
5V Brilliant Blue

Universal board (5V and 3.3V) none

-48V Red

3.28

Installing the Board

3.4.8. Bus Mastering

The cPCI-MXS64GX provides seven pairs of REQ/GNT (0-6) arbitration signals through
the Secondary PCI bus. T his means the board is capable of driving up to seven CPCI slots
with PCI Bus Master capabilities.

3.4.9. Connection

To install the cPCI-MXS64GX board into a bay, proceed as follows:

1. Locate the 6U system slot

2. Remove the front plate of the slot where you intend to insert the cPCI-MXS64GX.

3. Ensure the module is properly aligned with the guide-rails a nd slide it gentl y until

it touches the backplane connector

! WARNING

1. Some mechanical parts of the guide-rail are fragile (shield contacts

and clips). Do not use force to insert and connect a CompactPCI
module.

2. If there is any mechanical resistance while you insert a module, first

ensure there is no mechanical obstacle and check for the alignment
of all parts.

5. To engage the board’s connectors into the backplane connector, press

simultaneously on the front plate.

6. Fasten the module using the fellow-plate fixing screw to secure the module to the

system chassis.

To remove the module from the chassis, proceed as follows:

1. Remove the front plate fixing screws.

2. Press the handle to act as a lever to disengage the CompactPCI connector from the

backplane.

3. Pull on the handle and gently remove the board.

3.29

cPCI-MXS64GX Technical Reference Manual

3.5. CPCI I/O SIGNALS

This section describes integrated feature signals available on rear panel CPCI I/O
connectors (J3, J4, and J5)

3.5.1. J3 Signal Specification

3.5.1.1. Ethernet LEDS

Signal Pin Assignation Description

SPEEDLED 0-1 A6, E6 Speed LED signal
LINKLED 0-1 B6, D6 Link integrity LED signal
ACTLED 0-1 C6, A7 Transm it / receive act i vi ty LED signal

3.5.1.2. Ethernet 1

Signal Pin Assignation Description

ETX+1 A9 Ethernet High Transmit Data line
ETX-1 B9 Ethernet Low Transmit Data line
ERX+1 C9 Ethernet High Receive Data line
ERX-1 D9 Ethernet Low Receive Data line

3.5.1.3. Serial Port 3

Signal Pin Assignation Description

/DCD3 A13 Data Carrier Detect
RXD3 C13 Receive Data
/DSR3 D13 Data Set Ready
TXD3 E13 Transmit Data
/RTS3 A14 Ready To Send
/CTS3 B14 Clear To Send
/RI3 C14 Ring Indicator
/DTR3 E14 Data Terminal Ready

3.30

3.5.1.4. Serial Port 4

Signal Pin Assignation Description

/DCD4 A11 Data Carrier Detect
RXD47 C11 Receive Data
/DSR4 D11 Data Set Ready
TXD4 E11 Transmit Data
/RTS4 A12 Ready To Send
/CTS4 B12 Clear To Send
/RI4 C12 Ring Indicator
/DTR4 E12 Data Terminal Ready

3.5.1.5. IDE LED Signals.

Signal Pin Assignation Description

/S-IDE-ACT B18 Secondary IDE activity
/P-IDE-ACT C18 Primary IDE activity

3.5.1.6. IR Serial Port 2

Signal Pin Assignation Description

Serial Port 2

IRRX

Serial Port 2

IRTX

D18 IR receive data line (Serial Port 2)
E18 IR transmit data line (Serial Port 2)

Installing the Board

3.5.1.7. Hot Swap HA (High Availability) signals

Signal Pin Assignation Description

BDSEL S2-S5 A 15, B15, E15, D19 B oard Select, one of the shortest pins (the last to
HEALTHY S2-S 4 A16, B16, D17 Used to acknowledge the health of the board

PCIRST S2-S4 A17, C15, E17 Used to indicate the CompactPCI Bus reset si gnal

mate and the first to break contact).

3.5.1.8. Miscellaneous Signals

Signal Pin Assignation Description

/PWRBT A19 ACPI Reserved
EXT-SMI B19 System Management Interrupt Input
PX4-NMI C19 Non Maskable Interrupt Input
PWROK-33 E19 High when 3.3V supply is valid on the board

3.31

cPCI-MXS64GX Technical Reference Manual

3.5.2. J4 Signal Specification

3.5.2.1. Power Management

Signal Pin Assignation Description

I2C-CLK A1 I2C clock signal
I2C-DATA B1 I2C data signal
LID C1 Reserved

/EXT-FAN0-FAIL D1 Enclosure fan 0 fail
/EXT-FAN1-FAIL E1 Enclosure fan 1 fail

/SM-BYPASS A2 Reserved

3.5.2.2. SCSI Interface

Signal Pin Assignation Description

SD 0-15 E7, D7, C7, B7, A7, E6,

D6, C6, E2, D2, C2, B2,
E8, D8, C8, B8

/IO A3 In/Out – Indicates the In directi on when ass erted and
/SREQ B3 Request – A target will assert REQ to indicate a byte is
/CD C3 Command/Data – Indicates Comm and or message

/SSEL D3 SCSI Select – The line is driven after a successful

/SMSG E3 SCSI Message - Indicates a Message phase when

/RST A4 Reset – Signal is interpreted as a hard reset and will
/ACK B4 Acknowledge – Indic ate a byte is ready for or was
/BSY C4 Busy – Handshake signal used during arbitration.

/SATN E4 Attention – This line is activated when a special
/WIDEPS B5 Wide Present – When Low, indicates that a wide (16­TERMPWR C5, D5 Termination Power.

/SDPH, /SDPL A8, B6 SCSI High/Low Parity – Provide odd parity for data

SCSI Data – The SCSI data lines drive the ID during
arbitration and selection, and command and data
information as well as status and messages.

the Out direction when not asserted.
ready or is needed by the Target.
phase when asserted, and Data phase when not

asserted.
arbitration to select as an initiator or reselect as a

target and otherwise it is received.
asserted, and Command or Data phase when not

asserted.
clear all commands pending on the SCSI bus.
received from the Target.

condition occurs.
bit) cable is present.

lines.

3.32

Installing the Board

3.5.2.3. Video Interface

Signal Pin Assignation Description

VSDA D9 Video serial data line (video I2C)
VSCL A10 Video serial clock line (video I2C)
HSYNC B10 Horizontal sync line
VSYNC C10 Vertical sync line
RED D10 Analog Red video signal
GREEN E10 A nal og Green vi deo si gnal
BLUE A11 Analog Blue video signal

3.5.2.4. Ethernet 1 Interface

Signal Pin Assignation Description

ETX+0 A16 Ethernet 1 High Transmit Data line
ETX-0 B16 Ethernet 1 Low Transmit Data line
ERX+0 C16 Ethernet 1 High Receive Data line
ERX-0 D16 Ethernet 1 Low Receive Data line

3.5.2.5. Hot Swap HA (High Availability) signals

Signal Pin Assignation Description

BDSEL S6-S8
HEALTHY S5-S 8 C9, D15, C22, C25 Used to acknowledge the health of the board

PCIRST S5-S8 E9, E15, A25, D25 Used to indicate the CompactPCI Bus reset signal

C11, E20, B25 Board Select, one of the shortest pins (the last to mate

and the first to break contact).

3.33

cPCI-MXS64GX Technical Reference Manual

3.5.2.6. IDE 1 Interface

Signal Pin Assignation Description

/BRSTDRV A17
IDE1_ 0-15 B20, E19, C19, A19,

D18, B18, E17, C17,
D17, A18, C18, E18,
B19, D19, A20, C20

SDREQ A21 Sec. Disk DMA Request - This signal is directly driven

/SDIOW C21 Sec. Disk I/O Write – In normal IDE mode, this is the

/SDIOR E21 Sec. Disk I/O Read – In normal IDE mode, this is the

SIORDY B22 S ec. I/O Channel Ready – In normal mode, this input

/SDDACK D22 Sec. DMA Acknowledge – This signal directly dri ves

IRQ15 E22
/IOCS16 A23
SDA 0-2 D23, B23, E23 Sec. Disk Address – These signals indicates which

/SCS1, /SCS3 A24, B24 Secondary Chip Select - For ATA control register.
SEC-PD1 C24
/FAL1 E24

Sec. Disk Data – These signals are used to transfer
data to or from the IDE device.

from the IDE device DMARQ signal. It is asserted by
the IDE device to request a data transfer.

command to the IDE device that it may latch data from
SDD lines.

command to the IDE device that it may drive data on
SDD lines.

signal is driven directly by the corresponding IDE
device IORDY signal.

the IDE device /DMACK signal. It is asserted to
indicate to IDE DMA slave devices that a given data
transfer cycle is a DMA data transfer cycle.

byte in either the ATA command block or control block
is being addressed.

IDE 1 (IDE 1) is assigned to the Secondary IDE logical interface. It s upports directly two
IDE devices configured as master and slave devices.

3.34

Installing the Board

3.5.3. J5 Signal Specification

3.5.3.1. IDE 0 Interface

Signal Pin Assignation Description

/BRSTDRV A1
/BRSTDRV B1
PDD 0-15 B4, E3, C3, A3, D2, B2,

E1, C1, D1, A2, C2, E2,
B3, D3, A4, D4

PDREQ A5 Prim. Disk DMA Request - This signal is directly driven

/PDIOW C5 Prim. Disk I/O Write – In normal IDE mode, this is the

/PDIOR E5 Prim. Disk I/O Read – In normal IDE mode, this is the

PIORDY B5 Prim. I/O Channel Ready – In normal mode, this input

/PDDACK D5 Prim. DMA Acknowledge – This signal direct l y drives

IRQ14 E4 IRQ14 line
/IOCS16 A6 IOCS16 line
PDA 0-2 D6, C7, E6 Prim. Disk Address – These signals indicates which

/PCS1, /PCS3 A7, B7
PRI-PD1 D7
/PDIAG C6

Prim. Disk Data – These signals are used to transfer
data to or from the IDE device.

from the IDE device DMARQ signal. It is asserted by
the IDE device to request a data transfer.

command to the IDE device that it may latch data from
SDD lines.

command to the IDE device that it may drive data on
SDD lines.

signal is driven directly by the corresponding IDE
device IORDY signal.

the IDE device /DMACK signal. It is asserted to
indicate to IDE DMA slave devices that a given data
transfer cycle is a DMA data transfer cycle.

byte in either the ATA command block or control block
is being addressed.

3.5.3.2. USB 0 and 1 Interfaces

Signal Pin Assignation Description

USBD1-0 (+/-) B18, C18, D19, E19 USB Data – Differential data path for USB 0 and 1 ports
USBG 1-0 B19, D18 USB Ground – Differential ground referenc e for USB 0

USBV 1-0 C19, E18 USB Voltage – Differential power level for USB 0 and 1

and 1 ports
ports

3.35

cPCI-MXS64GX Technical Reference Manual

3.5.3.3. Floppy Disk Interface

Signal Pin Assignation Description

/FD-DRVEN 0-1 E7, A8 Drive 0-1 density select
/FD-INDEX B8 Index
/FD-MTR 0-1 C8, A9 Motor 0-1 enable
/FD-DS 0-1 E8, D8 Drive 0-1 select
/FD-DIR B9 Direction
/FD-STEP C9 Step pulse
/FD-WDATA D9 Write disk data
/FD-WGATE E9 Write gate
/FD-TRK0 A10 Track 0
/FD-WRTPRT B10 Write protected
/FD-RDATA C10 Read disk data
/FD-HDSEL D10 Head s el ect
/FD-DSKCHG E10 Disk change

3.5.3.4. Serial Port 2

Signal Pin Assignation Description

/JDCD2 A11 Data Carrier Detect
JRXD2 C11 Receive Data
/JDSR2 D11 Data Set Ready
JTXD2 E11 Transmit Data
/JRTS2 A12 Ready To Send
/JCTS2 B12 Cl ear To S end
/JRI2 C12 Ring Indicator
/JDTR2 E12 Data Terminal Ready

3.5.3.5. Serial Port 1

Signal Pin Assignation Description

/JDCD1 A13 Data Carrier Detect
JRXD1 C13 Receive Data
/JDSR1 D13 Data Set Ready
JTXD1 E13 Transmit Data
/JRTS1 A14 Ready To Send
/JCTS1 B14 Cl ear To S end
/JRI1 C14 Ring Indicator
/JDTR1 E14 Data Terminal Ready

3.36

3.5.3.6. Parallel Port

Signal Pin Assignation Description

SLCT A15 Printer select
PE B15 Paper end
BUSY C15 Busy signal
/ACK D15 Acknowledge handshake
PD 0-7 E17, C17, A17, D16,

C16, B16, A16, E15
/SLCTIN E16 Printer select
ALF A18 Auto line feed
/INIT B17 Initiate output
/ERR D17 Error at printer
/STB A19 Strobe signal

Parallel port data bus

3.5.3.7. Miscellaneous Signals

Signal Pin Assignation Description

/SMBDATA B20 Onboard SMbus data
/SMBALERT C20 Onboard SMbus Alert (CPU overheati ng)
SMBCLK E20 Onboard SMbus Clock
/PBRST A22 Reset
/DIAG-OC C22 Reserved
SPK-OUT E22 Speaker signal

Installing the Board

3.5.3.8. Keyboard Interface

Signal Pin Assignation Description

KDATA A21 K eyboard data
KCLK B21 Keyboard clock
VCC-KBD C21 Keyboard power

3.5.3.9. Mouse Interface

Signal Pin Assignation Description

MDATA D21 Mouse data
MCLK E21 Mouse clock

3.37

4. SOFTWARE SETUPS

P

A

R

T

1. BIOS SETUP PROGRAM

2. VT100 MODE

4

cPCI-MXS64GX Technical Reference Manual

4.1. BIOS SETUP PROGRAM

All relevant information for operating the board and connected peripherals is stored in the
CMOS memory. A battery holds this information when the board is powered off, and the
BIOS Setup program is required to make changes to the setup.

✎ NOTES

Make sure you setup the BIOS Setup software prior to installing
your operat ing system and your drivers.

For systems that need the BIOS to first attempt to boot from LAN, follow
these steps:

1. Set the Boot From LAN First option to “Enabled” in the BIOS
Setup’s BIOS Features Setup

2. Follow the complete procedure in the Boot From LAN utility (this

utility is located on the driver’s CDROM).

4.1.1 Accessing the BIOS setup program

The system BIOS (Basic Input Output System) provides an interface between the operating
system and the hardware of the cPCI-MXS64GX system processor. The CPCI-MXS64GX
and uses the AWARD Setup program, a setup utility in flash memory that is accessed by
pressing the DELETE key at the appropriate time during system boot. This utility is used to
set configuration data in CMOS RAM.

CAUTION
Before modifying CMOS setup parameters, ensure that the W4 battery
selection jumper is installed to enable the CMOS battery back up (please refer
to Section 3.1).

To run the AWARD Setup program incorporated in the ROM BIOS:
Turn on or reboot the system.

Hit the DELETE key when the message - "Press DEL To Enter SETUP" appears near the
bottom of the screen.

4.1

cPCI-MXS64GX Technical Reference Manual

The main menu of the AWARD BIOS CMOS Setup Utility appears on the screen.

KONTRON COMMUNICATIONS INC. T1023 BIOS VERSION 2.0

AWARD SOFTWARE, INC. (2A69TU00)

STANDARD CMOS SETUP
BIOS FEATURES SETUP
CHIPSET FEATURES SETUP
POWER MANAGEMENT SETUP
THERMAL MANAGEMENT SETUP
PNP/PCI CONFIGURATION
INTEGRATED PERIPHERALS

Esc : Quit
F10 : Save & Exit Setup

Time, Date, Hard Disk Type . . .

CMOS SETUP UTILITY

LOAD BIOS DEFAULTS
LOAD SETUP DEFAULTS
SUPERVISOR PASSWORD
USER PASSWORD
IDE HDD AUTO DETECTION
SAVE & EXIT SETUP
EXIT WITHOUT SAVING

↑↓→← : Select Item
(Shift)F2 : Change Color

Whenever you are not sure about a certain setting, you may refer to the list of default
values. The list of defaults is provided in the event that a value has been changed and one
wishes to set this option to its original val ue. Loading the BIOS or SETUP defaults will
affect all the options in this screen (or all parameters if defaults are loaded fro m the Main
Menu) and will reset options previously altered.

The BIOS Default settings consi st of the safest set of parameters. Use them if the system is
behaving erratically. They should always work but do not provide optimal system
performance.

The SETUP Default values provide optimum performance settings for all devices and
system features.

CAUTION

These parameters have been provided to give control over the system.
However, the values for these options should be changed only if the user has a
full understanding of the timing relationships inv olved.

4.2

Software Setu ps

4.1.2 Main Menu

The Main Menu includes the following categories:

Category Description

Standard CMOS Setup This Setup page includes all the items in a standard, AT-compatible BIOS (date, time,

BIOS Features Setup This Setup page includes all the items of AWARD’s special enhanced features.
Chipset Features Setup This Setup page includes all the items of the chipset’s special features.
Power Management Setu p This Setup pag e sets po wer con s er vatio n opti ons.
PnP/PCI Configuration This Setup page sets Plug and Play and PCI configuration options.
CPU/Board Features Setup This Setup page sets processor speed, thermal management and board monitoring

Integrated Peripherals I/O susbsystems that depend on the integrated peripherals controller in your system.
Load Bios Defaults

Load Setup Defaults

Supervisor/User Password
Setting

IDE HDD Auto Detection Forces the detection of the IDE hard disk drives parameters and puts them in the

Save & Exit After having modified the BIOS Setup, you can save the configuration in CMOS

Exit Without Saving This option is used to exit AWARD Setup without saving the configuration to CMOS

hard disk type, floppy disk type, video adapter type, memory…).

options.

The BIOS defaults are fail safe settings which co nsi st of the saf est set of par am et ers.
Use them if the system is behaving erratically. They should always work but do not
provide optimal system performance.

The Setup defaults are the optimal settings that provide the optimum performance for
all devices and system features. If the CMOS RAM is corrupte d, the Setup defaults

are loaded automatically.

Change, set or disable the password. It allows you to limit the access to the system
and the Setup, or only to the Setup.

Standard CMOS Setup page.

RAM and the Flash BIOS, by selecting this option.

RAM or Flash BIOS.

4.3

cPCI-MXS64GX Technical Reference Manual

4.1.3 Setups

The arrow ke ys (↑ ↓ → ←) are used to highlight items on the menu and the PAGEUP and
PAGEDOWN keys are used to change the entry values for the highlighted item. To enter in
a submenu, press the ENTER key. Also, you can press the F1 key to obtain help
information or the ESC key to close a menu or to quit the program.

Key Function

↑↑↑↑

↓↓↓↓
←←←←
→→→→

ESC

PAGEUP or +

PAGEDOWN or -

F5

F6

F7

F10

Moves to previous item.
Moves to next item.
Moves to the item a the left.
Moves to the item at the right.
When in the Main Menu: Quits program (Answer ‘Y’ to save changes into CMOS).

When in other screens: Exits and returns to the Main Menu.
Increases the numeric value or changes value.
Decreases the numeric value or changes value.
When in the Main Menu: Restores the previous setup values for all the BIOS parameters

(except Standard CMOS Setup) which were displayed when you entered the program.
When in BIOS Features Setup, Chipset Features Setup, Power Management Setup, PNP/PCI
Setup or Integrated Peripherals Setup: Restores the previous setup values for that setup
screen only.

When in the Main Menu: Loads the BIOS Defaults of all the BIOS parameters (except
Standard CMOS Setup). The BIOS Defaults are fail safe settings, which consists of the safest
set of parameters.
When in BIOS Features Setup, Chipset Features Setup, Power Management Setup, PNP/PCI
Setup or Integrated Peripherals Setup: Loads the BIOS Defaults for all the BIOS parameters
for that setup screen only.

When in the Main Menu: Loads the Setup Defaults for all the BIOS parameters (except
Standard CMOS Setup).
When in BIOS Features Setup, Chipset Features Setup, Power Management Setup, PNP/PCI
Setup or Integrated Peripherals Setup: Loads the Setup Defaults for the BIOS parameters for
that setup screen only. If the CMOS RAM is corrupted, the Setup defaults are loaded
automatically.

When in the Main Menu: Saves all the CMOS changes and exit.

4.4

4.1.4 Standard CMOS Setups

Function Description

Date/Time

Hard Disks

The current values for each category are displayed. Enter new values through the
keyboard.

Two IDE controllers are defined on the cPCI-MXS64GX board. The Pr imary and
Secondary contro l le rs can bot h ha ve two dis ks: Mas ter D isk or Sla ve Dis k.

Only three settings are available for the hard disk type: Auto, User and None. Type 1
to 46 are not predefined in the system: Use auto-detect or enter the parameters for
the type in the user -d efi ned .

Software Setu ps

Drive A / Drive B
Video
Halt on

Memory

Select the type of floppy disk installed for drive A and drive B.
This option specifies the basic type of display adapter card installed in the system.
This option specifies the type of errors that will stop the system during the BIOS

booting proce dur e . A mes sag e as ks th at y ou pre ss F1 to co nt i nue or pr es s th e
DELETE key to enter Setup. The settings are: All errors, No errors, All but keyboard,
All but disket te , and Al l bu t d isk/ key (de f aul t sett in g) .

This display-only option indicates the amount of Base, Extended and other types of
memory installed in the system.

4.1.5 Saving & Exiting Operations

Use one of the following options available from the Main Menu:

Function Description

Save & Exit After having modified the BIOS Setup, you can save the configuration in CMOS

Exit Without Saving This option is used to exit AWARD Setup without saving the configuration to CMOS

RAM and the Flash BIOS, by selecting this option.

RAM or Flash BIOS.

4.5

cPCI-MXS64GX Technical Reference Manual

4.1.6 BIOS Features Setup

Option

Virus Warning Dis. Dis. En. / Dis. When Enabled, you receive a warning message if a program

Quiet POST Dis. Di s. En./Dis. At the power on self-test (POST), only the AWARD logo and the

Quick Power On Self
Test

Full Screen Logo
Show

Boot from LAN First Dis. Dis. En./Dis. If Enabled, the BIOS will first attempt to boot from the LAN. The

Raid Card Boot First Dis. Dis. En./Dis.

Boot Sequence A,C,

Swap Floppy Drive Dis. Dis. En./Dis. Selecting Enabled assigns physical drive B to logical drive A, and

Boot Up Floppy Seek En. Dis. En./Dis. Whe n E n a b l e d , t h e B I O S t e s ts (seeks ) f l o p p y d r iv e s t o d e t e rmine

Drive A Boot Permit En. En. En./Dis. When Disabled, this option will not permit booting from Drive A.
Floppy Disk Access

Control

BIOS

Setup Defaults

Defaults

Dis. En. En./Dis. Select Enabled to reduce the amount of time required running the

Dis. Dis. En./Dis. When enabled, a full screen bitmap (.BMP) picture will appear

SCSI

R/W R/W

C,A,

SCSI

Possible
Settings

A,C,SCSI;

C,A,SCSI;
C,CDROM,A;
CDROM,C,A;

D,A,SCSI;

E,A,SCSI;

F,A,SCSI;

SCSI,A,C;

SCSI,C,A;

C only;

LS/ZIP,C.

R/W,

Read Only

Description

(specifically, a virus) attempts to write to the boot sector or the
partition table of the hard disk drive. You should then run an anti­virus program. Keep in mind that this feature protects only the
boot sector, not the entire hard drive.

Note: Many disk diagnostic programs and OS setups (e.g.,
Win95 setup), that access the boot sector table, can trigger
the virus warning message. If yo u plan to run such a
program, we recommend that you first disable the virus
warning.

“Press DEL to enter SETUP” message appears.

POST. A quick POST skips certain steps. We recommend that
you enable quick POST to save time, since most major OS do
their own tests

during the POST or you can have your logo being displayed
(contact the Technical Support, see appendix G).

complete procedure for this function is available on the “Boot from
LAN” utility diskette.

If Enabled, the BIOS will first attempt to boot from the RAID disk
card.

This option defines the searching order in the BIOS for the boot
device(s).

Note: The Boot from LAN First and Raid Card Boot First
options take precedence over this option.

physical drive A to logical drive B.

whether they have 40 or 80 tracks. Only 360KB floppy drives have 40
tracks; drives with 720KB, 1.2MB, and 1.44MB capacity all have 80
tracks. Because very few modern PCs have 40 track floppy drives, we
recommend that you set this field to “Disabled” to save time.

When Read Only, this option will not permit writing to the floppy
disk.

4.6

Software Setu ps

BIOS Features Setup (Continued)

BIOS

Option

Report No FDD For
Win 95

Hard Disk Write
Protect

HDD S.M.A.R.T.
Capability

Delay For HDD (Secs) 0 0 0-15 This number of seconds inserted prior to HDD initialization. 0 is

OS Select For DRAM
> 64MB

Gate A20 Option Norm. Fast Normal, Fast When Fast, enables fast switching of Gate A20 via the 440GX

Security Option Setup Setup Setup, Normal

Diskette Access For All All All, Supervisor When this option is set to Supervisor and the Security option to

Boot Up NumLock
Status

Typematic Rate
Setting

Typematic Rate
(Chars/s)

Typematic Delay
(msec)

Comport 1 1 1,2,3,4 Use this option to select which COM port will be used for VT100
Speed Auto Auto Auto, 2400,

Parity None None None, Odd,

Data 8 8 7, 8 Use this option to specify the number of data bits being used.
Stop 1 1 1, 2 Use this option to specify the number of stop bits being used.

Defaults

Setup

Defaults

No No Yes, No

Dis. Dis. En./Dis. When Enabled, this option will not permit writing to the hard disk.

Dis. En. En./Dis. When Enabled, the Self-Monitoring, Analysis, and Reporting

Non-

Non-

OS/2

OS/2

On On On, Off

Dis. En. En./Dis. When Disabled, the following two items (Typematic Rate and

30 30 6-30

250 250 250-1000 ms When the typematic rate setting is Enabled, you can select a

Possible
Settings

Non-OS/2,

OS/2

char/sec.

VT100 Settings

9600, 19200,

38400, 57600,

115200

Mark, Even,

Space

Description

Select Yes to release IRQ6 when the system contains no floppy
drive, for compatibility with Windows 95 logo certification. In the
Integrated Peripherals screen, select NO on the Onboard FDC
Controller option.

Technology (S.M.A.R.T.) features of the HDD are supported.
S.M.A.R.T is used for prediction of devi ce degradation and/or
faults.

disabled.
Select OS2 only if you are running OS/2 with greater than 64MB of

RAM.

chipset, instead of the keyboard controller.
If you have set a password, select whether the password is

required every time the system boots (“System” option), or only
when you enter Setup (“Setup” option).

System, all floppy disk accesses (read/write) are limited to the
Supervisor (supervisor password required).

Control the state of the NumLock key when the system boots.
When set to “On”, the numeric keypad generates numbers instead
of controlling cursor operations.

Typematic Delay) are irrelevant. Keystrokes repeat at a rate
determined by the keyboard controller in your system. When
Enabled, you can select a typematic rate and a typematic delay.

When the typematic rate setting is Enabled, you can select a
typematic rate (the rate at which characters repeat when you hold
down a key).

typematic delay (the delay before keystrokes begin to repeat when
you hold down a key).

Select the baud rate of COM port. being used in VT100 mode.

Use this option to select the parity .

4.7

cPCI-MXS64GX Technical Reference Manual

4.1.7 Chipset Features Setup

This part of the setup allows you to define chipset-specific options and features.

BIOS

Option

CPU Internal Cache Dis. En. En./Dis. Enables or Disables the CPU Internal Cache (L1 cache).
External Cache Dis. En. En./Dis. Enables or Disables the External Cache (L2 cache).
CPU L2 Cache ECC

Checking

SDRAM RAS-to-CAS
Delay

SDRAM RAS
Precharge Time

SDRAM CAS Latency
Time

SDRAM Precharge
Control

DRAM Data Integrity
Mode

Memory Hole At 15M­16M

Video BIOS
Cacheable

Video RAM Cacheable Dis. En. En./Dis.

8 Bit I/O Recovery
Time

16 Bit I/O Recovery
Time

Defaults

Setup

Defaults

Dis. En. En./Dis. Enables or Disables ECC Checking for L2 cache.

33 2, 3

33 2, 3

33 2, 3

Dis. Dis. En./Dis.

Non-

ECC ECC,

ECC

Dis. Dis. En./Dis. You can reserve this area of system memory for ISA adapter ROM.

Dis. En. En./Dis. Selecting Enabled allows caching of the video BIOS ROM at C0000h

31 1-8, NA

21 1-4, NA

Possible
Settings

Non-ECC

Description

Note: processors provided by Kontron support ECC.
However, not all Pentium® II / III processors support ECC.
Check Intel’s website to know if your processor supports
ECC: http://developer.intel.com/support/

processors/pentiumII/identify.htm.

Note: Upon boot-up, the BIOS will detect and display the optimal
value for the SDRAM options (first four options in this menu), if it
is different from the Setup value. You must enter the AWARD
Setup, and set the options at the suggested value if you want the
best performance.

This option inserts a timing delay between the CAS and RAS strobe
signals, used when SDRAM is written to, read from, or refreshed. The
number selected is the number of clocks to be inserted between a row
activate command and either a read or write command.

Selects the number of CPU clocks for the RAS precharge. If an
insufficient number of cycles is allowed for the RAS to accumulate its
charge before SDRAM refresh, the refresh may be incomplete and the
DRAM may fail to retain data.

This option controls the number of clocks between when a read
command is sampled by the SDRAMs and when the chipset samples
read data from the SDRAMs. Select 3 for 3 DCLKs and 2 for 2 DCLKs.
If a given row is populated with a registered SDRAM DIMM, an extra
clock is inserted between the read command and when the chipset
samples read data.

When Enabled, all CPU cycles to SDRAM result in an All Banks
Precharge Command on the SDRAM interface.

When set to ECC, allows auto-correction of the data read from
memory. The ECC error flags’ status register and the error pointer are
updated if error correction occurs in this mode.
When set to Non-Ecc, no error checking or error reporting is done.

This option will w or k in EC C mod e on ly if all ins ta lled m em ory b anks
supports ECC (Error Checking and Correction)

When this area is reserved, it cannot be cached. The user information
of peripherals that need to use this area of system memory usually
discusses their memory requirements.

plus the VGA BIOS size, resulting in better video performance.
However, in any program writes to this memory area, a system error
may occur.

When Enabled, video memory region is cacheable. Some off-board
video card drivers may behave strangely; in such a case, disable this
option.

The I/O recovery mechanism adds bus clock cycles between PCI­originated I/O cycles to the ISA bus. This delay takes place because the
PCI bus is much faster than the ISA bus. These two fields let you add
recovery time (in bus clock cycles) for 8-bit and 16-bit I/O.

4.8

Software Setu ps

Chipset Features Setup (Continued)

BIOS

Option

PCI/VGA Palette
Snoop

Passive Release En. En. En./Dis. When Enabled, CPU to PCI bus accesses are allowed during passive

Delayed Transaction Dis. Dis. En./Dis. The chipset has an embedded 32-bit posted write buffer to support

Supervisor I/O Base
Address

Power-Supply Type AT AT AT, ATX This option selects the type of power supply.
AGP Aperture Size
(MB)
Video BIOS Shadow En. En. En./Dis.
C8000-CBFFF En. En. En./Dis.
CC000-CFFFF En. En. En./Dis.
D0000-D3FFF En. En. En./Dis.
D4000-D7FFF En. En. En./Dis.
D8000-DBFFF En. En. En./Dis.
DC000-DFFFF En. En. En./Dis.

Defaults

Setup

Defaults

Dis. Dis. En./Dis.

190h 190h

64 64 4 to 256 This option selects the size in megabytes of the AGP Aperture.

Possible
Settings

190h, 290h,

390h

Description

Palette snooping allows multiple VGA devices operating on
different buses to handle data from the CPU on each set of palette
registers.
When set to Enabled, data read and written by the CPU is
directed to both the PCI VGA device’s palette registers and the
ISA VGA device’s palette registers, permitting the palette registers
of both to be identical.
When set to Disabled, data read and written by the CPU is only
directed to the PCI VGA device’s palette registers.

release otherwise the arbiter only accepts another PCI master access
to local SDRAM .

delay transactions cycles. Select Enabled to support compliance with
PCI specific at ion s v ers ion 2.1.

This option determines the base address for the Supervisor I/O
Register, which is used for such functions as power fail detection
and the watchdog timer.

Software that resides in a read-only memory (ROM) chip on a
device is called firmware. Award permits shadowing of firmware
such as the system BIOS, video BIOS, and similar operating
instructions that come with some expansion peripherals.

Shadowing copies from ROM into system RAM, where the CPU
can read it through the 64-bit DRAM bus. Firmware not shadowed
must be read by the system through the 8 or 16-bit ISA bus.
Shadowing improves the performance of the system BIOS and
similar firmware for expansion peripherals.

Enable shadowing into each section of memory separately. Many
system designers hardwire shadowing of the system BIOS and
eliminate a System BIOS Shadow option. Note that on a PCI VGA
card (on board or off-board), the VGA BIOS is always shadowed.

Video BIOS shadows into memory area C0000 plus the VGA
BIOS size. The remaining areas between C0000 and DFFFF
shown on the BIOS Features Setup screen may be occupied by
other expansion card firmware. If an expansion peripheral in your
system contains ROM-based firmware, you need to know the
address range the ROM occupies to shadow it into the correct
area of RAM.

4.9

cPCI-MXS64GX Technical Reference Manual

4.1.8 Power Management Setup

This part of the setup confi g ures power conservation options.

Option

ACPI Function Dis. En. En./Dis. The Advanced Configuration and Power Interface (ACPI) allows

Power
Management

PM Control by
APM
Video Off Method V/H SYNC

Video Off After Standby Standby NA, Suspend,
Doze Mode Dis. Dis Disable

Standby Mode Dis. Dis. Disable

Suspend Mode Dis. Dis. Disable

HDD Power Down Dis. Dis. Disable

HDD Down When
Suspend
Throttle Duty Cycle 75.0% 75.0% 12.5%-75.0% When the syste m enters Doze mode, the C PU cl ock ru ns onl y part of

PCI / VGA
Act-Monitor
Soft-OFF by
PWR-BTTN

BIOS

Defaults

User

Def.

Yes Yes Yes, No If Yes, the OS can control the PM by APM calls. If No, the BIOS

Blank

En. En. En./Dis. When Enabled and the system goes in Suspend Mode, the hard disk is

Dis. Dis. En./Dis. When Enabled, continuous video activity restarts the global timer for

Instant-off Instant-off Instant-off,

Setup

Defaults

User

Def.

V/H SYNC

+

Blank

+

Possible
Settings

User Define,

Min Saving,
Max Saving

Blank Screen

V/H

SYNC+Blank,

DPMS,

Standby, Doze,

1min to 1h

1min to 1h

1min to 1h

1-15min

Delay 4 sec.

Description

Operating System Direct Power Management (OSPM) and make
advanced configuration architectures possible.
When Enabled, the OS supports ACPI or OSPM (e.g., Win98, and
Windows 2000

Note: When Enabled, and the OS is ACPI compliant, the OS
setting take precedence over all settings in this menu.

This option allows you to select the type (or degree) of power
saving for Doze, Standby, and Suspend modes.
Max Saving: Maximum power savings. Inactivity period is 1
minute in each mode.
Min Saving: Minimum power savings. Inactivity period is the
maximum setting in each mode (1 hour for Doze, Standby and
Suspend).
User Define: Set each mode individually. Select time-out periods
in the PM Timers section (see below).

will control the PM (Power Management)
Determines the manner in which the monitor is blanked.
V/H SYNC + Blank: System turns off vertical and horizontal
synchronization ports and writes blanks to the video buffer.
DPMS Support: Select this option if your monitor supports the Display
Power Management Signaling (DPMS) standard of the Video
Electronics Standards Association (VESA). Use the software supplied
for your video subsystem to select video power management values.
Blank Screen: System only writes blanks to the video buffer.
As the system moves from lesser to greater power-saving modes,
select the mode in which you want the monitor to blank.
After the selected period of system inactivity (1 minute to 1 hour), the
CPU clock r uns at low er spee d wh ile all o th er d ev ice s still operate at full
speed.
After entering Doze mode and the selected period of system inactivity
(1 minute to 1 hour) has elapsed, the video shuts off while all other
devices st ill ope rat e a t fu ll sp eed.
After entering Standby mode and the selected period of system
inactivity (1 minute to 1 hour) has elapsed, all devices including the
CPU shut off and the system waits for an event to wake them up again.
After the selected period of drive inactivity (1 to 15 minutes), the hard
disk drive powers down while all other devices remain active. The HDD
power down mode is o nly av aila ble if th e ha rd d riv e has this ca pab ility .

shut down.
the time. You may select the percentage of time that the clock

does not ru n. W hen 12.5% i s selected, the CPU is ru nning at n early
Full Speed and if 75% is selected, the CPU will be idle 75% of time .

Standby mode.
This option only works with an ATX power supply. It allows two
configurations for the power button: Instant-off for power supply on/off
switch, or Delay 4 sec. for entering Suspend Mode after pressing the
button at least 4 seconds.

4.10

Software Setu ps

Power Management Setup (Continued)

BIOS

Option

Resume by Ring Dis. En. En./Dis. When Enabled and a modem is connected to a serial port, allows a
IRQ 8 Break Suspend Dis. En. En./Dis. When Enabled, the RTC alarm interrupt is monitored to allow an

Resume by Alarm Dis. Dis. En./Dis. When Enabled, allows setup of a time to re-activate the CPU when in

IRQ[3-7,9-15], NMI Dis. En. En./Dis.
Primary IDE 0 Dis. En. En./Dis.
Primary IDE 1 Dis. En. En./Dis.
Secondary IDE 0 Dis. En. En./Dis.
Secondary IDE 1 Dis. En. En./Dis.
Floppy Disk Dis. En. En./Dis.
Serial Port En. En. En./Dis.
Parallel Po rt Dis. En. En./Dis .

Defaults

Reload Global Timer Events:

Setup

Defaults

Possible
Settings

Description

modem ring to re-activate the CPU when in Suspend mode.
interrupt to awaken the system when in Doze, Standby or Suspend

Mode.
Suspend mode with the options Date (of Month) Alarm and Time

(hh:mm:ss) Alarm.

Note: The IRQ 8 Break Suspend option in this setup screen must
be Enabled to use the RTC alarm.

When any of the options below is Enabled, monitoring of the interrupt
will occur to a llow an in te rru pt to awa ken the s yst em wh en in Do ze,
Standby or Suspend Mode.

4.11

cPCI-MXS64GX Technical Reference Manual

4.1.9 PnP/PCI Configuration

This part of the setup configures PnP/PCI options.

BIOS

Option

PNP OS Installed Yes No Yes, No If the operating system (OS) is Plug and Play (for example

Resources ControlledByAuto Man. Auto, Man. The Award Plug and Play BIOS can automatically configure all the

Reset Configuration
Data

IRQ n Assigned To PCI/ISA

DMA n Assigned To PCI/ISA

Init Display First Onboard Onboard PCI Slot,

Assign IRQ For VGA Dis. Dis. En./Dis. When Enabled, the video card is assigned an IRQ.
Assign IRQ For USB En. En. En./Dis. When Enabled, the USB is assigned an IRQ. When Disabled, the

PCI Latency Timer 32 32 0-255
Used MEM Base

Address

Used MEM length 16K 16K 16K, 32K,

Defaults

Setup

Defaults

Dis. Dis. En./Dis. Normally, you leave this field Disabled. Select Enabled to reset

PCI/ISA

PnP

PnP

PCI/ISA

PnP

PnP

N/A N/A N/A,

Possible
Settings

PCI/ISA PnP,

Legacy ISA

PCI/ISA PnP,

Legacy ISA

Onboard, AGP

(integers)

C800, CC00,

D000, D400,
D800, DC00

48K, 64K

Description

Windows 95), select “Yes” if you want the OS to allocate
resources according to Plug and Play standards, or “No” if you
want the same resource allocations at every system boot-up.
Select “No” when the OS is not Plug and Play (for example,
DOS).

Note: When set to “Yes”, only the boot devices will get

Resources.

boot and Plug and Play-compatible devices. If you select Auto, all
the interrupt requests (IRQs) and DMA assignment fields
disappear as well as Used Mem Base Address and Lenght as the
BIOS automatically assigns them.

Extended System Configuration Data (ESCD) when you exit
Setup if you have installed a new add-on and the system
reconfiguration has caused such a serious conflict that the
operating system cannot boot.
When resources are controlled manually, assign each system
interrupt as one of the following types, depending on the type of
device using the interrupt:
Legacy ISA: Devices compliant with the original PC AT bus
specification, requiring a specific interrupt.
PCI/ISA PnP: Devices compliant with the Plug and Pla y standard,
whether designed for PCI or ISA bus architecture.
When Legacy ISA is selected for an IRQ line, this resource will not
be available for PCI /ISA PnP.
When resources are controlled manually, assign each system
DMA channel as one of the following types, depending on the type
of device using the interrupt:
Legacy ISA: Devices compliant with the original PC AT bus
specification, requiring a specific DMA channel.
PCI/ISA PnP: Devices compliant with the Plug and Pla y standard,
whether designed for PCI or ISA bus architecture.
When Legacy ISA is selected for a DMA channel, this resource
will not be available for PCI/ISA PnP.
Initializes the specified video display. The chosen display
becomes the primary display. Other display devices are ignored
by the BIOS and configured by the OS.

IRQ is freed up for another purpose.
This option specifies the value of the Latency Timer for the PCI
bus master, in units of PCI bus clocks.
Select a base address for the memory area used by any
peripheral that requires high memory.

Select a base address for the memory area used by any
peripheral that requires high memory. When this option is not set
to N/A, the menu for used memory lengths available is displayed.

4.12

4.1.10 CPU/Board Features Setup

Software Setu ps

Option

Current Processor(s)
Speed

Front Side Bus Speed nnn nnn nnn This option displays the current Front Side Bus speed. This speed

. Thermal

Management

. Thermal Audio Alarm Dis. Dis. En./Dis. When the Thermal Management option and this option are

. CPU 1 Die
Temperature

. Resume Alarm (°C)

. Overheat Alarm (°C)

. CPU1 Local
Temperature

. Resume Alarm (°C)
. Overheat Alarm (°C)

Save CMOS in Flash Dis. Dis. En./Dis. Saving CMOS memory content into Flash Memory will prevent to

Watchdog Timer Dis Dis En./Dis.

Watchdog After POST Ds Dis En./Dis. This option enables Watchdog circuit after the POST sequence
Watchdog Duration

(ms)
Current CPU Fan 1

and 2 speed

Current Vcpp1 and 2 - - Varies This value is set according to the actual value of Vcpp1 & Vcpp2
Vin values : +12V,

+5V, +3.3V, +2.5V

BIOS

Defaults

nnn nnn nnn This option displays the current processor speed.

262144 262144 64 to

Setup

Defaults

Dis. Dis. En./Dis. When this option is enabled, the CPU temperature is monitored.

--Varies

50 50 10-70

70 70 30-90 The CPU will be slowed down (Doze mode) when it reaches the

--Varies

42 42 10-70
50 50 30-90

- - Varies Speed sensing device sets this value according to the fan speed.

- - Varies The values of these voltages are each displayed according to the

Possible
Settings

Thermal Management Optio ns:

262144

is selected by the CPU auto-detection logic.

Whenever the CPU overheats, the CPU slows down to lower the
temperature.

enabled, a continuous audible alarm is sounded when the
temperature specified in the Overheat Alarm options is reached.
Such an alarm may not be supported by the Operating System.

Displays the current die (internal) CPU temperature, when
Thermal Management is enabled.

The CPU will be slowed down (Doze mode) when it reaches the
selected Overheat Alarm (°C) temperature.

Full speed (Normal mode) will be resumed when the temperature
comes down to the selected Resume Alarm (°C) temperature.

A minimum of + 4° is automatically ensured for the Overheat
Alarm temperature with reference to the Resume Alarm.

selected Overheat Alarm (°C) temperature.
Full speed (Normal mode) will be resumed when the temperature

comes down to the selected Resume Alarm (°C) temperature.
A minimum of + 4° is automatically ensured for the Overheat

Alarm temperature with reference to the Resume Alarm
Displays the current case (external) CPU temperature, when

Thermal Management is enabled.
The CPU will be slowed down (Doze mode) when it reaches the

selected Overheat Alarm (°C) temperature.
Full speed (Normal mode) will be resumed when the temperature

comes down to the selected Resume Alarm (°C) temperature.
A minimum of + 4° is automatically ensured for the Overheat

Alarm temperature with reference to the Resume Alarm.

loose CMOS options when battery fails.
This option enables the Watchdog option when the POST is

running.

Use this option to setup duration time (in ms) of the Watchdog
timing circuitry.

If no fan is installed or if a fan has no tachymetric capability, this
value will be 0.

current value.

Description

4.13

cPCI-MXS64GX Technical Reference Manual

4.1.11 Integrated Peripherals

Option BIOS

On-Chip
Primary/Secondary

On-Chip Primary IDE

Master PIO
Slave PIO
Master UDMA
Slave UDMA

On-Chip Secondary IDE
Master PIO

Slave PIO
Master UDMA
Slave UDMA

IDE HDD Block
Mode

Onboard PCI SCSI
Chip
Ethernet Controller 1
and 2

USB Keyboard
Support

PS/2 Mouse
Function Control
Onboard FDC
Controller

Onboard Serial Port13F8/

Onboard Serial Port
2

IRQ Line 3 3 3,4,5,7 Sets IRQ line for serial port 2
Onboard Serial Port33E8/

Serial Port 3 Mode RS-232 RS-232
Onboard Serial Port

4
IRQ Line 3 3 3,4,5,7 Sets the IRQ line for serial port 4.
Onboard Parallel

Port

Parallel Port Mode

ECP Mode Use DMA 3 3 1, 3 Select a DMA channel for the parallel port.

Defaults

378/ IRQ7

EPP1.9

Setup

Defaults

En. En. En./Dis.

Auto Auto

Dis. Auto Auto, Disabled.

Dis. En. En./Dis.

En. En. En./Dis. Enables/disables the onboard SCSI controller.
En. En. En./Dis. Enables/disables the onboard Ethernet controller.

OS OS OS/BIOS

Auto Auto Auto/Dis.

En. En. En./Dis.

IRQ4

IRQ4

ECP

3F8/

IRQ4

Dis 2F8

3E8/

IRQ4

Dis 2E8

378/

IRQ7

ECP

+

EPP1.9

+

Possible

Settings

Auto,

Modes

0-4

Dis, 3F8/IRQ4,

2F8/IRQ3,
3E8/IRQ4,

2E8/IRQ3

3F8,2F8, 3E8,

2E8

Disabled

Dis, 3F8/IRQ4,

2F8/IRQ3,
3E8/IRQ4,

2E8/IRQ3

RS-232 RS-422

RS-485

3F8,2F8, 3E8,

2E8

Disabled

Description

Select Enabled to activate the Primary/Secondary IDE channel.
The four options below appear only if the On-Chip Primary option
is enabled.

Use this option to set a PIO mode (0-4) for each of the onboard
IDE devices. Modes 0 through 4 provide successively increased
performance and speed. In Auto mode, the system auto matically
determines the best mode for each device. If you select a mode
that the drive does not support, it may not work, so choose a
lesser value or Auto to see the best mode for the drive.

Ultra DMA/33 implementation is possible only if your IDE hard
drive supports it and the operating environment includes a DMA
driver (Windows 95 OSR2 or a third-party IDE bus master driver).
If your hard drive and your system software both support Ultra
DMA/33, select Auto to enable BIOS support.

Block mode is also called block transfer, multiple commands, or
multiple sector read/write. If your IDE hard drive supports block
mode (most new drives do), select Enabled for automatic
detection of the optimal number of block read/writes per sector the
drive can support.

This option is for DOS and BIOS support only (Win 95 has it is
own drivers). It does not enable or disable the USB controller.

When set to Auto, the PS/2 mouse is automatically enabled, if it is
present.
Select Disabled to disable the onboard floppy disk controller
(FDC).

Select a COM port address and IRQ# for Serial Port 1

Select a COM port address for Serial Port 2.

Select a COM port address and IRQ# for Serial Port 3

Select the operation mode for Serial Port 3.

Select a COM port address for serial port 4.

Select a LPT address and IRQ# for the physical parallel (printer)
port. Possible settings are:
Disabled, 3BC/IRQ7, 378/IRQ7, 278/IRQ5,
Select an operating mode for the onboard parallel port. Select
ECP or EPP unless you are certain both your hardware and
software does not support ECP or EPP mode.
Possible settings are SPP, EPP1.9+SPP, ECP, ECP+ EPP1.9,
Normal, EPP1.7+SPP, ECP+EPP1.7

4.14

cPCI-MXS64GX Technical Reference Manual

4.2. VT100 MODE

The VT100 operating mode allows remote setups of the board. This configuration requires
a remote terminal that must be connected to the boa rd through a se rial communication link.

4.2.1 Requirements

The terminal should emulate a VT100 or ANSI terminal. Terminal emulation programs such
as Telix

®

or Procom® can also be used.

4.2.2 Setup & Configuration

Follow these steps to set up the VT100 mode:

1. Connect a monitor and a keyboard to your board and turn on the power.

2. Enter into the CMOS Setup program in the “BIOS Feature Setup”

3. Select the VT100 mode and the appropriate COM port and save your setup.

4. Connect the communications cable as shown in the next page.

✎ NOTE

If you do not require a full cable for your terminal, you can set up a partial
cable by using only the TXD and RXD lines. To ignore control lines simply
loop them back as shown in VT100 Partial Setup cable diagram.

5. Configure yo ur terminal to communicate using the sa me parameters as in CMOS

Setup.

6. Reboot the board.

7. Use the remote keyboard and display to setup the BIOS.

8. Save the setup, exit, and disconnect the remote co mputer from the board to operate

in stand-alone configuration.

4.15

cPCI-MXS64GX Technical Reference Manual

4.2.3 Running Without a Terminal

The board can boot up without a screen or terminal attached. If the speed is set to Auto a nd
no terminal is connected, the speed is set to 115,200 bauds.

Furthermore, you can run without any console at all by simply not enabling VT100 Mode and
by disabling the onboard video.

Full Setup

COM

Connector

TXD
RXD
DTR
DSR
RTS

SBC Board

CTS
DCD
GND

RXD
TXD
DSR
DTR
CTS
RTS

GND

Partial Setup

TXD
RXD
DTR
DSR
RTS

SBC Board

VT100 Terminal

CTS
DCD
GND

RXD
TXD

VT100 Terminal

GND

4.16

APPENDICES

P

A

R

T

A. BOARD SPECIFICATIONS

B. MEMORY & I/O MAPS

C. INTERRUPT LINES

D. BOARD DIAGRAMS

E. CONNECTOR PINOUTS

F. BIOS SETUP ERROR CODES

G. EMERGENCY PROCEDURE

H. GETTING HELP & RMA

5

A. BOARD SPECIFICATIONS

FEATURES DESCRIPTION
Overview
Supported

Microprocessors
CHIPSET

Bus Interface

Cache Memory

System Memory

Data Path

Interrupts

Flash Memory

Video

CompactPCI System Processor board

Pentium III Processor – Low Power 500MHz

Intel 440GX AGPset.
22-signal High-Availability controller: #Select, #Healthy, #Reset for 7

CPCI I/O slots #E num, (43 with mezzanine)
100MHz Front side bus
CompactPCI bus, 64 bi ts (33MHz) through J1 and J2
PCI-PCI bridge: DEC 21154; supports up to 7 REQ/GNT f or fully loaded

CompactPCI® sys tem
PCI Mezzanine (PMC)
Proprietary Mezzanine with PCI bus, FD and EI DE support
SMBus (for power management of CP U temperature m onitoring, DRAM

control, clock buf fers and power control)
cPCI-MXS64GX: Level 1: 16/16KB instruc tion/Data CPU-internal Level 1

Level 2: 256KB internal, 64-bit wide, pi pel i ned burst
Three 168-pin Latching DIMM sockets, 64/72-bit
Up to 1.5GB of SDRAM with parity or ECC
(for single bit error correcti on and doubl e bi t error detection)
64-bit on CPU, 32-bit on video mem ory; 32-bit on local PCI and 64-bits

on CompactPCI connec tors
11 edge sensitive and configurable
4 PCI level sensitive, configurable to any interrupt vector for PnP

compatibility.
512KB for BIOS field upgrade; Silic on Serial ID TAG for unique board

identification accessible via software.
32-bit AGP video controller (I ntel 69000) with 2MB video memory
CRT resolutions up to 1024 x 768 x 64K colors or 1280 x 1024 x 256

colors

A-1