Kontron CP6500-V User Manual

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Page 1

CP6500-V

6U CompactPCI

Intel® Celeron® Based CPU Board

Manual ID: 28945, Rev. Index 01

04 March, 2005

USER GUIDE

P R E L I M I N A R Y

The product described in this manual is in compliance with all applied CE standards.

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Preface CP6500-V

Revision History

Publication Title: CP6500-V: 6U CompactPCI Intel® Celeron® Based CPU Board

ID Number: 28945

Rev.

Index

01 User Guide 04 Mar, 2005

Brief Description of Changes Date of Issue

Imprint

Kontron Modular Computers GmbH may be contacted via the following:

MAILING ADDRESS TELEPHONE AND E-MAIL

Kontron Modular Computers GmbH +49 (0) 800-SALESKONTRON Sudetenstraße 7 sales@kontron.com

D - 87600 Kaufbeuren Germany

For further information about other Kontron Modular Computers products, please visit our Internet web site: www.kontron.com

P R E L I M I N A R Y

Copyright

Copyright © 2005 Kontron Modular Computers GmbH. All rights reserved. This manual may not be copied, photocopied, reproduced, translated or converted to any electronic or machinereadable form in whole or in part without prior written approval of Kontron Modular Computers. GmbH.

Disclaimer:

Kontron Modular Computers GmbH rejects any liability for the correctness and completeness of this manual as well as its suitability for any particular purpose.

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CP6500-V Preface

Revision History .........................................................................................................ii

Imprint ........................................................................................................................ii

Copyright ....................................................................................................................ii

Table of Contents ......................................................................................................iii

List of Tables .............................................................................................................ix

List of Figures ...........................................................................................................xi

Proprietary Note ...................................................................................................... xiii

Trademarks ............................................................................................................. xiii

Environmental Protection Statement ....................................................................... xiii

Explanation of Symbols .......................................................................................... xiv

For Your Safety ........................................................................................................xv

High Voltage Safety Instructions ..........................................................................xv

Special Handling and Unpacking Instructions .....................................................xv

General Instructions on Usage ...............................................................................xvi

Two Year Warranty ................................................................................................. xvii

Chapter

1. Introduction .................................................................................................. 1 - 3

1.1 System Overview .................................................................................... 1 - 3

1.2 Board Overview ....................................................................................... 1 - 4

1.2.1 Board Introduction .......................................................................... 1 - 4

1.2.2 Board-Specific Information ............................................................. 1 - 5

1.3 System Expansion Capabilities ............................................................... 1 - 6

1.3.1 PMC Modules ................................................................................. 1 - 6

1.3.2 CP-CTM80-2 Rear I/O Module ....................................................... 1 - 6

1.4 System Relevant Information .................................................................. 1 - 6

1.5 Board Diagrams ...................................................................................... 1 - 7

1.5.1 Functional Block Diagram ............................................................... 1 - 7

1.5.2 Front Panels ................................................................................... 1 - 8

1.5.3 Board Layout .................................................................................. 1 - 9

1.6 Technical Specification .......................................................................... 1 - 11

P R E L I M I N A R Y

1.7 Applied Standards ................................................................................. 1 - 15

1.8 Kontron Software Support ..................................................................... 1 - 16

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1.9 Related Publications ..............................................................................1 - 16

Chapter

2. Functional Description .................................................................................2 - 3

2.1 CPU, Memory and Chipset ......................................................................2 - 3

2.1.1 CPU .................................................................................................2 - 3

2.1.2 Memory ...........................................................................................2 - 4

2.1.3 815-B0 Chipset Overview ................................................................2 - 4

2.1.4 Graphics and Memory Controller Hub (815-B0) ..............................2 - 5

2.1.5 I/O Controller Hub ICH4 ..................................................................2 - 5

2.2 Peripherals ...............................................................................................2 - 6

2.2.1 Timer ...............................................................................................2 - 6

2.2.2 Watchdog Timer ..............................................................................2 - 6

2.2.3 Battery .............................................................................................2 - 6

2.2.4 Reset ...............................................................................................2 - 7

2.2.5 SMBus Devices ...............................................................................2 - 7

2.2.6 Thermal Management/System Monitoring ......................................2 - 7

2.2.7 Serial EEPROM ..............................................................................2 - 8

2.2.8 FLASH Memory ...............................................................................2 - 8

2.2.8.1 BIOS FLASH (Firmware Hub) .................................................2 - 8

2.2.8.2 CompactFlash Socket .............................................................2 - 8

2.2.9 Front Panel LEDs ............................................................................2 - 9

P R E L I M I N A R Y

2.2.9.1 Watchdog and Overtemperature LEDs .................................2 - 10

2.2.9.2 Front-I and Front-II General Purpose LEDs ..........................2 - 10

2.2.9.3 Hot Swap LED ......................................................................2 - 10

2.2.10 Keyboard/Mouse Interface ............................................................2 - 10

2.2.11 USB Interfaces ..............................................................................2 - 11

2.2.12 Graphics Controller .......................................................................2 - 12

2.2.12.1 Video Memory Usage ...........................................................2 - 12

2.2.12.2 Video Resolution ...................................................................2 - 13

2.2.12.3 CRT Interface and Connector J10 ........................................2 - 14

2.2.13 COM Port ......................................................................................2 - 15

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2.2.14 Floppy Drive Interface ................................................................... 2 - 16

2.2.15 Fast Ethernet ................................................................................ 2 - 16

2.2.16 EIDE Interfaces ............................................................................. 2 - 17

2.2.16.1 EIDE 44-Pin Connector J19 ................................................. 2 - 19

2.2.16.2 EIDE 40-Pin Connector J20 ................................................. 2 - 20

2.2.17 Extension Connector J12 .............................................................. 2 - 20

2.2.18 PMC Interface ............................................................................... 2 - 21

2.2.18.1 PMC Connectors J23, J24, and J25 Pinouts ..................... 2 - 22

2.2.19 CompactPCI Interface .................................................................. 2 - 24

2.2.19.1 System Master Configuration ............................................... 2 - 24

2.2.19.2 PCI-to-PCI Bridge ................................................................ 2 - 24

2.2.19.3 Peripheral Master Configuration (Passive Mode) ................ 2 - 24

2.2.19.4 Packet Switching Backplane (PICMG 2.16) ......................... 2 - 24

2.2.19.5 Hot Swap Support ................................................................ 2 - 24

2.2.19.6 Power Ramping .................................................................... 2 - 25

2.2.19.7 Precharge ............................................................................. 2 - 25

2.2.19.8 Handle Switch ...................................................................... 2 - 25

2.2.19.9 ENUM# Interrupt .................................................................. 2 - 25

2.2.19.10 Hot Swap LED ...................................................................... 2 - 25

2.2.20 CompactPCI Bus Connector ......................................................... 2 - 26

2.2.20.1 CompactPCI Connector Keying ........................................... 2 - 26

2.2.20.2 CompactPCI Connectors J1 and J2 Pinouts ........................ 2 - 27

2.2.20.3 CompactPCI Rear I/O Connectors J3-J5 and Pinouts ......... 2 - 31

2.2.20.4 Rear I/O Configuration ......................................................... 2 - 35

Chapter

P R E L I M I N A R Y

3. Installation ................................................................................................... 3 - 3

3.1 Safety Requirements ............................................................................... 3 - 3

3.2 CP6500-V Initial Installation Procedures ................................................. 3 - 4

3.3 Standard Removal Procedures ............................................................... 3 - 5

3.4 Hot Swap Procedures ............................................................................. 3 - 5

3.4.1 System Master Hot Swap ............................................................... 3 - 5

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3.4.2 Peripheral Hot Swap Procedure ......................................................3 - 6

3.5 Installation of CP6500-V Peripheral Devices ...........................................3 - 7

3.5.1 CompactFlash Installation ...............................................................3 - 7

3.5.2 USB Device Installation ...................................................................3 - 7

3.5.3 Rear I/O Device Installation .............................................................3 - 8

3.5.4 Battery Replacement .......................................................................3 - 8

3.5.5 Hard Disk Installation ......................................................................3 - 8

3.6 Software Installation ................................................................................3 - 9

Chapter

4. Configuration ................................................................................................4 - 3

4.1 Jumper Description ..................................................................................4 - 3

4.1.1 CompactFlash Configuration ..........................................................4 - 3

4.1.2 CompactFlash Power Configuration ................................................4 - 3

4.1.3 Clearing BIOS CMOS Setup ...........................................................4 - 3

4.1.4 Shorting Chassis GND (Shield) to Logic GND ................................4 - 4

4.1.5 VGA CRT Rear I/O Configuration ...................................................4 - 4

4.1.6 Front-I and Front-II General Purpose LEDs ....................................4 - 4

4.1.7 Serial Ports COM1 and COM2 Jumper and Resistor Settings ........4 - 5

4.1.7.1 COM1 Jumper and Resistor Setting .......................................4 - 5

4.1.7.2 COM2 Jumper and Resistor Setting .......................................4 - 6

4.2 Interrupts ..................................................................................................4 - 8

P R E L I M I N A R Y

4.3 Onboard PCI Interrupt Routing ................................................................4 - 9

4.4 Memory Map ............................................................................................4 - 9

4.4.1 Memory Map for the 1st Megabyte .................................................4 - 9

4.4.2 I/O Address Map ...........................................................................4 - 10

4.5 Special Registers Description ................................................................4 - 11

4.5.1 Watchdog ......................................................................................4 - 11

4.5.2 Watchdog Trigger ..........................................................................4 - 11

4.5.3 Watchdog Timer Register ..............................................................4 - 12

4.5.4 Geographic Addressing Register ..................................................4 - 13

4.5.5 Watchdog, CompactPCI Interrupt Configuration Register .............4 - 14

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4.5.6 CPCI Master Reset ....................................................................... 4 - 15

4.5.7 I/O Status ...................................................................................... 4 - 16

4.5.8 Board ID ........................................................................................ 4 - 16

4.5.9 Hardware Index Register .............................................................. 4 - 17

4.5.10 Hot Swap Control Register ........................................................... 4 - 17

4.5.11 Logic Version Register .................................................................. 4 - 18

4.5.12 LED Control Register .................................................................... 4 - 18

4.5.13 Hot Swap LED Control Register ................................................... 4 - 19

Chapter

5. BIOS ............................................................................................................ 5 - 3

Chapter

6. Power Consumption .................................................................................... 6 - 3

6.1 System Power ......................................................................................... 6 - 3

6.1.1 CP6500-V Baseboard ..................................................................... 6 - 3

6.1.2 Backplane ....................................................................................... 6 - 4

6.1.3 Power Supply Units ........................................................................ 6 - 4

6.1.3.1 Start-Up Requirement ............................................................ 6 - 5

6.1.3.2 Power-Up Sequence .............................................................. 6 - 5

6.1.3.3 Tolerance ................................................................................ 6 - 5

6.1.3.4 Regulation .............................................................................. 6 - 6

P R E L I M I N A R Y

6.1.3.5 Rise Time Diagram ................................................................ 6 - 6

6.2 Power Consumption ................................................................................ 6 - 7

6.2.1 Real Applications ............................................................................ 6 - 7

6.2.2 Power Consumption of CP6500-V Accessories ............................ 6 - 8

6.2.3 Power Requirement for the CP6500-V ................................................6 - 8

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Chapter

7. System Considerations ................................................................................7 - 3

7.1 Passive Thermal Regulation ....................................................................7 - 3

7.1.1 CPU External Thermal Supervision ................................................7 - 3

7.1.2 CPU Emergency Thermal Supervision ...........................................7 - 4

7.1.3 Thermal Management Recommendations ......................................7 - 4

7.2 Active Thermal Regulation .......................................................................7 - 4

7.2.1 Heat Sinks .......................................................................................7 - 4

7.2.2 Forced Air Flow ...............................................................................7 - 5

7.2.3 Peripherals ......................................................................................7 - 6

Annex

A. CP-CTM80-2 RIO Module ........................................................................... A - 3

A.1 Introduction ............................................................................................. A - 3

Annex

B. AMIBIOS8 ................................................................................................... B - 3

P R E L I M I N A R Y

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CP6500-V Preface

List of Tables

1-1 System Relevant Information .................................................................... 1 - 6

1-2 CP6500-V Main Specifications ................................................................ 1 - 11

1-3 Applied Standards ................................................................................... 1 - 15

1-4 Related Publications ................................................................................ 1 - 16

2-1 Supported Intel Celeron Processors on the CP6500-V ............................. 2 - 3

2-2 Maximum Power Dissipation of Intel Celeron (CPU only) ......................... 2 - 3

2-3 SM Bus Device Addresses ........................................................................ 2 - 7

2-4 EEPROM Address Map ............................................................................. 2 - 8

2-5 CompactFlash Connector J14 Pinout ........................................................ 2 - 9

2-6 Keyboard Connector J22 Pinout .............................................................. 2 - 10

2-7 USB Connectors J7 and J8 Pinout .......................................................... 2 - 11

2-8 Partial List of Display Modes Supported .................................................. 2 - 13

2-9 CRT Connector J10 Pinout ...................................................................... 2 - 14

2-10 Serial Port Connectors CON9 (COM1) Pinout ........................................ 2 - 15

2-11 Pinouts of J6A/B Based on the Implementation ...................................... 2 - 17

2-12 Pinout of EIDE Connector J19 ................................................................. 2 - 19

2-13 Pinout of EIDE Connector J20 ................................................................. 2 - 20

2-14 PMC Connectors J23 and J25 Pinouts .................................................... 2 - 22

2-15 PMC Connector J24 Pinouts ................................................................... 2 - 23

2-16 Coding Key Colors on J1 ......................................................................... 2 - 26

2-17 CompactPCI Bus Connector J1 System Slot Pinout .............................. 2 - 27

2-18 CompactPCI Bus Connector J1 Peripheral Slot Pinout ........................... 2 - 28

2-19 64-bit CompactPCI Bus Connector J2 System Slot Pinout .................... 2 - 29

2-20 64-bit CompactPCI Bus Connector J2 Peripheral Slot Pinout ................. 2 - 30

2-21 Backplane J3 Pinout ................................................................................ 2 - 31

2-22 Backplane J3 Signals .............................................................................. 2 - 32

P R E L I M I N A R Y

2-23 Backplane J4 Pinout ................................................................................ 2 - 33

2-24 Backplane J5 Pinout ................................................................................ 2 - 34

2-25 Backplane J5 Signals .............................................................................. 2 - 34

4-1 CompactFlash Configuration ..................................................................... 4 - 3

4-2 CompactFlash Power Configuration .......................................................... 4 - 3

4-3 Clearing BIOS CMOS Setup ..................................................................... 4 - 3

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4-4 Shorting Chassis GND (Shield) to Logic GND ........................................... 4 - 4

4-5 VGA-CRT Jumper Setting .......................................................................... 4 - 4

4-6 General Purpose LED Setting .................................................................... 4 - 4

4-7 Resistor Setting to Configure COM1 .......................................................... 4 - 5

4-8 Jumper Setting for RS422 RXD Termination (COM1) ................................ 4 - 5

4-10 Resistor Setting to Configure COM2 .......................................................... 4 - 6

4-9 Jumper Setting for RS422 TXD and RS485 Termination (COM1) ............. 4 - 6

4-11 Jumper Setting for RS422 RXD Termination (COM2) ................................ 4 - 7

4-12 Jumper Setting for RS422 TXD and RS485 Termination (COM2) ............. 4 - 7

4-13 Interrupt Setting .......................................................................................... 4 - 8

4-14 PCI Interrupt Routing ................................................................................. 4 - 9

4-15 Memory Map for the 1st Megabyte ............................................................ 4 - 9

4-16 I/O Address Map ...................................................................................... 4 - 10

4-17 Watchdog Timer Register ........................................................................ 4 - 12

4-18 Geographic Addressing Register ............................................................. 4 - 13

4-19 Watchdog, CompactPCI Interrupt Configuration Register ....................... 4 - 14

4-20 CPCI Master Reset Register .................................................................... 4 - 15

4-21 I/O Status Register ................................................................................... 4 - 16

4-22 Board ID Register .................................................................................... 4 - 16

4-23 Hardware Index Register ........................................................................ 4 - 17

4-24 Hot Swap Control Register ....................................................................... 4 - 17

4-25 Logic Version Register ............................................................................ 4 - 18

4-26 LED Control Register ............................................................................... 4 - 18

4-27 Hot Swap LED Control Register .............................................................. 4 - 19

P R E L I M I N A R Y

6-1 Maximum Input Power Voltage Limits ........................................................ 6 - 3

6-2 DC Operational Input Voltage Ranges ....................................................... 6 - 3

6-3 Input Voltage Characteristics ..................................................................... 6 - 5

6-4 Power Consumption: DOS ......................................................................... 6 - 7

6-5 Power Consumption: Windows® 2000 IDLE Mode .................................... 6 - 7

6-6 Power Consumption: Windows® 2000 100% CPU Usage ........................ 6 - 8

6-7 Power Consumption Table for CP6500-V Accessories .............................. 6 - 8

6-8 Start-Up Current of the CP6500-V ............................................................. 6 - 8

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CP6500-V Preface

List of Figures

1-1 CP6500-V Functional Block Diagram ...................................................... 1 - 7

1-2 CP6500-V 4 HP Front Panel .................................................................... 1 - 8

1-3 CP6500-V Board Layout (Top View) ........................................................ 1 - 9

1-4 CP6500-V Board Layout (Bottom View) ................................................ 1 - 10

2-1 815-B0 Chipset Functional Block Diagram .............................................. 2 - 4

2-2 Keyboard Connector J22 ....................................................................... 2 - 10

2-3 USB Connectors J7 and J8 .................................................................... 2 - 11

2-4 D-SUB CRT Connector J10 ................................................................... 2 - 14

2-5 PC-Compatible D-SUB Serial Connectors J9 (COM1) .......................... 2 - 15

2-6 Dual Fast Ethernet Connector J6A/B .................................................... 2 - 16

2-7 EIDE Interface Connectors J19 and J20 ................................................ 2 - 18

2-8 Extension Connector J12 ....................................................................... 2 - 20

2-9 PMC Connectors J23, J24, and J25 ...................................................... 2 - 21

2-10 CompactPCI Connectors J1-J5 ............................................................ 2 - 26

4-1 COM1 Configuration Jumpers and Resistors .......................................... 4 - 5

4-2 COM2 Configuration Jumpers and Resistors ......................................... 4 - 6

6-1 Start-Up Ramp of the CP3-SVE180 AC Power Supply ............................ 6 - 6

7-1 Celeron Temperature Vs. Airspeed Graph with Heat Sink ..................... 7 - 5

A-1 CP-CTM80-2 RIO Module, 4HP Variant .................................................. A - 4

P R E L I M I N A R Y

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P R E L I M I N A R Y

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CP6500-V Preface

Proprietary Note

This document contains information proprietary to Kontron Modular Computers GmbH. It may not be copied or transmitted by any means, disclosed to others, or stored in any retrieval system or media without the prior written consent of Kontron Modular Computers GmbH or one of its authorized agents.

The information contained in this document is, to the best of our knowledge, entirely correct. However, Kontron Modular Computers GmbH cannot accept liability for any inaccuracies or the consequences thereof, or for any liability arising from the use or application of any circuit, product, or example shown in this document.

Kontron Modular Computers GmbH reserves the right to change, modify, or improve this document or the product described herein, as seen fit by Kontron Modular Computers GmbH without further notice.

Trademarks

Kontron Modular Computers GmbH, the PEP logo and, if occurring in this manual, “CXM” are trademarks owned by Kontron Modular Computers GmbH, Kaufbeuren (Germany). In addition, this document may include names, company logos and trademarks, which are registered trademarks and, therefore, proprietary to their respective owners.

Environmental Protection Statement

This product has been manufactured to satisfy environmental protection requirements where possible. Many of the components used (structural parts, printed circuit boards, connectors, batteries, etc.) are capable of being recycled.

Final disposition of this product after its service life must be accomplished in accordance with applicable country, state, or local laws or regulations.

P R E L I M I N A R Y

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Preface CP6500-V

Explanation of Symbols

CE Conformity

This symbol indicates that the product described in this manual is in compliance with all applied CE standards. Please refer also to the section “Applied Standards” in this manual.

Caution, Electric Shock!

This symbol and title warn of hazards due to electrical shocks (> 60V) when touching products or parts of them. Failure to observe the precautions indicated and/or prescribed by the law may endanger your life/health and/or result in damage to your material.

Please refer also to the section “High Voltage Safety Instructions” on the following page.

Warning, ESD Sensitive Device!

This symbol and title inform that electronic boards and their components are sensitive to static electricity. Therefore, care must be taken during all handling operations and inspections of this product, in order to ensure product integrity at all times.

Please read also the section “Special Handling and Unpacking Instructions” on the following page.

Warning!

This symbol and title emphasize points which, if not fully understood and taken into consideration by the reader, may endanger your health and/or result in damage to your material.

Note ...

This symbol and title emphasize aspects the reader should read

P R E L I M I N A R Y

through carefully for his or her own advantage.

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CP6500-V Preface

For Your Safety

Your new Kontron product was developed and tested carefully to provide all features necessary to ensure its compliance with electrical safety requirements. It was also designed for a long fault-free life. However, the life expectancy of your product can be drastically reduced by improper treatment during unpacking and installation. Therefore, in the interest of your own safety and of the correct operation of your new Kontron product, you are requested to conform with the following guidelines.

High Voltage Safety Instructions

Warning!

All operations on this device must be carried out by sufficiently skilled personnel only.

Caution, Electric Shock!

Before installing your new Kontron product into a system always ensure that your mains power is switched off. This applies also to the installation of piggybacks.

Serious electrical shock hazards can exist during all installation, repair and maintenance operations with this product. Therefore, always unplug the power cable and any other cables which provide external voltages before performing work.

Special Handling and Unpacking Instructions

ESD Sensitive Device!

Electronic boards and their components are sensitive to static electricity. Therefore, care must be taken during all handling operations and inspections of this product, in order to ensure product integrity at all times.

Do not handle this product out of its protective enclosure while it is not used for operational purposes unless it is otherwise protected.

P R E L I M I N A R Y

Whenever possible, unpack or pack this product only at EOS/ESD safe work stations. Where a safe work station is not guaranteed, it is important for the user to be electrically discharged before touching the product with his/her hands or tools. This is most easily done by touching a metal part of your system housing.

It is particularly important to observe standard anti-static precautions when changing piggybacks, ROM devices, jumper settings etc. If the product contains batteries for RTC or memory backup, ensure that the board is not placed on conductive surfaces, including anti-static plastics or sponges. They can cause short circuits and damage the batteries or conductive circuits on the board.

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Preface CP6500-V

General Instructions on Usage

In order to maintain Kontron’s product warranty, this product must not be altered or modified in any way. Changes or modifications to the device, which are not explicitly approved by Kontron Modular Computers GmbH and described in this manual or received from Kontron Modular Computers’ Technical Support as a special handling instruction, will void your warranty.

This device should only be installed in or connected to systems that fulfill all necessary technical and specific environmental requirements. This applies also to the operational temperature range of the specific board version, which must not be exceeded. If batteries are present, their temperature restrictions must be taken into account.

In performing all necessary installation and application operations, please follow only the instructions supplied by the present manual.

Keep all the original packaging material for future storage or warranty shipments. If it is necessary to store or ship the board, please re-pack it as nearly as possible in the manner in which it was delivered.

Special care is necessary when handling or unpacking the product. Please consult the special handling and unpacking instruction on the previous page of this manual.

P R E L I M I N A R Y

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CP6500-V Preface

Two Year Warranty

Kontron Modular Computers GmbH grants the original purchaser of Kontron’s products a TWO

YEAR

LIMITED HARDWARE WARRANTY as described in the following. However, no other warran-

ties that may be granted or implied by anyone on behalf of Kontron are valid unless the consumer has the express written consent of Kontron Modular Computers GmbH.

Kontron Modular Computers GmbH warrants their own products, excluding software, to be free from manufacturing and material defects for a period of 24 consecutive months from the date of purchase. This warranty is not transferable nor extendible to cover any other users or longterm storage of the product. It does not cover products which have been modified, altered or repaired by any other party than Kontron Modular Computers GmbH or their authorized agents. Furthermore, any product which has been, or is suspected of being damaged as a result of negligence, improper use, incorrect handling, servicing or maintenance, or which has been damaged as a result of excessive current/voltage or temperature, or which has had its serial number(s), any other markings or parts thereof altered, defaced or removed will also be excluded from this warranty.

If the customer’s eligibility for warranty has not been voided, in the event of any claim, he may return the product at the earliest possible convenience to the original place of purchase, together with a copy of the original document of purchase, a full description of the application the product is used on and a description of the defect. Pack the product in such a way as to ensure safe transportation (see our safety instructions).

Kontron provides for repair or replacement of any part, assembly or sub-assembly at their own discretion, or to refund the original cost of purchase, if appropriate. In the event of repair, refunding or replacement of any part, the ownership of the removed or replaced parts reverts to Kontron Modular Computers GmbH, and the remaining part of the original guarantee, or any new guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired items. Any extensions to the original guarantee are considered gestures of goodwill, and will be defined in the “Repair Report” issued by Kontron with the repaired or replaced item.

Kontron Modular Computers GmbH will not accept liability for any further claims resulting directly or indirectly from any warranty claim, other than the above specified repair, replacement or refunding. In particular, all claims for damage to any system or process in which the product was employed, or any loss incurred as a result of the product not functioning at any given time, are excluded. The extent of Kontron Modular Computers GmbH liability to the customer shall not exceed the original purchase price of the item for which the claim exists.

Kontron Modular Computers GmbH issues no warranty or representation, either explicit or implicit, with respect to its products’ reliability, fitness, quality, marketability or ability to fulfil any particular application or purpose. As a result, the products are sold “as is,” and the responsibility to ensure their suitability for any given task remains that of the purchaser. In no event will Kontron be liable for direct, indirect or consequential damages resulting from the use of our hardware or software products, or documentation, even if Kontron were advised of the possibility of such claims prior to the purchase of the product or during any period since the date of its purchase.

P R E L I M I N A R Y

Please remember that no Kontron Modular Computers GmbH employee, dealer or agent is authorized to make any modification or addition to the above specified terms, either verbally or in any other form, written or electronically transmitted, without the company’s consent.

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Preface CP6500-V

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CP6500-V Introduction

Chapter 1

Introduction

P R E L I M I N A R Y

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Introduction CP6500-V

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CP6500-V Introduction

1. Introduction

1.1 System Overview

The CompactPCI board described in this manual operates with the PCI bus architecture to support additional I/O and memory-mapped devices as required by various industrial applications. For detailed information concerning the CompactPCI standard, please consult the complete Peripheral Component Interconnect (PCI) and CompactPCI Specifications. For further information regarding these standards and their use, visit the home page of the

PCI Industrial Computer Manufacturers Group (PICMG).

Many system-relevant CompactPCI features that are specific to Kontron Modular Computers CompactPCI systems may be found described in the Kontron CompactPCI System Manual. Due to its size, this manual cannot be downloaded via the internet. Please refer to the section “Related Publications” at the end of this chapter for the relevant ordering information.

The CompactPCI System Manual includes the following information:

• Common information that is applicable to all system components, such as safety information, warranty conditions, standard connector pinouts etc.

• All the information necessary to combine Kontron’s racks, boards, backplanes, power supply units and peripheral devices in a customized CompactPCI system, as well as configuration examples.

• Data on rack dimensions and configurations as well as information on mechanical and electrical rack characteristics.

• Information on the distinctive features of Kontron CompactPCI boards, such as functionality, hot swap capability. In addition, an overview is given for all existing Kontron CompactPCI boards with links to the relating data sheets.

• Generic information on the Kontron CompactPCI backplanes, such as the slot assignment, PCB form factor, distinctive features, clocks, power supply connectors and signalling environment, as well as an overview of the Kontron CompactPCI standard backplane family.

• Generic information on the Kontron CompactPCI power supply units, such as the input/ output characteristics, redundant operation and distinctive features, as well as an overview of the Kontron CompactPCI standard power supply unit family.

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Introduction CP6500-V

1.2 Board Overview

1.2.1 Board Introduction

The CP6500-V is a highly integrated CompactPCI board that has been designed to support the

Celeron® processor, which is based on the same core as existing mobile processors. The

Intel CP6500-V utilizes the Intel 815-B0 chipset and the ICH4 I/O Controller Hub. The CPU speed ranges from 400 MHz through 1 GHz.

To achieve high system performance, the board supports one SODIMM socket for a flexible memory configuration, up to 512 MB SDRAM memory without Error Checking and Correcting (ECC).The CP6500-V supports memory speed up to 100 MHz.

The CP6500-V comes with two Fast Ethernet ports, two USB 2.0 ports, two COM ports, two EIDE interfaces, one PMC interface with 32-bit/33 MHz on the PCI bus (in accordance with the PICMG 2.3 specification), a Low Pin Count interface (LPC), rear I/O with several interfaces, one CompactFlash socket, and a built-in Intel 3D Graphics accelerator with a VGA CRT display interface. Several onboard connectors provide flexible expendability.

The board supports a configurable 32-bit/33 MHz, hot swap CompactPCI interface. In the System Master slot the interface is enabled, and if installed in a peripheral slot, the CP6500-V is isolated from the CompactPCI bus.

One of the more important features of the CP6500-V is its support of the PICMG CompactPCI Packet Switching Backplane Specification 2.16. When installed in a backplane which supports packet switching, the CP6500-V can communicate via two Fast Ethernet interfaces with other peripherals.

The board is offered with the Microsoft Embedded operating systems. Kontron further supports, as a standard, Linux and VxWorks Please contact Kontron Modular Computers for further information concerning other operating systems.

Windows® 2000, Windows® XP and Windows® XP

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CP6500-V Introduction

1.2.2 Board-Specific Information

The CP6500-V is a CompactPCI Celeron based single-board computer specifically designed for use in highly integrated platforms with solid mechanical interfacing for a wide range of industrial environment applications.

Some of the CP6500-V's outstanding features are:

• Intel Celeron microprocessor

• 479-pin µFCBGA package

• Up to 256 kB L2 cache on-die, running at CPU speed

• 100 MHz or 133 MHz processor system bus

• 815-B0 chipset

• Up to 512 MB SDRAM memory

• Integrated 3D VGA controller

• Analog display support up to 1600 x 1200 pixels at 8-bit and 75 Hz

• PMC interface (32-bit/33 MHz PCI, 3.3 V and 5 V) with rear I/O support and bezel cutout on front panel and PCI functionality

• Two Fast Ethernet interfaces on the front panel switchable to rear I/O (PICMG 2.16)

• Two EIDE Ultra ATA/100 interfaces

• Optional socket for 2.5" hard disk

• Onboard CompactFlash type II socket (True IDE)

• Four USB ports

• Two USB 2.0 ports on the front panel

• Two USB 2.0 ports on rear I/O

• 1 MB onboard FWH for BIOS

• Hardware monitor integrated in Windbond Super I/O W83627HF

• Floppy disk interface on rear I/O

• One 32-bit PCI-to-PCI bridge at 33 MHz

• Watchdog timer

• Real-time clock

• Two COM ports

• one switchable to front or rear I/O with RS232 or RS422

• one only for rear I/O with RS232/RS422/RS485

• POST code or general purpose LEDs (Front-I and Front-II)

• I/O extension connector (LPC)

• 4HP, 6U CompactPCI

• Passive heat sink solution for external airflow

•AMI BIOS

• Compatible with CompactPCI spec. Rev. 2.3 (32-bit/33 MHz)

• Hot swap capability: as system controller or as peripheral device

• Supports PICMG Packet Switching Backplane Specification 2.16

• Several rear I/O configurations

• Rear I/O on J3, J4,and J5

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Introduction CP6500-V

1.3 System Expansion Capabilities

1.3.1 PMC Modules

The CP6500-V has one PCI, 32-bit/33 MHz, 3.3 V or 5 V, rear I/O capable, PMC mezzanine interface. This interface supports a wide range of available PMC modules with PCI interface including all of Kontron’s PMC modules and provides an easy and flexible way to configure the CP6500-V for various application requirements.

1.3.2 CP-CTM80-2 Rear I/O Module

The CP-CTM80-2 rear I/O module has been designed for use with the CP6500-V 6U CompactPCI board from Kontron Modular Computers. This module provides comprehensive rear I/O functionality and may also be configured for use in other applications.

Note ...

The CP-CTM80-2 rear I/O module provides only USB 1.1 ports.

For further information concerning the CP-CTM80-2 module, please refer to Appendix A.

1.4 System Relevant Information

The following system relevant information is general in nature but should still be considered when developing applications using the CP6500-V.

Table 1-1: System Relevant Information

SUBJECT INFORMATION

System Slot/System Master Functionality

Peripheral Slot Functionality

P R E L I M I N A R Y

Hot Swap Compatibility

The CP6500-V is designed for use as a System Master board whereby it can support up to 7 peripheral boards with 32-bit/ 33 MHz.

It may, however, be operated in a peripheral slot in which case it does not support the CompactPCI bus interface.

When installed in a peripheral slot, the CP6500-V is electrically isolated from the CompactPCI bus. It receives power from the backplane and supports rear I/O and, if the system supports it, packet switching (in this case up to two channels of Fast Ethernet).

When operated as a System Master, the CP6500-V supports individual clocks for each slot and ENUM signal handling is in compliance with the PICMG 2.1 Hot Swap Specification.

When operated in a peripheral slot the CP6500-V supports basic hot swap.

Operating Systems

The CP6500-V can be operated under the following operating systems:

• Microsoft Windows 2000

• Microsoft Windows XP

• Microsoft Windows XP Embedded

• Linux

• VxWorks Please contact Kontron Modular Computers for further information concerning other operating systems.

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CP6500-V Introduction

1.5 Board Diagrams

The following diagrams provides additional information concerning board functionality and component layout.

1.5.1 Functional Block Diagram

Figure 1-1: CP6500-V Functional Block Diagram

144-pin SDRAM

up to 512 MB

100 MHz

CPCI

Floppy

EIDE Secondary

COM1

9-pin

VGA CRT

Tem p.

Monitor

Power

Supply

BIOS FWH 1 MB

100 MHz/ 133 MHz

Keyboard

GMCH

815-B0

ULV/LV Celeron

Super

I/O

LPC

I/O

Ext.

Floppy

ICH4

I/O Hub

CompactFlash

type I an d II

2.5” HDD

Primary EIDE

EIDE

Secondary EIDE

RTC

USB 2.0

4-pin

USB 2.0

4-pin

Local PMC

32-bit/33 MHz

Fast Ethernet 82551ER

PCI-to-PCI

Bridge

Ethernet

RJ45

Onboard ConnectorsBus ConnectorsFront Panel ConnectorsCPU

CPCI

J1/J2 CPCI

Hot Swap

Ethernet

RJ45

PMC REAR I/O

VGA COM1/2 KB/Mouse USB3/4 2.0 PICMG 2.16

CPCI 32-bit/33 MH z Hotswap

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Introduction CP6500-V

1.5.2 Front Panels

Figure 1-2: CP6500-V 4 HP Front Panel

Legend:

General Purpose LEDs

WD (green): Watchdog, when lit during boot-up,

it indicates a PCI reset is active.

TH (green): Overtemperature Status, when lit

during boot-up, it indicates a power failure.

HS (blue): Hot Swap Control

Front-I: General Purpose or POST code

Front-II: General Purpose or POST code

Integral Ethernet LEDs

ACT (green): Ethernet Link/Activity

SPEED (green/orange): Ethernet Speed

SPEED ON (orange): 100 Mbit

SPEED ON (green): 10 Mbit

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CP6500-V Introduction

1.5.3 Board Layout

Figure 1-3: CP6500-V Board Layout (Top View)

J10

J12

CompactFlash

J16 J17

FWH

J18 J21

J23 J25

J22

Socket

SDRAM Socket

63 64

J24

63 64

J20

815-B0

39 40

2 1

J19

1 2

44 43

WD/TH LEDs

POST

CODE

LEDs

HS LED & RST

J11

CPU

Battery

Fast

Eth.

Fast

Eth.

ICH4

P R E L I M I N A R Y

PCI-to-

PCI

Bridge

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Introduction CP6500-V

Figure 1-4: CP6500-V Board Layout (Bottom View)

COM2

COM1

JP7

JP8

JP3

JP5

R329

JP4

JP6

R320

R330

R311

JP1

R218

R215

R199

P R E L I M I N A R Y

C63

C224

C64

C205

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CP6500-V Introduction

1.6 Technical Specification

Table 1-2: CP6500-V Main Specifications

CP6500-V SPECIFICATIONS

CPU

Memory Main Memory:

Processor and Memory

Intel 815-B0 GMCH 815-B0 Graphics Memory Controller Hub (GMCH)

The CP6500-V supports the following microprocessors:

• Intel Celeron with 256 kB L2 cache

• 400 MHz version with 100 MHz PSB in 479 µFCBGA

• 1.0 GHz version with 133 MHz PSB in 479 µFCBGA

• Up to 512 MB SDRAM memory without ECC via one 144-pin SODIMM

socket running at 100 MHz

Cache structure:

• 32 kB L1 on-die full speed processor cache

• 16 kB for instruction cache

• 16 kB for write-back data cache

• Up to 256 kB L2 on-die full speed processor cache

FLASH Memory:

• 8 Mbit Firmware Hub (FWH) for BIOS

Memory Extension:

• CompactFlash socket type II (true IDE mode with DMA capability)

Serial EEPROM:

• 24LC64 (8 kB) for storing CMOS data when operating without battery

• Support for a single Celeron microprocessor

• 64-bit AGTL-based System Bus interface at 100 MHz for 400 MHz pro-

cessor and 133 MHz for 1GHz processor

• 64-bit System Memory interface with support for SDRAM memory at

100 MHz

• Integrated 2D and 3D Graphics Engines

• Integrated H/W Motion Compensation Engine

• Integrated 230 MHz DAC

Intel ICH4 Chipset Intel ICH4 I/O Controller Hub

Chipsets

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• PCI Rev. 2.2 compliant with support for 32-bit/33 MHz PCI operations

• Power management logic support

• Enhanced DMA controller, interrupt controller, and timer functions

• Integrated IDE controller Ultra ATA/100/33

• USB 2.0 host interface with up to four USB ports available on the

CP6500-V

• System Management Bus (SMBus) compatible with most I²C™ devices

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

P R E L I M I N A R Y

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Introduction CP6500-V

Table 1-2: CP6500-V Main Specifications (Continued)

CP6500-V SPECIFICATIONS

CompactPCI

Compliant with CompactPCI Specification PICMG

2.0 R 3.0

• System Master operation

• 32-bit / 33 MHz master interface

• 3.3 V and 5.0 V compliant (default configuration: 5V)

When the CP6500-V is operated in a peripheral slot, the CPCI bus is electrically isolated (passive mode).

Rear I/O The following interfaces are routed to the rear I/O connector J3, J4 and J5:

• COM1 and COM2 (RS232, RS422 and RS485 signaling); no buffer on the

rear I/O module is necessary

• 2 x USB 2.0

• CRT VGA

• PS/2 (Mouse / Keyboard)

• 2 x Fast Ethernet (compliant with PICMG 2.16, R 1.0)

• Secondary EIDE (ATA 100)

• General purpose signals

• PMC rear I/O

• Floppy disk interface

Hot Swap Compatible

The CP6500-V supports System Master hot swap functionality and application dependent hot swap functionality when used in a peripheral slot.

When used as a System Master the CP6500-V supports individual clocks for each slot and ENUM signal handling is in compliance with the PICMG 2.1 Hot Swap Specification, Rev. 2.0, January 17, 2001.

VGA Built-in Intel 2D and 3D Graphics accelerator:

• Supports resolutions of up to 1600 x 1200 by 8-bit color resolution at a 75 Hz

Interfaces

refresh rate or up to 1280 x 1024 by 24-bit color resolution at an 85 Hz refresh rate.

• Hardware motion compensation for software MPEG2 and MPEG4 decoding

• The graphics controller provides flexible allocation of video memory up to

6MB.

Fast Ethernet Up to two 10 Base-T/100 Base-TX Fast Ethernet interfaces based on the Intel

82551ER Ethernet 32-bit PCI bus controller.

P R E L I M I N A R Y

• Two channels on rear I/O

• Two RJ45 connectors on the front panel

• Automatic mode recognition

• Automatic cabling configuration recognition

Cabling requirement: Category 5, UTP

USB Four USB ports supporting UHCI and EHCI:

• Two USB 2.0 connectors on the front panel

• Two USB 2.0 on the rear I/O interface

Serial Two serial ports from Super I/O

• COM1 on the front panel or rear I/O

• COM2 on the rear I/O interface (RS232, RS422 and RS485 signaling)

PMC CMC/ PMC P1386 / Draft 2.4a compliant mezzanine interface

• J23, J24, and J25 PCI mezzanine connectors for standard PMC modules

• 32-bit / 33 MHz PCI interface

• 3.3 V and 5 V compatible (default configuration 5V)

• Rear I/O supported through the CompactPCI connector J4

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CP6500-V Introduction

Table 1-2: CP6500-V Main Specifications (Continued)

CP6500-V SPECIFICATIONS

Keyboard and Mouse Keyboard and mouse are supported

• USB Support

• PS/2 (keyboard and mouse) with rear I/O module (e.g. CP-CTM80-2)

• Separate onboard keyboard connector (5-pin) that requires an adapter in

order to be connected to a regular keyboard

Mass Storage EIDE Ultra ATA/100/33:

• Two interfaces:

• One 44-pin, 2.0 mm male pinrow connector for onboard HDD

• One 40-pin, 2.54 mm, male pinrow connector

• Up to four devices (hard disks or CD-ROMs)

Onboard 2.5" hard disk:

Interfaces

• Onboard 2.5" hard disk can be mounted to the 44-pin connector

CompactFlash:

• CompactFlash type II socket (true IDE mode with DMA capability)

• Supports type I and II CompactFlash cards and Microdrive

Floppy Disk (only with rear I/O module):

• Supports 5.25" or 3.5 " floppy drives

• 1.2 or 1.44 MB, 3.5" floppy disks

I/O Extension Interface

I/O extension interface

• LPC devices

Front Panel Connectors

• VGA: 15-pin, D-SUB connector

• USB: two 4-pin connectors

• Ethernet: up to two RJ-45 connectors

• COM: 9-pin, D-SUB connector

• PMC front panel

Onboard Connectors

• Two EIDE interfaces supporting Ultra ATA/100/33

• one 44-pin, 2.0 mm connector

Sockets

• one 40-pin, 2.54 mm connector

• CompactFlash socket type II (primary EIDE interface)

• I/O extension connector

• PMC interface (connector Jn1 - Jn4)

• CompactPCI Connector J1 and J2 (J3 - J5 optional)

• 5-pin PS/2 connector (keyboard)

• 144-pin SODIMM connector

Mechanical 6U, 4HP, CompactPCI compliant form factor

Power Consumption See Chapter 5 for details

Temperature Range Operational: 0°C to 60°C

Storage: -55°C to +85°C Without hard disk

Climatic Humidity 93% RH at 40 °C, non-condensing (acc. to IEC 60068-2-78)

P R E L I M I N A R Y

Dimensions 233.35 mm x 160 mm

General

Board Weight 443 g (with standard heat sink and without mezzanine boards)

Battery 3.0 V lithium battery for RTC with battery socket. Recommended types:

• VARTA CR2025

• PANASONIC BR2020

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Introduction CP6500-V

Table 1-2: CP6500-V Main Specifications (Continued)

CP6500-V SPECIFICATIONS

LEDs System status:

• TH (green): Overtemperature Status, when remains lit during boot-up, it indicates a power failure.

• WD (green): Watchdog, when remains lit during boot-up, it indicates a PCI reset is active.

Fast Ethernet status:

• ACT (green): network activity

• SPEED (green/ orange): network speed

General Purpose LEDs:

• I (green): General Purpose or POST code

• II (green): General Purpose or POST code

Watchdog Software configurable two-stage watchdog with programmable timeout ranging

HW Monitoring

from 125 msec to 256 sec in 12 steps generates IRQ, NMI, or hardware reset.

Thermal Management CPU overtemperature protection is provided by:

• CPU shut down via hardware monitor

• Custom-designed heat sinks

System Monitor Integrated HW monitoring in Winbond Super I/O W83627HF for the supervision

of:

• Several system power voltages

• Two fan speed input

• CPU and system temperature

Software BIOS

AMI BIOS with 1 MB of Flash memory and having the following features:

• QuickBoot

QuietBoot

•

• BootBlock

• LAN boot capability for diskless systems (standard Etherboot / PXE on

demand)

• Boot from USB devices

P R E L I M I N A R Y

• BIOS boot support for USB keyboards

• Plug and Play capability

• BIOS parameters are saved in the EEPROM

Software

• Board serial number is saved within the EEPROM

• PC Health Monitoring

• ACPI

Operating Systems Operating systems supported:

• Microsoft Windows 2000

• Microsoft Windows XP

• Microsoft Windows XP Embedded

• Linux

• VxWorks

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CP6500-V Introduction

1.7 Applied Standards

The Kontron Modular Computers’ CompactPCI systems comply with the requirements of the following standards:

Table 1-3: Applied Standards

COMPLIANCE TYPE STANDARD

CE Emission EN55022

EN61000-6-3

Immission EN55024

EN61000-6-2

Electrical Safety EN60950 --

Mechanical Mechanical Dimensions IEEE 1101.10 --

Environmental and Health Aspects

Vibration (Sinusoidal) IEC60068-2-6

Shock IEC60068-2-27 30 [g]

Bump IEC60068-2-29 15 [g]

TEST LEVEL

(RUGGEDIZED VERSION)

10-300 [Hz] 2 [g] 1 [oct/min] 10 cycles/axis

3 axes

9 [ms] 3 shocks per direction 6 directions 5 [s] recovery time

11 [ms] 500 bumps per direction 6 directions 1 [s] recovery time

Vibration, broad-band random (digital control) and guidance

Climatic Humidity IEC60068-2-78 93% RH at 40 °C, non-condensing

WEEE Directive 2002/96/EC Waste electrical and electronic

RoHS Directive 2002/95/EC Restriction of the use of certain

IEC 60068-2-64

20-500Hz, 0.05[g²] 500-2000Hz, 0.005[g²] 3,5 [g RMS] 30 [min] test time/axis 3 axes

equipment

hazardous substances in electrical and electronic equipment

P R E L I M I N A R Y

Note ...

The values in the above table are valid for boards which are ordered with the ruggedized service. For more information, please contact your local Kontron office.

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Introduction CP6500-V

1.8 Kontron Software Support

Kontron is one of the few CompactPCI and VME manufacturers providing inhouse support for most of the industry-proven real-time operating systems that are currently available. Due to its close relationship with the software manufacturers, Kontron is able to produce and support BSPs and drivers for the latest operating system revisions thereby taking advantage of the changes in technology.

Finally, customers possessing a maintenance agreement with Kontron can be guaranteed hotline software support and are supplied with regular software updates. A dedicated web site is also provided for online updates and release downloads.

1.9 Related Publications

The following publications contain information relating to this product.

Table 1-4: Related Publications

PRODUCT PUBLICATION

CompactPCI Systems and Boards

CompactFlash Cards CF+ and CompactFlash Specification Revision 1.4

CompactPCI Specification 2.0, Rev. 3.0

CompactPCI Packet Switching Backplane Specification PICMG 2.16 Rev. 2.0 CompactPCI System Management Specification PICMG 2.9 Rev. 1.0 CompactPCI Hot Swap Specification PICMG 2.1 Rev. 2.0

Hot Swap Specification PICMG 2.1

Kontron Modular Computers’ CompactPCI System Manual, ID 19954

P R E L I M I N A R Y

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CP6500-V Functional Description

Chapter 1

Functional Description

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CP6500-V Functional Description

2. Functional Description

2.1 CPU, Memory and Chipset

2.1.1 CPU

The CP6500-V supports all low voltage Intel Celeron processors with the Tualatin core up to speeds of 1 GHz. Tualatin is the code name for Celeron chips manufactured using Intel’s 0.13 micron process.

The following list sets out some of the key features of this processor:

• Supports Intel Architecture with Dynamic Execution

• Low-power core

• On-die, primary 16 kB instruction cache and 16 kB write-back data cache

• On-die, second level cache with Advanced Transfer Cache Architecture

• Intel Celeron with 256 kB L2 cache

• Advanced Branch Prediction and Data Prefetch Logic

• Streaming SIMD Extensions (SSE)

• 100 MHz PSB (Source-Synchronous processor system bus) for 400 MHz processor

• 133 MHZ PSB for 1 GHz processor

The following tables provide information on the Intel Celeron processor supported on the CP6500-V and its maximum power dissipation.

Table 2-1: Supported Intel Celeron Processors on the CP6500-V

SPEED 400 MHz 1.0 GHz

PACKAGE µFCBGA µFCBGA

L2 CACHE 256 kB 256 kB

CORE VOLTAGE 0.95 V 1.15 V

PROCESSOR

SIDE BUS

Table 2-2: Maximum Power Dissipation of Intel Celeron (CPU only)

FREQUENCY MODE 400 GHz 1.0 GHz

Maximum Power 4.2 W 12.4 W

100 MHz 133 MHz

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Functional Description CP6500-V

2.1.2 Memory

The CP6500-V has one SODIMM socket without ECC for installing memory and supports a maximum of 512 MB. All installed memory will be automatically detected by the Serial Presence Detect (SPD) EEPROM, so there is no need to set any jumpers. The CP6500-V supports all PC100- and PC133-compliant SDRAMs on 144-pin SODIMM without ECC offered by Kontron Modular Computers. The SODIMM used with this board must comply with the PC Serial Presence Detect Specification.

Only qualified SDRAMs from Kontron Modular Computers ca be used with the CP6500-V.

2.1.3 815-B0 Chipset Overview

The Intel 815-B0 chipset consists of the following devices:

• 815-B0 Graphics and Memory Controller Hub (GMCH) with Accelerated Hub Architecture (AHA) bus

• 82801 I/O Controller Hub (ICH4)

• Firmware Hub (FWH)

The GMCH provides the processor interface for the Celeron microprocessor, the memory bus and includes a graphics accelerator. The ICH4 is a centralized controller for the boards’ I/O peripherals, such as the PCI, USB 2.0, and EIDE ports. The Firmware Hub (FWH) provides the non-volatile storage for the BIOS.

Figure 2-1: 815-B0 Chipset Functional Block Diagram

Intel Celeron

Processor

(100/133 FSB)

Standard

Monitor

P R E L I M I N A R Y

4 USB Ports

2 ATA 100 IDE

Channels

GMCH

82815

Intel Hub Architecture

ICH4

SODIMM

for up to 100 MHz

SDRAM

SMBus

PCI

SIO

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CP6500-V Functional Description

2.1.4 Graphics and Memory Controller Hub (815-B0)

The 815-B0 Graphics Memory Controller Hub (GMCH) is a highly integrated hub that provides the CPU interface, the SDRAM system memory interface, a hub link interface to the ICH4 and an internal graphics.

Graphics and Memory Controller Hub Feature Set

Host Interface

The 815-B0 is optimized for the Intel sor Side Bus (PSB) frequency of up to 133 MHz using 1.25 V AGTL signalling. Single-ended AGTL termination is supported for single-processor configurations. The AGTL bus supports 32-bit host addressing for decoding up to 4 GB memory address space.

System Memory Interface

The 815-B0 integrates a system memory SDRAM controller with a 64-bit wide interface without ECC. The chipset supports Single Data Rate (SDR) SDRAM for system memory with 64 Mbit, 128 Mbit, 256 Mbit and 512 Mbit SDRAM devices.

815-B0 Graphics Controller

The 815-B0 includes a highly integrated graphics accelerator decoding delivering high performance 3D and 2D video capabilities. The internal graphics controller provides interfaces for a standard progressive scan monitor, TV-Out device, and TMDS transmitter. These interfaces are only active when running in internal graphics mode.

The advantage of the internal graphics solution is the price, the integration reduces the number of the components and design complexity.

The disadvantage of the internal graphics controller is the shared memory architecture, which results in a lower memory performance for the processor. To avoid memory conflicts with the processor, the maximum VGA resolution is limited to 1600 x 1200 pixel with 256 colors and 60 Hz.

Celeron microprocessor. The chipset supports a Proces-

2.1.5 I/O Controller Hub ICH4

The ICH4 is a highly integrated multifunctional I/O Controller Hub that provides the interface to the PCI Bus, and integrates many of the functions needed in today's PC platforms, such as Ultra DMA 100/33 controller, USB host controller supporting USB 2.0, LPC interface and FWH Flash BIOS interface controller. The ICH4 communicates with the host controller over a dedicated hub interface.

The I/O Controller Hub Feature set comprises:

• PCI 2.2 interface with 32-bit/33 MHz and eight IRQ inputs

• Bus Master EIDE controller UltraDMA 100/33

• Up to four USB 2.0

• Hub interface for a 815-B0 chipset

•FWH interface

• LPC interface

• RTC controller

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Functional Description CP6500-V

2.2 Peripherals

The following standard peripherals are available on the CP6500-V board:

2.2.1 Timer

The CP6500-V is equipped with the following timers:

• Real-time clock The ICH4 contains a MC146818A compatible real-time clock with 256 bytes of batterybacked RAM. The real-time clock performs timekeeping functions and includes 256 bytes of general purpose battery-backed CMOS RAM. Features include an alarm function, programmable periodic interrupt and a 100-year calendar. All battery-backed CMOS RAM data remains stored in an additional EEPROM. This prevents data loss.

• Counter/Timer Three 8254-style counter/timers are included on the CP6500-V as defined for the PC/AT.

2.2.2 Watchdog Timer

A watchdog timer is provided, which forces either an IRQ5, NMI, or Reset condition (configurable in the watchdog register). The watchdog time can be programmed in 12 steps ranging from 125 msec up to 256 seconds. If the watchdog timer is enabled, it cannot be stopped.

2.2.3 Battery

The CP6500-V is provided with a 3.0 V “coin cell” lithium battery for the RTC.

To replace the battery, proceed as follows:

• Turn off power

• Remove the battery

• Place the new battery in the socket.

• Make sure that you insert the battery the right way round. The plus pole must be on the top!

The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. Suitable batteries include the VARTA CR2025 and PANASONIC

P R E L I M I N A R Y

BR2020.

Note ...

Care must be taken to ensure that the battery is correctly replaced.

The battery should be replaced only with an identical or equivalent type recommended by the manufacturer.

Dispose of used batteries according to the manufacturer’s instructions.

The typical life expectancy of a 170 mAh battery (VARTA CR2025) is 5 - 6 years with an average on-time of 8 hours per working day at an operating temperature of 30°C. However, this typical value varies considerably because the life expectancy is dependent on the operating temperature and the standby time (shutdown time) of the system in which it operates.

To ensure that the lifetime of the battery has not been exceeded, it is recommended to exchange the battery after 4 - 5 years.

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2.2.4 Reset

The CP6500-V is automatically reset by a precision voltage monitoring circuit that detects a drop in voltage below the acceptable operating limit of 4.85 V for the 5 V line and below 500 mV for the 3.3 V line, or in the event of a power failure of the DC/DC converter. Other reset sources include the watchdog timer and the push-button switch on the front panel. The CP6500-V responds to any of these sources by initializing local peripherals.

A reset will be generated under the following conditions:

• +5 V supply falls below 4.68 V (typ.)

• +3.3 V supply falls below 3.09 V (typ.)

• Power failure of all onboard DC/DC converters

• Push-button "RESET" pressed

• Watchdog overflow

• CompactPCI backplane PRST input

2.2.5 SMBus Devices

The CP6500-V provides a System Management Bus (SMBus) for access to several system monitoring and configuration functions. The SM Bus consists of a two-wire I²C bus interface. The following table describes the function and address of every onboard SM Bus device.

Table 2-3: SM Bus Device Addresses

DEVICE SMB ADDRESS

Hardware Monitor W83627HF 0101101xb

EEPROM 24LC64 1010111xb

Clock 1101001xb

SPD 1010000xb

2.2.6 Thermal Management/System Monitoring

The W83627HF can be used to monitor several critical hardware parameters of the system, which are very important for the proper operation and stability of a high-end computer system.

The temperature sensors on the W83627HF monitor the CPU temperature and the ambient temperature around the CPU to ensure that the system is operating at a safe temperature level. If the temperature is too high, the sensors automatically reduce the CPU clock frequency, depending on the mode chosen in the BIOS set.

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Functional Description CP6500-V

2.2.7 Serial EEPROM

This EEPROM is connected to the I²C bus provided by the ICH4.

Table 2-4: EEPROM Address Map

ADDRESS FUNCTION

0 - FF CMOS backup

100 - 1FF Production data

200 - 3FF OS Boot parameter

400 - 7FF User

2.2.8 FLASH Memory

There are two flash devices available as described below, one for the BIOS and one for the CompactFlash socket.

2.2.8.1 BIOS FLASH (Firmware Hub)

For simple BIOS updating a standard onboard 1 MB Firmware Hub device is used.

The FWH stores both the system BIOS and video BIOS. It can be updated as new versions of the BIOS become available. You may easily upgrade your BIOS using the AMI utility. For detailed information on BIOS refer to Appendix B.

2.2.8.2 CompactFlash Socket

To enable flexible flash extension, a CompactFlash (CF) type II socket, J14, with DMA support is available.

CF is a very small removable mass storage device. It is provides true IDE functionality compatible with the 16-bit ATA/ATAPI-4 interface.

The CompactFlash socket is connected to the primary EIDE port and can be set to master or slave.

Note ...

P R E L I M I N A R Y

The easiest way to remove the CompactFlash card is to affix a wide piece of adhesive tape to the top side, then pull it out and afterwards remove the tape.

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CP6500-V Functional Description

The following table provides the pinout of the CompactFlash connector J14.

Table 2-5: CompactFlash Connector J14 Pinout

I/O FUNCTION SIGNAL PIN PIN SIGNAL FUNCTION I/O

-- Ground signal GND 1 2 D03 Data 3 I/O

I/O Data 4 D04 3 4 D05 Data 5 I/O

I/O Data 6 D06 5 6 D07 Data 7 I/O

O Chip select 0 IDE_CS0 7 8 GND (A10) -- --

-- -- GND (ATASEL) 9 10 GND (A09) -- --

-- -- GND (A08) 11 12 GND (A07) -- --

-- 5 V Power VCC (5 V) 13 14 GND (A06) -- --

-- -- GND (A05) 15 16 GND (A04) -- --

-- -- GND (A03) 17 18 A02 Address 2 O

O Address 1 A01 19 20 A00 Address 0 O

I/O Data 0 D00 21 22 D01 Data 1 I/O

I/O Data 2 D02 23 24 IOCS16 -- O

-- -- NC (CD2) 25 26 NC (CD1) -- --

I/O Data 11 D11 27 28 D12 Data 12 I/O

I/O Data 13 D13 29 30 D14 Data 14 I/O

I/O Data 15 D15 31 32 IDE_CS1 Chip select 1 O

-- -- NC (VS1) 33 34 IORD I/O read O

O I/O write IOWR 35 36 VCC (5 V) Write enable --

I Interrupt INTRQ 37 38 VCC (5 V) 5 V power --

O Master/Slave CSEL (GND pull-

up)

O Reset Reset 41 42 IORDY I/O ready I

O DMA request DMARQ (INPACK) 43 44 DMACK DMA acknowl-

I/O Activity DASP LED 45 46 PDIAG ATA detection I/O

39 40 NC (VS2) -- --

edge

P R E L I M I N A R Y

I/O Data 08 D08 47 48 D09 Data 09 I/O

I/O Data 10 D10 49 50 GND -- --

2.2.9 Front Panel LEDs

The CP6500-V is equipped with two LEDs for watchdog (WD) and overtemperature (TH), eight LEDs for general purpose or POST code (four LEDs for Front-I and four LEDs for Front-II), and one LED for hot swap. Their functionality is described in the following chapters.

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Functional Description CP6500-V

2.2.9.1 Watchdog and Overtemperature LEDs

The CP6500-V provides two front LEDs for Overtemperature (TH) and Watchdog (WD) status. Additionally, if the TH LED remains on during bootup, it indicates a power failure, and if the WD LED remains on during bootup, it indicates a PCI reset is active. In this case, check the power supply. If the power supply appears to be functional and this LED remains on, contact Kontron Modular Computers’ Technical Support.

2.2.9.2 Front-I and Front-II General Purpose LEDs

These are two sets of General Purpose LEDs available on the front panel of the CP6500-V which are designed to indicate the boot-up POST code if required or are available to the application as general purpose LEDs. To indicate POST code, J22 must be set. For general purpose use, J22 must not be set. Together Front-I and Front-II indicate a two-place hexadecimal number. Front-II is the lower nibble, Front-I is the higher nibble. An one is indicated by a lit LED. The LSB is 0, the MSB is 7. Default setting is general purpose and all LEDs not lit.

2.2.9.3 Hot Swap LED

On the CP6500-V, a blue HS LED can be switched on or off by software. It may be used, for example, to indicate that the shutdown process is finished and the board is ready for extraction.

2.2.10 Keyboard/Mouse Interface

The onboard keyboard controller is 8042 software compatible.

The keyboard and mouse port is routed to the CompactPCI rear I/O interface. There is no front I/O connector available. To connect a keyboard, a separate onboard connector is available.

The mouse port is only available on the CompactPCI rear I/O interface.

The CP6500-V has a 5-pin male pinrow connector J22 for the keyboard interface.

Figure 2-2: Keyboard Connector J22

J22

P R E L I M I N A R Y

The following table provides the pinout for the keyboard connector J22.

Table 2-6: Keyboard Connector J22 Pinout

PIN SIGNAL FUNCTION I/O

1 KDATA Keyboard data I/O

2-- -- --

3 GND Ground --

4VCC VCC 5V --

5 KCLK Keyboard clock O

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CP6500-V Functional Description

2.2.11 USB Interfaces

The CP6500-V supports four USB 2.0 ports (two on the front I/O and two on the rear I/O). On the two rear I/O ports it is strongly recommended to use a cable below 3 metres in length for USB 2.0 devices. All four ports are high-speed, full-speed, and low-speed capable. High-speed USB 2.0 allows data transfers of up to 480 Mb/s - 40 times faster than a full-speed USB (USB 1.1).

One USB peripheral may be connected to each port. To connect more than four USB devices an external hub is required.

The USB power supply provides 500 mA continuous load current and 900 mA short-circuit protection.

Figure 2-3: USB Connectors J7 and J8

132

USB Connectors J7 and J8 Pinout

The CP6500-V has two USB interfaces implemented on a 4-pin connector with the following pinout:

Table 2-7: USB Connectors J7 and J8 Pinout

PIN SIGNAL FUNCTION I/O

1VCC VCC --

2 UV0- Differential USB- I/O

3 UV0+ Differential USB+ I/O

4GND GND --

Note ...

P R E L I M I N A R Y

The USB power supply to the USB connector provides a 500 mA continuous load current and 900 mA short-circuit protection. All the signal lines are EMI filtered.

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Functional Description CP6500-V

2.2.12 Graphics Controller

The 815-B0 includes an integrated graphics accelerator delivering high performance 3D, 2D video capabilities. The internal graphics controller provides interfaces to a standard progressive scan monitor. This interface is only active when running in internal graphics mode.

Integrated 2D/3D Graphics:

• 3D hyperpipelined architecture

• Full 2D hardware acceleration

• Intel 815-B0 D.V.M. Technology graphics core

• Integrated 230 MHz DAC

• Resolution up to 1600 x 1200 @ 75 Hz with 8 bits

• Integrated H/W Motion Compensation engines for software MPEG2 decode

2.2.12.1 Video Memory Usage

The 815-B0 chipset supports the new Dynamic Video Memory Technology (D.V.M.T.). This new technology ensures the most efficient use of all available memory for maximum 3D graphics performance. D.V.M.T. dynamically responds to application requirements allocating display and texturing memory resources as required.

The operating system requires a minimum of 1 MB and a maximum of 6 MB of system memory to support legacy VGA. System properties will display up to 6MB less than physical system memory available to the operating system.

The graphics driver for the Intel 815-B0 configuration will request up to 6 MB of memory from the OS. By reallocating memory to the system, memory is freed up for other applications when not needed by the graphics subsystem. Thus, efficient memory usage is ensured for optimal graphics and system memory performance.

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2.2.12.2 Video Resolution

The 815-B0 has an integrated 230 MHz RAMDAC that can directly drive a progressive scan analog monitor up to a resolution of 1600x1200 @ 75 Hz.

Table 2-8: Partial List of Display Modes Supported

BITS PER PIXEL (FREQUENCY IN HZ)

RESOLUTION

8-BIT INDEXED 16-BIT 24-BIT

320x200 70 70 70

320x240 70 70 70

352x480 70 70 70

352x576 70 70 70

400x300 70 70 70

512x384 70 70 70

640x400 70 70 70

640x480 60,70,72,75,85 60,70,72,75,85 60,70,72,75,85

720x480 75,85 75,85 75,85

720x576 60,75,85 60,75,85 60,75,85

800x600 60,70,72,75,85 60,70,72,75,85 60,70,72,75,85

1024x768 60,70,72,75,85 60,70,72,75,85 60,70,72,75,85

1152x864 60,70,72,75,85 60,70,72,75,85 60,70,72,75,85

1280x720 60,75,85 60,75,85 60,75,85

1280x960 60,75,85 60,75,85 60,75,85

1280x1024 60,70,72,75,85 60,70,72,75,85 60,70,75,85

1600x900 60,75,85 60,75,85 --

1600x1200 60,70,72,75 -- --

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Functional Description CP6500-V

2.2.12.3 CRT Interface and Connector J10

Figure 2-4: D-SUB CRT Connector J10

The 15-pin female connector J10 is used to connect a CRT monitor to the CP6500-V board.

Table 2-9: CRT Connector J10 Pinout

PIN SIGNAL FUNCTION I/O

1 Red Red video signal output O

2 Green Green video signal output O

3 Blue Blue video signal output O

4 NC Not connected --

5 GND Signal ground --

6 GND Signal ground --

7 GND Signal ground --

8 GND Signal ground --

P R E L I M I N A R Y

9 VCC Power +5V, 200 mA, no fuse protection O

10 GND Signal ground --

11 NC Not connected --

12 Sdata

13 Hsync Horizontal sync. TTL Out

14 Vsync Vertical sync. TTL Out

15 Sclk

C data

C clock

I/O

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CP6500-V Functional Description

2.2.13 COM Port

One PC compatible serial 9-pin, D-SUB port is available, which is fully compatible with the 16550 controller and includes a complete set of handshaking and modem control signals, maskable interrupt generation and data transfer of up to 460.8 kB/s.

Figure 2-5: PC-Compatible D-SUB Serial Connectors J9 (COM1)

The COM interface may be configured as either RS232 or RS422 by setting the appropriate solder jumpers. The standard setting of the COM port envisages the RS232 configuration.

RS422 configuration:

The RS422 interface uses two differential data lines RX and TX for communication (Full-Duplex).

The following table provides the pinout for the serial port connector J9, which depends on the interface configuration.

Table 2-10: Serial Port Connectors CON9 (COM1) Pinout

1 DCD +RXD

2RXD NC

RS232

(STANDARD PC)

RS422

3 TXD +TXD

4DTR NC

5GND GND

6 DSR -RXD

7RTS NC

8CTS -TXD

9RIN NC

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Functional Description CP6500-V

2.2.14 Floppy Drive Interface

The onboard floppy disk controller supports either 5.25 inch or 3.5 inch (1.44 or 2.88 MB) floppy disks. The floppy disk port is only available on the CompactPCI rear I/O interface.

2.2.15 Fast Ethernet

The CP6500-V board includes two 10Base-T/100Base-TX Fast Ethernet ports based on the Intel 82551ER Fast Ethernet PCI Controller, which is connected the PCI interface.

The Intel 82551ER Fast Ethernet Controller architecture is optimized to deliver high performance with the lowest power consumption. The controller's architecture includes independent transmit and receive queues to limit PCI bus traffic.

The Boot from LAN feature is supported.

The following figure illustrates the pinout and LED positioning of the J6A/B connector.

Figure 2-6: Dual Fast Ethernet Connector J6A/B

Fast Ethernet

J6B

J6A

Note ...

The maximum length of cabling over which the Ethernet transmission can operate effectively depends upon the transceiver in use.

The Ethernet connectors are realized as RJ45 connectors. The interfaces provide automatic

P R E L I M I N A R Y

detection and switching between 10Base-T, 100Base-TX and data transmission.

The two Fast Ethernet channels may be configured via the BIOS setting or the rear I/O configuration register for front I/O or rear I/O. The standard software configuration is front I/O.

RJ45 Connector J6A/B Pinouts

The J6A/B connector supplies the 10Base-T, 100Base-TX and interfaces to the Ethernet controller.

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CP6500-V Functional Description

Table 2-11: Pinouts of J6A/B Based on the Implementation

STANDARD ETHERNET CABLE

1OTX+OTX+

2OTX-OTX-

3IRX+IRX+

4----

5----

6IRX-IRX-

7----

8----

10BASE-T 100BASE-TX

I/O SIGNAL I/O SIGNAL

Ethernet LED Status

ACT (green): This LED monitors network connection and activity. The LED lights up when net-

work packets are sent or received through the RJ45 port. When this LED is not lit it means that either the computer is not sending or receiving network data or that the cable connection is faulty.

SPEED (green/orange): This LED lights up to indicate a successful 10Base-T or 100BASETX connection. When green it indicates a 10Base-T connection and when orange it indicates a 100Base-TX connection.

2.2.16 EIDE Interfaces

The EIDE interfaces support the following modes:

• Programmed I/O (PIO): CPU controls data transfer.

• 8237-style DMA: DMA offloads the CPU, supporting transfer rates of up to 16 MB/sec.

• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 33 MB/sec.

• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH4 ATA-100 logic can achieve read transfer rates of up to 100 MB/sec and write transfer rates up to 88 MB/sec.

Note ...

Due to the high transfer rate of ATA-100, a specialized cable which has additional grounding wires to reduce reflections, noise, and inductive coupling is required. This cable will also support all legacy IDE drives.

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Functional Description CP6500-V

Figure 2-7: EIDE Interface Connectors J19 and J20

J20

J19

There are two independent EIDE ports available. The primary port is connected to the 44-pin, 2-row male connector, J19, and to the onboard CompactFlash socket, J14. The secondary EIDE interface is a 40-pin, 2-row male connector, J20, AT standard interface for an EIDE hard disk. This interface is also available at rear I/O.

The onboard 2.5" HDD can be installed on the 44-pin connector.

Each EIDE interface provides support for two devices (one master and one slave) and the two EIDE interfaces together support a maximum of 4 devices. All hard disks can be used in cylinder head sector (CHS) mode with the BIOS also supporting the logical block addressing (LBA) mode.

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2.2.16.1 EIDE 44-Pin Connector J19

A 2.5” hard disk or Flash disk may be mounted directly onto the CP6500-V board using the optional 44-pin connector J19. The maximum length of the cable that may be used is 35 cm.

Table 2-12: Pinout of EIDE Connector J19

I/O FUNCTION SIGNAL PIN PIN SIGNAL FUNCTION I/O

O Reset HD IDERESET 1 2 GND Ground signal --

I/O HD data 7 HD7 3 4 HD8 HD data 8 I/O

I/O HD data 6 HD6 5 6 HD9 HD data 9 I/O

I/O HD data 5 HD5 7 8 HD10 HD data 10 I/O

I/O HD data 4 HD4 9 10 HD11 HD data 11 I/O

I/O HD data 3 HD3 11 12 HD12 HD data 12 I/O

I/O HD data 2 HD2 13 14 HD13 HD data 13 I/O

I/O HD data 1 HD1 15 16 HD14 HD data 14 I/O

I/O HD data 0 HD0 17 18 HD15 HD data 15 I/O

-- Ground signal GND 19 20 N/C -- --

I DMA request IDEDRQ 21 22 GND Ground signal --

O I/O write IOW 23 24 GND Ground signal --

O I/O read IOR 25 26 GND Ground signal --

I I/O channel ready IOCHRDY 27 28 GND Ground signal --

O DMA Ack IDEDACKA 29 30 GND Ground signal --

I Interrupt request IDEIRQ 31 32 IOCS16 -- O

O Address 1 A1 33 34 PDIAG Past Diagnostics I

O Address 0 A0 35 36 A2 Address 2 O

O HD select 0 HCS0 37 38 HCS1 HD select 1 O

I LED driving LED 39 40 GND Ground signal --

-- 5V power VCC 41 42 VCC 5V power --

-- Ground signal GND 43 44 VCC 5 V power --

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Functional Description CP6500-V

2.2.16.2 EIDE 40-Pin Connector J20

The following table sets out the pinout of the J20 connector, giving the corresponding signal names. The maximum length of cable the that may be used is 35 cm.

Table 2-13: Pinout of EIDE Connector J20

I/O FUNCTION SIGNAL PIN PIN SIGNAL FUNCTION I/O

O Reset HD IDERESET 1 2 GND Ground signal --

I/O HD data 7 HD7 3 4 HD8 HD data 8 I/O

I/O HD data 6 HD6 5 6 HD9 HD data 9 I/O

I/O HD data 5 HD5 7 8 HD10 HD data 10 I/O

I/O HD data 4 HD4 9 10 HD11 HD data 11 I/O

I/O HD data 3 HD3 11 12 HD12 HD data 12 I/O

I/O HD data 2 HD2 13 14 HD13 HD data 13 I/O

I/O HD data 1 HD1 15 16 HD14 HD data 14 I/O

I/O HD data 0 HD0 17 18 HD15 HD data 15 I/O

-- Ground signal GND 19 20 N/C -- --

I DMA request IDEDRQ 21 22 GND Ground signal --

O I/O write IOW 23 24 GND Ground signal --

O I/O read IOR 25 26 GND Ground signal --

I I/O channel ready IOCHRDY 27 28 GND Ground signal --

O DMA Ack IDEDACKA 29 30 GND Ground signal --

I Interrupt request IDEIRQ 31 32 N/C -- --

O Address 1 A1 33 34 ATA100 Detect ATA100 I

O Address 0 A0 35 36 A2 Address 2 O

O HD select 0 HCS0 37 38 HCS1 HD select 1 O

P R E L I M I N A R Y

I LED driving LED 39 40 GND Ground signal --

2.2.17 Extension Connector J12

The I/O extension connector provides cost-effective, flexible configuration options. To provide flexible configuration of additional low speed PC devices, e.g. Super I/O, or CAN controller, the LPC port is connected to the I/O extension connector. The I/O extension interface contains all the signals necessary to connect up to two LPC devices.

Figure 2-8: Extension Connector J12

J12

121

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CP6500-V Functional Description

2.2.18 PMC Interface

For flexible and easy configuration one onboard PMC socket is available. The Jn1 and Jn2 and Jn4 connectors provide the signals for the 32-bit PCI Bus. The PMC port supports 33 MHz. The Jn3 connector is for the 64-bit CompactPCI bus and is not populated. User defined I/O signals are supported (Jn4) and are connected to the CompactPCI rear I/O connector J4.

This interface has been designed to comply with the IEEEP1386.1 specification which defines a PCI electrical interface for the CMC (Common Mezzanine Card) form factor. The CP6500-V provides 3.3V and 5 V (default) PMC PCI signaling environment.

Figure 2-9: PMC Connectors J23, J24, and J25

J23 J25

Jn1

63 64

Jn2

J24

Jn4

63 64

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2.2.18.1 PMC Connectors J23, J24, and J25 Pinouts

Table 2-14: PMC Connectors J23 and J25 Pinouts

Jn1 (J23) Jn2 (J25)

SIGNAL PIN PIN SIGNAL SIGNAL PIN PIN SIGNAL

Signal 1 2 -12V +12V 1 2 Signal

Ground 3 4 Signal Signal 3 4 Signal

Signal 5 6 Signal Signal 5 6 Ground

BUSMODE1# 7 8 +5V Ground 7 8 Signal

Signal 9 10 Signal Signal 9 10 Signal

Ground 11 12 Signal BUSMODE2# 11 12 +3.3V

Signal 13 14 Ground Signal 13 14 BUSMODE3#

Ground 15 16 Signal +3.3V 15 16 BUSMODE4#

Signal 17 18 +5V Signal 17 18 Ground

V (I/O) 19 20 Signal Signal 19 20 Signal

Signal 21 22 Signal Ground 21 22 Signal

Signal 23 24 Ground Signal 23 24 +3.3V

Ground 25 26 Signal Signal 25 26 Signal

Signal 27 28 Signal +3.3V 27 28 Signal

Signal 29 30 +5V Signal 29 30 Ground

V (I/O) 31 32 Signal Signal 31 32 Signal

Signal 33 34 Ground Ground 33 34 Signal

Ground 35 36 Signal Signal 35 36 +3.3V

Signal 37 38 +5V Ground 37 38 Signal

Ground 39 40 Signal Signal 39 40 Ground

Signal 41 42 Signal +3.3V 41 42 Signal

Signal 43 44 Ground Signal 43 44 Ground

V (I/O) 45 46 Signal Signal 45 46 Signal

P R E L I M I N A R Y

Signal 47 48 Signal Ground 47 48 Signal

Signal 49 50 +5V Signal 49 50 +3.3V

Ground 51 52 Signal Signal 51 52 Signal

Signal 53 54 Signal +3.3V 53 54 Signal

Signal 55 56 Ground Signal 55 56 Ground

V (I/O) 57 58 Signal Signal 57 58 Signal

Signal 59 60 Signal Ground 59 60 Signal

Signal 61 62 +5V Signal 61 62 +3.3V

Ground 63 64 Signal Ground 63 64 Signal

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Table 2-15: PMC Connector J24 Pinouts

Jn4 (J24)

SIGNAL PIN PIN SIGNAL

Rear I/O 1 2 Rear I/O

Rear I/O 3 4 Rear I/O

Rear I/O 5 6 Rear I/O

Rear I/O 7 8 Rear I/O

Rear I/O 9 10 Rear I/O

Rear I/O 11 12 Rear I/O

Rear I/O 13 14 Rear I/O

Rear I/O 15 16 Rear I/O

Rear I/O 17 18 Rear I/O

Rear I/O 19 20 Rear I/O

Rear I/O 21 22 Rear I/O

Rear I/O 23 24 Rear I/O

Rear I/O 25 26 Rear I/O

Rear I/O 27 28 Rear I/O

Rear I/O 29 30 Rear I/O

Rear I/O 31 32 Rear I/O

Rear I/O 33 34 Rear I/O

Rear I/O 35 36 Rear I/O

Rear I/O 37 38 Rear I/O

Rear I/O 39 40 Rear I/O

Rear I/O 41 42 Rear I/O

Rear I/O 43 44 Rear I/O

Rear I/O 45 46 Rear I/O

Rear I/O 47 48 Rear I/O

Rear I/O 49 50 Rear I/O

Rear I/O 51 52 Rear I/O

Rear I/O 53 54 Rear I/O

Rear I/O 55 56 Rear I/O

Rear I/O 57 58 Rear I/O

Rear I/O 59 60 Rear I/O

Rear I/O 61 62 Rear I/O

Rear I/O 63 64 Rear I/O

P R E L I M I N A R Y

Note ...

The PMC rear I/O signals from Jn4 (J27) are routed to CompactPCI connector J4, whose pinout is described later in this chapter.

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2.2.19 CompactPCI Interface

The CP6500-V supports a flexibly configurable, hot swap CompactPCI interface. In the System Master slot the interface is in the transparent mode, and in the peripheral slot the CompactPCI interface is isolated so that it cannot communicate with the CompactPCI bus. This mode is known as "passive mode".

2.2.19.1 System Master Configuration

In a system slot, the CP6500-V can communicate with all other CompactPCI boards through a 32-bit/3MHz interface.

The CP6500-V supports up to seven CompactPCI loads through a passive backplane.

The CP6500-V is fully compliant with the PCI Local Bus Specification Rev. 2.2 for 32-bit/

33 MHz.

2.2.19.2 PCI-to-PCI Bridge

The Texas Instruments® PCI2050BI bridge is a 32-bit 33 MHz PCI-to-PCI bridge device. It supports up to seven CompactPCI loads through a passive backplane.

The PCI2050I is a second generation PCI-to-PCI bridge and is fully compliant with the PCI Local Bus Specification Rev. 2.2.

The PCI-to-PCI bridge allows the primary and secondary PCI bus to operate concurrently. A master and target on the same PCI bus can communicate while the other PCI bus is busy.

2.2.19.3 Peripheral Master Configuration (Passive Mode)

In a peripheral slot, the board receives power but does not communicate on the CompactPCI bus; all CompactPCI signals are isolated.

In this configuration, the communication is achieved via the two Fast Ethernet ports as defined in the PICMG 2.16 specification. In the passive mode, the board may be hot-swapped.

2.2.19.4 Packet Switching Backplane (PICMG 2.16)

The CP6500-V supports a dual Fast Ethernet link port (Node) on the J6 connector in accordance with the CompactPCI Packet Switching Backplane Specification PICMG 2.16, Version

1.0. The two nodes are connected in the chassis via the CompactPCI Packet Switching back-

P R E L I M I N A R Y

plane to the Fabric slots "A" and "B".

The PICMG 2.16 feature can be used in the system slot and in the peripheral slot.

2.2.19.5 Hot Swap Support

To ensure that a board may be removed and replaced in a working bus without disturbing the system, the following additional features are required:

• Power ramping

• Precharge

• Hot swap control and status register bits

• Automatic interrupt generation whenever a board is about to be removed or replaced

• An LED to indicate that the board may be safely removed

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2.2.19.6 Power Ramping

On the CP6500-V a special hot swap controller is used to ramp up the onboard supply voltage. This is done to avoid transients on the +3.3V, +5V, +12V and -12V power supplies from the hot swap system. When the power supply is stable, the hot swap controller generates an onboard reset to put the board into a definite state.

2.2.19.7 Precharge

Precharge is provided on the CP6500-V by a resistor on each signal line (PCI bus), connected to a +1V reference voltage.

2.2.19.8 Handle Switch

A microswitch is situated in the extractor handle. Opening the handle initiates the generation of a local interrupt (produced by the onboard logic). The microswitch is routed to J11 on the board.

2.2.19.9 ENUM# Interrupt

The onboard logic generates a low active interrupt signal to indicate that the board is about to be extracted from the system or inserted into the system. This interrupt is only generated in the peripheral master configuration. In system master configuration the ENUM signal is an input.

2.2.19.10 Hot Swap LED

On the CP6500-V a blue HS LED can be switched on or off by software. It may be used, for example, to indicate that the shutdown process is finished and the board is ready for extraction.

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2.2.20 CompactPCI Bus Connector

Figure 2-10: CompactPCI Connectors J1-J5

The complete CompactPCI connector configuration comprises five connectors named J1 to J5. Their functions are as follows:

• J1/J2: 32-bit CompactPCI interface with PCI bus signals, arbitration, clock and power

• J3, J4 and J5 have rear I/O interface functionality

• J4 only has optional rear I/O functionality from the PMC module

The CP6500-V is designed for a CompactPCI bus architecture. The CompactPCI standard is electrically identical to the PCI local bus. However, these systems are enhanced to operate in rugged industrial environments and to support multiple slots.

2.2.20.1 CompactPCI Connector Keying

CompactPCI connectors support guide lugs to ensure a correct polarized mating. A proper mating is further assured by the use of color coded keys for 3.3V and 5V operation.

Color coded keys prevent inadvertent installation of a 5V peripheral board into a 3.3V slot. The CP6500-V board is a 5V version. Backplane connectors are always keyed according to the signaling (VIO) level. Coding key colors on J1 are defined as follows:

Table 2-16: Coding Key Colors on J1

SIGNALING VOLTAGE KEY COLOR

3.3V Cadmium Yellow

5V Brilliant Blue

Universal board (5V and 3.3V) None

To prevent plugging a 5V CP6500-V version into a 3.3V VI/O backplane slot, a blue key is installed in J1.

To prevent plugging the CP6500-V into an H.110 backplane slot, a

P R E L I M I N A R Y

brown key is installed in J4.

Note: Pinrows

F and Z are

GND pins

DEFCBAZ

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2.2.20.2 CompactPCI Connectors J1 and J2 Pinouts

The CP6500-V is provided with two 2 mm x 2 mm pitch female CompactPCI bus connectors, J1 and J2.

Table 2-17: CompactPCI Bus Connector J1 System Slot Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

25 GND 5V REQ64# ENUM# 3.3V 5V GND

24 GND AD[1] 5V V(I/O) AD[0] ACK64# GND

23 GND 3.3V AD[4] AD[3] 5V AD[2] GND

22 GND AD[7] GND 3.3V AD[6] AD[5] GND

21 GND 3.3V AD[9] AD[8] M66EN# C/BE[0]# GND

20 GND AD[12] GND V(I/O) AD[11] AD[10] GND

19 GND 3.3V AD[15] AD[14] GND AD[13] GND

18 GND SERR# GND 3.3V PAR C/BE[1]# GND

17 GND 3.3V NC NC GND PERR# GND

16 GND DEVSEL GND V(I/O) STOP# LOCK# GND

15 GND 3.3V FRAME# IRDY# BDSEL# TRDY# GND

12 - 14 Key Area

11 GND AD[18] AD[17] AD[16] GND C/BE[2]# GND

10 GND AD[21] GND 3.3V AD[20] AD[19] GND

9 GND C/BE[3]# NC AD[23] GND AD[22] GND

8 GND AD[26] GND V(I/O) AD[25] AD[24] GND

7 GND AD[30] AD[29] AD[28] GND AD[27] GND

6 GND REQ0# NC 3.3V CLK0 AD[31] GND

5 GND NC NC RST# GND GNT0 GND

4 GND NC Healthy# V(I/O) INTP INTS GND

3 GND INTA# INTB# INTC# 5V INTD# GND

2 GND TCK 5V TMS NC TDI GND

1 GND 5V -12V TRST# +12V 5V GND

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Table 2-18: CompactPCI Bus Connector J1 Peripheral Slot Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

25 GND 5V * ENUM# 3.3V 5V GND

24 GND * 5V V(I/O) * * GND

23 GND 3.3V * * 5V * GND

22 GND * GND 3.3V * * GND

21GND3.3V**** GND

20 GND * GND V(I/O) * * GND

19GND3.3V**GND* GND

18 GND * GND 3.3V * * GND

17GND3.3VNCNCGND* GND

16 GND * GND V(I/O) * * GND

15 GND 3.3V * * BDSEL# * GND

12 - 14 Key Area

11GND***GND* GND

10 GND * GND 3.3V * * GND

9 GND * NC * GND * GND

8 GND * GND V(I/O) * * GND

7GND***GND* GND

6GND* NC 3.3V * * GND

5 GND NC NC * GND * GND

4 GND NC Healthy# V(I/O) INTP INTS GND

3GND***5V* GND

P R E L I M I N A R Y

2 GND TCK 5V TMS NC TDI GND

1 GND 5V -12V TRST# +12V 5V GND

Note ...

A * indicates that the signal normally present at this pin is disconnected from the CompactPCI bus when the CP6500-V is inserted in a peripheral slot.

Warning!

The pins marked with a * are connected to the voltage source on the CPU via a pull-up resistor, and are not suitable for general use. These pins must not be connected. Please contact Kontron Modular Computers’ Technical Support for information on using these pins.

Failure to comply with the above may result in damage to your board.

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Table 2-19: 64-bit CompactPCI Bus Connector J2 System Slot Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

22 GND GA4 GA3 GA2 GA1 GA0 GND

21 GND CLK6 GND NC NC NC GND

20 GND CLK5 GND NC GND NC GND

19 GND GND GND NC NC NC GND

18GNDNCNCNCGNDNC GND

17 GND NC GND PRST# REQ6# GNT6# GND

16GNDNCNCDEG#GNDNC GND

15 GND NC GND FAL# REQ5# GNT5# GND

14 GND AD[35] AD[34] AD[33] GND AD[32] GND

13 GND AD[38] GND V(I/O) AD[37] AD[36] GND

12 GND AD[42] AD[41] AD[40] GND AD[39] GND

11 GND AD[45] GND V(I/O) AD[44] AD[43] GND

10 GND AD[49] AD[48] AD[47] GND AD[46] GND

9 GND AD[52] GND V(I/O) AD[51] AD[50] GND

8 GND AD[56] AD[55] AD[54] GND AD[53] GND

7 GND AD[59] GND V(I/O) AD[58] AD[57] GND

6 GND AD[63] AD[62] AD[61] GND AD[60] GND

5 GND C/BE[5]# NC V(I/O) C/BE[4]# PAR64 GND

4 GND V(I/O) NC C/BE[7]# GND C/BE[6]# GND

3 GND CLK4 GND GNT3# REQ4# GNT4# GND

2 GND CLK2 CLK3 SYSEN# GNT2# REQ3# GND

1 GND CLK1 GND REQ1# GNT1# REQ2# GND

Note ...

The 64-bit CompactPCI signals are not supported, but all 64 control signals are terminated to V(I/O).

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Table 2-20: 64-bit CompactPCI Bus Connector J2 Peripheral Slot Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

22 GND GA4 GA3 GA2 GA1 GA0 GND

21 GND CLK6 GND NC NC NC GND

20 GND CLK5 GND NC GND NC GND

19 GND GND GND NC NC NC GND

18GNDNCNCNCGNDNC GND

17 GND NC GND PRST# REQ6# GNT6# GND

16GNDNCNCDEG#GNDNC GND

15 GND NC GND FAL# REQ5# GNT5# GND

14GND***GND* GND

13 GND * GND V(I/O) * * GND

12GND***GND* GND

11 GND * GND V(I/O) * * GND

10GND***GND* GND

9 GND * GND V(I/O) * * GND

8GND***GND* GND

7 GND * GND V(I/O) * * GND

6GND***GND* GND

5 GND * GND V(I/O) * * GND

4 GND V(I/O) NC * GND * GND

3 GND CLK4 GND GNT3# REQ4# GNT4# GND

2 GND CLK2 CLK3 SYSEN# GNT2# REQ3# GND

P R E L I M I N A R Y

1 GND CLK1 GND REQ1# GNT1# REQ2# GND

Note ...

A * indicates that the signal normally present at this pin is disconnected from the CompactPCI bus when the CP6500-V is inserted in a peripheral slot.

Warning!

Failure to comply with the above may result in damage to your board.

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2.2.20.3 CompactPCI Rear I/O Connectors J3-J5 and Pinouts

The CP6500-V conducts all I/O signals through the rear I/O connectors J3, J4 and J5. The CP6500-V board provides optional rear I/O connectivity for peripherals for special compact systems. All standard PC interfaces are implemented and assigned to the front panel and to the rear I/O connectors J3, and J5.

When the rear I/O module is used, the signals of some of the main board/front panel connectors are routed to the module interface. Thus the rear I/O module makes it much easier to remove the CPU in the rack as there is practically no cabling on the CPU board.

For the system rear I/O feature a special backplane is necessary. The CP6500-V with rear I/O is compatible with all standard 6U CompactPCI passive backplanes with rear I/O support on the system slot.

The CP6500-V conducts all I/O signals through the rear I/O connectors J3, J4 and J5.

Table 2-21: Backplane J3 Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

1 GND SP0:RTS SP0:RX# SP0:DSR SP0:DCD ID1 GND

2 GND SP0:RI SP0:DTR SP0:CTS SP0:TX# PS2:CLK GND

3 GND SP1:RTS SP1:RX# SP1:DSR SP1:DCD PS2:DATA GND

4 GND SP1:RI SP1:DTR SP1:CTS SP1:TX# KB:DATA GND

5 GND VGA:BLUE VGA:HSYNC VGA:VSYNC VGA:SCL KB:CLK GND

6 GND VGA:RED VGA:GREEN VGA:SDA NC NC GND

7 GND RIO_VCC3 NC ID3 ID4 SPEAKER GND

8 GND USB0:D- USB0:D+ GND NC NC GND

9 GND USB1:D- USB1:D+ GND NC NC GND

10 GND RIO_USB1:VCCRIO_USB0:VCCGND NC NC GND

11 GND NC NC GND NC NC GND

12 GND NC NC GND NC NC GND

13 GND LPa:ACT LPb:ACT NC NC FAN:SENSE1 GND

14 GND LPa:LINK LPb:LINK LPab:CT1

15 GND LPb_DB+ LPb_DB- GND NC NC GND

LC_LINK

FAN:SENSE2 GND

P R E L I M I N A R Y

16 GND LPb_DA+ LPb_DA- GND NC NC GND

17 GND LPa_DB+ LPa_DB- GND NC NC GND

18 GND LPa_DA+ LPa_DA- GND NC NC GND

19 GND RIO_VCC RIO_VCC RIO_VCC3 RIO_+12V RIO_-12V GND

a. This pin is connected to GND via a bypass capacitor.

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Functional Description CP6500-V

Warning!

The RIO_XXX signals are power supply outputs from the CPU board to supply the RIO board with power and must not be supplied with external power.

Failure to comply with the above may result in damage to your board.

The following table describes the signals of the J3 connector.

Table 2-22: Backplane J3 Signals

SIGNAL DESCRIPTION

SP0 COM1 Signaling (RS232, RS422)

SP1 COM2 Signaling (RS232, RS422, RS485)

VGA

USB0 USB Port Signaling

USB1 USB Port Signaling

KB PS2 Keyboard Signaling

PS2 PS2 Mouse Signaling

SPEAKER Standard PC Speaker

FAN Fan Sensoring

LPa Rear I/O LAN Port B

LPb Rear I/O LAN Port A

Graphic Signaling

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Table 2-23: Backplane J4 Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

1 GND PIM:61 PIM:63 GND PIM:62 PIM:64 GND

2 GND PIM:57 PIM:59 GND PIM:58 PIM:60 GND

3 GND GND GND GND GND GND GND

4 GND PIM:53 PIM:55 GND PIM:54 PIM:56 GND

5 GND PIM:49 PIM:51 GND PIM:50 PIM:52 GND

6 GND GND GND GND GND GND GND

7 GND PIM:45 PIM:47 GND PIM:46 PIM:48 GND

8 GND PIM:41 PIM:43 GND PIM:42 PIM:44 GND

9 GND GND GND GND GND GND GND

10 GND PIM:37 PIM:39 GND PIM:38 PIM:40 GND

11 GND PIM:33 PIM:35 GND PIM:34 PIM:36 GND

12 - 14 Key Area

15 GND PIM:29 PIM:31 GND PIM:30 PIM:32 GND

16 GND PIM:25 PIM:27 GND PIM:26 PIM:28 GND

17 GND GND GND GND GND GND GND

18 GND PIM:21 PIM:23 GND PIM:22 PIM:24 GND

19 GND PIM:17 PIM:19 GND PIM:18 PIM:20 GND

20 GND GND GND GND GND GND GND

21 GND PIM:13 PIM:15 GND PIM:14 PIM:16 GND

22 GND PIM:9 PIM:11 GND PIM:10 PIM:12 GND

23 GND NC RIO_VCC GND NC RIO_VCC3 GND

24 GND PIM:5 PIM:7 GND PIM:6 PIM:8 GND

25 GND PIM:1 PIM:3 GND PIM:2 PIM:4 GND

Note ...

The J4 connector is directly connected to the Jn4 connector from the PMC module.

P R E L I M I N A R Y

Warning!

The RIO_XXX signals are power supply outputs from the CPU board to supply the RIO board with power and must not be supplied with external power.

Failure to comply with the above may result in damage to your board.

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Table 2-24: Backplane J5 Pinout

PIN ROW Z ROW A ROW B ROW C ROW D ROW E ROW F

1 GND GND GND GND GND GND GND

2 GND NC NC GND NC NC GND

3 GND GND GND GND GND GND GND

4 GND NC NC GND NC NC GND

5 GND GND GND GND GND GND GND

6 GND NC NC GND NC NC GND

7 GND GND GND GND GND GND GND

8 GND NC NC GND NC NC GND

9 GND GND GND GND GND GND GND

10 GND GND GND GND SMB:SDA SMB:SCL GND

11 GND FD: MTR0# FD: INDEX# GND FD: FDEDIN# FD: DENSEL# GND

12 GND FD: DIR# FD: MTR1# GND FD: DSEL0# FD: DSEL1# GND

13 GND FD: TRK0# FD: WGATE# GND FD: WDATA# FD: STEP# GND

14 GND FD: DSKCHG# FD: HDSEL# GND FD: RDATA# FD: WRPROT# GND

15 GND IDE:D6 IDE:D8 GND IDE:D7 IDE:RESET# GND

16 GND IDE:D4 IDE:D10 GND IDE:D5 IDE:D9 GND

17 GND IDE:D2 IDE:D12 GND IDE:D3 IDE:D11 GND

18 GND IDE:D0 IDE:D14 GND IDE:D1 IDE:D13 GND

19 GND IDE:IOR# IDE:IOW# GND IDE:REQ IDE:D15 GND

20 GND NC IDE:IRQ GND IDE:ACK# IDE:IORDY GND

21 GND IDE:A2 IDE:A0 GND IDE:A1 NC GND

P R E L I M I N A R Y

22 GND IDE:DASP IDE:CS1# GND IDE:CS0#

a. This pin is intended for connecting an external battery to the CP6500-V.

The following table describes the signals of the J5 connector.

Table 2-25: Backplane J5 Signals

BATT (3.0V)

GND

SIGNAL DESCRIPTION

SMB

FD Floppy Disk Signaling

IDE Secondary Hard Disk Drive Channel Signaling

System Management Bus Signaling

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2.2.20.4 Rear I/O Configuration

Rear I/O interfaces are only available on the rear I/O version of the board.

Ethernet Interfaces

Fast Ethernet signals are available on the rear I/O interface (PICMG 2.16 pinout).

VGA CRT Interface

The VGA signals are available on both rear I/O and front I/O. The 75 ohm termination resistor for the red, green and blue video signals are equipped on the CP6500-V.

To enable the rear I/O VGA port, configure the jumper J17.

Note ...

Both VGA ports are electrically identical and can be switched between front and rear by configuring jumper J17 (open = front; closed = rear).

Serial Interfaces COM1 and COM2

Only one interface may be used (rear I/O or front I/O) for COM 1.

Note ...

Previous boards such as CP604 and CP605 used TTL signaling voltage for the COM1 and COM2 rear I/O interfaces. Due to a new common Kontron rear I/O pinout, the COM1 and COM2 ports can now be configured as RS232, RS422 and RS485 ports. Thus, neither RS232, RS424 nor RS485 buffers are now required on the rear I/O. The signals can be connected directly to the D-SUB connector.

Keyboard/Mouse Interface

The keyboard interface is available onboard and via the rear I/O. The combination of the onboard and the rear I/O is not supported. The mouse interface is only available via the rear I/O.

USB Interface

Two USB interfaces are available via the rear I/O. The USB power comes from the baseboard and it is protected by a self-resettable fuse.

Secondary EIDE Interface

Only one EIDE connector may be used at any one time through the same port; connecting both EIDE devices to the CP6500-V baseboard and the rear I/O simultaneously will result in malfunction and data loss.

P R E L I M I N A R Y

Floppy Interface

The floppy interface is only available via the rear I/O.

PMC Rear I/O

The PMC Rear I/O pinout is optimized to connect the Kontron SCSI PMC board (PMC 261). This module provides SCSI rear I/O support. Other PMC modules with rear I/O functionality can also be used on the CP6500-V.

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Chapter 1

Installation

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3. Installation

The CP6500-V has been designed for easy installation. However, the following standard precautions, installation procedures, and general information must be observed to ensure proper installation and to preclude damage to the board, other system components, or injury to personnel.

3.1 Safety Requirements

The following safety precautions must be observed when installing or operating the CP6500V. Kontron assumes no responsibility for any damage resulting from failure to comply with these requirements.

Warning!

Due care should be exercised when handling the board due to the fact that the heat sink can get very hot. Do not touch the heat sink when installing or removing the board.

In addition, the board should not be placed on any surface or in any form of storage container until such time as the board and heat sink have cooled down to room temperature.

Caution!

If your board type is not specifically qualified as being hot swap capable, switch off the CompactPCI system power before installing the board in a free CompactPCI slot. Failure to do so could endanger your life or health and may damage your board or system.

Note ...

Certain CompactPCI boards require bus master and/or rear I/O capability. If you are in doubt whether such features are required for the board you intend to install, please check your specific board and/or system documentation to make sure that your system is provided with an appropriate free slot in which to insert the board.

ESD Equipment!

This CompactPCI board contains electrostatically sensitive devices. Please observe the necessary precautions to avoid damage to your board:

• Discharge your clothing before touching the assembly. Tools must be discharged before use.

• Do not touch components, connector-pins or traces.

• If working at an anti-static workbench with professional discharging equipment, please do not omit to use it.

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3.2 CP6500-V Initial Installation Procedures

The following procedures are applicable only for the initial installation of the CP6500-V in a system. Procedures for standard removal and hot swap operations are found in their respective chapters.

To perform an initial installation of the CP6500-V in a system proceed as follows:

1. Ensure that the safety requirements indicated Chapter 3.1 are observed.

Warning!

Failure to comply with the instruction below may cause damage to the board or result in improper system operation.

2. Ensure that the board is properly configured for operation in accordance with application requirements before installing. For information regarding the configuration of the CP6500-V and rear I/O

refer to Chapter 4. For the installation of

devices refer to the appropriate chapters in Chapter 3.

CP6500-V

specific peripheral devices

Warning!

Care must be taken when applying the procedures below to ensure that neither the CP6500-V nor other system boards are physically damaged by the application of these procedures.

3. To install the CP6500-V perform the following:

1. Ensure that no power is applied to the system before proceeding.

Warning!

When performing the next step, DO NOT push the board into the backplane connectors. Use the ejector handles to seat the board into the backplane connectors.

P R E L I M I N A R Y

2. Carefully insert the board into the slot designated by the application requirements for

the board until it makes contact with the backplane connectors.

3. Using both ejector handles, engage the board with the backplane. When the ejector

handles are locked, the board is engaged.

4. Fasten the two front panel retaining screws.

5. Connect all external interfacing cables to the board as required.

6. Ensure that the board and all required interfacing cables are properly secured.

4. The CP6500-V is now ready for operation. For operation of the CP6500-V, refer to appropriate CP6500-V specific software, application, and system documentation.

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3.3 Standard Removal Procedures

To remove the board proceed as follows:

1. Ensure that the safety requirements indicated in Chapter 3.1 are observed. Particular attention must be paid to the warning regarding the heat sink!

Warning!

Care must be taken when applying the procedures below to ensure that neither the CP6500-V nor system boards are physically damaged by the application of these procedures.

2. Ensure that no power is applied to the system before proceeding.

3. Disconnect any interfacing cables that may be connected to the board.

4. Unscrew the front panel retaining screws.

Warning!

Due care should be exercised when handling the board due to the fact that the heat sink can get very hot. Do not touch the heat sink when changing the board.

5. Disengage the board from the backplane by first unlocking the board ejection handles and then by pressing the handles as required until the board is disengaged.

6. After disengaging the board from the backplane, pull the board out of the slot.

7. Dispose of the board as required.

3.4 Hot Swap Procedures

The CP6500-V is designed for hot swap operation. When installed in the system slot it is capable of supporting peripheral board hot swapping. When installed in a peripheral slot, its hot swap capabilities depend on the type of backplane in use and the system controller’s capabilities. The reason for this being that communications with the system controller requires either front panel Ethernet I/O or use of a packet switching backplane. In any event, hot swap is also a function of the application running on the CP6500-V.

3.4.1 System Master Hot Swap

Hot swapping of the CP6500-V itself when used as the system controller is possible, but will result in any event in a cold start of the CP6500-V and consequently a reinitialization of all peripheral boards. Exactly what transpires in such a situation is a function of the application and is not addressed in this manual. The user must refer to appropriate application documentation for applicable procedures for this case. In any event, the safety requirements above must be observed.

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3.4.2 Peripheral Hot Swap Procedure

This procedure assumes that the board to be hot swapped has undergone an initial board installation and is already installed in an operating system, and that the system supports hot swapping of the board.

To hot swap the CP6500-V proceed as follows:

1. Ensure that the safety requirements indicated in Chapter 3.1 are observed. Particular attention must be paid to the warning regarding the heat sink!

Warning!

Care must be taken when applying the procedures below to ensure that neither the CP6500-V nor other system boards are physically damaged by the application of these procedures.

2. Unlock both board ejection handles ensuring that the bottom handle has activated the hot swap switch (this occurs with a very small amount of movement of the handle).

Note ...

What transpires at this time is a function of the application. If hot swap is supported by the application, then the blue HS LED should light up after a short time period. This indicates that the system has recognized that the CP6500-V is to be hot swapped and now indicates to the operator that hot swapping of the CP6500-V may proceed.

If the blue HS LED does not light up after a short time period, either the system does not support hot swap or a malfunction has occurred. In this event, the application is responsible for handling this situation and must provide the operator with appropriate guidance to remedy the situation.

3. After approximately 1 to 15 seconds, the blue HS LED should light up. If the LED lights up, proceed with the next step of this procedure. If the LED does not light up, refer to appropriate application documentation for further action.

4. Disconnect any interfacing cables that may be connected to the board.

5. Unscrew the front panel retaining screws.

P R E L I M I N A R Y

Warning!

Due care should be exercised when handling the board due to the fact that the heat sink can get very hot. Do not touch the heat sink when changing the board.

6. Using the ejector handles, disengage the board from the backplane and carefully remove it from the system.

7. Dispose of the “old” board as required observing the safety requirements indicated in Chapter 3.1.

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8. Obtain the replacement CP6500-V board.

Warning!

When performing the next step, DO NOT push the board into the backplane connectors. Use the ejector handles to seat the board into the backplane connectors.

9. Carefully insert the “new” board into the “old” board slot until it makes contact with the backplane connectors.

10. Using both ejector handles, engage the board with the backplane. When the ejector handles are locked, the board is engaged.

11. Fasten the front panel retaining screws.

12. Connect all required interfacing cables to the board. Hot swap of the CP6500-V is now complete.

3.5 Installation of CP6500-V Peripheral Devices

The CP6500-V is designed to accommodate a variety of peripheral devices whose installation varies considerably. The following chapters provide information regarding installation aspects and not detailed procedures.

3.5.1 CompactFlash Installation

The CompactFlash socket supports CompactFlash ATA cards type I and II with 5 V (default) or

3.3 V.

Note ...

The CP6500-V does not support removal and reinsertion of the CompactFlash storage card while the board is in a powered-up state. Connecting the CompactFlash cards while the power is on, which is known as "hot plugging", may damage your system.

3.5.2 USB Device Installation

The CP6500-V supports all USB Plug and Play computer peripherals (e.g. keyboard, mouse, printer, etc.).

Note ...

All USB devices may be connected or removed while the host or other peripherals are powered up.

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3.5.3 Rear I/O Device Installation

To ensure proper functioning of the rear I/O VGA interface, the jumpers on the CP6500-V must be configured for the rear I/O. See Chapter 4 for configuration details.

For physical installation of rear I/O devices, refer to the documentation provided with the device itself.

Note ...

It is strongly recommended to use COM1 only on the front or rear I/O panel.

3.5.4 Battery Replacement

The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer. Suitable batteries include the VARTA CR2025 and PANASONIC BR2020.

Note ...

Care must be taken to ensure that the battery is correctly replaced.

The battery should be replaced only with an identical or equivalent type recommended by the manufacturer.

Dispose of used batteries according to the manufacturer’s instructions.

3.5.5 Hard Disk Installation

The following information pertains to hard disks which may be connected to the CP6500-V via normal cabling. To install a hard disk, it is necessary to perform the following operations in the

P R E L I M I N A R Y

given order:

1. Install the hardware.

Warning!

The incorrect connection of power or data cables may damage your hard disk unit and/or CP6500-V board.

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Note ...

Due to the high transfer rate of ATA-100, a specialized cable which has additional grounding wires to reduce reflections, noise, and inductive coupling is required This cable will also support all legacy IDE drives.

The blue end of the ATA-100 cable must connect to the motherboard, the gray connector to the UltraDMA/100 slave device, and the black connector to the UltraDMA/100 master device.

Some symptoms of incorrectly installed HDDs are:

• Hard disk drives are not auto-detected: may be a Master / Slave problem or a bad IDE cable. Contact your vendor.

• Hard Disk Drive Fail message at boot-up: may be a bad cable or lack of power going to the drive.

• No video on boot-up: usually means the cable is installed backwards.

• Hard drive lights are constantly on: usually means bad IDE cable or defective drives / motherboard. Try another HDD.

• Hard drives do not power up: check power cables and cabling. May also result from a bad power supply or IDE drive.

Note ...

A 2.5" HDD can be directly installed only on the standard CP6500-V.

2. Initialize the software necessary to run the chosen operating system.

3.6 Software Installation

The installation of the Ethernet and all other onboard peripheral drivers is described in detail in the relevant Driver Kit files.

Installation of an operating system is a function of the OS software and is not addressed in this manual. Refer to appropriate OS software documentation for installation.

Note ...

Users working with pre-configured operating system installation images for Plug and Play compliant operating systems, for example Windows® 95/98/ME, Windows® 2000, Windows® XP, Windows® XP Embedded, must take into consideration that the stepping and revision ID of the chipset and/or other onboard PCI devices may change. Thus, a re-configuration of the operating system installation image deployed for a previous chipset stepping or revision ID is in most cases required. The corresponding operating system will detect new devices according to the Plug and Play configuration rules.

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Chapter 1

Configuration

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4. Configuration

4.1 Jumper Description

4.1.1 CompactFlash Configuration

Table 4-1: CompactFlash Configuration

R199/ J16 DESCRIPTION

Open Configured for master

Closed Configured for slave

The default setting is indicated by using italic bold.

4.1.2 CompactFlash Power Configuration

Table 4-2: CompactFlash Power Configuration

R215 R218 DESCRIPTION

Open Closed 5 V

Closed Open 3.3 V

The default setting is indicated by using italic bold.

4.1.3 Clearing BIOS CMOS Setup

If the system does not boot (due to, for example, the wrong BIOS configuration, or wrong password setting), the CMOS setting may be cleared using jumper JP1.

Procedure for clearing CMOS setting:

The system is booted with the jumper in the new, closed position, then powered down again. The jumper is reset back to the normal position, then the system is rebooted again

Table 4-3: Clearing BIOS CMOS Setup

J21 DESCRIPTION

Open Normal boot using the CMOS settings

Closed Clear the CMOS settings and use the default values

The default setting is indicated by using italic bold.

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4.1.4 Shorting Chassis GND (Shield) to Logic GND

The front panel and front panel connectors are isolated to the logic ground.

To enable the connection between the chassis GND and logic GND the capacitors must be exchanged with zero ohm resistors.

Table 4-4: Shorting Chassis GND (Shield) to Logic GND

CAPACITOR SETTING DESCRIPTION

Closed 470pF 2KV capacitors Connectors are isolated to logic GND with three

C1, C3, C4, C5

Closed zero ohm resistors

Closed 1.5nF 2KV capacitors Connectors are isolated to logic GND with four

C63, C224, C64,

C205

Closed zero ohm resistors

470pF 2KV capacitors

Connectors are connected to logic GND and chassis GND

1.5nF 2KV capacitors

Connectors are connected to logic GND and chassis GND

The default setting is indicated by using italic bold.

4.1.5 VGA CRT Rear I/O Configuration

The VGA CRT signals are configurable either for rear I/O or front I/O using the jumper J17.

Table 4-5: VGA-CRT Jumper Setting

J17 DESCRIPTION

Open Only front I/O

Closed Only rear I/O

The default setting is indicated by using italic bold

4.1.6 Front-I and Front-II General Purpose LEDs

The General Purpose LEDs are available for either general application use or indicating the

P R E L I M I N A R Y

POST code during boot-up.

When POST code is selected, the General Purpose LEDs indicate POST code during BIOS boot-up. If not required to indicate POST code, they can be used as general purpose LEDs.

Table 4-6: General Purpose LED Setting

J18 DESCRIPTION

Open General purpose functionality

Closed POST code

The default setting is indicated by using italic bold.

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4.1.7 Serial Ports COM1 and COM2 Jumper and Resistor Settings

4.1.7.1 COM1 Jumper and Resistor Setting

The serial interface COM1 (J9) may be configured for either RS232 or RS422 using solder jumpers and appropriate resistors. The following figure and tables indicate the physical locations of these jumpers and resistors, and their required configurations for the various operational modes.

Figure 4-1: COM1 Configuration Jumpers and Resistors

JP7

R329

R320

JP3

JP4

JP8

COM1

R330

R311

JP5

JP6

Table 4-7: Resistor Setting to Configure COM1

RESISTOR RS232 RS422

JP8 (soldered or 0 ohm, 0805 package) Closed Open

R311 (4700 ohm, 0603 package) Open Open

R330 (soldered or 0 ohm, 0603 package) Open Open

The default setting is indicated by using italic bold.

RS422 and RS485 COM1 Termination

When COM1 is configured for RS422 operation and is the last device on the RS422 bus, then the RS422 interface must provide termination resistance. The purpose of jumpers JP5 and JP7 is to enable this line termination resistor (120 ohm).

Table 4-8: Jumper Setting for RS422 RXD Termination (COM1)

P R E L I M I N A R Y

TERMINATION JP5

ON Closed (soldered or 0 ohm, 0805 package)

OFF Open

The default setting is indicated by using italic bold.

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Table 4-9: Jumper Setting for RS422 TXD and RS485 Termination (COM1)

TERMINATION JP6

ON Closed (soldered or 0 ohm, 0805 package)

OFF Open

The default setting is indicated by using italic bold.

Note ...

COM1 is available on the front and rear I/O without any switch. It is strongly recommended to use only one option at the same time.

4.1.7.2 COM2 Jumper and Resistor Setting

The serial interface COM2 (rear I/O) may be configured for either RS232, RS422 or RS485 by setting solder jumpers. The following figure and tables indicate the physical locations of these solder jumpers and their required configurations for the various operational modes.

Figure 4-2: COM2 Configuration Jumpers and Resistors

JP7

COM2

JP3

JP8

P R E L I M I N A R Y

Table 4-10: Resistor Setting to Configure COM2

JP5

R329

R320

JP4

R330

R311

JP6

RESISTOR RS232 RS422 RS485

JP7 (soldered or 0 ohm, 0805 package) Closed Open Open

R320 (4700 ohm, 0603 package) Open Open Closed

R329 (soldered or 0 ohm, 0603 package) Open Open Closed

The default setting is indicated by using italic bold.

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RS422 and RS485 COM2 Termination

When COM1 is configured for RS422 or RS485 operation and is the last device on the RS422 or RS485 bus, then the RS422 or RS485 interface must provide termination resistance. The purpose of jumpers JP3 and JP4 is to enable this line termination resistor (120 ohm).

Table 4-11: Jumper Setting for RS422 RXD Termination (COM2)

TERMINATION JP3

ON Closed (0 ohm resistor)

OFF Open

The default setting is indicated by using italic bold.

Table 4-12: Jumper Setting for RS422 TXD and RS485 Termination (COM2)

TERMINATION JP4

ON Closed (0 ohm resistor)

OFF Open

The default setting is indicated by using italic bold.

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4.2 Interrupts

The CP6500-V board uses the standard AT IRQ routing (8259 controller).

This interrupt routing is the default, but can be modified via the BIOS.

Table 4-13: Interrupt Setting

IRQ PRIORITY STANDARD FUNCTION

IRQ0 1 System Timer

IRQ1 2 Keyboard Controller

IRQ2 -- Input of the second IRQ controller (IRQ8-IRQ15)

IRQ3 11 COM2

IRQ4 12 COM1

IRQ5 13 Watchdog

IRQ6 14 Floppy Disk Controller

IRQ7 15 Free

IRQ8 3 System Real-Time Clock

IRQ9 4 PCI or ACPI

IRQ10 5 PCI

IRQ11 6 PCI

IRQ12 7 PCI or PS/2 mouse

IRQ13 8 Coprocessor error

IRQ14 9 Primary hard disk

IRQ15 10 Secondary hard disk

NMI Watchdog

Warning!

P R E L I M I N A R Y

IRQ5 should normally have only one source enabled, otherwise improper system operation may result.

If more than one source is required to be enabled, contact Kontron Modular Computers’ Technical Support before implementing the IRQs.

For events that are not time critical, such as ENUM, DERATE, etc., polling should be considered instead of using an IRQ.

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4.3 Onboard PCI Interrupt Routing

The ICH4 provides up to 8 PCI interrupt inputs. The table below describes the connection of these IRQ signals.

For more information, refer to the INTEL ICH4 data sheet.

Table 4-14: PCI Interrupt Routing

ICH4 / IRQ INPUT PCI DEVICE CHIPSET DEVICE

PIRQA PMC INTA USBI (front)

VGA

PIRQB PMC INTB Fast Ethernet I

SMBus

PIRQC PMC INTC Fast Ethernet II

USBIII (unused)

PIRQD PMC INTD USBII (rear)

PIRQE CPCI INTA Free

PIRQF CPCI INTB Free

PIRQG CPCI INTC Free

PIRQH CPCI INTD USB 2.0 controller

4.4 Memory Map

The CP6500-V board uses the standard AT ISA memory map.

4.4.1 Memory Map for the 1st Megabyte

The following table sets out the memory map for the first megabyte:

Table 4-15: Memory Map for the 1st Megabyte

MEMORY RANGE SIZE FUNCTION

0xE0000 – 0xFFFFF 128 k BIOS implemented in FWH

Reset vector 0xFFFF0

0xD0000 – 0xDFFFF 64 k Free

0xCC000 – 0xCFFFF 16 k Free

0xC0000 – 0xCBFFF 48 k BIOS of the VGA card.

P R E L I M I N A R Y

0xA0000 – 0xBFFFF 128 k Normally used as video RAM as follows:

CGA video: 0xB8000-0xBFFFF

Monochrome video: 0xB0000-0xB7FFF

EGA/VGA video: 0xA0000-0xAFFFF

0x000000 – 0x9FFFF 640 k DOS reserved memory space

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4.4.2 I/O Address Map

The following table sets out the memory map for the I/O memory. The shaded table cells indicate CP6500-V specific registers.

Table 4-16: I/O Address Map

ADDRESS DEVICE

000-00F DMA controller #1

020-021 Interrupt controller #1

022-02F Reserved

040-043 Timer

060-063 Keyboard interface

070-071 RTC port

080-08F DMA page register

0A0-0AF Interrupt controller #2

0C0-0DF DMA controller #2

0E0-0EF Reserved

0F0-0FF Math coprocessor

170-17F Hard disk secondary

1F0-1FF Hard disk primary

280 Watchdog trigger

282 Watchdog timer

283 Geographic addressing

284 Watchdog, CPCI IRQ routing

285 CPCI reset

286 I/O status

287 I/O configuration

P R E L I M I N A R Y

288 Board version

289 Hardware index

28A HS status

28B Logic index

28D LED control

28E HS LED control

2F8-2FF Serial port COM2

378-37F Parallel printer port LPT1

3F0-3F7 Floppy Disk + Super-I/O #1 Com.

3F8-3FF Serial port COM1

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4.5 Special Registers Description

The following registers are special registers which the CP6500-V uses to watch the onboard hardware special features and the CompactPCI control signals.

Normally, only the system BIOS uses these registers, but they are documented here for application use as required.

Note ...

Take care when modifying the contents of these registers as the system BIOS may be relying on the state of the bits under its control.

4.5.1 Watchdog

The CP6500-V has one watchdog timer. This timer is provided with a programmable timeout ranging from 125 msec to 256 sec. Failure to strobe the watchdog timer within a set time period results in a system reset, NMI or an interrupt. This can be configured via the 0x284 register.

To enable the watchdog, bit ”4” of the 0x282 register must be set. If the watchdog is enabled via bit ”4”, this bit cannot be cleared later.

With a write access to the 0x280 register the watchdog is retriggered. Once the watchdog is enabled, it must be continuously strobed within the terminal count period to avoid resetting the system hardware.

The watchdog can be configured in several modes, one of which is the dual stage configuration. If the NMI and the reset configuration bits are set (0x284 = 0x84), the watchdog has two stages. The first stage timeout generates an NMI interrupt. If the NMI handler does not reconfigure the watchdog, the watchdog switches to the second stage and generates a master reset after the configured timeout elapses.

4.5.2 Watchdog Trigger

A write access triggers the watchdog.

The I/O location for the watchdog trigger is 0x280.

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4.5.3 Watchdog Timer Register

Table 4-17: Watchdog Timer Register

ADDRESS 0x282 R W

BIT POSITION

CONTENT Res. Res. WDR WDEN WDT3 WDT2 WDT1 WDT0

DEFAULT 00000000

BIT NAME VAL DESCRIPTION

0 WDT[3:0] Timeout Period:

7 6 5 4 3 2 1 0

MSB

Bits: 3 2 1 0

Setting: 0 0 0 0 = 0 = 000.125 sec

0 0 0 1 = 1 = 000.250 sec

0 0 1 0 = 2 = 000.500 sec

0 0 1 1 = 3 = 001 sec

0 1 0 0 = 4 = 002 sec

0 1 0 1 = 5 = 004 sec

0 1 1 0 = 6 = 008 sec

0 1 1 1 = 7 = 016 sec

1 0 0 0 = 8 = 032 sec

1 0 0 1 = 9 = 064 sec

1 0 1 0 = 10 = 128 sec

1 0 1 1 = 11 = 256 sec

1 1 0 0 = 12 = res.

1 1 0 1 = 13 = res.

1 1 1 0 = 14 = res.

1 1 1 1 = 15 = res.

LSB

4 WDEN 0 Watchdog timer disabled

P R E L I M I N A R Y

1 Watchdog timer enabled

Note ...

Once the watchdog timer is enabled it cannot be disabled except by resetting the system.

5 WDR 0 System reset generated by power-on reset

1 System reset generated by Watchdog

60Reserved

70Reserved

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4.5.4 Geographic Addressing Register

The geographic addressing register describes the CompactPCI geographic addressing signals.

Table 4-18: Geographic Addressing Register

ADDRESS 0x283 R

BIT POSITION

CONTENT Res. Res. Res. GA4 GA3 GA2 GA1 GA0

DEFAULT 00000000

BIT NAME VAL DESCRIPTION

0GA0

1GA1

2GA2

3GA3

4GA4

7 6 5 4 3 2 1 0

MSB

Geographic address

Reserved

LSB

P R E L I M I N A R Y

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4.5.5 Watchdog, CompactPCI Interrupt Configuration Register

The interrupt configuration register holds a series of bits defining the interrupt routing for the watchdog, the power control derate signal and the CompactPCI enumeration signal. If the watchdog timer fails, it can generate three independent hardware events: reset, NMI and IRQ5 interrupt.

The enumeration signal is generated by a hot swap compatible board after insertion and prior to removal. The system uses this interrupt signal to force software to configure the new board. The derate signal indicates that the power supply is beginning to derate its power output.

Table 4-19: Watchdog, CompactPCI Interrupt Configuration Register

ADDRESS 0x284 R W

BIT POSITION

CONTENT WNMI CFNMI CFIRQ CEIRQ CDIRQ WRST WIRQ HSIRQ

DEFAULT 00000000

BIT NAME VAL DESCRIPTION

0HSIRQ0

1WIRQ0

2WRST0

3CDIRQ0

4CEIRQ0

5 CFIRQ 0 Disable CPCI fail signal to IRQ5 routing

P R E L I M I N A R Y

6 CFNMI 0 Disable CPCI fail signal to NMI routing

7 6 5 4 3 2 1 0

MSB

Disable hot swap handle IRQ5

1 Enable CPCI enum signal to IRQ5 routing

1 Enable CPCI fail signal to IRQ5 routing

Enable hot swap handle IRQ5

Disable Watchdog IRQ5 routing

Enable Watchdog IRQ5 routing

Disable Watchdog hardware reset

Enable Watchdog hardware reset

Disable CPCI derate signal to IRQ5 routing

Enable CPCI derate signal to IRQ5 routing

Disable CPCI enum signal to IRQ5 routing

LSB

1 Enable CPCI fail signal to NMI routing

7 WNMI 0 Disable Watchdog NMI routing

1 Enable Watchdog NMI routing

Note ...

To enable the dual stage watchdog, the NMI and the reset bits must be set. At the first stage the watchdog generates an NMI, and at the second stage the system will be reset.

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4.5.6 CPCI Master Reset

The CPCI master reset register describes the routing of the reset signal from the CompactPCI interface to the local reset controller if the board is installed in a peripheral slot. If the board is installed in a system slot, the reset is always an output. If the reset is disabled, the CP6500-V ignores the reset signal from the CompactPCI interface.

Table 4-20: CPCI Master Reset Register

ADDRESS 0x285 R W

BIT POSITION

CONTENT Res. Res. Res. Res. Res. Res. Res. CRST

DEFAULT 00000000

BIT NAME VAL DESCRIPTION

0CRST0

7 6 5 4 3 2 1 0

MSB

Disable the reset routing from the CompactPCI interface

Enable the reset routing from the CompactPCI interface

Reserved

LSB

P R E L I M I N A R Y

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4.5.7 I/O Status

The I/O status register describes the local and CompactPCI control signals. The watchdog status bit indicates the status of the watchdog timer. If the timer is not retriggered within the previously set time period, the bit is set to ”0” and the watchdog LED lights up. The fail signal is an output of the power supply and indicates a power supply failure. For the description of the derate and enumeration signals, please see the interrupt routing register.

Table 4-21: I/O Status Register

ADDRESS 0x286 R

BIT POSITION

CONTENT WST Res. Res. Res. CSLOT CENUM CFAIL CDER

DEFAULT 10000000

BIT NAME VAL DESCRIPTION

0CDER0

1CFAIL0

2 CENUM 0

3CSLOT0

50Reserved

60Reserved

7 WST 0 Indicates that a Watchdog timeout has occurred

7 6 5 4 3 2 1 0

MSB

Indicates power derating (CPCI DEG signal)

1 Indicates that no Watchdog timeout has occurred

Power normal

Indicates a power supply failure (CPCI FAIL signal)

Power normal

Indicates the insertion or removal of a hot swap system board (CPCI ENUM)

No hot swap event

Indicates that the board is installed in a system slot

Indicates that the board is installed in a peripheral slot

Reserved

P R E L I M I N A R Y

LSB

4.5.8 Board ID

The board ID register describes the hardware and the board index. The content of this register is unique for each Kontron CompactPCI board.

Table 4-22: Board ID Register

ADDRESS 0x288 R

BIT POSITION

CONTENT BID7 BID6 BID5 BID4 BID3 BID2 BID1 BID0

DEFAULT 01110000

7 6 5 4 3 2 1 0

MSB

LSB

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4.5.9 Hardware Index Register

The hardware index will signal to the software when differences in the hardware require different handling by the software. It starts with the value 0 and will be incremented with each change in hardware as development continues.

Table 4-23: Hardware Index Register

ADDRESS 0x289 R

BIT POSITION

CONTENT HWI7 HWI6 HWI5 HWI4 HWI3 HWI2 HWI1 HWI0

DEFAULT 00000000

7 6 5 4 3 2 1 0

MSB

4.5.10 Hot Swap Control Register

The hot swap control register describes the hot swap control signals.

Table 4-24: Hot Swap Control Register

ADDRESS 0x28A R

BIT POSITION

CONTENT Res. HSH HSLED Res. Res. Res. Res. Res.

DEFAULT 00000000

BIT NAME VAL DESCRIPTION

7 6 5 4 3 2 1 0

MSB

Reserved

LSB

5HSLED0

6HSH0

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Hot swap LED switch off

Hot swap LED switch on

Hot swap handle in closed position

Hot swap handle in open position

Reserved

P R E L I M I N A R Y

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4.5.11 Logic Version Register

The logic version register may be used to identify the logic status of the board by software. It starts with the value 0 and will be incremented with each logic update.

Table 4-25: Logic Version Register

ADDRESS 0x28B R

BIT POSITION

CONTENT LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0

DEFAULT 00000000

7 6 5 4 3 2 1 0

MSB

4.5.12 LED Control Register

The LED control register enables the user to switch on and off the Front-I and Front-II LEDs on the front panel.

Table 4-26: LED Control Register

ADDRESS 0x28D R W

BIT POSITION

CONTENT LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0

DEFAULT 00000000

BIT NAME VAL DESCRIPTION

0LED00

1LED10

7 6 5 4 3 2 1 0

MSB

LED switch off

LED switch on

LED switch off

LSB

2LED20

P R E L I M I N A R Y

3LED30

4LED40

5LED50

6LED60

7LED70

LED switch on

LED switch off

LED switch on

LED switch off

LED switch on

LED switch off

LED switch on

LED switch off

LED switch on

LED switch off

LED switch on

LED switch off

LED switch on

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4.5.13 Hot Swap LED Control Register

The hot swap LED control register enables the user to switch on and off the hot swap LED on the front panel.

Table 4-27: Hot Swap LED Control Register

ADDRESS 0x28E R W

BIT POSITION

CONTENT Res. Res. Res. Res. Res. HSLED Res. Res.

DEFAULT 00000000

BIT NAME VAL DESCRIPTION

10Reserved

2HSLED0

50Reserved

60Reserved

70Reserved

7 6 5 4 3 2 1 0

MSB

Reserved

Hot swap LED switch off

Hot swap LED switch on

Reserved

LSB

P R E L I M I N A R Y

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Configuration CP6500-V

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P R E L I M I N A R Y

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