In compliance with Federal Regulations, following are reproduction of labels on, or inside the product relating to laser
product safety.
Caution : No connection of ground line if disassemble
the unit. Please connect the ground line on
rear panel, PCBs, Chassis and some others.
IC-Remote
(W02-2717-05)
Con phono socket
(E63-1309-08)x2
Con phono socket
(E56-0052-08)x2
Con phono socket
(E63-1268-05)
Con phono socket
(E63-1310-08)
Con phono socket
(E63-1269-05)x3
IC-Remote
(W02-2716-05)x2
* Refer to parts list on page 24.
KENWOOD Corp. certifies this equipment conforms to DHHS
Regulations No.21 CFR 1040. 10, Chapter 1, subchapter J.
DANGER : Laser radiation when open and interlock defeated.
AVOID DIRECT EXPOSURE TO BEAM.
Tuner module *
(W02-)
The marking of products using lasers (For countries other than U.S.A., U.S.-Military and Canada)
The marking this product has been classified as Class 1. It means that there is no
danger of hazardous radiation outside
the product.
Location: Back panel
CLASS 1
LASER PRODUCT
CAUTION
INVISIBLE LASER RADIATION
WHEN OPEN. DO NOT STARE
INTO BEAM OR VIEW DIRECTLY
WITH OPTICAL INSTRUMENTS.
CAUTION
VISIBLE LASER RADIATION
WHEN OPEN. DO NOT
STARE INTO BEAM.
Inside this laser product, a laser diode classified as Class 2 laser radiation is contained as
alerted by the internal caution label shown
above. Do not stare into beam.
Location: DVD laser pick-up unit cover inside
this product
Inside this laser product, a laser diode classified as Class
3A laser radiation is contained as alerted by the internal
caution label shown above. Do not stare into beam or
view directly with optical instruments.
Location: CD laser pick-up unit cover inside this product
Operation to reset
The microcomputer may fall into malfunction (impossibility
to operate, erroneous display, etc.) when the power cord is
unplugged while power is ON or due to an external factor. In
this case, execute the following procedure to reset the
microcomputer and return it to normal condition.
Please note that resetting the microcomputer clears the contents stored in and returns and to condition when it left the
factory.
Set the POWER switch to ON (set to Standby
mode). Then press the
key, key and STOP
key in this order.
SystemSpeakers
DVR-8100KSW-8100 (Left speaker, right speaker, center speaker, surround speakers and subwoofer)
Speaker model names
Note related to transportation and movement
Before transporting or moving this unit, carry out the
following operations.
1 Remove the disc from the unit.
2 Press the 6 key.
3 Wait a few seconds and turn the unit OFF.
Manufactured under license from Dolby Laboratories.
“DOLBY”, “Pro Logic” and the double-D symbol are
trademarks of Dolby Laboratories.
“DTS” and “DTS Digital Surround” are trademarks of
Digital Theater Systems, Inc.
FM indoor antenna (1)
(T90-0882-08)
Loop antenna (1)
(T90-0896-08)
Remote control unit (1)
(A70-1600-08): X
(A70-1601-08): ET
1. Insert a flat driver in the drawing through the hole on the loading
chassis bottom and pull the lever down.
2. Pull out the tray frontward by hand when it comes just out.
BLOCK DIAGRAM
DVR-8100
3
DVR-8100
CIRCUIT DESCRIPTION
1. Pin Description of MPEG Processor IC (DVD & VIDEO IC61)
Pin No.Pin NameI/OPin Description
PIOs and communication
1PIO2(5) RGB SEL(BLANK)I/O RGB sel (blank). unused
2PIO2(6) VIDEO MUTEI/O Video mute control.
3PIO2(7) 16: 9 INDICATORI/O 16 : 9 indicator (unused).
6PIO3(0) SCART H (TV/AUX)I/O Unused.
7PIO3(1)I/O Unused.
8PIO3(2) -CSB (unused).
9PIO3(3)-SDIN (unused).
10PIO3(4) IR REMOCONI/O Unused.
11PIO3(5) -SCLK (unused).
12PIO3(6)I/O Unused.
13PIO3(7) DVD RESETI/O Power- on reset of front-end module.
Front-end
16B DATAII2S Data
17B BCLKII2S Bit clock
18B FLAGII2S Error flag
19B SYNCI/O I2S Sector / ABS time
Reserved
20B WCLKI/O Unused.
21B V4I/O Unused.
22NRSS OUTI/O Unused.
23VDD RGB-Supply voltage for RGB (+3.3VA).
24VSS RGB-GND
Video DAC
25,26,27B/G/R (OUT)OB/G/R signal outputs.
28V REF RGIReference voltage input for DAC RGB.
29I REF RGIReference current input for DAC RGB.
30VDD YCC-Supply voltage for YCC (+3.3VA).
31VSS YCC-GND
32~34Y/C/CV (OUT)OY/C/CV signal outputs.
35V REF YCCIReference voltage input for DAC YCC.
36I REF YCCIReference current input for DAC YCC.
48VDD PCM-Supply voltage for PCM (+3V3).
49VSS PCM-Ground for PCM.
51DAC SCLK ODAC over sampling clock.
52DAC PCMOUT0 ODAC PCM data out 0.
53DAC PCMOUT1ODAC PCM out 1 (unused).
54DAC PCMOUT2ODAC PCM out 2 (unused).
55DAC PCMCLKODAC PCM clock.
56DAC LRCLKODAC PCM Left/Right clock.
57SPDIF OUTOAudio digital data output.
103ADC SCLKI/O ADC digital audio port clock (unused).
104ADC LRCLKI/O ADCsample rate clock (unused).
105ADC DATAIADC digital audio data input (unused).
106ADC PCMCLKOCrystal input or master clock input (unused).
JTAG
109TRSTITest reset from emulator module.
110TMSITest mode select.
111TDOOTest data out to emulator module.
112TDIITest data input from emulator module.
113TCKITest clock input from emulator module.
Timers
114PWM2I/O Unused.
115PWM1I/O ROM boot option port (voltage low = emulator booting).
116PWM0I/O Unused.
EMI Interface
117CPU OEI/O Flash ROM output enable.
118CPU PRO CLKOSDRAM clock (unused).
Clock & Reset
120PIX CLKI27MHz main clock input.
122VDD PLL-Supply voltage for PLL (+3V3).
123VSS PLL-Ground for PLL.
124RESETIChip reset input.
Interrupt
125IRQ(2)IInterrupt request 2 from front-end module.
126IRQ(1)IUnused.
127IRQ(0)IUnused.
EMI Interface
128CPU BE(0)OBYTE 0 Enable
129CPU BE(1)OBYTE 1 Enable
130CPU RWOUnused.
131CPU WAITIWait state (connected to ground).
132CPU CE(3)OFlash ROM chip select.
133CPU CE(2)OFlash ROM down-load JIG module select.
134CPU CE(1)OUnused.
135CPU CE(0)OUnused.
138CPU RAS1I/O Unused.
139CPU CAS0OUnused.
140CPU CAS1OUnused.
141~148CPU DATA(0~7)I/O Flash ROM data input/output (0~7).
151~158CPU DATA(8~15)I/O Flash ROM data input/output (8~15).
161~170CPU ADR(1~10)OFlash ROM address (1~10).
173~181CPU ADR(11~19)OFlash ROM address (11~19).
5
DVR-8100
Pin No.Pin NameI/OPin Description
182,183CPU ADR(20,21)-Unused.
PIOs and communication
186PIO0(0) T STROBEI/O UART0 data
187PIO0(1) MOD SWI/O ATAPI RD
188PIO0(2)OUnused.
189PIO0(3) OUnused.
190PIO0(4) OUnused.
191PIO0(5) IUnused.
PIO0(6) SLIDER SENSOR
192OPEN/CLOSEI/O Detection port of slider sensor for DVD mechanism.
(DRAWER POSITION)
193
194PIO1(0) SDAI/O SSC0 data (MTSR out / MRST in)
195PIO1(1) SCLI/O SSC0 clock
I/O Control port of slider (IN) for DVD mechanism.
I/O Control port of slider (OUT) for DVD mechanism.
2. Pin Description of Main Microcomputer : CXP82860 (X09, IC22)
Pin No.Pin NameI/OPin Description
1,2NCNCUnused.
3VDDIPower supply (+5.0V)
4POWER DOWNIDetection pin for the power failure.
5RDS-CLKIRDS clock input.
6H/P CHKIDetection pin for the headphones.H/P IN
7RDS OPTIONISetting pin for RDS.RDSNO RDS
8REMOCONIRemote controller signal input.
9RDS-DATAIRDS data input.
10NCNCUnused.
11EEPROM CLKOClock output to EEPROM.
12,13ENCODE (1,2)IVolume encoder input.
14AMP PROTECTIDetection pin for the protection.
6
Logic
HL
PROTECTI
ON ON
CIRCUIT DESCRIPTION
DVR-8100
Pin No.Pin NameI/OPin Description
15SUPPLY PROTECTIUnused.
164586 CDTOIData input from level shift (X09, IC8).
17AK4586 INT0IError detection when digital input.ERROR
18AK4586 INT1IAudio bit validity detection for digital input.DETECTED
19AK4586 OVERLEVELIClip detection from AK4586 (X09, IC7).CLIP
20AK4586 DZF1IZero detection when digital input.ZERO
21DSP-INTREQIInterruption pin for DSP.
22SUB CPU CLKOClock output to sub CPU.
23SUB CPU DATA INIData input from sub CPU.
24SUB CPU DATA OUTOData output to sub CPU.
25DSP 493xxCLKOCommunication clock to DSP.
26DSP493xxDATA INICommunication data input from DSP.
27DSP493xxDATA OUTOCommunication data output to DSP.
28AD REFAV ref Power supply (+5.0V)
29,30KEY IN (1,2)IA/D key inputs.
31EEPROM DATAI/OEEPROM data input and output.
32TUNEDITuned signal input from tuner.
33OPT_DETI
34MODEL_OPTIONIUnused.
35PLL-DATA IN/ST CHKIControl data for tuner.
36STEP-OPTIONISetting pin for tuner.
37VSSAvssGND
38RSTIReset signal input.
39XTAL-INICrystal oscillator input (10MHz).
40XTAL-OUTOCrystal oscillator output (10MHz).
41VSSIGND
42NCNCUnused.
43GNDIGND
44VDDVDDPower supply (+5.0V)
45VFDP-GND
46BD3811_DATAOControl data output to BD3811 (X09, IC23).
47RELAY-FOControl pin for front speaker relay.RELAY ON
48BD3811_CLKOClock output to BD3811 (X09, IC23).
49BD3811_MUTEOMute control to BD3811 (X09, IC23).
50PLL-CEOChip select to PLL IC.
51PLL-CLKOClock output to PLL IC.
52PLL D OUTOControl data output to PLL IC.
53AK4586CSOAD/DA chip select.
54AK4586RSTOAD/DA reset.
55~57VIDEO CTL(1~3)OSelect signal (1~3) for video selector.
58,59VIDEO MUTE (1,2)OMute signal (1,2) for video selector.
60AK4586 MST/SLVOUnused.
6110dB ATTOUnused.
62A_MUTEOAmplifier mute control.MUTE ON
63T_MUTEOTuner mute control.MUTE ON
64DSP 493xxRSTOReset output to DSP.
65~67DSP (A15~A17)OAddress output to DSP.
68STBY LEDOControl pin for standby LED.LED ON
69RELAY-ROControl pin for surround speaker relay.RELAY ON
70PACK CONTROLOMute control to TA2022 (X09, IC500~502).MUTE ONMUTE OFF
71RELAY POWEROControl pin to power relay.POWER ON
72SUB RSTOReset signal output to sub CPU.
73AK4586 CLKOData output to AK4586 (X09, IC7).
39EXTALIConnection pin for system clock oscillation crystal.
40XTALOConnection pin for system clock oscillation crystal.
41,43GND-GND
42NC-Unused.
44VDD-Positive power supply (+5.0V).
45VFDP-Power supply (-30V) for FDP.
46~53NC-Unused.
54~79P01~P25OSegment signal output for FDP.
80~86NC-Unused.
87G15OGrid signal output for FDP.
88G14OGrid signal output for FDP.
89VDD-Positive power supply (+5.0V).
90~100G13~G03OGrid signal output for FDP.
✽ DVD Option Table
RegionR501
M2,E,T1.5K
M3.9K
M3,X6.8K
Logic
HL
8
DVR-8100
CIRCUIT DESCRIPTION
4. Pin Description of IC's
4-1 64 Bit SDRAM : HY57V641620HGT (DVD & VIDEO IC63)
Pin No.Pin NameI/OPin description
38CLKI
37CKE-
19CS-Enables or disables all inputs except CLK, CKE, and DQM.
20,21BA0,BA1-
22~26
29~35Auto-precharge flag : A10
16,17,18WE,CAS,RAS-WE, CAS and RAS define the operation.
15,39LDQM,UDQMI/O Controls output buffers in read mode and masks input data in write mode.
2,4,5,7,8,10
11,13,42,44
45,47,48,50
51,53
1,3,9,14,27
43,49
6,12,28,41,
46,52,54
36,40NC-Unused.
A0~A11-
DQ0~DQ15I/O Multiplexed data input/output pin.
VCC/VCC Q-Power supply for internal circuits and input buffers.
VSS/VSS Q-Ground terminal.
The system clock input. all other inputs are registered to the SDRAM on
the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
Row address : RA0~RA11, Column address : CA0~CA7
2VC1INIInput of C signal for S-video terminal (unused).
4NFBCG-Negative feed-back pin of amplifier (unused).
6VC2INIInput of C signal from video driver.
8VC3INIInput of C signal for S-video 1 terminal.
10VC4INIInput of C signal for S-video 2 terminal.
12VC5INIInput of C signal for video (unused).
14VC6INIUnused.
15GND2-GND
16MUTE-Mute time constant changing pin.
17~19MUTE(3~1)-Switching pin of mute.
20CTL 3IVideo switch control 3 input.
21CTL 2IVideo switch control 2 input.
22CTL 1IVideo switch control 1 input.
23VC02OOutput of C signal for monitor output.
24VC01ORec output of C signal for S-video 1terminal.
25-VCC-Negative power supply.
26VB02OOutput of Y signal for monitor output.
27VB01ORec output of Y signal for video 1.
28-VCC-Negative power supply.
29VA02OMonitor output to video 2.
30VA01OREC output to video 1.
33VCC-Positive power supply.
35VA6IUnused.
37NFB(G)-Negative feed-back pin of amplifier (unused).
39VA5 INIInput of video signal (unused).
41VA4 INIInput of video signal for video 2.
43VA3 INIInput of video signal for video 1.
45VA2 INIInput of CY signal from video driver.
47VA1IInput of video signal for composite (unused).
50VB1INIInput of Y signal for S-video terminal (unused).
52NFBBG-Negative feed-back pin of amplifier (unused).
54VB2 INIInput of Y signal from video driver.
56VB3 INIInput of Y signal for S-video 1terminal.
58VB4 INIInput of Y signal for S-video 2 terminal.
60VB5 INIInput of Y signal for video (unused).
62VB6 INIUnused.
63VCC4-Positive power supply.
NC-Unused.
Internal Block Diagram
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