In compliance with Federal Regulations, following are reproduction of labels on, or inside the product relating to laser
product safety.
Miniature phone jack
(E11-0905-05)
Slide switch
(S31-2630-05)
Pin jack *
(E63-)
Caution : No connection of ground line if disassemble
the unit. Please connect the ground line on
rear panel, PCBs, Chassis and some others.
Pin jack
(E63-1217-05)
Metallic cabinet *
(A01-)
Pin jack *
(E63-)
KENWOOD-Corp. certifies this equipment conforms to DHHS
Regulations No.21 CFR 1040. 10, Chapter 1, subchapter J.
Cylindrical receptacle *
(E56-)
Pin jack *
(E63-)
Slide switch
(S31-1623-05)
* Refer to parts list on page 64.
AC power cord bushing
(J42-0083-05)
Pin jack *
(E63-)
AC power cord *
(E30-)
DANGER : Laser radiation when open and interlock defeated.
AVOID DIRECT EXPOSURE TO BEAM.
Standard remote
control unit (1)
Keyboard remote control unit(1)
REMOTE CONTROL UNIT RC-KB2
Audio cable
DV-5900M.............................(3)
DV-5050M/DVF-6050............(1)
(E30-0505-05)
Video cable(1)
(E30-1427-05)
RS-232C cable(1)
(E30-7209-05)
System control cable(2)
(E30-2816-05)
S-Video cable(1)
(E30-2956-05)
Coaxial cable(1)
(E30-2365-05)
DV-5900M only
Batteries (R03/AAA)(2)
Batteries (R6/AA)(2)
(DV-5900M only)
(A70-1486-05): RC-D0512.....KYEM
(A70-1488-15): RC-D0513.....K1
(A70-1513-05): RC-KB3.....K1
Battery cover (A09-1176-08)
Battery cover (A09-1242-08)
AC Plug Adaptor (1)
(E03-0115-05)
Use to adapt the plug on the
power cord to the shape of the
wall outlet.
(Accessory only for regions where
use is necessary.)
For countries other than U.S.A., U.S.-Military,
DV-5050M/5900M/DVF-J6050/J6050-G
CLASS 1
LASER PRODUCT
The marking of products using lasers
(For countries other than U.S.A., U.S.-
Military and Canada)
The marking this product has been classified as Class 1.
It means that there is no danger of hazardous radiation
outside the product.
CAUTION
VISIBLE LASER RADIATION
WHEN OPEN. DO NOT
STARE INTO BEAM.
Location: Back panel
Inside this laser product, a laser diode classified as Class
2 laser radiation is contained as alerted by the internal
caution label shown above. Do not stare into beam.
• While holding down the "LIBRARY" key depressed,
plug the power cord into the socket.
POWER ON
óí"INITIALIZE"
The rotary tray turns.
ó
The rotary tray stops at disc 1 position.
ó
The microcomputer is initialized.
2. Test Mode
• This model has 3 kind of test modes : unit inspection,
factory test mode, measurement.
• In this manual, items of repair, test mode and inspection are available.
2-1 Setting Method
2-1-1 FCT Mode (Factory Mode)
• While holding down the MUSIC TYPE key depressed,
plug the power cord into the socket.
2-1-2 Inspection Mode
• While holding down the TEXT DISPLAY key
depressed, plug the power cord into the socket.
2-2 Cancellation of the Test Mode
• Unplug the power cord from the power socket.
2-3 Key Operation During the Test Mode
• During the test mode, it can be operated in a special
manner that is different from an ordinary operation by
using the keys on the panel, specifically as shown in
the following table.
FCT Mode
KeyModeDisplayOperation
PLAY-Playback timeDisc playback
All segments light î
TEXT DISPLAY-Niagara mode îDisplay shows cyclically by pressing key.
Playback time î
SKIP UPPlaybackPlayback timePlayback next chapter/track #/program #
SKIP DOWNPlaybackPlayback timePlayback before chapter/track #/program #
STOP-Playback timeStop to operate and return to first step of this test mode.
RANDOMPlaybackMute ON îMute OFFMute works cyclically on or off.
USER FILE-
TIME DISPLAY-
DISC FLIP-OK or *** ERRORSelf check mode (Refer to Servo Error Code)
PLUS1 PLAY-S-CWThe stocker motor turns clockwise.
PLUS1 EJECT-S-CCWThe stocker motor turns counterclockwise.
PLUS2 PLAY-OPENThe door opens.
PLUS2 EJECT-CLOSEThe door closes.
PLUS3 PLAY-0°î180°0°î180°operation of clamper motor.
PLUS3 EJECT-180°î0°180°î0°operation of clamper motor.
OPEN/CLOSE-UNLOADUnload operation of loading motor.
EJECT-LOADLoad operation of loading motor.
WIDE1îWIDE2
NORMAL
SCART RGB îSCARTVideo signal of SCART changes cyclically
Key MatrixThe number inside ( ) is pin number of FL driver & display u-com (X14, IC1).
0DVD VIDEOSTOPPAUSEPLUS1 PLAY
0.76~0.913DVD AUDIOSKIP DOWEJECTPLUS1 EJECT
1.53~1.81CDSKIP UPDISC FLIPPLUS2 PLAY
Key0(Pin22)Key1(Pin21)Key2(Pin20)Key3(Pin19)
2.32~2.71MUSIC TAPELIBRARY-PLUS2 EJECT
3.12~3.57USER FILETEXT DISPLAY-PLUS3 PLAY
3.93~4.41SET-PLUS3 EJECT
7
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
4-2 Port Function of Main Microcomputer
Port No.Port NameI/OFunction
1A16OAddress bus of SRAM (X25, IC14).
2A17OAddress bus of SRAM.
3SCLOClock output for audio/video switching IC.
4SDAI/O Data input/output for audio/video switching IC.
5RDORead strobe for SRAM (X25, IC14).
6WROWrite strobe for SRAM (X25, IC14).
7CSOChip selector for SRAM (X25, IC14).
8ASTB-Unused.
9VDD-Supply voltage (+5V).
10RGB HORGB signal output. DVF-J6050 (E/T) Only
11RWRREQORequest of transmission data to remote cont. microcomputer.
12RWRIRead-out the data of remote cont. microcomputer.
13RTRENIPermission of transmission data from remote cont. microcomputer.
14~21D7~D0OData output to remote cont. microcomputer (X14, IC2).
22VPP-Unused.
23STB LEDOControl port for power led.ON
24PURE LEDOControl port for pure audio led.ON
25192k LEDOControl port for 192kfs led.ON
2696k LEDOControl port for 96kfs led.ON
27ICRESETOReset signal output to display microcomputer (X14, IC1).RESET
28POWEROPower on/off control for regulator (X00, IC3).ON
29SUB WAKEOOutput port of power on signal to sub microcomputer.
30EXSWOSwitching port of (ext./int.) for video and audio output.INT.
31VMUTEOVideo mute control port.MUTE
32PURE AUDIO
33YC LOYC signal output. DVF-J6050 (E/T) OnlyOUT
34LINE2-Unused.
35WIDE1-Unused.
36WIDE2-Unused.
37VDD-Supply voltage (+5V).
38X2-System clock input.
39X1ISystem clock input.
40VSS-Connected to GND.
41XT2-Unused.
42XT1-Unused.
43RESETIReset signal input.
44REMIRemote control signal input.
45REM RCVIIR signal input.
46STB SUB INIStrobe signal input from sub microcomputer.
47PLAYIKey input (PLAY) port.ON
48OPEN/CLOSEIKey input (OPEN/CLOSE) port.ON
49POWER ONIInput port of power on signal from sub microcomputer.
50NC-Unused.
51AVDD-Supply voltage (+5V).
52AVREFO-Connected to VDD.
53SHIMUKEIDiscrimination of destination. K : 0V E : 5V
54KISYUIDiscrimination of model. DV-5050M : 5V DV-5900M : 2.5V
55M/S SWIInput port of M/S switch. MAIN : 5V SUB1 : 2.5V SUB2 : 0V
56PLUGCH-Unused.
57, 58NC-Unused.
59JOG1IEncoder signal input.
60JOG2IEncoder signal input.
-Unused. DV-5050M/DVF-J6050-
OPure audio on/off control port. DV-5900MON
Active
HL
8
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
Port No.Port NameI/OFunction
61AVSS-Connected to GND.
62LED DVDODVD active led control port.
63LINE3-Unused.
64AVREF1-Connected to VDD.
65SI0IData input from DVD microcomputer.
66SO0OData output to DVD microcomputer.
67SCK0IClock input from DVD microcomputer.
68SI1IData input from sub microcomputer.
69SO1OData output to sub microcomputer.
70SCK1I/O Clock input/output between main/sub microcomputer.
71STB SUBOStrobe signal output to sub microcomputer.
72STBOStrobe signal output to display microcomputer (X14, IC).
73SIIData input from display microcomputer (X14, IC).
74SOOData output to display microcomputer (X14, IC).
75SCK0OClock output to display microcomputer (X14, IC).
76~83A0~A7OAddress bus of SRAM (X25, IC14).
84~91AD0~AD7I/O Data bus of SRAM (X25, IC14).
92~99A8~A15OAddress bus of SRAM (X25, IC14).
100VSS-Connected to GND.
5. Sub Microcomputer: 703034AGFA01(X25-644/655, IC2)
5-1 Sub Microcomputer Periphery Block Diagram
X25, IC1
Active
HL
Main Microcomputer
uPD784217AGF519
S.DT 98
SCX0 99
DVM-01
STCKER MOTOR +56 R CCW
STCKER MOTOR -55 R CW
DOOR MOTOR +51 DOOR CLOSE
DOOR MOTOR -52 DOOR OPEN
CLUMP MOTOR +53 CLUMP -
CLUMP MOTOR -54 CLUMP +
LOADING MOTOR +57 UNLOADX25, IC13
LOADING MOTOR -60 LOAD
D 191 PWMIERX 26Daisy Chain
Q 168 D SWDrive IC
PH 170 PH 1IETX 27HA12187FP
PH 371 PH 3
PH 272 PH 2Microcomputer
S177 LOCK SWX25, IC12
S278 CLOSE SW
D289 EJECT LEDDSR 4DSR
S361 OPEN SWDTR 5DTR
S463 EJECT SWRXD 1 6TD
S564 0 SWTXD 1 7RD
S666 180 SW
S767 90 SW
S979 PL SW
S880 HP SW
S LED92 S LED
Sub
4 DSR
S.RQ 95
M.DT 97
5 DRT
6 RXD1
M.RQ 96
MAX232NS
PC Drive IC
7 TXD1
X25(IC12)
DSR
DTR
PC Drive IC
MAX232NS
RD
TD
9
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
5-2 Port Function of Sub Microcomputer
Port No.Port NameI/OFunction
1TXD0-No used.
2,3NC-No used.
4DSROPC link data set ready output.READY
5DTRIPC link data set ready input.
6TDIPC link data input.
7RDOPC link data output.
8NC-No used.
9EVDD-Supply voltage.
10EVSS-GND
11~20NC-No used.
21IC/VPP-Connected to VSS.
22~25NC-No used.
26IERXIDaisy chain IE bus data input.
27IETXODaisy chain IE bus data output.
49SCLOClock output for ROM correction.
50SDAI/OData input/output for ROM correction.
51DOOR CLOSEOControl port of door motor for mechanism.CLOSE
52DOOR OPENOControl port of door motor for mechanism.OPEN
53CLUMP -MOControl port of clump motor for mechanism.180°î0°
54CLUMP-POControl port of clump motor for mechanism.0°î180°
55R CWOControl port of rotary motor for mechanism.CW
56R CCWOControl port of rotary motor for mechanism.CCW
57UNLOADOControl port of load motor for mechanism.UNLOAD
58BVDD-Supply voltage.
59BVSS-GND
60LOAD-MOControl port of load motor for mechanism.LOAD
61OPEN SWIInput port of open switch for mechanism.OPEN
62NC-No used.
63EJECT SWIInput port of eject switch for mechanism.EJECT
640 SWI0°switch input of mecha, traverse.0°
65NC-No used.
66180 SWI180°switch input of mecha, traverse.180°
6790 SWI90°switch input of mecha, traverse.90°
68D SWIInput port of disc sensor for mechanism.
69NC-No used.
70PH 1IDetection port of stocker position.
71PH 3IDetection port of stocker position.
72PH 2IDetection port of stocker position.
73NC-No used.
74AVDD-Analog power supply.
75AVSS-Connected to VSS.
76AVREF-Reference voltage.
Active
HL
10
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
Port No.Port NameI/OFunction
77LOCK SWIInput port of stocker lock switch for mechanism.LOCK
78CLOSE SWIInput port of door close switch for mechanism.CLOSE
79PL SWIMechanism load clump position switch input.
80HP SWIMechanism home position switch input.
81~88NC-No used.
89EJECT LEDOControl port of eject LED.LED ON
90+BOOn/off control port of power supply for photo sensor (PH 1~3).ON
91PWMODisc sensor on/off control.ON
92S LEDOControl port of LED in the stocker.LED ON
93POWER OUTOOutput port of power on signal to main microcomputer.
94POWER INIInput port of power on signal from main microcomputer.
95SUB-STBIRequest signal input from main microcomputerREQUEST
96MAIN-STBORequest signal output to main microcomputerREQUEST
97SI0ISerial data input from main microcomputer.
98SO0OSerial data output to main microcomputer.
99SCX0ISerial clock input from main microcomputer.
13XRSTISystem reset input. L : Reset
15CLK81-Connected to digital ground.
16PLLAVDD-Main PLL supply voltage (+3.3v).
17TCPOUT0Unused.
18PLLAVSS-Connected to digital ground.
19CLK27ISystem clock input (27MHz).
20PLLTESTITest input port for main PLL. L : Fixed
21CKIOIDecode clock change-over.
22PLLVDD-Supply voltage (+2.5V) of internal logic for main PLL..
23,24HMD1,HMD0-Connected to digital supply voltage (+3.3V).
25XHINTOInterruption to DVD microcomputer. L : Active
26XDKOAcknowledgment to DVD microcomputer. L : Active
28XWRIWrite enable from DVD microcomputer.
29XRDIRead enable from DVD microcomputer.
30XCSIChip select from DVD microcomputer.
31HCLKIClock input from DVD microcomputer.
33~36,38~41,43~45HA1~HA11IAddress input from DVD microcomputer.
VDD-Digital supply voltage (+3.3V).
MA0~MA11OSDRAM address 0~11
VSS-Digital ground.
LVDD-Digital supply voltage (+2.5V) for internal logic.
PLAY
POSITION
HOME
POSITION
11
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
Port No.Port NameI/OFunction
47~51,54~59,61~65HD0~HD15I/ODVD microcomputer data bus 0~15.
67AUDSTRIValid signal of bit stream input data.
68ARQ0Unused.
69VSTRIClock signal input for bit stream.
71VRQORequest of program stream.
72AVRTMISector separation signal.
84EXTCKIExternal FS384 input terminal.
85APLLVDD-Supply voltage (+2.5V) of internal logic for Audio PLL..
86P5481-Audio PLL ground.
87PHCOPMOOAudio PLL phase comparison output.
88APLLAVSS-Audio PLL ground.
89NC-Unused.
90APLLAVDD-Supply voltage (+3.3V) for Audio PLL..
91ACKIO-Connected to digital ground.
92VSS-Digital ground.
93DCTEST-Connected to digital ground.
94,95TESTSEL1,0-Connected to digital ground.
97~102,106,108,109
103CLKMONOUnused.
107RFFOUnused.
110IECOUTOIEC958 format data output.
111DMIXOAudio down mix signal output.
113DACCKOOver sampling DAC clock output
114LRCKOLR clock output.
115SRCKOBit clock output.
117~119ADOUT(0~2)OAudio data output (0~2).
121XPOWDIDAC power down control input.
122VREFCIDAC reference voltage input for C signal.
123IREFCIDAC bias current setting port for C signal.
124COMPCICapacitance connection for DAC (C signal) stabilization.
125VCOUTOUnused.
126,136AVDD-Analog supply voltage (+3.3V) for DAC.
127VREFCBIDAC reference voltage input for CB signal.
128IREFCBIDAC bias current setting port for CB signal.
129COMPCBICapacitance connection for DAC (CB signal) stabilization.
130VCBOUTOUnused.
131,141AVSS-Analog ground for DAC.
132VREFCRIDAC reference voltage input for CR signal.
133IREFCRIDAC bias current setting port for CR signal.
134COMPCRICapacitance connection for DAC (CR signal) stabilization.
135VCROUTOUnused.
137VREFYIDAC reference voltage input for Y signal.
138IREFYIDAC bias current setting port for Y signal.
139COMPYICapacitance connection for DAC (Y signal) stabilization.
140VYOUTOUnused.
143XYSYNCOI/O Vertical synchronizing signal input/output.
144XHSYNCOI/OHorizontal synchronizing signal input/output.
146VCLKOClock output for digital video data output.
148~155VD0~VD7ODigital video data output (0~7).
158,159,161,162
164,165,167,168
170,171,173,175
177,178,180,181
TEST4~TEST9
TEST3,1,0
MDQ0~MDQ15 I/OSDRAM data bus (0~15).
OUnused.
12
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
Port No.Port NameI/OFunction
183MCKIIClock input from SDRAM.
185MCK OClock output to SDRAM.
187DQMLEOLower bite data, mask signal of expander SDRAM.
189DQMLMOLower bite data, mask signal of main SDRAM.
190DQMUEOUpper bite data, mask signal of expander SDRAM.
192DQMUMOUpper bite data, mask signal of main SDRAM.
193XWEOWrite enable signal of SDRAM.
195XCASOCAS signal of SDRAM.
196XRASORAS signal of SDRAM.
198XCSEOChip select signal of expander SDARM.
199XCSMOChip select signal of main SDARM.
183MCKIIClock input from SDRAM.
185MCK OClock output to SDRAM.
187DQMLEOLower bite data, mask signal of expander SDRAM.
189DQMLMOLower bite data, mask signal of main SDRAM.
190DQMUEOUpper bite data, mask signal of expander SDRAM.
192DQMUMOUpper bite data, mask signal of main SDRAM.
193XWEOWrite enable signal of SDRAM.
195XCASOCAS signal of SDRAM.
196XRASORAS signal of SDRAM.
198XCSEOChip select signal of expander SDARM.
199XCSMOChip select signal of main SDARM.
• Block Diagram
ODC, TS
Decoder etc.
System Controller
(Microprocessor)
SDRAM
(16bit)
Stream
Interface
Stream
Parser
Host
Interface
Memory
Interface
CD-DA
Video
and
Audio
Decoder
Sub- pictureREC656
Decoder(Digital Video Out)
Video
Interface
NTSC/PAL
Encoder
AudioDAC
Interface
IEC958
PLL27MHz
DAC
DAC
DACCr
Y/Y
Cb/Composite
C/C
Audio Out
(DAC for Audio)
13
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
6-2 Port Function of AV decoder : MN677533MP (X35, IC301) DV-5050M/DVF-J6050 only
Port No.Port NameI/OFunction
1,9,34,48,53,74,91,98,
111,156,160,166,172,VDD-Digital supply voltage (+3.3V).
179,184,191,197,205
2~4,6~8,10,201
203,204,206,207
5,19,24,29,44,52,58,
68,84,95,107,151,
157,163,169,176,182,
186,194,200,208
11,13,15~18,20~23TEST0~TEST9OTest terminal.
12XRSTISystem reset input. L : Reset
14,39,63,79,87,105,
146,174,188,202
25HMD1ISelect signal 1 from DVD microcomputer.
26HMD0ISelect signal 0 from DVD microcomputer.
27XHINTOInterruption to DVD microcomputer. L : Active
28XDKOAcknowledgment to DVD microcomputer. L : Active
30XWRIWrite enable from DVD microcomputer.
31XRDIRead enable from DVD microcomputer.
32XCSIChip select from DVD microcomputer.
33HCLKIClock input from DVD microcomputer.
35~38,40~43,45~47HA1~HA11IAddress input from DVD microcomputer.
49~51,54~57
59~62,64~67,69
70AUDSTRIValid signal of bit stream input data.
71VSTRIClock signal input for bit stream.
72VRQORequest of program stream.
73AVRTMISector separation signal.
99CLK27ISystem clock input (27MHz).
100PLLAVDD-Main PLL supply voltage (+3.3V).
101TCPOUT0Unused.
102PLLAVSS-Connected to digital ground.
103CKIOIDecode clock change-over.
104PLLVDD-Supply voltage (+1.8V) of internal logic for main PLL.
106CLK81-Connected to digital ground.
108APLLVDD-Supply voltage (+1.8V) of internal logic for Audio PLL.
109ATCPOUTOUnused.
110EXTCKIExternal FS384 input terminal.
112APLLAVDD-Supply voltage (+3.3V) for Audio PLL.
113ATVROUTOUnused.
114AVCOIN-Connected to digital ground.
115APLLAVSS-Connected to digital ground.
116VREFBIDAC reference voltage input for C signal.
117IREFBIDAC bias current setting port for C signal.
118COMPBICapacitance connection for DAC (C signal) stabilization.
119VBOUTOC signal output for DAC.
MA0~MA11OSDRAM address 0~11
VSS-Digital ground.
LVDD-Digital supply voltage (+1.8V) for internal logic.
HD0~HD15I/O DVD microcomputer data bus 0~15.
14
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
Port No.Port NameI/OFunction
120,130AVDD(1,0)-Analog supply voltage (+3.3V) for DAC.
121VREFGIDAC reference voltage input for Cb signal.
122IREFGIDAC bias current setting port for Cb signal.
123COMPGICapacitance connection for DAC (Cb signal) stabilization.
124VGBOUTOCb signal output for DAC.(Unused)
125,135AVSS(0,1)-Analog ground for DAC.
126VREFCIDAC reference voltage input for Cr, C signal.
127IREFCIDAC bias current setting port for Cr, C signal.
128COMPCICapacitance connection for DAC (Cr, C signal) stabilization.
129VCOUTOUnused.
131VREFYIDAC reference voltage input for Y signal.
132IREFYIDAC bias current setting port for Y signal.
133COMPYICapacitance connection for DAC (Y signal) stabilization.
134VYOUTOY signal output for DAC.
136NC-Unused.
137ACKIO-Connected to digital ground.
138MODE121IConnected to digital ground.
139PLLTESTIConnected to digital ground.
140,141TESTSEL1,0-Test mode terminal. L : Fixed
142DCTEST-DC test mode terminal.
143XYSYNCOI/O Vertical synchronizing signal input/output.
144XHSYNCOI/OHorizontal synchronizing signal input/output.
145VCLKOClock output for digital video data output.
147~150,152~155VD0~VD7ODigital video data output (0~7)
183MCKIIClock input from SDRAM.
185MCK OClock output to SDRAM.
187DQMLEOLower bite data, mask signal of expander SDRAM.
189DQMLMOLower bite data, mask signal of main SDRAM.
190DQMUEOUpper bite data, mask signal of expander SDRAM.
192DQMUMOUpper bite data, mask signal of main SDRAM.
193XWEOWrite enable signal of SDRAM.
195XCASOCAS signal of SDRAM.
196XRASORAS signal of SDRAM.
198XCSEOChip select signal of expander SDARM.
199XCSMOChip select signal of main SDARM.
MDQ0~MDQ15 I/OSDRAM data bus (0~15).
15
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
6-3 Port Function of DVD Microcomputer : MN102N62GGB (X35, IC201)
11FRD(ROM)OFlash ROM read port.
12WORD-Connected to VDD (+3.3V).
13~16CPUADR0~3OBus address (0~3).
17VDD-Supply voltage (+3.3V).
18SYSCLK(AVDEC)OClock output to AV decoder (X35, IC300).
19VSS-Connected to GND.
20XIIConnected to GND.
21XOOUnused.
22VDD-Supply voltage (+3.3V).
23OSCI(CLK135)ISystem clock input (13.5MHz).
24OSCOOUnused.
25MODEIProcessor mode selection.
26~33CPUADR4~11OBus address (4~11).
34AVDD-Supply voltage (+3.3V).
35~42CPUADR12~19OBus address (12~19).
43VSS-Connected to GND.
44CPUADR20OBus address (20).
4525BSYOBusy data output.Normal Busy
46STBPSLO
47HFMONOHF monitor output.
48KMODEOSelection for writing the ROM.Writing Normal
49AMUTEOAudio mute control.
50CIRCEN(ENC)OEnable to Digital Servo Controller (X35, IC1).
51PROGSWI
52STBTIO
53FRSWOFlash ROM 1, 2 (X35, IC207, 215) change-over.Default
54VDD-Supply voltage (+3.3V).
55FEPENOEnable to FEP (traverse).
56CLKSELOClock selection.
57STBDAC2O
58STBSP1O
NRD(ODC/AVDEC
/SRAM)
NWEH (ODC/AVDEC
/SRAM/ROM)
OBus read port.
OSelection port of clock (2:1). 0:0 33MHz, 0:1 36MHz,
Unused. DV-5900M
OBus read port.
Clock output to VDAC (IC600). DV-5050M/DVF-J6050
(X25, IC600) DV-5900M (X35, IC600)
Data output to VDAC (IC600). DV-5050M/DVF-J6050
(X25, IC600) DV-5900M (X35, IC600)
Unused. DV-5050M/DVF-J6050
Change-over the component terminal. DV-5900M
Unused. DV-5050M/DVF-J6050
Strobe output to MP3 decoder (X35, IC900). DV-5900M
Unused. DV-5050M/DVF-J6050
Strobe output to ADAC (X25, IC205). DV-5900M
Unused. DV-5050M/DVF-J6050
Strobe output to serial-parallel converter (X25, IC224). DV-5900M
Active
HL
Expan.
Mode
16
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
Port No.Port NameI/OFunction
59STBDAC1O
60ADSCEN(ENS)OEnable to Digital Servo Controller (X35, IC1).
61VSS-Connected to GND.
62WMINTI
63E2CSOChip select to EEPROM (X33, IC206).
64SCSIBNOEnable control to jig for writing the ROM.
65196BSYIBusy data input.Normal Busy
66VDD-Supply voltage (+3.3V).
67SCLK0O
68SI0I
69SO0O
70SCLK1OSIO1 clock output for control ICs.
71SI1ISIO1 data input for control ICs.
72SO1OSIO1 data output for control ICs.
73PULL UP0IUnused.
74PULL UP1IUnused.
75NMIIUnused.
76ADSCINTIInterruption port from Digital Servo Controller (X33, IC1).
77ODCINTIInterruption port from Optical Disc Controller (X33, IC101).
78AVINTIInterruption port from AV decoder (X33, IC301).
79ICRSTOReset signal output to periphery ICs.
80MP3INTI
81ADSEPIUnused.
82RSTIReset signal input.
83VDD-Supply voltage (+3.3V).
84~91CPUDT0~7I/O Bus data (0~7) input and output.
92VSS-Connected to GND.
93~100CPUDT8~15I/O Bus data (8~15) input and output.
Strobe output to ADAC. X25, IC204 (DV-5900M)
X25, IC203 (DV-5050M/DVF-J6050)
Unused. DV-5050M/DVF-J6050
Interruption port from Water Mark Detector (X35, IC500). DV-5900M
SIO0 clock output to communicate between main
microcomputer and DVD system microcomputer.
SIO0 data input to communicate between main
microcomputer and DVD system microcomputer.
SIO0 data output to communicate between main
microcomputer and DVD system microcomputer.
Unused. DV-5050M/DVF-J6050
Interruption port from MP3 decoder (X33, IC900). DV-5900M
Active
HL
17
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
6-4 Digital Video Enhancer : FL12220 (X35, IC703) DV-5900M only
• Port Function
Port No.Port NameI/OFunction
External OSD Interface
1~5OSDC(0~4)
156~160OSDC(5~9)
6OSDSEL-External OSD select input. (Connected to ground.)
144~153OSDY(0~9)-External OSD luma input. (Connected to ground.)
Test outputs(Not shown on Block diagram)
7~10TEST(03~06)
13~15TEST(00~02)
Test inputs(Not shown on Block diagram)
19TESTBIActive low test input. This pin should be tied to VDD for normal operation.
69,70,143TEST (0~2)IActive high test inputs. This pin should all be tied to VSS for normal operation.
Power Supply Connections(Not shown on Block diagram
11,28,40,49,59,60,81,
87,93,99,101,107,
113,119,121,127,supply and decouple to the digital ground plane.
131,135,141,154
12,29,41,50,79,80,82,
88,94,100,102,108,
114,120,122,128,
132,136,142,155
72ISINK-
68AVDD-Analog power connections for the clock PLL circuits.
74AVDD-Analog power connections for the video DAC circuits.
Control Signals
16SDAII2C compatible serial control bus data.
17SCLI/O I2C compatible serial control bus clock.
18,20MODE(0,1)-I2C operating MODE( 0,1).
21~23ADDR(0~2)-
24I2CCLKIClock input for the internal I2C circuit.
25RESETBI
67CLKINIMaster clock input.
139ENHOFF-When this pin is set low the FL12220 will be in normal enhancement mode.
Input Signals
26,27,30~37CBIN(0~9)I10-bit non-multiplexed Cb or multiplexed Cb/ Cr signal input bus.
43~48,51~54CRIN(0~9I10-bit non-multiplexed Cr signal input bus.
55~58,61~66YIN(0~9)I10bit luminance or multiplexed Y/Cb/Cr signal input bus.
6-5 Video Deinterlacer : FL12200(X35, IC700) DV-5900M only
• Port Function
Port No.Port NameI/OFunction
Test outputs
112,113TEST(00, 01)OThese pins are test outputs and should be left unconnected in normal operation.
Test inputs
41,50,51,108These pins are used for test purposes only and should always be tied low
109,111
Power Supply Connections(Not shown on Block diagram)
1,33,63,73,84,95
105,114,123,137VDD33-
144,151, 167
2,17,34,55,64,74
85 ,96,106,115
124,132, 138,145
152,159,168
43AVSS-Ground connection for the clock PLL circuits. Connect to the digital ground plane.
16,54,107,158AVDD25-
42AVDD-
Control Signals
49RESETBI
53OEO
56~58IFORMAT(2~0)IInput signal format control.
59~61OFORMAT(2~0)OOutput signal format control.
44,45DADDR(1,0)-
46MODE-
47SDAI2-wire serial control bus data.
48SCLI/O2-wire serial control bus clock.
40PIXCLKI Pixel clock input. This clock is used to drive all the circuits in the FL12200.
62N/P/IN/OUTI/ONTSC/PAL input or output.
Control Signals(contd.)
52NOMEMI No memory mode control input.
Input Signals
18~27G/YIN(0~9)I10-bit green or luminance signal input bus.
6~15B/CbIN(0~9)I10-bit blue or Cb chroma signal input bus.
28~32R/CrIN(0~4)
35~39R/CrIN(5~9)
3HSYNCREFIIHorizontal sync or reference.
4VSYNCREFIIVertical sync or reference.
5FIELDINIField identifier input.
89VREFO-Start of active field or frame indicator.
90HREFOOStart of active line indicator output.
20
TEST(0~5)-
VSS-Ground connections. Connect to the digital ground plane.
for normal operation.
Pad Ring digital power connections. Connect to the digital +3.3 volt power
supply and decouple to the digital ground plane.
Core Logic digital power connections. Connect to the digital +2.5 volt
power supply and decouple to the digital ground plane.
Analog power connections for the clock PLL circuit. Connect to a separately
decoupled +2.5 volt power supply and decouple directly to the AVSS pin.
Reset. When this input is set low it will reset all the internal registers
to the default states.
When this pin is set high the the outputs of the FL12200 will be enabled ; when
it is set low the outputs will be set into a high-impedance state.
The settings of DADDR(1,0) allow the device address of the control bus to
be programmed to prevent conflict with the other devices connected to the bus.
When this pin is set low the control bus will operate in the slave mode; allowing
the device to programmed from an external controller.
I10-bit red or Cr chroma signal input bus.
OGreen or luminance output bus.
OBlue or Cb chrominance output bus.
ORed or Cr chrominance output bus.
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
Port No.Port NameI/OFunction
91VSYNC/CREFOO
92H/CSYNCOO
110FILMOFilm mode detector output.
SDRAM Interface Signals
125~131ADDR(4~10)SDRAM address bus. This signal bus is used to address
118MEMCLKOOSDRAM clock and 2x output sampling clock.
119WEN-
120RASN-
121CASN-
122BSEL-SDRAM bank select.
Vertical sync output. This signal provides the vertical sync function
for the outputs.
Horizontal or composite sync output. This signal provides the horizontal sync
function for the outputs.
the external SDARM(s) used for field memories.
SDRAM data bus. This signal bus is used to transfer the data to and from
the external SDRAM(s) used for field memories.
SDRAM write enable. This active low signal should be connected
to the WE pin(s) on the SDRAM(s).
SDRAM row address select. This active low signal should be connected to
the RAS pin(s) on the SDRAM(s).
SDRAM column address select. This active low signal should be connected to
the CAS pin(s) on the SDRAM(s).
• Simplified Block Diagram
Ext. Syncs /
PIXCLK
10
RGB/YUV/Y
CrCb/D1
DADDR
SDA
SCL
PLL/Clock
PLl/Clock
Generator
Generator
/
/
/
2
/
Input
Signal
Formatter
Control
Interface and
Registers
Deinterlacer Core with DCDi
Motion Compensation, Film
Mode Detection and Bad Edit
Correction
TM
,
Sync
Generator
Output
Signal
Formatter
10
/
/
/
Sync Out
YU V
/RGB/
YCrCb
21
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
6-6 Port Function of Video Encoder /DAC : ADV7190 (X35-229, IC600) DV-5900M only
Port No.Port NameI/OFunction
1~16P0~P15I8 bit or 16 bit 4:2:2 multiplexed Y/Cr/Cb pixel port.
17,25,54,63VDD-Digital supply voltage (+3.3V).
18,24,33,55,64DGND-Digital ground.
19HSYNCI/OConnected to VDD.
20VSYNCI/OConnected to VDD.
21BLANKI/OConnected to VDD.
22ALSBIConnected to digital ground.
23TTXREQOConnected to VDD.
26,39,42AGND-Analog ground.
27CLKINIClock input.
28CLKOUTOUnused.
29,38,43VAA-Analog supply voltage (+3.3v).
30SCLISerial interface clock input.
31SDAI/OSerial data input/output.
32SCRESET/RTC/TRIConnected to analog ground.
34RSET2I
35COMP2OCompensation pin for DACs D, E and F.
36DAC FOS-Video C/V /RED analog output.
37DAC EOS-Video Y/U/ BLUE analog output.
40DAC DOComposite Y/GREEN analog output.
41DAC COS-Video C/V/ RED analog output.
44DAC BOS-Video Y/U /BLUE analog output.
45DAC AOComposite Y/GREEN analog output.
46COMP1OCompensation pin for DACs A, B and C.
47VREFI/OVoltage reference input for DACs or voltage reference output.
48RSET1I
49RESETIReset signal input.
50CSO HSOOUnused.
51VSO/ CLAMPI/OUnused.
52PAL NTSCIConnected to digital ground.
53NC-Unused.
56TTX IConnected to digital ground.
57~62NC-Unused.
Used to control full-scale amplitudes of the video signals from the DAC D, E,
and F.
Used to control full-scale amplitudes of the video signals from the DAC A, B,
and C.
22
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
6-7 Progressive Convert DAC : PM0026A (X25, IC601) DV-5050M/DVF-J6050 only
• Port Function
Port No.Port NameI/OFunction
1VDD3-Positive supply voltage (+3.3V) for pad ring.
2~8VIB9~VIB3IConnected to digital ground.
9~11GND-Digital ground for core.
12~14VIB2~VIB0IConnected to digital ground.
15,16DOS1, DOS0IConnected to digital ground.
17~19TEST2~TEST1IConnected to digital ground.
20VDD3-Positive supply voltage (+3.3V) for pad ring.
21VDD2-Digital positive supply voltage (+2.5V) for core.
22AGND-Analog ground for D/A converter.
23DAO YOY analog output.
24AVDD2-Positive supply voltage (+2.5V) for D/A converter.
25DAO BOCb analog output.
26AGND-Analog ground for D/A converter.
27DAO ROCr analog output.
28AVDD2-Positive supply voltage (+2.5V) for D/A converter.
29VREFIReference voltage input for 3DACs.
30FSADJI/OCurrent source for full scale adjustment of 3DACs.
31AVDD2-Positive supply voltage (+2.5V) for D/A converter.
32VGOCompensation pin for gate voltage of DAC current cells.
33AGND-Analog ground for D/A converter.
34CLMPOUnused.
35SPR7/V09OUnused.
36GND-Digital ground for core.
37~39
40,41VDD3-Positive supply voltage (+3.3V) for pad ring.
42GND-Digital ground for core.
43~45
46SPR0/V02O
47VO1OPixel data output.
48VO0OPixel data output (LSB).
49VDD3-Positive supply voltage (+3.3V) for pad ring.
50~52GND-Digital ground for core.
53RMA5IAddress input for monitoring internal register (MSB).
54~56RMA4~RMA2IAddress input for monitoring internal register.
57GND-Digital ground for core.
58CLKISystem clock input (27MHz).
59SRPISystem reset input (negative).
60VDD3-Positive supply voltage (+3.3V) for pad ring.
61VDD2-Digital positive supply voltage (+2.5V) for core.
62CSBIChip select input of MPU serial interface.
63SDATAIData input of MPU serial interface.
64SCLKIClock input of MPU serial interface.
65RMA1IAddress input for monitoring internal register.
66RMA0IAddress input for monitoring internal register (LSB).
67CKPOL-Internal clock. polarity control input.
68VIA9IPixel port A input (MSB).
69~76VIA8~VIA1IPixel port A input.
77VIA0IPixel port A input (LSB).
78NVSI/OActive low vertical sync.
79NHSI/OActive low horizontal sync.
80VDD3-Positive supply voltage (+3.3V) for pad ring.
SPR4/V06~Multi-purpose parallel output converted from serial data through MPU interface / pixel
SPR6/V08
SPR1/V03~Multi-purpose parallel output converted from serial data through MPU interface / pixel
SPR3/V05
O
data output.
O
data output.
Multi-purpose parallel output converted from serial data through MPU interface (LSB) /
pixel data output.
23
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
• Block Diagram for Progressive Convert DAC
MPU
Video
Decoder
MPU Interface with
Configuration register
Sync and Timing
Generator
Input
Interface
Signal Processor
Video Processing Engine
6-8 Port Function of 6ch DAC : PCM1602KY (X25, IC205) DV-5900 only
Port No.Port NameI/OFunction
1~6
7, 8NC-Analog ground.
9VOUT6OVoltage output for audio signal corresponding to Rch on data3. Up to 96 kHz
10VOUT5OVoltage output for audio signal corresponding to Lch on data3. Up to 96 kHz
11VOUT4OVoltage output for audio signal corresponding to Rch on data2. Up to 96 kHz
12VOUT3OVoltage output for audio signal corresponding to Lch on data2. Up to 96 kHz
13VOUT2OVoltage output for audio signal corresponding to Rch on data1. Up to 192 kHz
14VOUT1OVoltage output for audio signal corresponding to Lch on data1. Up to 192 kHz
15VCOMOCommon voltage output.
16NC-Analog ground.
17AGND5-Analog ground.
18VCC5-Analog power supply (+5.0V).
19AGND6-Analog ground.
20NC-Analog ground.
21AGND4-Analog ground.
22VCC4-Analog power supply (+5.0V).
23AGND3-Analog ground.
24VCC3-Analog power supply (+5.0V).
25AGNG2-Analog ground.
26VCC2-Analog power supply (+5.0V).
27AGND1-Analog ground.
28VCC1-Analog power supply (+5.0V).
29~32NC-Analog ground.
33MDOOSerial data output for function register control port. (Unused)
34MDII Serial data input for function register control port.
35MCIShift clock for function register control port.
36MLILatch enable for function register control port.
37RSTISystem reset input. (Active low)
38SCKIISystem clock input. Input frequency is 128, 192, 256, 384, 512 or 768fs.
39SCKOOBuffered clock output. (Unused)
40BCKIShift clock input for serial audio data.
41LRCKILeft and right clock input. This clock is equal to the sampling rate, fs.
42TEST-Test pin.
43VDD-Digital power supply (+3.3V).
44DGND-Digital ground for +3.3V.
45DATA1ISerial audio data input for Vout1 and Vout2.
46DATA 2ISerial audio data input for Vout3 and Vout4.
47DATA 3ISerial audio data input for Vout5 and Vout6.
48ZEROAOZero data flag. Logical "AND " of ZERO1 through ZERO6.
ZERO1~6Zero data flag for Vout 1~6. Can also be used as GPO pin.
/GPO1~6
O
(Unused)
24
Anti Copy
3ch 3ch 75Ω
D/A
Driver
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
6-9 Port Function of 2ch DAC : PCM1748E
Port No.Port NameI/OFunction
1BCKIAudio data bit clock input.
2DATAIAudio data digital input.
3LRCKIL-ch/R-ch audio data latch enable input.
4DGND-Digital ground.
5VDD-Digital power supply (+3.3v).
6VCC-Analog power supply (+5.0V).
7VOUTLOAnalog output for L-ch.
8VOUTROAnalog output for R-ch.
9AGND-Analog ground.
10VCOM-Common voltage decoupling.
11ZEROR/ZEROAOZero flag output for R-ch / Zero flag output for L/R-ch.
12ZEROL/NAOZero flag output for L-ch / No assign.
13MDIMode control data input.
14MCIMode control clock input.
15MLIMode control latch input.
16SCLISystem clock input.
1SURHOSurround on/off control
2H2CHOFront/Mix change-over (X25, IC212, 213) H : DOWN MIX L : L,R
3BASSODVD A BASS Management change-over DV-5900M only (X25, IC601)
4FRNTHOUnused