Kenwood DP-1100 B, DP-1100 II Service Instructions

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COMPACT DISC PLAYER

NOTE: Please replace this service manual with the old DP-1100's manual (B51-1592-00). This manual has all descriptions for DP-1100 and DP-1100II.

DANGER: Laser radiation when open and Interlock defeated. AVOID DIRECT EXPOSURE TO BEAM.

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MEANING OF ABBREVIATIONS

AFC: Disc motor speed control signal output from IC8 on process PCB
APC: Disc motor phase control signal output from IC8 on process PCB
BCK: Clock pulse on which music data is sent to D/A converter (Bit clock pulse)
CK4M: Clock signal of about 4 MHz for microprocessor (the signal resultant from 1/2 frequency division of X'tal OSC 8.4672 MHz)
CK88: About 88 kHz signal which is identical with signal WDCK (word clock pulse) output from IC6 on process PCB. It is used as clock signal for IC15 on servo PCB or as pseudo EFM signal.
CLS: Switch to inform opened or closed tray state. It is shorted with tray closed. ("L" with tray closed)
CLV: Circuit which makes the linear velocity of disc motor constant to provide constant reading rate of disc data.
DATA 12 and DATA 21: Signals for data communication (transmission and reception) between CPU 1 and CPU 2.
DATA: Signal line on which data is sent from process PCB to D/A converter.
DCON: Signal which is output from IC15 on servo PCB. It is normally "H" and becomes "L" when RF signal is lowered in level due to disc flaw. (Dropout control)
DIN: Signal line on which positional data of disc flaw is transmitted between disc flaw position memory circuit and IC15 on servo PCB.
DISK: Disc motor drive signal
DOCK: Clock pulse output from IC15 on servo PCB to disc flaw position memory circuit. It is a six times amplified signal of FGS. (Dropout clock pulse)
DOK: With disc provided, this pulse output is "L". Q1 on servo PCB detects the presence or absence of disc. (Disc OK)
DSG: Refer to "IC15 pin function" on page 68.
EFM, EFM 1 and EFM 0: Eight-to-Fourteen-Modulation signals. These are high-frequency signals or RF signals given from optical pickup.
EMPH: Pre-emphasis signal output from IC8 on process PCB.
F.COIL and T.COIL: Focusing and tracking coils control signals.
FE or F.E: Focus error signal
FG4: Signal resultant from 1/30 frequency division of signal DOCK. It controls disc motor drive signal.
FGS: IC15 input pin of FG signal from disc motor.
FOK: Focus servo control signal. Servo ON with signal FOK "'L''.

FOKG: Refer to "IC15 pin function" on page 69.

FSRH or FSRCH: 2 Hz signal to detect just focusing point. It moves the pickup actuator up and down.
IRQ: Interrupt control I/O pin between CPU 1 and CPU 2 (Interrupt request)
KGC: Inversion signal of signal RFG in IC15. It is normally "L" and "H" during kick of motor.
KICFB or KCIF: Refer to "IC15 pin function" on page 70.
LDC: Refer to "IC15 pin function" on page 69.
LRCK: Signal output from IC6 on process PCB. It indicates whether output data is for L-ch or R-ch.
MODE 4: IC15 control signal which is output from main CPU. (Refer to page 70.)
M5P: Disc motor ON/OFF control signal.
MUTE: Music signal muting signal.
OPEN: Switch which turns ON ("L") with tray open to inform opened tray state.
OPNS: Refer to "IC15 pin function" on page 68.
PLAY: Refer to "IC15 pin function" on page 69.
PLCK: Refer to "IC15 pin function" on page 71.
PU or P.U: Pickup.
PUD: Refer to ''IC15 pin function'' on page 68.
PUFB: Inversion signal of signal PUFF in IC15.
RES: CPU initialize signal
RFES: Refer to "IC15 pin function" on page 69.
RFG: Refer to "IC15 pin function" on page 70.
RFOK: This output becomes "L" when RF signal from pickup is input to IC10 (V2).
RMC: Output signal from remote control signal amplifier
S1 and S2: Pickup output signals emitted from preamplifier on mechanism PCB.
SCK: Clock pulse for communication between CPU1 and CPU 2. (Serial clock pulse)
SLT: Switch which turns ON (''L'') with pickup at innermost track.
START or STAT: IC12 control signal to enable SVC opera tion by main CPU. (IC12 ON at "H")
SVC (A, B, C and INH): Servo control
TE or T.E: Tracking error signal or tracking monitor pin
TEG 1 and TEG 2: Refer to "IC15 pin function" on page 68.
TEOP and TEON: Refer to "IC15 pin function" on page 68.
TEP: Refer to "IC15 pin function" on page 68.
TES: Refer to "IC15 pin function" on page 68.
TRAY or TRY: Disc tray or tray drive signal
TTAC: Refer to "IC15 pin function" on page 68.
WDCK: Signal output from IC6 on process PCB. Its fre quency is twice that of signal LRCK.

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Page 4

1 FUNDAMENTALS

1-1 SAMPLING

An analog voltage is continuous in respect to time, and has a value at each time of t₁, t₂, t₃, etc. as shown in Fig. 1.1 and as well a value at any time between t₁ and t₂.

If an analog voltage is represented corresponding to a code system, the analog voltage over the definite time range of t₁ to t₂ is made of the indefinite number of codes. In order to transmit a digital signal corresponding to the voltage at t₁, it needs a definite time length, but when transmitting indefinite codes, the transmission does not end forever.

Therefore, in case where an analog voltage is converted to a coded system, analog voltages at timings with some interval are only converted as shown in Fig. 1.2. With such a process, the definite number of codes corresponding to the definite timings, for example, five codes for the time interval t₁ to t₅ are produced.

When having transmitted codes described in Fig. 1.2, only five codes can be received at the receive side between t₁ and t₅. The number of voltage values reproduced thereby is only five, any voltage at timings except t₁, t₂, t₃, etc. cannot be determined.

However, if the frequency component (20 kHz) of the original analog signal is less than the value (44.1 kHz) depending upon the time interval between timings t₁, t₂, t₃, etc. at which coding is staged, even the value for non-transmitted portions can be reproduced. To pick up analog values at a fixed time interval by such a process is called "sampling".

1-2 QUANTIZATION

Fig. 1.3 indicates one example where analog signals ranging from OV to 10V are converted to 11-step voltage values of OV, 1V, 2V,...,9V and 10V via round-off. With this conversion, preparation of only 11 kinds of codes is needed. To convert an analog signal to a kind of a digital signal with the process of round-off or the like is called "Quantization".

Fig. 1.4

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1-3 SAMPLING THEOREM

The frequency of picking up an analog signal, for example, 50,000 times per second, is called "a sampling frequency. It is proven that if sampling is conducted at the rate larger than a certain value, the original waveform can be reproduced just the same to an inch. This is called "a sampling theorem".

Sampling Theorem: If sampling is conducted at the frequency (44.1 kHz) which is over double the maximum frequency (20 kHz) in a spectrum of a signal, the original waveform can be completely reproduced.

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II. FUNDAMENTALS

1-4 QUANTIZING NOISES

A rounding error is caused by quantization at sampling points as described in 1-2, and seeing Fig. 1.6 it can be thought that this rounding error is created as a distortion or noise. This

noise is of the nature different from noises emitted from an analog system, being called "a quantization noise".

The ratio of a quantizing noise against the maximum value of the signal in a binary-coded 16-bit system is plotted in respect to a sinusoidal wave input as shown in Fig. 1.7.

If a 16-bit code is used in quantizing one sampled value, the number of steps which can be taken, i.e., the quantizing number N is given as follows:

N = 2¹⁶ = 65536

When making the amplitude of 0 to V corresponding to this, the width E₀ of one quantization step is given by:

$E_0 = V/(N - 1)$

Therefore, the amplitude of a quantizing noise is E₀ at the peak-to-peak value, so that the noise power N₂ is:

Page 7

On the other hand, supposing that an input signal is a sinusoidal wave whose amplitude at the peak-to-peak value is V, the signal power S is:

$S = \frac{1}{2\pi} \int_{0}^{2\pi} \left(\frac{V}{2}\sin X\right)^{2} dX = \frac{V^{2}}{8}$

1-5 EFM (EIGHT TO FOURTEEN MODULATION)

To convert a level of an analog signal at every interval of a fixed period (1/44.1 kHz = 22.7 µs), as described in 1-4, to a binary code (1 and 0) after quantization is called a "PCM" (Pulse Code Modulation).

PCM has various kinds of modulation systems, but here a Sony and Philips jointly developed new system, called EFM, used for DAD is described.

Therefore, the power ratio is:

$\frac{S}{N_Q} = \frac{V^2}{8} / \frac{E o^2}{12} = -\frac{3}{2} (N-1)^2$ $D = 10 \log \frac{S}{N_Q} = 10 \log \frac{3}{2} (2^{16}-1)^2 \div 9.8 d$

Role of Margin Bits

The purpose of the margin bits is to reduce a DC component and low frequency components by adding three additional bits to the signals converted into EFM.

Channel Bits

One of 14 bits converted from 8 bits is called a channel bit.

(1) EFM is the modulation to first divide a 16-bit datum (data bit) into two 8-bit data and then convert each of these 8-bit data to a 14-bit datum (channel bit) as shown in Fig. 1.8. The conversion is to select patterns of 2⁸ kinds among patterns of 2¹⁴ kinds, meeting the following condition. Channel bits of 2⁸ meeting this condition have been predetermined by a computer as indicated in Tables 1-1 and 1-2:

Two or more but 10 or less 0s (zeros) should be always inserted between channel bits 1 and 14.

(2) Three channel bits are always inserted between 14-bit blocks. The role of these 3 bits is to make adjustment so that the above condition (enclosed in the box) is met even at the connection of blocks.

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II. FUNDAMENTALS

	8 bit	s→14 bits
Order	data bits	channel bits
0 1 2 3 4 5 6 7 8 9 10 11 2 3 4 5 6 7 8 9 10 11 2 3 4 5 6 7 8 9 10 11 2 13 14 5 16 17 8 9 0 11 2 2 2 3 4 5 6 7 8 9 10 11 2 2 2 3 4 5 5 6 7 8 9 10 11 2 2 2 3 4 5 5 6 7 8 9 10 11 2 2 2 3 4 2 5 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3
	♥ d1d8	★ ↓ C1C14

		8 bits⊶14 bits
	Order	data bits	channel bits
	64 65 667 688 69 70 71 723 74 75 76 77 78 79 80 81 82 83 84 85 88 90 91 92 93 94 95 96 97 98 90 101 1023 104 105 106 107 1023 114 115 116 117 122 123 124 126	01000000 01000001 0100001 0100001 0100001 01000101 01000101 01000101 010010
L	127	01111111	00100000000010

EFM Conversion table 0 to 127 (NRZ-1 represantation)

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II. FUNDAMENTALS

	8	bits→14 bits
Order	data bits	channel bits
128 129 130 131 132 1334 1356 137 1389 140 142 143 145 147 143 1445 1457 1534 1557 1556 15789 161 1623 1667 1667 1667 1773 1756 1777 1789 1881 1883 1885 18890 191
		▼ C1 C14

C1	is	first	cut
	13	mat	cut.

EFM Conversion table 128 to 255 (NRZ-1 representation)

cf: NRZ Non Return to Zero


	8 bi	ts→14 bits
Order	data bits	channel bits
192 193 194 1956 197 198 200 202 203 204 205 206 207 208 210 211 212 213 214 215 2167 218 219 2203 221 212 214 215 2223 2224 2226 2227 2228 2229 231 232 2334 235 66 237 238 239 240 241 243 244 245 244 245 244 245	11000000 1100001 1100001 1100001 1100010 1100010 1100010 1100010 1100010 1100100
247 248 249 250 251 252	11110111 1111000 11111001 1111010 11111010 11111011 111111	00100010010010 01001000010010 100000000
253 254 255		00001000010010 00010000010010 0010000001001

data bits

channel bits

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II. FUNDAMENTALS

1-6 FRAME SYNCHRONIZATION AND FRAME STRUCTURE

Reproduction signals cannot be recovered RF signals do not come out for a long time due to dropout or one information bit has been shifted owing to jittering in digital recording or playback. Because one bit shift of a digital signal makes the signal quite different in its signal level.

Therefore, by dividing a recorded signal to many small blocks, the system is organized so that even when a signal is disturbed due to jittering or the like, a bit synchronization is always estabilished at the new block to identify the joint part between blocks. Such a block is called a ''Frame''. Frame Sync signals are inserted to indicate the boundary of the frame and to make a bit synchronization. Fig. 1.9 shows the structure of one frame.

	Channel bits	Margin bits	Total bits
Frame Synchro- nization	24	3	27
Users buts	14	3	17
Data bits	14 bit x 24 = 336	3 bit × 8 = 24 = 72	408
Error correction bits (Parity bits)	14 bit×8=112	3 bit x 24	136
	486	102	588

Frame Structure

Fig. 1.9

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1-7 COMPACT DISC (CD)

1. There are many kinds of DAD systems: CD, MD and AHD. (Refer to Fig. 1.10)
2. DP-1100B/II adopts the CD system. The CD system is also called ''a light system''. A light beam from a semiconductor laser is converged with an objective lens to hit pits inside a disc for using their reflected light.
There are no groove in the CD system hit pits. Size of Pit: Width 0.5 μm, Length: 0.9 to 3.3 μm, Depth: 0.1 μm
4. Laser beam is hit through a transparent disc layer to read out data. (See Fig. 1.11)
5. Construction of disc. (See Fig. 1.11)
6. Disc baseplates are usually made of PC (polycarbonate), PMMA (acryl) is superior for a disc baseplate, but its

moisture absorption causing bend is a big defect. (Refer to precautions on handling the disc.)

7. Playback time is 60 minutes with a 120 mm disc. Dimensions are given in Fig. 1.12.
The rotating speed of the disc is not constant. Because of a constant linear velocity system employed, the rotating speed is varied between around 500 to 200 r.p.m. (counterclockwise) CLV (constant linear velocity): capstan drive type taperecorder CAV (constant angular velocity): rim drive type taperecorder.
9. PU (pickup) does not contact a disc surface but traces a track moving from inner radius to outer radius.
How much effectively does it use a laser beam? It depends upon the transmission factor, reflection factor and double refraction.

Fig. 1-11

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Fig. 1.12

Lead In: TOC (table of contents) → Absolute time of the heading of music is included. Lead Out: Used for retrieving of the heading indicates of program end. Other → Control Data P, Q

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11.

12. Double Refraction

The rating of double refraction is represented by a light path difference (mm). Rating: 100 mm

The main cause of double refraction is mold distortion. Fig. 1.14

Fig. 1.14

13. CD is tough against dusts Fig. 1.15(a) and (b)

(a) In a case where dusts are deposited on the disc surface

14. Fabricating process of baseplate. Fig. 1.16

15. Mastering: Procedures for Photo-resist coating, laser recording and development are included. This is corresponding to the fabricating process of a lacquer disc in an analog record production.
16. Molding: Injection molding Photo Polymerization

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II. FUNDAMENTALS

Fig. 1.16 Manufacturing Process of CD

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Fig. 1.17 Encoding system

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2 CODE ERROR

2-1 CAUSES OF CODE ERROR

(1) Defectives which are already present on a disc at delivery:
- Dusts attached to pits during production of disc.
- Disc molding distortion (entering of air bubbles whose refraction factor is not equal.)
(2) Faults created on handling of a disc: dusts, scratches, stains and finger prints.
(3) Level variations of reproduction signal (eye pattern) Because protection of out-of-tracking, Focus and CLV are all depending on a servo system, poor stability of the servo leads to increased code errors.

2-2 KINDS OF CODE ERROR

(1) Random Error: an error which causes an error in one bit
(2) Burst Error: an error which causes an error in many successive bits.

2-3 INTERLEAVE

Even if reading every page of a book slantwise from its upper left side to lower right side, you can fully recognize the context or contents. However, you cannot recognize the contents of the book if you are reading carefully one character or clause without reading several tens of pages.

An error collection code is the same as this, and correction is easy even when code errors of some bits are present. However, if many, say 1000, bits are consecutively wrong at a time, it is very difficult to correct those errors.

Therefore, the technique with which an order of a signal is once changed and then recorded and, after reproduction, returned back to the original order is employed. This changing of the order of a signal is called an "interleave", and the returning to the original order is called a "deinterleave".

Fig. 2.1 is the illustration explaining the principle of interleave. The order of a signal at fabrication of the disc is out of order. Therefore, by deinterleaving the signal, successive code errors are disperesed, so that operation of error correction and associated jobs are made facilitative.

Signal words returned to their original locations (10 successive error words are dispersed.)

Fig. 2.1

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2-4 SINGLE ERASURE CORRECTING METHOD

Bill (a) as shown in Fig. 2-2 indicates prices of four kinds of articles A, B, C and D and the total. In bill (b), the price of article B disappears. This calls a disappearance or erasure. When the total amount is known, the price of article B can be found even if one figure is missed. In the coding theory, wether the total amount is correct in bill (a) is checked. This operation is called "syndrome".
(2) In bill (b), the price of article B disappears. (It is indicated by B*. B* = 0) Conducting the syndrome does not creat S = 0 because there is an erasure. However, as the number of erasure is one, the amount of B* can be found from syndrome S = -200. According to the single diserasure correcting method, operation of correction is conducted on the assumption that all other data (A', C' and D') are correct. If there is an error for another article, miscorrection happens.
(3) Operating the syndrorme on bill (c), zero does not come out. Therefore, it may be found that something is wrong, but it cannot be found which of A', B', C', D' and P' is incorrect. In such a case, correction is infeasible.

(4) Bill (d) illustrates the example that the location to be corrected is known, and the correction can be done by the same means as in bill (b). The means to indicate the location of error in such a way is called a "pointer".

In the examples of (1) to (4), "Total P" is used for check of error or erasure of data A, B, C and D. A word used for check and correction besides required data is called a "parity word" or a "parity bit".

Syndrome (Checking) S=A+B+C+D-P=0


			Bil	ll (b)
+	A' B* C' D'	¥ ¥ ¥ ¥	100 ? 300 400		◄ Disppearan
Tota	al P'	¥	1,000

Syndrome (Checking) S = A' + B' + C' + D' - P = 0 B = B* - S = 200

			Bill (c)
	A'	¥	100
	Bʻ	¥	300
	C'	¥	300
+	D'	¥	400
Tota	al P'	¥	1,000

S = A' + B' + C' + D' - P' = 0


			Bill (c	4)
	A'	¥	100
	В*	¥	300
	C'	¥	300
+	D'	¥	400
Tot	al P'	¥	1,000	-

S = A' + B' + C' + D' - P' = 100 B = B* - S = 200

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2-5 SINGLE ERROR CORRECTION, DOUBLE ERASURES

(1) In case of (3) in 2-4, correction is infeasible because the location of error is unknown. Even in such a case, the way by which correction is feasible is a single error correcting method. In 2-4, there is only one parity word, P. Besides this, a "Weighted Total Value", Q, is used. Because two parity words P and Q are used, there are also two syndromes S₁ And S₂.

Now suppose that there is an incorrect bill (b) in respect to a correct bill (b) and that the location of error (one) in bill (b) is unknown.

Supposing that the differences from original values are E_A, E_B, E_C, E_D, E_P and E_Q with respect to A', B', C', D', P' and Q', respectively, of bill (b) (for no error, E_A, to E_Q=0) A' = A + E_A, B' = B + E_B, C' = C + E_C, D' = D + E_D, P' = P + E_D, Q' = Q + E_Q

Obtaining syndrome S₁,

S₁ = A' + B' + C' + D' - P' = (A + E_A) + (B + E_B) + (C + E_C) + (D + E_D) - (P + E_P) = A + B + C + D - P + E_A + E_B + E_C + E_D - E_P - E_P - (1) 0 = E_A + E_B + E_C + E_D - E_P

Obtaining syndrome S₂

S₂ = 4A' + 3B' + 2C' + D' - Q' = 4A + 3B + 2C + D - Q + (4E_A + 3E_E + 2E_c + E_D - E_Q) (2) 0 = 4E_A + 3E_B + 2E_c + E_D - E_Q

Supposing that a code error is one word between A' to P', Q'

(1)	A' wrong	S ₁ = E _A , S ₂ = 4E _A
(11)	B' wrong	S ₁ = E _B , S ₂ = 3E _B
(111)	C' wrong	S ₁ = E _c , S ₂ = 2E _c
(IV)	D' wrong	S ₁ = E _D , S ₂ = E _D
(VI)	P' wrong	S ₁ = E _P , S ₂ = 0
(VII)	Q' wrong	S ₁ =0, S ₂ =-E ₂

By a method where two syndromes are introduced as mentioned above and determined, wrong words can be found and corrected.


		Bill (a)
А	¥	100
В	¥	200
С	¥	300
D	¥	400
Ρ	¥	1,000
Q	¥	1,000

P=A+B	+ C	+ D
Q = 4A +	Q = 4A + 3B + 2C + D
	-

Syndromes S₁ = A + B + C + D - P = 0 S₂ = 4A + 3B + 2C + D - Q = 0

			and the second
			Bill (b)
A'	¥	100
Β′	¥	300
C′	¥	300
D'	¥	400
Ρ	¥	1,000
Qʻ	¥	2,000

Syndrome

S₁=A'+B'+C'+D'-P'=100 S₂=4A'+3B'+2C'+D'-O'=300

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(2) The principle of double erasure correction is described below. In this case, the location of error is indicated with a pointer. It is here known that two words in bill (c) are wrong and there are no other wrong words. Using equation (1) in paragraph (1).

$S_1 = A + B + C + D - P + E_A + E_B + E_C + E_D - E_P = 200$ O

Supposing E_A = 0, E_D = 0 and E_P = 0

S₁=E_B+E_c=200 _____(3)

From Equation (2) of (1)

S₂ = 4A + 3B + 2C + D + (4E_A + 3E_B + 2E_c + E_p - E_Q) = 500

S₂ = 3E_B + 2E_C = 500 _____ (4)

Determining E_B and E_c from simultaneous equations of (3) and (4),


			Bill (c)

A'	¥	100
B'	¥	300
Cʻ	¥	400
D'	¥	400
P'	¥	1,000
Q'	¥	2,000

Pointer

E_c=100

S₁=A' + B* + C* + D' - P' = 200 S₂ = 4A' + 3B' + 2C* + D' - Q' = 500 Where B* = E + E_B C* + = C + E_c

This theory is the principle of a Reed Solomon Code. In practice, the Reed Solomon Code with four parity words is used.

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2-6 CROSS-INTERLEAVE

(1) Fig. 2.2 shows a principle of a cross-interleave. An original series of signals is divided into a number of words, and parity words are inserted.

$P_{1} = W_{1} + W_{2} + W_{3} + W_{4}$ $P_{5} = W_{5} + W_{6} + W_{7} + W_{8}$ $P_{9} = W_{9} + W_{10} + W_{11} + W_{12}$ (5)

Four original series of signals (W₁, W₅, W₉, W₁₃...), (W₂, W₆, W₁₀, W₁₄,...), (W₃, W₇, W₁₁, W₁₅,...) and (W₄, W₈, W₁₂, W₁₆,...) among many original series of signals are arranged for four lines No. 1 via No. 4 in Fig. 2.2 of these words, the words passing through No. 1 are

delivered directly, but words fed into No. 2 to No. 4 lines are subject to delay with delay memories by one to three words so that the word order is changed (interleaved) at their respective terminals.

There is an adder following the delay memories, where another parity word Q is created.

$\begin{aligned} &\Omega_1 = W_1 + W_{-2} + W_{-5} + W_{-8} + W_{-15} \\ &\Omega_5 = W_5 + W_2 + W_{-1} + W_{-4} + P_{-11} \\ &\Omega_a = W_a + W_6 + W_3 + W_n + P_{-7} \end{aligned}$ (6)

In other words, two system of codes are used on both sides of the delay memories.

(2) Fig. 2.3 indicates relations between two parity codes. The solid lines mean a P's series, and the dotted lines mean a Q's series. Each of them has the capability of single erasure correction, so that an error of a single word can be easily corrected of course.

The	syndrome	of eac	h othe	's	series	can	be	used	as	а
pointer for pointing out a location of error.

Fig. 2.3 Code Series of Cross Interleave (Black circules indicate errors).

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3 BRIEF EXPLANATIONS ON CD PLAYER (See the BLOCK DIAGRAM)

3-1 PICKUP FOR CD APPLICATION

A pickup part corresponding to a cartridge for a conventional analog player is detailed later. Briefly speaking, this part allows the laser diode to emit a light beam (\u03c6 = 780 nm) and convert the intensity of the reflected light from disc pits into electric signals.

3-2 SIGNAL PROCESSING CIRCUIT

A signal detected at a pickup is delivered to a signal processing circuit, and split into the following three signals.

(1) Focus Error Signal
(2) tracking (Radial) Error Signal
(3) Radio Frequency (RF) Signal: This signal is processed to generate an analog signal.

3-3 SERVO CIRCUIT

3-3-1 Focus Servo Circuit

A focus error signal is fed into a focus servo circuit to control a lens system with the use of a focus servo coil (like a voice coil of a loudspeaker) so that the focus spot of the laser beam is

always kept on a pit surface against fluctuations due to the revolutions of a disc. (The same as auto-focusing in an EE camera)

3-3-2 Tracking Servo Circuit

Because a compact disc has no guide groove, it is needed to operate a servo so that a laser beam spot can automaitcally follow a signal track. A tracking error signal is fed into a track-

ing servo circuit, the output of which drives a tracking servo coil to operate the servo system.

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DP-1100B/11

II. FUNDAMENTALS

3-3-3 CLV Servo Circuit

Constant linear velocity (CLV) means to keep a line speed at a constant speed of approx. 1.2 m/sec.

For this purpose disc is rotated: approx. 500 r.p.m. at inside

radios approx. 200 r.p.m. at outside radios

The CLV servo circuit is the circuit to servo-control revolutions of the disc motor to keep circumferential speed of the disc constant.

3-4 EYE PATTERN

The RF signal is being delivered from the signal processing circuit as described under 3-2. The RF signal is vaired acording to appearance or disappearance of a pit on a disc. This signal can be displayed on an oscilloscope as illustrated in the Fig. 3-5.

The waveform is generally called "Eye Pattern".

Fig. 3-5 is sketches explaining concept of the eye pattern. The RF signal is converted to a digital signal composed of 1s and 0s with the aid of a comparator to generate an EFM signal.

Fig. 3.5

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4 SEMICONDUCTOR LASER (LASER DIODE)

4-1 PRINCIPLE OF LED LIMINESCENCE

A LED is formed with a P-N junction composed of an n-type semiconductor which allows electric conduction with electrons and p-type semiconductor in which holes serves electric conduction. Applying a voltage in the forward direction, electrons in the n-type semiconductor are injected into the p-type semiconductor, and holes in the p- type semiconductor are injected into the n-type semiconductor. Red luminescence is emitted when electrons injected into the p-type semiconductor tor combine with holes.

Green luminescence is emitted when holes injected into the n-type semiconductor combine with electrons.

Fig. 4.1

4-2 LASER DIODE

A laser diode, as mentioned 4-1 , is the same as an LED in terms of recombination luminescence of carriers, but different in that the light emitted is a coherent laser light, the phase of which is uniform (single wavelength).

4-3 PROPERTIES REQUIRED FOR A LASER DIODE

(1) Oscillation Wavelength

According to a CD's proposal, there should be the following relaiton between a wavelength of a laser diode and the number of aperture of lens NA: λ/NA = 1.75 μm

As long as today's GaAlAs material is used, it is difficult to make a laser diode having a wavelength shorter than apporx. 760 nm, but a laser diode with higher than 780 nm can be made in mass production.

Therefore, NA = λ/1.75 μm = 0.446

As the result, the objective lens in the pickup used in DP-1100B/II has been designed for approx. NA = 0.47 ± 0.01

(2) Operating Current

An laser diode has a threshold current I, with which oscillation starts, and with a current larger than this threshold level, a light power P increases linearly with increase of a current I. Furthermore, if keeping drive at a fixed current, the light outpout is greatly varied due to temperature increase. Therefore, control is always done so that the light output is kept constant.

Fig. 4.2 Oscillating Characteristic of a Laser Diode

Page 24

II. FUNDAMENTALS

5 PICK-UP (PU) AND PU SERVO

5-1 STRUCTURE OF A PICKUP

Light beams emitted from a semiconductor laser are changed to parallel light ralys by a collimator lens system and enter a polarization prism. Since the semiconductor laser beams are linear-polarized in the direction vertical to the plane of incidence, the beams are reflected by the polarizing film. The light beams reflected from another plane of the polarization prism pass through a quarter-wave plate, and then are converged to a spot of nearly 1.5 µm in diameter with the aid of an objective lens.

The light reflected from a disc passes again through the objective lens and follows the same path as the forward path to the polarizing film. By the effect of the quarter-wave plate, the light incoming into the polarizing film is changed so that its polarizing direction is perpendicular to the polarizing direction in the forward path. Therefore, the light transmits the polarizing film and does not go back to the semiconductor laser. Next, the light incoming into a critical angle prism for detection of a foucs point is reflected three times inside the prism and then fed into 4-divided photodiodes. The output of these photodiodes are used for controling a tracking servo coil and a focus servo coil to obtain an optimum focusing of the abjective lens on pits of the disc.

Page 25

II. FUNDAMENTALS

(1) Collimator Lens

Diffused light beams are changed to parallel light beams. Light beams distributed in oval pattern is changed to approx. circular distributions.

(2) Polarized Prism

Light polarized in parallel to a surface is reflected, and light polarized in vertical is passed through the prism.

(3) 1/4 Wavelength Plate

(4) Objective Lens

(5) 4-divided photodiodesConverts light into an electrical signal.

5-2 FOCUS ERROR AND TRACKING ERROR

To read tiny pits (width: 0.5µm, length 0.9#3.2 µm) on a disc by means of a laser spot, the location must be precisely controlled to follow surface and axial deviations of the disc caused by rotating the disc for playback. For this purpose,

(1) Focus error and(2) Tracking error
(2) Tracking error

must be detected. The detection muthods for both errors will be given below.

5-2-1 Focus Error Detection

When a light beam is passed from a high refraction material to a low refraction material, a relaion, as shown in Fig. 5.2, is existed between the incident angle and refleciton ratio at the boundary of the materials. As can be seen from the graphs, the reflection ratio will change rapidly as the incident light angle changes in the area where the incident angle is slightly less than the critical angle.

Fig. 5.2 Refleciton changes rapidly at angles dose to critical angle.

Page 26

II. FUNDAMENTALS

In Fig. 5.3, the angle of the critical prism has been adjusted so that the incident light angle is just equal to the critical angle for a center light beam of incident light. Accordingly, if parallel light beams are impinged, the incident light angle is equal to critical angle for all light beams and all light beams are reflected, giving equal light amount to each element of 4-divided photo-diodes (PDa, PDb, PDc and PDd). If diffused or divergent light is impinged, reflection strength at a left half of the prism lowers and light amount received by the photo diodes PDa and PDb will be decreased. On the contrary, if convergent light is impinged, light amount received by PDc and PDd is reduced. By utilizing this phenomenon, the photo diodes convert light received into four electrical signals and the signals are processed with a differential amplifier to provide a focus error signal in terms of (A₁ + A₂) – (A₃ + A₄).

(A₁, A₂, A₃, and A₄ Are electrical signals developed by PDa, PDb. PDc and PDd. respectively.)

θc: Criticl angle
-: Disc too close (point A) (divergent light beams....)
•: Focus point (point B) (parallel light....)
+: Disc too far (point C) (convergent light beams....)

Fig. 5.4 Focus error detection method using a critical angla prism

Page 27

5-2-2 Tracking Error Detection

Tracking error is a deviation of the reading light spot from the pits (track) to be traced.

In the Pickup a method called "heterodyne system" is adopted to detect the spot deviation from a pit.

The heterodyne system is based upon the distribution of the reflected light diffracted from a pit depends upon a relative location of the pit and spot.

In this system, each electrical signal converted by the 4-divided photodiode is assumed as A₁, A₂, A₃ And A₄, and A₁+A₃ and A₂+A Are evaluated. Namely, both phases for A₁+A₃ and A₂+A₄ are the same when the tracking is established, while phase difference will be caused when the spot deviates from a pit.

5-3 RF SIGNAL

A RF signal is a sum of each electrical signal A₁, A₂, A₃ and A₄ developed by the 4-divided photodiode (refer to 3-5). The RF signal is then processed to provide EFM signal. The EFM signal is then converted into an analog signal in passing through a D-A convertor after demodulated.

5-4 LIGHT EMISSION FROM LASER DIODE

When the LDC goes H, the output of TA75458(Q108) becomes positive as shown in the schematic diagram, And a current flowing through R145, D102, And D104 turns Q109 cut off, thereby stops the oscillation of the Laser Diode.

When the LDC goes to L level, the output of TA75458 (1/2) changes to negative, and this allows bias current of Q109 to flow from its emitter to the base, thus Q109 is turned on and the Laser diode emits infrared light (810 mm).

When light emitted from the laser diode is impinged to the pin diode, a current proportional to strength of the light flows from anode to cathode of the diode. With the strength of the light increased, a voltage developed across R113 also increases and makes non-inverted (+) terminal of the operational amplifier positive. As the result, the operational amplifier output also increases in positive, thus reducing the current flowing into the laser diode.

Page 28

6. GENERAL DESCRIPTION ON MICROPROCESSOR

6-1 Address Data (Q Signal)

1) Address Data (Q Signal) Reading Section

In the CD system specifications, one symbol consisting of 8 bits and located after frame synchronization signal of PCM data is called CONTROL & DISPLAY SYMBOL, and each of 8 bits is called P-Channel, Q-Channel,

R-Channel....& W-Channel. Of the eight channels, Q-Channel is used for address data and one address data is comprized of 98 frame Q-Channel data. Fig. 5.6 shows this configuration of the CONTROL & DISPLAY symbol data.

Fig. 6-1

Page 29

Address data format (outside lead-in area) are as follows:

S0, S1: 2 bits address signal sync pattern.

CONTROL: 4 bits control data, MSB indicates pre-emphasis on or off, and LSB indicates 4CH/2CH.

ADR:	4 bit mode data
	MODE 1 (1 in BCD): Adress mode
	MODE 2 (2 in BCD): Disc catalog number mode
	MODE 3 (3 in BCD): Special information mode (recorded by alphanumeric code 0#9, A#Z)
MNR:	Program number expressed by BCD in 2 digits (8 bits)
X:	Index for each program expressed by BCD in 2 digits (8 bits)
MIN:	Elapsed time (minute) for each program expressed by BCD in 2 digits (8 bits)
FRAME:	Elapsed time for each program expressed by BCD in 2 digits (8 gits) (Frame, 1 frame = 1/75 sec)
ZERO:	Not used (8 bits ødata)
A MIN:	Elapsed time (sec) for disc expressed by BCD in 2 digits (8 bits)
A SEC:	Elapsed time (sec) for a disc expressed by BCD in 2 digits (8 bits)
A FRAME:	Elapsed time for a disc expressed by BCD in 2 digits (8 bits) (frame).
CRC:	16 bit CRC code data calculated for data CONTROL #A FRAME.

Fig. 6-2 Shows the address data configuration.

Each figure under a code shows bit number required for the code.

S ₀ , S ₁	CONTROL	A D R	MNR	x	ΜΙΝ	SEC	FRAME	ZERO	AMIN	ASEC	AFRAME	CRC	S ₀ ,S ₁ -
	,		0		0	0	0		0	0	0	10
2	4	4	8	8	8	8	8	8	8	8	8	16

Fig. 6-2 Address Data configuration

Page 30

1. CIRCUIT DESCRIPTION

Subsequent to ''1-2 Head amp'', the servo PCB and the process PCB are described in order along the RF signal flow.

1-1 Head amplifier

The four signals from the pickup are input to preamplifier IC (Q103) on the mechanism PCB.

1-1-1 Focus balance and SVC operation circuit (Q103)

The internal block diagram of Q103 is shown in section 2-1-1. Through the resistors, connected between pins 1 and 2 and between pins 15 and 16 of Q103 (TA7731P), focus balance and SVC operation (described later) are performed. Weak signal is amplified and output to servo PCB as S1 and S2.

1-1-2 Focus error signal generation circuit (Q101 and Q104)

The FE amplifier and peak detector, consisting of Q101 and Q104, is a circuit to generate the focus error signal. Peak detection is made with the B-E diode characteristic of Q104 and the CR time constant of its emitter. The focus error signal is obtained from (C + D) - (A + B) operation of the picked-up four signals from the pickup by Q101.

1-1-3 SVC circuit operation (Q102)

The servo control (SVC) is performed by processor IC12 on the process PCB (X32-1010), when the disc is exchanged or

when play mode is entered from stop mode. It checks the number of data errors to control control inputs A, B, C and INH of Q102 on the mechanism PCB to obtain the optimum playback.

The internal block diagram and truth table of Q102 is shown in Fig 2-1 C and D of section 2-1-2. Inputs A, B, C and INH, determine which output 0 to 7 (bilateral switch should be internally connected with COM).

1-1-4 APC (laser power control) circuit (Q105, Q106 and Q107)

Q105, which is the laser ON/OFF switch, turns ON with "L" signal LDC (J8-3P) from the microprocessor so that the laser diode emits light. This laser diode incorporates a light emission monitor diode. Then, APC operation is performed by using the monitor output as the APC control input.

1-1-5 FG amplifier circuit (Q101 (2/2), Q108 and Q109)

FG signal is produced by Q101, Q108 and Q109 to monitor the rotation of the disc motor. Q101 performs amplification and Q108, Q109 and D104 perform waveform shaping. For adjustment of each trimming potentiometer, refer to "Adjustment" on page 165.

Fig. 1-1-3 SVC Circuit Operation

Page 31

1. CIRCUIT DESCRIPTION

1-2 Servo circuits

1-2-1 Focus servo circuit

The focus error (FE) signal, generated in the mechanism PCB, is fed into pin 8 of CN6 on the servo PCB. This signal is used in making signal DOK which the presence or absence of the disc is judged when the tray is closed.

With a disc present, "L" signal DOK is output from pin 1 of CN2 to pin 27 of IC15 on the process PCB (X32).

On the other hand, when the RF signal from the pickup is input to pin 20 of IC15, pin 12 (FOK) of IC16 is at -12 V and O2 turns OFF. Signal FE through focus gain adjustment potentiometer VR1 is amplified in IC1 (1/2) and input to IC2 (1/2) via the phase correction CR circuit. Then, the signal power-amplified in IC2 (1/2) drives the pickup actuator coil to form a servo loop including the optical pickup by which the laser beam is always focused exactly on the disc pit surface irrespective of the amount of disc warp, etc.

During light emission of the laser diode, the gate of FET Q4 connected to the LDC line is "L" so that IC2 (1/2) performs normal amplification. In addition, the gate of Q6 connected to the FOK line is at -12 V when RF signal is provided. Therefore, Q6 turns OFF and amplification is possible in the loop connecting IC1 and IC2, where the focus servo works.

1-2-2 Tracking servo circuit

Signals S1 (A + B) and S2 (C + D), produced by the preamplifier on the mechanism PCB, are fed into pins 6 and 7 of connector CN6. These signals are partially amplified by a 3-stage amplifier of inverter IC5 to generate the tracking error signal, then waveform-shaped by IC7 and input to TS1 and TS2 of IC15.

The tracking error signal is generated in IC15 and output from TEOP and TEON. This signal works as the tracking servo signal.

On the other hand, signals S1 and S2 are combined via R100 and R101 to extract music signal. The combined signal is input to IC6 which acts as an amplifier like IC5. After 1st stageamplification, it is further 2-stage amplified through the EFM test point via the second-stage amplifier which is biascontrolled by DSV and is input to pin 17 (EFM I) of IC15.

The tracking error signals output from pins 3 and 4 of IC15 (TEOP and TEON) are combined in IC12 (1/2). The combined output (TE) is phase-inverted in IC14 (1/2) and input via tracking gain trimming potentiometer VR2 to pin 6 of IC1 (2/2) in which it is phase-corrected and amplified.

Further, output of IC1 (2/2) is power-amplified in IC2 (2/2), Q10 and Q11. Amplified TE signal drives the pickup actuator coil to form a tracking servo by which the laser beam spot follows exactly the pit sequence on the disc.

1-2-3 DSV circuit (IC8 (1/2) and IC15 DLS 1 and 2)

Pits are made on a disc in such a way that the sum of "H" durations is equal to that of "L" durations i.e. DSV (Digital Sum Value) is zero. Thus, this circuit controls the amplifier bias so that the data on the disc is identical to that read by the player, thereby decreasing error.

1-2-4 Envelope detection

The signal from pin 4 of IC6 is further amplified and applied to the base of Q21. The variation in amplitude of the DC component, that is equivalent to the amplitude of the EFM signal wave, appears in the emitter of Q21. This DC component is amplified only in low frequency by IC8 (1/2) and applied to the gate of AGC FET Q33, thus reducing the change in EFM signal. In addition, the EFM signal is level-compared in IC10 (1/2). Then "L" at pin 1 of IC10 (1/2) informs to pins 20 (RFOK) of IC15 on SERVO (×29) PCB and 29 (RFOK) of IC15 on the process (X32) PCB through pin 1 of CN7 that the EFM signal is provided.

In addition, the EFM signal is also applied to IC10 (2/2) via diode D19 for level-comparing. Then, it is output from pin 8 as signal RFES. This signal is used in dropout control on play or used in the kick processing circuit at kick of motor.

1-2-5 Pickup carry motor driver

As play advances tracing the disc pit sequence by the pickup, a positive offset voltage appears at the output of tracking coil driver pin 8 of IC2 (2/2) by the tracking servo function. Since the high-frequency component, which is also contained in the tracking driver output besides the offset voltage, is unnecessary for driving the pickup carry motor, it is eliminated by an LPF amplifier of IC3 (2/2). Further, this output is power-amplified in IC4 (2/2) to drive the pickup carry motor.

In addition, Q14 is ON to avoid application of the tracking servo output signal during modes other than play. Signal PUFB, which is entered to the input of the power amplifier (pin 3 of IC4 (2/2)), is used in kick operation or fast movement of the pickup.

1-2-6 Disc motor driver

When pin 15 (MSP) of IC15 on the servo PCB emits an "H" signal according to the CPU command, the gate of Q17 becomes "L" and Q17 turns OFF. Disc motor driver IC4 (1/2) can amplify signal AFC emitted from IC8 on the process PCB due to start the disc motor. Due to shorten the start time or the stop time, a circuit consisting of Q19, C36, Q18 and R94 applies positive or negative pulse to the pin 7 of IC4 (1/2). (Positive pulse at motor's start Negative pulse at motor's stop).

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1100R/11

Page 33

1-2-7 Tray motor driver

3-state output situation in pin 9 of IC15 is used for driving the tray motor. The signal at "H" is inversion-amplified in IC3 (1/2) to drive Q16 to make pin 3 of CN4 negative so that the tray motor rotates in the direction in which the tray is closed. Conversely, the signal at "L" is also inversion-amplified in IC3 (1/2) to turn ON Q15 so that the tray motor rotates in the direction in which the tray motor rotates in the direction in which the tray motor rotates in the direction in which the tray motor rotates in the direction in which the tray motor rotates in the direction in which the tray motor rotates in the direction in which the tray motor rotates in the direction in which the tray is opened.

In addition, when pin 9 of IC15 is opened, pin 2 of IC3 is at zero voltage so that the tray motor stops since no voltage is applied.

1-2-8 Tracking error detector control

(This circuit is effective only at kick operation.)

Both IC12 (2/2) and IC13 (1/2) output "H" signals in normal operation. Thereupon, when the tracking error voltage at pin TE output goes up more than about +0.6 V, pin 2 of IC12 (2/2) becomes "L" and this voltage is applied to TEG 1 input of IC15. See "1" in the table below.

State	TE Voltage	TEG1	TEG2
1	>+0.6	L	Н
2	<-0.6	Н	L

Table-1
I UDIC I

Conversely, when the tracking error voltage at TE output goes down less than -0.6 V, pin 2 of IC12 (2/2) becomes "H" and pin 2 of IC13 (1/2) "L" so that this voltage is applied to TEG 2 input of IC15. See "2" in the table above. The search time is shortened by this control circuit. Normally, in play mode, this voltage is offset by signal TEP, therefore inputs TEG 1 and TEG 2 are invalid.

1-2-9 Peak hold circuit

The peak hold circuit consists of Q23 to Q26, D28 to D35, IC14 (1/2), etc. When KGC becomes "H" on kick state, Q23 and Q24 turn ON, and Q25 and Q26 turn OFF. Thereby, C70 is charged with the positive peak voltage at tracking error input TE and C69 is charged with the negative peak voltage. During kick, C69 and C70 are continuously charged with these peak voltages. When the unit returns to normal play from the kick state, Q23 and Q24 turn OFF and Q25 and Q26 turn ON. Then, the average value of the voltages at C70 and C69 is input to IC14 (1/2). Here, it is subject to subtraction with the value of voltage TE, so that the unit is restored to normal play from the kick state.

1-2-10 TE noise limiter

This noise limiter consists of IC14 (2/2) and Q27 to Q30. Q29 is the limiter ON/OFF switch. When signal TEP is "L" (during kick), no limiter operation is possible. Normally, Q29 is OFF during play.

The tracking error (TE) voltage is amplified to about 6 times in IC14 (2/2) and is applied to the bases of Q27 and Q28 through an HPF consisting of C73 and others. When the voltage goes up more than about +0.6 V, Q27 turns ON, while when it goes down less than about -0.6 V, Q28 turns ON. During that ON period, the peak noise of the voltage is suppressed so that the following stage gets free from the disturbance caused by this noise. Thereby, the pickup is prevented from jumping off the correct track to another one due to noise.

1-2-11 Disc flaw position memory circuit (See Fig. 1-2A.)

Signal RFES produced in IC10 (2/2) becomes "H" when the RF signal level is discreased by flaws or dust on the disc. This signal at "L" is output as signal DIN from the dropout control block in IC15 to the disc flaw position memory circuit in which positional data of flaw is stored. At the same time, this signal is also output as signal DCON which is the tracking servo gain reduction gate pulse. Dropout control is thus made. Pin DIN of IC15 outputs a signal indicating the RFES state at the rising edge of signal DOCK. It also checks the output of the disc flaw position memory circuit (pin 8 of IC7) at the falling edge of signal DOCK and then outputs signal DCON (pin 12 of IC15) to tracking servo amp circuit.

1-2-12 Relationship between servo and control line

For play, the actuator of the pickup is moved up or down by the 2 Hz signal from F.SRCH (pin 2 of CN2). At this time, when the disc is in rotation, the BE signal is output from the pickup only at the moment the laser beam is focused. With the RF signal. IC10 (1/2) outputs an "L" signal (RFOK) to turn ON Q31. Further, this signal is inverted at IC16 and FOK becomes - 12 V. Q2 and Q6 is turned off by "L" FOK signal, "H" LDC signal is inverted to "L" to turn Q4 off, so that the focus servo starts operation. Thus, a continuous RF signal appears at pins 6 and 7 of CN6 from the pickup. Thereby, pin 14 (FOKG) of IC15 outputs an ''H'' signal. This signal is inverted at IC16. The voltage at pin 11 of IC15 becomes - 12 V. Therefore, Q12 turns OFF so that IC2 (2/2) can perform amplification. In addition, DCON is "L" as long as the level of the RF signal does not drop suddenly due to flaws or dirt on the disc. As the KGC line is at -12 V in normal play (except for the kick state), Q7, Q8, Q9 and Q12 are all OFF. Thus, the tracking servo works so that the pickup traces the pit sequence on the disc. The data on the disc can thereby be read out continuously.

Page 34

1-3 PROCESS CIRCUIT

1-3-1 EFM signal demodulation

The EFM signal (EFMO) output from pin 41 of IC15 on the servo PCB is input to pin 52 (EFM 2) of IC8 and pin 14 (EFMI) of IC9 on the process PCB.

IC9 works as a digital PLL together with VCO Q3. Signal EFMI is phase-compared with signal PLCK (4.32 MHz) resultant from 1/4 frequency division of signal VCOI.

Here, when signal PLCK is delayed from signal EFMI, pin U_ovr becomes "L" and acts to make the VCO frequency higher. Conversely, when it is advanced, pin D_ovr becomes "H" and acts to make the VCO frequency lower.

The EFM signal output from pin D_ovr in synchronization with the rising edge of signal PLCK is fed to pin 53 (EFMI) of IC8, in which detection is made to a frame sync signal which is a continuous signal of 11 "H" bits and 11 "L" bits.

When the frame sync signal is obtained, the EFM signal is demodulated into an 8-bit signal. Moreover, the user's bits just after the frame sync signal are demodulated and data Q among them are displayed as time data bundled by 98 frames. These are also used in FF or BWD operation, etc.

The music data, converted from 14-bit to 8-bit signals, are written in jitter absorption memory IC7 under control of IC6 (TC9179F). The one-frame 32-symbol data is corrected for error in the C1 correction section. Next, after de-interleave operation, the data which could not be corrected in the C1 correction section is corrected in the C2 correction section.

Only the data which could not be corrected even in the C2 correction section is subject to mean-value interpolation and is output to the D/A converter.

1-3-2 CLV servo control in IC8 (TC9178F) a) AFC

The signal resultant from 1/4 frequency division of frame sync signal and the input signal (2.1168 MHz) from C21K are used here. Then, with the center of the count of 1152 clock pulses of C21K in respect to the former signal, pin 20 (AFCO) outputs a 0 V signal when the speed of the disc motor rises about 10% and outputs a 5 V signal with the same voltage as voltage VDD when the speed lowers about 10%. Thus, in the range of ± 10% change in motor speed, the output voltage corresponds to motor revolution (PWM wave).

b) APC

Phase-comparison is made between the signal resultant from 1/8 frequency division of the frame sync signal and the signal from a frequency division of signal C21K. The comparison output is emitted as PWM signal with 8-bit resolution. Here, VDD/2 (2.5 V) is output at a phase difference of zero in a control range of ±7/8 π.

In addition, the speed of the disc motor can be controlled by signal DIV + or DIV- from TC9179F. For information about TC9178F and TC9179F, refer to the diagram on pages 81 to 90.

Page 35

1-4 D/A converter

The serial music data, which is output from IC6 on the process PCB, is input to the D/A converter (IC21) at the falling edge of signal BCK. The data of one word is transferred to IC21 by repeat input at 16 cycles of signal BCK. After that, when signal CC drops down to "L", a pulse (DCR or DCL) is output with which the integrator output is discharged. Then, after clearing the previous sampled value, signal IOUTR or IOUTL is continuously output according to the level of signal LRCK during the time in proportion to the amount of the digital music data and is held as an analog voltage at integration capacitor C212 or C213. The example of waveform ① in Fig. 1-4A represents a sequence of this state. ② Fig. 1-4A shows the waveform when signal IOUTR or IOUTL is sampled by signal LRCK. When this PAM wave is filtered by an LPF,

this LPF outputs a music signal with a peak amplitude of 1/2 that of the PAM wave. This music signal is input to buffer amplifier IC27 to which a frequency characteristic compensotor CR circuit is connected.

IC26 controls the emphasized signal detected by IC8. Pin EMPH of IC8 outputs an "H" signal with a disc on which emphasized signals are recorded, and thus the de-emphasis circuit works. The muting relay connected to the output pin is controlled by the muting signal from the micro-processor. In addition, IC21 judges the music data as an R-ch signal while signal LRCK is "L". During this period, IC6 outputs L-ch signals. Therefore, signal IOUTR of IC21 is handled as an L-ch signal and signal IOUTL as an R-ch signal.

Fig. 1-4A D/A Converter Circuit

Page 36

Fig. 1-5-1-1

VÐD (4) (I5)Res

Fig. 1-5-1-2 Timing Chart for IC13 Reset Signal

When power switch $1 is turned on, +5 V and +8 V are supplied to the RESET circuit from the voltage regulated power supply circuit. The rising time and the falling time of the power supply voltages +5 V and +8 V are different (+8 V rises faster when turned off.) This creates a difference in operation timing to the microprocessor circuit (+8 V) and the analog circuit (+8 V). Diode D9 clamps +8 V until +5 V rises, so that the timing difference can be eliminated. When +5 V rises, it is supplied to the enviter of 05. O5 turns on, producing about 5 V at its collector. It is coupled to fin 14 O1Cl3 and puts it to "M" level. When the enviter of 05 is provided with about 5 V, the base voltage becomes about 4.4 V due to time constants R34 and C42. This "H" level grant is applied to the inverted output is obtained at pin 11, after going through pin 12, pin 11 is set at "1" level by R36, but it changes the level from "1." to "H". (This signal is termed reset signal.)
When the reset signal is "H" level, IC15 (TMP4740N), IC12, IC1 and IC15 (TC15G002AP-0007) start function-ing, IC15 (TC15G) is, however, reset via 011 in order to avoid the overheading at pin 11 of IC13. When 011 is OFF, modes 0 through 4 are at "L" level by means of on?
OHF, modes 0 through 4 are at "L" level by means of R97. 6. When power switch S1 is turned OFF, + 8 V drops, mak-ing the emitter voltage of Q5 also drop. When + 8 V drops by 1 V, the emitter voltage of Q5 goes down to about 4 V, because about 3 V discharge voltage is being provided by C102 connected across R118. Since the base voltage of Q5 is charged by C42, it does not drop vary quickly. Q5 is placed under OFF state. The collector voltage drops, mak-ing pin 13 of IC13 to "H" level and pin 11 to "L" tevel. LC15 (TMF4740N), IC12, IC1 and LC15 (TC15G) stop functioned.

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Page 37

1-5-2 TRAY OPERATION

1. When tray OPEN/CLOSE switch S004 is pressed, 01 When tray OPEN/CLOSE switch SO04 is pressed, 01 momentarily turns on and a key scanning signal available from pin 13 of IC1 is spylled to pin 29 of IC1. The signal put through pin 29 is processed in IC1 and its output is coupled to pin 39 of IC15 (TMP4740N) through pin 40.
through pin 40. The data signal fed through pin 39 controls pin 1 to 5 in IC15. (An instruction signal to IC15 (TC15G or T7001) is developed by a combination of pin 1 to 5.)


TRAY	OP	ENS	CLC	SES	Remarks
Mode	E	F	8	с	Refer to control MODE of IC15 (TC15G008AP) Table 2-2B and notes below.
1	L	н	L	L
2	н	н	L	L
3	н	н	L	н
4	н	н	н	н
5	1.	L	L	E.

The SLT (start limit) switch is ON, i.e. the tray is rotra-pickup is moved toward the center of the disc till picku, switch is on. This occurs when the tray is retracted witl disc by OPENICLOSE switch.
PLAY button o C: The laser diode

4. When the power is turned on and tray OPEN/CLOSE switch is pressed, the tray opens. When the switch is pressed agin, it closes. The operation is repeated alternately by every pressure of OPEN/CLOSE switch (SOA) 5. The OPEN/CLOSE function of the tray is achieved by combinations of ''H' and ''I' levels at pin 1 to 5 of IC15 (TMP4740N) as shown below. 6. The outputs from pin 1 to 5 of IC15 (TMP4740N) are applied to pin 24 to 27 and 30, and the output is then available at pin 9 of IC15 (IC15G or T7001). 7. Pin 9 of IC16 (IC15G of T7001) has a high impedience for the conditions other than the listed left. The Input 16 pin 3 of IC15 to provide pin 4 of IC3 with + 2.5 V. The comparative difference between voltages at pin 3 and 4 of IC3 is available at pin 2 as an output. Since the voltages at pin 3 becomes 0 V. When the voltage at pin 3 and y becomes 0 V. When the voltage at pin 3 is 0 V, 015 and 016 are OFF and the tray motor does not run with no power supplied.
pin 2 of IC3 is 0 V, O1b and 016 are 01+ and the tray motor does not run with no power supplied. 8. When the tray opens, pin 9 of IC15 ITC15G or IT7001) is at "1" level. It pulls down the potential at pin 3 of IC3 from 2.5 V down toward ground. The inverted output changing (from 0 V) toward plus appears at pin 2. It turns on 0.15. The motor revolves in the clockwise direction. (015 and 016 prevent overloading of pin 2 of IC3.)
Fig. 1-5-3 When the tray closes, pin 9 of IC15 (TC15G of T7001) is at "H" level. It pushes the voltage at pin 3 of IC3 from 2.5 V up toward power supply voltage. When the voltage at pin 3 becomes higher than that of pin 4 (2.5 V), the inverted output changing throm 0 V1 toward minus appears at pin 2.1 turns on 016 (while 0.15 is 0FF), providing the tray motor with a minus voltage, which comes from -12 V line through R72 and L2. The motor trevlows in the counterclockwise direction. Whon the OPEN/CLOSE function of the tray is completed by pressing the tray OPEN/CLOSE switch, a leaf switch provided on the tray turns 0N or OFF. The state of the switch is given to IC15 (TMP4740N) to control the signals at pin 1 to 5 and the motor stops revolving.

Page 38

P-11NNR/TI NP-11NNR/TI

1. CIRCUIT DESCRIPTION

Fig. 1-5-3-2 Timing diagram for LASER ON TIME

When a signal to activate the laser is applied to pin 24 to 27 of IC15 (TC15G or T7001) from the system control microprocessor, the level at pin 11 changes from "L" to "H" and the level at pin 3 of IC16 also switches from "L"

1-5-3 LASER ON OPERATION

"H" and the level at pin 3 of IC16 also switches from "L" to "H". IC16 output becomes +5 V [power supply voltage of IC16: V_po] at pin 13, when input pin 3 is at "L" level. When the input is "H" level, the output becomes open. The output at pin 13, however, becomes -12 V, since it is connected with a -12 V line through R230. When the voltage at pin 13 of IC16 charges from +5 V to -12 V, Q105 turns ON, {+12 V is divided by R129 and R130 to provide the emitter of Q105 with about 3 V. When the base voltage drops below 3 V+0.6 V, it makes Q105 turn ON.) Q106 also turns ON. When Q106 turns ON, a voltage is developed across R135 connected to the collector. Q107 switches ON and
D106 consists of two transistors with the identical characteristics, being used under the same conditions (same emitter voltage and current). Therefore, it functions to produce the same base voltage. When laser current control R128 is adjusted, the base voltage of the other transistor is also affected (the voltage is dotermined by R123, R124 and the laser monitor diode.) The values of R123 and R124 are properly selected depending on the pickup used. When a voltage is increased across R135 placed in the collector of O108, it provides the base of O107 with a voltage in accordance with this collector voltage. The collector current of O107 changes accordingly, thereby controlling the output of the laser diode increases, the internal resistance of the 38r monitor diode becomes small. The base voltage of 106 gets higher, thereby reducing the current through 0106. The voltage across R136 in the collector circuit drops and it provides the base of 0107 with a lower voltage. Its collector current is reduced to produce less output from the laser diode.

Page 39

1-5-4 FOCUS SEARCH OPERATION

When a disc is set and the tray is closed , a signal of 2 Hz is output maximum four times to pin 36 of microprocessor IC15 (TMP4740N). This signal confirms that the disc has been properly set and prepares for focus servo operation. The focus servo maintains a constant position of the pick-up lens against the disc so that the size of the focused laser spot is kept constant as a result. If the distance between the pickup and the disc is to far or too close, a proper size of the laser spot can not be obtained on the disc surface, in another words, not properly focused.

3. A proper size of the laser spot is provided on the disc sur
A proper size of the laser spot is provided on the disc surface by moving the pickup lens up and down using the 2 Hz signal. This is called focus search operation. Once it is focused, the search signal is discontinued. The output signal from pin 36 of microprocessor IC15 is applied to pin 4 of focus coil moves the pickup lens up and down. Its output appears at pin 2 and is applied across the focus coil moves the pickup lens up and down. C5 in the above schematic diagram cuts off the DC component of the signal and 16, C4, R14 and C6 form a LPF to eliminate frequency characteristic and phase characteristic applied pickup1 in the above diagram is for the focus servo purpose. Refer to focus servo operation (1-5-7).

Fig. 1-5-4-2 Operation Timing of Focus Search

Page 40

1-5-5 DISC DETECTION OPERATION & REVERSE-REVOLUTION PREVENTION CIRCUIT FOR DISC MOTOR

An RF signal is produced by adding output signals S₁ (A₁ + A₂) and S₂ (A₂ + A₁) from the 4-devision photodetec-tor through R101 and R100 and amplified to an adequate level. It is then envelope detected by Q21. The detacted signal is applied to pin 3 of IC10 (1/2). The bit or borth rhand, a signal of reference level (about 0.8 V), which is divided by resistors, is fed to pin 4 of IC10 (1/2). The other hand, a reference level (about 0.8 V), which is divided by resistors, is reference level (about 0.8 V), which is divided by resistors, is reference level (about 0.8 V), which is divided by resistors. The time convolupe of RF signal is over 0.8 V, ''.'' (about 0 V) output results and whon it is less than 0.8 V, ''H'' (about 5 V) results. The time constant for transition to ''H'' signal or to ''L'' signal is different. The time constant for transition to ''H'' is determined by C54 and R148, and the time constant for it to ''L'' is detormined by C54 and R140. The time constant for ''H'' is about 1000 times larger than that for ''L'''. This prevents the output from accidentally becoming ''H'' because of diropouts of RF signals caused by scart-ches or dusts. It also falls to ''L'' quickly, whon RF signal (RFOK Signal) is detected.

3. The HFOK signal is to judge the presense of RF signal as explained above. It results in "L" when the RF signal is present and it results in "H" when not present. Both of the MSP and RFOK signals are "H", when the disc motor starts running (initial start from a complete stop state.) Q31 and Q19 go to QFF, while Q18 is QN. This increases a negative voltage at pin 8 of IC4 (1/2), horeby preventing the disc motor from revolving in the reverse direction.

Page 41

1-5-6 FG & DISC MOTOR DRIVE AND STOP OPERATIONS

The frequency generator consists of a polarized magnetic ring attached to the rotating spindle of the disc motor and a printed pattern in the form of coil, which is provided at a relative position below the motor spindle. When the motor revolves, a 20 Hz pulsive current with is sent out per each revolution of the motor.
revolves, a 20 Hz pulsive current with is sent out per each revolution of the motor. 2. It is fed to pin 7 of Q101 and a sine wave signal with an amplitude cl ± 5 V is available at pin 8. It is converted into a pulse signal by Q108 and Q109, divided to a TTL level by R237 and R238 and then applied to pin 39 of RC15 (TC156 or T70011 as FGS. The FGS is 6 times multiplied in IC15 (TC156 or T70011 as GS. The FGS is 6 times multiplied in IC15 (TC156 or T70011 as GS. The FGS is 6 DCK contains pulses sper a revolution, the DCK contains 120 pulses per a revolution and the FG4 includes 4 pulses.
The DOCK is used to detect a dropout position (Refer to section 1-5-15). The FG4 is coupled to pin 14 of IC8 (TC9178F) of detect the revolution of the disc motor.

3. The revolution control of the disc motor is accomplished by APCO (from pin 19) and AFCO (from pin 20). Both of the signals are PWM (puise-width modulation) signals with a carner frequency of 8.27 Hz in the CLV mode. When a disc is revolving at a normal speed, both of the AFCO and AFCO are clock waveform signals with a frequency of 8.27 Hz at a 50% duty. Since the AFCO regulates a range of zero revolution to high revolution of the disc motor, it may be fixed at "H" or "L" level in some in-
motor, it may be fixed at "H" or "L" level in some instances. 4. The APCO and the AFCO are integrated by R85 and C33, and R86 and C32 respectively. They are then added via R87 and R88. The added signal is pot to pin 7 of IC4 (1/2). The output signal goes through a low-pass filter to regulate the disc motor revolution. C35 and R35 are for phase compensation. L204 is a noise filter.
5. Q17 is in an OFF state during normal play. It is QN when the disc motor is not running, providing Q V output from IC4 (122). This QN/QFF operation is achieved by MSP and FGS. MSP is an output signal made available at pin 15 of IC15 (TC156 of T7001) by the microprocessor. When it is at "I"" level, Q17 is turned OFF and the disc motor is driven to run.
6. Since the FGS provides 20 pulses per one revolution of the disc motor as explained previously, it makes pin 7 of IC16 "H" level through DA0 during the revolution of the motor and 017 is turned 0FF. If disc stops revolution and the FGS becomes "L", 017 turns 0N to stop the disc motor. Thus an accidental rotation of the disc by noises or disturbances is prevented.

Page 42

1-5-7 FOCUS SERVO OPERATION

When laser is ON and a focus search signal is given by microprocessor IC15 (TMP4740N), the reflecting beam from the surface of a disc is detacted by a 4 division photodetector and these signals are sent to pin 4 to 7 of head armp 0103 as a variation of current. Inside 0103, A, and A₂ are added and output from pin 1, A₃ and A₄ are ad-ded and output from pin 16 respectively. The output level from pin 1 of 0103 is varied by R₃, which is in twin chang-ed by controlling SVC switch IC (0102) from SVC control microprocessor IC12. The output level at pin 16 of 0103 is variable by R119 and focus error balance R120. The outputs from pin 1 and 16 of 0103 are input to each base of 0104 and the focus signal offset is adjusted by R118. The outputs from emitters of 0104 is input to 0101 to obtain the difference of S₁ and S₂ as focus error tFE) signal at pin 2 of 0101.
The FE signal is applied to pin 4 of IC1 (1/2), through focus gain adjustment trimming potentiometer VR1 and R2 for monitoring gain adjustment. O1 turns ON to inform microprocessor IC15 (TMP4740N) that a disc has been properly set, when the 4-division photodetector detects a reflecting beam from the disc. When a reflecting beam from the disc is received, pin 2 of comparator IC10 (1/2) switches tis level from ''H' to ''...' Q31 turns from OFF to ON, changing the collector of Q31 from -12 V to +5 V. The change is input to pin 4 of inverter (IC16). The output of the inverter (pin 12) changes from +5 to -12 V and turns Q2 and Q6 OFF. Thus, a focus loop is formed. Q4 is QN to reduce the gain of the focus amplifier until laser beam is emitted, but it turns OFF after laser has been emitted.
6. The output from pin 2 of focus amp IC1 (1/2) is applied to pin 4 of focus amp IC2 (1/2) through a phase compensa-tion circuit. The output is available at pin 2 and the lens at-tached to the focus coll is moved up or down in accor-dance with the output.

Page 43

1-5-8 TRACKING SERVO OPERATION

The outputs A₁, A₂, A₃ and A₄ of 4-division photodetector are applied to pin 4 to 7 of 0103 respectively. The resul-tant output (A₂+A₃) appears at pin 12 and output (A₁+A₃) at pin 13. The (A₁+A₃) and (A₃+A₄) are an addition of photodiode output in crossed position, and are called 3; and S₃ respectively. The S₃ and S₆ are sent to RF amp con-sisting of C-MOS invertues transformed into TL levels. R239, 247, D44, D45, D46, and C87 are used as level in the sent and sent a
H239, 247, D44, D45, D46, D47 d57 are used as level limiter. 2. T5, and T5, signals iTTL level converted 5_x, S_y signals) are converted to TEOP (pin 4) and TEON (pin 5) by the phase comparison circuit of IC15 (TC6G or T7G01). When the phase of T5, is leading that of T5_x, TEOP outputs "H" level and TEON outputs".¹¹ "I vel when the phase of T5_y is leaging behind that of T5_y. 3. TEOP produces a few fine pulses at the almost "L" level under the normal play condition. On the contrary, TEON is almost at "H" level, producing similar fine pulses. The distances between these fine pulses shortens, when the tracking servo is off such as in search period.
To the pickup lens in accordance with a TE signal. 5. Tracking jump may occur because of an excessive amplitude of TE signal caused by scratches or dusts on a disc. RF signals are dropped out for more than a predater-mined period for such a cause as this, the DOC signal becomes "H" level to make D8, and Q9 turn ON. This reduces the gain of Q8 and changes the degree of the phase compensation in Q9.

7. The output available at pin 8 of IC2(2/2) is applied

Page 44

DP-1100B/TI DP-1100B/TI

(TEON). 2. The TEOP and TEON are added and fed to pin 6 of IC12 (1/2). They are doubled and the output to pin 8. This signal is termed tracking error (TE) signal. The tracking coll
During normal PLAY mode, pin 1 (TEP) of IC16 is at "H" level by the mode 0 to 4 signal from microprocessor IC15 (TIMP4740N). The "H" signal is applied to pin 6 (TEG1) via D26 and to pin 2 (TEG2) via D27. TEG1 and TEG2 signals are used to control TEOP and TEON signals inside the IC15 ITC15G or T7001), so that the mode can be switched into normal play mode very quickly. The TE signal, output to pin 8 of IC12 (1/2) via R178. When the input voltage at pin 4 of IC13 (1/2) via R178. When the input voltage at pin 4 of IC13 (1/2) is higher than that 0 pin 3, "H" level is output to pin 2.
Since the input to pin 3 of IC12 (2/2) is an inverted input, when the input voltage of pin 4 is compared, only the difference is inverted and made available as an output at pin 2. The output from pin 2 of IC15 (112) is applied to pin 2 of IC15 (1C156 or T7001) and the output from pin 2 of IC15 (1C156 or T7001), in order to control the circuit for producting TEOP and TEON singles from TS1 and TS2. Since the TEOP is held at "L" level and the TEON at "H" tevel during a kick operation and the totcus-of period, the output from pin 8 of IC12 (12) is applied to pin 7 and 6 of IC13 (221) are at "L" level. At the end of the kick operation, the output from pin 8 of IC12 (12) is applied to pin 7 and 6 of IC13 (221). Judging the polarity of the output from 10 for 1C12 (122) is "L" level, the signal is input to pin 8 of IC13 (122) is "L" level, the signal is ngot to pin 8 of IC13 (I21) is "L" level, the signal is ngot to pin 8 of IC15 (IC15 (IC2) is "L" level, the signal is ngot to pin 8 of IC15 IC15 (IC15 (IC15 Gor T7001). The control timing of a kick pulse is determined by this signal to the IC15 (IC15 (IC15 Gor C7001). The control timing of a kick pulse is determined by the signal in the IC15 (IC15 (IC15 Gor C7001). The control timing of a kick

Page 45

1-5-10. SEARCH AND LOCK-IN CIRCUIT OPERATION DURING KICK MODE

Pin 23 (RFG) of IC15 (TC15G or T7001) is at "L" level during the kick mode. The RFG signal is fed to pin 1 of IC18 and the inverted output of the level-shifted RFG signal (named KGC) is output to pin 15. It is "H" level dur-ing the kick mode, The signal is applied to the base of O2 through R33, turning Q7 ON under the kick mode to cut the tracking servo loop. The tracking error signal (pin 8 of IC12 (1/2) during the kick mode is a sawtooth waveform as shown, but the contror fits amplitude is not always in line with D V (some offset results). This may possibly cause unstableness, when the unit changes to a normal FLAY mode from the kick mode (when the tracking servo i SON). To solve this problem, the KGC signal (+5 V during kick mode and -12V during FLAY mode) is given to the heses of Q23 and Q26 are OFF during the kick mode.

The diodos D29 and D31 and G3 and threshold as below: 1.5 V + 0.6 V (D29) - 0.6 V (D31) = 1.5 V The 1.5 V is charged across C70.

Part (B) The -0.5 V is charged across C69.

PLAY

When the unit is switched from KICK to PLAY, Q26 and Q25 turn ON, C69 -0.5 V+C70+1.5 V=1.0 V is ap-plied to pin 6 of IC14 (1/2) and the output from pin 8

Page 46

1-5-11. PU DRIVE OPERATION

Fig. 1-5-11

Since control of the pickup feed motor should gradually be made just to componsate an offset of the tracking error signa during a normal PLAY mode, it is done by TCO+tracking coll+1 signal only. During a normal PLAY mode, the TCO+signal is applied to pin 7 of IC3 (22) through R74 Since PLAY is -12 V (pulled-down output of IC16) during normal PLAY mode, 014 is OFF. In this state, IC3 (22) and RC components form a low-pass filter. As a result, the high frequency components are eliminated from TCO+ signal to obtain offset signal. It is applied to pin 3 of IC4 (2/2) through R78. After gain adjusted, it drives the pickup carry motor through R80 and L3.

Page 47

1-5-12. FOCUS SERVO CONTROL SIGNAL OPERAITON

WHEN NO DISC IS LOADED: When no disc is loaded, 06 25K304 and 02 25C2578 are timed ON not to work the focus coil drive circuit, so that the focus coil can not be acrivated. Since no signal is increased across the 4-division photodetector, no RF is available and pin 2 of IC10 (1/2) TA75393S becomes "H" level. The collector of O31 25K1015 is in turn held at a "L" level. It is fait to pin 4 of Inverter IC16 and pin 12 becomes "H" level. The "H" level signal is applied to the gate of 06 25K30A through R29 100 KD. It turns ON to cut the signal to pin 2 of IC1 (1/2) A75555. The with Fand, the "H" level signal is applied to the base of 02 25C2878 through R3 22 kD. 02 is turned on to ground the FE signal. Thus, no signals are into IC1 (1/2) AN6555. The switching function of 06 and 02 controls the operation of focus coil. It is disabled by this circuit, when no tocusing is required.
50

WHEN A DISC IS LOADED AND IN PLAY MODE: When a disc is loaded, a signal picked up by the 4-division photodetector is divided into two signals. S₁ and S₁ by 0103 (TA7331P). They are amplified by 021 and fed to pin 3 of IC10 (1/2). When the Fr signal is present at pin 3 of IC10 (1/2), pin 2 becomes "L" level. It is applied to the base of 033 (2SA1015) through R140 and R220, placing the collec-tor of 031 at a "H" level. The "H" level signal is fed to pin 4 of IC16 through D38 and R213. Its invorted signal is avoitable at pin 12 as an "L" level signal. The "L" level signal is then applied to the gate of 06 (2SK30A) through R3, and O6 is turned OFF. Another signal going through R3, and piled to the base of 02 2SC2878 turning it OFF. Both of 06 and 02 are under OFF state, the focus servo circuit works.

Page 48

tion is discontinued when the laser diode is not being ac-tivated. 5. A "H" level output is applied to pin 1 (TEP) of IC15 only during normal PLAY mode. It, however, becomes "L" level, when a kick signal is given during the normal PLAY mode. The signal is integrated by R210, R209, D36 and C74 to turn on Q29 and Q30. In this instance, Q27 and Q28 are placed under OFC condition by making Q30 turn Q18 are placed under OFC condition by making Q30 turn Q14 during the kick mode. The noise limiter circuit is thus disabled during search mode.

NP-11008/11 NP-11008/11 1. CIRCUIT DESCRIPTION

tracking operation by shorting a part of the feedback loop for the tracking amplifier. 2. A "H" level output is provided at pin 13 (PLAY) of IC15 by tho microprocessor during normal PLAY mode. The signal is fed to pin 6 of IC16. It is level-shifted to activate the FET, and the inverted output is available at pin 10. Tho signal is applied to the gate of Q14 to make it turn ON dur-ing the modes other than PLAY. This bypases the pickup carry motor amp and prevents the tracking error signal from driving the pickup feed motor. 3. When an RF signal drops out for a certain portiod of time because of scatches or dutts on a disc, a dropout detec-tion signal of "L" level is provided at pin 12 (DCON) of IC15 at the same spotper every revolution of the disc. The signal is applied to pin 2 of IC16. It is level-shifted, and

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Page 49

1-5-14. SERVO CONTROL CIRCUIT OPERAITON

PLAF mode. This is called SVC (serve control). The operating principle of the circuit is to adjust to an optimum one out of the 3-step predetermined balances using the er-ror number in the EFM signal.
ror number in the EFM signal. t. C₁ and C₂ error detection conditions ("H" level when an error occurs) in the EFM signal is output to pin 63 (DAST) of IC6 (TC9179F). A clock signal of 88.2 kHz, which inof IC6 (TC9179F). A clock signal of 88.2 kHz, which in-dicates one word output period, is made available at pin 50 (WDCK) and a frame lach puble signal, which in-dicates one frame, is available at pin 60 (DSLP). These three signals are coupled to a shift register with strobe function IC11 (TC4094BP). DAST ferror present) is input as data, WDCK as shift clock and DSLP as strobe signal. As a result, C₂ areor presence condition per every one frame is output at pin 11 to 13 of IC11. They are than ap-plied to pin 1 of IC12 (MB88201) through a wired OR cr-cut ("H" level indicates the error detection.)

(pin 9 to 12), selecting one of R104 through R111 connections, which are pleaded in parallel with R121 connected to pin 1 and 2 of (D103 (TA7314)). (Refore to the truth table at right showing the connection status.) 4. The 4-division photodetector signal (A + B) is output to pin 1 of 0103. Pin 2 is used as a feedback terminal for the last stage amplifier. In the same way, the (C+D) signal is available at pin 16 and 15 is a feedback terminal. R121 is a feedback terminal. R121 is

8. For example, when the microprocessor indicates (INH, A, B C)= (L, L, pin 13 of 0102 is connected to pin 3 of 0102. Thus, 24 kB resistance is connected in parallel with the 15 kB resistance already inserted between pins 1

Q102 pin No.	Q102 input INH	Q102 input A	Q102 input B	Q102 input C	ut PU alignment level Resistance		Resistance value between pins 1 and 2 of Q103
6	н	L	L	L	INH	80	15 k
12	L	н	н	L	. 3	180 k	13.8 k
1	L	L	L.	н	4	82 k	12.7 k
5	L	н	£.	н	5	51 k	11.6 k
2	Ļ	L	н	н	6	39 k	10.8 k
4	L	Н	Н	н	7	30 k	10 k
13	L	L	L	L	0	24 k	9.23 k
14	L	н	L	L	1	20 k	8.57 k
15	L	L	н	L	2	16 k	7.74 k

Page 50

NP-1100R/II NP-1100R/II

Detection of Dropout Position 1. The dropout control eircuit employed in this unit has been designed to be strong against soratohes or shocks. The FGS signal (20 pulses generated per one revolution of the disc motor) is applied to pin 39 (FGS) al (C15 (TC15G or 77001) and it is 6 times frequency multiplied internally. An output with 120 pulses per one revolution is soutput to pin 35 (DOCK). If a scratch is present, the number of pulses are counted. The fiven lat pin 12 (DOCN) al (C15 is switched from "H" to "L" at the same position where the soratch was present but one track behind. 08 and 09 in the tracking serve circuit are lumed ON to increase the gain of the tracking serve control. Thus, the system is protected against scratches or shocks. 2. If a scratch is found on the surface of a disc, pin 8 (RFES) of comparator (C10 (2/2) is switched from "H" level. When pin 22 becomes "H" level, a shift register is set inside IC15 and the DOCK signel IC20 pulses per one revolution of disc is counted. Bech of the subcle strand pulses inside IC15 and the DOCK signel IC20 pulses per one revolution of disc is or pulse. When the 120 pulses per one revolution of disc is required IC3 are counted, Bech of the subcle at pulse inside IC15 and the IC3 pulses per one revolution of disc is in the 120 pulses per one revolution of disc is in the 120 pulses per one revolution of disc is in the 120 pulses per one revolution of disc is in the 120 pulses per one revolution of disc is on the 120 pulses per one revolution of disc is period beam of the shift register inside IC15. This changes the level at pin 1 21 (DCON) from "H" to "L".

Tracking error pulse control signal is present at pin 1 (TEP) of IC15 and it is "H" level during the normal PLAY mode. It, however, switches to "L" level during KICK mode. This is input to pin 3 and 12 of IC3 to disble the circuit during

Page 51

PUFF, KICF

PUFF, KICF 1. This is a circuit to control the carry motor for the pickup. During normal FLAY mode, the pickup earry motor can be controlled only by the TCO + signal, just to compensate the offset of the tracking error signal. During SEARCH or FAST FORWARD (FF, REV) mode, however, it has to be moved more aukkly. For this reason, the movement is controlled by KICF and PUFF. 2. More precisely, during a long (fan SEARCH mode, PUFF is used and during a short (close) SEARCH, FAST FORWARD or PAUSE mode, KICF is used for the control purpose. 3. KICF (available at pin 32 of IC15) is high impedance dur-ing the normel PLAY mode. The input voltage at pin 3 of IC11 (1/2) becomes 2.5 V by R153 and R155. Since the input voltage at pin 4 of IC11 (1/2) is at at 2.5 V by R157 and R156, the output from pin 2 of IC11 (1/2) becomes 0 V.

PUFF (available t pin 33 of IC15) is also high impedance during the normal PLAY mode. The input at pin 7 of IC11 (2/2) becomes 2.6 V by R160 and R162. Since the input voltage at pin 6 of IC11 (2/2) is set at 2.6 V, the output at pin 8 becomes 0 V. When the pickup is moved in the FORWARD (FF) direc-tion, PUFF and KICF are "1"' level. Inverted input pin 7 and 3 of IC11 are "1"' level and output at pin 8 and 2 are at "L" level. Inverted input pin 3 of IC4 (2/2) is also at "L" level to provide the carry motor with a high revolution in the clockwise direction. When the pickup is moved in the BACKWARD (REV) direc-tion, both of the PUFF and KICF are "L" level. By making the input of C214 "L" level and the output "1" level, the carry motor can be revolved at a high speed in the counterclockwise direction.

Mode Signal	Normal	Long (More than	Search 512 tracks)	Short (Less than	Search 512 tracks)	-	REV
Mode Signal	PLAY	FF Direction	REV Direction	FF Direction	REV Direction	FF	REV
KICF	2.5V	2.5	2.5
PUFF	2.5V	5	0	2.5	2.5	2.5	2.5
	i Intel Clanel durin	a cook Mada		i Applies reverse		Linds (N/)

Applies reverse to put a brake.

Page 52

1-5-16. KEY DATA AND TIMING PULSE OPERATION

Since the unit has many function keys, a 6 x 4 matrix had been made in order to make the best use of the input/out-put ports of IC1 (4-bit microprocessor). The key input can be judged by key scanning pulses from IC1 (6 lines in time division) and four key input lines.

2. Pin 11 to 16 of IC1 are periodically providing the pulses staggered by a regular timing as shown. Each of them enters the vertical line of the key matrix through a diode, which prevents more than 2 keys from being pressed at the same time. The 26 to 29 are input lines and they are alf 0 V when no keys are pressed. The pin 14 line and pin 26 are shorted, and scanning pulse from pin 14 is input to pin 26. IC1 (4-bit microprocessor) recognizes that the PLAY key is pressed. The pin 14 line and pin 26 are shorted, and scanning pulse from pin 14 is input to pin 26. IC1 (4-bit microprocessor) recognizes that the PLAY key has been pressed, based on the input to pin 26 and the timing of pulse at pin 14 and gives the PLAY instruction to IC16 (control microprocessor). The reason that the timing pulse has a double frequency at pin 16 is that two clock signals are entered simultaneously, when M-READ and CLEAR keys are pressed at same time.

Fig. 1-5-16-2 IC1 Timing Pulse Waveform

-0 *

Page 53

Page 54

1. An output signal EFMI from the EFM data sampling circuit is fed to pin 17 of IC15 (TC156 or T7001). It is processed through the buffer and the output signal EFMO is available at pin 41. It is then sent to pin 14 of IC9. A phase comparison process is made in IC9 and the resultant outputs are provided at pin 7 (UP output) and pin 8 (DOWN output). These two outputs express the lead or Iag of phase between the EFM signal and bit clock signal (PLCK). When a frequency of the PLCK is lower than the EFM clock, pin 7 is held at "UP evel for a longer time, decreasing the period of high impedance. On the contrary in 8 becomes "\" level for a shorter period of time, and the period of high impedance is increased.
period of high impedence is increased. 2. The UP and DOWN outputs are added through R20 and R18, and fed to a low-pass filter. Comparing it with a reference voltage, the phase difference is applied to VCO as DC output. An operation amp for the low-pass filter purpose is built in IC9, pin 1 (INA +) is for non inverted input and pin 2 (INA –) is for invand input respectively. pin 4 is an output terminal. The added UP and DOWN output is fod to INA – through R18, R17 and C25 form a filter network.

3. R21 and R22 are resistors to detarmine a reference voltage for the filter, and INA + is usually held at about 2.7 V. During the SEARCH mode, however, the reference voltage is raised up (about 3 V) to shorten the search period. For this purpose, an RFG signal of "L" level is applied to the base of 015 to Linn (IOA and is "H" outputs a dded to INA + through R110 during the SEARCH period. A The output from pin 4 (OUTA) of low-pass filter output controls voltage for VC0 through R15. The VC0 has been designed to coslite at e about 16 MHz to 19 MHz with a control voltage arange of 1 V to 8 V. Under normal PLAY condition, it is osalilating at about 17 MHz with a control voltage at a maximum of 8 V and D5 is a vanable capacitance dide. If Grave a blas to Q3 and D33 is a term redice Tig.

5. An oscillation amplitude of VCO is about 500 mVp-p. Eliminating the DC component by C19, it is applied to pin 9 of IC9. Being amplified in IC9 and 1/4 frequency divided, the output is available at pin 12.a s ELCK. (The PLCK is about 4.3 kHz during normal PLAY mode) EFMI input to pin 14 is synchronized by the PLCK, and the DOUT output is available at pin 13. 014 and 013 are connected in an emitter follower configuration and work as a buffer for the PLCK and DOUT signals are observed with the PLL circuit at the normal PLAY condition, the clean waveform is locked as shown in the diagram at right.

Page 55

1-5-19. MUTING CIRCUIT OPERATION

There are following two cases where muting output is required. One is during all modes except the normal PLAY mode, and the other is when adequate correction or compensation for normal playback can not be secured because of too many errors contained in the EFM signal depending on the condition of a disc even if it is normally being played. The muting can be made by the following two methods. One method is to mute the last output stage of the analog signal by using a relay and the other is to turn off the 16-bit digital signal in the process circuit. For this reason, the former is colled analog muting and the latter is called digital muting. Pin 38 of IC15 (TC15G or T7001) is at "L" level during all modes except normal PLAY mode and the provides 0 v to the base of C4. O4 is turned OFF, making relay flay. The cutput is thus muted. All the same time, in 34 of IC5 (TC9179F) is also held at "L" level through R103. The output of 15-bit digital signal is turned OFF, inside IC6.

3. When bad conditions of a disc (scratches or dust) make the adequate correction and compensation impossible because of too many errors in the EFM signal even during normal PLAY mode, pin 35 and 36 become "L" level. Pin 34 of IC6 turns to "L" level by a wired OR connection. The digital muting is thus accomplished by turning the 16-bit digital signal OFF.

Page 56

1-5-20. REMOTE CIRCUIT OPERATION (TRANSMITTER HAS A SIMILAR OPERATION AS TV OR VIDEO AND WILL NOT BE EXPLAINED)

A data signal (modulated by a 38 kHz carrier) sent from the transmitter enters to infrared ray sensor diode PH1. PH1 varies the current through it by changing its internal resistance in accordance with the input signal. The quies-cent point current is determined by load resistor R29 and +B supply. The varying current signal is fed to pin 7 of remoto contol amp (C17. It is about 40 dB amplified here and the output is available at pin 1. The signal is fed again to pin 2 of IC16 through the detec-tion circuit of D14, amplification centering around 38 kHz. The output appears at pin 7. The signal wave/orm-shaped by IC16 as shown at right is fed to pin 37 of IC1 for the control purpose of the microprocessor.

Fig. 1-5-20

Page 57

1-5-21. EMPHASIS CIRCUIT OPERATION

Fig. 1-5-21-2 Frequency response of high-end cut

Page 58

2-1 Head amp (J25-4404-08)

2-1-1 0103 (TA7731P) head amp

Q103 (TA7731P) is the head amp and operation IC for the laser beam receiver device, developed for CD system DAD player.

Pin connection diagram

Fig. 2-1A

Block diagram

Fig. 2-1B

NR/

Page 59

2. IC OPERATION OF EACH CIRCUIT AND PIN DESCRIPTION

Pin functions

Pin No.	Symbol	Description	Remarks
1	OUT1	Pin which outputs the sum signal (A + B) of pin IN A and IN B input signals out of 4-division photodetector outputs. The final stage buffer amp is provided with an external feedback resistance to neutralize the effect of the irregularity in characteristics between photodiodes.	FC I RF1 OUT I Buffer amp Note 1 With max. input of 100 kHz Transfer impedance
2	FC1	Final stage buffer amp negative input pin of OUT1 output signal. A resistance is connected between this pin and pin OUT1 to control the gain.	= 27 κα R _F1 = 9 kΩ (typical)
3	GND2	GND pin
4	IN A	Input pin of signal A (one of 4-division photodetector outputs)	Note 1
5	IN B	Input pin of signal B (one of 4-division photodetector outputs)
6	IN C	Input pin of signal C (one of 4-division photodetector outputs)
7	IN D	Input pin of signal D (one of 4-division photodetector outputs)
8	GND1	GND pin
9-10	NC	Not connected
11	V _cc	Positive supply voltage pin
12	OUT4	Pin which outputs the sum signal (B + D) of pin IN B and IN D input signals out of 4-division photodetector outputs.
13	OUT3	Pin which outputs the sum signal (A + C) of pin IN A and IN C input signals out of 4-division, photodetector outputs.	Note 1 With max. input of 100 kHz Transfer impedance = 27 kΩ (typical)
14	Vee	Negative supply voltage pin
15	FC2	Final stage buffer amp negative input pin of OUT2 output signal. A resistance (for feedback) is connected between this pin and pin OUT2 to control the gain.

Page 60

Pin No. S	Symbol	Description	Remarks
16 OU	JT2	Pin which outputs the sum signal (C + D) of pin IN C and IN D input signals out of 4-division photodetector outputs. The final stage buffer amp is provided with an external feedback resistance to neutralize the effect of the irregularity in characteristics between photodiodes.	FC2 FC2 BF2 OUT 2 m Buffer amp Note 1 With max. input of 100 kHz Transfer impedance = 27 kΩ R _F1 = 9kΩ

Table 2-1A

Note 1: 4-division photodetector configuration

Page 61

2-1-2 Q102 (TC4051BP) SVC switch

TC4051BP, of 8-channel configuration, is a multiplexer capable of selecting analog or digital signal, or combining them. The switch pin corresponding to each channel turns ON with the digital signal from the control pin.

Truth table

	JTS			"ON" CHANNEL
INHIBIT	С	в	A	TC4051BP
L	L	L	L	0
L	Ĺ	L	Н	1
L	L	н	L	2
L	L	н	н	3
L	H	L	L	4
L	н	L	н	5
L	н	н	L	6
L	н	н	Н	7

Table 2-1C

Page 62

2-2 Servo board (X29-1520-00)

2-2-1 IC9 (TC5050P) dropout memory, 50-stage/114-stage selection type shift register

Pin connection diagram

3 4 2 D_IN2 D_OUT 5 1 D_IN1 CLOCK NC ; 7, 15 12 6 11 V_DD ; 16 V_DD ; 16 V_SS ; 8 13 D_IN2 D_OUT 10

Logic diagram

Truth table

Block diagram

	t", t"+1		t,	+50	t _n+64
D _IN1	D _IN2	IM	ОМ	Dour	ОМ	Dour
Н	*	н	L	н	н	н
L	*	н	L	L	н	L
*	Н	L	L	Н	н	н
*	L	L	L	L	н	L

Page 63

2-2-2 IC15 (TC15G008AP) semi-custom IC

Pin connection

■ ; I/O port

Fig. 2-2-2A

Page 64

Block diagram

Fig. 2-2-2B Internal block diagram

Page 65

Pin functions

Pin No.	Symbol	Pin name	IN/OUT				Remarks
1	TEP	Tracking error pulse con- trol output	0	Out the	puts a ''H kick signa	ʻʻ signal o al is outpu	nly during play. However, it becomes ''L'' wh t during play.	ien

					TEG1	TEG2	Function
2	TEG2	Tracking error detector control (1) input	1		Н	Н	Tracking error detection and normal oper- ation		Pullup resistor incorporated
					L	Н	TEOP outputs a ''H'' signal at the timing of the absolute phase difference between TS1 and TS2. TEON is fixed to ''H''.
					Η	L	TEON outputs a ''L'' signal at the timing of the absolute phase difference between TS1 and TS2. TEOP is fixed to ''L''.
6	TEG1	Tracking error detector control (2) input			L	L	Stop of tracking error detection. TEOP is fixed to "L". TEON is fixed to "H".

3	TEON	Tracking error negative output	0	Whe (at n	When TS2 advances in edge phase against TS1, outputs a "L" signal (at normal operation).
4	TEOP	Tracking error positive output	0	Whe	en TS2 de nal operat	lays in edç ion).	ge phase against TS1, outputs a ''H'' signal (	at
5	TES	Tracking error polarity in- dication input	I	Cont	trol signal	input use	d in kick control for search operation		Pullup resistor incorporated
7	TTAC	Track TAC output	0	Pin o pletio	outputs cloon of kick	ock pulse or the co	which the microprocessor is informed of cor unt number of tracks.	n-
8	PUD	PU motor control input	l	Inpu carry	it which s γ signal is	tops the P a specific	U motor only when the PU motor compulsor code (PUD = ''H'').	·γ-
9	OPNS	Open/close output	0	Outŗ ''L''	out for dis = open,		3-state output
10	DSG	Data slice control input	1	Inpu circu ''H''	it for cont uit. ' input =	trol signal OFF.	which stops the sub-control of the data sli	се	Pullup resistor incorporated

Page 66

Pin No.	Symbol	Pin name	IN/OUT	Description	Remarks
11	LDC	Laser diode control out- put	0	Laser diode ON = ''H'' output, OFF = ''L'' output
12	DCON	Dropout control output	0	Output which indicates the dropout position of the RF signal.	·
13	PLAY	Play control output	0	Control signal output which operates the PU motor by the PU tracking servo signal.
14	FOKG	Focus OK output	0	Outputs the OK signal on instruction from the microprocessor when the laser spot is focused. Focus ON = "H" output.
15	MSP	Disc motor control output	0	Output for disc motor ON/OFF control signal.
16	TPCO	TES polarity select input	I	Input for signal which selects the polarity of the TES signal used in the kick process circuit. Open (V _pp ) or connected to GND.	Pullup resistor incorporated
17	EFMI	EFM signal input	l	Input for binary signal obtained by passing the RF signal regenerated by the PU through a comparator. Its polarity should be positive against the RF signal polarity.	Pullup resistor incorporated
18	TS2	Tracking error generation signal (1) input	I	Input for binary signal obtained from passing the A ₂ + A ₄ signal of 4-division photodetector through zero-cross comparator. (Used in tracking error generation.)	Pullup resistor incorporated
19	TS1	Tracking error generation signal (2) input	ļ	Input for binary signal obtained from passing the A ₁ + A ₃ signal of 4-division photodetector through zero-cross comparator. (Used in tracking error generation.)	Pullup resistor incorporated
20	RFOK	RF signal OK input	I	Input for signal indicating the regeneration of the RF signal by the pickup. It turns OFF the data slice (sub) and output EFMO. (At "H")	Pullup resistor incorporated
21	GND	GND
22	RFES	RF envelope signal input	I	Input for RF presence/absence signal, this signal is obtained by passing the RF envelope detection signal through comparator. It is used in the kick process and dropout process sections.	Pullup resistor incorporated

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Pin No.	Symbol	Pin name	IN/OUT	Description	Remarks
23	RFG	RFES control signal out- put	Ο	Output which controls the detection level of signal RFES. "L" only dur- ing kick operation.
24~27	MODE4~ MODE1	Mode select signal input	I	Input for servo system control signal generation and kick operation pro- cess direction indication. Connected to the microprocessor.	Pullup resistor incorporated
28	DSL1	Data slice control (1) out- put	О	Output for signal obtained by passing signal EFMI through the internal buffer amp. Has the same polarity as signal EFMI.
29	DSL2	Data slice control (2) out- put	Ο	Output for data slice control sub circuit. Detects the variation in slice level by check of the jitter of signal EFMI to control the slice level at an optimum level.
30	MODE-0	Mode select signal input	I	Input for servo system control signal generation and kick operation pro- cess direction indication. Connected to the microprocessor.	Pullup resistor incorporated
31	TEST	Test	ł	Normally, open or connected to V _pp .	Pullup resistor incorporated
32	PUFF	PU motor fast-carry signal output	0	''H'' output → FWD, ''L'' output → BWD, HiZ → OFF	3-state output
33	KICF	PU kick pulse output	о	''H'' output → FWD, ''L'' output → BWD, HiZ → Kick OFF
34	DIN	Dropout data I/O	1/0	Data I/O connected to shift register for dropout control
35	DOCK	Dropout control clock pulse output	0	Output for clock signal (with 6 times the FGS frequency) connected to shift register for dropout control
36	FG4	FG signal output	о	Output for clock signal obtained from 30 division of signal DOCK
37	CK88	88 kHz clock pulse input		Input for approx. 88 kHz reference clock signal	Pullup resistor incorporated
38	MUT	Muting output	0	Output for muting audio signal.	Pullup resistor incorporated

Page 68

Pin No.	Symbol	Pin name	IN/OUT	Description	Remarks
39	FGS	FG signal input	I	Input for FG signal with 20 pulse/disc rotation. Should have a duty ratio of approx. 50.	Pullup resistor incorporated
40	PLCK	PLL section clock pulse input	I	Input for reference signal (4.32 MHz) to PLL section for EFM signal reading	Pullup resistor incorporated
41	EFMO	EFM output	О	Inversion output of signal EFMI. With signal RFOK ''H'', is fixed to ''L''.
42	۷۵۵	V _DD		+5 V

Table 2-2A

Page 69

Each data for mode 0 to 3 is passed through the latch circuit, thereby different control signals are generated in the decoder section.

Control mode truth table A)

	MODE			*5		*7
0	1	2	3	4		TEP	PLAY	FOKG	LDC	MSP	MUTE	PUFF	OPNS	STATE
0	0	0	0	0	ο	0	0	0	0	0	0	HiZ	HiZ	Tray open state Standby mode after judging right/reverse side of the disc Pause mode (1) *1
1	0	0	0	0	1	0	0	0	1	0	0	HiZ	HiZ	At judgement of disc's loading.
0	1	0	0	0	2	(1)	1	1	1	1	1	HiZ	HiZ	1 REV 2 Cue 3 Play mode (1) x 2
1	1	0	0	0	3	(1)	1	1	1	1	0	HiZ	HiZ	BWD kick, REV, F REV, FWD kick, FWD, F FWD, Judgement of right/reverse side of the disc, TOC read.
0	0	1	0	0	4	0	О	0	1	1	0	HiZ	HiZ	Focus servo ON
1	0	1	0	0	5	0	о	1	1	1	0	HiZ	HiZ	Pause mode (2) *3 Focus tracking servo ON
0	1	1	0	0	6	0	0	1	1	1	0	1	HiZ	FWD search
1	1	1	0	0	7	0	0	1	1	1	0	0	HiZ	BWD search, Stop-BWD mode
0	0	0	1	0	8	0	0	0	1	0	0	HiZ	1	Tray close (laser diode: ON)
1.	0	0	1	0	9	(1)	1	1	1	1	0	0	HiZ	PU motor kick before BWD search
0	1	0	1	0	А	(1)	1	1	1	1	1	(1) ^*6	HiZ	Play mode (2) *4
1	1	0	1	0	в	(1)	1	1	1	1	0	1	HiZ	PU motor kick in FWD search
0	0	1	1	0	С	0	0	0	0	0	0	HiZ	1	Tray close (laser diode: OFF)
1	0	1	1	0	D	0	0	0	0	0	0	0	HiZ	Eject-BWD mode
0	1	1	1	0	E	0	0	ο	0	0	0	HiZ	0	Tray open (Open from ON of PU, SLT SW)
1	1	1	1	0	F	0	О	о	0	0	0	0	О	Tray open (Open from OFF of PU, SLT SW)
1 Pause mode 1 The The mot 2 Play mode 1 Norr 3 Pause mode 2 All ş 4 Play mode 2 Moc 5 TEP Moc case 6 PUFF Witt						e beginn en, 10 s tor) OFI rmal pla pause r de in w de whic se, a ''1 th code	hing of t sec later, F. ay mode modes o hich FW ch is eng '' outpu A, OUT	he first t pause r ther that /D pulse aged on it is emit	une is n node is n pause is outp ly a Lat ted. ts a ''1	neglecte engage mode out perio ch-SP = '' outpu	d, and t d with L dically in 1 (sect t only a	he unit D and N n play n ion 5-1; t PUD =	pauses. 1D (disc node 1 ). In this = 0.	5

emitted in any mode.

Table 2-2B TC15G008AP Normal mode table

Page 70

2. IC OPERATION OF EACH CIRCUIT AND PIN DESCRIPTION

Search control used in music scan, etc. is performed by the kick control circuit.

Mode 4 0→1

		MOD	)E		Stator
0	1	2	3	(X)	514101
0	0	0	0	0	Kick Reset
1	0	0	0	1	Kick Reset
0	1	0	0	2	BWD1 TRACK KICK
1	1	0	0	3	FWD1 TRACK KICK
0	0	1	0	4	BWD3 TRACK KICK
1	0	1	0	5	FWD3 TRACK KICK
0	1	1	0	6	BWD5 TRACK KICK
1	1	1	0	7	FWD5 TRACK KICK
0	0	0	1	8	BWD7 TRACK KICK
1	0	0	1	9	FWD7 TRACK KICK
0	1	0	1	А	BWD15 TRACK KICK
1	1	0	1	В	FWD15 TRACK KICK
0	0	1	1	С	BWD31 TRACK KICK
1	0	1	1	D	FWD31 TRACK KICK
0	1	1	1	E	BWD CONTINUOUS Kick
1	1	0	0	F	FWD CONTINUOUS Kick

Table 2-2C TC15G008AP Kick mode table

Page 71

2-3 Process board (X32-1010-00)

2-3-1 IC15 (TMP4740N-5909, 5914) Main microprocessor

Page 72

Pin description of IC15 (TMP4740N)

Pin No.	. Port name		Signal name	IN/OUT	Level	Function/operation
1		R40	MD0	0	L	Outputs various mode data and kick data outputs to IC15 (TC15G008AP) for interface with the servo system.
2	ku	R41	MD1	0	L	Outputs various mode data and kick data outputs to IC15 (TC15G008AP) for interface with the servo system.
3	R4	R42	MD2	0	L	Outputs various mode data and kick data outputs to IC15 (TC15G008AP) for interface with the servo system.
4		R43	MD3	0	L	Outputs various mode data and kick data outputs to IC15 (TC15G008AP) for interface with the servo system.
5		R50	MD4	ο	L	Data select signal output to IC15 (TC15G008AP). (The kick control data at "H" level and the mode control data at "L" level.)
6	RE	R51	SVCS	I/N	L	Operation start/stop control signal to the servo control microprocessor IC12 (MB88201)
7	no	R52	A2	0	L	Address data output to the external RAM IC14 (TC-5514P).
8		R53	A1	0	L	Address data output to the external RAM IC14 (TC-5514P).
9		R60	AO	0	Н	Address data output to the external RAM IC14 (TC-5514P).
10	R6	R61	A3	0	Н	Address data output to the external RAM IC14 (TC-5514P).
11	110	R62	Α4	0	н	Address data output to the external RAM IC14 (TC-5514P).
12		R63	A5	0	Н	Address data output to the external RAM IC14 (TC-5514P)
13		R70	D0/QDAd	1/0	Н	Data input terminal of the subcode Q from IC8 (TC-9178), (T-6391). Data input/output terminal, with the external RAM IC14 (TC5514).
14	D7	R71	D1/QDAC	I/O	н	Data input terminal of the subcode Q from IC8 (TC-9178), (T-6391). Data input/output terminal with the external RAM IC14 (TC5514).
15	17	R72	D2/QDAb	I/O	Н	Data input terminal of the subcode Q from IC8 (TC-9178), (T-6391). Data input/output terminal with the external RAM IC14 (TC5514).
16		R73	D3/QDAa	I/O	н	Data input terminal of the subcode Q from IC8 (TC-9178), (T-6391). Data input/output terminal with the external RAM IC14 (TC5514).
17		P10	A6	0	н	Address data to the external RAM IC14 (TC5514).
18	D1	P11	A7	о	Н	Address data to the external RAM IC14 (TC5514).
19	с I	P12	A8	0	Н	Address data to the external RAM IC14 (TC5514).
20		P13	A9	о	н	Address data to the external RAM IC14 (TC5514).

Table 2-3-1A

Page 73

Pin No.	Port	ort name Signal name		IN/OUT	Level	Function/operation
22		P20	R/W	о	Н	Read/write control signal to the external RAM IC14 (TC5514). (''H'' level in read mode and ''L'' level in write mode)
23	00	P21	QDSE	0	Н	Data input select signal to R7 port. (Data from the external RAM IC14 (TC5514) at "H" level and the data input of the subcode Q from IC8 (TC-9178) at "L" level)
24	٣2	P22	QDAS	0	ΨĽ	CRC error check data and subcode Q data select signal. (Error data at ''L'' level and Q-data at ''H'' level)
25		P23	QDARD	0	Ĺ	A signal to read the subcode Q data from IC8 (TC-9178) in 4-bit units. (Data is updated at ''H'' level. One cycle ends every 19 times.)
26		K00	CLS/RFG	I	*	Tray close signal input (''L'' level with the tray closed) Kick operation mode signal (''L'' level during the kick operation, and goes to ''H'' level after the kick operation ends.)
27	KO	K01		Marana	٠	Tray open signal (''L'' level with the tray opened) Disc existence judge signal (''L'' level when a disc exists.)
28	κυ	K02	SLT	I	*	Pickup position detect signal input (''H'' level when the pickup is positioned in the program area and ''L'' level in the read-in area.)
29		K03	RFOK	Ι	*	RF signal input (''L'' level when RF signal exists.)
35		R80	IRQ	1/0	Н	Data transfer request signal from IC1 (TMP47C41N) Usually ''H'' level and goes to ''L'' level when the request exists.
36		R81	FSRH	О	L	Focus search signal (≒2 Hz) Usually ''L'' level.
37	R8 -	R82	QDRE	l	Н	A signal to enable reading the subcode Ω data from IC8 (TC-9178).
38		R83	TTAC	I	Н	Kick end signal
39		R90	DAT21	1/0	L	Serial data input from IC1 (TMP47C41N) A signal for controlling data transfer mode with IC1 (TMP47C41N). ("H" level in transmission mode from IC15 (TMP4740N) to IC1 (TMP47C41N))
40	R9	R91	DAT12	1/0	Н	Serial data output to IC1 (TMP47C41N).
41		R92	SCK	1/0	Н	Serial data transfer synchronizing signal
21			V _ss	Power supply		Power supply (0 V)
30			TEST	١·		Not used (Connected to V _ss )
31	-		×w	I	_	Oscillator connection terminal
32			Xour	0		Oscillator connection terminal
33			RESET	I		Initialize signal input

Page 74

Pin No.	Port	Port name Sign		IN/OUT	Level	Function/operation
34		_	V _hh	Power supply		Power supply (+5 V)
42		_	V _DD	Power supply		Power supply (+5 V)

Table 2-3-1A

Page 75

2-3-2 IC9 (TD6315P) PLL IC

IC9 (TD6315P), the PLL IC developed for CD system DAD player, consists of a digital phase comparator, a charge pump circuit, an active LPF and a data separation circuit.

The digital phase comparator detects the phase error between the clock pulse obtained from 4-division of the VCO output and the reference of the HF signal (EFMI) emitted from the data slicer. Then, from the charge pump circuit, up and down signals UO and DO are output as phase error data.

Pin connection diagram

Block diagram

Fig. 2-3-2B TD6315P Block diagram

Page 76

Pin functions

Pin No.	Symbol	Description	Remarks
1	INA+	Positive input of built-in OP amp. Forms the guard ring of INA – together with pin 3 (NC) fixed to approx. 1/2 V _ccp voltage.
2	INA –	Negative input of built-in OP amp. The signal subject to resistance addition by charge pump circuit outputs UO and DO and TC9178F pin TMO is input.
3	NC	Not used. This pin connected to pin INA + for giving isolation between pins INA – and OUTA.
4	OUTA	Output of built-in OP amp. Connected to pin INA – through capacitor C and resistor R, forms a lag lead type filter to control VCO.
5	V _eea	Negative voltage supply to analog circuit.
6	NC	Not used. Connected to pin INA + for giving isolation between pin V _EEA and each of output pins UO and DO.
7	υο	Charge pump up signal output pin. When signal PLCK obtained from 4-division of VCO frequency is phase delayed in rising edge against signal EFMI input, its "L" output duration is prolonged to make VCO fre- quency higher. In phase lock, "L" level = 1/2 PLCK.	High impedance state ex- cept during ''L'' direction.
8	DO	Charge pump down signal output pin. When signal PLCK obtained from 4-division of VCO frequency is phase advanced in rising edge against signal EFMI input, its "H" output duration is prolonged to make VCO frequency lower. In phase save, "H" level = 1/2 PLCK.	High impedance state ex- cept during ''H'' period
9	VCOI	Input pin of VCO output signal. The signal subject to AC coupling by a capacitor is input.
10	GND	GND pin for digital circuit
11	G	Input by which charge pump outputs UO and DO are made into high impedance. When made ''L'', high impedance mode is entered to hold the VCO frequency.	TTL level
12	PLCK	Output of data separation clock pulse generated from EFMI input signal in PLL circuit. This output, obtained from 4-division of VCO frequency (17.3 MHz), is input to PLCK of C-MOS processor TC9178F. The clock pulse is 4.32 MHz with duty ratio of 50.	C-MOS leve

Page 77

Pin No.	Symbol	Description	Remarks
13	DOUT	Signal EFMI output. This output, synchronized with the rising edge of signal PLCK, is input to pin EFMI of C-MOS processor TC9178F.	C-MOS level
14	EFMI	Input for EFMI signal obtained by passing the RF signal regenerated from disc through data slicer.	TTL level
15	V _ccp	Voltage supply to digital circuit.
16	V _CCA	Positive voltage supply pin to analog circuit.

Table 2-3-2A

Page 78

2-3-3 IC8 (TC9178F) E.F.M decoder Pin Description

Pin connection

Fig. 2-3-3A

1100R/11

Page 79

TC9178F Block diagram

Fig. 2-3-3B

Page 80

Pin functions

Pin No.	Symbol	1/0	Waveform	Description	Remarks
1	NC		_	Not connected
2 3	PCSA PCSB	I		These inputs determines the phase comparison frequency. Phase comparison frequency = 7.35 kHz (frame sync signal)/N
				PCSA PCSB N fc (Hz)
				L L 6 1225
				H L 8 918.75
				L H 17 612.5
				Н Н 16 459.375
4	DIV +	I	5 V 0.5 µS 0 V (Appears only at low disc rotation.)	Input for setting reference frequency division coefficient in APC signal generation circuit for CLV servo control. Input as buffer memory status signal from TC9179F (IC6). In addition, the varying amount is selectable by DIVC.	Connected to each of TC9179F DIV+ (pin 65) and DIV- (pin 64)
			5 V 0.5 #S	DIV + DIV - DIVC quency division coefficient Disc motor speed
5	DIV		U ov	L L * 1/288
Ū	2		(Appears only at	H L L 1/287.5 Higher
			high disc rotation.)	H L H 1/287 Higher
				L H L 1/288.5 Lower
				L H H 1/289 Lower
6	DIVC	1		Н Н 1/288
				* Don't care
7	C21K	1	5 V 0.2 μS 0 V	2.1168 MHz input. This signal, the clock pulse obtained from 4-division of X'tal OSC frequency 8.4672 MHz, is input from TC9179F (IC6). Its duty ratio is 50.	Connected to CK2M (pin 56) of TC9179F (IC6)
8~10	TES-1 ~ TES-3	l		Test inputs, which operates normally at ''H'' or open state.	Pullup resistor incor- porated
11	NC			Not connected.
12	ЕМРН	0		Output for emphasis presence/absence judgement represented by control bit of sub-code signal Q. "'H'' = de-emphasis ON

Table 2-3-3A

Page 81

Pin No.	Symbol	1/0	Waveform		Desc	ription
13	2/4S	0	_	Output for CH 2/CH 4 sele of sub-code signal Q. "L" = CH 2, "H" = CH	ection ju	dgement rej	presented by control b	oit
14	FG IN	I	5 V 10 mS 0 V (4 pulses/disc ro- tation) Near disc center Near disc edge	Input for FG pulse from di 1 or 4 pulse per each rota the motor within the range Disc motor speed (rpm) -175 175-740 740-	isc moto tion of d e of 17C A Fixed to Normal Fixed to	r. lisc motor is ) to 400 rpn \FCO ) ''H'' operation ) ''L''	fed to control speed c n. APCO Fixed to 50% duty cycle output Normal operation Fixed to 50% duty cycle output	of
15	4/1	I		FG IN pulse setting. Eithe set. 4/1 ''H'' level	r of 1 o	r 4 pulse pe FG p disc	er each rotation can b rulse per each motor rotation 1 4	)e
16	OVRG	I	At start On play, CLV ap	5 V 0 V plication begins.	o select v ol is peri - FG IN	whether or formed by F input valid	not disc motor rotatio G IN input.	'n
17	APCG	I	"Н"	ON/OFF selection input of trol. "'L'' (generator OFF): Al th th qu pr fre pa Ol	f APC sin PC output at is dut e internat Jency ge hase diff equency arison with FF to ON	gnal genera ut is fixed to y ratio of 50 al phase cor eneration se erence ''0'' , the start hen the gen I is set to pl	tor for CLV servo cor o phase difference ''0' ). At the same time, a mparison reference fre ection is arranged int against the controlle point of phase com erator is changed from mase difference ''0''.	1- 45 2- 50 4d 1- m
18	DMLD	0	START † Lock	Disc motor lock detection vo control. Detects the frequency of t is within ±5% deviation, deviation, it is reset. This When set, this flip-flop out to pin APCG, is used for c	output o he frame it is set. output s put beco ontrol o	f AFC signal e sync signa When the signal is the pmes ''H''. f APC block	l generator for CLV ser il. When the frequenc frequency is over ±10 flip-flop output signa This output, connecter	r- 9 0 1. d

Page 82

Pin No.	Symbol	1/0	Waveform	Description	Remarks
19	APCO	0	5 V 50 μS 0 V	APC signal output for CLV servo control. The output is a PWM (Pulse Width Modulation) wave with resolution = 8 bits, carrier frequency = 8.27 kHz and linear output range = 8 π/9.
20	AFCO	0	5 V 50 μS 0 V	AFC signal output for CLV servo control. The output is a PWM wave with resolution = 8 bits, carrier frequen- cy = 8.27 kHz and linear output range = ±10%.
21	P/S	I	"Н"	CLV servo control signal ON/OFF input. At play, this pin is set to "H" and, at stop, to "L". This input signal is given the highest priority in the CLV servo control system. When this pin is "L", AFC output is fixed to "L", and APC output gets duty ratio of 50.
22	SCSE	I		Data selection input for 4 outputs of sub-code signal SCT/T - S/W ''L'' level: Data of 4 bits, P, Q, R and S is output. ''H'' level: Data of 4 bits T, U, V and W is output.
23-26	SC P/T SC Q/U SC R/V SC S/W	0	_	8-bit data output of sub-code signal P, Q, R, S, T, U, V, W. This signal is the data of each frame. Here, 4-bit data is output by signal SCSE as required. Data selection of each frame is performed in syn- chronization with the rising edge of signal PFCK.	Not connected
27	V _DD	_	_	Voltage supply pin.
28	V _ss	-		GND pin
29	S ₀ S ₁	0	_	When sub-code signal pattern SO or S1 is detected, this output becomes "H" for that input frame period.	Not connected
30	SCPD	0		Output to indicate the date contents of sub-code signal P. Data ob- tained when the data of each frame is checked in units of 5 frames by the sub-code signal P detection section is output.	Not connected
31	PFCK	0	_	The frame period output with duty ratio of 50. The sub-code data is switched in synchronization with the falling edge of this output.	Not connected

Table 2-3-3A

Page 83

Pin No.	Symbol	1/0	Waveform	Description
32	QDSS		"H"	Input for sub-code sync pattern detection mode selection, demodulating sub-code signal Q.
33	QDRD		QDRD 5 V 5mS 0 V QDRE 13 mS	Input used in reading the sub-code signal Q data inside internal memory in units of 4 bits via outputs QDA-a to QDA-d. When signal QDRD becomes "H", the next 4-bit data is set to pins QDA-a to QDA-d after an arbitrary period from that pulse edge.
36	QDRE	ο	5 V 5 mS 0 V 13 mS 5 V 5 mV 0 V 13 mS 0 V	Enable signal output reading sub-code signal Q. When error judge- ment of 80-bit input sub-code signal Q data is completed, those 4-bit data of MSB side are set to pin QDA-a to QAD-d, and output QDRE becomes "H". When 20 pulses are input to QDRD or when data Q in the next block is written before the data written in internal RAM is read out, output QDRE becomes "L" so that data reading is disabled.
37	QDAS		_J LJ I With block error	Data selection input for sub-code signal Q data outputs QAD-a to QAD-d. For easier interface with the microprocessor, this input determines output data at QDA-a to b, QDRE and QDE ports. QDAS Port QDAa QDAb QDAc QDAd L QDRE QDAb QDAc L H QDAa QDAb QDAc QDAd
34, 35	NC	-	Not connected.
38	QDA-d		5 V 20 mS 0 V	The 80-bit sub-code signal Q data, the block error judgement result of the sub-code signal Q data output or signal QDRE, is output according to the ''L'' or ''H'' setting of QDAS. For data transfer to the
39	QDA-c	0	5 V 20 mS 0 V	Inicroprocessor, QDAS is made "L" lifst, then the error judgement result of data Q is transferred and signal QDRD is input with QDAS "L". Thus, data Q is transferred in units of 4 bits as required. In addition, QDA-a to QDA-d are 3-state outputs, where selection bet- ween output mode and high-impedance mode is made by "L" or "H" of QDSE.
40	QDA-b	0	5 V 20 mS 0 V	QDEa QDEb Result of judgement Output data processing H H No error Direct output L H 1-bit error of CRCC Direct output
41	QDA-a		(Example of wave- form)	H L 1-bit error of data Q 1-bit correction output L L Error of 2 bits or more Direct output

Table 2-3-3A

Page 84

Pin No.	Symbol	1/0	Waveform	Description
42	WSEG			Window selection of gate signal which, when the frame sync pattern of EFM signal is detected, determines whether or not this pattern is given as the sync signal for the internal system. WSEG Gate signal window (number of clocks PLCK) L ±3 H ±7
43	TMWS	1	_	Selects the number of Tmax = N (PLCK) in detection of T _mex of EFM signal which is input from pin EFM2. TMWS N (PLCK) L 11±1 H 11±0.5
44	FSGM			When no frame sync pattern is detected within the window of the frame sync separation protection gate signal in N continuous frames, system synchronization is made by the next input frame sync pattern without the window. These two inputs are used in selection of number N. FSGL FSGM N (frame)
45	FSGL	ł	_	L L 12 H L 8 L H 4 H H 2
46	TMGS	I		To prevent faulty T _max detection, data is valid only when data T _max continues N times. This number N is determined by the input. TMGS N L 7 H 4
47	NC	_	_	Not connected.

Page 85

Pin No.	Symbol	1/0	Waveform	Description
				The frequency data obtained from Tmax detection of EFM signal which is input from EFM2 is output in one of 3 states as the result of comparison between signal PLCK and Tmax. This output can be used as the frequency status for the PLL circuit. When P/S signal is "L" (stop mode), output TMO is compulsorily fixed to "H".
48	тмо	о	''DC 2.5 V'' ∼3.0 V	EFM signal frequency status TMO
				fTmax>fPLCK L
				fTmax≒fPLCK High impedance
				fTmax>fPLCK H
49	QDSE	I	"H"	Input of ''H'' compulsorily makes outputs QDA-a to QDA-d into high impedance state. This input enables effective use of microprocessor input ports.
50	TMOR	I	This appears when no synchronization is obtained over some frames.	Input of "L" compulsorily makes output TMO into high impedance state. Normally, it is connected to FSPS or FSLO.
51	FSPS	ο	20 mS 5 V 0 V	Output to indicate the system sync state on the frame sync pattern. Becomes "H" when no sync pattern is given within the window of gate signal in N continuous frames on selection by input FSGL or FSGM.
52	EFM2		5 V 0.2 µS 0 V	Input of EFM signal regenerated from disc. The signal obtained by slicing the signal from the RF amp by the level comparator is directly input (asynchronous to signal PLCK).
53	EFM1		4.2 V 0.2 µS 0.4 V 0 V	Input for EFM signal regenerated from disc. Differently from input signal EFM2, this signal is synchronized to falling edge of signal PLCK phase-locked in the PLL circuit.
54	PLCK		4.4 V 0.2 µS 0 V	Clock pulse input for frame sync separation. This signal is fed from external PLL circuit based on HF signal reproduced from disc. This Clock pulse signal is locked to 4.32 MHz and have duty ratio of 50.

Page 86

2. IC OPERATION OF EACH CIRCUIT AND PIN DESCRIPTION

Pin No.	Symbol	1/0	Waveform	Description	Remarks
55	FSLO	0	5 V 2 mS 0 V	When each system is in synchronization by the frame sync pattern, and when that input pattern is completely synchronized with the frame sync pattern in internal frame counter (the frame synchroniza- tion necessarily has 588 pulses PLCK), "L" is output during the frame period.	Not connected
56	PBFS	0	5 V 50 μS 140 μS	When "H" is output with a frame sync signal, demodulation data U ₀ to U ₃₁ are transferred to TC9179 (IC6). If "H" which acts as an enable flag, symbol data U ₀ to U ₃₁ transfer will be possible by MWRE.	* Note Connected to PBFS (pin 2) of TC9179F (IC6)
57~60 62~65	DBOO- DB07	о	5 V 0.2 μS 0 V	Outputs for demodulation data U ₀ to U ₃₁ in each frame. These are 3-state outputs. When pin BOEN is "L", data is output. DB00 (LSB) to DB07 (MSB)	* Note Connected to I/O 0 - 7 (pins 19-26) of TC9179F (IC6)
66	BOEN	ł	5 V 1 μS 0 V 3.8 μS	Input for enable signal which turns ON the DBOO to BD07 bus driver.	* Note Connected to BOEN (pin 4) of TC9179F (IC6)
67	MWRE	0	5 V 1 μS 0 V 3 μS	Output for the enable signal which makes memory write enable. Becomes "L" at the timing at which data is set to the DBOO to DBO7 data transfer register. When pin BOEN is "H" and it becomes "L" when pin MWRE becomes "H". After signal PBFS becomes "H", it emits 32 outputs every 17 clock pulses PLCK.	DB00

Table 2-3-3A

* Note Data are set to register and MWRE is changed to ''L'' from ''H''. This means data are ready to be written into the external RAM. In this condition, BOEN (''L'' active) from TC9179F turns bus driver on for 8-bit data DB00 to DB07 transfer. At the same time of DB00 to DB07 data transfer, PBFS signal is sent to TC9179AF as a frame sync signal. When PBFS is ''H'', U₀ to U₃₁ is output.

Page 87

2-3-4 IC6 (TC9179F) Error correction

Pin connection

Fig. 2-3-4A

Page 88

Block diagram

Fig. 2-3-4B TC9179F Block diagram

Page 89

Pin functions

Pin No.	Symbol	I/O	Waveform	Description	Remarks
27, 61	V _DD	_		Voltage supply pin
28, 62, 67	V _ss	-	-	GND pin
2	PBFS	I	_	Frame sync input. The symbol data period signal of each frame sent from TC9178F (IC8) is input.	Connected to PBFS (pin 56) of TC9178F (IC8)
З	MWRE		-	Memory write request input which accepts MWRE signal from TC9178F (IC8)	Connected to MWRE (pin 67) of TC9178F (IC8)
4	BOEN	0	-	Output enable. When signal MWRE from TC9178F (IC8) can be ac- cepted, the control signal to release symbol data output DB00 to DB07 from Hi-impedance state is output.	Connected to BUSE (pin 66) of TC9178F (IC8)
5~14, 18	AD0 ~ AD9, AD10	О	5 V 0.2 μS 0 V	External RAM address data output, Connected to address data input of external RAM.
15	R/W	О	5 V 0.2 μS 0 V	Read/write signal output to external RAM. Connected to R/W input of external RAM. ''L'' = Read, ''H'' = Write
16	CE2	о		Chip enable 2 signal is output when external RAM is read or written. Connected to CE2 input of external RAM.	Not connected
17	CE1	0	5 V 0.5 μS 0 V 0.48 μS	Chip enable 1 signal is output when external RAM is read or written. Connected to CE1 input of external RAM.
19~26	1/0-7 ~ 1/0-0	1/0	5 V 0.2 μS 1 μS	Data bus line connected to I/O-O to 7 of external RAM and DBO4 -DB07.

Page 90

Pin No.	Symbol	1/0	Waveform	Description	Remarks
29	ALGC		_	Process selection input of C2 correction section. Selects the process algorithm for the frame in which detection of error symbol is not possible in C2 correction section. It is "L" in normal operation.	Connect to system GND. (Normal position)
30~33	АТ-0 ~ АТ-3	1/0		Digital attenuator I/O controlled by signal WDCK WDCK = ''L'', outputs internal digital attenuator level WDCK = ''H'', reads external control data for digital attenuator. (AT-3 is not connected.)
34	MUT-1	I		Muting control input of the automatic control section of the internal digital attenuator. At ''L'', attenuation amount increases (finally, it becomes digital ''0''). At ''H'', attenuation amount decreases (it shifts to 0 dB side).
35	MUT-01	0	_	Muting 1 output. Outputs an "L" signal when burst error over 64 frames or buffer-over of jitter absorption memory is detected.
36	MUT-02	0	_	Muting 2 output. Outputs an "L" signal when deinterleave error is detected over 3 continuous frames.
37	P/S SE	I		Output data parallel/serial selection input. ''L'' = parallel output, [''H'' = serial output.]
38	DA-0	0		P/S SE = ''L'' P/S SE ≈ ''H'' Outputs LSB of 8-bit data. Outputs serial data from LSB.	Not connected
39	DA-1	0		P/S SE = ''L'' P/S SE = ''H'' Outputs the second bit from LSB of 8-bit data. Outputs correction flag of 8 bits of MSB side.	Not connected
40	DA-2	0	_	P/S SE = ''L'' P/S SE = ''H'' Outputs the third bit from LSB of 8-bit data. Outputs correction flag of 8 bits of LSB side.	Not connected

Page 91

Pin No.	Symbol	1/0	Waveform	Description	Remarks
41, 42	NC	_	_	Not connected.
43	DA-3	0		P/S SE = ''L'' P/S SE = ''H'' Outputs the fourth bit from LSB of 8-bit data. Outputs a ''H'' signal when correction flag of LSB side is set side with level of MSB side at -30 dB.	Not connected
44	DA-4	0	_	P/S SE = ''L'' P/S SE = ''H'' Outputs the fifth bit from LSB of 8-bit data. 1 MCK output. Outputs the clock signal (1.058 MHz) obtained from 2-division of signal CK2M.	Not connected
45	DA-5	0	_	P/S SE = ''L'' P/S SE = ''H'' Outputs the sixth bit from LSB of 8-bit data. APL output. Outputs R-channel aperture signal.	Not connected
46	DA-6	0		P/S SE = ''L'' P/S SE = ''H'' Outputs the seventh bit from LSB of 8-bit data. APL output. Outputs L-channel aperture signal.	Not connected
47	DA-7	0	5 V 0.5 μS 0 V	P/S SE = ''L'' P/S SE = ''H'' Outputs MSB of 8-bit data. Outputs music data in serial from MSB.
48	ВСК	0	5 V 0.2 μS 0 V	Bit clock pulse is output when serial data is output. Thus, serial data is output in synchronization with the rising edge of this clock pulse (1.4 MHz).

Page 92

Pin No.	Symbol	1/0	Waveform	Description	Remarks
49	MLCK	0		MSB/LSB clock pulse output. Outputs the clock signal (176.4 kHz) obtained from 8-division of signal BCK, which is used as a set clock pulse when 8-bit parallel data is output.	Not connected
50	WDCK	0	5 V 5 μS 0 V	Word clock pulse output. Outputs the clock signal (88.2 kHz) obtained from 16-division of signal BCK, which indicates the output period of one word.
51	L/RG	0	5 V 5 µS 0 V	Sampling frequency output. Outputs the clock signal (44.1 kHz) ob- tained from 2-division of signal WDCK, which indicates the data out- put channel. "'L'' = L channel, "'H'' = R channel.
52	X-0	0		X'tal OSC connection pins. X'tal OSC is connected to generate the clock signal required in the system.
53	X-1	\|	0.05 μS	(Feedback resistance and amp incorporated) X'tal OSC frequency = 8.4672 MHz
54	CKSE	1	_	Selection pin which informs X'tal OSC frequency. (Pullup resistance incorporated) [''H'' or open = 8.4672 MHz, ''L'' = 4.2336 MHz
55	CK4M	0	5 V 0.2 µS 0 V	4 MHz clock pulse output. Outputs 4.2336 MHz, which is also used as the clock signal for microprocessor.
56	CK2M	0	5 V 0.2 μS 0 V	2 MHz clock pulse output. Outputs 2.1162 MHz, which is used as the clock signal for TC9178F (IC8).	Connected to C21K (pin 7) of TC9178F (IC8)
57	TES1			Test pins (pullup resistance incorporated)
58	TES2			In normal operation, it is "H" or open.
59	COFS	Ο	5 V 50 μS 0 V 44 μS 90 μS	Frame period signal output. Outputs corrected frame period signal.

Page 93

Pin No.	Symbol	I/O	Waveform	Description	Remarks
60	DSLP	0	5 V 50 µS 0 V	Data status signal output. (Error information signal output)
63	DAST	0	5 V 50 μS 0 V 138 μS	Data status signal output. (Error information signal output)
64	DIV –	0	5 V 0.5 mS 0 V 138 μS	Buffer memory status output. Outputs an "H" signal when the jitter absorption buffer memory enters range of +2 or +3 frames in its capacity of ±4 frames. This output is connected to pin DIV- of TC9178F (IC8) to lower the disc motor revolution.	Connected to DIV – (pin 5) of TC9178F (IC8)
65	DIV +	0	5 V 0.5 mS 0 V 138 μS	Buffer memory status output. Outputs an "H" signal when the jitter absorption buffer memory enters range of -2 or -3 frames in its capacity of ±4 frames. This output is connected to pin DIV + of TC9178F (IC8) to raise the disc motor revolution.	Connected to DIV + (pin 4) of TC9178F (IC8)
66	BUSE			Buffer selection input pin. Selects the output condition of DIV – /DIV + . At "H", Div± output are made when the buffer memory enters range of ±2 frames. At "L", Div± output are made when it enters range of ±3 frames.

Table 2-3-4A

Page 94

2. IC OPERATION OF EACH CIRCUIT AND PIN DESCRIPTION

2-3-5 IC12 (MB88201-115K) SVC mircoprocessor

Fig. 2-3-5A

Block diagram

Fig. 2-3-5B

Page 95

DP-1100B/II

2. IC OPERATION OF EACH CIRCUIT AND PIN DESCRIPTION

Pin functions

Pin No.	Port name	Signal name	I/O	Initial value	Description
9	RO	SVC (A)	0		Output for focus offset amount control data to Q102 (SVC circuit) bit 0
10	R1	SVC (B)	0		Output for focus offset amount control data to Q102 (SVC circuit) bit 1
11	R2	SVC (C)	0	U	Output for focus offset amount control data to Q102 (SVC circuit) bit 2
12	R3	OF _INH	0		Output for focus offset amount control data to Q102 (SVC circuit) bit 3
13	R4	TEP	I	1	Input for focus offset amount 1-level shift request signal. During execution of kick operation, becomes ''L'' to perform 1-level shift.
14	R5	RFES	I	1	Input for SVC operation (counting the number of errors) halts request signal. When track jump occurs, becomes ''H''. After that, stops operation for 1.2 msec.
1	R6	CIER	ł	1	Input for block error signal from IC11. When block error occurs, becomes "H".
2	R7	COFS	1	1	Input for corrected frame period signal (7.35 kHz square wave) from IC6. At the point when it becomes "H" signal CIER is judged.
3	R8	EOF _#	о	1	Output for focus offset amount control data to Q102 (TC4051BP) Not used. bit 1
4	R9	EOF₄	0	1	Not used. Grounded.
5	R10	STAT	1/0	1	SVC operation start/stop control, which is connected to IC15 (TMP4740N). When a ''H'' signal is input, operation starts, while when a ''L'' signal is input, operation stops. In addition, when offset amount adjustment is complete, it output a ''L'' signal with a duration of 3.4 msec.
6	R11	EXSEL	I	1	Not used. Grounded.
7		CK2M	I		Clock pulse input.
8		Vss			GND pin
15		RESET	I		Initialize signal input.
16		_	Power supply		Power supply (+5 V) pin.

Page 96

Operation of IC12 (MB88201)

IC12 (MB88201) is the CPU to control focus offset amount against temperature change, etc. (This control operation is termed SVC operation for short.)

Focus offset amount is controlled by control of bilateral switch Q102 (TC4051BP) through SVC (A) ≅ SVC (C) and OF_INH. The following table shows the relationship between each ports and offset level.


Ports Level	OFINH	SVC (A)	SVC (B)	SVC (C)	Remarks
2	0	0	1	0
1	0	1	0	0
0	0	0	0	0	Initial select offset level
7	0	1	1	1
6	0	0	1	1
5	0	1	0	1
4	0	0	0	1
3	0	1	1	0
INH	1	×	×	×

Table 2-3-5B

x : Don't care

As shown in the table, the offset level can be set to 8 levels. The offset level is determined by the amount of NFB to the focus error amp Q103, i.e. the value of resistor is changed by bilateral switch controlled by SVC (A) to (C), OF_INH. The following outlines the focus offset amount adjustment procedure.

Fig. 2-3-5C shows that, starting from the initial offset level, counting of number of block errors executed from level 0. The offset level is stepped down one by one till the count exceeds 2000 (in this case N=A>2000 at level 3). From the level of which the count exceeded 2000, the offset level is stepped up 3 levels (in this case to level 6: N=B) for enough clearance margin for block error numbers. This level is maintained till the end of playback unless the disc is changed or stopped.

For counting of the number of block errors, the number of times by which block error signal CIER from IC11 (TC4094BP) generated in synchronization with correction frame period signal COFS (7.35 kHz square wave) from IC6 (TC9179F) becomes "H" is counted.

Measurement of the number of block errors at each offset level is done by 256 x 6 samples (rising edges of signal COFS). Normally, this measurement is completed in approx. 0.2 sec. In addition, when signal RFES becomes "H" (when track jump occurs), the measurement is halted for approx. 1.2 msec.

Start and stop of this SVC adjustment operation is controlled by IC15 (TMP4740N). In this case, when STAT becomes "H", this operation starts, while when it becomes "L", the operation stops and focus offset amount returns to the set value before adjustment. Further, when the operation is complete, STAT outputs an "L" signal with a duration of about 3.4 msec to inform IC15 (TMP4740N) of completion.

Fig. 2-3-5D

Page 97

2-3-6 IC14 (TC5514P) T.O.C. Memory

Pin connection diagram

Fig. 2-3-6A

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Pin functions of external RAM IC14 (TC5514P)

Pin No.	Port pin name	Signal name	1/0	Initial value	Description
5	AO	AO	I		Address input from IC15 (TC4740N) (X32-1010-11)	bit 0
6	A1	A1	Ι		Address input from IC15 (TC4740N) (X32-1010-11)	bit 1
7	A2	A2	I		Address input from IC15 (TC4740N) (X32-1010-11)	bit 2
4	A3	A3	1		Address input from IC15 (TC4740N) (X32-1010-11)	bit 3
3	A4	A4	Ι	*	Address input from IC15 (TC4740N) (X32-1010-11)	bit 4
2	A5	A5	Ĩ		Address input from IC15 (TC4740N) (X32-1010-11)	bit 5
1	A6	A6	Ĩ		Address input from IC15 (TC4740N) (X32-1010-11)	bit 6
17	A7	A7			Address input from IC15 (TC4740N) (X32-1010-11)	bit 7
16	A8	A8	I		Address input from IC15 (TC4740N) (X32-1010-11)	bit 8
15	A9	A9	1		Address input from IC15 (TC4740N) (X32-1010-11)	bit 9
14	I/01	D0	I		Data in/output from IC15 (TC4740N) (X32-1010-11)	bit 0
13	1/02	D1	1/0		Data in/output from IC15 (TC4740N) (X32-1010-11)	bit 1
12	1/03	D2	1/0		Data in/output from IC15 (TC4740N) (X32-1010-11)	bit 2
11	1/04	D3	1/0		Data in/output from IC15 (TC4740N) (X32-1010-11)	bit 3
10		R/W	I	1	Read/write control signal input. "H" = Read, "L" = Write
8		CE	1		Chip enable signal input (active "L")
9		GND	Ground		Ground
18		V _DD	Power supply		Power supply pin (+5 V)

Control of external RAM IC14 (TC5514P)

The external RAM is provided with the following data storage areas. Different data are written or read by control of microprocessor ports R6, P1 and R5 (R52, R53) (address designation), port R7 (data I/0), port P2 (P20) (write/read control) or port P2 (P21) (chip enable). (Refer to "Pin functions of IC15", Table 2-3-1A.)

(1) Area of lead-in data (play start time of each tune and read-out start time)
(2) Area of tune No. data (TNO, X) of preset channels (CH 1 - 16)
(3) Area of play time data of each preset channel
(4) Area of total play time of each channel

First, the method of access to the area of read-in data (Area (1)) is described.

As shown in Table 2-3-6A, IC14 is so configured that row address is designated by microprocessor ports R52 and R53, LSB data of column address by 4 ports R6, and MSB data of column address by 4 ports P1. Here, the microprocessor is programmed so that the binary conversion value of the point data (tune No.) which is read, in reading the lead-in data, is set as column address. A compact disc can record up to a maximum of 99 tunes. Thus, area of column addresses H'01 to H'63 (H' before the number or alphabet means that they are expressed in hexadecimal) is used as save area of lead-in

data (Area (1)). (read-out start time data is saved in code address H'64.)

In combination with the column address determined in this manner, the 10's digit of minutes data of play start time is saved in address 0 of the row address given by ports R52 and R53, the 1's digit of minutes data is saved in address 1, the 10's digit of seconds data in address 2, and the 1' digit of seconds data in location 3. This operation timing is shown in Fig. 2-3-6B. The remaining three areas (2), (3) and (4) relate with preset channels. For channel presetting, a data save area for 16 channels is needed. To meet this need, the area of column addresses H'80 -H'FF is divided into 16 sections. As shown in Table 2-3-6B, four words of index LSB data, index MSB data, TNO LSB data and TNO MSB data (Area (2)) are saved in row address 0 in order from the head column address of each section, four words of 1's digit of seconds data. 10's digit seconds data, 1's digit of minutes data and 10's digit of minutes data (Area (3)) are in row address 1, and five words of 1's digit of seconds data, 10's digit of seconds digit data, 1's digit of minutes data, 10's digit minutes data and 100's digit of minutes data (Area (4)) are in row address 3. Fig. 2-3-6C shows this operation timing.

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External RAM IC14 (TC5514P) map

RAM capacity, 1023 words Capacity used, 626 words _____→4 bit

Column address			_
R1	R6	0	1	2	3
0	0
0	1	10 MIN	1 MIN	10 SEC	1 SEC	TNO. 1
0	2	10 MIN	1 MIN	10 SEC	1 SEC	TNO. 2
6	2	10 MIN	1 MIN	10 SEC	1 SEC	TNO. 98
6	3	10 MIN	1 MIN	10 SEC	1 SEC	TNO. 99
6	4	10 MIN	1 MIN	10 SEC	1 SEC	Read-out start time
6 ≀ 7	5 ∼ 8
7	9		Upueed		CH CNTL
7	А		Onuseu		CH CNTH	Number of memories

8	0	INDEX L	1 SEC	1 SEC
8	1	INDEX H	10 SEC	10 SEC
8	2	TNO. L	1 MIN	1 MIN		0111
8	3	TNO. H	10 MIN	10 MIN	llowed	CH DATA
8	4			100 MIN	Unused
8	5	Linu	and	Unused		TOTAL TIME
8	6	Und	sea
8	7
8	8	INDEX L	1 SEC	1 SEC
8	9	INDEX H	10 SEC	10 SEC
8	А	TNO. L	1 MIN	1 MIN
8	В	TNO. H	10 MIN	10 MIN		011.0
8	С			100 MIN		CH 2
8	D	linuard	Ununged
8	E	Unusea	Unused	Unused
8	F
9	0				СН 3
۲	1	The sar	ne as in 8-8 to 8-F is re	peated.	Unused
F	F			CH 16

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2. IC OPERATION OF EACH CIRCUIT AND PIN DESCRIPTION

The operation timing when play start time data of 53 min 41 sec is written on the point data of tune 20 which is read out in reading the read-in data.

As mentioned above, the binary conversion data of the point data read out is used as column address. Therefore, in this case (tune 20), the column address is H'14.
** Data is written or read in order from sec digit.