MODEL 165
are developed by QA601, 9402, and Q4lO. They sre
coupled to the modulator gates by c417 and C418, and
to the demodulator by c409. 0421 an* 0422 clamp the
gate *rives co a reference level equal to the feed-
back "olrsge. developed by QA409, a Xl amplifier
whose input is connected to the feedback point.
c.
Input Zeroing. Input seroing is accomplished
by R431 which determines rhe current throunh R428 and
R429. The voltage ,vzneraced by this c”rr&t across
R428 is added to the feedback “olLaSe developed
across the lo-kilohm element ,,f RN403 between pins
6 and 7. “se a pure copper wire end a dual banana
plug for a shorting plug.
CIRCUIT DESCRIPTION
The reference resistance consists of F.409. and R414
rbrouSh R419. .The specific value of the resistance
is determined by the state of relays K409 through
K415. The rota1 resisfsnce is equal to the fullran8e resistance. Note that this circuit applies
a ne$sti”e reference currant through the unknown
resi*Lance.
3-5.
le. CURRENT SO”RCE.
bee Schemetic 25392E).
The lmA current is developed by 9404, R411 through
R413 and D405.
It is applied LO the HI renninal by
mean8 of rile fronr pane1 BWitCh S402. R410 ad D406
protect 9404 if S402 is eccidantally depressed while
the voltage is applied to the HI terminal.
d. Input Offset Current. Input offset current is
comwnsated for b” ad,usrinp. R424 “hich develow a
“o&e referenceh to-the f;edback point at the o”tput of QA409. This voltage generates a compensafing
current through R423 which is applied to the common
node of the FET modulators, Q4OU and Q4OlB.
e. Offset “olra*es.
Offset “oltaSes within the dc
amplifier loop are compensated for by R434 which applies a volrage to the positi”e input terminal of
QA406, the final dc amplifier. The controlling time
constant within the loop is determined by C413 and
R427 in the negative feedback loop of Q.4406.
3-4. OHMS CIRC"ITRY. (sea Schematic 25392E). on a11
ahms ranges, K404 and 9407 are on, firing the dc “altage preamplifier at 100 millivolts full range. D416
near QA406 limits the output of this amplifier such
that no more than 1 volt appears at the ioput under
open-circuit conditions. The ohms circuit in the
lower left corner of Schematic 25392E generates a
reference current at the input terminals. This reference c”rre”f is generated by a “oleage at “0 OUT”
G4OU Deck No. 3) divided by a reference resistance
selected by K409 through K415.
8. Reference Voltage.
The reference voltage is
the sunnnacion of 0.1 times the “DC PRW OUTPUT”,
and a fixed lOO-millivolt reference. QA402 performs
this summafion. R462 and R463 provide an output of
0.08 times “DC PW OUTPUT” BL their iunction.
This voltage is applied to rhe positive-input terminal
of QA402 which has a non-in”errinS gain of 1.25 determined by R407 and R461. 9405 is on in normal
OperaLion. The lOO-milli”alt reference is developed
from an aftenuaeor scros~ the g-volt reference diode
D408 consisrin~ of R458. R402, and R465. The “olt-
age at R465 is about -1.6 volts. This is amplified
by -0.25 using QA401, and by another -0.25 with QA402.
b. Overload Conditions. Under negati”e overloads,
D418 blocks current flow to 9405 or QA402 output, and
0415 limits the input “oILage at the naSafi”e terminal
of QA402 to the supply “olfaSe. Under positive o”erloads, D414 limits the neSari”a input of QA402 to the
positive voltage.
This drives the output of QA402
negative until it is limited by D426. AC that level,
the c”rrenf flow in the emitter of Q405 is determined
by voltage across D426, rhe base-emitter drop in 4405,
R454. and R408. These elements limit the collector
current in 9405 LO abo”f 1.2 milliamps. This current
is essentially independent of the voltage appaariwj
at the collector of Q405, which ie determined by the
po~itive voltage at the HI terminal and the voltage
drop of the 1.2 milllamps in the reference resistance.
1073
3-6.
DC-AMPS PREAMPLIFIER. (see Schematic 25392E).
The Fnput c”rre”t passes rbro”Sh S4OlA Deck No. 2
to a reference resistance selected by K406 throush
K411. The voltage across chin reference resistance
is sensed by the dc amplifier in B 4-terminal method
between terminal 1 of RN401 (at circuit LO) and juncCio” of K411 end R415, which is applied to the inpur
of the amplifier through S401A Deck No. 4, R420, and
R421. 0” the I-microamp through 1OO-milliamp ranges.
the dc preamplifier is set to a gain of 100, COP
respondinS co a full-range voltage of 10 millivolts.
On these radges, K406 through K411 select the reference resistance which covers s span from 0.1 ohm
(in RN401) through 9 kilohms u(415). On rha IOOO-
mflliamp range, K406 selects the 0.1 ohm resistance
in RN401, and the gain of the dc preamplifier is
changed to 10. correspondinS LO 100 millivolts full
ran$a, as indicated in ParaSraphs 3-3. D401 rhrouSh
D404 protects rhe relays and the sensing resistances
from overcurrent.
3-7. AC-Am3 PRWLHPLIFIRR. (see Schematic 25392E).
As in the case of dc amps. the BC input current is
passed tbraugh S4OU Deck No. 2 to a sensing resistance selected by relays. In this cE.se, only re1#ys
K406 thrc.“Sh K409 are used. The output voltage is ,
sensed at S4Ol.A Deck No. 3 and coupled through C401,
S4OU Deck No. 2, and R455 to the AC Preamplifier,
chain. The ac preamplifier is set to a gain of 100
corresponding to IO millivolts full range on the 100
microamp rhrouSh 100 milliamp ranges. a Sain of 10
corresponding to 100 milli”olLs full range on rhe 1000
rsilliamp ac amps range, selected as in Paragraphs 3-2.
As in the case of dc amps, D401 throuSh D404 protect
the relays and sensing resista”ce from a”erc”rreoL.
Note that since the capacitor-couplin8 through C401
OCC”rs I.” the circuit folloving the sensing resistances, dc or ac ~“ercurrents .3 A may hsve danaSing
affects on either DC AEIPS or AC AMPS functions.
3-8. “NIPOLAR AMPLIFIER. bee Schematic 25393D).
This circuit, consistinS of QUO2 and QA203. is shown
in the left-half of Schematic 253930. The preampli-
fier output is applied to 3201. an analog outp”t
at the rear panel, and fo X213. R213 and R404 (on
Sehemstie 25392E. near S401A Deck No. 8) attenuate
dc signals to the 0.91-volt level corresponding Co
1 “Ok full range. Note chat the positive terminals
of QA202 and QA203 are essentially at LO. thus the
feedback loops around each op-amp rend LO constrain
the neSsri”e inputs also to the LO level. Since
terminals 3 and 16 of RN.01 are connected to these
ne&ati”e inputs, we may consider the IO-kilobm elements connected co terminal 2 88 a siwle 5-kilOInn
element to LO. The 5 kilohm element from Le”r.i~Ul
11
l .