Page 1
XV-S60BK
XV-S62SL/XV-S65GD
SERVICE MANUAL
DVD VIDEO PLAYER
XV-S60BK
XV-S62SL / XV-S65GD
STANDBY/ON
OPEN
/COSE
TV DVD
3D
TV/VIDEO
REPEAT
PHONIC
CANCEL
TV1 TV2 TV3
123
TV4 TV5 TV6
4
56
TV7 TV8 TV9
89
7
-/-- TV0
TV
0+1010
AUDIO
SUBTITLEANGLE
DIGEST
S
U
IO
V
E
R
P
SELECT
R
A
E
L
C
–
W
O
L
S
TLE
I
T
+
CH
VOL
-
ENTER
C
-
CH
HO
I
C
E
RM-SXVS60J REMOTE CONTROL
Area Suffix (XV-S60BK)
J ------------- U.S.A.
C ---------- Canada
TV DVD
RETURN
MUTING
VFP
PROGRESSIVE
SCAN
+ZOOM–
N
E
X
T
S
T
R
O
B
E
S
L
OW
+
M
E
N
U
VOL
STANDBY
+
STANDBY/ON
N
E
E
R
C
S
N
O
PROGRESSIVE
XV-S60 DVD/CD PLAYER
OPEN/CLOSE
SKIP
PAUSEPLAYSTOP
DVD/VIDEO CD/CD
Area Suffix
(XV-S62SL/XV-S65GD)
J ------------- U.S.A.
Each difference point
Model
XV-S60BK
XV-S62SL
XV-S65GD
Body color
Black
Silver
Gold
Contents
Safety precautions ------------------------ 1-2
Preventing static electricity ------------- 1-3
Importance admistering
point on the safety ------------ 1-4
Precautions for service ----------------- 1-5
This service manual is printed on 100% recycled paper.
COPYRIGHT 2001 VICTOR COMPANY OF JAPAN, LTD.
Disassembly method -------------------- 1-6
Adjustment method ---------------------- 1-15
Troubleshooting -------------------------- 1-19
Description of major ICs ---------------- 1-23
Glossary of term and abbreviations -- 1-42
No.A0012
Jun. 2001
Page 2
XV-S60BK/XV-S62SL/XV-S65GD
1. This design of this product contains special hardware and many circuits and components specially
for safety purposes. For continued protection, no changes should be made to the original design
unless authorized in writing by the manufacturer. Replacement parts must be identical to those
used in the original circuits. Services should be performed by qualified personnel only.
2. Alterations of the design or circuitry of the product should not be made. Any design alterations of
the product should not be made. Any design alterations or additions will void the warranty
and will further relieve the manufacture of responsibility for personal injury or property damage
resulting therefrom.
3. Many electrical and mechanical parts in the products have special safety-related characteristics.
These characteristics are often not evident from visual inspection nor can the protection afforded
by them necessarily be obtained by using replacement components rated for higher voltage,
wattage, etc. Replacement parts which have these special safety characteristics are identified in
the Parts List of Service Manual. Electrical components having such features are identified by
shading on the schematics and by ( ) on the Parts List in the Service Manual. The use of a
substitute replacement which does not have the same safety characteristics as the recommended
replacement parts shown in the Parts List of Service Manual may create shock, fire, or other
hazards.
4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the
like to be separated from live parts, high temperature parts, moving parts and/or sharp edges
for the prevention of electric shock and fire hazard. When service is required, the original lead
routing and dress should be observed, and it should be confirmed that they have been returned
to normal, after reassembling.
5. Leakage current check (Electrical shock hazard testing)
After reassembling the product, always perform an isolation check on the exposed metal parts of
the product (antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control
shafts, etc.) to be sure the product is safe to operate without danger of electrical shock.
Do not use a line isolation transformer during this check.
Plug the AC line cord directly into the AC outlet. Using a "Leakage Current Tester", measure
the leakage current from each exposed metal parts of the cabinet , particularly any exposed
metal part having a return path to the chassis, to a known good earth ground. Any leakage
current must not exceed 0.5mA AC (r.m.s.)
Alternate check method
Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms
per volt or more sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by
a 0.15 F AC-type capacitor between an exposed
metal part and a known good earth ground.
Measure the AC voltage across the resistor with the
AC voltmeter.
AC VOLTMETER
(Having 1000
ohms/volts,
or more sensitivity)
Move the resistor connection to each exposed
metal part, particularly any exposed metal part
having a return path to the chassis, and measure
the AC voltage across the resistor. Now, reverse
the plug in the AC outlet and repeat each
measurement. voltage measured Any must not
0.15 F AC TYPE
1500 10W
Place this
probe on
each exposed
metal part.
exceed 0.75 V AC (r.m.s.). This corresponds to 0.5
Good earth ground
1. This equipment has been designed and manufactured to meet international safety standards.
2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.
3. Repairs must be made in accordance with the relevant safety standards.
4. It is essential that safety critical components are replaced by approved parts.
5. If mains voltage selector is provided, check setting for local voltage.
!
Burrs formed during molding may be left over on some parts of the chassis. Therefore,
pay attention to such burrs in the case of preforming repair of this system.
1-2
Page 3
XV-S60BK/XV-S62SL/XV-S65GD
Preventing static electricity
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged,
can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs.
1.1. Grounding to prevent damage by static electricity
Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as DVD players.
Be careful to use proper grounding in the area where repairs are being performed.
1.1.1. Ground the workbench
1. Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over
it before placing the traverse unit (optical pickup) on it.
1.1.2. Ground yourself
1. Use an anti-static wrist strap to release any static electricity built up in your body.
(caption)
Anti-static wrist strap
Conductive material
(conductive sheet) or iron plate
1.1.3. Handling the optical pickup
1. In order to maintain quality during transport and before installation, both sides of the laser diode on the
replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition.
(Refer to the text.)
2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power
source can easily destroy the laser diode.
1.2. Handling the traverse unit (optical pickup)
1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.
2. Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific
details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the traverse
unit. Be careful not to take too long a time when attaching it to the connector.
3. Handle the flexible cable carefully as it may break when subjected to strong force.
4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it
1-3
Page 4
XV-S60BK/XV-S62SL/XV-S65GD
Importance Admistering point on the Safety
1.6A/125V
FC902 FC901
EP901
C992
C905
B4
B3
P901
C902
L901
C906
R911
C914
R910
B15
R906
K902
R907
D908
B302
D910
D904
R908
C918
R904
PC901
B16
D991
Q991
B227
J702
L709
R920
C903
D901
C907
R905
B501
B301
C913
R901
IC901
HS901
R903
PC902
B502
B503
D952
R992
D954
D992
C965
C963
D951
CP951
C960
L952
EP951
R956
Q951
C908
D903
C909
D902
T901
B515
B14
D956
D957
C987
D953
B611
C979
L959
C989
L955
C997
C966
C969
B101
B17
IC951IC952
B78
D950
C978
JT102JT202
C1
J804
B21
L710
B102
B19
B18
B405
B505
B504
B13
C982
B852
B853
L957
C984
B313
B408
C973
B63
HS952
C2
C962
D960
B22
C815
C816
B20
B103
B203
C814
C813
C812
B12
B35
B69
B402
B403
B404
B126
B309
B307
B306
B308
B212
B507
B330
B509
B314
B79
B219
B868
B605
B202
DI1
S801
R818
B24
L804
C817
B303
B304
B26
B25
L803
L802
B602
B112
B113
B114
B516
B517
CN512
B61
B62
B406
B506
B854
B706
B215
B218
B508
B64
B127
B702
B703
B705
B864
B865
B866
B867
B869
B759
RA3
B28
B27
C806
C807
C808
B305
B310
C801
L801
C810
C809
B872
C818
B410
B204
B104
B31
B32
B115
B226
B123
B315
B316
B754
B317
B318
B755
B604
B855
B603
B858
B859
B860
B861
B856
B857
B66
B606
B607
B65
B863
B1
B409
B2
B870
B760
J801
B36
B106
B107
B29
K801
CN801
B108
B30
B105
B701
B873
CN513
B417
B419
B862
B323
B324
B39
B41
B110
B34
B33
B411
B205
B111
B510
B412
B42
B43
B119
B118
B206
B321
B77
B209
B413
B415
B608
B220
B756
B322
B418
CN802
B125
RA1RA2
J700
J802
R777
C757
B45
Q753
B37
B38
B874
R726
C700
B67
B414
B871
C5
C111
C8
R775
B55
B40
B109
R711
R712
C717
C731
B610
B416
B511
B46
R713
R715
R740
R742
C716
B75
R741
R743
Q756
C711
C715
Q755
C721
B601
B422
R753
C714
R731
C730
B512
R751
B48
B122
R750
R752
B49
C703
B131
B757
B758
B513
B420
EP902
J701
R767
B54
C747
Q743
T1701
R765
B875
B514
B753
C740
B50
C741
C742
R782
C761
C743
C744
C754
C753
C752
C750
IC701
B132
B133
B216
R776
R748
R783
R761
R764
R774
B311
B58
C746
C745
B223
C748
B128
B129
C762
R762
C771
R772
C737
C749
B224
R771
R792
C756
C755
R758
C772
R793
C751
B130
B325
B57
B329
B320
B319
CN3
J703
C707
C1800
B229
D702
C1701
R1721
C1702
R766
B225
Q754
R791
R790
C738
R781
Q744
R780
EP711
B56
R797
B208
B326
B207
B327
B328
CN701
Full Fuse Replacement Marking
Graphic symbol mark
(This symbol means fast blow type fuse.)
should be read as follows ;
FUSE CAUTION
FOR CONTINUED PROTECTION AGAINST RISK
OF FIRE, REPLACE ONLY WITH SAME TYPE
AND RATING OF FUSES ;
1.6 A / 125 V
Marquage Pour Le Remplacement
Complet De Fusible
Le symbole graphique (Ce symbole signifie
fusible de type a fusion rapide.)
doit etre interprete comme suit ;
PRECAUTIONS SUR LES FUSIBLES
POUR UNE PROTECTION CONTINUE CONTRE
DES RISQUES D'INCENDIE, REMPLACER
SEULEMENT PAR UN FUSIBLE DU MEME TYPE ;
1.6 A / 125 V
1-4
Page 5
XV-S60BK/XV-S62SL/XV-S65GD
Precautions for Service
Handling of Traverse Unit and Laser Pickup
1. Do not touch any peripheral element of the pickup or the actuator.
2. The traverse unit and the pickup are precision devices and therefore must not be subjected to
strong shock.
3. Do not use a tester to examine the laser diode. (The diode can easily be destroyed by the
internal power supply of the tester.)
4. To replace the traverse unit, pull out the metal short pin for protection from charging.
5. When replacing the pickup, after mounting a new pickup, remove the solder on the short land
which is provided at the center of the flexible wire to open the circuit.
6. Half-fixed resistors for laser power adjustment are adjusted in pairs at shipment to match the
characteristics of the optical block.
Do not change the setting of these half-fixed resistors for laser power adjustment.
Destruction of Traverse Unit and Laser Pickup by Static Electricity
Laser diodes are easily destroyed by static electricity charged on clothing
or the human body. Before repairing peripheral elements of the traverse
unit or pickup, be sure to take the following electrostatic protection:
1. Wear an antistatic wrist wrap.
2. With a conductive sheet or a steel plate on the workbench on which
the traverse unit or the pick up is to be repaired, ground the sheet
or the plate.
3. After removing the flexible wire from the connector (CN101),
short-circuit the flexible wire by the metal clip.
4. Short-circuit the laser diode by soldering the land which is provided
at the center of the flexible wire for the pickup.
After completing the repair, remove the solder
to open the circuit.
Please refer to "Fig.4" of "Disassembly
method" for details.
Short circuit
Short circuit
Servo control
board
1-5
Page 6
XV-S60BK/XV-S62SL/XV-S65GD
Disassembly method
<Main body>
Removing the top cover (see Fig.1)
1.Remove the two screws A attaching the top cover
on both sides of the body.
2.Remove the three screws B attaching the top cover
on the back of the body.
3.Remove the top cover from the body by lifting the
rear part of the top cover.
ATTENTION: Do not break the front panel tab
fitted to the top cover.
Removing the mechanism assembly
(see Fig.2,3)
* Prior to performing the following procedure, remove
the top cover.
* There is no need to remove the front panel assembly.
B
B
A x 2
Fig.1
B
1.Remove the three screws C attaching the mechanism
assembly on the bottom chassis.
2.The servo control board is removed from the connector
CN512 and CN513 connected with the main board
respectively.
3.Remove the mechanism assembly by lifting the rear part
of the mechanism assembly.
Removing the servo control board
(see Fig.4)
* Prior to performing the following procedure, remove
the top cover and mechanism assembly.
1.Disconnect the card wire from connector CN201 and
CN202 on the servo control board respectively.
2.Disconnect the flexible wire from connector CN101
on the servo control board from pick-up.
Mechanism
assembly
Main board
CN513
Fig.2
Fig.3
CN512
Servo control
board
ATTENTION
At this time, please extract the wire after short-circuited
of two places on the wire in part a with solder.
Please remove the solder two places of part a after
connecting the wire with CN101 when reassembling.
3.Two places in hook b are removed, the servo control board
is lifted, and it is removed.
1-6
Hook b
Hook b
Servo control
board
Fig.4
Page 7
Removing the rear panel (see Fig.5)
XV-S60BK/XV-S62SL/XV-S65GD
*Prior to performing the following procedure, remove
the top cover.
1.Remove the nine screws D attaching the rear panel
on the back of the body.
Removing the front panel assembly
(see Fig.6,7)
* Prior to performing the following procedure, remove
the top cover.
* There is no need to remove the mechanism assembly.
1.Remove the one screw E attaching the front panel
assembly on the bottom chassis.
2.Disconnect the wire from CN3 and JT102,JT202 on
the main board respectively.
3.Hook c and d are removed respectively, and the front
panel assembly is removed.
Removing the main board (see Fig.8)
D
Front panel
assembly
Hook d
D
Hook c
Rear panel
D
Fig.5
E
D
Hook d
Fig.6
* Prior to performing the following procedure, remove
the top cover, mechanism assembly and rear panel.
1.Disconnect the wire from CN3 and JT102,JT202 on
the main board respectively.
2.Remove the four screws F attaching the main board
on the bottom chassis.
Fig.7
F
F
F
Fig.8
F
1-7
Page 8
XV-S60BK/XV-S62SL/XV-S65GD
<Loading assembly section>
Removing the clamper assembly
(See Fig.1)
1.
Remove the four screws A attaching the clamper
assembly.
2.
Move the clamper in the direction of the arrow to
release the two joints a on both sides.
ATTENTION:
When reattaching, fit the clamper to
the two joints a.
Removing the tray (See Fig.2 and 3)
Prior to performing the following procedure, remove
the clamper assembly.
1.
Push b of the slide cam into the slot on the left side
of the loading base until it stops.
2.
Draw out the tray toward the front.
Joint a
A
Joint a
A
AA
Fig.1
ATTENTION:
Before reattaching the tray, slide the
part c of the slide cam to the right as
shown in Fig.3.
Clamper base
Push
Tray
b
Fig.2
Par t c
Slide cam
Fig.3
1-8
Page 9
Removing the traverse mechanism
assembly (See Fig.4 and 5)
XV-S60BK/XV-S62SL/XV-S65GD
Prior to performing the following procedure, remove
the clamper assembly and the tray.
1.
Remove the four screws B attaching the traverse
mechanism assembly.
ATTENTION:
Before reattaching the traverse
mechanism assembly, pass the card
wire extending from the spindle motor
board through the notch d of the
elevator.
Removing the elevator (See Fig.6 and 7)
Prior to performing the following procedure, remove
the clamper assembly, the tray and the traverse
mechanism assembly.
1.
Extend each bar e inside of the loading base
outward and detach the elevator shaft.
B
Traverse mechanism
assembly
B
B
BB
BB
Fig.4
Traverse mechanism assembly
BB
Elevator
Notch d
ATTENTION:
Elevator
When reattaching, first fit the two
shafts on the front of the elevator to
the slots f of the slide cam.
Shafts
Slide cam
Elevator
Fig.5
e
Elevator
Elevator
Loading base
Slots f
e
Fig.6Fig.7
1-9
Page 10
XV-S60BK/XV-S62SL/XV-S65GD
Removing the motor assembly
(See Fig.8 and 9)
Prior to performing the following procedure, remove
the clamper assembly, the tray, the traverse
mechanism assembly and the elevator.
1.
Remove the belt from the pulley.
2.
Remove the screw C attaching the motor assembly.
3.
Turn over the body and remove the screw D
attaching the motor assembly.
4.
Release the two tabs g retaining the motor board.
Belt
C
Motor assembly
Fig.8
Tabs g
Motor assembly
D
Loading base
Fig.9
1-10
Page 11
XV-S60BK/XV-S62SL/XV-S65GD
Pulley gear
Pulley gear bracket
Motor assembly
Pulley gear bracket
E
Idle gear
Fig.10
Idle gear
Pulley gear
Tads h
Pulley gear
Removing the Idle gear / pulley gear /
middle gear / slide cam (See Fig.10 to 12)
Prior to performing the following procedure, remove
the clamper assembly, the tray, the traverse
mechanism assembly, the elevator and the motor
assembly.
1.
Press the two tabs h inward and pull out the idle
gear.
2.
Remove the screw E attaching the pulley gear
bracket. Slide the pulley gear bracket in the direction
of the arrow and pull out the pulley gear.
3.
Slide the slide cam in the direction of the arrow to
release the two joints i and remove upward.
4.
Remove the middle gear.
Slide cam
Joint i
Slide cam
Middle gear
Joint i
Fig.11
Middle gear
Fig.12
Loading base
1-11
Page 12
XV-S60BK/XV-S62SL/XV-S65GD
<Traverse mechanism assembly section>
Removing the feed motor assembly
(See Fig.13)
1.
Unsolder the two soldering j on the spindle motor
board.
2.
Remove the two screws F attaching the feed motor
assembly.
Removing the feed motor
(See Fig.13 to 15)
Prior to performing the following procedure, remove
the feed motor assembly.
1.
Remove the screw G attaching the thrust spring.
Feed motor assembly
F
F
Notch k
Soldering j
Spindle motor board
Pickup
Spindle motor
Fig.13
Feed gear (M)
Thrust spring
ATTENTION:
2.
Remove the feed gear (M).
3.
Pull out the feed gear (E) and the lead screw.
4.
Remove the two screws H attaching the feed motor.
ATTENTION:
When reattaching the thrust spring,
make sure that the thrust spring
presses the feed gear (M) and the feed
gear (E) reasonably.
When reattaching, pass the two cables
extending from the feed motor through
the notch k of the feed holder as
shown in Fig.13.
G
Lead screw
Feed gear (E)
Fig.14
Feed motor
1-12
Feed holder
H
Fig.15
Page 13
XV-S60BK/XV-S62SL/XV-S65GD
Removing the pickup (See Fig.16 and 17)
1.
Remove the screw I attaching the T spring (S) and
the shaft holder. Remove also the plate.
ATTENTION:
2.
Pull out the part l of the shaft upward. Move the part
m in the direction of the arrow and detach from the
spindle base.
3.
Disengage the joint n of the pickup and the shaft in
the direction of the arrow.
4.
Pull out the shaft from the pickup.
5.
Remove the two screws J attaching the actuator.
6.
Disengage the joint of the actuator and the lead
spring. Pull out the lead spring.
When reattaching, make sure that the
T spring (S) presses the shaft.
Shaft holder
I
Plate
T spring (S)
Lead spring
Pickup
Joint n
Part m
Part l
Fig.16
Actuator
J
Actuator
Lead spring
Shaft
Spring
The spring must be under the shaft when you
install pick-up.
Removing the shaft holder / shaft
(See Fig.18)
1.
Remove the screw K attaching the shaft holder.
2.
Remove the shaft.
Pick-up
Pickup
K
Shaft
Fig.17
Shaft
Shaft holder
Fig.18
1-13
Page 14
XV-S60BK/XV-S62SL/XV-S65GD
Removing the spindle motor assembly
(See Fig.19 to 21)
1.
Remove the three screws L attaching the spindle
motor on the bottom of the mechanism base.
ATTENTION:
2.
Remove the three screws M attaching the spindle
base.
When reattaching, pass the card wire
extending from the spindle motor
board through the notch of the spindle
base.
L
L
Spindle motor assembly
Spindle motor
Fig.19
Spindle base
M
L
Fig.20
M
Spindle base
Mechanism base
Fig.21
1-14
Page 15
XV-S60BK/XV-S62SL/XV-S65GD
Adjustment method
(1) Test mode setting method
1)Take out the disc and close the tray.
2)Unplug the power plug.
3)Insert power plug into outlet while pressing both "PLAY" button and "STOP" button of the main body.
4)The player displays "TEST " on the FL display. " " means the player version.
5)When the power supply is turned off, test mode is released.
The mode changes as follows whenever the "CHOICE" button of remote control is pushed in test mode.
TEST_ _ -----------------------
_ _ _ ------------
CHECK ---------------------------------
FL display becomes all lighting ---
----------------------------
Becomes test mode
Version of microcomputer
Check mode
Confirmation of FL display
Not use mode
(2) Initialization method
Please initialize according to the following procedures when microprocessor or pick-up is
exchanged and when the up-grade is done.
1)Makes to test mode.
2)After "FORWARD SKIP" button ( ) of the main body is pushed, "PAUSE" button is pushed.
3)A green progressive indicator lights when about ten seconds pass. Then, it is initialization completion.
(When scan mode is set to the progressive scanning, the indicator is green from red. )
(3) Method of displaying version of microcomputer
1)Makes to test mode and initializes
2)When "CHOICE" button of remote control is pushed once, the figure is displayed on the FL display as follows.
FL Display
FL Display microcomputer (IC2)
Front end microcomputer (IC401)
STANDBY/ON
OPEN
/
TV DVD
3D
TV/VIDEO
REPEAT
PHONIC
CANCEL
TV1 TV2 TV3
123
TV4 TV5 TV6
4
56
TV7 TV8 TV9
89
7
TV
-/-- TV0
0+1010
AUDIO
SUBTITLEANGLE
DIGEST
ZOOM
–
S
U
IO
V
E
R
P
SELECT
R
A
E
L
C
S
–
W
O
L
S
E
L
IT
T
+
CH
VOL
-
ENTER
C
-
CH
H
O
IC
E
RM-SXVS60J REMOTE CONTROL
TV DVD
RETURN
MUTING
PROGRESSIVE
SCAN
N
E
X
S
T
R
L
O
W
M
S
N
O
VFP
+
T
O
B
E
+
E
N
U
VOL
+
N
E
E
R
C
BACK SKIP
Button
(display of current value)
TITLE
Button
(laser ON)
CURSOR UP Button
(firmware upgrade)
CHOICE
Button (switch of mode)
POWER
Button
STANDBY
STANDBY/ON
23_06_16_F9
PROGRESSIVE
Indicator
(for initialize)
PROGRESSIVE
Microcode of decoder
Decoder part (IC509)
FORWARD SKIP
FL Display
XV-S60 DVD/CD PLAYER
(for test mode or
display of jitter value)
Button
(for initialize)
OPEN/CLOSE
PLAY
Button
(for test mode)
SKIP
PAUSE Button
(automatic adjustment
STOP
Button
PAUSEPLAYSTOP
DVD/VIDEO CD/CD
or initialize)
1-15
Page 16
XV-S60BK/XV-S62SL/XV-S65GD
(4) Display of current value of laser
1)Makes to test mode and initializes
2)When "CHOICE" button of remote controller is pushed twice, It is displayed on the FL display, "CHECK".
3)The display of FL display changes from "CHECK" into "LD_ON" if the "TITLE" button of remote controller
is pushed.
4)The laser is turned on if the "BACK SKIP" button ( ) of remote controller is pushed in the state,
and the current value of the laser is displayed on the FL display.
FL Display
LD_0042
As for the current value of the laser, the figure displayed on the
FL display becomes a current value as it is by "mA" unit.
becomes 42mA if displayed as 42.
5)The laser changes from CD into DVD if 3) and 4) of the above-mentioned procedures are done after
the tray is opened and closed pushing the "OPEN/CLOSE" button of the main body.
(The laser changes whenever this is done.)
If the laser current value is 64mA or less, it is roughly good. There is a possibility to which pick-up is
deteriorated, and exchange pick-up, please when there are 65mA or more laser current value.
(5) Display of jitter value
1)Makes to test mode and initializes
2)When "CHOICE" button of remote controller is pushed twice, It is displayed on the FL display, "CHECK".
3)The automatic adjustment starts when test disk (VT-501) is inserted, and "PAUSE" button of the main body
is pushed.
4)When the display of the FL display changes into "CHECK OK", the "PLAY" button of the main body is pushed.
5)The jitter value is displayed on the FL display as follows.
FL Display
JIT_3978
If the indication value is 11% or less, it can be judged by this simple checking method that the signal
read precision of the set is satisfactory.
Please do "Flap adjustment of the pick-up guide shaft" when you replace the pick-up and the spindle
motor when there are 11% or more jitter value.
The jitter value is displayed by the hexadecimal number and refer
to the conversion table of following, please.
1-16
Jitter value
FL display FL display
3818
3828
3838
3848
3858
3868
3878
3888
3898
38A8
38b8
38c8
38d8
38E8
38F8
3918
3928
3938
3948
3958
3968
3978
3988
Conversion
value(%)
4.7
4.8
4.9
5.1
5.2
5.3
5.4
5.5
5.7
5.8
5.9
6.0
6.1
6.3
6.4
6.6
6.7
6.9
7.0
7.1
7.2
7.3
7.5
3998
39A8
39B8
39C8
39D8
39E8
39F8
3A18
3A28
3A38
3A48
3A58
3A68
3A78
3A88
3A98
3AA8
3AB8
3AC8
3AD8
3AE8
3AF8
Conversion
value(%)
7.6
7.7
7.8
7.9
8.1
8.2
8.3
8.5
8.7
8.8
8.9
9.0
9.1
9.3
9.4
9.5
9.6
9.7
9.9
10.0
10.1
10.2
FL display FL display
3B18
3B28
3B38
3B48
3B58
3B68
3B78
3B88
3B98
3BA8
3BB8
3BC8
3BD8
3BE8
3BF8
3C18
3C28
3C38
3C48
3C58
3C68
3C78
3C88
Conversion
value(%)
10.5
10.6
10.7
10.8
10.9
11.1
11.2
11.3
11.4
11.5
11.7
11.8
11.9
12.0
12.1
12.4
12.5
12.7
12.7
12.9
13.0
13.1
13.2
3C98
3CA8
3CB8
3CC8
3CD8
3CE8
3CF8
3D18
3D28
3D38
3D48
3D58
3D68
3D78
3D88
3D98
3DA8
3DB8
3DC8
3DD8
3DE8
3DF8
Conversion
value(%)
13.3
13.5
13.6
13.7
13.8
13.9
14.1
14.3
14.4
14.5
14.7
14.8
14.9
15.0
15.1
15.3
15.4
15.5
15.6
15.7
15.9
16.0
This jitter value is not correctly
displayed according to the version
of the microcomputer.
Please do the microcomputer in
the up-grade when the jitter value
is not correctly displayed.
Front end microcomputer (IC401)
Version : 06
Decoder part (IC509)
Version : 18
The jitter value is not correctly
displayed when the version is
below this figure.
(This version is contained. )
Page 17
XV-S60BK/XV-S62SL/XV-S65GD
(6) Upgrading of firmware
1)The power supply is turned on pushing the "POWER" button.
2)The up-grade disk is inserted.
3)When FL display of the main body changes from "READING" into "UPGRADE", cursor UP button ( ) of
remote controller is pushed.
4)The up-grade starts if the entire screen becomes blue and it is displayed, "Upgrade progress".
5)The tray opens automatically, the up-grade disk is removed.
6)The up-grade ends if the tray closes automatically, and the screen returns to the normal screen.
7)Please confirm the version of the microcomputer after makes to test mode and initializes.
Upgrade progress...
Upgrading (blue screen)After inserting the up-grade disk
When up-grade is completed
The disk for the up-grade is usually one piece. The disk becomes two pieces according to
the version. In that case, please note the undermentioned content.
* The up-grade is done by using the STEP1 disk according to "1)" and "4)" of the above-mentioned procedure.
* The tray opens automatically after a few seconds and exchange for the disk of STEP2, please.
* The tray closes automatically. There is only about five second time that the tray opens this time,
and replace the disk quickly between those, please.
ATTENTION
When the tray shuts with the STEP1 disk left for the tray
The up-grade starts again and exchange for the STEP2 disk, please when the tray opens automatically.
When the tray closes with there no disk in the tray
The tray opens automatically and turn off the power supply once, please pushing the "POWER" button
in the state. When the STANDBY indicator lights, the STEP2 disk is putting in the tray and "POWER"
button is pushed.
* After the up-grade ends, the STEP2 disk is removed because the tray opens automatically.
* Afterwards, it is the same as 6),7) of the above-mentioned procedures.
1-17
Page 18
XV-S60BK/XV-S62SL/XV-S65GD
Flap adjustment of the pick-up guide shaft
<Tool list for adjustment>
Stud (four pieces set)
Parts No. : JIGXVS40
Extension cord set (two cord and two board)
Parts No. : EXTXVS40CB
Hex wrench for adjustment
Off-the-shelf (1.3mm)
Test disc
VT-501 or VT-502
Assistance board
(Connect to main board)
XV-S40
MAIN CONNECT
Extension
cord
XV-S40 CONTROL CONNECT
Assistance board
(Connect to servo control board)
One is not used though it is one
set which consists of four units.
Stud
<Adjustment preparation>
1.The mechanism assembly is made in the state from the main body from which is detached referring to the
disassembly method.
2.Three studs are installed in the mechanism assembly respectively.
3.The servo control board is removed from the mechanism assembly, and puts into the state set up as shown
in figure. (Each wire connected by the servo control board this time leaves the connection maintained.)
Between shaft and hook of mechanism assembly of figure Board is put And, the board is inclined in the
direction of the arrow on figure as much as possible.
4.The extension cord is inserted in the connector of the assistance board respectively.
The main board is connected with the servo control board as shown in figure.
Shaft
Hook
Mechanism assembly
Extension
Assistance
board
Servo control board
Stud
cord
Mechanism assembly
Stud
Servo control board
Assistance
board
Main board
<Adjustment>
1.Puts into the state to display the jitter value on the FL display referring to "Display of the jitter value".
2.The adjustment screw under the traverse mechanism is turned with hex wrench, and matches so that the
jitter value displayed on the FL display may become minimum value.
Adjustment screw a Adjustment screw b
<POINT>
1.turns in the forward or the opposite direction,
and makes to the position where the jitter value
is good the half rotation of adjustment screw a
and b(180 degrees) respectively.
Adjustment
screw c
2.Afterwards, adjustment screw b and c are turned
in the same way, and makes to the best position.
1-18
Page 19
Troubleshooting
Servo volume
Press OPEN
/CLOSE key
XV-S60BK/XV-S62SL/XV-S65GD
Is tray
operation
Confirmation of tray drive circuit
N
and circuit in surrounding
correct?
Y
Is the traverse moving
along the innermost
N
perimeter for SW detection?
Y
"NO DISC" message appears
Y
immediately after vertical
movement of the pick-up lens
N
The state that DISC does not rotate continues for
several seconds, and becomes NO DISC or an
error display afterwards.
The rotation of DISC becomes high-speed and
abnormal, and becomes NO DISC or an error
display afterwards.
N
Is focus retraction OK?
FE
OFF
Even when it retracts
correctly, if it is out of focus
and makes repeated retries
with a clicking sound, it is
in error.
ON
See "(4) Focus ON error"
N
in "Check points for
individual errors"
Y
Is tracking retraction OK?
See "(3) Traverse movement error"
in "Check points for individual errors"
See "(2) Disk detection, distinction error"
in "Check points for individual errors"
Y
See "(1) Spindle startup error"
in "Check points for individual errors"
Is the inter-layer jump OK?
FE
LO LI
A
Two layers of DVD only.
N
(8) Inter-layer
jump error
Y
TE
OFF
If TE waveform reappears
or fails to converge after the
TE retraction, it is in error.
ON
Y
Is the spindle servo
locked correctly?
Is the RF OUT waveform
locked correctly?
Y
A
See "(5) Tracking ON error"
N
in "Check points for
individual errors"
See "(6) Spindle CLV error"
N
in "Check points for
individual errors"
Has the disc information
been collected?
Stop will result
Y
Is playback
N
possible?
Y
OK !
N
(7) Address read
error
Check (9),(10),(11), and
(12) items in "Check points
for individual errors"
1-19
Page 20
XV-S60BK/XV-S62SL/XV-S65GD
Check points for each error
(1) Spindle start error
1.Defective spindle motor
*Are there several ohms resistance between each pin of CN201 "5-6","6-7","5-7"?
(The power supply is turned off and measured.)
*Is the sign wave of about 100mVp-p in the voltage had from each terminal?
[ CN201"9"(H1-),"10"(H1+),"11"(H2-),"12"(H2+),"13"(H3-),"14"(H3+) ]
2.Defective spindle motor driver (IC251)
*Has motor drive voltage of a sine wave or a rectangular wave gone out to each terminal(SM1~3)
of CN201"5,6,7" and IC251"2,4,7"?
*Is FG pulse output from the terminal of IC251"24"(FG) according to the rotation of the motor?
*Is it "L(about 0.9V)" while terminal of IC251"15"(VH) is rotating the motor?
3.Has the control signal come from servo IC or the microcomputer?
*Is it "L" while the terminal of IC251"18"(SBRK) is operating?
Is it "H" while the terminal of IC251"23"(/SPMUTE) is operating?
*Is the control signal input to the terminal of IC251"22"(EC)?
(changes from VHALF voltage while the motor is working.)
*Is the VHALF voltage input to the terminal of IC251"21"(ECR)?
4.Is the FG signal input to the servo IC?
*Is FG pulse input to the terminal of IC201"53"(FG) according to the rotation of the motor?
(2) Disc Detection, Distinction error (no disc, no RFENV)
* Laser is defective.
* Front End Processor is defective (IC101).
* APC circuit is defective. --- Q101,Q102.
* Pattern is defective. --- Lines for CN101 - All patterns which relate to pick-up and patterns between IC101
* Servo IC is defective (IC201).
* IC101 --- For signal from IC101 to IC201, is signal output from IC101 "20" (ASOUT) and
IC101 "41"(RFENV) and IC101 "22" (FEOUT)?
1-20
Page 21
(3) Traverse movement NG
1.Defective traverse driver
*Has the voltage come between terminal of CN101 "1" and "2" ?
2.Defective BTL driver (IC271)
*Has the motor drive voltage gone out to IC271"17" or "18"?
3.Has the control signal come from servo IC or the microcomputer?
*Is it "H" while the terminal of IC271"9"(STBY1) ?
*TRSDRV Is the signal input? (IC201 "51")
4.TRVSW is the signal input from microcomputer? (IC401 "50")
(4) Focus ON NG
* Is FE output ? --- Pattern, IC101
* Is FODRV signal sent ? (R279) --- Pattern, IC201
* Is driving voltage sent ?
IC271 "13", "14" --- If NG, pattern, driver, mechanical unit .
* Mechanical unit is defective.
(5) Tracking ON NG
XV-S60BK/XV-S62SL/XV-S65GD
* When the tracking loop cannot be drawn in, TE shape of waves does not settle.
* Mechanical unit is defective.
Because the self adjustment cannot be normally adjusted, the thing which cannot be normally
drawn in is thought.
* Periphery of driver (IC271)
Constant or IC it self is defective.
* Servo IC (IC201)
When improperly adjusted due to defective IC.
(6) Spindle CLV NG
* IC101 -- "35"(RF OUT), "30"(RF-), "31(RF+).
* Does not the input or the output of driver's spindle signal do the grip?
* Has the tracking been turned on?
* Spindle motor and driver is defective.
* Additionally, "IC101 and IC201" and "Mechanism is defective(jitter)", etc. are thought.
(7) Address read NG
* Besides, the undermentioned cause is thought though specific of the cause is difficult because various
factors are thought.
Mechanism is defective. (jitter)
IC201, IC301, IC401.
The disc is dirty or the wound has adhered.
(8) Between layers jump NG (double-layer disc only)
Mechanism defective
Defect of driver's IC(IC271)
Defect of servo control IC(IC201)
1-21
Page 22
XV-S60BK/XV-S62SL/XV-S65GD
(9) Neither picture nor sound is output
1.It is not possible to search
*Has the tracking been turned on?
"(5) Tracking ON NG" in "Check points for each error"
*To
*Is the feed operation normal?
To "(3) traverse movement NG" in "Check points for each error" when it is not normal.
Are not there caught of the feeding mechanism etc?
(10) Picture is distorted or abnormal sound occurs at intervals of several seconds.
Is the feed operation normal?
Are not there caught of the feeding mechanism etc?
(11) Others
The image is sometimes blocked, and the image stops.
The image is blocked when going to outer though it is
normal in surroundings in the disk and the stopping
symptom increases.
when the tracking is not normal.
There is a possibility with bad jitter
value for such a symptom.
(12) CD During normal playback operation
a) Is TOC reading normal?
Displays total time
for CD-DA.
Shifts to double-speed
mode for V-CD.
YES
NO
b)Playback possible?
*--:-- is displayed during FL search.
According to [It is not possible to search ] for DVD(9), check the feed
and tracking systems.
*No sound is output although the time is displayed.(CA-DA)
DAC, etc, other than servo.
*The passage of time is not stable, or picture is abnormal.(V-CD)
*The wound of the disc and dirt are confirmed.
1-22
Page 23
Description of major ICs
AK93C65AF-X(IC403):EEPROM
1.Pin layout
XV-S60BK/XV-S62SL/XV-S65GD
PE
VCC
CS
SK
1
2
3
4
2.Block diagram
DI
CS
8
7
6
5
INSTRUCTION
REGISTER
NC
GND
DO
DI
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
DATA
REGISTER
ADD.
BUFFERS
16
R/W AMPS
AND
AUTO ERASE
DECODER
DO
16
EEPROM
4096bit
256 x 16
SK
PE
3.Pin function
Pin No.
1
2
3
4
5
6
7
8
Symbol
PE
VCC
CS
SK
DI
DO
GND
NC
Program enable (Resistance with built-in pull-up)
Power supply terminal
Chip select
Serial clock input
Serial data input
Serial data output
Connect to ground
Non connect
Description
Attention : Resistors of pin No.1(PE) are 2.5M ohm.
VREF
VPP SW
VPP
GENERATOR
1-23
Page 24
XV-S60BK/XV-S62SL/XV-S65GD
AN8702FH(IC101):Frontend processor
1.Pin layout
HDTYPE
VIN12
VIN11
GND1
VIN4
VIN3
VIN2
VIN1
VREF1
VCC1
VIN10
VIN9
VIN8
VIN7
646362616059585756555453525150
VIN6
VIN5
49
2.Pin function
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Symbol
PC1
PC01
PC2
PC02
TGBAL
TBAL
FBAL
POFLT
DTRD
IDGT
STANDBY
SEN
SCK
STDI
RSEL
JLINE
TEN
TEOUT
ASN
ASOUT
FEN
FEOUT
VSS
TG
VDD
GND2
VREF2
VCC2
VHALF
DFLTON
DFLTOP
DSFLT
GND3
1
PC1
2
PC01
3
PC2
4
PC02
5
TGBAL
6
TBAL
7
FBAL
8
POFLT
9
DTRD
10
IDGT
SEN
SCK
STDI
RSEL
JLINE
11
12
13
14
15
16
171819202122232425262728293031
TEN
TEOUT
STANDBY
I/O Description
Disc detection signal input (DVD)
I
I/O
Laser current control terminal
I
Disc detection signal input (CD)
I/O
Laser current control terminal
I
Tangential phase balance control terminal
I
Tracking balance control terminal
I
Focus balance control terminal
O
Track detection threshold level terminal
I
Data slice part data read signal input terminal
(For RAM)
I
Data slice part address part gate signal input
terminal( For RAM)
I
Standby mode control terminal
I
SEN(Serial data input terminal)
I
SCK(Serial data input terminal)
I
STDI(Serial data input terminal)
I
J-line setting input(FEP)
O
Tracking error signal output terminal
O
Full adder signal output
I
Focus error output amplifier reversing input terminal
O
Focus error signal output terminal
-
Connect to GND
O
Tangential phase error signal output terminal
-
Power supply terminal 3V
-
Connect to GND
O
VREF2 voltage output terminal
-
Power supply terminal 5V
O
VHALF voltage output terminal
O
Equivalence RF-
O
Equivalence RF+
-
Connect to GND
AN8702FH
FEN
ASN
FEOUT
ASOUT
VSS
TG
VDD
Pin No.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
48
RFINN
RFINP
47
TESTSG
46
AGCO
45
AGCG
44
PEAK
43
42
BOTTOM
41
RFENV
40
BDO
39
OFTR
38
DCRF
37
RFC
36
VCC3
35
RFOUT
34
RFDIFO
33
GND3
32
VCC2
GND2
VREF2
VHALF
DFLTON
DSFLT
DFLTOP
Symbol I/O Description
RFDIFO
To TP101
RFOUT
VCC3
-
Power supply terminal 5V
-
RFC
All addition amplifier capacitor terminal
DCRF
OFTR
BDO
RFENV
BOTTOM
PEAK
AGCG
O
OFTR output terminal
O
O
Drop out
O
RF envelope output terminal
O
Bottom envelope detection filter terminal
O
Peak envelope detection filter terminal
O
AGC amplifier gain control terminal
AGCO
TESTSG
RFINP
RFINN
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VCC1
VREF1
VIN1
VIN2
VIN3
VIN4
GND1
VIN11
VIN12
HDTYPE
I
TEST signal input terminal
I
RF signal positive input terminal
I
RF signal negative input terminal
I
Focus input of external division into two terminal
I
Focus input of external division into two terminal
I
I
I
Focus input of external division into two terminal
I
Focus input of external division into two terminal
-
Power supply terminal 5V
O
VREF1 voltage output terminal
I
External division into four (DVD/CD) RF input
terminal1
I
External division into four (DVD/CD) RF input
terminal2
I
External division into four (DVD/CD) RF input
terminal3
I
External division into four (DVD/CD) RF input
terminal4
-
Connect to GND
I
Tracking input
I
Tracking input
-
Connect to ground
1-24
Page 25
BA5983FM-X (IC271) : 4CH DRIVER
1.Block diagram
27
26
25
28
Vcc
10k
24
20k
23 22
10k
20k
21
STAND BY
CH4
20
Vcc
XV-S60BK/XV-S62SL/XV-S65GD
17 16
18
19
10k
10k
10k
Level Shift
10k
10k
15
10k
10k
10k
Level Shift
10k
Level Shift
10k
10k
Level Shift
10k
12
10k
10k
10k
10k
13
Vcc
10
10k
10k
11
STAND BY
CH1/2/3
1
2
3
5
4
6
7
89
2.Pin function
Pin No. Pin No.Symbol SymbolI/O I/OFunction Function
10
11
12
13
14
1
2
3
4
5
6
7
8
9
BIAS IN
OPIN1(+)
OPIN1(-)
OPOUT1
OPIN2(+)
OPIN2(-)
OPOUT2
GND
STBY1
PowVcc1
VO2(-)
VO2(+)
VO1(-)
VO1(+)
Input for Bias-amplifier
I
Non inverting input for CH1 OP-AMP
I
Inverting input for CH1 OP-AMP
I
Output for CH1 OP-AMP
O
Non inverting input for CH2 OP-AMP
I
Inverting input for CH2 OP-AMP
I
Output for CH2 OP-AMP
O
Substrate ground
-
Input for CH1/2/3 stand by control
I
Vcc for CH1/2 power block
-
Inverted output of CH2
O
Non inverted output of CH2
O
Inverted output of CH1
O
Non inverted output of CH1
O
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VO4(+)
VO4(-)
VO3(+)
VO3(-)
PowVcc2
STBY2
GND
OPOUT3
OPIN3(-)
OPIN3(+)
OPOUT4
OPIN4(-)
OPIN4(+)
PreVcc
O
Non inverted output of CH4
O
Inverted output of CH4
O
Non inverted output of CH3
O
Inverted output of CH3
-
Vcc for CH3/4 power block
I
Input for Ch4 stand by control
-
Substrate ground
O
Output for CH3 OP-AMP
I
Inverting input for CH3 OP-AMP
I
Non inverting input for CH3 OP-AMP
O
Output for CH4 OP-AMP
I
Inverting input for CH4 OP-AMP
I
Non inverting input for CH4 OP-AMP
-
Vcc for pre block
10k
10k
14
74LCX373MTC-X(IC512,IC513)
1.Pin layout
1
OE
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10
GND
20
19
18
17
16
15
14
13
12
11
2.Pin function
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Symbol Description
D0~D7
LE
OE
Q0~Q7
Data inputs
Latch enable input
Output enable input
3-State latch outputs
3.Truth table
INPUTS OUTPUTS
LE
X
H
H
L
OE
H
L
L
L
Dn
X
L
H
X
H = HIGH Voltage level
L = LOW Voltage level
Z = High impedance
X = Immaterial
Q0 = Previous Q0 before HIGH to LOW transition of latch enable
Qn
Z
L
H
Q0
1-25
Page 26
XV-S60BK/XV-S62SL/XV-S65GD
BA6664FM-X(IC251):Spindle motor driver
1.Pin layout
1
NC
A3
NC
A2
NC
NC
A1
29
GND
H1+
10
H1-
11
H2+
12
H2-
13
H3+
14
H3-
2.Pin function
28
2
3
4
5
6
7
8
9
RNF
27
VM
26
GSW
25
VCC
24
FG
23
PS
22
EC
30
21
ECR
20
FR
19
FG2
18
SB
17
CNF
16
BR
15
VH
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
NC
A3
NC
A2
NC
NC
A1
GND
H1+
H1-
H2+
H2-
H3+
H3-
VH
BR
CNF
SB
FG2
FR
ECR
EC
PS
FG
VCC
GSW
VM
RNF
I/O
-
O
-
O
-
-
O
I
I
I
I
I
I
I
-
-
O
-
I
I
O
O
-
O
-
O
-
-
Description
Non connect
Output 3 for spindle motor
Non connect
Output 2 for spindle motor
Non connect
Non connect
Output 1 for spindle motor
Connect to ground
Positive input for hall input AMP 1
Negative input for hall input AMP 2
Positive input for hall input AMP 2
Negative input for hall input AMP 2
Positive input for hall input AMP 3
Negative input for hall input AMP 3
Hall bias terminal
Non connect
Capacitor connection pin for phase compensation
Short brake terminal
Non connect
Non connect
Torque control standard voltage input terminal
Torque control voltage input terminal
Start/stop switch (power save terminal)
FG signal output terminal
Power supply for signal division
Gain switch
Power supply for driver division
Resistance connection pin for output current sense
Connect to ground
Connect to ground
1-26
Page 27
K4S643232E-TC70(IC505):DRAM
1.Block diagram
Bank select
XV-S60BK/XV-S62SL/XV-S65GD
I/O control
LWE
Data input register
LDQM
refresh counter
Row buffer
Address register
CLK
Row decoder
512K x 32
512K x 32
512K x 32
512K x 32
ADD
LCBR
LRAS
Col. buffer
Column decoder
Latency & burst length
LCKE
LRAS
LCBR LWE
LCAS LWCBR
Programming register
Timing register
CLK CKE CS RAS CAS WE DQM
2.Pin function
Symbol Description Symbol Description
CLK
CS
CKE
A0~A10
BA0,1
RAS
CAS
WE
System clock signal input
Chip select input
Clock enable
Address
Bank select address
Row address strobe
Column address strobe
Write enable
DQM0~3
DQ0~31
VDD
VSS
VDDQ
VSSQ
NC
Data input/output mask
Data input/output
Power supply terminal
Connect to ground
Power supply terminal
Connect to ground
Non connect
Sense AMP
Output buffer
DQI
LDQM
1-27
Page 28
XV-S60BK/XV-S62SL/XV-S65GD
MN102L25GGM1(IC401):Unit CPU
Pin function
Pin No. Pin No.
Symbol Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
WAIT
RE
SPMUTE
WEN
LMMUTE
CS1
CS2
CS3
DRVMUTE
SPKICK
LSIRST
WORD
A0
A1
A2
A3
VDD
SYSCLK
VSS
XI
XO
VDD
OSCI
OSCO
MODE
A4
A5
A6
A7
A8
A9
A10
A11
VDD
A12
A13
A14
A15
A16
A17
A18
A19
VSS
A20
TXSEL
HAGUP
TCLOSE
TOPEN
HMFON
TRVSW
I/O I/O
Micon wait signal input
I
Read enable
O
Spindle muting output to IC251
O
Write enable
O
Loading motor standby control
O
Chip select for ODC
O
Connect to TP166
Non connect
Driver mute
O
Spin kick (Non connect)
O
LSI reset
O
Bus selection input
O
Address bus 0 for CPU
O
Address bus 1 for CPU
O
Address bus 2 for CPU
O
Address bus 3 for CPU
O
Power supply
Connect to TP169
Ground
Not use (Connect to vss)
Connect to TP170
Power supply
Clock signal input
I
Clock signal output
O
CPU Mode selection input
I
Address bus 4 for CPU
O
Address bus 5 for CPU
O
Address bus 6 for CPU
O
Address bus 7 for CPU
O
Address bus 8 for CPU
O
Address bus 9 for CPU
O
Address bus 10 for CPU
O
Address bus 11 for CPU
O
Power supply
Address bus 12 for CPU
O
Address bus 13 for CPU
O
Address bus 14 for CPU
O
Address bus 15 for CPU
O
Address bus 16 for CPU
O
Address bus 17 for CPU
O
Non connect
Non connect
Ground
Non connect
Connect to TP910
-
O
Tray close signal
I/O
Tray open signal
I/O
Detection switch of traverse
I
inside
Function
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SWUPDN
SWOPEN
ADSCEN
VDD
FEPEN
SLEEP
BUSY
REQ
CIRCEN
-
VSS
EPCS
EPSK
DPDI
EPDO
VDD
SCLKO
S2UDT
U2SDT
CPSCK
SDIN
SDOUT
-
-
NMI
ADSCIRQ
ODCIRQ
DECIRQ
CSSIRQ
ODCIRQ2
ADSEP
RST
VDD
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
TEST8
VSS
D0
D1
D2
D3
D4
D5
D6
D7
Function
Elevator UP/DOWN switch detect
I
Tray OPEN/CLOSE switch detect
I
Serial enable signal for ADSC
O
Power supply
Serial enable signal for FEP
O
Standby signal for FEP
O
Non connect
Communication Request
O
CIRC command select
O
Non connect
Ground
EEPROM chip select
O
EEPROM clock
O
EEPROM data input
I
EEPROM data output
O
Power supply
Communication clock
I
Communication input data
I
Communication output data
O
Clock for ADSC serial
O
ADSC serial data input
I
ADSC serial data output
O
Not use
Not use
Not use
Interrupt input of ADSC
I
Interrupt input of ODC
I
Interrupt input of ZIVA
I
Not use
Interruption of system control
I
Address data selection input
I
Reset input
I
Power supply
Test signal 1 input
I
Test signal 2 input
I
Test signal 3 input
I
Test signal 4 input
I
Test signal 5 input
I
Test signal 6 input
I
Test signal 7 input
I
Test signal 8 input
I
Ground
Data bus 0 of CPU
I/O
Data bus 1 of CPU
I/O
Data bus 2 of CPU
I/O
Data bus 3 of CPU
I/O
Data bus 4 of CPU
I/O
Data bus 5 of CPU
I/O
Data bus 6 of CPU
I/O
Data bus 7 of CPU
I/O
1-28
Page 29
MN103S13BDA(IC301):Optical disc controller
1.Pin layout
DMARQ
NIOWR
VSS
NIORD
IORDY
NDMACK
VDD
INTRQ
NIOCS16
DA1
VSS
NPDIAG
DA0
DA2
VDD
NCS1FX
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
HDD15
HDD0
HDD14
VDD
HDD1
HDD13
HDD2
VSS
HDD12
VDD
HDD3
HDD11
HDD4
HDD10
VDD
HDD5
HDD9
VSS
HDD6
HDD8
HDD7
VDDH
NRESET
MASTER
NINT0
NINT1
WAITDOC
NMRST
DASPST
VDD
OSCO2
OSCI2
UATASEL
VSS
PVSSDRAM
PVDDDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3738394041424344454647484950515253545556575859606162636465666768697071
129
MN103S13BDA
NCS3FX
NDASP
NTRYCL
128
127
126
VDD
NEJECT
125
124
VSS
123
MONI0
MONI1
122
121
MONI2
MONI3
120
119
SDATA
SCLOCK
118
117
VDD
116
DAT0
115
DAT1
114
XV-S60BK/XV-S62SL/XV-S65GD
DAT2
DAT3
CHCK40
NCLDCK
SUBC
113
112
111
110
109
108
SBCK
107
VSS
106
P0
105
P1
104
PVDD
103
PVSS
102
VDD
101
OSCO1
100
OSCI1
99
VSS
98
LRCK
97
BLKCK
96
IPFLAG
95
DACCLK
94
DACLRCK
93
DA C DATA
92
NTRON
91
LG
90
JMPINH
89
IDHOLD
88
SBCK/PLLOK
87
CLKOUT2
86
VDD
85
NRST
84
MMOD
83
VSS
82
CPDET1
81
CPDET2
80
BDO
79
IDGT
78
DTRD
77
TEHLD
76
VDD
75
CLKOUT1
74
CPUDT0
73
CPUDT1
72
2.Block diagram
DVD-ROM
Formatter
CGEN
MODE
CPUADR17
CPUADR16
VSS
CPUADR15
CPUADR14
CPUADR13
CD-PRE
Instruction
memory
(40KB)
DATA
MEMORY
(6KB)
VDD
CPUADR9
CPUADR8
CPUADR11
CPUADR10
CPUADR7
CPUADR12
Formatter
General purpose IO bus
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
i /t
High speed IO bus
32 bit
CPU core
GCAL
CPUADR1
VSS
CPUADR0
ECC
NCS
NWR
NRD
VDD
CPUDT7
CPUDT6
PVPPDRAM
PVDDDRAM
PTESTDRAM
Host i / f
MPEG i / t
DMA
BCU
DRAMC
CPUDT5
CPUDT4
CPUDT3
PVSSDRAM
VSS
CPUDT2
ATAPI
4Mbit
DRAM
WDT
16 bit
timer x 2
SYSTEM
i / f
INTC
1-29
Page 30
XV-S60BK/XV-S62SL/XV-S65GD
3.Pin function (1/3)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
HDD15
HDD0
HDD14
VDD
HDD1
HDD13
HDD2
VSS
HDD12
VDD
HDD3
HDD11
HDD4
HDD10
VDD
HDD5
HDD9
VSS
HDD6
HDD8
HDD7
VDDH
NRESET
MASTER
NINT0
NINT1
WAITDOC
NMRST
DASPST
VDD
OSCO2
OSCI2
UATASEL
VSS
PVSSDRAM
PVDDDRAM
CPUADR17
CPUADR16
VSS
CPUADR15
CPUADR14
CPUADR13
CPUADR12
VDD
CPUADR11
CPUADR10
CPUADR9
CPUADR8
CPUADR7
CPUADR6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
O
O
O
O
I
-
O
I
I
-
I
I
-
I
I
I
I
-
I
I
I
I
I
I
Description
ATAPI Data
ATAPI Data
ATAPI Data
Power supply 3V
ATAPI Data
ATAPI Data
ATAPI Data
Connect to GND
ATAPI Data
Power supply 2.7V
ATAPI Data
ATAPI Data
ATAPI Data
ATAPI Data
Power supply 3V
ATAPI Data
ATAPI Data
Connect to GND
ATAPI Data
ATAPI Data
ATAPI Data
ATAPI Reset input
ATAPI Master/slave select
Interruption of system control 0
Interruption of system control 1
Wait control of system control
Reset of system control (Connect to TP302)
Setting of initial value of DASP signal
Power supply 3V
Non connect
Non connect
Connect to VSS
Connect to GND
Connect to VSS
Connect to VDD(2.7V)
System control address
System control address
Connect to GND
System control address
System control address
System control address
System control address
Power supply 2.7V
System control address
System control address
System control address
System control address
System control address
System control address
1-30
Page 31
3.Pin function (2/3)
XV-S60BK/XV-S62SL/XV-S65GD
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
VSS
CPUADR0
NCS
NWR
NRD
VDD
CPUDT7
CPUDT6
PVPPDRAM
PTESTDRAM
PVDDDRAM
PVSSDRAM
CPUDT5
CPUDT4
CPUDT3
VSS
CPUDT2
CPUDT1
CPUDT0
CLKOUT1
VDD
TEHLD
DTRD
IDGT
BDO
CPDET2
CPDET1
VSS
MMOD
NRST
VDD
CLKOUT2
SBCK/PLLOK
IDOHOLD
JMPINH
LG
NTRON
DAC DATA
DACLRCK
DACCLK
IPFLAG
BLKCK
LRCK
VSS
OSCI1
I/O
I
I
I
I
I
I
I
I
I
I/O
I/O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
O
-
O
O
O
I
I
I
-
I
I
-
O
O
O
O
O
I
O
O
I
I
I
I
-
I
Description
System control address
System control address
System control address
System control address
System control address
Connect to GND
System control address
System control chip select
Writing system control
Reading system control
Power supply 3V
System control data
System control data
Connect to VSS
Connect to VSS
Connect to VDD(2.7V)
Connect to VSS
System control data
System control data
System control data
Connect to GND
System control data
System control data
System control data
Clock signal output (16.9/11.2/8.45MHz)
Power supply 3V
Mirror gate (Connect to TP141)
Data frequency control switch (Connect to TP304)
CAPA switch
RF Dropout/BCA data
Outer capacity detection
Inner capacity detection
Connect to GND
Connect to VSS
System reset
Power supply 3V
Clock 16.9MHz
Flame mark detection
ID gate for tracking holding
Jump prohibition
Land/group switch
Tracking ON
Serial data output (Connect to TP148)
Identification signal of L and R (Connect to TP149)
Clock for serial data output
Input of IP flag
Sub code/block/input clock
Identification signal of L and R (Connect to VSS)
Connect to GND
Oscillation input terminal 16.9MHz
1-31
Page 32
XV-S60BK/XV-S62SL/XV-S65GD
3.Pin function (3/3)
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Symbol
OSCO1
VDD
PVSS
PVDD
P1
P0
VSS
SBCK
SUBC
NCLDCK
CHCK40
DAT3
DAT2
DAT1
DAT0
VDD
SCLOCK
S DATA
MONI3
MONI2
MONI1
MONI0
VSS
NEJECT
VDD
NTRYCL
NDASP
NCS3FX
NCS1FX
VDD
DA2
DA0
NPDIAG
VSS
DA1
NIOCS16
INTRQ
VDD
NDMACK
IORDY
NIORD
VSS
NIOWR
DMARQ
I/O
O
-
-
I/O
I/O
-
O
I
I
I
I
I
I
I
I/O
I/O
O
O
O
O
-
I
-
I
I/O
I
I
I/O
I/O
I/O
I/O
O
O
-
I
O
I
I/O
O
Description
Oscillation output terminal 16.9MHz
Power supply 3V
Connect to GND
Power supply 3V
Terminal master polarity switch input
CIRC-RAM,OVER/UNDER Interruption
Connect to GND
Clock output for sub code,serial input
Sub code,serial input
Sub code,flame clock input
Clock is read to DAT3~0 (Output of division frequency from ADSC)
Data is read from disc (Going side by side output from ADSC)
Data is read from disc (Going side by side output from ADSC)
Data is read from disc (Going side by side output from ADSC)
Data is read from disc (Going side by side output from ADSC)
Power supply 3V
Debug serial clock (270 ohm pull up)
Debug serial data (270 ohm pull up)
Internal good title monitor (Connect to TP150)
Internal good title monitor (Connect to TP151)
Internal good title monitor (Connect to TP152)
Internal good title monitor (Connect to TP153)
Connect to GND
Eject detection
Power supply 2.7V
Non connect (Tray close detection)
ATAPI drive active / slave connect I/O
Non connect (ATAPI host chip select)
Non connect (ATAPI host chip select)
Power supply 3V
ATAPI host address
Non connect (ATAPI host address)
ATAPI Slave master diagnosis input
Connect to GND
Non connect (ATAPI host address)
Output of selection of width of ATAPI host data bus
ATAPI Host interruption output
Power supply 3V
Non connect (ATAPI Host DMA characteristic)
ATAPI Host ready output (Connect to TP157)
Non connect (ATAPI host read)
Connect to GND
ATAPI Host write
ATAPI Host DMA request (Connect to TP159)
1-32
Page 33
MN67706ZY (IC201) : Auto digital servo controller
1.Pin layout
33VDD
33VSS
TEST
MINTEST
NCLDCK/JUMP
SUBC
IPFLAG
DACCLK
NTRON
DACDATA/LG
DACLRCK/JMPINH
IDHOLD
SBCK/PLLOK
BLKCK/CPDET1
LRCK/CPDET2
IDGT/TEMUTE
DTRD
25VDD
25VSS
TILTN
75747372717069686766656463626160595857565554535251
CHCK40
DAT3
DAT2
DAT1
DAT0
33VSS
33VDD
XRESET
ENS
ENC
CPUIRQ
CPUCLK
CPUDTIN
CPUDTOUT
MONA
MONB
MONC
25VSS
25VDD
LDCUR(AD6)
TDOFS(AD5)
TG(AD4)
RFENV(AD3)
TX
NC
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
123456789
MN67706ZY
101112131415161718192021222324
TILT
TILTPFGSPDRV
TRSDRV
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
XV-S60BK/XV-S62SL/XV-S65GD
TSTSG
BDO
SYSCLK
OFTR
33VDD
33VSS
FBAL
TBAL
TGBAL
AVSS
ROUT
LOUT
AVDD
JLINE
DBALO
VCOF
TRCRS
CMPIN
LPFOUT
LPFIN
AVSS
HPFOUT
HPFIN
AVDD
VFOSHORT
TE(AD1)
FE(AD0)
AS(AD2)
AVSS
AVDD
TRDRV(DA0)
FODRV(DA1)
ARF
NARF
IREF1
IREF2
DSLF1
AVDD
DSLF2
PLPG
VHALF
PLFG
VREFH
2.Pin functions (1/3)
Pin No. Symbol I/O Description
I
AS : Full adder signal(FEP)
I
Phase difference/3 beam tracking error(FEP)
I
Focus error(FEP)
Apply 3.3V(For analog circuit)
Focus drive(DRVIC)
Tracking drive(DRVIC)
Ground(For analog circuit)
I
Equivalence RF+(FEP)
I
Equivalence RF-(FEP)
I
Reference current1(For DBAL)
I
Reference current2(For DBAL)
Connect to capacitor1 for DSL
Connect to capacitor2 for DSL
Apply 3.3V(For analog circuit)
I
Reference voltage 1.65+-0.1V(FEP)
Not use(PLL phase gain setting resistor terminal)
Not use(PLL frequency gain setting resistor terminal)
I
Reference voltage 2.2V+-0.1V(FEP)
Connect to resistor for VREFH reference current source
Ground(For analog circuit)
Connect to capacitor1 for PLL
Connect to capacitor2 for PLL
Output for jitter signal monitor
I
Not use
Pull-up to VHALF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
AS(AD2)
TE(AD1)
FE(AD0)
AVDD
FODRV(DA1)
TRDRV(DA0)
AVSS
ARF
NARF
O
O
-
IREF1
IREF2
DSLF1
DSLF2
AVDD
I/O
I/O
-
VHALF
PLPG
PLFG
-
-
VREFH
RVI
AVSS
PLFLT1
PLFLT2
JITOUT
I/O
O
O
I/O
RFDIF
CSLFL1
I/O
RVI
AVSS
PLFLT1
RFDIF
JITOUT
PLFLT2
CSLFL1
1-33
Page 34
XV-S60BK/XV-S62SL/XV-S65GD
2.Pin function (2/3)
Pin No. Symbol I/O Description
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VFOSHORT
AVDD
HPFIN
HPFOUT
AVSS
LPFIN
LPFOUT
CMPIN
TRCRS
VCOF
DBALO
JLINE
AVDD
LOUT
ROUT
AVSS
TGBAL
TBAL
FBAL
33VSS
33VDD
OFTR
SYSCLK
BDO
TSTSG
TRSDRV
SPDRV
FG
TILTP
TILT
TILTN
25VSS
25VDD
DTRD
IDGT/TEMUTE
LRCK/CPDET2
BLKCK/CPDET1
SBCK/PLLOK
IDHOLD
DACLRCK/JMPINH
DACDATA/LG
NTRON
DACCLK
IPFLAG
SUBC
NCLDCK/JUMP
MINTEST
TEST
33VSS
33VDD
CHCK40
DAT3
DAT2
DAT1
DAT0
O
O
O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
VFO short output
I
I
I
I
-
-
-
I
I
I
I
-
I
I
I
I
I
I
I
I
-
-
Apply 3.3V(For analog circuit)
Pull-up to VHALF
Connect to TP208
Ground(For analog circuit)
Pull-up to VHALF
Not use
Connect to TP210
Input signal for track cross formation
JFVCO control voltage
DSL balance adjust output
J-line setting output(FEP)
Apply 3.3V(For analog circuit)
Connect to TP203 (Analog audio left output)
Connect to TP204 (Analog audio right output)
Ground(For analog circuit)
Tangential balance adjust(FEP)
Tracking balance adjust(FEP)
Focus balance adjust(FEP)
Ground(For I/O)
Apply 3.3V(For I/O)
Off track signal
16.9344MHz system clock input(ODC)
Drop out(FEP)
Calibration signal(FEP)
Traverse drive(DRVIC)
Spindle drive output(DRVIC)
FG signal input (Spindle motor driver)
Connect to TP205
Connect to TP206
Connect to TP207
Ground(For internal core)
Apply 2.5V(For internal core)
Data read control signal(ODC)
Pull-down to Ground
LR channel data strobe(ODC)/
CD sub code synchronous signal(ODC)/
CD sub code data shift clock(ODC)/PLL pull-in OK signal input
Pull-down to Ground
1bit DAC-LR channel data strobe(ODC)/
CD 1bit DAC channel data(ODC)
L : Tracking ON(ODC)
1bit DAC channel data shift clock(ODC)
CIRC error flag(ODC)
CD sub code(ODC)
CD sub code data frame clock(ODC)/DVD JUMP signal(ODC)
Pull-down to Ground(For MINTEST)
Pull-down to Ground(For TEST)
Ground(For I/O)
Apply 3.3V(For I/O)
Clock for SRDATA(ODC)
SRDATA3(ODC)
SRDATA2(ODC)
SRDATA1(ODC)
SRDATA0(ODC)
1-34
Page 35
2.Pin function (3/3)
Pin No. Symbol I/O Description
-
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
33VSS
33VDD
TX
XRESET
ENS
ENC
CPUIRQ
CPUCLK
CPUDTIN
CPUDTOUT
MONA
MONB
MONC
NC
25VSS
25VDD
LDCUR(AD6)
TDOFS(AD5)
TG(AD4)
RFENV(AD3)
O
O
O
O
O
O
O
Ground(For I/O)
-
Apply 3.3V(For I/O)
Digital audio interface
I
Reset input (System control)
I
Servo DSC serial I/F chip select (System control)
I
CIRC serial I/F chip select (System control)
Interrupt request (System control)
I
Syscon serial I/F clock (System control)
I
Syscon serial I/F data input (System control)
Syscon serial I/F data output (System control)
Connect to TP226 (Monitor terminal A)
Connect to TP225 (Monitor terminal A)
Connect to TP224 (Monitor terminal A)
Connect to TP211
-
Ground(For internal core)
-
Apply 2.5V(For internal core)
I
I
I
Tangential phase difference(FEP)
I
RF envelope input(FEP)
XV-S60BK/XV-S62SL/XV-S65GD
1-35
Page 36
XV-S60BK/XV-S62SL/XV-S65GD
SST39VF160-7CEK (IC509) : 16M EEPROM
1. Pin layout
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
/WE
/RST
NC
NC
R/B
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2. Block diagram
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
/BYTE
Vss
D15
D7
D14
D6
D13
D5
D12
D4
VDD
D11
D3
D10
D2
D9
D1
D8
D0
/OE
Vss
/CE
A0
16,777,216Bit
X-Decoder
EEPROM
Cell Array
A19~A0
Address Buffer & Latches
/CE
/OE
/WE
3. Pin function
Symbol FunctionPin name
A19~A0
DQ15~DQ0
/CE
/OE
/WE
VDD
Vss
NC
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Y-Decoder
Control Logic
I/O Buffers & Data Latches
DQ15~DQ0
To provide memory addresses. During sector erase A19~A11 address
lines will select the sector. During block erase A19~A15 address lines
will select the block.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are
in tri-state when /OE or /CE is high.
To activate the device when /CE is low.
To gate the data output buffers.
To control the write operations.
To provide 3-volt supply ( 2.7V-3.6V ).
1-36
Page 37
UPD780232GC-039(IC2):System controller
1.Pin layout
60 41
61
40
XV-S60BK/XV-S62SL/XV-S65GD
80
1 20
2.Pin function
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26,27
28,29
30,31
32,33
34
35
36
37
38
39~58
59
60
61~64
65~67
68~80
POWERSW
STANDBYRED
PROGRN
AUDIOLED
INT/PROG
Symbol
VDD1
VSS1
X1
X2
IC(VPP)
RESET
SCK
RXD
TXD
AVCO
INTP
P.ON
RESET
AVCI
CS
REMO
AVSS
ANI3
ANI2
ANI1
ANI0
VSS0
AVDD
VDD0
PRORED
S24~S5
VDD2
VLOAD
S4~S1
13G~1G
21
I/O
-
I
O
I
I/O
I
O
I
O
I/O
O
O
I
I
I
I
I
-
-
-
-
-
O
-
O
O
-
-
-
O
O
O
-
-
O
-
O
Description
Power supply terminal (+)
Connect to ground
Main system clock oscillation terminal
Main system clock oscillation terminal
Internal connection (connect to VSS1)
System reset input
Serial clock input/output of serial interface
Serial data input of serial interface
Serial data output of serial interface
Power switch (S1) input terminal
AV Compulink output terminal
8 bit input/output port
Power ON signal output
CPU Reset output
AV Compulink input terminal
Chip select input
Remote controller signal input
Connect to ground for A/D converter
Operation switch (S2,S3) input terminal
Operation switch (S4~S7) input terminal
Connect to ground
Connect to ground
Connect to ground for port section
Standard voltage input for analog power supply of A/D converter
Power supply terminal (+) for port section
Standby LED control signal output
Non connect
Progressive LED control signal output (red)
Progressive LED control signal output (green)
Not use
Non connect
Interlace/progressive switch signal output
Muting control signal output
FL Segment control signal output
Power supply terminal (+) for driver section
Connected to pull down resistor for FL driver
FL Segment control signal output
Non connect
FL Grid control signal output
1-37
Page 38
XV-S60BK/XV-S62SL/XV-S65GD
NDV8601VWA(IC501):AV Decoder
1.Pin layout
240 181
1
180
60
61 120
2.Block diagram
digital audio
serial
peripherals
DVD data
121
audio DAC
Serial
port
controller
digital audio
Audio
output
processor
DVD
A/V
+
CSS
Audio
DSP
Demux
engine
MPEG
Video
decoder
SDRAM
controller
Video I/O port
Video
output
processor
RISC
uProcessor
+ cache
NTSC
PA L
SCART
encoder
XBUS
controller
Video
XBUS
3.Pin function (1/4)
Pin No.
1
2,3
4
5
6
7~9
10
11
12,13
14
15,16
17
18
19
20,21
22
23
24
25,26
27
28
29
Symbol
VDDio
MD10,11
VDD
MD12
VSSio
MD13~15
VDDio
DQM1
MA9,8
VSSio
MA7,6
VSS
MA5
VDDio
MA4,3
MCLK
VSSio
CKE
MA2,1
VDDio
MA0
MA10
I/O
Power supply terminal 3.3V
SDRAM Data bus terminal
I/O
Power supply terminal 1.8V
SDRAM Data bus terminal
I/O
Connect to ground
SDRAM Data bus terminal
I/O
Power supply terminal 3.3V
SDRAM Data byte enable
O
SDRAM Address bus terminal
O
Connect to ground
SDRAM Address bus terminal
O
Connect to ground
SDRAM Address bus terminal
O
Power supply terminal 3.3V
SDRAM Address bus terminal
O
SDRAM Clock output
O
Connect to ground
SDRAM Clock enable output
O
SDRAM Address bus terminal
O
Power supply terminal 3.3V
SDRAM Address bus terminal
O
SDRAM Address bus terminal
O
SDRAM
Description
1-38
Page 39
3.Pin function (NDV8601VWA 2/4)
XV-S60BK/XV-S62SL/XV-S65GD
Pin No.
30
31
32,33
34
35
36
37
38
39
40
41
42
43
44
45,46
47
48
49
50~52
53
54~56
57
58~61
62
63,64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Symbol
MA11
VSSio
MA12,13
VDD
CS0
VDDio
RAS
CAS
WE
VSSio
DQM0
DQM2
MD16
VDDio
MD17,18
VSS
MD19
VSSio
MD20~22
VDDio
MD23~25
VSSio
MD26~29
VDDio
MD30,31
DQM3
CS1
VSSD
SPDIF
VSSio
AIN
AOUT3
AOUT2
AOUT1
AOUT0
VDDio
PCMCLK
VDD
ACLK
LRCLK
SRST
RSTP
VSSio
RXD1
SSPIN1
VSS
SSPOUT1
SSPCLK1
SSPCLK0
VDD
SSPIN0
I/O
Non connect
Connect to ground
SDRAM Address bus, reserved for terminal compatibility with 64Mb SDRAM
O
Power supply terminal 1.8V
SDRAM Primary bank chip select
O
Power supply terminal 3.3V
SDRAM Command bit
O
SDRAM Command bit
O
SDRAM Command bit
O
Connect to ground
SDRAM Data byte enable
O
SDRAM Data byte enable
O
SDRAM Data bus terminal
I/O
Power supply terminal 3.3V
SDRAM Data bus terminal
I/O
Connect to ground
SDRAM Data bus terminal
I/O
Connect to ground
SDRAM Data bus terminal
I/O
Power supply terminal 3.3V
SDRAM Data bus terminal
I/O
Connect to ground
SDRAM Data bus terminal
I/O
Power supply terminal 3.3V
SDRAM Data bus terminal
I/O
SDRAM Data byte enable
O
SDRAM Extension bank chip select
O
Connect to ground
S/PDIF Digital audio output terminal
O
Connect to ground
Digital audio input for digital micro; can be used as GPIO
I
Serial audio output data to audio DAC for left and right channels for down-mix
O
Serial audio output data to audio DAC for surround left and right channels
O
Serial audio output data to audio DAC for center and LFE channels
O
Serial audio output data to audio DAC for left and right channels
O
Power supply terminal 3.3V
Audio DAC PCM sampling clock frequency, common clock for DACs and ADC
O
Power supply terminal 1.8V
Audio interface serial data clock, common clock for DACs and AD converter
O
Left / right channel clock, common clock for DACs and ADC
O
Active low RESET signal for peripheral reset
O
RESET_Power : from system, used to reset frequency synthesizer and rest
I
of chip
Connect to ground
UART1 Serial data input from external serial device, used for IR receiver
I
SSP1 Data in or 16X clock for USART function in UART1
I/O
Connect to ground
SSP1 Data out or UART1 data-terminal-ready signal
I/O
SSP1 Clock or UART1 clear-to -send signal
I/O
SSP0 Clock or request-to-send function in UART1
I/O
Power supply terminal 1.8V
SSP0 Data in or 16X clock for USART function in UART0
I/O
Description
1-39
Page 40
XV-S60BK/XV-S62SL/XV-S65GD
3.Pin function (NDV8601VWA 3/4)
Pin No.
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126~131
132
133,134
135
136~139
140
141~144
145
146
147
148~153
154
155
156
157,158
159
Symbol
VDDio
SSPOUT0
TXD0
RXD0
CTS0
RTS0
VSSio
CXI
CXO
OSCVSS
OSCVDD
MVCKVDD
SCEN
MVCKVSS
ACLKVSS
SCMD
ACLKVDD
VDDDAK
VSSDAC
Cr/R
IOM
C/Cb/B
VAA3
Y/G
VSSA
VREF
VAA
CVBS/C
RSET
COMP
VSS
VCLK
VSYNC
HSYNC
VDDio
VI07~02
VSSio
VI01,00
VDD
AD31~28
VDDio
AD27~24
PWE3
AD23
VSSio
AD22~17
VDDio
AD16
PWE2
AD15,14
VDD
I/O
Power supply terminal 3.3V
SSP0 Data out or UART0 data-terminal-ready signal
I/O
UART0 Serial data output to an external serial device
I/O
UART0 Serial data input from external serial device
I
UART0 Clear-to-send signal
I/O
UART0 Request-to-send signal
I/O
Connect to ground
Crystal input terminal for on-chip oscillator or system input clock
I
Crystal output terminal for on-chip oscillator
O
Connect to ground for oscillator
Power supply terminal for oscillator 1.8V
Power supply terminal for main and video clock PLL 3.3V
Scan chain test enable
I
Connect to ground for main and video clock PLL
Connect to ground for audio clock PLL
Scan chain test mode
I
Power supply terminal for audio clock PLL 3.3V
Power supply terminal for DAC digital 1.8V
Connect to ground for DAC digital
Video signal output (Cr output : composite/component Red output)
O
Cascaded DAC differential output used to dump current into external resistor
O
for power
Video signal output (Chrominance output for NTSC/PAL S-Video
O
Cb output for component Blue output)
Power supply terminal for DAC analog 3.3V
Video signal output (Luminance for S-Video and component Green output)
O
Connect to ground for DAC analog
Non connect
-
Video signal output (Composite video Chrominance output for S-Video)
O
Current setting resistor of output DACs
O
Compensation capacitor connection
O
Connect to ground
Non connect
Non connect
Non connect
Power supply terminal 3.3V
Non connect
Connect to ground
Non connect
Power supply terminal 1.8V
Multiplexed address / data bus terminal
I/O
Power supply terminal
Multiplexed address / data bus terminal
I/O
Byte write enable for FLASH,EEPROM,SRAM or peripherals terminal
I/O
Multiplexed address / data bus terminal
I/O
Connect to ground
Multiplexed address / data bus terminal
I/O
Power supply terminal 3.3V
Multiplexed address / data bus terminal
I/O
Byte write enable for FLASH,EEPROM,SRAM or peripherals terminal
I/O
Multiplexed address / data bus terminal
I/O
Power supply terminal 1.8V
-
Description
1-40
Page 41
3.Pin function (NDV8601VWA 4/4)
XV-S60BK/XV-S62SL/XV-S65GD
Pin No.
160
161
162
163~168
169
170
171
172~176
177
178~180
181
182
183
184~187
188
189
190
191
192
193
194,195
196
197~200
201
202,203
204
205
206~209
210
211
212
213
214
215
216
217
218
219~223
224
225,226
227
228
229
230
231,232
233
234~236
237
238~240
Symbol
SCLK
ACK
VSSio
AD13~8
VDDio
PWE1
VSS
AD7~3
VSSio
AD2~0
VDDio
PWE0
ALE
LA0~3
VSSio
RD
LHLDA
LHLD
VDD
PCS0
XI01,02
VDDio
XI03~06
VSS
XI07,08
VSSio
XI09
XID10~13
VDDio
XID14
VDD
DSYNC
DREQ
DCLK
DSTB
DVD0
VSSio
DVD1~5
VDDio
DVD6,7
MD0
VSSio
MD1
VSS
MD2,3
VDDio
MD4~6
VSSio
MD7~9
I/O
External bus clock used for programmable host peripherals
O
Programmable WAIT/ACK/RDY control
I/O
Connect to ground
Multiplexed address / data bus terminal
I/O
Power supply terminal 3.3V
Byte write enable for FLASH,EEPROM,SRAM or peripherals terminal
I/O
Connect to ground
Multiplexed address / data bus terminal
I/O
Connect to ground
Multiplexed address / data bus terminal
I/O
Power supply terminal 3.3V
Byte write enable for FLASH,EEPROM,SRAM or peripherals terminal
I/O
Address latch enable
I/O
Latched address 0~3
I/O
Connect to ground
Read terminal
I/O
Bus hold acknowledge in slave mode
O
Bus hold request from external master in slave mode
I
Power supply terminal 1.8V
Peripheral chip select 0, generally used for enabling the program store
O
ROM/FLASH
Programmable general purpose external input/output
I/O
Power supply terminal 3.3V
Programmable general purpose external input/output
I/O
Connect to ground
Programmable general purpose external input/output
I/O
Connect to ground
Programmable general purpose external input/output
I/O
Programmable general purpose external input/output
I/O
Power supply terminal 3.3V
Programmable general purpose external input/output
I/O
Power supply terminal 1.8V
DVD Parallel mode sector sync
I
DVD Parallel mode data request
O
Data sampling clock
I
Parallel mode data valid, serial mode left/right clock
I
DVD Drive parallel data port
I
Connect to ground
DVD Drive parallel data port
I
Power supply terminal 3.3V
DVD Drive parallel data port
I
SDRAM Data bus terminal
I/O
Connect to ground
SDRAM Data bus terminal
I/O
Connect to ground
SDRAM Data bus terminal
I/O
Power supply terminal 3.3V
SDRAM Data bus terminal
I/O
Connect to ground
SDRAM Data bus terminal
I/O
Description
1-41
Page 42
XV-S60BK/XV-S62SL/XV-S65GD
Glossary of term and abbreviations
3D
3-dimension
A/V
1)audio/video 2)audio/visual
ac
alternating current
ACLK
ADC
ALE
ANSI/SMPTE
AOP
AXCLK
baud
CCIR
CD-DA
CMOS
CPU
CSS
CTS
CVBS
DAC
DEMUX
DSP
DTS
DVD
EAV
EAV/SAV
EEPROM
GPIO
HDCD
HDTV
HSYNC
IOM
LCLK
LRCLK
LSB
audio serial-data (bit) clock
AD
multiplexed address / data bus
analog-to-digital converter
AIN
digital audio input
address latch enable
American National Standards Institute / Society of Motion Pictures and Television Engineers
Audio Output Processor
test-mode audio-PLL clock output
unit of signaling speed equal to one code element per second
Cb
blue color difference component ( in accordance with the CCIR 601 specifications)
Consultative Committee on International Radio
CD
compact disc
compact disc-digital audio
Complementary Metal Oxide Semiconductor
Central Processing Unit
Cr
red color difference component ( in accordance with the CCIR 601 specifications)
Content Scrambling System
Clear To Send
Composite Video Blank and Sync
Digital-to-Analog Converter
dc
direct current
DEMUX Engine
Digital Signal Processing
Digital Theater System
Digital Versatile Disc
End Active Video
End Active Video / Start Active Video
EEI
Enable Error Interrupt
Electrically Erasable Programmable Read-Only Memory
FS
FIFO Status
General Purpose Input/Output
High Definition Compatible Digital
High-Definition television
Horizontal sync
I/O
Input/Output
IEC
International Electrotechnical Commission
Current (I) Output Minus ( complementary shared current path to Video DAC current paths)
IR
infrared
ITU
International Telecommunications Union
LA
Latched Address Bus
oscillator clock ( derived from internal crystal oscillator )
Lfe
Low-frequency effect
Left/Right clock
Least Significant Bit
Mb
Megabit
MB
Megabyte
(for AV Decoder section)
1-42
Page 43
XV-S60BK/XV-S62SL/XV-S65GD
MCLK
MHz
MIPS
MmCPU
MP3
MPEG1 audio
MPEG2 audio
NOP
NTSC
NTSC-M
OSD
PAL
PCM
PCMCLK
PCS
PLL
PQFP
PWM
r/w
RAM
RGB
RISC
ROM
RXD
RW
SAV
SCART
SCLK
SDRAM
S/PDIF
S/PDIFCLK
SRAM
SSP
TXD
UART
USART
VGA
VIO
VREF
Vref
VSSA
VSYNC
XBUS
XIO
YCbCr
primary or master clock
Megahertz
Million Instructions Per Second
Mediamatics CPU (synonym for internal RISC CPU)
Moving Picture Experts Group Layer-3 Audio (audio file format / extension)
A digital audio format mainly used in video CDs. It is based on the moving picture expert group
(MPEG1) format, a data compression technology.
A digital audio format mainly used in Europe and Australia. It provides high quality, multi-channel
audio of up to eight channels in the same was as Dolby Digital and DTS. It is based on the
MPEG2 format, a data compression technology more improved than MPEG1
No Operation
1)National Television System Committee 2)Worldwide video standard in North America and Japan
Version of NTSC used in certain parts of the world (Brazil)
On-screen display
Phase alteration by line
Pulse Code Modulation
PCM audio-data over-sampling clock
1)Picture Control and Size 2)Perpheral Chip Select
Phase Lock Loop
Plastic Quad Flat Pack (Package)
Pulse Width Modulator
Read/Write access
Random Access Memory
Red-Green-Blue (color model)
Reduced Instruction Set Computer
Read-Only Memory
Receive signal
Readable / Write able
Start Active Video
Syndicat des Constructeurs d'Appareils Radiorecepteurs et Televiseurs ( connector used in
Europe to connect many kinds of audiovisual equipment)
Secondary or slave clock
Synchronous Dynamic Random Access Memory
Sony / Philips Digital Interface
clock associated with the S/PDIF output
Static Random Access Memory
Synchronous Serial Port
transmit signal
Universal Asynchronous Receiver-transmitter
Universal Synchronous / Asynchronous Receiver / Transmitter
Video Graphics Array
Video Input / Output
Voltage REFerence
Vertical reference
quiet analog ground
Vertical sync
External peripheral bus
External Input / Output
Y
Luminance component (in accordance with the CCIR 601 specifications)
Luminance component, blue color difference component, red color difference component
(in accordance with the CCIR 601 specifications)
1-43
Page 44
XV-S60BK
XV-S62SL/XV-S65GD
VICTOR COMPANY OF JAPAN, LIMITED
PERSONAL & MOBILE NETWORK BUSINESS UNIT
1644, Shimotsuruma, Yamato, Kanagawa 242-8514, Japan
No.A0012
Printed in Japan
200106(O)
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