JVC TH-A5UW Schematic

SERVICE MANUAL

DVD DIGITAL CINEMA SYSTEM

Area suffix

TH-A5

A ------------------ Australia US -------------- Singapore UB ------------- Hong Kong UW -- Brazil,Mexico,Peru UY --------------- Argentina UJ ------------- U.S.Military UG ------------------ Turkey, South Africa,Egypt

TH-A5

STANDBY/ON

AUDIO

VCR

CONTROL

ON

VCR

TV

OFF

TV CHANNEL

MENU

TOP MENU

AUDIO/

SUBTITLE

TV VOLUME

FM MODE

STEP

TV/VIDEO

DISPLAY

RETURN

TUNER PRESET

DOWN UP

REW FF

VCR CHANNEL

TUNING

B.SEARCH F.SEARCH

ENTER

VOLUME

DVD FM/AM AUX MUTING

RM-STHA5U

DVD CINEMA SYSTEM

SP-XSA5 2

COMPACT

DIGITAL VIDEO

STANDBY

STANDBY/ON

AUDIO/FM MODE

DSP

Contents

Safety precautions Important for laser products Preventing static electricity Disassembly method

VOLUME SOURCE

SP-XCA5 SP-XSA5 2

DIGITAL

DVD DIGITAL CINEMA SYSTEM TH-A5

SURROUND

DIGITAL

XV-THA5 SP-WA5

1-2 1-3 1-4

Wiring connection Adjustment method Description of major ICs

1-5

1-12 1-13 1-15~33

No.21062

Jan. 2002

TH-A5

1. This design of this product contains special hardware and many circuits and components specially for safety purposes. For continued protection, no changes should be made to the original design unless authorized in writing by the manufacturer. Replacement parts must be identical to those used in the original circuits. Services should be performed by qualified personnel only.

2. Alterations of the design or circuitry of the product should not be made. Any design alterations of the product should not be made. Any design alterations or additions will void the manufacturer`s warranty and will further relieve the manufacture of responsibility for personal injury or property damage resulting therefrom.

3. Many electrical and mechanical parts in the products have special safety-related characteristics. These

characteristics are often not evident from visual inspection nor can the protection afforded by them necessarily be obtained by using replacement components rated for higher voltage, wattage, etc. Replacement parts which have these special safety characteristics are identified in the Parts List of Service Manual. Electrical components having such features are identified by shading on the schematics and by ( ) on the Parts List in the Service Manual. The use of a substitute replacement which does not have the same safety characteristics as the recommended replacement parts shown in the Parts List of Service Manual may create shock, fire, or other hazards.

4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the like to be separated from live parts, high temperature parts, moving parts and/or sharp edges for the prevention of electric shock and fire hazard. When service is required, the original lead routing and dress should be observed, and it should be confirmed that they have been returned to normal, after re-assembling.

5. Leakage currnet check (Electrical shock hazard testing) After re-assembling the product, always perform an isolation check on the exposed metal parts of the product (antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control shafts, etc.) to be sure the product is safe to operate without danger of electrical shock. Do not use a line isolation transformer during this check.

Plug the AC line cord directly into the AC outlet. Using a "Leakage Current Tester", measure the leakage current from each exposed metal parts of the cabinet, particularly any exposed metal part having a return path to the chassis, to a known good earth ground. Any leakage current must not exceed 0.5mA AC (r.m.s.).

Alternate check method Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms per volt or more sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by a 0.15 F AC-type capacitor between an exposed metal part and a known good earth ground. Measure the AC voltage across the resistor with the AC voltmeter. Move the resistor connection to each exposed metal part, particularly any exposed metal part having a return path to the chassis, and meausre the AC voltage across the resistor. Now, reverse the plug in the AC outlet and repeat each measurement. Voltage measured any must not exceed 0.75 V AC (r.m.s.). This corresponds to 0.5 mA AC (r.m.s.).

0.15 F AC TYPE

1500 10W

Good earth ground

AC VOLTMETER (Having 1000 ohms/volts, or more sensitivity)

Place this probe on each exposed metal part.

!

1. This equipment has been designed and manufactured to meet international safety standards.

2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.

3. Repairs m ust be made in accordance with the relevant safety standards .

4. It is essential that safety critical components are replaced by approved parts.

5. If mains voltage selector is provided, check setting for local voltage.

Burrs formed during molding may be left over on some parts of the chassis. Therefore, pay attention to such burrs in the case of preforming repair of this system.

In regard with component parts appearing on the silk-screen pr inted side (parts side) of the PWB diagrams, the parts that are printed over with black such as the resistor ( ), diode ( ) and ICP ( ) or identified by the " " mark nearby are critical for safety.

(This regulation does not correspond to J and C version.)

1-2

Important for laser products

TH-A5

1.CLASS 1 LASER PRODUCT

2.DANGER : Invisible laser radiation when open and inter

lock failed or defeated. Avoid direct exposure to beam.

3.CAUTION : There are no serviceable parts inside the Laser Unit. Do not disassemble the Laser Unit. Replace the complete Laser Unit if it malfunctions.

4.CAUTION : The compact disc player uses invisible laserradiation and is equipped with safety switches whichprevent emission of radiation when the drawer is open and the safety interlocks have failed or are de feated. It is dangerous to defeat the safety switches.

REPRODUCTION AND POSITION OF LABELS

5.CAUTION : If safety switches malfunction, the laser is able

to function.

6.CAUTION : Use of controls, adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

!

Please use enough caution not to see the beam directly or touch it in case of an adjustment or operation check.

CLASS 1 LASER PRODUCT

1-3

TH-A5

Preventing static electricity

1.Grounding to prevent damage by static electricity

Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged, can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs.

2.About the earth processing for the destruction prevention by static electricity

Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as CD players. Be careful to use proper grounding in the area where repairs are being performed.

2-1 Ground the workbench

Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over it before placing the traverse unit (optical pickup) on it.

2-2 Ground yourself

Use an anti-static wrist strap to release any static electricity built up in your body.

(caption) Anti-static wrist strap

Conductive material (conductive sheet) or iron plate

3. Handling the optical pickup

1. In order to maintain quality during transport and before installation, both sides of the laser diode on the replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition. (Refer to the text.)

2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power source can easily destroy the laser diode.

4.Handling the traverse unit (optical pickup)

1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.

2. Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the traverse unit. Be careful not to take too long a time when attaching it to the connector.

3. Handle the flexible cable carefully as it may break when subjected to strong force.

4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it.

Attention when traverse unit is decomposed

*Please refer to "Disassembly method" in the text for pick-up and how to detach the substrate.

Solder is put up before the card

1. wire is removed from connector on the pick up board as shown in Figure. (When the wire is removed without putting up solder, the CD pick-up assembly might destroy.) Please remove solder after

2. connecting the card wire with when you install picking up in the substrate.

DVD mechanism assembly (bottom side)

DVD loading mechanism

Pick up board

Card wire

Short land

(These two points are soldered respectively, and are made to short-circuit)

Connector

1-4

DVD loader board

TH-A5

Disassembly method

Removing the top cover (See Fig.1)

1.

Remove the four screws A attaching the top cover on the both sides of the body.

2.

Remove the two screws B on the back of the body.

3.

Remove the top cover from behind in the direction of the arrow while pulling both sides outward.

Removing the front panel assembly

(See Fig.2A, 2B and 3)

Prior to performing the following procedure, remove the top cover.

1.

Remove the one screw a and remove the earth wier.

2.

Remove the three screws C attaching the front panel assembly on the bottom of the body.

3.

Remove the two screws D attaching the front panel assembly on the both sides of the body.

4.

Remove the claw1, claw2 and claw3, and detach the front panel assembly toward the front.

5.

Disconnect the card wire from the connector DW20 on the DSP board.

Top cover

Claw1

(bottom side)

Claw2 (both side)

B

A

2

Fig.1

Front panel assembly

CC

Fig.2A

Front panel

assembly

Claw3

Removing the power cord (See Fig.4)

Prior to performing the following procedure, remove the top cover.

1.

Disconnect the power cord from the connector CW1 on the main board and pull up the cord stopper upward.

Notes : The power cord is exchangeable.

Power cord

CW1

Tie band

D

(both side)

a

(fixing the earth wire)

Fig.2B

DSP board

DW20

Rear panel

Fig.4

Power cord

stopper

Front panel assembly

(Inner side)

Display board

Fig.3

1-5

TH-A5

Removing the DVD mechanism assembly (See Fig.5 and 6)

Prior to performing the following procedure, remove the top cover.

1.

Disconnect the card wire from the connector J14 and J21 on the DVD MPEG board.

2.

Remove the two screws E attaching the DVD mechanism assembly and pull up with drawing out.

3.

Disconnect the harness from the connector J2 on the DVD loader board.

Removing the rear panel (See Fig.7 and 8)

Prior to performing the following procedure, remove the top cover and power cord.

1.

Disconnect the harness from the connector NW11 on the DSP board.

2.

Remove the two screws F, four screws G, five screws I attaching the each boards to the rear panel.

Rear panel

DVD mechanism assembly

DVD MPEG board

J14

E

J21

Fig.5

DVD mechanism assembly

3.

Remove the three screws J attaching the rear panel on the back of the body.

Removing the tuner pack (See Fig.7 and 8)

Prior to performing the following procedure, remove the top cover.

1.

Disconnect the card wire from the connector CON01 on the tuner pack.

2.

Remove the two screws F attaching the tuner pack to the rear panel.

Removing the jack board (See Fig.7 and 8)

Prior to performing the following procedure, remove the top cover.

1.

Disconnect the card wire from the connector VW2 on the jack board.

2.

Remove the four screws G attaching the jack board to the rear panel.

3.

Disconnect the connector VW1 on the jack board and pull up the jack board.

DVD loader board

J2

Fig.6

Rear panel

Fan motor

JJJ

DSP board

H

I

Fig.7

G

F

CON01

Removing the fan motor (See Fig.7 and 8)

Prior to performing the following procedures, remove the top cover .

1.

Disconnect the harness from the connector NW11 on the DSP board .

2.

Removing the two screws H attaching the fan motor on the rear panel.

1-6

Rear panel

NW11 (on the DSP board)

VW1

Fig.8

VW2

Tuner pack

Jack board

TH-A5

Removing the DSP board (See Fig.9)

Prior to performing the following procedure, remove the top cover, the front panel assembly and jack board.

1.

Untied the harness band and disconnect the harness from the connector CW2 on the main board.

2.

Disconnect the harness from the connector NW11 on the DSP board.

3.

Disconnect the card wire from the connector VW12 on the DSP board.

4.

Pull up the DSP board from the front side upwards disconnecting the connector DW10, DW13, DW14 and DW15.

Removing the main board (See Fig.10)

Prior to performing the following procedure, remove the top cover, front panel assembly, DVD mechanism assembly, jack board and DSP board.

1.

Disconnect the card wire from the connector CW4 and CW8 on the main board.

2.

Disconnect the harness from the connector CW3 on the main board.

DSP board

(Front panel side)

Main board

CW8

K2

VW12

DW14DW15

Harness band

Fig.9

K1

Main board

CW2

NW11

(Rear panel side)

DW10DW13

Heat sink

(to which

power

transistor

is attached)

K1

3.

Remove the five screws I attaching the speaker terminals and jack to the rear panel (see fig.7).

4.

Remove the six screws K1 (short) and one screw K2 (long) attaching the main board.

5.

When the rear panel is not removed, pull up the main board from front side.

Removing the power transistor & power IC (See Fig.10 and 11)

Prior to performing the following procedure, remove the top cover, front panel assembly, DVD mechanism assembly, jack board, DSP board and main board.

1.

After removing the solder part soldered to the main board, remove each screw and remove the heat sink from Power transistor.

2.

After removing the solder part soldered to the main board, remove each screw and remove the heat sink from Power IC.

CW4

Fig.10

(Each power transistor is fixed)

Solder part

Solder part Solder part

Heat sink (to which power IC is attached)

Fig.11

CW3

Power ICs

Main board

(Reverse side )

Solder part (Power IC is fixed)

1-7

TH-A5

Removing the DVD power board (See Fig.12)

Prior to performing the following procedure, remove the top cover, front panel assembly and DSP board.

1.

Disconnect the harness and card wire from the connector PW1, PW2 and PW5 on the DVD power board.

2.

Remove the one screw L1 (short) and two screws L2 (long) attaching the DVD power board.

L1

PW5 PW2

DVD

power

board

Removing the power transformer (See Fig.12)

Prior to performing the following procedure, remove the top cover.

1.

Cut off the tie band fixing the harness, if needed.

2.

Disconnect the harness from the connector CW2 on the main board (see fig.9) and PW1, PW2 on the DVD power board.

3.

Remove the four screws M attaching the power transformer.

PW1

Tie band

L2

Power transformer

M

Fig.12

Removing the display board & switch board (See Fig.1 and 2)

Prior to performing the following procedure, remove the top cover and the front panel assembly.

1.

Disconnect the card wire from the connector FW1 on the display board.

2.

Remove the five screws A attaching the display board on the inner of the front panel assembly.

3.

Remove the four screws B attaching the switch board on the inner of the front panel assembly.

4.

Disconnect the harness from connector FW2 on the display board, if needed.

Removing the front window (See Fig.2 and 3)

Prior to performing the following procedure, remove the top cover, front panel assembly, display board and switch board.

FW1

Display board

A

Switch button

Front panel assembly

Switch board

FW2

Fig.1

(inner side)

B

CCC

Claw

Fig.2

Front panel assembly (front side)

Remove the switch buttons, if needed.

1. Remove the three screws C attaching the front

2. window on the front panel.

Remove the eight claws fixing the front window on

3. the front panel.

1-8

Front window

Fig.3

TH-A5

Removing the DVD loader board (See Fig.1 to 3)

Prior to performing the following procedure, remove the top cover and DVD mechanism assembly.

1.

Disconnect the card wire from the connector J6 on the DVD MPEG board.

2.

Disconnect the harness from the connector on the motor board.

3.

Disconnect the harness from the connector J5 on the DVD loader board.

4.

Remove the four screws A attaching the DVD loader board to DVD mechanism assembly.

CAUTION!! (see fig.3) Before removing the card wire which

connects the pickup board and DVD loader board, solder the two soldering parts and make it short-circuit. Moreover, while having removed the card wire, don't remove these solder.

DVD MPEG board

DVD loader board

A

U9

J5

DVD mechanism assembly

(top side)

J6

Fig.1

DVD mechanism assembly

(bottom side)

Motor board

Connector

Fig.2

5.

Disconnect the card wire from the connector U9 on the DVD loader board.

ONE POINT

How to eject the DVD tray manually (see fig.2)

The white lever of the mark is moved in the direction of the arrow. Then, the tray will be opened. Moreover, the tray is separable from a DVD mechanism assembly by removing two screws of the mark (see fig.1) and drawing out the tray.

Removing the DVD loading mechanism (See Fig.4)

Prior to performing the following procedure, remove the top cover, DVD mechanism assembly and DVD loader board.

1.

Remove the two screws B and remove the bracket.

2.

Remove the one screw C fixing the DVD loading mechanism.

Pick up

board

Lever

Soldering parts

X

Motor board

Fig.3

DVD mechanism assembly

B

Bracket

DVD loading

mechanism

(bottom side)

DVD loading

mechanism

3.

Move the lever in the direction of the arrow X.

4.

Remove the DVD loading mechanism from the DVD mechanism assembly by moving it in the direction of the arrow Y.

Y

C

Fig.4

1-9

TH-A5

m

)

Removing the DVD traverse mechanism

(See Fig.5)

Prior to performing the following procedure, remove the top cover, DVD mechanism assembly, DVD loader board and DVD loading mechanism.

1.

Remove the four screws D attaching the DVD traverse mechanism to DVD loading mechanism.

Removing the holder & DVD MPEG board (See Fig.6 and 7)

Prior to performing the following procedure, remove the top cover, DVD mechanism assembly and DVD loader board.

1.

Remove the two claws1, and remove the holder from the DVD mechanism assembly as it is pushed down.

DVD traverse

mechanism

Claw1

D

Holder

DVD loading mechanis

(top side

D

Fig.5

Note: When removing only the DVD MPEG board, it is not necessary to remove this holder.

2.

Remove the four claws2 and remove the DVD MPEG board from the holder.

ONE POINT

When inserting DVD MPEG board in holder. (see fig.8)

Holder

DVD mechanism assembly

Fig.6

DVD MPEG board

Fig.7

DVD MPEG board

(bottom side)

Claw2

1-10

Insert in after uniting with a lower claws, when inserting DVD MPEG board in holder.

Fig.8

<Speaker section> [SP-XSA5 / Satellite speaker]

It is exchange in a unit.

[SP-XCA5 / Center speaker]

It is exchange in a unit.

[SP-WA5 / Woofer]

Removing the front panel (See Fig.1 and 2)

1.

Remove the six bosses and remove the front panel.

TH-A5

Front panel

The tool with

a flat tip

Notes: It will be good to use the tool with a flat tip, since it is hard to remove. Please take care not to damage the cabinet at this time.

2.

The packing separates. It removes if needed.

Removing the speaker unit (See Fig.3 to 5)

1.

Remove the four bosses and remove the net assembly.

Notes: It will be good to use the tool with a flat tip, since it is hard to remove. Please take care not to damage the cabinet at this time.

2.

Remove the eight screws A attaching the speaker unit to cabinet.

3.

Disconnect the code from the two terminals of the speaker unit.

Packing

Fig.1

Fig.2

Net assembly

Front panel (inner side)

Boss

Terminals

red

Speaker unit (reverse side)

Fig.5

Fig.3

Code

Speaker unit

black

A

Cabinet

Fig.4

1-11

TH-A5

Wiring connection

J6

J14

2

0

J21

3809-001273

DVD MPEG

BOARD

3809-001295

9

AH39-00368A

0

J3

J4

0

9

3809-001294

DVD LOADER BOARD

U9

J5

J2

0

9

Color codes are shown below. 1 Brown 2 Red 3 Orange 4 Yellow 5 Green

3809-001274

3809-001224

CON01

VW2

VW1

6 Blue 7 Violet 8Gray 9 White 0 Black

TUNER PACK

JACK BOARD (V-OUT)

0

9

SWITCH BOARD

FW3

AH39-00176A

0

9

FW2

DISPLAY BOARD

3809-001296

6

1

AH39-50001K

0

9

DW20

PW1

PW3

BOARD

3

DW15

0

DVD

POWER

4

9

5

PW4

0

6

PW5

PW2

1

VW11

9

2

AH39-00104A

AH39-00291A

DSP1 BOARD

9

4

2

8

0

3

DW14

DW32

0

2

DW12

DW23

DW13

DSP2 BOARD

3809-001283

9 2 4

DW10

DW31

8

3

0

NW11

DW11

CW4

0

2

CW7

RE3

RE4

CW6

CW8

0

2

CW1

CW2

1 C

FU1

FU2

FU4

FU3

PT1

CW5

1-12

FW1

0

POWER TRANCE

6

1

2

6

3

5

1

4

0

9

2

0

CW3

MAIN BOARD

Adjustment method

1. Tuner

TH-A5

*Adjustment Location of Tuner PCB

ITEM

Received FREQ.

Adjustment point

Output 1~7.0V

AM(MW) OSC Adjustment

: 522~1629KHz (9k step)

A

US/UB/

UW/UJ

: 531~1602KHz (9k step) 530~1600KHz (10k step)

MAIN PCB

MO

VT GND

AM(MW) RF Adjustment

603 KHz

MA

Maximum Output(Fig1-1)

TESTER

Fig 1-1 OSC Voltage

1-13

TH-A5

FM THD Adjustment

SSG FREQ. Adjustment

point (FD)

Output Minimum Distortion (0.4% below)

(Figure 1-2)

FM Search Level Adjustment

SSG FREQ.

FM DETECTOR COIL

60 dB

98 MHz

Output

Output GND

GND

FM S.S.G

FM Antenna Terminal

Te

T

Speaker Terminal

Te

T

SET

Input

output

Distortion Meter

Figure1-2 IF CENTER and THD Adjustment

28 dB

FM Antenna

Oscilloscope

Input

Adjustment point

(SVR3)

Output

BEACON SENSITIVITY SEMI-VR(20K )

28 dB(

dB)

Adjust SVR1 so that “TUNED” of FL T is lighted (Figure 1-3)

*Adjust FM S.S.G level to 28dB

AM(MW) I.F Adjustment

SSG FREQ. Frequency

450 kHz 522 kHz

Adjustment point

AA

Maximum output (Figure 1-4)

SET

GND

FM S.S.G

GND

FM IN

Figure1-3 FM Auto Search Level Adjustment

60cm

OUTPUT

AM SSG 450KHZ

INPUT

AM ANT IN

Speaker Terminal

OUTPUT

20 k

AM IF

VTVM Oscilloscope

Figure1-4 AM I.F Adjustment

Notes: This set is a non-adjusted set fundamentally. It is adjusted when the tuner pack is exchanged.

1-14

Description of major ICs

BA5983FM (U6) : 4CH driver

1.Block diagram

TH-A5

27

28

Vcc

1

2

25

26

10k

3

20k

10k

4

24

5

23 22

10k

6

20k

10k

7

2.Pin function

Pin No. Pin No.

Symbol Symbol

1

BLAS IN

2

OPIN1(+)

3

OPIN1(-)

4

OPOUT1

5

OPIN2(+)

6

OPIN2(-)

7

OPOUT2

8

9 10 11 12 13 14

GND

STBY1

PowVcc1

VO2(-)

VO2(+)

VO1(-)

VO1(+)

I/O I/O

Input for Bias-amplifier

I

Non inverting input for CH1 OP-AMP

I

Inverting input for CH1 OP-AMP

I

Output for CH1 OP-AMP

O

Non inverting input for CH2 OP-AMP

I

Inverting input for CH2 OP-AMP

I

Output for CH2 OP-AMP

O

Substrate ground

Input for CH1/2/3 stand by control

I

Vcc for CH1/2 power block

Inverted output of CH2

O

Non inverted output of CH2

O

Inverted output of CH1

O

Non inverted output of CH1

O

Function

15 16 17 18 19 20 21 22 23 24 25 26 27 28

21

20

STAND BY CH4

STAND BY CH1/2/3

89

VO4(+)

VO4(-)

VO3(+)

VO3(-)

PowVcc2

STBY2

GND OPOUT3 OPIN3(-)

OPIN3(+)

OPOUT4 OPIN4(-)

OPIN4(+)

PreVcc

17 16

18

19

Vcc

10

10k

11

Level Shift

10k

Level Shift

10k

12

13

Function

O

Non inverted output of CH4

O

Inverted output of CH4

O

Non inverted output of CH3

O

Inverted output of CH3

-

Vcc for CH3/4 power block

I

Input for Ch4 stand by control

-

Substrate ground

O

Output for CH3 OP-AMP

I

Inverting input for CH3 OP-AMP

I

Non inverting input for CH3 OP-AMP

O

Output for CH4 OP-AMP

I

Inverting input for CH4 OP-AMP

I

Non inverting input for CH4 OP-AMP

-

Vcc for pre block

15

10k

14

74VHC574 (DIC16, DIC17) : Flip flop

OE

D0 D1 D2 D3 D4 D5 D6 D7

GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

Vcc O0 O1 O2 O3 O4 O5 O6 O7 CP

Symbol

D0-D7

CP OE

O0-O7

Function

Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs

3. Truth table2. Pin function1. Pin layout

Inputs Outputs

Dn

CP

H

L

X

H:HIGH Voltage Level L:LOW Voltage Level X:Immaterial Z:High Impedance :HIGH to LOW transition

X

OE

L L

H

On

H

L

Z

1-15

TH-A5

ZiVA-5 (U8) : DVD controller

1. Pin layout

DA-IEC958

DA-DATA3

DA-DATA2

VSS

156

155

154

153

DAI-DATA

DAI-BCK/SYSCLKBP

DAI-LRCK/IEC958BP

2

C_CL

I I

2

C_DA RTS1 RXD1 TXD1 CTS1

VSS

VDD_3.3 SD-DATA7 SD-DATA6 SD-DATA5 SD-DATA4

VSS

VDDC SD-DATA3 SD-DATA2 SD-DATA1 SD-DATA0

SD-REQ

SD-EN

VSS

VDD_3.3

SD-ERROR

SD-CLK

VSYNC/HIRQ1

RTS2/SPI_CLK RXD2/SPI_MISO TXD2/SPI_MOSI

CTS2/SPI_CS

VDD_5

HCS4 HCS3 HCS2 HCS1 HCS0

VSS

VDD_3.3

TRST

TDO TMS

TCK

RESET

ALE VSS

VDDC

HAD3 HAD2

VSS

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199

TDI

200 201 202 203 204 205 206 207 208

152

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051

VDD_3.3

DA-DATA1

DA-DATA0

151

150

DA-BCK

DA-LRCK

149

148

DA-XCK

VSS

147

146

VDDC

145

A_VSS1

A_VDD1

144

143

A_VDD2

A_VSS2

142

141

XVDD

140

XTAL/VCLK216BP

XTAL

XVSS

VSS_RREF

VDAC_RREF

VDD_RREF

139

138

137

136

135

134

VDAC_DVDD

VDAC_DVSS

VDAC_0

VDAC_VDD0

133

132

131

130

VDAC_0B

VDAC_1

VDAC_VDD1

129

128

127

VDAC_1B

VDAC_2

VDAC_VDD2

126

125

124

VDAC_2B

VDAC_3

VDAC_VDD3

123

122

121

VDAC_3B

VDAC_4

VDAC_VDD4

120

119

118

VDAC_4B

HSYNC/IRQ2

VDATA0

117

116

115

VDATA1

VDATA2

114

113

VSS

VDD_3.3

112

111

VDATA3

VDATA4

110

109

VDATA5

VDATA6

VDATA7

108

107

106

VCLK

105

104 103 102 101 100

52

VDD_3.3 VSS MDATA31 MDATA30 MDATA29 MDATA28

99

VDD_3.3

98

MDQM3

97

VSS

96

MDATA27

95

MDATA26

94

MDATA25

93

MDATA24

92

MDATA23

91

MDATA22

90

MDATA21

89

MDATA20

88

VDD_3.3

87

MDQM2

86

VSS

85

MDATA19

84

MDATA18

83

MDATA17

82

MDATA16

81

VDDC

80

VSS

79

MDATA15

78

MDATA14

77

MDATA13

76

MDATA12

75

VDD_3.3

74

MDQM1

73

VSS

72

MDATA11

71

MDATA10

70

MDATA9

69

MDATA8

68

MDATA7

67

MDATA6

66

MDATA5

65

MDATA4

64

VDD_3.3

63

MDQM0

62

VSS

61

MDATA3

60

MDATA2

59

MDATA1

58

MDATA0

57

MCLK

56

VDD_3.3

55

VSS

54

MWE

53

BA1

HA1

VDD_3.3

HAD15

HAD14

HAD13

HAD12

HAD11

HAD10

HAD9

HAD8

HAD7

VDD_3.3

VSS

HAD6

HAD5

HAD4

HAD3

HAD2

HAD1

VDD_3.3

VSS

HAD0

HDTACK/WAIT

HIRQ0

UDS/UWE

R/W

IRRX1

LDS/LWE

VSS

VDDC

VSS

VDD_3.3

MADDR9

MADDR8

MADDR7

MADDR6

MADDR5

MADDR4

MADDR3

MADDR2

MADDR1

MADDR0

VSS

VDD_3.3

MADDR10

MADDR11

BA0

MCS0

MCS1

MRAS

MCAS

2. Pin function (1/4)

1

Name

RESET

Pin No.

202

Description

Type

Active Low Reset. Assert for at least 5-milliseconds in the presence of

I

clock to reset the entire chip.

VCLK XOUT

105 138

Video clock that outputs 27 MHz.

I/O

Crystal output. When the internal DCXO is used, a 13.5 MHz crystal

O

should be con-nected between this pin and the XIN pin.

XIN/bypass clk_216

139

Crystal input. When the internal DCXO is used, a 13.5 MHz crystal should

I

be con-nected between this pin and the XOUT pin. When an external oscillator or VCXO is used, its output should be connected to this pin.

System Services

When configured for an external bypass clock, a 216 MHz clock should be connected to this pin. The frequency of an external VCXO can be either 27 or 13.5 MHz.

1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.

1-16

2. Pin function (2/4)

Name

VNW VDDP VDD25 XVDD VDD VDD_VDAC[4:0] VDAC_DVDD A_VDD[2:1] VDAC_REFVDD GNDP GND

Power and GroundHost Interface

GND25 VDAC_DVSS AVSS[2:1] VDAC_REFVSS XVSS HCS[4:2]/GPIO[41:43]

HCS[1:0]

HA[3:1]

HA[15:0]

HDTACK/WAIT HIRQ0

HUDS/UWE

HLDS/LWE

HREAD ALE MCS[1:0] MCAS MRAS MDQM[3:0]

MA[11:0] MD[31:0]

MWE

SDRAM Interface

MCLK BA[1:0] HSYNC/HIRQ2/ GPIO1[9]

VCLK

VDATA[7:0]/GPIO[1:7]

VSYNC/HIRQ1/ GPIO36

Digital Video Input/Output

1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.

12, 20, 111, 152, 167, 181, 196

32, 44, 55, 63, 74, 87, 98, 104

13, 21, 112, 153, 166, 180, 195, 208

31, 43, 54, 61, 72, 85, 96, 103

Pin No.

189

140

30, 80, 145, 173, 205

118, 121, 124, 127, 130

133

142, 143

134

29, 79, 146, 172, 204

132

141, 144

136 137

190-192

193, 192

206, 207, 2

3-11, 14-19, 22

23 24

25

26

27

203

50, 49

52 51

97, 86, 73, 62

46, 45, 33-42

102-99, 95-88, 84-81,

78-75, 71-64, 60-57

53

56

47, 48

116

105

106-110, 113-115

184

Type

Power Power Power Power Power Power

Power Ground Ground Ground Ground Ground Ground Ground

O

I

I/O

I/OD

I/O

I/O I/O

O O O O

O

I/O

O

O O

I/O

1

Description

5-V supply voltage for 5V-tolerant I/O signals.

3.3-V supply voltage for I/O signals

3.3-V supply voltage for SDRAM I/O signals

3.3V Crystal interface power

1.8-V supply voltage for core logic Analog Video DAC Power

3.3V Digital supply for 5 DACs

3.3-V Analog PLL Power

3.3V Analog Video Reference Voltage Ground for I/O signals Ground for core logic Ground for SDRAM I/O signals Digital VSS for DACs Analog PLL Ground Video Analog Ground Crystal interface ground Host chip select. Host asserts HCS to select the controller for a read or write operation. The falling edge of this signal triggers the read or write operation. General Purpose I/Os 41, 42, and 43, respectively. Host chip select. Host asserts HCS to select the contr ol le r fo r a re ad or write operation. The falling edge of this signal triggers the read or write operation. Host (muxed address) address bus. 3-bit address bus selects one of eight host inter-face registers. These signals are not muxed in ATAPI master mode. HA[15:0] is the 16-bit (muxed address and data) bi-directional host data bus through which the host writes data to the decoder Code FIFO. MSB of the 32-bit word is writ-ten first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via HA[7:0]. These signals are not muxed for ATAPI master mode. Host Data Transfer Acknowledge. Host interrupt. Open drain signal, must be pulled-up via 4.7k to 3.3 volts. Driven high for 10 ns before tristate. Host Upper Data Strobe. Host high byte data, HA[15:8], is valid when this pin is active. Host Lower Data Strobe. Host low byte data, HA[7:0], is valid when this pin is active. Read/write strobe Address latch enable Memory chip select. Active LOW SDRAM Column Address Strobe. Active LOW SDRAM Row Address Strobe. These pins are the bytes masks corresponding to MD[7:0], [15:8], [23:16] and [31:24]. They allow for byte reads/writes to SDRAM. SDRAM Address SDRAM Data

SDRAM Write Enable. Specifies transaction to SDRAM: read (=1) or write (=0) SDRAM Clock SDRAM bank select Horizontal sync. The decoder begins outputting pixel data for a new horizontal line after the falling (active) edge of HSYNC. Host Interrupt Request 2 General Purpose I/O 9 Video clock. Clocks out data on input. VDATA[7:0]. Clock is typically 27 MHz. Video data bus. Byte serial CbYCrY data synchronous with VCLK. At powerup, the decoder does not drive VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA. General Purpose I/Os [1:7] Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the first HSYNC after the falling edge of VSYNC. VSYNC can accept vertical synchroni-zation or top/bottom field notification from an external source. (VSYNC HIGH = bot-tom field. VSYNC LOW = Top field) Active Low Host Interrupt Pin General Purpose I/O 36

TH-A5

1-17

TH-A5

2. Pin function (3/4)

Name

SDDATA[7]/VDATA2[7] /HDMARQ/GPIO24

SDDATA6/VDATA2[6] /HXCVR_EN/GPIO25

SDDATA5/VDATA2[5] HDMACK/GPIO26

SDDATA4/VDATA2[4]/ GPIO27

SDDATA3/ VDATA2[3]/GPIO28

SDDATA2/ VDATA2[2]/GPIO29

SDDATA1/

Parallel DVD/CD or Serial CD Interface

VDATA2[1]/GPIO30

SDDATA0/ VDATA2[0]/GPIO31

SDCLK

SDERROR

SDEN/GPIO33

SDREQ/GPIO32

VDAC_[4B:0B] VDAC_4 VDAC_3V DAC_2 VDAC_1 VDAC_0 VDAC_REF

VCLK

Analog Video OutputAudio InterfaceDigital Mic In

ADATA[3:0]/GPIO[4:1]

BCK LRCK

XCK

IEC958/GPIO14

DAI_DATA/GPIO15

DAI_BCK/ BYPASS_SYSCLK/ GPIO16 DAI_LRCK/ IEC958BP/GPIO17

Pin No.

168

169

170

171

174

175

176

177

183

182

179

178

117, 120, 123, 126, 129

119 122 125 128 131 135

105

155, 154, 151, 150

149

148 147

156

157

158

159

Type

I

O

Analog O Analog O Analog O Analog O Analog O Analog O

Analog I

I/O

O

I/O

O

I

1

Description

Compressed data from DVD DSP. Bit 7. In parallel mode, bit 7 is the first

(earliest in time) bit in the bitstream, while bit 0 is the last bit.

Video Data Bus 2, Bit 7

Host DMA Request

General Purpose I/O 24

Compressed data from DVD DSP. Bit 6.

Video Data Bus 2, Bit 6

ATAPI Transceiver Enable

General Purpose I/O 25

Compressed data from DVD DSP. Bit 5.

Video Data Bus 2, Bit 5

Host DMA Acknowledge

General Purpose I/O 26

Compressed data from DVD DSP. Bit 4.

Video Data Bus 2, Bit 4

General Purpose I/O 27

Compressed data from DVD DSP. Bit 3.

Video Data Bus 2, Bit 3

General Purpose I/O 28

Compressed data from DVD DSP. Bit 2.

Video Data Bus 2, Bit 2

General Purpose I/O 29

Compressed data from DVD DSP. Bit 1.

Video Data Bus 2, Bit 1

General Purpose I/O 30

In serial mode, bit 0 should be used as the input, with the unused bits

either used as GPIOs or tied to ground.

Video Data Bus 2, Bit 0

General Purpose I/O 31

Data clock. The maximum frequency is 25 MHz for parallel mode, and

???? MHz for serial mode. The polarity of this signal is programmable.

Error in input data. This signal carries the error bit associated with the

channel data type (if set, the byte is corrupted).

Data enable. Assertion indicates that data on SDDATA[7:0] is valid.

The polarity of this signal is programmable.

General Purpose I/O [33]

Bitstream request. controller asserts SDREQ to indicate that the bitstream

input buffer has available space.

General Purpose I/O 32

Video DAC Bias Bits[4:0]

DAC video output format: R, V, C, or CVBS. Macrovision encoded.

DAC video output format: B, U, C, or CVBS. Macrovision encoded.

DAC video output format: G or Y. Macrovision encoded.

DAC video output format: C. Macrovision encoded.

DAC video output format: CVBS or Y. Macrovision encoded.

Video DACs Reference Resistor. Connecting to pin 136 through

a 1.18K+/- 1% resis-tor is required.

System clock that drives internal PLLs. ZiVA-5 27-MHz TTL oscillator.

(See descrip-tion of VCLK for Digital Video Output.) Also optional video

clock for internal PLLs or external encoder.

PCM Data Out. Eight channels. Serial audio samples relative to BCK

and LRCK. General Purpose I/Os [4:1]

PCM Bit Clock. BCK can be either 48 or 32 times the sampling frequency

PCM Left Clock. Identifies the channel for each sample. The polarity is

programma-ble.

Audio External Frequency clock input or output. BCK and LRCK are

derived from this clock.

PCM data out (IEC-958 format ) or compressed data out

(IEC-1937 format). General Purpose I/O [14]

PCM data input.

General Purpose I/O [15]

PCM input bit clock.

BYPASS_SYSCLK: Alternate function TBS.

General Purpose I/O [16]

PCM left/right clock.

IEC958 input bypass

General Purpose I/O [17]

1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.

1-18

2. Pin function (4/4)

1

Name

IRRX1/GPIO0

IR

IDC_CL/GPIO18

IDC

IDC_DA/GPIO19

RTS1/GPIO20

RXD1/GPIO21

TXD1/GPIO22

UART1UART2JTAG

CTS1/GPIO23

RTS2/SPI_CLK/ GPIO37

RXD2/SPI_MISO/ GPIO38

TXD2/SPI_MOSI/ GPIO39

CTS2/SPI_CS/ GPIO40

TRST

TDO TDI/GPI0

TMS/GPI1

TCK

1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.

Pin No.

28

160

161

162

163

164

165

185

186

187

188

197

198 199

200

201

Description

Type

IR Remote Receive. This input connects to an integrated (photo diode,

I

band pass, demodulator) IR receiver. General Purpose I/O 0 Serial clock signal for IDC data transfer. It should be pulled up to the

I/O

positive supply voltage, depending on the device) using an external pull-up resistor. General Purpose I/O [18] Serial data signal for IDC data transfer. It should be pulled up to the supply voltage using an external pull-up resistor. General Purpose I/O [19] Ready to send, UART1

O

General Purpose I/O [20] Receive data, UART1

I

General Purpose I/O [21] Transmit data, UART1

O

General Purpose I/O [22] Clear to send, UART1

I

General Purpose I/O [23] Ready to send, UART2

O

Serial Peripheral Interface Clock General Purpose I/O [37] Receive data, UART2

I

Serial Peripheral Interface - Master Input/Slave Output General Purpose I/O [38] Transmit data, UART2

O

Serial Peripheral Interface - Master Output/Slave Input General Purpose I/O [39] Clear to send, UART2

I

Serial Peripheral Interface ???? General Purpose I/O [40] Test reset. BST reset - resets the TAP controller.

I

This signal must be pulled low. Test data Out. BST serial data output.

O

Test data In. BST serial data chain input.

I

General Purpose Input pin 0. Test mode select. Controls state of test access port (TAP) controller.

I

General Purpose Input pin 1. Test clock. Boundary scan test (BST) serial data clock.

I

TH-A5

3. Block diagram

Parallel/serial DVD Interface

I2S Stereo In

32-128Mbit

SDRAM

SDRAM Controller

Track Buffer

Processor

Audio

Decryption

ZiVA

A/V Core

Graphics

Engine

Input Unit

System Control Bus

Bus Interface Unit

IR GPIO SPI UART1&2ASYNC BUS IDC

ATAPI

Interlaced/

Progressive

Encoder

SPARC

Microprocessor

Phase

Lock

Loop

Video

JTAG Interface

Five 10-bit

Audio

Output

Unit

Video DACs

CCIR 656 Digital Video

Composite Y/R C Cr/Pr/G Cb/Pb/B

IEC 958/1937

Downmix Left/right Center/subwoofer Left/ right/surround

Remote Control

13.5 MHz Crystal

1-19

TH-A5

CS493292 (DIC11) : Audio decoder

1. Pin layout

A1,SCDIN

RD,R/W,EMOE,GPIO11

WR,DS,EMWR,GPIO10

AUDATA3,XMT958

DGND1

VD1

MCLK

SCLK

LRCLK

AUDATA0

AUDATA1

A0,SCCLK

DATA7,EMAD7,GPIO7

DATA6,ENAD6,GPIO6 DATA5,EMAD5,GPIO5 DATA4,EMAD4,GPIO4

VD2

DGND2 DATA3,EMAD3,GPIO3 DATA2,EMAD2,GPIO2 DATA1,EMAD1,GPIO1 DATA0,EMAD0,GPIO0

2. Block diagram

65432144 43 42 41 40

7 8 9 10 11 12 13 14 15 16 17

18 19 20 21 22 23 24 25 26 27 28

CS

VD3

DGND3

SDATAN1

ABOOT,INTERQ

EXTMEM,GPIO8

SCLKN1,STCCLK2

SCDIO,SCDOUT,PSEL,GPIO9

AUDATA2

39

DC

38

DD

37

RESET

36

AGND

35

VA

34

FILT1

33

FILT2

32

CLKSEL

31

CLKIN

30

CMPREQ,LRCLKN2

29

LRCLKN1

CMPCLK,SCLKN2

CMPDAT,SDATAN2,RCV958

1-20

CMPDAT

SDATAN2

CMPCLK

SCLKN2

CMPREQ

LRCLKN2

SCLKN1

STCCLK2 LRCLKN1

SDATAN1

CLKIN

CLKSEL

RESET

Compressed

Data Input

Interface

Digital

Audio

Input

Interface

PLL

Clock Manager

DATA7:0

EMAD7:0

GPIO7:0

Framer

Shifter

Input

Buffer

Controller

RAM Input

Buffer

CS

RD

R/W

EMOE

GPIO11

SCDIO

WR

SCDOUT

DS

EMWR

GPIO10

Parallel or Serial Host Interface

DPS Processing

RAM

Program

Memory

ROM

Program

Memory

PSEL

GPIO9A0SCCLKA1SCDIN

24-Bit

RAM

Data

Memory

ROM

Data

Memory

STC

VD[3:1]DGND[3:1]AGNDVAFILT1 FILT2

RAM

Output

Buffer

ABOOT

INTERQ

EXTMEM

GPIO8

Output

Formatter

DC DD

MCLK

SCLK

LRCLK

AUDATA[2.0]

XMT958 /AUDATA3

3. Pin function

TH-A5

Pin No. 1,12,23 2,13,24

3 4

5 6

7 8

9 10 11 14 15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Symbol

VD1,VD2,VD3

DGND1,DGND2,DGND3

AUDATA3,XMT958

WR,DS,EMWR,GPIO10

RD,R/W,EMOE,GPIO11

A1,SCDIN

A0,SCCLK

DATA7,EMAD7,GPIO7

DATA6,ENAD6,GPIO6 DATA5,EMAD5,GPIO5 DATA4,EMAD4,GPIO4 DATA3,EMAD3,GPIO3 DATA2,EMAD2,GPIO2 DATA1,EMAD1,GPIO1 DATA0,EMAD0,GPIO0

CS

SCDIO,SCDOUT,PSEL,GPIO9

ABOOT,INTERQ

EXTMEM,GPIO8

SDATAN1

SCLKN1,STCCLK2

LRCLKN1

CMPDAT,SDATAN2

CMPCLK,SCLKN2

CMPREQ,LRCLKM2

CLKIN

CLKSEL

FILT1 TILT2

VA

AGND

RESET

DC

DD AUDATA2 AUDATA1 AUDATA0

LRCLK

SCLK MCLK

Function Digital Positive Supply Digital Supply Ground SPDIF Transmitter Output, Digital Audio Output 3 Host write strobe or Host data strobe or External Memory write enable or General purpose input& output Number 10 Host Parallel Output Enable or Host Parallel R/W or External Memory Output Enable or General Purpose Input & Output Number11 Host Address Bit One or SPI Serial Control Data Input Host Parallel Address Bit Zero or Serial Control Port Clock Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Host Parallel Chip Select, Host Serial SPI Chip Select Serial Control Port Data Input and Output, Parallel Port Type Select Control Port Interrupt Request, Automatic Boot Enable External Memory Chip Select or General Purpose Input & Output Number 8 PCM Audio Data Input Number One PCM Audio Input Bit Clock PCM Audio Input Sample Rata Clock PCM Audio Data Input Number Tow PCM Audio Input bit Clock PCM Audio Input Sample Rate Clock Master Clock Input DSP Clock Select Phase Locked Loop Filter Phase-Locked Loop Filter Analog Positive Supply Analog Supply Ground Master Reset Input Reserved Reserved Digital Audio Output 2 Digital Audio Output 1 Digital Audio Output 0 Audio Output Sample Rate Clock Audio Output Bit Clock Audio Master Clock

BA4560 (IC2, IC5, IC6, IC7, CIC11, CIC13, FIC2, FIC4, FIC5, FIC6, FIC11, RIC11, RIC13)

: Dual op amp.

1.Pin layout

V

OUT1

– IN1

+ IN1

V

1

2

1ch

+

–

3

EE

4

2ch

+

–

CC

8

OUT2

7

– IN2

6

+ IN2

5

1-21

TH-A5

SP3721A (U7) : DVD driver

1.Pin layout

1

16

2.Pin function (1/2)

Pin No.

2

3,4

5~6

7~ 8

11~14

15~16

Symbol I/O Function

1

DVDRFP DVDRFN

PD1,PD2

A2,B2 C2,D2

9

10

17 18 19 20 21 22 23 24 25

26

27 28 29 30

31

32

33

CP

CN

A,B,C,D

E,F

CDTE

VCI2

NC

VNB DVDPD DVDLD

CDPD CDLD

LDON#

VC

VCI

VPB

MIRR

MP

MB

FDCHG#

MLPF

I/O

64 ~ 49

48

~

17 ~ 32

RF Signal Inputs. Differential RF signal attenuator input pins.

I

CD Photo detector Interface Inputs. Inputs from the CD photo detector error outputs.

I

Photo Detector Interface Inputs. AC coupled inputs for the DPD from

I

the main beam Photo detector matrix outputs. Differential Phase tracking LPF pin. An external capacitance is connected between this pin and the CN pin. Differential Phase tracking LPF pin. An external capacitance is connected between this pin and the CP pin. Photo Detector Interface Inputs. Inputs from the main beam Photo

I

detector matrix outputs. CD tracking Error Inputs. Inputs from the CD photo detector error outputs.

I

CD Tracking. E-F Opamp output for feedback.

Reference Voltage input. DC bias voltage input for the servo input reference.

No Connect.

Ground. Ground pin for the servo block.

APC Input. DVD APC input pin from the monitor photo diode.

I

APC output. DVD APC output pin to control the laser power.

O

APC Input. DVD APC input pin from the monitor photo diode.

I

APC output. DVD APC output pin to control the laser power.

O

APC output. on/off. APC output control pin. A low level activates the

I

LD output. (open high) Reference Voltage output. This pin provides the internal DC bias

reference voltage (+2.5+ fix). Output impedance is less than 50 ohms. Reference Voltage input. DC bias voltage input for the servo input reference.

Power. Power supply pin for the servo block.

Mirror Detect Output. Mirror Detect comparator output. Pseudo CMOS output.

O

MIRR signal Peak hold pin. An external capacitance is connected to

between this pin and VPB. MIRR signal Bottom hold pin. An external capacitance is connected to

between this pin and VPB. Low Impedance Enable. A TTL compatible input pin that activates the FDCHG switches.

I

A low level activates the switches and the falling edge of the internal FDCHG triggers the fast decay for the NIRR bottom hold circuit. (open high) MIRR signal LPF pin. An external capacitance is connected between this pin and VPB.

-

~

33

1-22

2.Pin function (2/2)

Pin No.

34 35

36

37

38 39

40 41 42 43 44

45

46

47

48

49

50 51 52 53

54

55

56

57 58 59 60 61 62 63 64

Symbol

MEVO

MIN

PI

DFT

TPH

MEV

MEI

TE FE

CE

LCN

LCP

SCLK

SDATA

SDEN

HOLD1

VNA FNN FNP

DIP

DIN

RX

BYP

SIGO

VPA

AIP

AIN ATON ATOP CDRF

CDRFDC

I/O

SIGO Bottom Envelope Output. Bottom envelope for Mirror detection.

O

RF signal Input for Mirror. AC coupled inputs for the mirror detection

I

circuit from the pull-in signal output. (PI) Pull-in Signal Output. The summing signal output of A,B,C,D or PD1,

O

PD2 for mirror detection. Reference to VCI. Defect Output. Pseudo CMOS output. When a defect is detected, the

O

DFT output goes high. Also the servo AGC output can be monitored at this pin, When CAR bits 7-4 are '0011'. PI Top Hold pin. An external capacitance is connected between this pin and VPB.

SIGO Bottom Envelope pin. An external capacitance is connected

between this pin and VPB.

Mirror Envelope Input. The SIGO envelope input pin.

I

Tracking Error Signal Output. Tracking error output reference to VCI.

O

Focusing Error Signal Output. Focus error output reference to VCI.

O

Center Error Signal Output. Center error out put reference to VCI.

O

Center Error LPF pin. An external capacitance is connected between

this pin and the LCP pin.

Center Error LPF pin. An external capacitance is connected between

this pin and the LCN pin.

Serial Clock. Serial Clock CMOS input. The clock applied to this pin

I

is synchronized with the data applied to SDATA. (Not to be left open). Serial Data. Serial data bi-directional CMOS pin. NRZ programming

I/O

data for the internal registers is applied to this input. (Not to be left open) Serial Data Enable. Serial enable CMOS input. A high level input

I

enables the serial port. (Not to be left open) Hold Control. ATTL compatible control pin which, when pulled high, disables the RF AFC

I

charge pump and holds the RE AGC amplifier gain at its present value. (open high) Ground. Ground pin for the RF block and serial port.

Differential Normal Output. Filter normal outputs.

O

Differential Normal Output. Filter normal outputs.

O

Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended

I

output buffer and full wave rectifier. Analog inputs for RF Single Buffer. Differential analog inputs to the RF single-ended

I

output buffer and full wave rectifier. Reference Resistor Input. An external 8.2 kohm, 1% resistor is

connected from this pin to ground to establish a precise PTAT

(proportional to absolute temperature) reference current for the filter. The RF AGC integration capacitor CBYP, is connected between BYP and VPA.

I/O

Single Ended Normal Output. SIngle-ended RF output.

O

Power. Power supply pin for the RF block and serial port.

AGC Amplifier Inputs. Differential AGC amplifier input pins.

I

AGC Amplifier Inputs. Differential AGC amplifier input pins.

I

Differential Attenuator Output. Attenuator outputs.

O

Differential Attenuator Output. Attenuator outputs.

O

RF Signal Input. Single-ended RF signal attenuator input pin.

I

CD RF Signal Output. Single ended CD RF summing output.

O

Function

TH-A5

1-23

TH-A5

W986432DH (U5) : SDRAM

1. Pin layout

Q CC

DQ12

VssDQ15

VSSQDQ14

86858483828180797877767574737271706968676665646362616059585756555453525150494847464544

12345678910111213141516171819202122232425262728293031323334353637383940414243

Q

DQ0

DQ1

VCC

CC V

DQ13

DQ2

V

Q SS

V

DQ3

DQ11

DQ4

Q SS

V

Q CC

V

DQ10

DQ5

DQ9

DQ6

Q CC

DQ8NCV

V

VSSQ

DQ7

NC

SS

DQM1NCNC

VCC

WE

DQM0

CLK

CKEA9A8A7A6A5A4A3DQM3

CAS

RAS

CS

NC

BS0

BS1

A0A1A2

A10/AP

VSSNC

CC V

DQM2

NC

DQ31

DQ16

Q CC

V

Q SS

V

DQ30

DQ17

DQ29

DQ18

Q SS

V

Q CC

V

DQ28

DQ19

DQ27

DQ20

Q CC

V

Q SS

V

DQ26

DQ21

DQ25

DQ22

Q SS

V

Q CC

V

DQ24

DQ23

2. Block diagram

CLK

CKE

CS

RAS

CAS

WE

CLOCK

BUFFER

COMMAND

DECODER

CONTROL

SIGNAL

GENERATOR

COLUMN DECODER

SS V

CC V

3. Pin function

Symbol A0-A10

BS0, BS1

DQ0-DQ31

CS RAS CAS

WE

DQM0-DQM3

CLK CKE VCC VSS

VCCQ VSSQ

NC

A10

A0

ADDRESS

BS0 BS1

A9

REFRESH

COUNTER

BUFFER

Function Address Bank Select Data Input/Output Chip Select Row Address Strobe Column Address Strobe Write Enable Input/output mask Clock Inputs Clock Enable Power(+3.3V) Ground Power(+3.3V) for I/O buffer Ground for I/O buffer No Connection

MODE REGISTER

COLUMN

COUNTER

CELL ARRAY

BANK #0

ROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

CELL ARRAY

BANK #2

ROW DECODER

SENSE AMPLIFIER

DATA CONTROL

CIRCUIT

CELL ARRAY

BANK #1

ROW DECODERROW DECODER

SENSE AMPLIFIER

COLUMN DECODER

CELL ARRAY

BANK #3

SENSE AMPLIFIER

DQ BUFFER

DQ0

DQ31

DQM0~3

1-24

LC86P6548 (UIC1) : Microcontroller

1.Pin layout

S47/PF7

S46/PF6

S45/PF5

S44/PF4

S43/PF3

S42/PF2

S41/PF1

S40/PF0

VDD4

S39/PE7

S38/PE6

S37/PE5

S36/PE4

S35/PE3

S34/PE2

S33/PE1

S32/PE0

S31/PD7

S30/PD6

S29/PD5

S28/PD4

S27/PD3

S26/PD2

S25/PD1

S24/PD0

S23/PC7

S22/PC6

S21/PC5

S20/PC4

VP

TH-A5

2.Block diagram

S48/PG0 S49/PG1 S50/PG2 S51/PG3

P00 P01 P02 P03

VSS2

VDD2

P04 P05 P06 P07

P10/SO0

P11/SI0/SB0

P12/SCK0

P13/SO1

P14/SI1/SB1

P15/SCK1

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Interrupt Control

Standby Control

CF

RC

X’tal

8079787776757473727170696867666564636261605958575655545352

1234567891011121314151617181920212223242526272829

P30

P31

P32

P33

P34

P35

P36

P16/BUZ

P17/PWM0

Clock

Generator

P37

P70/INT0

RES

XT1/P74

CF1

VSS1

XT2/P75

CF2

VDD1

P80/AN0

P81/AN1

P82/AN2

IR PLA

PROM Control

PROM(48KB)

PC

P83/AN3

P84/AN4

P85/AN5

A15-A0 D7-D0 TA CE OE DASEC

P86/AN6

P87/AN7

P71/INT1

P72/INT2/T0I

51

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

30

S0/T0

P72/INT3/T0I

S19/PC3 S18/PC2 S17/PC1 S16/PC0 VDD3 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1

Base Time

r

SIO0

SIO1

Timer 0

er 1

Tim

ADC

INT0-3

Noise Filter

SIO Auto

matic

transmission

RAM

128 by

s

te

VFD

Controller

High voltage Output

Bus Interface

Port 1

Port 3

Port 7

Port 8

ACC

B Register

C Register

A

PSW

RAR

RAM

Stack Poi nter

Port 0

Watchdog Timer

1-25