* All printed circuit boards and its assemblies are not available as service parts.
Area suffix
B ------------------------------- U.K.
E ----------- Continental Europe
EN ------------ Northern Europe
EV -------------- Eastern Europe
EE --------- Russian Federation
TH-A30R
- Contents -
Exploded view of general assembly and parts list (Block No.M1)
DVD mechanism assembly and parts list (Block No.MJ)
Electrical parts list (Block No.01~05)
Packing materials and accessories parts list (Block No.M3,M5)
SCREW
SCREW
SCREW
SCREW
SCREW
SCREW
DVD BADGE
WINDOW FRONT
FRONT CAP
TRAY DOOR
FRONT CABINET
POWER LENS
KNOB POWER
KNOB OPEN
LENS FRONT
KNOB FUNCTION
HOLDER LED
KNOB PLAY
VFD HOLDER
FOOT HOLDER
CUSHION FOOT
FOOT HOLDER
CUSHION FOOT
CABINET BOTTOM
CABINET TOP
CABINET REAR
COVER FAN
HEAT SINK D
HEAT SINK B
HEAT SINK
IC HOLDER
IC HOLDER
HEAT SINK
HEAT SINK M
HEAT SINK
POWER CUSHION
LABEL DTS
STICKER CD
LABEL RATING
LABEL RATING
MOTOR FAN
TUNER PACK
TRANS POWER
POWER CORD
POWER CORD
AC CORD RING
PACKING CASE
CUSHION L
CUSHION R
POLY BAG
POLY BAG
CUSHION TOP
CUSHION BOTTO M
CUSHION TOP
CUSHION BOTTO M
POLY BAG
POLY BAG
PACKING CASE
REMOCON ASSY
INSTRUCTIONS
INSTRUCTIONS
INSTRUCTIONS
INSTRUCTIONS
INSTRUCTIONS
INSTRUCTIONS
WARANTY CARD
WARANTY CARD
IMPORTANT CARD
FM ANT
AM ANT
RCA CABLE
BATTERY
SPEAKER BOX
SPEAKER BOX
SPK CORD LABEL
SPK CORD LABEL
SPK CORD LABEL
SPK CORD LABEL
SPK CORD LABEL
SPEAKER BOX
SPK CORD LABEL
Q'ty
1
SET
1
SET
1
SET
1
SET
1
INSTRUCTIONS
1
SPEAKER BOX
1
SPEAKER BOX
1
SPEAKER BOX
1
SPEAKER BOX
1
SPEAKER BOX
1
SPEAKER BOX
1
SPEAKER BOX
Q'ty
1
1
SWE,FIN,DAN
1
GER,FRE,SPA,ITA
1
ENG
1
FRE,FRE,DUT
1
POL,HUN,CZE
1
RUS
1
1
1
1
1
1
2
3
FRONT/CENTER
2
REAR
1
ERONT L
1
ERONT R
1
CENTER
1
REAR L
1
REAR R
1
SUBWOOFER
1
SUBWOOFER
Block No. M3MM
Description
Block No. M5MM
Description
EN
EN
B
E
EV
EE
EV,EE
B,E,EN
B
3-23
SERVICE MANUAL
DVD DIGITAL CINEMA SYSTEM
TH-A30R
STAND BY/ON
AUDIO
TV/VIDEO
VCR
TV
DISPLAY
STEP
AUDIO/
SUBTITL E
FM MOD E
DVD FM/AM AUX
TUNER PRESET
DOWNUP
REW
VCR CHANNE L
TUNING
B.SEARCHF.SEARCH
ENTER
VOLUM E
TOP MENU
MENU
RETURN
RM-STHA30R
DVD CI NEMA SYST E M
TH-A30R
Area suffix
B -------------------------- U.K.
E ------ Continental Europe
EN ------- Northern Europe
EV --------- Eastern Europe
EE ---- Russian Federation
SP-XSA30 2
RDS
DISPLAY
TV CHANNE L
TV VOLUME
VCR
CONT ROL
FF
MUTING
STANDBY
STANDBY/ON
AUDIO/FM MODE
DSP
VOLUMESOURCE
DVD DIGITAL CINEMA SYSTEM TH-A30R
XV-THA30RSP-WA30
SP-XA30 3
DIGITAL
SURROUN D
DIGITAL
Contents
Safety precautions
Preventing static electricity
Important for laser products
1-2
1-4
1-5
Disassembly method
Wiring connection
Description of major ICs
COPYRIGHT 2002 VICTOR COMPANY OF JAPAN, LTD.
1-6
1-12
1-13~30
No.21163
Dec. 2002
TH-A30R
1. This design of this product contains special hardware and many circuits and components specially for safety
purposes. For continued protection, no changes should be made to the original design unless authorized in
writing by the manufacturer. Replacement parts must be identical to those used in the original circuits. Services
should be performed by qualified personnel only.
2. Alterations of the design or circuitry of the product should not be made. Any design alterations of the product
should not be made. Any design alterations or additions will void the manufacturer`s warranty and will further
relieve the manufacture of responsibility for personal injury or property damage resulting therefrom.
3. Many electrical and mechanical parts in the products have special safety-related characteristics. These
characteristics are often not evident from visual inspection nor can the protection afforded by them necessarily
be obtained by using replacement components rated for higher voltage, wattage, etc. Replacement parts which
have these special safety characteristics are identified in the Parts List of Service Manual. Electrical
components having such features are identified by shading on the schematics and by ( ) on the Parts List in
the Service Manual. The use of a substitute replacement which does not have the same safety characteristics
as the recommended replacement parts shown in the Parts List of Service Manual may create shock, fire, or
other hazards.
4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the like to be
separated from live parts, high temperature parts, moving parts and/or sharp edges for the prevention of
electric shock and fire hazard. When service is required, the original lead routing and dress should be
observed, and it should be confirmed that they have been returned to normal, after re-assembling.
5. Leakage currnet check (Electrical shock hazard testing)
After re-assembling the product, always perform an isolation check on the exposed metal parts of the product
(antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control shafts, etc.) to be sure the
product is safe to operate without danger of electrical shock.
Do not use a line isolation transformer during this check.
Plug the AC line cord directly into the AC outlet. Using a "Leakage Current Tester", measure the leakage
current from each exposed metal parts of the cabinet, particularly any exposed metal part having a return
path to the chassis, to a known good earth ground. Any leakage current must not exceed 0.5mA AC (r.m.s.).
Alternate check method
Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms per volt or more
sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by a 0.15 F AC-type capacitor
between an exposed metal part and a known good earth ground.
Measure the AC voltage across the resistor with the AC
voltmeter.
Move the resistor connection to each exposed metal part,
particularly any exposed metal part having a return path to
the chassis, and meausre the AC voltage across the resistor.
Now, reverse the plug in the AC outlet and repeat each
measurement. Voltage measured any must not exceed 0.75 V
AC (r.m.s.). This corresponds to 0.5 mA AC (r.m.s.).
0.15 F AC TYPE
1500 10W
Good earth ground
AC VOLTMETER
(Having 1000
ohms/volts,
or more sensitivity)
Place this
probe on
each exposed
metal part.
!
1. This equipment has been designed and manufactured to meet international safety standards.
2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.
3. Repairs m ust be made in accordance with the relevant safety standards.
4. It is essential that safety critical components are replaced by approved parts.
5. If mains voltage selector is provided, check setting for local voltage.
Burrs formed during molding may
be left over on some parts of the
chassis. Therefore, pay attention to
such burrs in the case of
preforming repair of this system.
In regard with component parts appearing on the silk-screen pr inted side (parts side) of the PWB diagrams, the
parts that are printed over with black such as the resistor ( ), diode ( ) and ICP ( ) or identified by the " "
mark nearby are critical for safety.
(This regulation does not correspond to J and C version.)
1-2
TH-A30R
(U.K only)
1. This design of this product contains special hardware and many circuits and components specially
for safety purposes. For continued protection, no changes should be made to the original
design unless authorized in writing by the manufacturer. Replacement parts must be identical to
those used in the original circuits.
2. Any unauthorised design alterations or additions will void the manufacturer's guarantee ; furthermore the
manufacturer cannot accept responsibility f or personal injury or property damage resulting therefrom.
3. Essential safety critical components are identified by ( ) on the Parts List and by shading on the
schematics, and must never be replaced by parts other than those listed in the manual. Please note
however that many electrical and mechanical parts in the product have special safety related
characteristics. These characteristics are often not evident from visual inspection. Parts other than
specified by the manufacturer may not have the same safety characteristics as the recommended
replacement parts shown in the Parts List of the Service Manual and may create shock, fire, or
other hazards.
4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the
like to be separated from live parts, high temperature parts, moving parts and/or sharp edges
for the prevention of electric shock and fire hazard. When service is required, the original lead
routing and dress should be observed, and it should be confirmed that they have been returned
to normal, after re-assembling.
1. Service should be performed by qualified personnel only.
2. This equipment has been designed and manufactured to meet international safety standards.
3. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.
4. Repairs must be made in accordance with the relevant safety standards.
5. It is essential that safety critical components are replaced by approved parts.
6. If mains voltage selector is provided, check setting for local voltage.
!
Burrs formed during molding may be left over on some parts of the chassis. Therefore,
pay attention to such burrs in the case of preforming repair of this system.
1-3
TH-A30R
Preventing static electricity
1.Grounding to prevent damage by static electricity
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged,
can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when perf orming repairs.
2.About the earth processing for the destruction prevention by static electricity
Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as CD players.
Be careful to use proper grounding in the area where repairs are being performed.
2-1 Ground the workbench
Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over
it before placing the traverse unit (optical pickup) on it.
2-2 Ground yourself
Use an anti-static wrist strap to release any static electricity built up in your body.
(caption)
Anti-static wrist strap
Conductive material
(conductive sheet) or iron plate
3. Handling the optical pickup
1. In order to maintain quality during transport and before installation, both sides of the laser diode on the
replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition.
(Refer to the text.)
2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power
source can easily destroy the laser diode.
4.Handling the traverse unit (optical pickup)
1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.
2. Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific
details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the traverse
unit. Be careful not to take too long a time when attaching it to the connector.
3. Handle the flexible cable carefully as it may break when subjected to strong force.
4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it.
Attention when traverse unit is decomposed
*Please refer to "Disassembly method" in the text for pick-up and how to detach the substrate.
Solder is put up before the card
1.
wire is removed from connector
on the pick up board as shown in
Figure.
(When the wire is removed
without putting up solder, the CD
pick-up assembly might destroy.)
Please remove solder after
2.
connecting the card wire with
when you install picking up
in the substrate.
DVD mechanism assembly (bottom side)
DVD loading
mechanism
Pick up board
Card wire
Short land
(These two points are
soldered respectively,
and are made to
short-circuit)
Connector
1-4
DVD loader board
Important for laser products
TH-A30R
1.CLASS 1 LASER PRODUCT
2.DANGER : Invisible laser radiation when open and inter
lock failed or defeated. Avoid direct exposure to beam.
3.CAUTION : There are no serviceable parts inside the
Laser Unit. Do not disassemble the Laser Unit. Replace
the complete Laser Unit if it malfunctions.
4.CAUTION : The compact disc player uses invisible laser
radiation and is equipped with safety switches which
prevent emission of radiation when the drawer is open and
the safety interlocks have failed or are de
feated. It is dangerous to defeat the safety switches.
5.CAUTION : If safety switches malfunction, the laser is able
to function.
6.CAUTION : Use of controls, adjustments or performance of
procedures other than those specified herein may result in
hazardous radiation exposure.
!
Please use enough caution not to
see the beam directly or touch it
in case of an adjustment or operation
check.
REPRODUCTION AND POSITION OF LABELS
CLASS 1
LASER PRODUCT
WARNING LABEL
1-5
TH-A30R
Disassembly method
Removing the top cover (See Fig.1)
1.
Remove the four screws A attaching the top cover
on both sides of the body.
2.
Remove the three screws B on back of the body.
3.
Remove the top cover from behind in the direction of
the arrow while pulling both sides outward.
Removing the front panel assembly
(See Fig.2A, 2B and 3)
Prior to performing the following procedure, remove
the top cover.
1.
Remove the three screws C attaching the front panel
assembly on bottom of the body.
2.
Remove the two screws D attaching the front panel
assembly on both sides of the body.
3.
Remove the claw1, claw2 and claw3, and detach the
front panel assembly toward the front.
4.
Disconnect the card wire from the connector FCW1
and FCW2 on the display board.
Top cover
(both sides)
Claw1
(bottom side)
B
A
Fig.1
Front panel assembly
CC
Fig.2A
Claw3
Front panel assembly
Claw2
(both sides)
Removing the power cord (See Fig.4)
Prior to performing the following procedure, remove
the top cover.
1.
Cut off the tie bands fixing the power cord.
2.
Disconnect the power cord from the connector
ACW1 on the main board and pull up the cord
stopper upward.
Notes : The power cord is exchangeable.
Power cord
ACW1
Tie band
D
(both sides)
Display board
Front panel assembly
(Inner side)
Fig.2B
FCW1FCW2
1-6
Rear panel
Fig.4
Power cord
stopper
Fig.3
TH-A30R
Removing the DVD mechanism assembly
(See Fig.5 and 6)
Prior to performing the following procedure, remove
the top cover.
1.
Disconnect the card wire from the connector J14 and
J21 on the DVD MPEG board.
2.
Remove the two screws E attaching the DVD
mechanism assembly and pull up with drawing out.
3.
Disconnect the harness from the connector DJ6 on
the DVD loader board.
Removing the rear panel (See Fig.7 and 8)
Prior to performing the following procedure, remove
the top cover and power cord stopper.
1.
Disconnect the harness from the connector J9 on the
DSP board.
2.
Remove the two screws F, four screws G, one screw
I and five screws J attaching the each board to the
rear panel. And remove the three screws K attaching
the rear panel on back of the body.
DVD mechanism assembly
DVD
MPEG
board
J14
E
J21
Fig.5
DVD mechanism
assembly
Removing the tuner pack (See Fig.7 and 8)
Prior to performing the following procedure, remove
the top cover.
1.
Disconnect the card wire from the connector CON01
on the tuner pack.
2.
Remove the two screws F attaching the tuner pack
to the rear panel.
Removing the jack board (See Fig.7 and 8)
Prior to performing the following procedure, remove
the top cover.
1.
Cut off the tie bands fixing the power cord.
2.
Disconnect the card wire from the connector JVW2
on the jack board.
3.
Remove the four screws G attaching the jack board
to the rear panel.
4.
Disconnect the connector VW1 and remove the DSP
board.
Fan motor
J
VW1
H
DJ6
Fig.6
I
Fig.7
DSP board
K
DVD loader board
Rear panel
G
F
KK
Removing the fan motor (See Fig.7 and 8)
Prior to performing the following procedures, remove
the top cover .
1.
Disconnect the harness from the connector J9 on the
DSP board .
2.
Removing the two screws H attaching the fan motor
to the rear panel.
Rear panel
J9(on the
DSP board)
Fig.8
JVW2
Jack board
CON01
Tie band
Tuner pack
1-7
TH-A30R
Removing the DSP board (See Fig.9)
Prior to performing the following procedure, remove
the top cover, front panel assembly, DVD
mechanism assembly and jack board.
1.
Remove the harness band fixing the harness.
2.
Disconnect the harness from the connector J9 on the
DSP board.
3.
Disconnect the card wire from the connector J1 and
J3 on the DSP board.
4.
Remove the one screw L attaching the DSP board.
5.
Remove the screw M1 and remove the earth wire.
6.
Remove the one screw I attaching the DSP board to
the rear panel (see fig.7).
7.
Pull up the DSP board from the front side upwards
disconnecting the connector J2, J5, J6 and J7.
Removing the main board (See Fig.10)
Prior to performing the following procedure, remove
the top cover, front panel assembly, power cord,
DVD mechanism assembly, jack board and DSP
board.
1.
Disconnect the card wire from the connector CW8 on
the main board.
2.
Disconnect the harness from the connector ACW2,
ACW3, ACW4 and ACW5 on the main board.
Harness band
J9
(Rear panel side)
Main board
ACW2
CW8
M2
DSP board
J6J5 J7J2
M1
(fixing the
earth wire)
Fig.9
M2
J1J3
L
(Front panel side)
Heat sink1
M2
Heat sink2
ACW3
M2
3.
Remove the five screws J attaching the speaker
terminals and jack to the rear panel (see fig.7).
4.
Remove the nine screws M2 attaching the main
board.
5.
When the rear panel is not removed, pull up the
main board from front side.
Removing the power transistor & power IC
(See Fig.10 to 12)
Prior to performing the following procedure, remove
the top cover, front panel assembly, DVD
mechanism assembly, jack board, DSP board and
main board.
1.
After removing the solder part 1 soldered to the main
board, remove each screw and remove the heat sink
from the power transistor.
2.
After removing the solder part 2 soldered to the main
board, remove each screw and remove the heat sink
from the power IC.
1-8
Heat sink3
Fig.10
(Each power transistor is fixed)
Solder part 1
Solder part 3
Solder part 2
(Power IC is fixed)
(Power IC is fixed)
Fig.11
ACW5
ACW4
Main board
(Reverse side )
TH-A30R
3.
The power ICs fixed to the heat sink 3 can be
removed individually that it is easy to remove
screws (in meaning that a screw driver reaches). It is
not necessary to remove whole like abovementioned 1. and 2. .
After removing each screw which is fixing each
power IC to the heat sink 3, the solder part 3 to
which it corresponds on the main board is removed.
In addition, probably, the way after removing the
whole will be safe when a screw driver does not
reach too.
Removing the power transformer
(See Fig.13)
Prior to performing the following procedure, remove
the top cover.
1.
Cut off the tie band fixing the harness, if needed.
2.
Disconnect the harness from the connector ACW2
(see fig.10), ACW3, ACW4 and ACW5 on the main
board.
3.
Remove the four screws N attaching the power
transformer.
<Front panel assembly section>
Removing the display board & switch
board (See Fig.1 and 2)
Prior to performing the following procedure, remove
the top cover and the front panel assembly.
Heat sink 3
(to which power
IC is attached)
Heat sink 2
(to which power
IC is attached)
Heat sink 1
(to which power
transistor is attached)
Tie band
Display board
FCW2
N
Screws
FCW1
Fig.12
ACW4 ACW3
ACW5
Power
transformer
Fig.13
Front panel assembly
(inner side)
Switch board
1.
Disconnect the card wire from the connector FCW1
and FCW2 on the display board.
2.
Remove the five screws A attaching the display
board on the inner of the front panel assembly.
3.
Remove the four screws B attaching the switch
board on the inner of the front panel assembly.
4.
Disconnect the harness from connector FW2 on the
display board, if needed.
Removing the front window
(See Fig.2 and 3)
Prior to performing the following procedure, remove
the top cover, front panel assembly, display board
and switch board.
Remove the switch buttons, if needed.
1.
Remove the three screws C attaching the front
2.
window on the front panel.
Remove the eight claws fixing the front window on
3.
the front panel.
A
FW2
B
Fig.1
Front panel assembly
(inner side)
Switch button
CCC
Claw
Fig.2
Front panel assembly
Front window
Fig.3
(front side)
1-9
TH-A30R
<DVD mechanism assembly section>
Removing the DVD loader board
(See Fig.1 to 3)
Prior to performing the following procedure, remove
the top cover and DVD mechanism assembly.
1.
Disconnect the card wire from the connector J6 on
the DVD MPEG board.
2.
Disconnect the harness from the connector on the
motor board.
3.
Disconnect the harness from the connector MJ5 on
the DVD loader board.
4.
Remove the four screws A attaching the DVD loader
board to DVD mechanism assembly.
CAUTION!! (see fig.3)
Before removing the card wire which
connects the pickup board and DVD loader
board, solder the two soldering parts and
make it short-circuit.
Moreover, while having removed the card
wire, don't remove these solder.
DVD MPEG board
DVD loader board
A
RCN1
MJ5
DVD mechanism assembly
(top side)
J6
Fig.1
DVD mechanism assembly
(bottom side)
Motor board
Connector
Fig.2
5.
Disconnect the card wire from the connector RCN1
on the DVD loader board.
ONE POINT
How to eject the DVD tray manually
(see fig.2)
The white lever of the mark is moved in
the direction of the arrow. Then, the tray will
be opened.
Moreover, the tray is separable from a DVD
mechanism assembly by removing two
screws of the mark (see fig.1) and drawing
out the tray.
Removing the DVD loading mechanism
(See Fig.4)
Prior to performing the following procedure, remove
the top cover, DVD mechanism assembly and DVD
loader board.
1.
Remove the two screws B and remove the bracket.
2.
Remove the one screw C fixing the DVD loading
mechanism.
Pick up
board
Lever
Soldering parts
X
Motor board
Fig.3
DVD mechanism assembly
B
Bracket
DVD loading
mechanism
(bottom side)
DVD loading
mechanism
3.
Move the lever in the direction of the arrow X.
4.
Remove the DVD loading mechanism from the DVD
mechanism assembly by moving it in the direction of
the arrow Y.
1-10
Y
C
Fig.4
TH-A30R
m
)
Removing the DVD traverse mechanism
(See Fig.5)
Prior to performing the following procedure, remove
the top cover, DVD mechanism assembly, DVD
loader board and DVD loading mechanism.
1.
Remove the four screws D attaching the DVD
traverse mechanism to DVD loading mechanism.
Removing the holder & DVD MPEG board
(See Fig.6 and 7)
Prior to performing the following procedure, remove
the top cover, DVD mechanism assembly and DVD
loader board.
1.
Remove the two claws1, and remove the holder from
the DVD mechanism assembly as it is pushed down.
DVD traverse
mechanism
Claw1
D
Holder
DVD loading mechanis
(top side
D
Fig.5
Note: When removing only the DVD MPEG board, it is not
necessary to remove this holder.
2.
Remove the four claws2 and remove the DVD
MPEG board from the holder.
ONE POINT
When inserting DVD MPEG board in
holder. (see fig.8)
Insert in after uniting with a lower claws,
when inserting DVD MPEG board in holder.
Holder
Holder
DVD mechanism assembly
Fig.6
DVD MPEG board
Fig.7
DVD MPEG board
(bottom side)
Claw2
< Speaker section >
It is exchange in a unit.
Please do not decompose.
Fig.8
1-11
TH-A30R
Wiring connection
J6
J14
J21
3809-001273
DVD MPEG
BOARD
3809-001295
DJ3
3809-001305
DVD LOADER BOARD
RCN1
Color codes are shown below.
1 Brown
2 Red
3 Orange
4 Yellow
5 Green
Power for input buffers and logic circuit inside DRAM. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
No connection
Power for input buffers and logic circuit inside DRAM. (+3.3V)
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Referred to RAS
Referred to RAS
Command input. When sampled at the rising edge of the clock RAS,
CAS and WE define the operation to be executed.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
No connection
Select bank to activate dining row address latch time,
or bank to read / write during address latch time.
Multiplexed pins for row and column address. Row address: Ao-A10.
Column address:A0-A7.A10 is sampled during a recharge command to
determine if all banks are to be recharged or bank selected by BS0, BS1.
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Power for input buffers and logic circuit inside DRAM. (+3.3V)
No connection
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity.
Function
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Power for input buffers and logic circuit inside DRAM. (+3.3V)
Ground for input buffers and logic circuit inside DRAM.
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
No connection
Ground for input buffers and logic circuit inside DRAM.
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Multiplexed pins for row and column address. Row address: Ao-A10.
Column address:A0-A7.A10 is sampled during a recharge command to
determine if all banks are to be recharged or bank selected by BS0, BS1.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down rising edge of clock.
System clock used to sample inputs on the rising edge of clock.
No connection
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
Ground for input buffers and logic circuit inside DRAM.
No connection
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Separated power from VCC, to improve DQ noise immunity. (+3.3V)
Multiplexed pins for data out put and input.
Separated power from VSS, to improve DQ noise immunity.
Multiplexed pins for data out put and input.
Ground for input buffers and logic circuit inside DRAM.
1-14
3. Block diagram
TH-A30R
CLK
CKE
CS
RAS
CAS
WE
A10
A0
A9
BS0
BS1
Clock
buffer
Command
buffer
Address
buffer
Control
signal
generator
Mode
register
Column decoder
Cell array
bank #0
Row decoder
Sense amplifier
Column decoder
Cell array
bank #1
Row decoder
Sense amplifier
Refresh
counter
Column
counter
Data control
circuit
Column decoder
Cell array
bank #2
Row decoder
Sense amplifier
NOTE:
The cell array configuration is 2048 * 256 * 32
Active Low Reset. Assert for at least 5-milliseconds in the presence of
I
clock to reset the entire chip.
VCLK
XOUT
105
138
Video clock that outputs 27 MHz.
I/O
Crystal output. When the internal DCXO is used, a 13.5 MHz crystal
O
should be con-nected between this pin and the XIN pin.
XIN/bypass clk_216
139
Crystal input. When the internal DCXO is used, a 13.5 MHz crystal should
I
be con-nected between this pin and the XOUT pin. When an external
oscillator or VCXO is used, its output should be connected to this pin.
System Services
When configured for an external bypass clock, a 216 MHz clock should be
connected to this pin. The frequency of an external VCXO can be either 27
or 13.5 MHz.
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
12, 20, 111, 152, 167, 181, 196
32, 44, 55, 63, 74, 87, 98, 104
13, 21, 112, 153, 166, 180, 195, 208
31, 43, 54, 61, 72, 85, 96, 103
Pin No.
189
140
30, 80, 145, 173, 205
118, 121, 124, 127, 130
133
142, 143
134
29, 79, 146, 172, 204
132
141, 144
136
137
190-192
193, 192
206, 207, 2
3-11, 14-19, 22
23
24
25
26
27
203
50, 49
52
51
97, 86, 73, 62
46, 45, 33-42
102-99, 95-88, 84-81,
78-75, 71-64, 60-57
53
56
47, 48
116
105
106-110, 113-115
184
Type
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
O
I
I/O
I/O
I/OD
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I/O
O
O
O
I/O
I/O
I/O
I/O
1
Description
5-V supply voltage for 5V-tolerant I/O signals.
3.3-V supply voltage for I/O signals
3.3-V supply voltage for SDRAM I/O signals
3.3V Crystal interface power
1.8-V supply voltage for core logic
Analog Video DAC Power
3.3V Digital supply for 5 DACs
3.3-V Analog PLL Power
3.3V Analog Video Reference Voltage
Ground for I/O signals
Ground for core logic
Ground for SDRAM I/O signals
Digital VSS for DACs
Analog PLL Ground
Video Analog Ground
Crystal interface ground
Host chip select. Host asserts HCS to select the controller for a read or
write operation. The falling edge of this signal triggers the read or write
operation. General Purpose I/Os 41, 42, and 43, respectively.
Host chip select. Host asserts HCS to select the controller for a read or
write operation. The falling edge of this signal triggers the read or write
operation.
Host (muxed address) address bus. 3-bit address bus selects one of eight
host inter-face registers. These signals are not muxed in ATAPI master
mode.
HA[15:0] is the 16-bit (muxed address and data) bi-directional host data
bus through which the host writes data to the decoder Code FIFO. MSB of
the 32-bit word is writ-ten first. The host also reads and writes the decoder
internal registers and local SDRAM/ROM via HA[7:0]. These signals are
not muxed for ATAPI master mode.
Host Data Transfer Acknowledge.
Host interrupt. Open drain signal, must be pulled-up via 4.7k to 3.3 volts.
Driven high for 10 ns before tristate.
Host Upper Data Strobe. Host high byte data, HA[15:8], is valid when this
pin is active.
Host Lower Data Strobe. Host low byte data, HA[7:0], is valid when this pin
is active.
Read/write strobe
Address latch enable
Memory chip select.
Active LOW SDRAM Column Address Strobe.
Active LOW SDRAM Row Address Strobe.
These pins are the bytes masks corresponding to MD[7:0], [15:8], [23:16]
and [31:24]. They allow for byte reads/writes to SDRAM.
SDRAM Address
SDRAM Data
SDRAM Write Enable. Specifies transaction to SDRAM: read (=1) or
write (=0)
SDRAM Clock
SDRAM bank select
Horizontal sync. The decoder begins outputting pixel data for a new
horizontal line after the falling (active) edge of HSYNC.
Host Interrupt Request 2
General Purpose I/O 9
Video clock. Clocks out data on input. VDATA[7:0].
Clock is typically 27 MHz.
Video data bus. Byte serial CbYCrY data synchronous with VCLK. At
powerup, the decoder does not drive VDATA. During boot-up, the
decoder uses configuration parameters to drive or 3-state VDATA.
General Purpose I/Os [1:7]
Vertical sync. Bi-directional, the decoder outputs the top border of a new
field on the first HSYNC after the falling edge of VSYNC. VSYNC can
accept vertical synchroni-zation or top/bottom field notification from an
external source. (VSYNC HIGH = bot-tom field. VSYNC LOW = Top field)
Active Low Host Interrupt Pin
General Purpose I/O 36
Analog O
Analog O
Analog O
Analog O
Analog O
Analog O
Analog I
I/O
O
O
O
I/O
O
I
I
I
1
Description
Compressed data from DVD DSP. Bit 7. In parallel mode, bit 7 is the first
(earliest in time) bit in the bitstream, while bit 0 is the last bit.
Video Data Bus 2, Bit 7
Host DMA Request
General Purpose I/O 24
Compressed data from DVD DSP. Bit 6.
Video Data Bus 2, Bit 6
ATAPI Transceiver Enable
General Purpose I/O 25
Compressed data from DVD DSP. Bit 5.
Video Data Bus 2, Bit 5
Host DMA Acknowledge
General Purpose I/O 26
Compressed data from DVD DSP. Bit 4.
Video Data Bus 2, Bit 4
General Purpose I/O 27
Compressed data from DVD DSP. Bit 3.
Video Data Bus 2, Bit 3
General Purpose I/O 28
Compressed data from DVD DSP. Bit 2.
Video Data Bus 2, Bit 2
General Purpose I/O 29
Compressed data from DVD DSP. Bit 1.
Video Data Bus 2, Bit 1
General Purpose I/O 30
In serial mode, bit 0 should be used as the input, with the unused bits
either used as GPIOs or tied to ground.
Video Data Bus 2, Bit 0
General Purpose I/O 31
Data clock. The maximum frequency is 25 MHz for parallel mode, and
???? MHz for serial mode. The polarity of this signal is programmable.
Error in input data. This signal carries the error bit associated with the
channel data type (if set, the byte is corrupted).
Data enable. Assertion indicates that data on SDDATA[7:0] is valid.
The polarity of this signal is programmable.
General Purpose I/O [33]
Bitstream request. controller asserts SDREQ to indicate that the bitstream
input buffer has available space.
General Purpose I/O 32
Video DAC Bias Bits[4:0]
DAC video output format: R, V, C, or CVBS. Macrovision encoded.
DAC video output format: B, U, C, or CVBS. Macrovision encoded.
DAC video output format: G or Y. Macrovision encoded.
DAC video output format: C. Macrovision encoded.
DAC video output format: CVBS or Y. Macrovision encoded.
Video DACs Reference Resistor. Connecting to pin 136 through
a 1.18K+/- 1% resis-tor is required.
System clock that drives internal PLLs. ZiVA-5 27-MHz TTL oscillator.
(See descrip-tion of VCLK for Digital Video Output.) Also optional video
clock for internal PLLs or external encoder.
PCM Data Out. Eight channels. Serial audio samples relative to BCK
and LRCK. General Purpose I/Os [4:1]
PCM Bit Clock. BCK can be either 48 or 32 times the sampling frequency
PCM Left Clock. Identifies the channel for each sample. The polarity is
programma-ble.
Audio External Frequency clock input or output. BCK and LRCK are
derived from this clock.
PCM data out (IEC-958 format ) or compressed data out
(IEC-1937 format). General Purpose I/O [14]
PCM data input.
General Purpose I/O [15]
PCM input bit clock.
BYPASS_SYSCLK: Alternate function TBS.
General Purpose I/O [16]
PCM left/right clock.
IEC958 input bypass
General Purpose I/O [17]
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
1-18
2. Pin function (4/4)
Name
IRRX1/GPIO0
IR
IDC_CL/GPIO18
IDC
IDC_DA/GPIO19
RTS1/GPIO20
RXD1/GPIO21
TXD1/GPIO22
UART1UART2JTAG
CTS1/GPIO23
RTS2/SPI_CLK/
GPIO37
RXD2/SPI_MISO/
GPIO38
TXD2/SPI_MOSI/
GPIO39
CTS2/SPI_CS/
GPIO40
TRST
TDO
TDI/GPI0
TMS/GPI1
TCK
1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor.
Pin No.
28
160
161
162
163
164
165
185
186
187
188
197
198
199
200
201
1
Type
Description
I
IR Remote Receive. This input connects to an integrated (photo diode,
band pass, demodulator) IR receiver. General Purpose I/O 0
I/O
Serial clock signal for IDC data transfer. It should be pulled up to the
positive supply voltage, depending on the device) using an external
pull-up resistor. General Purpose I/O [18]
Serial data signal for IDC data transfer. It should be pulled up to the supply
voltage using an external pull-up resistor. General Purpose I/O [19]
O
Ready to send, UART1
General Purpose I/O [20]
I
Receive data, UART1
General Purpose I/O [21]
O
Transmit data, UART1
General Purpose I/O [22]
I
Clear to send, UART1
General Purpose I/O [23]
O
Ready to send, UART2
Serial Peripheral Interface Clock
General Purpose I/O [37]
I
Receive data, UART2
Serial Peripheral Interface - Master Input/Slave Output
General Purpose I/O [38]
O
Transmit data, UART2
Serial Peripheral Interface - Master Output/Slave Input
General Purpose I/O [39]
I
Clear to send, UART2
Serial Peripheral Interface ????
General Purpose I/O [40]
I
Test reset. BST reset - resets the TAP controller.
This signal must be pulled low.
O
Test data Out. BST serial data output.
I
Test data In. BST serial data chain input.
General Purpose Input pin 0.
I
Test mode select. Controls state of test access port (TAP) controller.
General Purpose Input pin 1.
I
Test clock. Boundary scan test (BST) serial data clock.
To provide memory addresses. During Sector-Erase AMS-A11 address lines will
select the sector. During Block-Erase AMS-A15 address lines will select the block.
To output data during Read cycles and receive input data during Write cycles. Data is
internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is
high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
Unconnected pins.
1-23
TH-A30R
3
AK4355 (U6) : DAC
1.Pin layout2.Block diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DZF
LOUT1+
LOUT1-
ROUT1+
ROUT1-
LOUT2+
LOUT2-
ROUT2+
ROUT2-
LOUT3+
LOUT3-
ROUT3+
ROUT3-
SCF
SCF
SCF
SCF
SCFDAC
SCFDAC
3.Pin function
Pin No. SymbolI/OFunction
1VREFIPositive Voltage Reference Input Pin
2DZFOZ
3PDNIPower-Down Mode Pin
When at “L”, the AK4355 is in the power-down mode and is held in reset.
The AK4355 should always be reset upon power-up.
An external TTL clock should be input on this pin.
Audio Serial Data Clock Pin
DAC1 Audio Serial Data Input Pin
DAC2 Audio Serial Data Input Pin
DAC3 Audio Serial Data Input Pin
L/R Clock Pin
hip Select Pin
Control Clock Pin
Control Data Input Pin
igital Power Supply Pin
igital Ground Pin
DAC3 Rch Negative Analog Output Pin
DAC3 Rch Positive Analog Output Pin
DAC3 Lch Negative Analog Output Pin
DAC3 Lch Positive Analog Output Pin
DAC2 Rch Negative Analog Output Pin
DAC2 Rch Positive Analog Output Pin
DAC2 Lch Negative Analog Output Pin
DAC2 Lch Positive Analog Output Pin
DAC1 Rch Negative Analog Output Pin
DAC1 Rch Positive Analog Output Pin
DAC1 Lch Negative Analog Output Pin
DAC1 Lch Positive Analog Output Pin
Analog Ground Pin
Analog Power Supply Pin
DAC
DAC
DAC
DAC
DATT
DATT
DATT
DATT
DATT
DATT
Audio
I/F
Control
Register
MCLK
LRCK
BICK
CSN
CCLK
CDTI
SDTI1
SDTI2
SDTI
1-24
M62463FP (U11) : Surround decoder
1. Pin layout
RLC3
RLC7
RLC4
RLC1
RLC2
RLC5
PSC4
PSC1
PSC5
PSC2
PSC6
PSC3
48
47
46
45
44
43
42
41
40
39
38
37
DBC3
DBC2
36
35
DBC1
BNR IN
34
33
TH-A30R
49
RLC8
50
RLC6
LT
RT
LIN
RIN
AVcc
VREF
IREF
NGC3
NGC2
NGC1
51
52
53
54
55
56
57
58
59
60
61
62
63
64
LBPF2
LBPF1
RBPF2
RBPF1
2. Block diagram
1 2 3 4 5 6 7 8 9
LOUT
ROUT
CVOLOUT
COUT
CVOLIN
SOUT
SVOLIN
SVOLOUT
10
CMC
11
AGND
VREFD
12
13
DVdd
MICIN
14
15
SCK
DATA
16
REQ
32
FBIN
31
LPF2 OUT
30
LPF2 IN2
29
LOF2 IN1
28
DAINT OUT
27
DAINT IN
26
DACONT
25
ADCONT
24
ADINT OUT
23
ADINT IN
22
LPF1 OUT
21
LPF1 IN2
20
LPF1 IN1
19
DSEL OUT
18
MICOUT
17
DVss
LIN
RIN
MICIN
57
58
12
L+R
2
SW6
L-R
1
2
NOISE
SEQUENCER
INPUT
BALANCE
SW4
1
2
3
4
MICVOL
MICOUT
ADAPTICVE
MATRIX
SELECTOR
S'
Digital Delay
10Kbit SRAM
LPF
A/D
SW5
Logic
F.B.VOL
CENTER
MODE
CONTROL
WIDE
NORMAL
PHANTOM
OFF
D/A
LPF
L
R
C
Modified BNR
PROLOGIC
PROLOGIC
SW3
BY-PASS
SPACE
SURROUND
SPACE
SURROUND
+
MUTE
BY-PASS
+/-
MUTE
MASTER
VOLUME
1
2
MASTER
VOLUME
MCU
Interface
DATA SCK REQ
SW1
2
3
2
3
SW2
161514333132201918
1
LOUT
1
4
1
ROUT
2
4
5
4
CVOLOUT
3
SVOLOUT
8
7
6
1-25
TH-A30R
SP3721A (RU1) : DVD anlog front end chip
1.Pin layout
64-49
16-1
17-32
33-48
2.Pin function
Pin No.
1,2
3,4
5-8
9
10
11-14
15,16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51,52
53,54
55
56
57
58
59,60
61,62
63
64
Symblo
DVDRFP,VDVDRFN
PD1,PD2
A2,B2,C2,D2
CP
CN
A,B,C,D
E,F
CDTE
VCI2
NC
VNB
DVDPD
DVDLD
CDPD
CDLD
LDON#
VC
VCI
VPB
MIRR
MP
MB
FDCHG#
MLPF
MEVO
MIN
PI
DFT
TPH
MEV
MEI
TE
FE
CE
LCN
LCP
SCLK
SDATA
SDEN
HOLD1
VNA
FNP,FNN
DIP,DIN
RX
BYP
SIGO
VPA
AIP,AIN
ATOP/ATON
CDRF
CDRFDC
CD Tracking
Reference Voltage Input
No Connct
Ground
APC Input
I
APC ouput
APC Input
I
APC output
APC Output On/Off
I
Reference Voltage output
Reference Voltage Input
Power
Mirror Detect Output
MIRR signal Peak hold pin
MIRR signal Bottom hold pin
Low Impedance Enalle
I
MIRR signal LPF pin
SIGO Bottom Envelope Output
RF signal Input for Mirror
I
Pull-in Signal Output
Defect Output
PI Top Hold pin
Sigo Bottom Envelope pin
Mirror Envelope Input
I
Tracking Error Signal Output
Focusing Error Signal Output
Center Error Signal Output
Center Error LPF pin
Center Error LPF pin
Serial Clock
I
Serial Data
Serial Data Enable
I
Hold Control
I
Ground
Differential Normal Output
Analog inputs for RF Single Buffer
I
Reference Resistor Input
Single Ended Normal Output
Power
AGC Amplifier Inputs
I
Differential Attenuator Output
RF Signal Input
I
CD RF signal Output
1-26
TH-A30R
BA4560 (AIC2, IC5, IC6, IC7, U1, U3, U5, U9, U13)
1.Pin layout
OUT1
– IN1
+ IN1
V
1
2
1ch
+
–
3
EE
4
2ch
+
V
CC
8
OUT2
7
– IN2
6
–
+ IN2
5
74LVT573 (U10, U11, U12) : Latch
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vcc
O0
O1
O2
O3
O4
O5
O6
O7
LE
Symbol
D0-D7
LE
OE
O0-O7
Function
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
: Dual op amp.
3. Truth table1. Pin layout2. Pin function
H:HIGH Voltage Level
L:LOW Voltage Level
Z:High Impedance
X:Immaterial
O0:Previous O0 before HIGH to LOW transition of Latch Enable
InputsOutputs
LE
X
H
H
L
OE
H
L
L
L
Dn
On
X
L
H
X
Z
L
H
O0
FAN8082 (MU10) : DC motor driver
1.Pin layout
V
GND
1
V
O1
2
V
CTL
3
V
IN1
4
3. Pin function
12V
3V
4V
5V
6SV
7PV
8V
GND
O1
CTL
IN1
IN2
CC
CC
O2
O2
8
PV
CC
7
SV
CC
5
V
IN2
6
I/O
OOutput 1
IMotor speed control
IInput 1
IInput 2
-Supply voltage (Signal)
-Supply voltage (Power)
OOutput 2
Ground
2. Block diagram
GND
V
V
CTL
V
O1
IN1
1
2
DRIVER OUT
PRE DRIVER
3
4
TSD
LOGIC SWITCH
BIAS
8
V
O2
7
PV
CC
6
SV
CC
5
V
IN2
FunctionPin No.Symbol
1-27
TH-A30R
74HCT245 (U15) : Transceiver
1.Pin layout2.Truth table
ENABLE
Vcc G B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
Control
G
LL
LH
H
H = HIGH Level
L = LOW Level
X = Irrelevant
Inputs
DIR245
X
Operation
B data to A bus
A data to B bus
isolation
M5705 (DU3) : DVD-ROM controller
1.Block diagram
M5703/M5707
RF
Amp
M
Motor
Driver
Data
Separator
Digital
Servo
DVD-DSP
CD-DSP
4M DRAM
RAM
Arbiter
Target
Search
ATAPI
&
MPEG
I/F
C3 ECC
EDC
MCU
ROM
PC
MPEG
DEC.
1-28
BA7612F (JVIC1, JVIC2, JVIC3) : Video signal switcher
TH-A30R
1. Block diagram
1
IN1
CTLA
CTLB
IN2
MUTE
2
LOGIC
3
4
8
V
OUT
75Ω6dB
7
CC
V
6
IN3
5
GND
2. Truth table
CTL ACTL B
L (OPEN)
L (OPEN)
HIN3
HHMUTE
TDA7440D (U2) : Audio processor
1. Terminal layout2. Block diagram
4
RIN3
RIN2
RIN1
MUXO-L
IN(L)
MUXO-R
IN(R)
BIN(R)
BOUT(R)
BIN(L)
1
2
3
4
LIN1
5
LIN2VS
6
LIN3
LIN4
7
8
9
10
11
12
13
14
28
RIN4
LOUT
27
ROUT
26
25
AGND
24
CREF
23
SDA
22
SCL
21
DGND
20
TRE(R)
19
18
TRE(L)
PS1
17
LP
16
BOUT(L)
15
LIN1
LIN2
LIN3
LIN4
RIN1
RIN2
RIN3
RIN4
100K
5
100K
6
100K
7
100K
3
100K
2
100K
1
100K
28
100K
L (OPEN)
HIN2
L (OPEN)
MUXO-L IN(L)
89181415
G
0/30dB
2dB STEP
G
INPUT MULTIPLEXER
+ GAIN
VOLUME
VOLUME
101119121323
MUXO-R IN(R)
OUT
IN1
TRE(L)
TREBLE
I2CBUS DECODER + LATCHES
TREBLE
TRE(R)
BIN(L)
BASS
BASS
R
B
R
B
BOUT(L)
BOUT(R)BIN(R)
SPKR ATT
LEFT
SPKR ATT
RIGHT
V
REF
SUPPLY
CREF
27
LOUT
21
SCL
22
SDA
20
DGND
26
ROUT
24
VS
25
AGND
W29EE512 (DU5) : Flash memory
1. Pin layout
A12
4 3 2 1 32 31 30
5
A7
6
A6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
DQ0
14 15 16 17 18 19 20
A15NCNC
DQ1
DQ2
GND
VccWENC
DQ3
DQ4
DQ5
29
28
27
26
25
24
23
22
21
DQ6
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
2. Block diagram
V
DD
Vss
CS
OE
WE
A0
A15
CONTROL
DECODER
OUTPUT
BUFFER
CORE
ARRY
DQ0
DQ7
3. Pin function
Symbol
A0~A15
DQ0~DQ7
CE
OE
WE
Vcc
GND
NC
Function
Address input
Data I/O
Chip enable
Output enable
Write enable
Power
Ground
No connect
1-29
TH-A30R
TDA7449L (U7, U12) : Audio processor
1.Pin layout2.Block diagram
CREF
PGND
ROUT
LOUT
R_IN2
R_IN1
L_IN1
L_IN2
MUXOUT(L)10MUXOUT(R)
1
2
V
S
3
4
5
6
7
8
9N.C.
SDA20
SCL
19
DIG_GND
18
N.C.
17
N.C.
16
N.C.
15
N.C.
14
N.C.
13
12
11
L-IN1
L-IN2
R-IN1
R-IN2
8
100K
9
100K
7
100K
6
100K
G
0/30dB
2dB STEP
G
INPUT MULTIPLEXER
+ GAIN
MUXOUTL
10
VOLUME
I2CBUS DECODER + LATCHES
VOLUME
111
MUXOUTR
SPKR ATT
LEFT
SPKR ATT
RIGHT
V
REF
SUPPLY
CREF
5
19
20
18
4
2
3
LOUT
SCL
SDA
DIG_GND
ROUT
V
S
AGND
D98AU868
TL3472 (RU2) : Op. amp.
1.Pin layout
V
CC±
1OUT
1IN±
1IN+
/GND
1
2
3
4
8
7
6
5
V
CC+
2OUT
2IN±
2IN+
1-30
< MEMO >
TH-A30R
1-31
TH-A30R
VICTOR COMPANY OF JAPAN, LIMITED
AUDIO & COMMUNICATION BUSINESS DIVISION
PERSONAL & MOBILE NETWORK BUSINESS UNIT. 10-1,1chome,Ohwatari-machi,Maebashi-city,371-8543,Japan
(No.21163)
Printed in Japan
200212
SCHEMATIC DIAGRAMS
DVD DIGITAL CINEMA SYSTEM
TH-A30R
STAND BY/ON
AUDIO
TV/VIDEO
VCR
TV
TV CHANNE L
DISPLAY
STEP
AUDIO/
SUBTITL E
TV VOLUME
FM MOD E
DVD FM/AM AUX
TUNER PRESET
DOWNUP
REW
VCR CHANNE L
TUNING
B.SEARCHF.SEARCH
ENTER
VOLUM E
TOP MENU
MENU
RETURN
RM-STHA30R
DVD CI NEMA SYST E M
TH-A30R
Area suffix
CD-ROM No.SML200212
SP-XSA30 2
RDS
DISPLAY
VCR
CONT ROL
FF
MUTING
STANDBY
STANDBY/ON
AUDIO/FM MODE
DSP
VOLUMESOURCE
DVD DIGITAL CINEMA SYSTEM TH-A30R
SP-XA30 3
DIGITAL
SURROUN D
DIGITAL
XV-THA30RSP-WA30
B -------------------------- U.K.
E ------ Continental Europe
EN ------- Northern Europe
EV --------- Eastern Europe
EE ---- Russian Federation
Contents
Block diagrams
Standard schematic diagrams
Printed circuit boards
COPYRIGHT 2002 VICTOR COMPANY OF JAPAN, LTD.
2-1
2-3
2-8~12
No.21163SCH
Dec. 2002
TH-A30R
In regard with component parts appearing on the silk-screen pr inted side (par ts side) of
the PWB diagrams, the parts that are printed over with black such as the resistor ( ),
diode ( ) and ICP ( ) or identified by the " " mark nearby are critical for safety.
(This regulation does not correspond to J and C version.)
Block diagrams
r
Main section
5
S_VIDEO_C
VW2
S_VIDEO_Y
VIDEO_COMPO
JVIC1
VIDEO SW
JVIC2
VIDEO SW
JVIC3
VIDEO SW
S-VIDEO
SCART JACK
VIDEO
TH-A30R
VFD
UIC1
MICOM
TUNER
V Signal
Front
FCW2
J1
CW8
4
R
U11
PROLOGIC IC
J21
MUX-OUT RIN R
DVD PACK
(Refer to the following page
"DVD mecha block section")
3
J14
J3
DAC
D3
D2
D1
U6
FL
FR
C
W
RL
RR
2
LPF
(1/2)
U1
LPF
(2/2)
LPF
(1/2)
U5
LPF
AUX L
TUN L
AUX R
TUN R
FL
FUNCTION IC
FR
MUX-OUT LIN L
C
W
U2
U12
FUNCITON IC
U13
J6
IC5
POWER
AMP.
CW5
IC7
POWER
AMP.
(2/2)
U9
L
AUX1
6
(35W)
6
(35W)
6
(35W)
4
(110W)
Front L-ch
Front R-ch
Center
Sub Woofe
LPF
RL
(1/2)
U3
1
LPF
RR
U7
FUNCTION IC
J5
CW6
(2/2)
DSP
Main
IC6
POWER
AMP.
ABCDEFG
6
(35W)
6
(35W)
Rear L-ch
Rear R-ch
2-1
TH-A30RTH-A30R
DVD mecha block section
RU1 RF AMP SP3721
RF AGC
& EQ
CONTROL
DECK ASS’Y
FOCUS OK
5
DETECT DEFECT
DETECT MIRROR
GEN
PICK UP
& I/V AMP
FOCUS
SERVO
DISC
MOTOR
FEED
MOTOR
LOOP
4
DISC
MOTOR
DRIVER
ACTUATOR
MOTOR
DRIVER
MICOM DATA INTERFACE
LOGIC DECODER
TRACKING
ERROR
I/V AMP
APC.LASER
CONTROL
&LPC
TRACKING
SERVO
LOOP
HARDWARE
COMPARATOR
LOGIC
EFM
RF&FOCUS
ERROR
I/V AMP
SPINDLE
SERVO LPF
MICOM
M6759
DATA
SEPARATOR
DIGITAL
SERVO
DU3
DVD ROM CONTROLLER
M5701/ M5705
BCA
DVD-D SP
CD-DSP
4M DRAM
416C256
RAM
ARBITER
TARGET
SEARCH
Parallel/Serial
DVD Interface
ATAPI
&
MPEG
I/F
C3 ECC
EDP
MCU I/F
3
HOST
MEMORY
SST39VF800A
Track Buffer
Processor
Audio
2
Input Unit
Decryption
A/V CORE
SDRAM CONTROLLER
--------ZIVA
Graphics
Engines
Interlace/
Progressive
Video
Encoder
Digital Video
Five 10-bit
Video
DACs
Analog
Video
Output
64M SDRAM
W986432DH-7
BUFFER
SIGNAL
KSA812
SWITCHING
BUFFER
BA7612
(Refer to "Main section.")
VIDEO OUT
System Control Bus
Audio
Output
AMP PARTS
System Control Bus
SPARC
Microprocessor
Audio
Output
Phase
1
ASYNC BUS/IR/GPIO/SPI/UART1&2/ATAPI/IDC
Lock
Loop
JTAG
Interface
U8
MPEG DECODER
ZIVA5
(Refer to "Main section.")
Parallel/Serial
DVD Interface
13.5MHZ Crystal
ATAPI 40PIN
2-2
HABCDEFG
Standard schematic diagrams
Main section /Power supply section
5
4
To Tuner Pack
To J7
Sheet 2/5
To J2
Sheet 2/5
TH-A30R
To DJ6
Sheet 4/5
3
2
1
SHEET
NUMBER
CIRCUIT DESCRIPTION
Main /Power supply
1/5
FL display & System control /DSP
2/5
Video signal output
3/5
DVD loader
4/5
DVD MPEG
5/5
To J6 Sheet 2/5
To J5
Sheet 2/5
Tuner signal
To FCW1
Sheet 2/5
Front signal
Center signal
Rear signal
Parts are safety assurance parts.
When replacing those parts, make
sure to use the specified parts.
SHEET 1/5
ABCDEFG
2-3
TH-A30RTH-A30R
FL display & System control section / DSP section
To J14
Sheet 5/5
To FCW1-1
Sheet 1/5
Front signalCenter signalRear signalTuner signalDigital audio signal