JVC TH-A25 Schematics
SCHEMATIC DIAGRAMS
DVD DIGITAL THEATER SYSTEM
TH-A25
CD-ROM No.SML200403
SOUND
DVD DIGITAL CINEMA
SYSTEM TH-A
STANDBY
STANDBY/ON
Since the printed circuit board of DVD was changed, the schematic diagram
and printed circuit boad which were changed are published.
25
SOURCE
VOLUME
Area suffix
J ----------------------------- U.S.A.
C -------------------------- Canada
Contents
Standard schematic diagrams ---------------------------------- 2-1
Printed circuit board ----------------------------------------------- 2-5
COPYRIGHT 2004 VICTOR COMPANY OF JAPAN, LTD.
No.MB141BSCH
2004/3
In regard with component parts appearing on the silk-screen printed side (parts side) of
the PWB diagrams, the parts that are printed over with black such as the resistor ( ),
diode ( ) and ICP ( ) or identified by the " " mark nearby are critical for safety.
(This regulation does not correspond to J and C version.)
8
Standard schematic diagrams
SDRAM (MIC7)
VCC33
PIN 1 PIN 3 PIN 9 PIN 14 PIN 27 PIN 43 PIN 49
BC2
BC1
0.1U
SBAD
XFLAG0
XFLAG1
XFLAG2
XFLAG3
RFO
TESTAD
DA
RFRP
DIP
DIN
TRACK
FOCUS
SLEGP
SLEGN
SPINDLE
MIRR
TEI
FEI
CEI
SPDON
SFGIN
1
2
3
4 5
EGND
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
DSCK
DOE#
CS0#
RAS0#
CAS#
DWE#
DQM
RAS1#
RAS2#
BEFR_OP2
ATR_OP2
MIC6
S0
S1
S2
GND SDA
MR67 33
MR69 33
MR71 33
MR72 33
MR73 33
MR76 33
MR77 33
MR78 33
0.1U
MIRR2
24C02A
TP1
FLAG0
TP3
FLAG2
TP5
RFO
TP7
DA
TP9
DIP
TP11
STRACK
TP13
SSLEGP
TP18
SSPINDLE
TP20
TEI
TP22
CEI
TP24
FGIN
VCC33
VCC
WC
SCL
BC3
0.1U
SPINDLE3
SVREF152
8
7
6
23
24
25
26
29
30
31
32
33
34
22
35
38
37
19
18
17
16
15
39
20
21
36
40
BC4
0.1U
TP32
SBAD
TP2
FLAG1
TP4
FLAG3
TP6
TESTAD
TP8
RFRP
TP10
DIN
TP12
SFOCUS
TP14
SSLEGN
TP19
MIRR
TP21
FEI
TP23
XSPDON
MR22 0
MR26 0
MR27 R
MR28 R
MR30 33K
OPEN
OPEN3
SPINDLE
FOCUS
FOCUS3
SLEGN
SLEGN3
TRACK
TRACK3
SVREF15
SCSJ
SCSJ2
SDATA
SDATA2
SCLK
SCLK2
BC8
MR49
0.1U
1K
EGND
MIC8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
BA0
BA1
NC
NC
4Mx16 SDRAM (9ns)
VCCQ
VCCQ
VCCQ
VCCQ
VSSQ
VSSQ
VSSQ
VSSQ
DECOUPLING CAPACITORS
BC6
BC5
0.1U
0.1U
MIRRASVREF15
RFRP
TESTAD
MC24
1U
MR32 0(2012)
PLLGND
RFGND
MR25 0
MC32
0.015U
MC36
0.22U
MC39
33P
MR50
1K
RFGND
MR55 33
MR56 33
HSYNC4
VSYNC4
DB0
2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VCC
VCC
VCC
VSS
VSS
VSS
DB1
4
DB2
5
DB3
7
DB4
8
DB5
10
DB6
11
DB7
13
DB8
42
DB9
44
DB10
45
DB11
47
DB12
48
DB13
50
DB14
51
DB15
53
VCC33
1
14
27
3
9
43
49
6
12
46
52
28
41
54
EGND
MC40
33P
EGND
MC33
C
EGND
MGND
MC28
0.1U
MIRRA
A5V
BC7
0.1U
TR1
TR2
MC41
33P
AUX0
AUX1
RESET#4
MC37
560P
AUX4
AUX5
AUX6
AUX7
L25 CIC21
L23 L
C30 C
MC29
47P
MC34
560P
OUTSW3
RS232_DET
MOCTL2
VCC33
A5V
EGND
RS232 CONNECTOR 2.54MM
RF33V
MR29 R
MR31 1.2K
MR33 10K
MR34 5.1K
MC30
0.1U
DA
MC35
0.015U
MC38
0.1U
HOMESW3
MR53
RESET#
MR89 100
MR59 4.7K(OPEN)
RR1 4.7K(SD)
RR2 4.7K(SD)
STXD
RS232_DET
SRXD
SBAD2
FEI2
CEI2
TEI2
DIP2
RFO2
DIN2
SVREF212
MC17
MC18
0.1U
0.1U
RFGND
MC22
C
MC23
C
MC25
0.047U
MC27
560P
MC31
0.1U
MR38 6.8K
MR39 6.8K
MR40 6.8K
MR41 R
MR42 5.1K
MR43 6.8K
MR44 6.8K
SFGIN3
SPHOI
MR45 33
MR46 33
MR47 33
SDEFCT2
SLDC2
SPDON3
INSW3
CLOSE3
DVD/CD2
FR3
0
GPIO2
GPIO1
GPIO0
HSYNC
MC47
0.1U
VCC33
EGND
MC45
24P
EGND
SBAD
FEI
CEI
TEI
DIP
RFO
DIN
SVREF21
MC19
0.1U
PLL33V
MC26
0.1U
TR1
TR2
SLEGP
SFGIN
1
XSCSJ
XSDATA
XSCLK
DEFCT
SLDC
SPDON
FR
1
1
1
EGND
1
2
GNQ
X1 33.33MHZ(DA)
MR74 100K
X2
27MHz
MC20
C
V
JJ1(SD)
SERVO MCU
1
2
DEBUG
3
HEADER
4
5
RFGND
MC8
4700P
MC9
C
MC11
C
MC13
4700P
MR19 68K
MR21 20K
MC21
6800P
157
AVSS_DS
158
AVSS_PL
159
XSPDOFTR1
160
XSFDO
161
XSFTROPI
162
AVDD3_PL
163
XSPLLFTR1
164
XSPLLFTR2
165
XSVREF0
166
XSAWRC
167
AVSS_DA
168
XSRFRPCTR
169
XSTRAY
170
AVDD3_DA
171
XSSPINDLE
172
XSFOCUS
173
XSSLEGP
174
XSSLEGN
175
XSTRACK
176
XSTESTDA
177
XSFGIN
178
XSPHOI
179
SXCSJ
180
XSDATA
181
XSCLK
182
XSDFCT
183
XSLDC
184
XSSPDON
185
VD33
186
VS33
187
XGPIO[9]
188
XGPIO[8]
189
XGPIO[7]
190
XGPIO[6]
191
XGPIO[5]
192
XGPIO[4]
193
XGPIO[3]
194
XGPIO[2]
195
XGPIO[1]
196
XGPIO[0]
197
VSS
198
VDD
199
AUX0
200
AUX1
201
AUX2/ HSYNC
202
AUX3/ VSYNC
203
AUX4
204
AUX5
205
AUX6
206
AUX7
207
RESET
208
VS33
4
3
MR70
MR75
33(OPEN)
100(DVI)
MR65
MC44
27P
PLL3(pin124)
CLK SOURCE
CRSTAL OSC
1
DCLK INPUT
0
PLL2
PLL1
PLL0
MULTI
139
XSTEXI
Frequency
114.75
4.5
5
bypass
4
4.25
4.75
5.5
6
137
138
VSS
VDD
121.5
NA
135
27
NA
101.25
108
121.5
114.75
NA
128.25
94.5
148.5
108
162
3
DRV
TP16
TP15
SRXD
STXD
XFLAG2
XFLAG1
XFLAG3
XFLAG0
129
130
131
132
133
134
135
136
XSLG
XSIP2
XSIP1
XSWBL
XSFLAG[0]
XSFLAG[1]
XSFLAG[2]
XSFLAG[3]
ML4 CIM10
MCLKMCL
TP17
MR60 33
UDAC1
TSD1
TSD3
TBCK
TWS
TSD2
TSD0
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VS33
XSWBLCLK
VS33
VD33
TSD2
TSD3
TBCK
MCLK
SPDIFIN
TWS/SEL_PLL2
TSD0/SEL_PLL0
TSD1/SEL_PLL1
SPDIF/SEL_PLL3
TWS
0
0
0
0
1
1
1
1
MC4
1000P
MC6
1000P
MR10 3.3K
MR11 3.3K
MR16 3.3K
MR17 3.3K
152
153
154
155
156
XSIPIN
XSRFIP
XSRFIN
XSDSSLV
TSD1
0
0
1
1
0
0
1
1
MC3
1000P
MC5
1000P
MR18 10K
MC10 10U/16V
SVREF21
SVREF09
SVREF15
148
149
150
151
XSIREF
AVDD3_DS
XSVREF[21]
XSVREF[09]
XSVREF[15]
TSD0
DEFAULT S-CHIP DEFAULT S-CHIP
0
4.25
1
reserved
bypass
0
1
3.75
4.5
0
reserved
1
3.5
0
1
4
MC7
0.1U
MC12
1U
MC14
1U
RFRP
TESTAD
140
141
142
143
144
145
146
147
XSFEI
XSTEI
XSCEI
XSSBAD
XSRFRP
AVSS_AD
AVDD3_AD
XSTESTAD
ES66x8
VD33
XIN
XOUT
DCLK
DMA0
DMA1
DMA2
DMA3
VS33
VD33
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
DMA10
VS33
VD33
DMA11
DCAS
DCS0
DCS1
DRAS0
DBANK0/ DRAS1
VSS
VDD
DBANK1/ DRAS2
DCKE/DOE/TDMTSC
DWE
DB0
DB1
DB2
VS33
VD33
DB3
DB4
DB5
DB6
DB7
BC14
0.1U
DB15
DB3
DB5
DB7
DB4
DB6
DB15
DB14
BC15
0.1U
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051
33(DA)
DCLK_DVI
XOUT
DCLK
XIN
DMA5
DMA2
DMA3
DMA0
DMA1
DMA6
DMA4
4.7K
MR94
RN1 10x4
1 8
2 7
3 6
4 5
1 8
2 7
3 6
MA1
MA6
MA4
MA0
MA2
MA5
MA3
CAS#
RAS0#
CS0#
DMA7
DMA11
DMA8
DMA10
DMA9
10x4
RN3
RN2 10x4
1 8
2 7
3 6
4 5
4 5
MA10
MA11
MA7
MA8
MA9
DB1
DB2
DB0
DWE#
RAS1#
RAS2#
DOE#
VCC33
CDAC1
114
YUV0/UDAC
DB14
MR4
MR12
YDAC1
113
YUV2/CDAC
VS33
YUV5/YDAC
VD33
GNDV
112
VS33_DA
DB13
DB13
BC16
0.1U
1.2K(OPEN)
1.2K
VCC33V
111
DB12
EGND
VDAC1
110
VD33_DA
DB12
DB11
MR5
MR13
FDAC1
109
YUV7/FDAC
YUV6/VDAC
DB11
DB10
DB10
1.2K(OPEN)
1.2K
EGND
COMP
DATA1
RSET
106
107
108
YUV4/RSET
YUV3/COMP
RBCK/TDMCLK
DB9
DB8
MR66 33
DB8
DB9
DSCK
BC17
0.1U
VCC33VCC33 VCC33
VCC33
MR6
MR7
1.2K(OPEN)
MR91 0(OPEN)
1.2K
MR14
MR15
RSET 4
DATA1 4
MC15 0.1U
DATA3 4
VS33_PL2
MIC4
105
VS33_PL
YUV1/VREF
VD33_PLL
RWS/TDMFS
RSD/TDMDR
LD7
LD6
LD5
LD4
VD33
VS33
LD3
LD2
LD1
LD0
LOE
LWRLL
LCS3
VDD
VSS
LCS2
LCS1
LCS0
LA0
LA1
LA2
VD33
VS33
LA3
LA4
LA5
LA6
LA7
LA8
VDD
VSS
LA9
LA10
LA11
LA12
LA13
LA14
LA15
VD33
VS33
LA16
LA17
LA18
LA19
LA20
LA21
DQM
VD33
DSCK
VS33
52
MC50
27P
BC18
0.1U
1.2K(OPEN)
1.2K
1.2K
MR84
EGNDEGNDEGND
UDAC
CDAC
YDAC
VDAC
5DAC
MR20 390
MC16 0.1U
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
EGND
BC19
0.1U
VCC20
SPDIF
TBCK 4
MCLK 4
MCLK_DIR
TSD3 4
TSD2 4
TSD1 4
TSD0 4
TWS 4
BC9
0.1U
BC20
0.1U
VCC33
UDAC 4
CDAC 4
YDAC 4
VDAC 4
5DAC 4
R5 R
R6 R
R4 R
VD33_PL1
TDMFS
TDMCLK
TDMDR
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
LOE#
WRLL#
LCS3#
LCS2#
LCS1#
LCS0
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA20
LA21
DQM
BC10
0.1U
BC21
0.1U
MR61 100K(OPEN)
MQ1
5
VCC
TC7S04F(OPEN)
VCC33V
C2
0.1U
VGND
TWS 4
TBCK 4
RSD 4
ML2
CIC21
VCC20
TP49
BC11
0.1U
BC22
0.1U
RXD
RXD4
DQ15/A_1
MIC5
CLK/CE1
VCC
GND
A5V
BYTE
GND
DQ14
DQ13
DQ12
DQ11
DQ10
GND
D0
D1
D2
D3
D4
D5
D6
D7
ACK4
ML1
CIC21
Q2
1
R1103(OPEN)
2 3
VCC33
48
A16
47
46
45
44
DQ7
43
42
DQ6
41
40
DQ5
39
38
DQ4
37
VCC
36
35
DQ3
34
33
DQ2
32
DQ9
31
DQ1
30
DQ8
29
DQ0
28
G
27
26
E
EGND
LD0
13
LD1
14
LD2
15
LD3
17
LD4
18
LD5
19
LD6
20
LD7
21
A5V
32
16
EGND
34
GNDOUT
2
IN A
1
NC
RESET#4
INSTALL
R51, R54
R48, R52
WRLL#
LA18
LA19
LA20
LCS2#
EGND
C1
100U/6.3V
VCC33
L1CIC21
L2
CIC21
MC42
0.047U(OPEN)
VCC33
12
12
EGND
RESET#
MR90 100
TYPE
REMOVE
EPROM
R48, R52
FLASH
R51, R54
MR48 OPEN
MR51 0(EM)
MR52 OPEN
MR54 0(EM)
RESET#4
MR57 0(EM)
MR58 OPEN
SPDIF_IN
LA16
LA15
LA14
LA13
LA12
LA11
LA10
LA9
LA20
WRLL#
LA19
LA18
LA8
LA7
LA5
LA4
LA3
LA2
RESET#
WRLL#
EGND
LA0
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LCS3#
LOE#
SPDIF_IN 4
MC48
0.1U
RESET#4
MIC3
1
A15
2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
9
NC
10
NC
11
W
12
RP
13
VPP
14
DU/WP
15
NC
16
NC
17
A17
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24 25
A1 A0
A29L160
12
A0
11
A1
10
A2
9
A3
8
A4
7
A5
6
A6
5
A7
27
A8
26
A9
23
A10
25
A11
4
A12
28
A13
29
A14
3
A15
2
A16
30
A17
31
A18
1
A19
22
CE
24
OE
27C040/080-90(EM)
MIC7
1 4
RESET
2 3
WE ADDR/CE1
ROM EMULATOR SOCKET
AUX5
ACK
AUX7
DCLK_DVI
SPDIF
MR95
10K(OPEN)
47U/6.3V(OPEN)
EGND
LA17
LA0
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0LA6
LOE#
LCS3#
LA1
LA21
PC4
MR2 100
MR68 100
MR96
0
MC2
0.1U
SPSYNC
TWS4
SPCLK
TBCK4
SPDAT
RSD4
MIC1
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
1
DIR
19
OE
20
GND
+5V
74HCT245
ACK : AUX6
TXD : AUX7
RXD : AUX4
STB : AUX5
MCLK LINE SHIELD
ANASYNC
SPCLK
ANACLK
SPDAT
ANDAT
SELECT0
SELECT1
DVD DRIVE EXPANSION
LD0
LD1
LD2
LD3
LCS1#
MR1 1K
18
B1
17
TP38
B2
B3
B4
B5
B6
B7
B8
MR3 1K
16
15
MR8 100
14
13
12
MR9 33(OPEN)
11
MC1
47P(OPEN)
10
EGND
EGND
MCLK_DIR SPMCLK
LD4
LD5 EMPH
LD6
LD7
VCC33
SELECT0
HIGH
LOW
EGND
18
16
14
12
20
10
EGND
U17
2
1A
1Y
3
1B
5
2A
2Y
6
2B
11
3Y
3A
10
3B
14
4A
4Y
13
4B
1
A/B
VCC33
15
G
EGND
74LVX157
AUDIO
SPDIF
ANALOG
OPIC3
3
Q1
D1
4
Q2
D2
7
Q3
D3
8
Q4
D4
13
Q5
D5
14
Q6
D6
17
Q7
D7
18
Q8
D8
11
CLK
PL33
1 10
OE
GND
74LVX374
9
7
5
3
MR92
2.7K(OPEN)
OPIC2
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
PL33
GND
4
7
9
12
16
8
EGND
2
5
6
9
12
15
16
19
20
R40
33(OPEN)
74LVX244
R105 33
R106 33
R107 33
VCC33
SELECT0
SELECT1
CCLK
AUX4
STB
AUX6
TXD
MR93
2.7K(OPEN)
2
1A1
4
1A2
6
1A3
8
1A4
11
2A1
13
2A2
15
2A3
17
2A4
1
1G
19
2G
RWS
33(OPEN)
EGND
TDMCLK
R57
VCC33
STB 4
TXD 4
DVICLK 4
OPT_OUT 4
TDMDR
ERR
SELECT0
LCS1#
TDMFSSPSYNC
TDMCLK
TDMDR
EAUX40
TP4
4-PIN EXTENSION FOR ROM EMULATOR INTERFACE
A5V
BC12
0.1U
BC23
0.1U
EGND
EGND
BC13
0.1U
BC24
0.1U
SPDIF_IN4
SELECT1
AUX0
AUX1
GND_SHIELD
AUX0
AUX1
VCC33
1
2 3
EGND
PLL LOCK TIMS
60ms(Z VER)
35ms(R VER)
PRODUCTION
C38
47U/6.3V
R44 33
R45 33
R47 33
R55
1K
Q1
R1103
EGND
ASL1
6
1
28
4
12
13
14
15
26
9
11
8
7
CR
2.2nF
47nF
4.7nF
CIC21
VA+
SDA/CDOUT
SCL/CCLK
RXP0
RXP1
RXP2
RXP3
RXP4
RXP6
RST
RERR
FILT
AGND
OPIC1
AD1/CDINRXP5
CS8415A - SOIC
CS8415A-CS
C56
0.1U
EGND
RXP0SPDIF_IN
SPRST
ERR
1.2K
R58
C58
C59
0.1U
4700P
CF
RF
0.47uF
0.4K
0.1uF
1.2K
0.047uF
3K
OLRCK
OSCLK
SDOUT
RMCK
OMCK
AD0/CS
EMPH
RXN0
DGND
VCC33
23
VL+
17
16
18
10
21
2
2725
3
19
INT
5
20
U
24
H/S
22
SPSYNC
SPCLK
SPDAT
SPMCLK
MCLK_DIR
AD0
AD1
EMPH
EGND
C57
0.01U
VCC33
R48
R49
4.7K
R50
4.7K
R51 4.7K(OPEN)
R53 4.7K(OPEN)
R54 4.7K(OPEN)
EGND
4.7K
2-1
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