Page 1
SERVICE MANUAL
DVD DIGITAL THEATER SYSTEM
TH-A10
SP-PWA10
TH-A10TH-A10
TH-A10
SP-XSA10
(DVD player)/XV-TH-A10
SP-THA10
(Speaker section)
XV-THA10
SP-XCA10
SP-PWA10 (Powered subwoofer)
SP-XCA10 (Center speaker)
SP-XSA10 (Satellite speaker) x 4
SP-XSA10
3U
4U
Area Suffix
TH-A10
Maiaysia, Thailand,
Philippines
Brazil, Mexico, Peru
Contents
Safety precautions
Preventing static electricity
Dismantling and assembling
the traverse unit
Disassembly method
COPYRIGHT 2001 VICTOR COMPANY OF JAPAN, LTD.
1-2
1-3
1-4
1-5
Disassembly method
Main adjustment
Precautions for service
Description of major ICs
1-17
1-21
1-24
1-25
No.20890
JAN. 2001
Page 2
TH-A10
Safety precautions
1. This design of this product contains special hardware and many circuits and components specially
for safety purposes. For continued protection, no changes should be made to the original design
unless authorized in writing by the manufacturer. Replacement parts must be identical to those
used in the original circuits. Services should be performed by qualified personnel only.
2. Alterations of the design or circuitry of the product should not be made. Any design alterations of
the product should not be made. Any design alterations or additions will void the manufacturer`s
warranty and will further relieve the manufacture of responsibility for personal injury or property
damage resulting therefrom.
3. Many electrical and mechanical parts in the products have special safety-related characteristics.
These characteristics are often not evident from visual inspection nor can the protection afforded
by them necessarily be obtained by using replacement components rated for higher voltage,
wattage, etc. Replacement parts which have these special safety characteristics are identified in
the Parts List of Service Manual. Electrical components having such features are identified by
shading on the schematics and by ( ) on the Parts List in the Service Manual. The use of a
substitute replacement which does not have the same safety characteristics as the recommended
replacement parts shown in the Parts List of Service Manual may create shock, fire, or other
hazards.
4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the
like to be separated from live parts, high temperature parts, moving parts and/or sharp edges
for the prevention of electric shock and fire hazard. When service is required, the original lead
routing and dress should be observed, and it should be confirmed that they have been returned
to normal, after re-assembling.
5. Leakage currnet check (Electrical shock hazard testing)
After re-assembling the product, always perform an isolation check on the exposed metal parts
of the product (antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control
shafts, etc.) to be sure the product is safe to operate without danger of electrical shock.
Do not use a line isolation transformer during this check.
Plug the AC line cord directly into the AC outlet. Using a "Leakage Current Tester", measure
the leakage current from each exposed metal parts of the cabinet , particularly any exposed
metal part having a return path to the chassis, to a known good earth ground. Any leakage
current must not exceed 0.5mA AC (r.m.s.)
Alternate check method
Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms
per volt or more sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by
a 0.15 F AC-type capacitor between an exposed
metal part and a known good earth ground.
Measure the AC voltage across the resistor with the
AC voltmeter.
Move the resistor connection to eachexposed metal
part, particularly any exposed metal part having a
return path to the chassis, and meausre the AC
voltage across the resistor. Now, reverse the plug in
the AC outlet and repeat each measurement. voltage
measured Any must not exceed 0.75 V AC (r.m.s.).
This corresponds to 0.5 mA AC (r.m.s.).
0.15 F AC TYPE
1500 10W
Good earth ground
AC VOLTMETER
(Having 1000
ohms/volts,
or more sensitivity)
Place this
probe on
each exposed
metal part.
Warning
1. This equipment has been designed and manufactured to meet international safety standards.
2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.
3. Repairs must be made in accordance with the relevant safety standards.
4. It is essential that safety critical components are replaced by approved parts.
5. If mains voltage selector is provided, check setting for local voltage.
Burrs formed during molding may be left over on some parts of the chassis. Therefore,
pay attention to such burrs in the case of preforming repair of this system.
1-2
CAUTION
!
Page 3
Preventing static electricity
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged,
can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs.
1.1. Grounding to prevent damage by static electricity
Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as DVD players.
Be careful to use proper grounding in the area where repairs are being performed.
1.1.1. Ground the workbench
1. Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over
it before placing the traverse unit (optical pickup) on it.
1.1.2. Ground yourself
1. Use an anti-static wrist strap to release any static electricity built up in your body.
TH-A10
(caption)
Anti-static wrist strap
Conductive material
(conductive sheet) or iron plate
1.1.3. Handling the optical pickup
1. In order to maintain quality during transport and before installation, both sides of the laser diode on the
replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition.
(Refer to the text.)
2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power
source can easily destroy the laser diode.
1.2. Handling the traverse unit (optical pickup)
1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.
2. Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific
details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the traverse
unit. Be careful not to take too long a time when attaching it to the connector.
3. Handle the flexible cable carefully as it may break when subjected to strong force.
4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it
1-3
Page 4
TH-A10
Dismantling and assembling the traverse unit
1. Notice regarding replacement of optical pickup
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged,
can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing
repairs to the optical pickup or connected devices.
(Refer to the section regarding anti-static measures.)
1. Do not touch the area around the laser diode and actuator.
2. Do not check the laser diode using a tester, as the diode may easily be destroyed.
3. It is recommended that you use a grounded soldering iron when shorting or removing the laser diode.
Recommended soldering iron: HAKKO ESD-compatible product
4. Solder the land on the optical pickup's flexible cable.
Note : Short the land after shorting the terminal on the flexible cable using a clip, etc., when using an
ungrounded soldering iron.
Note : After shorting the laser diode according to the procedure above, remove the solder according
to the text explanation.
Short circuit land
Laser pick-up unit
Flexible cable
Shorting
Shot with the rclip
1-4
Page 5
TH-A10
Disassembly method
<Main body>
Removing the top cover
(See Fig.1 and 2)
1.
Remove the four screws A attaching the top cover
(Use an Allen wrench).
2.
Lift up the front part of the top cover to release the
two joints a and remove the top cover toward the
front.
Removing the rear cover (See Fig. 3)
Prior to performing the following procedure, remove
the top cover.
1.
Remove the four screws B attaching the rear cover
on the back of the body. Pull out the rear cover
backward.
Joints a
A
Top cover
A
Fig.1
Top cover
Removing the right and left side covers
(See Fig. 4 and 5)
Prior to performing the following procedure, remove
the top cover and the rear cover.
1.
Move the left side cover backward to release the five
joint hooks b and remove the left side cover outward.
2.
Remove the right side cover in the same way.
Right side cover
B
Joint a
B
Fig.2
Rear cover
Fig.3
Left side cover
B
B
Joints b
Joints b
Fig.4Fig.5
1-5
Page 6
TH-A10
Removing the front panel assembly
(See Fig. 6 to 9)
Prior to performing the following procedure, remove
the top cover, the rear cover and the side covers.
1.
Disconnect the harness from connector CN802 on
the main board on the upper side of the body.
2.
Remove the two screws C on the upper side of the
body.
3.
Remove the three screws D on the bottom of the
body.
4.
Release the five joints c and detach the front panel
assembly toward the front.
C
Joint c
Joint c
CN802
Front panel assembly
Fig.6
C
Joint c
D
Front panel assembly
Joint c
Fig.7
D
Joint c
1-6
Front panel assembly
Front panel assembly
Fig.8Fig.9
Page 7
Removing the right and left corner
covers (See Fig.10 and 11)
Prior to performing the following procedure, remove
the top cover, the rear cover, the side covers and the
front panel assembly.
It is not necessary to remove the front panel
assembly.
1.
Move the left corner cover backward to release the
three joint hooks d.
2.
Remove the right corner cover in the same way.
Removing the rear panel
(See Fig.12 to 14)
Prior to performing the following procedure, remove
the top cover and the rear cover.
1.
Remove the eighteen screws E and the one screw F
attaching the rear panel.
Left corner cover
Joint d
Joints d
TH-A10
Joints d
Fig.10
Joint d
Right corner cover
Fig.11
2.
Release the two joints e on both sides of the body.
Joint e
E
E
F
E
E
Fig.12
E
Rear panel
E
E
Joint e
Rear panel
Rear panel
Fig.12Fig.12
1-7
Page 8
TH-A10
Removing the DVD servo control board
(See Fig.15 to 17)
Prior to performing the following procedure,
remcover and the right side cover.ove the top cover,
the rear
1.
Remove the three screws G and pull the DVD servo
control board case upward.
2.
Disconnect the harness from connector CN501 and
CN503, and the card wire from CN101, CN103 and
CN502 of the DVD servo control board on the
underside of the DVD servo control board case.
3.
Remove the four screws H attaching the DVD servo
control board.
Digital I / O board
CN687
CN501
Analog I / O board
CN681
CN201
DVD servo control board (case)
Fig.15
CN503
CN502
G
DVD servo control board case
DVD servo control board
H
DVD servo control board case
CN103
Fig.16
H
Fig.17
CN101
H
H
1-8
Page 9
TH-A10
Removing the analog I / O board / the
digital I / O board (See Fig.18 and 19)
Prior to performing the following procedure, remove
the top cover and the rear cover.
1.
Remove the two screws E attaching the analog I / O
board on the back of the body.
2.
Disconnect the card wire from connector CN201 on
the analog I / O board.
3.
Remove the four screws E attaching the digital I / O
board on the back of the body.
4.
Disconnect the card wire from connector CN681 and
CN687 on the digital I / O board.
Removing the tuner board / the sub
board (See Fig.20 and 21)
Digital I / O board
CN687
E
Analog I / O board
CN681
E
CN201
DVD servo control board (case)
Fig.18
E
G
Rear panel
Prior to performing the following procedure, remove
the top cover, the rear cover and the DVD servo
control board case.
1.
Remove the two screws E attaching the tuner board
on the back of the body.
2.
Disconnect connector CN111 on the tuner board
from the sub board.
3.
Disconnect connector CN131 on the sub board from
the main board.
Sub board
Sub board
CN111
Fig.19
Tuner board
CN131
E
Fig.20Fig.21
1-9
Page 10
TH-A10
Removing the DVD mechanism assembly
(See Fig.22 and 23)
Prior to performing the following procedure, remove
the top cover, the rear cover, the front panel
assembly, the DVD servo control board case, the
analog I / O board, the digital I / O board and the
tuner board.
1.
Disconnect the harnesses from the spacer on the
upper side of the DVD mechanism cover.
2.
Remove the two screws I and the one screw J
attaching the DVD mechanism cover.
3.
Remove the two screws K attaching the DVD
mechanism assembly.
4.
Remove the DVD mechanism assembly upward
while pulling it backward.
K
I
DVD mechanism assembly
DVD mechanism cover
J
Spacer
Fig.22
K
I
Removing the power board
(See Fig.24 and 25)
Prior to performing the following procedure, remove
the top cover, the rear cover, the front panel
assembly, the DVD servo control board case and the
digital I / O board.
1.
Disconnect the harness from the spacer on the
upper side of the DVD mechanism cover.
2.
Remove the two screws E attaching the power
board on the back of the body.
3.
Disconnect the harness from connector CN911 and
CN912 on the power board.
4.
Remove the four screws L attaching the power
board.
5.
Disconnect connector CN913 and CN914 of the
power board from the main board by pulling out them
respectively.
Fig.23
Rear panel
Fig.24
Power transformer assembly
CN911,CN912
L
M
L
E
E
1-10
Power board
CN914
CN913
Spacer
L
Fig.25
Page 11
TH-A10
Removing the power transformer assembly
(See Fig.24 and 25)
Prior to performing the following procedures, remove
the top cover and the rear cover.
1.
Disconnect the harnesses from connector CN911
and CN912 on the power board.
2.
Remove the two screws M attaching the power
transformer assembly.
3.
Remove the screw E attaching the power
transformer assembly on the back of the body.
Removing the main board (See Fig.26)
Prior to performing the following procedure, remove
the top cover, the rear cover, the front panel
assembly, the rear panel, the DVD mechanism
assembly, the power board and the sub board.
1.
Remove the four DVD spacers on the upper side of
the main board.
2.
Remove the five screws N attaching the main board.
M
L
Power board
Rear panel
Fig.24
CN911,CN912
L
Fig.25
L
CN914
E
CN913
E
Spacer
<Front panel assembly>
Prior to performing the following procedure, remove
the top cover, the rear cover, the side covers and the
front panel assembly.
Removing the power switch board
(See Fig.27)
1.
Dithe harness from connector CN705 on the power
switch board.sconnect
2.
Remove the three screws O attaching the power
switch board.
N
Mainboard
IC board
Fig.26
R
N
N
CN706
Power switch board
O
O
S
Fig.27
LED board
1-11
Page 12
TH-A10
Removing the eject board (See Fig.28)
1.
Disconnect the harness from connector CN702 on
the eject board.
Eject board
Switch board
2.
Remove the three screws P attaching the eject
board.
Removing the LCD board (See Fig.29)
1.
Remove the four screws Q attaching the LCD board.
2.
Unsolder WA701, WA703 and WA704 on the LCD
board.
Removing the IC board (See Fig.27)
1.
Remove the screw R attaching the IC board.
2.
Disconnect the harness from connector CN706 on
the IC board.
Removing the LED board (See Fig.27)
P
CN702
WA701
Q
Q
T
Fig.28
LCD board
Fig.29
Q
WA704
WA703
Q
Prior to performing the following procedure, remove
the LCD board and the IC board.
1.
Disconnect the harness from connector CN705 on
the power switch board.
2.
Remove the two screws S attaching the LED board.
Removing the switch board (See Fig.28)
Prior to performing the following procedure, remove
the LCD board.
1.
Disconnect the harness from connector CN702 on
the eject board.
2.
Remove the two screws T attaching the switch
board.
IC board
S
R
Fig.27
CN706
Power switch board
O
O
LED board
1-12
Page 13
TH-A10
<Removing DVD mechanism unit>
Removing the clamper base (refer to Figure 1)
o Remove the top cover.
o Remove the DVD mechanism unit.
1. Remove the two screws at A fixing the clamper base.
Removing the loading tray (refer to Figures 2 - 4)
o Remove the clamper base.
1. Turn the up-down cam lever clockwise (in the direction
of the arrow in Figure 2) to lower the position of the mechanism.
2. Manually set the loading tray to the fully-open position.
3. Stretch the tray stoppers on both sides of the loading
base outward and pull out the tray.
Loading tray
Clamper base
Figure 1
Loading tray (front side)
Tray stopper
Loading tray
Loading base
Loading base
Up-down cam
Lever
Figure 2
Loading tray
Push
Push
Tray stopper
Figure 4
Figure 3
1-13
Page 14
TH-A10
Removing the traverse mechanism unit (refer to Figure 5)
o Remove the loading tray.
1. Remove the three screws at B fixing the traverse
mechanism unit.
Traverse mechanism unit
Protecting the optical pickup
o Solder the flexible ground point on the optical pickup
when replacing the pickup or before detaching the
mechanism control board. When assembling the unit,
remove the solder last.
Removing the mechanism control board
(refer to Figures 6 - 7)
o Remove the traverse unit. (Can be detached without
detaching the T-mechanism unit.)
1. Remove the two screws at C fixing the mechanism
control base from the bottom of the traverse unit.
2. Pull out the CN12 connector and detach the
mechanism control board.
3. Remove the card wire from the CN13 connector
on the mechanism control board.
4. Pull out the FPC holder from the CN12 connector
on the reverse side of the mechanism control board
and remove the flexible harness, referring to Figure 7.
B
Enlargement
Figure 5
Traverse mechanism unit
CN12
B
B
C
CN13
Connection area
(Solder the flexible
ground point)
Flexible harness
3
Enlargement
FPC holder
Figure 7
Mechanism control board
Figure 6
Flexible harness
2
1
CN12
Mechanism control board
1-14
Page 15
TH-A10
Removeing the turntable and spindle motor assemby
(refer to Figures 8 - 9)
o Remove the traverse mechanism unit.
o Solder the flexible ground point on the optical pickup.
(Figure 6)
o Remove the mechanism control board.
1. Remove the flexible harness from the feed motor
connector on the spindle motor board assembly.
2. Remove the three screws at D fixing the spindle motor
from the bottom of the traverse chassis.
Removing the feed motor unit (refer to Figure 9)
o Remove the traverse mechanism unit.
o Remove the mechanism control board.
1. Remove the FPC from the feed motor connector
on the turntable spindle motor board.
2. Remove the two screws at E fixing the feed motor unit.
Removing the optical pickup unit (refer to Figure 9)
o Remove the traverse mechanism unit.
Guide shaft B
o Remove the mechanism control board.
o Remove the feed motor unit.
1. Remove the screw at F fixing the guide shaft holder at B,
then simultaneously remove the guide shaft at B and the
optical pickup unit. While doing so, slide the unit
horizontally away from the guide shaft at A.
Traverse chassis
D
Figure 8
Traverse mechanism unit
F
Pick-up assembly
E
Guide shaft A
E
Feed motor assembly
Flexible harness
Feed motor connector
Turn table spindle motor unit
Figure 9
1-15
Page 16
TH-A10
Removeing the loading mechanism parts
(refer to Figures 10 - 11)
o Remove the clamper base.
o Remove the disk tray.
1. Turn the lever counterclockwise until it stops (position 1),
while pushing the switch lever in the direction of the
arrow and pushing up the pawl at A using a screwdriver.
2. Stretch the two pawls at B outward using a screwdriver
and remove the chassis.
3. Turn the lever clockwise (position 2) to remove the
up-down cam.
4. Remove the pulley gear and the pulley gear belt after
removing the screw at G fixing the pulley gear.
5. Pull out drive gear 2 then drive gear 1.
(1)When detaching
Removing the loading motor board
the chassis.
(refer to Figures 11 - 12)
o Remove the clamper base.
o Remove the disk tray.
1. Remove the loading belt.
2. Remove the two screws at H fixing the loading motor.
3. Remove the screw at I and the three pawls at C fixing
the loading motor base from the reverse side of the
loading base.
Up-down cam
Pawl B
G
chassis.
G
Lever
1
Up-down cam
Figure 10
Loading base
2
Pawl A
Chassis
Pawl B
Switch lever
(2)When detaching
the up-down cam.
Up-down cam
Switch lever
G
H
Loading motor unit
Loading base
H
Loading belt
Loading base
Drive gear 1
Drive gear 2
G
Pulley gear
Figure 11
Loading motor board
I
Pawl C
1-16
Figure 12
Page 17
TH-A10
Disassembly method
<Speaker>
Removing the amplifier assembly
(See Fig.1)
1.
Remove the twelve screws A attaching the amplifier
assembly on the back of the body.
2.
Move the amplifier assembly backward and
disconnect the harness from connector CN109 in the
lower part of the amplifier assembly.
Removing the heat sink cover and the
amplifier cover (See Fig.2 and 3)
Prior to performing the following procedure, remove
the amplifier assembly.
1.
Pull out the volume knob.
2.
Remove the four screws B attaching the heat sink
cover.
AA
CN109
Volume knob
A
Amplifier
assembly
A
Fig.1
B
Amplifier
assembly
3.
Remove the twenty screws C and the one screw D
attaching the amplifier cover.
Amplifier
cover
D
C
C
Fig.2
Heat sink
cover
B
C
Amplifier
assembly
CC
Fig.3
Amplifier
cover
C
C
1-17
Page 18
TH-A10
Removing the preamplifier board
(See Fig.4 to 6)
Prior to performing the following procedure, remove
the heat sink cover and the amplifier cover.
1.
Remove the two screws E attaching the preamplifier
board to the bracket.
2.
Disconnect connector CN201 on the preamplifier
board from the main amplifier board.
3.
Pull out the switch knob.
4.
Remove the nut and the two screws F attaching the
bracket.
Removing the power spply & SP terminal
board (See Fig.4and 5)
E
Braket
Preamplifier
board
Power spply &
SP terminal
board
Coard stopper
braket
G
Main amplifier board
G
Fig.4
Amplifier
assembly
Heat sink
Power
transformer
Prior to performing the following procedure, remove
the heat sink cover and the amplifier cover.
1.
Remove the three screws G attaching the coard
stopper braket.
2.
Disconnect connector CN210 and CN211 on the
power spply & SP terminal board from the main
amplifier board.
3.
Disconnect the power cord from connector CN108
on the power spply & SP terminal board and the
harness from CN107.
Preamplifier
board
Power spply &
SP terminal
board
Power cord
F
Switch knob
Braket
CN108
Nut
Braket
CN201
Main amplifier
board
CN211
CN210
CN107
Fig.5
Preamplifier
board
CN201
1-18
F
Fig.6
Page 19
Removing the Power Amplifier
Board(See Fig.7 and 8)
Prior to performing the following procedure, remove
the heat sink cover, the amplifier cover, the
preamplifier board and the power spply & SP
terminal board.
1.
Disconnect the harness from connector CN104 on
the power amplifier board.
2.
Remove the six screws H and the power amplifier
board with the heat sink.
3.
Remove the two screws I attaching the power
amplifier board (A) and the two screws J attaching
the power amplifier board (B) on the underside of
the power amplifier board.
H
Main amplifier
board
CN104
TH-A10
Power
transformer
H
Fig.7
4.
Disconnect connector CN102 and CN103 on the
power amplifier board (A) and CN105 and CN106 on
the power amplifier board (B) from the power
amplifier board respectively.
Removing the power amplifier board (A)
(See Fig.9 and 10)
Prior to performing the following procedure, remove
the heat sink cover, the amplifier cover, the
preamplifier board, the power spply & SP terminal
board and the power amplifier board.
1.
Remove the four screws K attaching the power
amplifier board (A) to the heat sink.
2.
Release the four joint hooks a bent and attached to
the outside of the power amplifier board (A).
3.
Move the power amplifier board (A) in the direction of
the arrow to release joint b and remove the power
amplifier board (A) from the bracket (A).
Joint a
CN102
CN103
Power amplifier
board (A)
CN102
CN103
IJ
CN106
CN105
Power amplifier
board (B)
IJ
Fig.8
LK
CN106
Heat sink
Braket (B)
CN102
CN103
Power amplifier
board (A)
Joint a
Fig.10
Joint b
Hooks
Braket(A)
K
Power amplifier
board (A)
K
K
L
CN105
Power amplifier
board (B)
L
Fig.9
1-19
Page 20
TH-A10
Removing the power amplifier board (B)
(See Fig.9 and 11)
Prior to performing the following procedure, remove
the heat sink cover, the amplifier cover, the
preamplifier board, the power spply & SP terminal
board and the main amplifier board.
1.
Remove the four screws L attaching the power
amplifier board (B) to the heat sink.
2.
Release the four joint hooks c bent and attached to
the outside of the power amplifier board (B).
3.
Move the power amplifier board (B) in the direction of
the arrow to release joint d and remove the power
amplifier board (B) from the bracket (B).
Removing the power transformer
(See Fig.12 and 13)
Prior to performing the following procedure, remove
the amplifier cover.
Hooks
Main amplifier
board
Joint c
CN106
Power amplifier
board
CN105
Joint d
Joint c
Fig.11
1.
Disconnect the harness from connector CN104 on
the main amplifier board.
2.
Disconnect the harness from connector CN107 on
the power spply & SP terminal board.
3.
Remove the four screws M attaching the power
transformer.
Power spply
& SP terminal
board
M
CN104
Power spply
& SP terminal
board
M
Power
transformer
M
M
Fig.12
1-20
CN107
Fig.13
Page 21
Main adjustment
Adjustment and confirmation matter
(1) Auto adjustment method
If microprocessor (IC401, IC402, IC714, IC716) or DVD Prek-up is replaced, initialize
the DVD player in the following matter:
1. Initialize the DVD player in the following matter:
1) Make sure that no disc is on the tray.
2) Insert the power pulag to the outret while pressing "PLAY" and "OPEN/CLOSE" button at the
same time.
FL Display indicate ; Region cord.
3) Press Enter button. And EEPROM initialize start.
4) When indicate "96kHz EEPROM" on the display , initialize finished.
Note : During the EEPROM initialization the keys may not be operated.
Press the "POWER" key to initiate the STAND-BY mode and the test mode will then
be cancelled.
TH-A10
(2) Confirmation of DVD RF level
1.The oscilloscope is connected between P1 and GND.
2.Reproduction of the test disc (VT-501)
made by JVC.
3.It is confirmed that RF LEVEL is 350mVp-p 150mVp-p.
4.When there is disorder in the waveform road cuts etc,
test disk is exchanged and measured.
(3) Confirmation of CD jitter level and RF level
1. The CD jitter meter is connected between GND and P12.
The RF level is observed at the same time.
2.The first test disk(CTS-1000) made of JVC is reproduced.
3.It is confirmed that RF LEVEL is 360 100mVp-p.
5. When there is disorder in the waveform road cuts
etc, test disk is exchanged and measured.
P12
and
GND
P1
and
GND
DVD SERVO CONTROL PWB
FRONT SIDE
1-21
Page 22
TH-A10
(4) Flap adjustment of the Pick-up guide shaft
1) Make sure that there is no disc on the tray.
2) Press both the "PLAY" and "OPEN/CLOSE" keys of the main unit to activate the primary
power and ∗ ∗ ( ∗ ∗ ; Version3, ; Region cord) will be displayed on the FL indicator.
Note: If the FL indicator display stops and remains at "TEST 0", unplug the power
cord from the outlet and after waiting at least 1 second, plug it in again. After
the tray open/close procedure has completed, unplug it again and then
perform the initialization procedure again.
3) Press the "OPEN/CLOSE" key of the main unit to draw the tray out.
*Place the test disk (VT-501) on the tray and then press the "OPEN/CLOSE" key.
(Note: Pushing the tray to close it is not possible.)
4) Press the "PLAY" key of the main unit.
5) The "JIT 0000" is displayed on the FL indicator.
Set the FL indicator figure value to its minimum by adjusting the pickup guide shaft flap.
* The test mode is cancelled when the power is turned off.
Measurement
Measurement machine
No need
General tool : Hex-head wrench (1.27 mm)
Adjustment point
Refer to Fig.2
connections
Refer to Fig.1
Mode
Reproduction
part
Extension cord No.
QUQ110-3740AM
Disc
VT-501
"Flap adjustment" of the Pick-up guide shaft adjusts
"Tangential adjustment machine screw" A and
"Tilt adjustment machine screw" B from the
DVD Mechanism A'ssy bottom.
1. The part at the center on the DVD test disc is
reproduced.
2.The flap adjustment screws is turned alternately
and adjusted like clearly seeing the waveform of
CN104"1" to the way.
Note
1.The tangential adjustment is done finish and,
then, tilt is adjusted.
2.The repeat the adjustment 2-3 times,for best
result.
3.The final adjustment should be tilt adjustment.
Extension Cord
DVD Mechanism A'ssy
CN11 of
Stand
Connection PWB
CN101 of DVD Servo Control PWB
DVD player
Stand
200mm
Fig.1
1-22
Page 23
Confirmation after adjustment.
Confirm to reproduce video CD and CD after
the DVD test disc is adjusted and to find abnormality.
B
Fig.2
A
A
(5) About keeping the disc
As for the DVD test disc, plane accuracy is demanded.Please note the keeping place on the disc.
1. Please do not put the disc directly on the work desk etc. after uses .
2. To keep the planarity of the disc, politely handle ,and please put in a special case and keep
the disc vertically after uses .
Please keep keeping the disc in a cool place where direct sunshine and the air-conditioning
wind do not drive.
3. When the disc curves,an accurate adjustment cannot be done.
Please exchange for a new test disc and adjust optics.
4. Other discs might not be able to be reproduced when adjusting on a curved disc.
TH-A10
Point of adjustment
* Please execute the static electricity protection measures before starting the adjustment.
* When the following parts are exchanged,optical adjustment "Adjust the flap of the disc motor"
is necessary.
1.The disc motor was exchanged.
2.The laser pick up was exchanged.
3.The traverse motor unit was exchanged.
Note
Additionally, please adjust the flap of the disc motor when the picture quality
deterioration is seen .The basic adjustment though, is unnecessary for part exchange
in the traverse.
An optical adjustment in the laser pick up cannot be done.
Please adjust the flap of the disc motor after exchanging the laser pick up.
* When the traverse unit is exchanged, the adjustment is basically unnecessary.
1-23
Page 24
TH-A10
Precautions for Service
Handling of Traverse Unit and Laser Pickup
1. Do not touch any peripheral element of the pickup or the actuator.
2. The traverse unit and the pickup are precision devices and therefore must not be subjected to
strong shock.
3. Do not use a tester to examine the laser diode. (The diode can easily be destroyed by the
internal power supply of the tester.)
4. To replace the traverse unit, pull out the metal short pin for protection from charging.
5. When replacing the pickup, after mounting a new pickup, remove the solder on the short land
which is provided at the center of the flexible wire to open the circuit.
6. Half-fixed resistors for laser power adjustment are adjusted in pairs at shipment to match the
characteristics of the optical block.
Do not change the setting of these half-fixed resistors for laser power adjustment.
Destruction of Traverse Unit and Laser Pickup by Static Electricity
Laser diodes are easily destroyed by static electricity charged on clothing
or the human body. Before repairing peripheral elements of the traverse
unit or pickup, be sure to take the following electrostatic protection:
1. Wear an antistatic wrist wrap.
2. With a conductive sheet or a steel plate on the workbench on which
the traverse unit or the pick up is to be repaired, ground the sheet
or the plate.
3. After removing the flexible wire from the connector (CN101),
short-circuit the flexible wire by the metal clip.
4. Short-circuit the laser diode by soldering the land which is provided
at the center of the flexible wire for the pickup.
After completing the repair, remove the solder
to open the circuit.
Short-circuit
1-24
Page 25
Discription of major IC's
AK5330 (IC701) : A/D Converter
1. Terminal layout
TH-A10
2. Block diagram
AINR
ZEROR
AINL
ZEROL
VREFR
VREFL
VCOM
AGND
VA
VB
TST2
TST3
1
2
3
4
5
6
7
8
9
10
11
12
To p
View
24
23
22
21
20
19
18
17
16
15
14
13
DIF2
DIF1
DIF0
SDT0
L/R
SCLK
MCLK
PD
CMODE
TST1
DGND
VD
AINL
ZEROL
AINR
ZEROR
VCOM
VREFL
VREFR
VA AGND VD VB DGND
Decimation
Modulator
Modulator
Voltage Reference
Filter
Decimation
Filter
PD
DIF0
MCLK CMODE
Clock Divider
Serial I/O
Interface
DIF1 DIF2
L/R
SCLK
SDT0
TST1
TST2
TST3
1-25
Page 26
TH-A10
3. Pin function
No. Pin Name I/O Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AINR
ZEROR
AINL
ZEROL
VREFR
VREFL
VCOM
AGND
VA
VB
TST2
TST3
VD
DGND
TST1
CMODE
PD
MCLK
SCLK
L/R
SDT0
DIF0
DIF1
DIF2
I
I
I
I
O
O
O
-
-
-
I/O
I/O
-
-
I
I
I
I
I
I
O
I
I
I
Rch Analog Input Pin
Rch Zero Input Pin
Lch Analog Input Pin
Lch Zero Input Pin
Rch Vopltage Reference Output Pin. 2.5V
Normally connected to AGND with a 0.1uF ceramic capacitor
in parallel with an electrolytic capacitor less than 10uF.
Lch Vopltage Reference Output Pin. 2.5V
Normally connected to AGND with a 0.1uF ceramic capacitor
in parallel with an electrolytic capacitor less than 10uF.
Voltage Common Output Pin. 2.5V
Normally connected to AGND with a 0.1uF ceramic capacitor
in parallel with an electrolytic capacitor less than 10uF.
Analog Ground Pin
Analog Supply Pin, +5V
Substrate Voltage Supply Pin, +5V
Test Pins (Pull-down pin)
Must be left floating.
Digital power Supply Pin, +5V
Digital Ground Pin
Test Pin (Pull-down pin)
Must be left floating or connected to DGND.
Master Clock Select Pin
"L" : MCLK=256fs, "H" : MCLK=384fs
Power-Down Pin
When "H", the circuit is in power-down mode,Upon
returning to "L", the AK5330 starts an offset calibration
cycle.A calibration cycle should always be initiated after
power-up.
Master Clock Input Pin
Serial Data Clock Pin
Output data is clocked out on the falling edge of SCLK.
Input data is clocked in on the rising edge of SCLK. SCLK
requires a continuously supplied clock at any frequency from
32fs to 64fs.
Left/Right Channel Select Pin
The fs clock is input to this pin.
"H" : Lch, "L" : Rch
Serial Data Output Pin
Data bits are presented MSB first, in 2's complement format.
This pin is "L" in the power-down mode.
Serial Interface Format Pin
Correspond to 8 modes.
1-26
Page 27
AK93C65AF-X (IC590) : EEPROM
1.Pin layout
TH-A10
PE
VCC
CS
SK
2.Block diagram
DI
CS
INSTRUCTION
1
2
3
4
8 PIN SOP
REGISTER
8
7
6
5
INSTRUCTION
GENERATION
NC
GND
DO
DI
DECODE,
CONTROL
AND
CLOCK
DATA
REGISTER
ADD.
BUFFERS
16
R/W AMPS
AND
AUTO ERASE
DECODER
DO
16
EEPROM
4096bit
256 x 16
SK
PE
3.Pin function
Pin no. Symbol
1 PE
2 VCC
3 CS
4 SK
5 DI
6 DO
7 GND
8 NC
Function
Program enable (With built-in pull-up resistor)
Power supply
Chip selection
Cereal clock input
Cereal data input
Cereal data output
Ground
No connection
NOTE : The pull-up resistor of the PE pin is about 2.5M (VCC=5V)
VREF
VPP SW
VPP
GENERATOR
1-27
Page 28
TH-A10
AN8706FHQ (IC101) : Front end processor
1.Pin layout
CBDOSL
CSAG
DCAGC
AGCG
PEAK
BOTTOM
RFENVFCBOOST
OFTR
BDO
JITOUT
75747372717069686766656463626160595857565554535251
RBCA
RFINP
RFINN
VCC2
GND2
VREF2
RFON
RFOP
TS
DCRF
FS
VIN6
VIN5
VCC1
VIN1
VIN2
VIN3
VIN4
VREF4
DIFP
DIFN
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AN8706FHQ
CBDOFS
TESTSG
COFTFS
COFTSL
GND3
FUPDN
ITDLI
VCOIN
PLFLT
PLFLT2
FCPO
PCPO
VCC3
CAPA
DTRD
IDGT
VCC5
50
RDCKP
49
RDCKN
48
RDTP
47
RDTN
46
GND5
45
GND4
44
VCC4
43
DTMONN
42
DTMONP
41
DSLFLT
40
DSLO
39
FLTOUT
38
DCFLT
37
VREF3
36
VPWBDO
35
VPWOFT
34
IDDLY
33
DBAL
32
GND1
31
VREF1
30
TKCNT
29
TKCFLT
28
TEOUT
27
TEI
26
RSCL
2.Block diagram
Head Amp.
SSD Signal
Head Amp.
DPD Signal
12345678910111213141516171819202122232425
TG
LPCOA
LDONB
LDONA
LPC1
VHARF
RFOUT
FS/TS
POFLT
TGBAL
PTH
TBAL
FBAL
FGCTL
FEN
VREFL
FEOUT
PULIN
VREFC
VREFH
TGTETKCNTTBALFBALFE
SEN
SCK
STDI
FC/Boost
AGC Cont
TKCNT
FE(SSD)
FE BAL
AGC EQ
MU
TE(DPD)
TE BAL
STNBY
XTRON
RFIN
MTRON
ROMRAM
RF ENV
DSL
BDO Det
OFTR Det
DFLTOP/NRFENV
PLL
JITTER Det
SYNC
JITOUT
CLK
DATA
DSLOUT
BDO
OFTR
1-28
TG(DPD)
LPC(Amp)
OPTICAL HEAD
(650nm)
INTERFACE
VREF reg
TGBAL CPU STNBY MTRON
SERVO PROCESSOR
Head Amp.
Page 29
TH-A10
3.Pin function
Pin No. Symbol I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
LDONB
LDONA
LPCOA
LPC1
VHARF
TGBAL
POFLT
PTH
TBAL
TG
FGCTL
FBAL
FEOUT
FEN
VREFL
VREFC
VREFH
PULIN
SEN
SCK
STDI
STNBY
XTRON
MTRON
ROMRAM
RSCL
TEI
TEOUT
TKCFLT
TKCNT
VREF1
GND1
DBAL
IDDLY
VPWOFT
VPWBDO
VREF3
DCFLT
FLTOUT
DSLO
DSLFLT
DTMONP
DTMONN
VCC4
GND4
GND5
RDTN
RDTP
RDCKN
RDCKP
Functions
I
Laser ON (CD Head) terminal
I
Laser ON (DVD Head) terminal
O
Laser drive output terminal
I
Laser PIN input terminal
O
VHALF voltage output terminal
I
Tangential phase balance control terminal
O
Track detection Threshold value level terminal
I
Track detection Threshold value level terminal
I
Tracking balance control terminal
O
Tangential phase error signal output terminal
I
Focus amplifier Gain control terminal
I
Focus balance control terminal
O
Focus error signal output terminal
I
Focus error output amplifier reversing input terminal
O
VREFL voltage output terminal
O
VREFC voltage output terminal
O
VREFH voltage output terminal
I
DSL,PLL drawing mode switch terminal
I
SEN(Cereal data input terminal)
I
SCK(Cereal data input terminal)
I
STDI(Cereal data input terminal)
I
Standby mode control terminal
I
Tracking OFF holding input terminal
I
Monitor output ON/OFF switch terminal
I
ROM . RAM switch terminal
O
Standard current source terminal
I
Tracking error output Amp reversing input terminal
O
Tracking error signal output terminal
O
Track count detection filter terminal
O
Track count output terminal
O
VREF1 voltage output terminal
O
Earth terminal 1
I
Data slice offset adjustment terminal
I
Data slice delay adjustment terminal
I
OFTR detection level setting terminal
I
BDO detection level setting terminal
O
VREF3 voltage output terminal
O
Capacity connection terminal for data slice input filter
O
Filter amplifier output terminal
O
Data slice single data output terminal
O
Constant filter terminal when data is sliceddelly
O
PLL differential motion 2 making to value edge signal moniter output (+)
O
PLL differential motion 2 making to value edge signal moniter output (-)
I
Power terminal 4 (5V)
O
Earth terminal 4
O
Earth terminal 5
O
PLL differential motion making to synchronization RF signal reversing output
O
PLL differential motion making to synchronization RF signal rotation output
O
PLL differential motion making synchronization clock reversing output
O
PLL differential motion making synchronization clock rotation output
AN8706FHQ (1/2)
1-29
Page 30
TH-A10
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VCC5
IDGT
DTRD
CAPA
VCC3
PCPO
FCPO
PLFLT2
PLFLT
VCOIN
ITDLI
FUPDN
GND3
JITOUT
BDO
OFTR
BOOST
FC
RFENV
BOTTOM
PEAK
AGCG
DCAGC
CSAG
CBDOSL
CBDOFS
RBCA
TESTSG
RFINP
RFINN
VCC2
GND2
VREF2
COFTFS
COFTFL
RFON
RFOP
TS
DCRF
FS
VIN6
VIN5
VCC1
VIN1
VIN2
VIN3
VIN4
VREF4
DIFP
DIFN
I/OPin No. Symbol Functions
Power terminal 5 (3.3V)
I
Data slice part address part gate signal input terminal (For RAM)
I
Data slice data read signal input terminal(For RAM)
I
Data slice CAPA(Address)signal input terminal (For RAM)
I
Power terminal 3 (5V)
I
PLL phase gain set terminal
O
PLL frequency gain set terminal
O
PLL low region filter terminal
O
PLL high region filter terminal
O
PLL VCO input terminal
I
PLL jitter free current ripple removal filter terminal
O
PLL frequency control input terminal
I
Earth terminal 3
O
Detection signal output of jitter
O
BDO output terminal
O
OFTR output terminal
O
Booth control terminal for filter
I
FC control terminal for filter
I
RF enve output terminal
O
Bottom enve detection filter terminal
O
Peak enve detection filter terminal
O
AGC amplifier gain control terminal
O
AGC amp filter terminal
O
Sag cancellation circuit filter terminal
O
BDO detection capacitor terminal
O
BDO detection capacitor terminal
O
BCA detection level setting terminal
O
TEST signal input terminal
I
RF signal positive moving input terminal
I
RF signal reversing input terminal
I
Power terminal 2 (5V)
I
Earth terminal 2
O
VREF2 voltage output terminal
O
OFTR detection capacitor terminal
O
OFTR detection capacitor terminal
O
RF signal output terminal P
O
RF signal output terminal N
O
All addition amplifier (DVD) output terminal
O
All addition amplifier capacitor terminal
O
All addition amplifier (CD) output terminal
O
Focus input of external division into two terminal
I
Focus input of external division into two terminal
I
Power terminal 1 (5V)
I
External division into four (DVD/CD) RF input terminal 1
I
External division into four (DVD/CD) RF input terminal 2
I
External division into four (DVD/CD) RF input terminal 3
I
External division into four (DVD/CD) RF input terminal 4
I
VREF4 voltage output terminal
O
RF signal (RAM) output terminal P
O
RF signal (RAM) output terminal N
O
AN8706FHQ(2/2)
1-30
Page 31
BA15218N (IC32 / IC35) : Dual Ope. Amp.
+
+
1
-
1 2 3 4 5 6 7 8
OUT1 +IN1 +IN1
+IN2 -IN2 OUT2
GND
2
-
Vcc
MC33269D-X (IC555) : Regurator
TH-A10
GND/ADJ NC
Vout Vout
1
2
3
4
8
7
6
5
NCVin
RN5RZ20BA-X(IC102) : High cycle module
2.Block diagram1.Terminal layout
CE
54
NC
V
2
DD
123
VOUT
3
3.Pin function
Pin No. Pin name Function
GND
1
2
3
4
5
VDD
GND
V
V
NC
CE
VOUT
DD
OUT
CE
5
Ground terminal
Input terminal
Output terminal
No connection
Chip enable terminal
Vref
GND
Current Limit
1
1-31
Page 32
TH-A10
BA5983FM (IC271) : 4CH DRIVER
1.Block Diagram
27
28
Vcc
1
2
25
26
10k
10k
3
20k
10k
4
24
5
23 22
10k
10k
6
20k
10k
7
2.Pin Function
Pin No. Pin No.
10
11
12
13
14
Symbol Symbol
1
BLAS IN
2
OPIN1(+)
3
OPIN1(-)
4
OPOUT1
5
OPIN2(+)
6
OPIN2(-)
7
OPOUT2
8
9
GND
STBY1
PowVcc1
VO2(-)
VO2(+)
VO1(-)
VO1(+)
I/O I/O
Input for Bias-amplifier
I
Non inverting input for CH1 OP-AMP
I
Inverting input for CH1 OP-AMP
I
Output for CH1 OP-AMP
O
Non inverting input for CH2 OP-AMP
I
Inverting input for CH2 OP-AMP
I
Output for CH2 OP-AMP
O
Substrate ground
-
Input for CH1/2/3 stand by control
I
Vcc for CH1/2 power block
-
Inverted output of CH2
O
Non inverted outpur of CH2
O
Inverted output of CH1
O
Non inverted outpur of CH1
O
Function
15
16
17
18
19
20
21
22
23
24
25
26
27
28
21
20
STAND BY
CH4
STAND BY
CH1/2/3
89
VO4(+)
VO4(-)
VO3(+)
VO3(-)
PowVcc2
STBY2
GND
OPOUT3
OPIN3(-)
OPIN3(+)
OPOUT4
OPIN4(-)
OPIN4(+)
PreVcc
Vcc
17 16
18
19
10k
10k
10k
10k
Level Shift
Level Shift
10k
10k
10k
10k
12
13
Vcc
10
10k
10k
Level Shift
Level Shift
10k
10k
11
Function
O
Non inverted output of CH4
O
Inverted output of CH4
O
Non inverted output of CH3
O
Inverted output of CH3
-
Vcc for CH3/4 power block
I
Input for Ch4 stand by control
-
Substrate ground
O
Output for CH3 OP-AMP
I
Inverting input for CH3 OP-AMP
I
Non inverting input for CH3 OP-AMP
O
Output for CH4 OP-AMP
I
Inverting input for CH4 OP-AMP
I
Non inverting input for CH4 OP-AMP
-
Vcc for pre block
15
10k
10k
10k
10k
14
1-32
Page 33
HY57V161610DTC8 or KM416S1120DT-G8 (IC504,IC505) : 16MB SDRAM
1.Block diagram
TH-A10
CLK
CKE
Address
CS
RAS
CAS
WE
Clock
Generator
Mode
register
Command decoder
Control logic
Row
address
buffer &
Refresh
counter
Column
address
buffer &
burst
counter
Bank B
Bank A
Row decoder
Sense amplifier
Column decoder
& latch circuit
Data counter
Input & output
Latch circuit
DQM
DQ
buffer
2.Pin function
Pin No. Symbol Description Pin No. Symbol Description
1
2,3
4
5,6
7
8,9
10
11,12
13
14
15
16
17
18
19,20
21~24
25
VCC
DQ0,1
VSS
DQ2,3
VDD
DQ4,5
VSS
DQ6,7
VCC
LDQM
WE
CAS
RAS
CS
A11,10
A0~3
VCC
Power supply
Data input/output
Connect to GND
Data input/output
Power supply
Data input/output
Connect to GND
Data input/output
Power supply
Lower DQ mask enable
Write enable
Column address strobe
Row address strobe
Chip enable
Address inputs
Address inputs
Power supply
26
27~32
33
34
35
36
37
38
39,40
41
42,43
44
45,46
47
48,49
50
VSS
A4~9
NC
CKE
CLK
UDQM
NC
VCC
DQ8,9
VSS
DQ10,11
VDD
DQ12,13
VSS
DQ14,15
VSS
Connect to GND
Address inputs
Non connect
Clock enable
System clock input
Upper DQ mask enable
Non connect
Power supply
Data input/output
Connect to GND
Data input/output
Power supply
Data input/output
Connect to GND
Data input/output
Connect to GND
1-33
Page 34
TH-A10
JCE8011(IC551):GRAPHIC CONTROLLER
Pin No. Symbol
1~8
9
10
11
12
13
14
15
16~23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39~46
47
48
49
50
51
52
53
54~61
62
63~70
71
72
73~82
83
84~93
94
95
96
97
98
99
100
VD0~7
VCLKI
HSYNCI
VSYNCI
VCC
VCLKD
HSYNCO
VSYNCO
DOUT0~7
TEST
RESETB
GND
NTB
DTSF0
DTSFI
VIDEG
DOSF0
DOSF1
XVRST
F1
HBL
VBL
VOEDG
VCC
FRD7~0
GND
FRCK
FWCK
FREB
FWEB
FRRSTB
FWRSTB
FWD7~0
VCC
CHD7~0
GND
CHOEB
CHA19~10
VCC
CHA9~0
GND
ACK
CS1B
CS2B
SCK
RXD
TXD
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function
DVD Image signal input (Multi plex data Y,Cr,Cb)
I
Dot clock signal input (27MHz)
I
The horizontal synchronous signal input
I
Vertical synchronous signal input
I
Power supply
Dot clock signal output (27MHz)
'H' blanking output
'V' blanking output
Digital data output
Test terminal (Uses as GND usually)
System reset signal
I
Connect to GND
Mode switching NTSC(low) / PAL(high)
I
Taking timing shift of VD input
I
Taking timing shift of VD input
I
Taking edge specification of VD input (0:up , 1:down)
I
Timing shift input of output data
I
Timing shift input of output data
I
Non connect
Field Identification signal output
'H' blanking output
'V' blanking output
Output timing setting of DOUT (0:up , 1:down)
I
Power supply
Field memory read data input
I
Connect to GND
Field memory read clock
Field memory write clock
Field memory read enable
Field memory write enable
Field memory read address reset
Field memory write address reset
Field memory write data output
Power supply
Character ROM data
I
Connect to GND
Character ROM output enable
Character ROM address output
Power supply
Character ROM address output
Connect to GND
-
Serial data chip select for graphic control
I
Serial data chip select for encoder control
I
Serial clock input
I
Serial input data
I
Serial output data
1-34
Page 35
TH-A10
MC44724AVFU (IC554) : VIDEO ENCODER
1.Terminal layout 2.Block diagrams
1
~
16
17 ~ 32
3.Pin function
No. Symbol
1
CVBS/Cb/B1
2
CVBS/Cb/B1
3
CVBS/Cb/B1Vdd
4
Y/G1
5
Y/G1
6
Y/G1/Vdd
7
C/Cr/R1
8
C/Cr/R1
9
C/Cr/R1Vdd
10
DAVss
11
TBIAS1
12
Vref1
13
DAVdd
14
Vref2
15
TBIAS2
16
NC
17
CVBS/Cb/B2
18
CVBS/Cb/B2
19
CVBS/Cb/B2Vdd
20
Y/G2
21
Y/G2
22
Y/GVdd
23
C/Cr/R2
24
C/Cr/R2
25
C/Cr/R2Vdd
26
ChipA
27
TEST
28
DVdd
29
CLOCK
30
DVss
31
Reset
32
PAL/NTSC
64 ~ 49
I/O
48
~
33
O
Analog composite drive signal (+)
O
Analog composite drive signal (-)
-
Power supply for CVBS/Cb/B DAC1
O
Analog brightness signal/G drive signal (+)
O
Analog brightness signal/G drive signal (-)
-
Power supply for Y/G DAC
O
Analog chroma signal (+)
O
Analog chroma signal (-)
-
Power supply for C/Cr/RDAC
-
Connect to ground for DAC
O
Standard BIAS for DAC1
-
Standard voltage for DAC1
-
Power supply for DAC
-
Standard voltage for DAC2
O
Standard BIAS for DAC2
-
Non connect
O
Analog composite drive signal (+)
O
Analog composite drive signal (-)
-
Power supply for CVBS/Cb/B DAC2
O
Analog brightness signal/G drive signal (+)
O
Analog brightness signal/G drive signal (-)
-
Power supply for Y/G DAC
O
Analog chroma signal (+)
O
Analog chroma signal (-)
-
Power supply for C/Cr/RDAC2
-
Chip address selection
I
Connect to test pin
-
Digital ground
I
Clock signal input (27MHz)
-
Power supply for digital circuit
I
Reset signal input L:ON
I
Selection NTSC/PAL NTSC:L PAL:H
ChipA
DVdd
DVdd
DVss
DVss
DVIN[7:0]
TP[8:1]
TVIN
TP[0]IN
Clock
Reset
PAL/NTSC
Function
H.V
DEMAX
Y
cb
cr
12C / SPI
SO
SDA/SI
EXT
Sync_ generator
CGMS,
wss gen
0
off_set
0
0
sub carrier
SEL
SCL/SCK
No. Symbol
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
F/Vsync
CCwss gen
Modulator
gen
SO
SDA/SI
SCL/SCK
SEL
DVdd
DVss
DVIN7
DVIN6
DVIN5
DVIN4
DVIN3
DVIN2
DVIN1
DVIN0
TVIN
EXT
F/Vsyac
Chsyac
DATST
TP-8
TP7
TP6
TP5
DVss
DVdd
TP4
TP3
TP2
TP1
TP0
DLVdd
DLVss
Hsync
RGB
matrix
Y/G2Vdd
C/Cr/R2Vdd
CVBS/Cb/B2Vdd
Copy,
protection
bus
0
+
0
+
0
0
0
Output Selector
0
DAC BIAS DAC DAC DAC
DAC
DAC
BIAS
TEST
TEST
I/O
-
Non connect
I
SPI Mode : Serial data input
I
Serial clock input
I
Power supply for serial data,chip select,digital
--
Power supply for digital circuit
--
Digital ground
I/O
Y data input / test data I/O
I/O
Y data input / test data I/O
I/O
Y data input / test data I/O
I/O
Y data input / test data I/O
I/O
Y data input / test data I/O
I/O
Y data input / test data I/O
I/O
Y data input / test data I/O
I/O
Y data input / test data I/O
I
VIDEO mute on Reset(0:nomal, 1:mute)
I/O
Frame output / VBI information input
I/O
Frame / Vertical, synchronous I/O
I/O
The horizontal, synchronous I/O
I
Data input
I/O
Multiplex data input
I/O
Multiplex data input
I/O
Multiplex data input
I/O
Multiplex data input
-
Ground for digital circuit
-
Power supply for digital circuit
I/O
Data input / Test data I/O
I/O
Data input / Test data I/O
I/O
Data input / Test data I/O
I/O
Data input / Test data I/O
I/O
Data input / Test data I/O
-
Power supply for D/A converter
-
Ground for D/A converter
DLVss
DLVdd
Function
Y/G1Vdd
CVBS/Cb/B1Vdd
C/Cr/R1Vdd
Y/G1
Y/G1
CVBS/Cb/B1
CVBS/Cb/B1
C/Cr/R1
C/Cr/R1
Vref1
iBIAS1
Y/G2
Y/G2
CVBS/Cb/B2
CVBS/Cb/B2
C/Cr/R2
C/Cr/R2
Vref2
Ibias
DAVdd
DAVss
1-35
Page 36
TH-A10
MN102LP25G-01(IC401):UNIT CPU
Pin No. Pin No.
Symbol Symbol
1
WAIT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RE
MUTE
WEM
CS0
CS1
CS2
CS3
TCLOSE
TOPEN
LSIRST
WORD
A0
A1
A2
A3
VDD
SYSCLK
VSS
XI
XO
VDD
OSCI
OSCO
MODE
A4
A5
A6
A7
A8
A9
A10
A11
VDD
A12
A13
A14
A15
A16
A17
A18
A19
VSS
A20
STOP
ADPD
-
-
TRVSW
I/O I/O
Micon wait signal input
I
Read enable
O
Driver mute
O
Write enable
O
Non connect
O
Chip select for ODC
O
Chip select for ZIVA
O
Chip select for outer ROM
O
Tray close signal output
O
Tray open signal output
O
LSI reset
I
Bus selection input
O
Address bus 0 for CPU
O
Address bus 1 for CPU
O
Address bus 2 for CPU
O
Address bus 3 for CPU
O
Power supply
System clock signal output
O
Power supply
Non connect
Non connect
Power supply
Clock signal input(13.5MHz)
I
Non connect
CPU Mode selection input
I
Address bus 4 for CPU
O
Address bus 5 for CPU
O
Address bus 6 for CPU
O
Address bus 7 for CPU
O
Address bus 8 for CPU
O
Address bus 9 for CPU
O
Address bus 10 for CPU
O
Address bus 11 for CPU
O
Power supply
Address bus 12 for CPU
O
Address bus 13 for CPU
O
Address bus 14 for CPU
O
Address bus 15 for CPU
O
Address bus 16 for CPU
O
Address bus 17 for CPU
O
Address bus 18 for CPU
O
Address bus 19 for CPU
O
Power supply
Address bus 20 for CPU
O
Non connect
Non connect
Non connect
Non connect
Non connect
Detection switch of traverse
I
inside
Function
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SWCLOSE
SWOPEN
ADSCEN
VDD
EFPEN
SLEEP
BUSY
REQ
WEROM
WPROM
VSS
EECS
EECK
EEDI
EEDO
VDD
SCLK0
S2UDT
S2SDT
CPSCK
SDIN
SDOUT
-
-
NMI
ADSCIRQ
ODCIRQ
DECIRQ
WAKEUP
ODCIRQ2
ADSEP
RST
VDD
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
TEST8
VSS
D0
D1
D2
D3
D4
D5
D6
D7
Function
Detection switch of tray close
I
Detection switch of tray open
I
Serial enable signal for ADSC
O
Non connect
Serial enable signal for FEP
O
Standby signal for FEP
O
Communication busy
I
Communication Request
O
Non connect
O
Non connect
O
Power supply
Chip select signal for EEPROM
O
Clock signal for EEPROM
O
Input data for EEPROM
I
Output data for EEPROM
O
Power supply
Communication clock
I
Communication input data
I
Communication output data
O
Clock for ADSC serial
O
ADSC serial data input
I
ADSC serial data output
O
Non connect
Non connect
Non connect
Interrupt input of ADSC
I
Interrupt input of ODC
I
Interrupt input of ZIVA
I
Non connect
O
Non connect
I
Address data selection input
I
Reset input
I
Power supply
Test signal 1 input
I
Test signal 2 input
I
Test signal 3 input
I
Test signal 4 input
I
Test signal 5 input
I
Test signal 6 input
I
Test signal 7 input
I
Test signal 8 input
I
Power supply
Data bus 0 of CPU
I/O
Data bus 1 of CPU
I/O
Data bus 2 of CPU
I/O
Data bus 3 of CPU
I/O
Data bus 4 of CPU
I/O
Data bus 5 of CPU
I/O
Data bus 6 of CPU
I/O
Data bus 7 of CPU
I/O
1-36
Page 37
MN103007BGA (IC301) : Optical disc controller
1.Terminal layout
DMARQ
NIOWR
VSS
NIORD
IORDY
NDMACK
5VDD
INTRQ
IOCS16
DA1
VSS
NPDIAG
DA0
DA2
VDD
NCS1FX
NCS3FX
NDASP
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
HDD15
HDD0
HDD14
5VDD
HDD1
HDD13
HDD2
VSS
HDD12
VDD
HDD3
HDD11
HDD4
HDD10
5VDD
HDD5
HDD9
VSS
HDD6
HDD8
HDD7
5VDD
NRESET
MASTER
NINT0
NINT1
WAITOOC
NMRST
DASPST
VDD
OSCO2
OSCI2
UATASEL
VSS
PVSSDRAM
PVDDDAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
3738394041424344454647484950515253545556575859606162636465666768697071
127
MN103007BGA
NTRYCL
126
5VDD
NEJECT
125
124
VSS
123
MONI0
MONI1
122
121
MONI2
MONI3
120
119
SDATA
118
SCLOCK
VDD
FAT0
117
116
115
DAT1
114
DAT2
113
DAT3
112
CHCK4
XCLDCK
111
110
SUBC
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
SBCK
VSS
P0
P1
PVDD
PVSS
VDD
OSC01
OSCI1
VSS
LRCK
BLKCK
IPFLAG
DACCLK
DACLRCK
DA C DATA
NTRON
LG
JMPINH
IDDHOLD
PLLOK
CLKOUT2
VDD
NRST
MMOD
VSS
CPDET1
CPDET2
BDO
IDGT
DTRO
TEHLD
VDD
CLKOUT1
CPUDT0
CPUDT1
TH-A10
2.Block diagram
DVD-ROM
Formatter
CGEN
MODE
VSS
CPUASR15
CPUNDA17
CPUADR16
CD-PRE
Instruction
memory
(40KB)
DATA
MEMORY
(6KB)
VDD
CPUADR9
CPUADR8
CPUADR11
CPUADR10
Formatter
CPUADR7
i /t
CPUADR14
CPUADR13
CPUADR12
General purpose IO bus
VSS
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
High speed IO bus
32 bit
CPU core
GCAL
NCS
CPUADR0
ECC
NWR
NRD
VDD
CPUDT17
CPUDT16
PVPODRAM
PTESTORAM
Host i / f
MPEG i / t
DMA
BCU
DRAMC
CPUDT15
PVSSDRAM
OVDDDRAM
VSS
CPUDT14
CPUDT13
CPUDT2
ATAPI
4Mbit
DRAM
WDT
16 bit
timer x 2
SYSTEM
i / f
INTC
1-37
Page 38
TH-A10
3.Function
Pin NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Symbol
HDD15
HDD0
HDD14
5VDD
HDD1
HDD13
HDD2
VSS
HDD12
VDD
HDD3
HDD11
HDD4
HDD10
5VDD
HDD5
HDD9
VSS
HDD6
HDD8
HDD7
5VDD
NRESET
MASTER
NINT0
NINT1
WAITODC
NMRST
DASPST
VDD
OSCO2
OSCI2
UATASEL
VSS
PVSSDRAM
PVDODRAM
CPUADR17
CPUADR18
VSS
CPUADR15
CPUADR14
CPUADR13
CPUADR12
VDD
CPUADR11
CPUADR10
CPUADR9
I/O
Function
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I
ATAPI reset
I/O
ATAPI master / slave selection
O
System control interruption 0
O
System control interruption 1
O
System control weight control
O
System control reset
I
DASP signal initializing
I,O
VSS connection,OPEN
I,O
VSS connection, OPEN
I
VSS connection
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
System control address
I
System control address
I
System control address
I
System control address
Pin NO.
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Symbol
CPUADR8
CPUADR7
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
VSS
CPUADR0
NCS
NWR
NRD
VDD
CPUDT7
CPUDT6
PVPPDRAM
PTESTDRAM
OVDDDRAM
PVSSDRAM
CPUDT5
CPUDT4
CPUDT3
VSS
CPUDT2
CPUDT1
CPUDT0
CLKOUT1
VDD
TEHLD
DTRO
IDGT
BDO
CPDET2
CPDET1
VSS
MMOD
NRST
VDD
CLKOUT2
PLLOK
IDOHOLD
JMPINH
MN103007BGA(1/2)
I/O
Function
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
GND
System control address
I
System control chip selection
I
System control wright
I
System control lead
I
Apply 3V
System control data
System control data
C=10000PF is connected
O
between VSS
VSS connected
I
System control data
System control data
System control data
GND
System control data
System control data
I/O
System control data
I/O
16.9/11.2/8.45MHz clock
O
Apply 3V
-
Mirror gate
O
Data part frequency control
O
switch
Part CAPA switch
O
RF dropout / BCA data of
I
making to binary
Outer side CAPA detection
I
Side of surroundings on inside
I
GND
VSS connected
I
System reset
I
Apply 3V
-
16.9MHz clock
O
Frame mark detection
O
ID gate for tracking holding
O
Jump prohibition
O
1-38
Page 39
MN103007BGA(2/2)
TH-A10
Pin NO.
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119~122
123
124
125
126
127
128
129
130
131
132
Symbol I/O Function
LG
NTRON
DAC D ATA
DACLRCK
DACCLK
IPFLAG
BLKCK
LRCK
VSS
OSCI1
OSCO1
VDD
PVSS
PVDD
P1
P0
VSS
SBCK
SUBC
XCLDCK
CHCK4
DAT3
DAT2
DAT1
DAT0
VDD
SCLOCK
S DATA
MONI3~0
VSS
NEJECT
5VDD
NTRYCL
NDASP
NCS3FX
NCS1FX
VDD
DA2
DA0
O
Land / group switch
I
Tracking ON
O
Cereal output
O
L and R identification output
I
Clock for cereal output
I
Interpolation flag input
I
Sub-code,Block clock input
I
L and R identification signal output
I,O
16.9MHz oscillation
I,O
16.9MHz oscillation
I/O
Terminal MASTER polarity switch
input
I/O
CIRC-RAM OVER/UNDER
Interruption signal input
O
Sub-code, Clock output for serial input
I
Sub-code, Cereal input
I
Sub-code, Frame clock input
I
Read clock to DAT3~0(Output of
dividing frequency four from ADSC)
I
Read data from DISC
I
(PAralle output from ADSC)
I
I
I/O
Debugging cereal clock
(270 pull up)
I/O
Debugging cereal data
(270 pull up)
O
Internal goods title monitor
I
Eject detection
I
Tray close detection
I/O
ATAPI Drive active/
Sulave connection I/O
I
ATAPI host chip selection
I
ATAPI host chip selection
I/O
ATAPI host address
I/O
ATAPI host address
Pin NO.
133
134
135
136
137
138
139
140
141
142
143
144
Symbol I/O Function
I/O
NPDIAG
VSS
DA1
IOCS16
INTRQ
5VDD
NDMACK
IORDY
NIORD
VSS
NIOWR
DMARQ
ATAPI slave master diagnosis input
I/O
ATAPI host address
O
ATAPI output of selection of width
of host data bus
O
ATAPI host interruption output
I
ATAPI host DMA response
O
ATAPI host ready output
I
ATAPI host read
I/O
ATAPI host writes
O
ATAPI host DMA demand
1-39
Page 40
TH-A10
MN103007BGA(3/4)
Pin NO.
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Symbol I/O Function
LG
NTRON
DAC D ATA
DACLRCK
DACCLK
IPFLAG
BLKCK
LRCK
O
Land / group switch
I
Tracking ON
O
Cereal output
O
L and R identification output
I
Clock for cereal output
I
Interpolation flag input
I
Sub-code,Block clock input
I
L and R identification signal output
VSS
OSCI1
OSCO1
I,O
16.9MHz oscillation
I,O
16.9MHz oscillation
VDD
PVSS
PVDD
P1
P0
I/O
Terminal MASTER polarity switch input
I/O
CIRC-RAM OVER/UNDER
Interruption signal input
VSS
SBCK
SUBC
XCLDCK
CHCK4
O
Sub-code, Clock output for serial input
I
Sub-code, Cereal input
I
Sub-code, Frame clock input
I
Read clock to DAT3~0
(Output of dividing frequency four from ADSC)
DAT3
DAT2
DAT1
I
Read data from DISC
I
(PAralle output from ADSC)
I
DAT0
VDD
SCLOCK
I/O
Debugging cereal clock
(270 pull up)
S DATA
I/O
Debugging cereal data
(270 pull up)
MONI3
MONI2
MONI1
MONI0
O
Internal goods title monitor
O
O
O
VSS
NEJECT
I
Eject detection
5VDD
NTRYCL
NDASP
I
Tray close detection
I/O
ATAPI Drive active/
Sulave connection I/O
NCS3FX
NCS1FX
I
ATAPI host chip selection
I
ATAPI host chip selection
VDD
DA2
DA0
I/O
ATAPI host address
I/O
ATAPI host address
1-40
Page 41
MN103007BGA(4/4)
TH-A10
Pin NO.
133
134
135
136
137
138
139
140
141
142
143
144
Symbol I/O Function
NPDIAG
I/O
ATAPI slave master diagnosis input
VSS
DA1
IOCS16
INTRQ
I/O
ATAPI host address
O
ATAPI output of selection of width of host data bus
O
ATAPI host interruption output
5VDD
NDMACK
IORDY
NIORD
I
ATAPI host DMA response
O
ATAPI host ready output
I
ATAPI host read
VSS
NIOWR
DMARQ
I/O
ATAPI host writes
O
ATAPI host DMA demand
1-41
Page 42
TH-A10
MN67705EA (IC201) : Digital servo controller
1.Terminal layout
FEPNTRON
N.C.
N.C.
CDDVD
N.C.
N.C.
N.C.
ECR(PWM3B)
EC(PWM3A)
DVS S
128
127
126
125
124
123
122
121
120
119
FGC
1
LDONA
2
LDONB
3
PULIN
4
SRF
5
DVSS
DVDD
TRVSW
ST/SP
HFMON
BRK
DVSS
PLLOK
N.C.
N.C.
N.C.
N.C.
DVSS
DVDD
TSTSG
FUPDN
MONA
MONB
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33343536373839404142434445464748495051525354555657585960616263
CPSEN
CPCEN
CPUIRQ
CPUCLK
CPUDTIN
MN67705
CHK4I
SCLK-
SDAT+
SCLK+
CPUDTOUT
TRAYSET1
TRAYSET2
DRVMUTE
TRAY-CLOSE
TRAY-OPEN
TBAL(PWMDA1)
GBAL(PWMDA2)
BDOLVL(PWMDA3)
OFTLVL(PWMDA4)
SYSCLK
VCOF1
DVS S
118
117
116
BDO
SDAT-
SBCK
IREF1
XRESET
115
114
N.C.
N.C.
TEST
MINTESTFGDSLO
113
112
111
N.C.
N.C.
DVS S
TKCRS2
110
109
DVS S
DVD D
TKCRS1
OFTR
DVD D
108
107
106
SUBC
MONC
BLKCLK
TRSDRVB(DA8)
TRSDRVA(DA7)
TRDRV(DA6)
105
104
103
LRCK
NTRON
NCLDCK
FODRV(DA5)
102
DVS S
DBAL(DA4)
101
DAT0
BOOST(DA3)
FC(DA2)
999897
100
DAT1
DAT2
FBAL(DA1)
AVD D
64
DAT3
CHCK4
AVSS
96
TS(AD1)
95
FS(AD2)
94
FE(AD3)
93
TROFS(AD4)
92
TE(AD5)
91
VREFLDA
90
VREFMDA
89
VREFHDA
88
TG(AD6)
87
N.C.(AD7)
86
N.C.(AD8)
85
RFENV(AD9)
84
VREFOP
83
LDCUR(AD10)
82
JITOUT(AD11)
81
VREFC
80
AVDD(AD12)
79
VREFHAD
78
VREFMAD
77
VREFLAD
76
AVSS
75
DVDD
74
DVSS
73
TX
72
MOND
71
IPFLAG
70
CIRCIRQ
69
N.C.
68
N.C.
67
N.C
66
DVSS
65
2.Block diagram
The signal of the error
of the servo input
from FEP.
Driver
ODC
A/Dconverter
Track crossing
counter
Phese
comparison
Line speed
detection
Detection at
FG cycle
CIRC core
Focus servo
Tracking servo
Traverse servo
Spindle servo
SERVO
DSP core
Serial port
CPU I/F
PLL
A/D converter
(Analog control)
PWM
Standard
clock
generation
PLL
FEP I/F
PLL
Focus tracking
driving value output
Spindre / traverse
driving value output
Crystal
33.8MHz
FEP
1-42
CPU
ADSC function block of the second generation.
Page 43
TH-A10
3.Pin function
Pin No. Symbol I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
FGC
LDONA
LDONB
PULIN
SRF
DVSS
TRAYSET1
TRAYSET2
DRVMUTE
DVDD
TRVSW
TRAY-CLOSE
TRAY-OPEN
ST/SP
HFMON
BRK
DVSS
PLLOK
N.C.
TBAL(PWMDA 1)
GBAL(PWMDA2)
BDOLVL(PWMDA3)
OFTLVL(PWMDA4)
N.C.
N.C.
N.C.
DVSS
DVDD
TSTSG
FUPDN
MONA
MONB
CPSEN
CPCEN
CPUIRQ
CPUCLK
CPUDTIN
CPUDTOUT
CHK4I
SCLK+
SCLK-
SDAT+
SDAT-
BDO
SBCK
IREF2
Function
0
H fixation
O
Laser drive controlA (ON / OFF)
O
Laser drive controlB (ON / OFF)
O
DSL and PLL high boost signal (FEP)
O
Head amplifier gain H/L selection
Ground for digital circuit
O
Tray drive ON/OFF and direction control
O
Tray drive ON/OFF and direction control
O
Drive IC mute control
Power supply for digital circuit
I
Surroundings position detection in traverse
I
Tray close detection SW
I
Tray opening detection SW
O
Spindle motor drive switch (START /STOP)
O
High cycle module control
O
Spindle motor IC short brake control
Ground for digital circuit
I
SYNC detection (DVD : 18T / CD : 22T)
O
O
Tracking balance (FEP)
O
Tangential balance (FEP)
O
BDO slice level (FEP)
O
Off-track error slice level (FEP)
O
O
O
Ground for digital circuit
Power supply for digital circuit
O
Self calibration signal (FEP)
O
Signal of frequency UP/DOWN of PLL (FEP)
O
Monitor terminal A
O
Monitor terminal B
I
Servo DSP cereal I/F chip selection (SYSCOM)
I
CIRC cereal I/F chip selection (SYSCOM)
O
Interrupt request to silicon (SYSCOM)
I
Silicon cereal I/F clock (SYSCOM)
I
Silicon cereal I/F data input (SYSCOM)
O
Silicon cereal I/F data output (SYSCOM)
I
Connects with unused DVSS
I
Lead channel clock differential motion signal (positive)
I
Lead channel clock differential motion signal (negative)
I
Lead channel data differential motion signal (positive)
I
Lead channel data differential motion signal (negative)
I
BDO + BCA (FEP)
I
CD sub-code data shift clock (ODC)
Connects with unused DVSS
MN67705EA (1/3)
1-43
Page 44
TH-A10
Pin No. Symbol I/O
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
IREF3
VCOF2
DVSS
VCOE3
DVSS
DVDD
SUBC
BLKCLK
MONC
NCLDCK
LRCK
NTRON
DVSS
DAT0
DAT1
DAT2
DAT3
CHCK4
DVSS
DACCLK
DACLRCK
DAC D ATA
CIRCIRQ
IPFLAG
MOND
TX
DVSS
DVDD
AVSS
VREFLAD
VREFMAD
VREFHAD
AVDD
VREFC(AD12)
JIOUT(AD11)
LDCUR(AD10)
VREFOP
RFENV(AD9)
N.C.(AD8)
N.C.(AD7)
TG(AD6)
VREFHDA
VREFMDA
VREFLDA
TE(AD5)
TROFS(AD4)
FE(AD3)
Function
Connects with unused DVSS
Connects with unused DVSS
Ground for digital circuit
Connects with unused DVSS
Ground for digital cirucuit
Power supply for digital cirucuit
CD sub-code (ODC)
O
CD sub-code synchronous signal (ODC)/Jump output of one at DVD
O
Monitor terminal C
O
Sub-code data freme clock (ODC)
O
LR channnel data strove circCIRC(ODC)
O
L: Tracking ON (ODC)
O
Ground for digital cirucuit
CIRC / Binary making DVD data output
O
CIRC / Binary making DVD data output
O
CIRC / Binary making DVD data output
O
CIRC / Binary making DVD data output
O
Synchronous clock of DAT0 3
O
Ground for digital circuit
O
Connects with unused DVSS
I
Connects with unused DVSS
I
RAM with built-in CIRC exceeds / Underflow interrupt
O
CIRC error flag
O
Monitor terminal D
O
Digital audio interface
O
Ground for digital cirucuit
Power supply for digital cirucuit
Ground for analog cirucuit
AD subordinate position standard voltage (0.6 0.1v)
It is a place standard voltage in AD (1.4 0.1V)
High-ranking AD standard voltage (2.2 0.1V)
Power supply for analog circuit
I
signal(FEP)
Jitter
I
Laser drive current signal
I
Operation amplifier standard voltage(VREFC)
RFENV(FEP)
I
Connects with VREFC
I
Connects with VREFC
I
Tangential Phase difference (FEP)
I
High-ranking AD standard voltage (2.2 0.1V)
It is a place standard voltage in AD (1.4 0.1V)
AD subordinate position standard voltage (0.6 0.1v)
Tracking error (FEP)
I
Tracking drive IC input offset
I
Focus error (FEP)
I
MN67705EA (2/3)
1-44
Page 45
Pin No. Symbol I/O
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
FS(AD2)
TS(AD1)
AVSS
AVDD
FBAL(DA1)
FC(DA2)
BOOST(DA3)
TBAL(DA4)
FODRV(DA5)
TRDRV(DA6)
TRSDRVA(DA7)
TRSDRVB(DA8)
DVDD
OFTR
TKCRS1
TKCRS2
DSLO
FG
MINTEST
TEST
XRESET
IREF1
DVSS
VCOF1
SYSCLK
DVSS
EC(PWM3A)
ECR(PWM3B)
N.C.(PWM3A)
N.C.(PWM2B)
N.C.(PWM1A)
CDDVD
N.C.(PWM0A)
N.C.(PWM0B)
FEPNTRON
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function
FS (FEP)
I
TS (FEP)
I
Ground for analog cirucuit
Power supply for analog circuit
Focus balance(FEP)
Cutting off frequency (FEP)
Amount of boost (FEP)
DSL offset balance (FEP)
Focus drive
Tracking drive
Traverse drive A aspect
Traverse drive B aspect
Power supply for digital cirucuit
I
Off-track error signal (FEP)
I
Track crossing signal 1 (FEP)
I
Track crossing signal 2 (FEP)
I
Binary making data slice signal (FEP)
I
FG signal input (spindle motor driver)
Connects with DVSS
Connects with DVSS
I
Reset L : Reset
VCO reference current 1( for SYSCLK)
Ground for digital circuit)
VCO control voltage 1 (for SYSCLK)
I
33.8MHz system clock input
Ground for digital circuit
Spindle motor drive
CD/DVD control signal (FEP) CD : H DVD : L
Tracking ON (FEP)
TH-A10
MN67705EA(3/3)
1-45
Page 46
TH-A10
STK402-030 (IC301) :
1.Pin layout
115
2.Block diagram
4
R1
TR7
8
TR9
R13
TR4
R6
C1
1
TR1
2
TR3
R2
TR2
D1
SUB
R3
R4
R5
13
TR5
TR6
TR8
R7
1256710
TR10
11
R8
TR12
TR13
R9
TR11
R10
C2
R11
R12
TR14 TR15
TR16
R14
9
14
15
1-46
Page 47
TH-A10
TC74VHC00FT-X (IC503) : Wright timing control
1.Terminal layout / Block diagram
Vcc 4B 4A 4Y 3B 3A 3Y
14 13
1
12
11 10 9 8
2
6
543
7
1A 1B 1Y 2A 2B 2Y GND
TC7SH32FU-X (IC312) : Timing control
1.Terminal layout
TC74VHC08FT-X (IC420) : NAND gate
1. Pin layout & Block diagram
1A 1
1B 2
1I 3
2A 4
2B 5
2Y 6
GND 7
14 Vcc
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
TC7SHU04FU-X (IC371,IC372): Clock generator
1. Terminal layout
IN B
IN A
GND
1
VCC
5
2
3
4
OUT Y
TC7SH08FU-X(IC311) : Timing control
1.Terminal layout
IN B
IN A
GND
1
2
3
5
4
VCC
OUT Y
IN B
IN A
GND
1
VCC
5
2
3
4
OUT Y
1-47
Page 48
TH-A10
TC7W125FU-X (IC452) : Buffer
1. Terminal layout
2. Block diagram
1
G1
2
A1
3
Y2
GND
4
TC7WH74FU-X (IC374) : Clock buffer
1.Terminal layout
2.Block diagram
8
Vcc
7
C2
6
Y1
5
A2
GND
CK
D
Q
1
2
3
4
8
VCC
7
PR
6
CLR
5
Q
1-48
Page 49
UPD42280GU-30-X (IC552) : 2M FRAM
TH-A10
1.Terminal Layout
DI
DI
DI
DI
WE
GND
TEST
WRST
WCK
V
DI
DI
0
1
2
3
DD
4
5
1
2
3
4
5
6
7
8
9
10
11
12
28
26
25
24
UPD42280GU-XX
23
22
21
20
19
18
17
2.Pin Function
5
6
7
8
9
Symbol
DI0~DI3
WE
GND
TEST
WRST
WCK
V
DD
DI4~DI7
DO7~DO4
V
DD
RCK
RRST
OE
GND
RE
DO3~DO1
I/O Function
Data input
I
Write enable input
I
Connect to GND
-
Connect to GND
-
Write reset input
I
Write clock input
I
Powre supply +5V
-
Data input
I
Data output
O
Power supply +5V
-
Read clock input
I
Read reset input
I
Output enable input
I
Connect to GND
-
Read enable input
I
Data output
O
Pin No.
DO
0
27
DO
DO
DO
RERE
GND
OE
1
2
3
1~4
10
11~14
15~18
19
20
21
RRST
RCK
22
23
24
V
DO
DO
DD
4
5
25~28
DI
6
DI
7
13
14
3.Block diagram
Refresh timer
WCK
RCK
Controller
WRST
RRST
WE
RE
OE
Timing
generator
Write
Address
counter
Read
Address
counter
Reflesh
Address
counter
16
15
DO
6
DO
7
Write Address pointer
Write Date registor
Address selector
Read Date registor
Write Address pointer
Write Date registor
8
256K
Memory cell array
Read Date registor
Read Date registor
DI
0~7
Buffer
input
8
80
SRAM Buffer
Buffer
output
Read Address pointer Read Address pointer
DO
0~7
1-49
Page 50
TH-A10
3.Function
Pin NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Symbol
HDD15
HDD0
HDD14
5VDD
HDD1
HDD13
HDD2
VSS
HDD12
VDD
HDD3
HDD11
HDD4
HDD10
5VDD
HDD5
HDD9
VSS
HDD6
HDD8
HDD7
5VDD
NRESET
MASTER
NINT0
NINT1
WAITODC
NMRST
DASPST
VDD
OSCO2
OSCI2
UATASEL
VSS
PVSSDRAM
PVDODRAM
CPUADR17
CPUADR18
VSS
CPUADR15
CPUADR14
CPUADR13
CPUADR12
VDD
CPUADR11
CPUADR10
CPUADR9
I/O
Function
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I/O
ATAPI data
I
ATAPI reset
I/O
ATAPI master / slave selection
O
System control interruption 0
O
System control interruption 1
O
System control weight control
O
System control reset
I
DASP signal initializing
I,O
VSS connection,OPEN
I,O
VSS connection, OPEN
I
VSS connection
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
System control address
I
System control address
I
System control address
I
System control address
Pin NO.
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Symbol
CPUADR8
CPUADR7
CPUADR6
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1
VSS
CPUADR0
NCS
NWR
NRD
VDD
CPUDT7
CPUDT6
PVPPDRAM
PTESTDRAM
OVDDDRAM
PVSSDRAM
CPUDT5
CPUDT4
CPUDT3
VSS
CPUDT2
CPUDT1
CPUDT0
CLKOUT1
VDD
TEHLD
DTRO
IDGT
BDO
CPDET2
CPDET1
VSS
MMOD
NRST
VDD
CLKOUT2
PLLOK
IDOHOLD
JMPINH
MN103007BGA(1/2)
I/O
Function
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
I
GND
System control address
I
System control chip selection
I
System control wright
I
System control lead
I
Apply 3V
System control data
System control data
C=10000PF is connected
O
between VSS
VSS connected
I
System control data
System control data
System control data
GND
System control data
System control data
I/O
System control data
I/O
16.9/11.2/8.45MHz clock
O
Apply 3V
-
Mirror gate
O
Data part frequency control
O
switch
Part CAPA switch
O
RF dropout / BCA data of
I
making to binary
Outer side CAPA detection
I
Side of surroundings on inside
I
GND
VSS connected
I
System reset
I
Apply 3V
-
16.9MHz clock
O
Frame mark detection
O
ID gate for tracking holding
O
Jump prohibition
O
1-50
Page 51
Pin Function (2/3)
TH-A10
Pin No. Pin No.
Symbol Symbol
51
ARAM-ADDR14
52
TEST-PIN1
53
M-DATA15
54
M-DATA0
55
E-VDD
56
M-DATA14
57
E-VSS
58
M-DATA1
59
M-DATA13
60
M-DATA2
61
E-VDD
62
M-DATA12
63
E-VSS
64
M-DATA3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
I-VDD
M-DATA11
I-VSS
M-DATA14
E-VDD
M-DATA10
E-VSS
M-DATA5
M-DATA9
M-DATA6
E-VDD
M-DATA8
E-VSS
M-DATA7
LDQM
UDQM
E-VDD
MWE
E-VSS
SD-CLK
SD-CAS
SD-RAS
E-VDD
SD-CS1
E-VSS
SD-CSO
I-VDD
EDO-CAS
I-VSS
EDO-RAS
E-VDD
M-ADDR9
I/O I/O
Connect to TP564
Test pin
Data bus I/O to IC508,IC504
I/O
Data bus I/O to IC508,IC504
I/O
Power supply
Data bus I/O to IC508,IC504
I/O
Connect to GND
Data bus I/O to IC508,IC504
I/O
Data bus I/O to IC508,IC504
I/O
Data bus I/O to IC508,IC504
I/O
Power supply
Data bus I/O to IC508,IC504
I/O
Connect to GND
Data bus I/O to IC508,IC504
I/O
Power supply
Data bus I/O to IC508,IC504
I/O
Connect to GND
Data bus I/O to IC508,IC504
I/O
Power supply
Data bus I/O to IC508,IC504
I/O
Connect to GND
Data bus I/O to IC508,IC504
I/O
Data bus I/O to IC508,IC504
I/O
Data bus I/O to IC508,IC504
I/O
Power supply
Data bus I/O to IC508,IC504
I/O
Connect to GND
Data bus I/O to IC508,IC504
I/O
Lower DQ mask enable
O
Upper DQ mask enable
O
Power supply
Write enable
O
Connect to GND
System clock signal output
O
column address strobe
O
Row address strobe
O
Power supply
Chip select output to IC508
O
Connect to GND
Chip select output to IC504
O
Power supply
Connect to TP511
Connect to GND
Connect to TP512
Power supply
Address output to IC508,504
O
Function
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
E-VSS
M-ADDR11
M-ADDR8
M-ADDR10
E-VDD
M-ADDR7
E-VSS
M-ADDR0
M-ADDR6
M-ADDR1
E-VDD
M-ADDR5
E-VSS
M-ADDR2
M-ADDR4
M-ADDR3
E-VDD
M-ADDR12
E-VSS
M-ADDR13
I-VDD
M-ADDR14
I-VSS
M-ADDR15
M-ADDR16
M-ADDR17
E-VDD
M-ADDR18
E-VSS
M-ADDR19
M-ADDR20
ROM-CS
TEST-PIN2
OSD-CLK
OSD-DATA0
OSD-DATA1
TEST-PIN3
E-VDD
OSD-DATA2
E-VSS
OSD-DATA3
TEST-PIN4
OSD-BLK1
OSDVC1
TEST-PIN5
V DATA 0
Function
Connect to GND
Address output to IC508,504
O
Address output to IC508,504
O
Address output to IC508,504
O
Power supply
Address output to IC508,504
O
Connect to GND
Address output to IC508,504
O
Address output to IC508,504
O
Address output to IC508,504
O
Power supply
Address output to IC508,504
O
Connect to GND
Address output to IC508,504
O
Address output to IC508,504
O
Address output to IC508,504
O
Power supply
Connect to TP513
Connect to GND
Connect to TP514
Power supply
Connect to TP515
Connect to GND
Connect to TP516
Connect to TP517
Connect to TP518
Power supply
Connect to TP519
Connect to GND
Connect to TP520
Connect to TP521
Connect to TP522
Test pin
Connect to TP523
Connect to TP525
Connect to TP526
Test pin
Power supply
Connect to TP528
Connect to GND
Connect to TP529
Test pin
Connect to TP531
Connect to TP532
Test pin
DVD image signal output
O
1-51
Page 52
TH-A10
Pin Function (3/3)
Pin No. Pin No.
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
Symbol Symbol
V DATA 1
I-VDD
V DATA 2
I-VSS
TEST-PIN6
V DATA 3
E-VDD
V DATA 4
E-VSS
V DATA 5
TEST-PIN7
V DATA 6
V DATA 7
TEST-PIN8
HSYNC
VSYNC
IEC-958
E-VDD
DA-DATA0
E-VSS
DA-DATA1
DA-DATA2
DA-DATA3
DA-LRCK
DA-BCK
I-VDD
DA-XCK
I-VSS
DAI-DATA
DAI-LRCK
DAI-BCK
TEST-PIN9
CLK-SEL
I/O I/O
O
DVD image signal output
-
Power supply
O
DVD image signal output
-
Connect to GND
-
Test pin
O
DVD image signal output
-
Power supply
O
DVD image signal output
-
Connect to GND
O
DVD image signal output
-
Test pin
O
DVD image signal output
O
DVD image signal output
-
Test pin
I/O
Horizontal synchronous signal output
I/O
Vertical synchronous signal output
O
Digital audio data output
-
Power supply
O
Data output to IC702
-
Connect to GND
O
Data output to IC702
O
Data output to IC702
O
Data output to IC702
O
L/R clock output to IC702
O
Bit clock output to IC702
-
Power supply
-
Non connect
-
Connect to GND
-
Connect to TP501
I
L/R clock input from IC702
I
Bit clock input from IC702
-
Test pin
-
Connect to GND
Function
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
A-VDD
VCLK
SYSCLK
A-VSS
DVD-DATA0
E-VDD
DVD-DATA1
E-VSS
DVD-DATA2
DVD-DATA3
DVD-DATA4
DVD-DATA5
DVD-DATA6
DVD-DATA7
TEST-PIN10
V-REQUEST
V-STROBE
I-VDD
A-REQUEST
I-VSS
V-DAC K
E-VDD
SECT-SYNC
E-VSS
ERROR
HOST-SEL
HADDR0
HADDR1
HADDR2
DTACK-SEL
CS
R/W
RD
Function
Connect to TP507
Dot clock signal output (27MHz)
I/O
Connect to TP505
Connect to GND
ATAPI data I/O to IC301
I
Power supply
ATAPI data I/O to IC301
I
Connect to GND
ATAPI data I/O to IC301
I
ATAPI data I/O to IC301
I
ATAPI data I/O to IC301
I
ATAPI data I/O to IC301
I
ATAPI data I/O to IC301
I
ATAPI data I/O to IC301
I/O
Test pin
-
Master/Sleave Selection for ATAPI
O
Host address for ATAPI
I
Power supply
Connect to TP539
Connect to GND
Host interrupt input for ATAPI
I
Power supply
Host write for ATAPI
I
Connect to GND
Connect to GND
Connect to GND
System control address input
I
System control address input
I
System control address input
I
Connect to GND
Chip select for ZIVA
I
Write enable
I
Read enable
I
1-52
Page 53
VICTOR COMPANY OF JAPAN, LIMITED
AUDIO & COMMUNICATION BUSINESS DIVISION
PERSONAL & MOBILE NETWORK B.U. 10-1,1Chome,Ohwatari-machi,Maebashi-city,371-8543,Japan
No.20890
Printed in Japan
200101(S)
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