JVC MX-DVA9R, SP-MXG79, SP-DSC99TN, SP-DSS99TN, CA-MXDVA9R Service Manual

MX-DVA9/MX-DVA9R

SERVICE MANUAL

COMPACT COMPONENT SYSTEM

MX-DVA9/MX-DVA9R

Contents

Area suffix

MX-DVA9R

B -------------------------- U.K.
EN ------- Northern Europe

SP-MXG79 CA-MXDVA9/CA-MXDVA9R SP-MXG79

Area suffix

MX-DVA9

A ------------------------- Australia

US ---------------------- Singapore

(SP-DSC99TN)

Center unit Speaker unit
CA-MXDVA9/CA-MXDVA9R SP-MXDVA9/SP-MXDVA9R
SP-MXG79(Front speaker)
SP-DSC99TN(Center speaker)
SP-DSS99TN(Surround speaker)

(SP-DSS99TN)

UW ---------- Brazil,Mexico,Peru
UJ --------------------- U.S.Military
UG - Turkey,South Africa,Egypt
UN ----------------------------Asean

Safety Precautions
Preventing static electricity
Precautions for service
Important for laser products
Disassembly method

COPYRIGHT 2001 VICTOR COMPANY OF JAPAN, LTD.

1-2
1-4
1-5
1-6
1-7

Adjustment method
Flow of functional operation until Toc read
Maintenance of laser pickup
Replacement of laser pickup
Description of major ICs

1-28
1-34
1-35
1-35
1-36

No.21040
Oct. 2001

MX-DVA9/MX-DVA9R

1. This design of this product contains special hardware and many circuits and components specially for safety
purposes. For continued protection, no changes should be made to the original design unless authorized in
writing by the manufacturer. Replacement parts must be identical to those used in the original circuits. Services
should be performed by qualified personnel only.

2. Alterations of the design or circuitry of the product should not be made. Any design alterations of the product
should not be made. Any design alterations or additions will void the manufacturer`s warranty and will further
relieve the manufacture of responsibility for personal injury or property damage resulting therefrom.

3. Many electrical and mechanical parts in the products have special safety-related characteristics. These

characteristics are often not evident from visual inspection nor can the protection afforded by them necessarily
be obtained by using replacement components rated for higher voltage, wattage, etc. Replacement parts which
have these special safety characteristics are identified in the Parts List of Service Manual. Electrical
components having such features are identified by shading on the schematics and by ( ) on the Parts List in
the Service Manual. The use of a substitute replacement which does not have the same safety characteristics
as the recommended replacement parts shown in the Parts List of Service Manual may create shock, fire, or
other hazards.

4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the like to be
separated from live parts, high temperature parts, moving parts and/or sharp edges for the prevention of
electric shock and fire hazard. When service is required, the original lead routing and dress should be
observed, and it should be confirmed that they have been returned to normal, after re-assembling.

5. Leakage currnet check (Electrical shock hazard testing)
After re-assembling the product, always perform an isolation check on the exposed metal parts of the product
(antenna terminals, knobs, metal cabinet, screw heads, headphone jack, control shafts, etc.) to be sure the
product is safe to operate without danger of electrical shock.
Do not use a line isolation transformer during this check.

Plug the AC line cord directly into the AC outlet. Using a "Leakage Current Tester", measure the leakage
current from each exposed metal parts of the cabinet, particularly any exposed metal part having a return
path to the chassis, to a known good earth ground. Any leakage current must not exceed 0.5mA AC (r.m.s.).

Alternate check method
Plug the AC line cord directly into the AC outlet. Use an AC voltmeter having, 1,000 ohms per volt or more
sensitivity in the following manner. Connect a 1,500 10W resistor paralleled by a 0.15 F AC-type capacitor
between an exposed metal part and a known good earth ground.
Measure the AC voltage across the resistor with the AC
voltmeter.
Move the resistor connection to each exposed metal part,
particularly any exposed metal part having a return path to
the chassis, and meausre the AC voltage across the resistor.
Now, reverse the plug in the AC outlet and repeat each
measurement. Voltage measured any must not exceed 0.75 V
AC (r.m.s.). This corresponds to 0.5 mA AC (r.m.s.).

0.15 F AC TYPE

1500 10W

Good earth ground

AC VOLTMETER
(Having 1000
ohms/volts,
or more sensitivity)

Place this
probe on
each exposed
metal part.

!

1. This equipment has been designed and manufactured to meet international safety standards.

2. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.

3. Repairs must be made in accordance with the relevant safety standards.

4. It is essential that safety critical components are replaced by approved parts.

5. If mains voltage selector is provided, check setting for local voltage.

Burrs formed during molding may
be left over on some parts of the
chassis. Therefore, pay attention to
such burrs in the case of
preforming repair of this system.

In regard with component parts appearing on the silk-screen printed side (parts side) of the PWB diagrams, the
parts that are printed over with black such as the resistor ( ), diode ( ) and ICP ( ) or identified by the " "
mark nearby are critical for safety.
When replacing them, be sure to use the parts of the same type and rating as specified by the manufacturer.
(Except the J and C version)

1-2

MX-DVA9/MX-DVA9R

(U.K only)

1. This design of this product contains special hardware and many circuits and components specially
for safety purposes. For continued protection, no changes should be made to the original
design unless authorized in writing by the manufacturer. Replacement parts must be identical to
those used in the original circuits.

2. Any unauthorised design alterations or additions will void the manufacturer's guarantee ; furthermore the
manufacturer cannot accept responsibility for personal injury or property damage resulting therefrom.

3. Essential safety critical components are identified by ( ) on the Parts List and by shading on the
schematics, and must never be replaced by parts other than those listed in the manual. Please note

however that many electrical and mechanical parts in the product have special safety related
characteristics. These characteristics are often not evident from visual inspection. Parts other than
specified by the manufacturer may not have the same safety characteristics as the recommended
replacement parts shown in the Parts List of the Service Manual and may create shock, fire, or
other hazards.

4. The leads in the products are routed and dressed with ties, clamps, tubings, barriers and the
like to be separated from live parts, high temperature parts, moving parts and/or sharp edges
for the prevention of electric shock and fire hazard. When service is required, the original lead
routing and dress should be observed, and it should be confirmed that they have been returned
to normal, after re-assembling.

1. Service should be performed by qualified personnel only.

2. This equipment has been designed and manufactured to meet international safety standards.

3. It is the legal responsibility of the repairer to ensure that these safety standards are maintained.

4. Repairs must be made in accordance with the relevant safety standards.

5. It is essential that safety critical components are replaced by approved parts.

6. If mains voltage selector is provided, check setting for local voltage.

!

Burrs formed during molding may be left over on some parts of the chassis. Therefore,
pay attention to such burrs in the case of preforming repair of this system.

1-3

MX-DVA9/MX-DVA9R

Preventing static electricity

Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged,
can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs.

1.1. Grounding to prevent damage by static electricity

Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as DVD players.
Be careful to use proper grounding in the area where repairs are being performed.

1.1.1. Ground the workbench

1. Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over
it before placing the traverse unit (optical pickup) on it.

1.1.2. Ground yourself

1. Use an anti-static wrist strap to release any static electricity built up in your body.

(caption)
Anti-static wrist strap

Conductive material
(conductive sheet) or iron plate

1.1.3. Handling the optical pickup

1. In order to maintain quality during transport and before installation, both sides of the laser diode on the
replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition.
(Refer to the next page.)

2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power
source can easily destroy the laser diode.

1.2. Handling the traverse unit (optical pickup)

1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.

2. For specific details, refer to the replacement procedure in the text. Be careful not to take too long a time
when attaching it to the connector.

3. Handle the flexible cable carefully as it may break when subjected to strong force.

4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it

1-4

Precautions for service

Handling of Traverse Unit and Laser Pickup

1. Do not touch any peripheral element of the pickup or the actuator.

2. The traverse unit and the pickup are precision devices and therefore must not be subjected to
strong shock.

3. Do not use a tester to examine the laser diode. (The diode can easily be destroyed by the
internal power supply of the tester.)

4. When replacing the pickup, after mounting a new pickup, remove the solder on the short land
which is provided at the center of the flexible wire to open the circuit.

5. Half-fixed resistors for laser power adjustment are adjusted in pairs at shipment to match the
characteristics of the optical block.
Do not change the setting of these half-fixed resistors for laser power adjustment.

Destruction of Traverse Unit and Laser Pickup by Static Electricity

Laser diodes are easily destroyed by static electricity charged on clothing

or the human body. Before repairing peripheral elements of the traverse
unit or pickup, be sure to take the following electrostatic protection:

MX-DVA9/MX-DVA9R

1. Wear an antistatic wrist wrap.

2. With a conductive sheet or a steel plate on the workbench on which
the traverse unit or the pick up is to be repaired, ground the sheet
or the plate.

When you remove the traverse mechanism from the servo control substrate

The laser diode of pick-up might be destroyed by static electricity and set switch (S11) on the pick-up board
on "SHORT" side, please before removing the card wire from connector (CN10).
Moreover, please set switch (S11) on "OPEN" side after assembling and inserting the card wire in
connector (CN10) without fail at times.

Traverse

mechanism

CN10

CN12

SWITCH S11

SHORT

OPEN

When you remove the pick-up from the traverse mechanism

The laser diode of the pick-up might be destroyed by static electricity, and solder with part a, please before
extracting a flexible wire from connector (CN12).
Moreover, please remove solder in part a after inserting a flexible wire in connector (CN12).

Soldering part

Pick-up

Traverse
mechanism

1-5

MX-DVA9/MX-DVA9R

Important for laser products

1.CLASS 2 LASER PRODUCT

2.DANGER : Invisible laser radiation when open and inter

lock failed or defeated. Avoid direct exposure to beam.

3.CAUTION : There are no serviceable parts inside the

Laser Unit. Do not disassemble the Laser Unit. Replace
the complete Laser Unit if it malfunctions.

4.CAUTION : The compact disc player uses invisible

laserradiation and is equipped with safety switches
whichprevent emission of radiation when the drawer is
open and the safety interlocks have failed or are de
feated. It is dangerous to defeat the safety switches.

5.CAUTION : If safety switches malfunction, the laser is able

to function.

6.CAUTION : Use of controls, adjustments or performance of

procedures other than those specified herein may result in
hazardous radiation exposure.

!

Please use enough caution not to
see the beam directly or touch it
in case of an adjustment or operation
check.

REPRODUCTION AND POSITION OF LABELS

WARNING LABEL

CLASS 2
LASER PRODUCT

1-6

MX-DVA9/MX-DVA9R

Disassembly method

<Main body>

Removing the metal cover

(See Fig.1 to 3)

1.

Remove the six screws A on the back of the body.

2.

Remove the two screws B on both sides of the
body.

3.

Remove the metal cover from the body by lifting the
rear part of the cover.

CAUTION:

Do not break the front panel tab fitted to
the metal cover.

A

A

Metal cover

Metal cover

A

Fig.1

B

Fig.2

Metal cover

Fig.3

B

1-7

MX-DVA9/MX-DVA9R

Removing the DVD mechanism assembly
(See Fig.4 to 7)

Prior to performing the following procedure, remove
the metal cover.

1.

Disconnect the card wire from connector CN542 on
the main board on the right side of the body.

2.

Disconnect the wire from CN501 on the DVD servo
board in the lower part of the DVD mechanism
assembly, on the left side of the body.

3.

Remove the screw F from the rear panel on the
back of the body. Disconnect the earth terminal
extending from the DVD changer mechanism
assembly and attached to the terminal on the
antenna board.

Remove the two screws C on top of the body and
the two screws D on back of the body.

Remove the DVD changer mechanism from behind
upward while pulling the front panel assembly and
the rear panel outward.

C

Main board

CN542

Rear panel

Front panel assembly

C

DVD changer
mechanism assembly

Fig.4

DVD changer mechanism assembly

CN501

Rear panel

Front panel assembly

REFERENCE:

6.

Disconnect the card wire from connector CN540 and
CN541 on the inner side of the main board on the
right side of the body, and remove the DVD
mechanism assembly.

REFERENCE:

REFERENCE:

At this point, the two card wires in the
lower part of the DVD mechanism
assembly is still connected.

To prevent damage to the DVD changer
mechanism assembly, make sure to pull
both the front panel assembly and the rear
panel outward enough to remove the DVD
changer mechanism assembly.

To prevent damage to the DVD fitting, be
sure to pull both the rear panel and the
front panel assembly enough to remove
the DVD changer mechanism assembly.

Fig.5

Tuner board

DVD changer mechanism assembly

Main board

CN542

CN541

CN540

Front panel assembly

Fig.6

Rear panel

F

Earth terminal

Rear panel

Tuner board

D

1-8

DVD changer mechanism assembly

Fig.7

MX-DVA9/MX-DVA9R

Removing the front panel assembly

(See Fig.8 to 12)

Prior to performing the following procedure, remove
the metal cover and DVD changer mechanism
assembly.

1.

Disconnect the card wires from connector CN500,
CN505 and CN510 on the main board respectively.

2.

Remove the wire clamp and disconnect the wire from
connector CN703 on the amplifier board.

3.

Disconnect the wire from connector CN220 on the
transformer board.

4.

Remove the plastic rivet attaching the main board to
the front assembly on the right side of the body.

5.

Remove the two screws E on the bottom of the
body.

6.

Release the two joints a on the lower right and left
sides of the body using a screwdriver, and remove
the front panel assembly toward the front.

Power amplifier board (2)

CN703

Wire clamp

Fig.8

Plastic rivet

Main board

CN500

CN505

CN510

Front panel
assembly

Transformer board

CN220

Front panel assembly

Front panel assembly

Fig.9

Main board

E

(Bottom)

Fig.10

Joint a

Front panel assembly

Fig.12

Front panel assembly

Fig.11

Joint a

1-9

MX-DVA9/MX-DVA9R

Removing the tuner board

(See Fig.13 and 14)

Prior to performing the following procedure, remove
the metal cover.

1.

Disconnect the card wire from connector CN1 on the
tuner board on the right side of the body.

2.

Remove the plastic rivet fixing the tuner board.

3.

Remove the two screws F on the back of the body.

CAUTION:

When reassembling, connect the earth
terminal which is extending from the
DVD changer mechanism assembly and
attached to the tuner board, to the inner
side of the rear panel.

Removing the rear cover / rear panel

(See Fig.15 to 17)

Plastic rivet

Joints b

CN1

Tuner board

Fig.13

G

Rear panel

F

Rear panel

Joints b

Prior to performing the following procedure, remove
the metal cover and the DVD changer mechanism
assembly, the tuner board.

1.

Remove the screw G attaching the rear cover on the
back of the body.

2.

Push each tab of the four joints b in the direction of
the arrow and release.

3.

Remove the fourteen (A/B/EN) or sixteen(US/UJ/UG/
UN/UW) screws F attaching the rear panel.

4.

Disengage the joints c on each lower side of the rear
panel using a screwdriver and remove the rear panel
backward.

Rear cover

F

F

F

F

Fig.14

Fig.15-1

Rear panel

F

F

Rear panel

F

Joint c

Rear panel

Fig.17

1-10

Rear panel

Fig.16

Joint c

F

F

F

FF

Fig.15-2

MX-DVA9/MX-DVA9R

Removing the main board

(See Fig.18 and 19)

Prior to performing the following procedure, remove
the metal cover, the DVD changer mechanism
assembly, the rear panel and the antenna board.

1.

Disconnect the card wire from connector CN500,
CN505, CN510 and the wire from CN513 on the
main board respectively.

2.

Remove the plastic rivet and the screw H attaching
the main board on the right side of the body.

3.

Disconnect connector CN521 on the main board
from the analog output board outward. Disconnect
connector CN530 and CN531 in the lower part of the
main board from the regulator board upward.

Main board

CN513

Analog output board

Plastic rivet

CN510

CN505

CN500

Fig.18

Main board

CN521

Front panel assembly

Analog output board

CN520

Removing the speaker board

(See Fig.20)

Prior to performing the following procedure, remove
the metal cover, the DVD changer mechanism
assembly and the rear panel.

REFERENCE:

1.

Disconnect connector CN287 on the speaker board
from the regulator board.

It is not necessary to remove the main
board.

H

CN287

CN530

Fig.19

Speaker board

Fig.20

CN531

Regulator board

1-11

MX-DVA9/MX-DVA9R

Removing the power board / power cord

(See Fig.21)

Prior to performing the following procedure, remove
the metal cover, the DVD changer mechanism
assembly and the rear panel.

1.

Disconnect the wire from connector CN218 and
CN219(only US/UJ/UG/UN/UW) on the power board.

Move the power cord stopper upward and remove.

2.
Disconnect connector CN213 on the power board

3.

from the regulator board.

Remove the two wire clamps fixing the power cord

4.

and disconnect the power cord from connector
CN250 on the power board.

Removing the analog output board / fan

(See Fig.22 to 24)

CN218

CN219

Power board

CN250

Power cord

Power cord stopper

Analog output board

Wire clamp

CN213

Fig.21

CN370

Wire clamp

CN371

Wire clamps

Main board

CN513

Prior to performing the following procedure, remove
the metal cover, the DVD changer mechanism
assembly, the rear panel and the antenna board.

1.

Disconnect the wire from connector CN513 on the
main board.

2.

Remove the two wire clamps fixing the wire on the
analog output board.

3.

Disconnect the wire extending from the fan from
connector CN705 on the power amplifier board (2).

4.

Disconnect connector CN370 (only US/UJ/UG/UN/
UW) CN371 on the analog output board from the
main board. Disconnect connector CN372 and
CN373 on the analog output board from the power
amplifier board (1) and the power amplifier board (2)
respectively upward.

5.

Remove the two screws I and the fan from the fan
bracket.

Main board

CN370

Fan

CN371

Power amplifier board (2)

CN705

Fig.22

Analog output board

CN372

CN373

Fig.23

Analog output board

1-12

Fan bracket

I

Fan

Fig.24

MX-DVA9/MX-DVA9R

Removing the power amplifier board (1)
/ power amplifier board (2) / heat sink

(See Fig.25 to 27)

Prior to performing the following procedure, remove
the metal cover, the DVD changer mechanism
assembly, the rear panel, the antenna board and the
analog output board.

1.

Disconnect the wire from connector CN513 on the
main board.

2.

Remove the wire clamp on the power amplifier board
(1).

3.

Disconnect the wire from connector CN703 on the
power amplifier board (2).

4.

Disconnect connector CN310 on the power amplifier
board (1) and CN701 on the power amplifier board
(2) from the regulator board upward. The heat sink is
detached with the power amplifier board (1) and the
power amplifier board (2).

Main board

CN513

Power amplifier

board (2)

Heat sink

CN701

Power amplifier board (1)

CN703

CN310

Fig.25

Power amplifier board (2)

Wire clamp

Power amplifier

Regulator board

board (1)

Heat sink

5.

Remove the four screws J attaching the power
amplifier board (1) to the heat sink.

6.

Remove the four screws K attaching the power
amplifier board (2) to the heat sink.

Power amplifier board (1)

Heat sink

K

J

J

Fig.26

Power amplifier board (2)

K

Fig.27

1-13

MX-DVA9/MX-DVA9R

Removing the power transformer assembly
(See Fig.28 and 29)

Prior to performing the following procedure, remove
the metal cover, the DVD changer mechanism
assembly and the rear panel.

1.

Disconnect the wire from connector CN218 and
CN219(only US/UJ/UG/UN/UW) on the power board.

2.

Remove the two wire clamps on the power amplifier
board (1) and power board.

3.

Disconnect the wire from connector CN204 on the
regulator board.

4.

Disconnect the wire from connector CN220 on the
transformer board.

5.

Remove the four screws L attaching the power
transformer assembly.

Removing the regulator board

(See Fig.30)

CN219

Power board

CN218

Power transformer assembly

Wire clamps

Wire clamp

L

Transformer board

CN220

Fig.28

L

Regulator board

L

Regulator board

CN204

CN204

Prior to performing the following procedure, remove
the metal cover, the DVD changer mechanism
assembly, the rear panel, the antenna board, the
main board, the analog output board, the power
board, the power amplifier board (1), the power
amplifier board (2) and the speaker board.

1.

Disconnect the wire from connector CN204 on the
regulator board.

2.

Remove the two screws M.

L

Power transformer assembly

M

Power transformer assembly

L

Fig.29

Fig.30

CN220

Regulator board

M

CN204

1-14

MX-DVA9/MX-DVA9R

<Front panel assembly>

Prior to performing the following procedure, remove
the metal cover, the DVD changer mechanism
assembly and the front panel assembly.

Removing the cassette mechanism
assembly (See Fig.31)

1.

Disconnect the card wire from connector CN306 on
the head amplifier & mechanism control board.

2.

Remove the seven screws N attaching the cassette
mechanism assembly.

Removing the display system control
board (See Fig.32 to 34)

1.

Remove the four screws O attaching the stay
bracket.

Head amplifier
& mechanism control board
CN306

N

N

Cassette mechanism
assembly

O

N

N

N

Fig.31

O

2.

Disconnect the card wires from connector CN316
and CN881 on the display system control board.

3.

Remove the six screws P attaching the display
system control board.

4.

If necessary, disconnect the wire from connector
CN870 on the front side of the display system control
board and unsolder FW915.

Display system control board

CN316

P

FW915

(Solding)

P

CN881

CN911

Fig.32

CN870

P

Display system control board

Fig.33

CD eject board

Stay bracket

P

P

FW915

FW915

Display system control board

Fig.34

1-15

MX-DVA9/MX-DVA9R

Removing the CD eject board

(See Fig.35)

1.

Remove the three screws Q attaching the DVD eject
board.

2.

If necessary, unsolder FW915 on the DVD eject
board.

Removing the preset / tuning switch
board (See Fig.36 and 37)

Prior to performing the following procedure, remove
the display system control board.

1.

Pull out the preset knob on the front panel.

2.

Remove the five screws R attaching the preset /
tuning switch board.

3.

If necessary, unsolder FW901 on the preset / tuning
switch board.

Removing the operation switch board

(See Fig.37 and 38)

Prior to performing the following procedure, remove
the display system control board and the preset /
tuning switch board.

DVD eject board

FW915

(Solding)

Q

Preset / tuning switch board

FW915

(Solding)

Preset knob

Q

Fig.35

R

R

Fig.36

Operation switch board

Surround mode knob

Surround woofer
level knob

1.

Pull out the volume knob on the front panel and
remove the nut. Pull out the surround mode knob
and the surround woofer level knob toward the front.
Pull out the mic level knob toward the front.
(only US/UJ/UG/UN/UW)

2.

Remove the eleven (A/B/EN) or thirteen (US/UJ/UG/
UN/UW) screws S attaching the operation switch
board.

3.

Release each tab of the seven joints g retaining the

Joints g

S

Joint g

S

Operation
switch board

S

Joint g

Joints g

S

S

S

Fig.38-2

S

Joint g

Joint g

Joint g

Joints g

Volume knob

S

S

Joints g

S

Fig.37

S

Fig.38-1

Nut

S

Mic level knob

S

Joint g

S

Operation
switch board

1-16

<Speaker unit section>

Removing the side cover (See Fig.1)

1.

Remove the six screws A on the side of the body.

Removing the squawker speaker

(See Fig.2)

Prior to performing the following procedure, remove
the side cover.

1.

Remove the four screws B on the side of the body.

2.

Disconnect the red and black wires from the speaker
terminals on the squawker speaker.

MX-DVA9/MX-DVA9R

A

A

Side cover

A

A

Fig.1

B

Removing the front cover (See Fig.3 to 5)

Prior to performing the following procedure, remove
the side cover.

1.

Pull out the saran net toward the front while
disengaging the four joints a.

2.

Remove the two screws C and D respectively.

3.

Remove the front cover toward the front and
disconnect the yellow and black wires from the two
tweeter speaker terminals.

CC

Front cover

Squawker speaker

B

Fig.2

DD

Fig.4

Joints a

Joints a

Saran net

Fig.3

1-17

MX-DVA9/MX-DVA9R

Removing the woofer speaker (See Fig.6)

Prior to performing the following procedure, remove
the side cover and the front cover.

Tweeter speaker

Fig.5

1.

Remove the four screws E on the front of the body.

2.

Pull out the woofer speaker toward the front and
disconnect the wire (yellow and black,blue and
black) from the two speaker terminals.

Removing the tweeter speaker

(See Fig.7)

Prior to performing the following procedure, remove
the side cover and the front cover.

1.

Remove the two screws F attaching the tweeter
speaker on the back of the front cover.

E

E

Woofer speaker

Fig.6

F

Tweeter speaker

1-18

Front cover

Fig.7

DVD Changer Mechanism Section

Removing the DVD Servo control
board

1.

Remove the Metal cover.

2.

Remove the DVD changer mechanism assembly.

3.

From bottom side the DVD changer mechanism
assembly, remove the one screw 1 retaining the DVD
Servo control board.
Ciconnect the card wire,From the connectors CN101

4.
and CN102, on the DVD Servo control board.

Disengage the two engagements "A" , remove the DVD

5.
Servo control board.

Removing the DVD tray assembly
(See Fig.2~4)

Remove the front panel assembly.

1.
Remove the DVD changer mechanism assembly.

2.
Remove the DVD Servo control board.

3.
Remove the screw 2 retaining the Disc stopper

4.
(See Fig.3).
Remove the three screws 3 retaining the T.bracket

5.
(See Fig.3).
From the clamper base section "C" , remove both of the

6.
edges fixing the rod(See Fig.2 and 3).
Remove the screw 4 retaining the clamper assembly

7.
(See Fig.3).
From the left side face of the chassis assembly, remove

8.
the one screw 5 retaining both of the return spring and
lock lever(See Fig. 4).
By removing the pawl at the section "D" fixing the return

9.
spring, dismount the return spring(See Fig.4).
Remove the three lock levers(See Fig.4).

10.

Disc stopper

T.Braket

MX-DVA9/MX-DVA9R

1

DVD servo control baord

CN102

CN101

AA

Fig.1

Clamper base

B

Rod

C

T.Braket

Fig.2

D

3

B

C

Clamper ass'y

Fig.3

2

3

Lod stopper
(C/J version only)

3

4

Return spring

5

Lock lever

Fig.4

1-19

MX-DVA9/MX-DVA9R

11.

Check whether the lifter unit stopper has been caught
into the hole at the section "E" of DVD tray assembly
as shown in Fig.5.
Make sure that the driver unit elevator is positioned as

12.
shown in Fig.6 from to the second or fifth hole on the
left side face of the DVD Traverse mechanism
assembly.

[Caution]

13.

14.

15.

Chassis assembly

In case the driver unit elevator is not at above
position, set the elevator to the position as
shown in Fig.7 by manually turning the pulley
gear as shown in Fig.8.

Manually turn the motor pulley in the clockwise
direction until the lifter unit stopper is lowered from the
section "E" of DVD tray assembly(See Fig.8).
Pull out all of the three stages of DVD tray assembly in
the arrow direction "F" until these stages stop
(See Fig.6).
At the position where the DVD tray assembly has
stoppend, pull out the DVD tray assembly while
pressing the two pawls "G and G' " on the back side of
DVD tray assembly(See Fig.9). In this case, it is easy
to pull out the assembly when it is pulled out first from
the stage DVD tray assembly.

Fig.5

Stopper

E

DVD tray
assembly

Refer to Fig.7

Pulley gear

Pawl

DVD tray assembly

G

F

Drive unit of elevator

Fig.7Fig.6

DVD tray assembly

Motor pulley

Fig.8

1-20

Pawl ,

G

Fig.9

G'

MX-DVA9/MX-DVA9R

Removing the DVD mechanism
assembly(See Fig.10)

1.2.While turning the cams R1 and R2 assembly in the
arrow direction "H" . align the shaft "I" of the DVD
mechanism assembly to the position shown in Fig.10.
Remove the four screw 6 retaining the DVD
mechanism assembly.

Removing the DVD mechanism
(See Fig.11 and 12 )

For dismounting only the DVD machanism without

1.
removing the DVD mechanism assembly, align the shaft
"J" of the DVD mechanism assembly to the position
shown Fig.11 while turning the cam R1 and R2
assembly in the arrow direction "K" .
By raising the DVD mechanism assembly in the arrow

2.
direction "L" , remove the assembly from the lifter unit
(See Fig.12).

Cam R1, R2 assembly

Cams R1, R2 assembly

Arrow

H

I

6

6

CD mechanism assembly

10

6

6

Fig.10

CD mechanism

Arrow

K

J

Lifter unit

Fig.11

Fig.12

Arrow

L

1-21

MX-DVA9/MX-DVA9R

Removing the actuator motor boad
(See Fig.14, 15)

1.

Absord the four soldered positions "M" of the right and
left motors with a soldering absorber(See Fig.14).

2.

Remove the two screws 7 retaining the actuator motor
board(See Fig.14).
Remove the two screws 8 retaining the tray select

3.
switch board(See Fig.15).

Removing the can unit
(See Fig.15~18 )

1.

Remove the CD mechanism assembly.

2.

While turning the cam gear L, align the pawl "N"
position of the drive unit to the notch position(Fig.15) on
the cam gear L.
Pull out the drive unit and cylinder gear(See Fig.17).

3.
While turning the cam gear L, align the pawl "O"

4.
position of the select lever to the notch position(Fig.18)
on the cam gear L.
Remove the four screws 9 retaining the cam unit(cam

5.
gear L and cams R1/R2 assembly)(See Fig.18).

M

Motor L

Actuator motor board

Fig.14

7

Motor R

M

7

Chassis assembly

CN801

Fig.15

CN802

Drive unit

Tray select
switch board

Cylinder gear

CN804

Drive unit

N

8

Cam gear L

9

Cam gear L

Fig.16

Cams R1, R2 assembly

9

Cam unit

9

1-22

Fig.17

O

Select lever

Fig.18

MX-DVA9/MX-DVA9R

Removing the actuator motor and belt
(See Fig.19~22)

1.

Remove the two screws 10 retaining the gear bracket
(See Fig.19).

2.

While pressing the pawl "P" fixing the gear bracket in
the arrow direction, remove the gear bracket
(See Fig.19).
From the notch "Q section" on the chassis assembly

3.
fixing the edge of gear bracket, remove and take out the
gear bracket(See Fig. 20).
Remove the belts respectively from the right and left

4.
actuator motor pulleys and pulley gears(See Fig. 19).
After turning over the chassis assembly, remove the

5.
actuator motor while spreading the four pawls "R" fixing
the right and left actuator motors in the arrow
direction(See Fig. 21).

[Note]

When the chassis assembly is turned over under
the conditions wherein the gear bracket and belt
have been removed, then the pulley gear as well
as the gear, etc. constituting the gear unit can
possibly be separated to pieces. In such a case,
assemble these parts by referring to the assembly
and configuration diagram in Fig. 22.

Pully gear

Gear bracket

Belt

Motor pulley

10

Fig.19

Actuator motor

Pulley gear
Belt

Motor pulley

10

Pawl

P

Chassis assembly

Q

Gear bracket

Fig.20

Assembly and Configuration Diagram

Pulley gear

R

R

Fig.21

Pulley gear

Gear B

Cylinder gear

Gear B

Gear C

Select gear

Gross gear L

Fig.22

Gross gear U

Gear C

1-23

MX-DVA9/MX-DVA9R

Removing the cams R1/R2 assembly
and cam gear L(See Fig.23)

Remove the slit washer fixing the cams R1 and R2

1.
assembly.
By removing the two pawls "S" fixing the cam R1,

2.
separate R2 from R1.
Remove the slit washer fixing the cam gear L.

3.
Pull out the cam gear L from the C.G. base assembly.

4.

Removing the C.G. base assembly
(See Fig.23 and 24)

Remove the three screws 11 retaining the C.G. base
assembly.

[Caution]

To retassemble the cylinder gear, etc.with the
cam unit (cam gear and cans R1/R2 assembly),
gear unit and drive unit, align the position of the
pawl "N" on the drive unit to that o f the notch
on the cam gear L. Then, make sure that the
gear unit is engaged by turning the cam gear L
(See Fig. 24).

Slit washer

Cam gear L

11

Slit washer

Cam R2

Pawl

S

Cam R1

Cam switch board

C.G. base assembly

Pawl

S

Notch

Pawl

N

Cylinder
gear

Drive unit

Fig.23

Cam gear L

Cam R1, R2 assembly

Gear unit

Gear bracket

Fig.24

1-24

MX-DVA9/MX-DVA9R

< Cassette Mechanism Section >

Removing the Playback,Recording and Eraser
Heads (See Fig.1~3)

1. While shifting the trigger arms seen on the right
side of the head mount in the arrow direction,turn
the flywheel R in counterclockwise direction until
the head mount has gone out with a click
(See Fig. 1).

2. When the flywheel R is rotated in counterclockwise
direction, the playback head will be turned in
counterclockwise direction from the position in
Fig.2 to that in Fig.3.

3. At this position, disconnect the flexible P.C.board
(outgoing from the playback head) from the
connector CN301 on the head amp. and mechanism
control P.C. board.

4. After dismounting the FPC holder,remove the
flexible P.C.board.

5. Remove the flexible P.C.board from the chassis
base.

6. Remove the spring "a" from behind the playback
head.

7. Loosen the reversing azimuth screw retaining the
playback head.

8. Take out the playback head from the front of the
head mount.

9. The recording and eraser heads should also be
removed similarly according to Steps 1~8 above.

Reassembling the Playback, Recording

and Eraser Heads (See Fig.2,3)

Cassette mechanism

Fig.1

Playback/Recording &
eraser head

Flexible
P.C.board

CN301

Head amplifier & mechanism
control P.C. board

Fig.2

Flywheel R

Trigger armHead mount

(Mechanism A side)

Spring "a"

Trigger arm

Flywheel R

(Mechanism A side)

1. Reassemble the playback head from the front of
the head mount to the position as shown in Fig.3.

2. Fix the reversing azimuth screw.

3. Set the spring a from behind the playback head.

4. Attach the flexible P.C.board to the chassis base,
and fix it with the FPC holder as shown in Fig.3.

5. The recording and eraser heads should also be
reassembled similarly according to Steps 1~4
above.

Playback head

Spring "a"

FPC holder

Fig.3

Reversing azimuth
screw

Head
mount

Flexible
P.C.board

CN302

Head amplifier &
mechanism control
P.C. board

(Mechanism B side)

1-25

MX-DVA9/MX-DVA9R

Removing the head Amp.and Mechanism
Control P.C.Board (See Fig. 4)

1.Remove the cassette mechanism assembly.

2.After turning over the cassette mechanism
assembly,remove the five screws "A" retaining
the head amp. and mechanism control P.C.
board

3.Disconnect the connectors CN303 and CN304
on the P.C.Board and the connectors CN1 on
both the right and left side reel pulse
P.C.Boards.

4.When necessary, remove the 4pin parallel
wire soldered to the main motor

Removing the Capstan Motor Assembly

1.Remove the six screws "B" retaining capstan
motor assembly (See Fig. 5).

2.While raising the capstan motor, remove the
capstan belts A and B respectively from the
motor pulley (See Fig. 6).

A

Flexible
board

Head amplifier &
mechanism control board

AA

CN304

CN302 CN301

Flexible
board

CN303

Fig.4

BB

Capstan motor
assembly

AA

Caution 1: Be sure to handle the capstan
belts so carefully that these belts
will not be stained by grease and
other foreign matter. Moreover,
these belts should be hand while
referring to the capstan belt
hanging method.

Capstan
belt A

BBBB

Fig.5

Capstan motor

Capstan
belt B

Capstan
belt A

Fig.7 Fig.6

1-26

Capstan
belt B

Motor pulley

MX-DVA9/MX-DVA9R

Removing the Capstan Motor (See Fig. 8)

From the joint bracket, remove the two screws "C"
retaining the capstan motor.

Removing the Flywheel (See Fig. 9,10)

1.Remove the head amp. and mechanism control
P.C.Board.

2.Remove the capstan motor assembly.

3.After turning over the cassette mechanism, remove
the slit washers "a" and "b" fixing the capstan shafts
R and L, and pull out the flywheels R and L respectively
from behind the cassette mechanism.

C

Capstan motor

Joint
bracket

C

Fig.8

Flywheel R Flywheel L

Flywheel R Flywheel L

Fig.10

Removing the Reel Pulse P.C.Board and Solenoid
(See Fig. 11)

1.Remove the five pawls (c,d,e,f,g) retaining
the reel pulse P.C.Board.

2.From the surface of the reel pulse P.C.Board parts,
remove the two pawls "h" and "i" retaining the solenoid.

hi

Solenoid

c

a

d

Slit
washer "a"

Fig.9

e

f

b

Slit
washer "b"

g

Reel pulse board

Solenoid

Fig.11

1-27

MX-DVA9/MX-DVA9R

Adjustment method

Measurement instruments required
for adjustment

1. Low frequency oscillator,
This oscillator should have a capacity to output 0dBs
to 600ohm at an oscillation frequency of 50Hz-20kHz.

2. Attenuator impedance : 600ohm

3. Electronic voltmeter

4. Frequency counter

5. Wow flutter meter

6. Test tape
VT712 : For Tape speed and wow flutter ( 3kHz)
VT724 : For Reference level (1kHz)
VT703L : For Head angle(10kHz)

Because of frequency-mixed tape with 63,1k,10k and
14kHz(250nWb/m -24dB).
Use this tape together with a filter.

7. Blank tape
TAPE : AC-225

8. Torque gauge : For play and back tension
Forward ; TW2111A, Reverse ; TW2121A
Fast Forward and Rewind ; TW2231A

9. Test disc
: CTS-1000(12cm),GRG-1211(8cm)

10. Jitter meter

Radio input signal

AM modulation frequency : 400Hz
Modulation factor : 30%
FM modulation frequency : 400Hz
Frequency displacement : 22.5kHz

Frequency Range
A/B/EN

AM 522kHz~1629kHz
FM 87.5MHz~108MHz

US/UJ/UG/UN/UW
AM 531kHz~1602kHz
FM 87.5MHz~108MHz

Standard measurement positions of volume
and switch

Power : Standby (Light STANDBY Indicator)
Sub woofer VOL. : Minimum
Sound mode : OFF
Main VOL. : 0 Minimum
Traverse mecha set position : Disc 1
Mic MIX VOL : MAX
ECHO : OFF

Measurement conditions

Power supply voltage
AC120V(60Hz)

Measurement
output terminal : Speaker out
:TP101(Mesuring for TUNER/DECK/CD)
:Dummy load 6ohm

Precautions for measurement

1. Apply 30pF and 33kohm to the IF sweeper output
side and 0.082 F and 100kohm in series to
the sweeper input side.

2. The IF sweeper output level should be made as
low as possible within the adjustable range.

3. Since the IF sweeper is a fixed device, there is
no need to adjust this sweeper.

4. Since a ceramic oscillator is used, there is no need
to perform any MPX adjustment.

5. Since a fixed coil is used, there is no need to adjust
the FM tracking.

6. The input and output earth systems are separated.
In case of simultaneously measuring the voltage
in both of the input and output systems with an
electronic voltmeter for two channels, therefore,
the earth should be connected particularly.

7. In the case of BTL connection amplifier, the minus
terminal of speaker is not for earthing. Therefore,
be sure not to connect any other earth terminal
to this terminal. This system is of an OTL system.

1-28

DVD section

TEST MODE FOR DVD a INITIALISE THE DVD UNIT BOARD

a) Insert A/C Power Cord
b) At standby mode press Stop Button and CANCEL/DEMO button.

Wait 4 seconds & for the display of " TEST VERSION REGION " i.e. TEST JC 1

c) Press the 'ENTER' button on remocon. The FL panel will display 'EEPROM'.

Plug out and plug in again the power cord. Repeat the process 1(a) and 1(b) again.

Confirm that the Area Code and Region Code is correctly display as below.

MX-DVA9/MX-DVA9R

Are Code FL indicate of Area Code in Test mode

Region Code.

J/C

UJ

UG/UX

US/UN/UP

UT

UW

E/EN/B

A

EE

JC

JC

2U

3U

UT

4U

E

A

EE

1

1

2

3

3

4

2

4

5

Note: Please plug out and plug in the power cord from A/C supply before continue the next test.

Adjustment
Jig setup

1. Remove the rubber cushion from each of the four
corners of the traverse mechanism.
(When installing be sure not to make a mistake with
the cushion colors).

2. Install the jig stud.

3. Make a jig clamp. (Remove the clamp from the set
and assemble it as shown in the diagram below.

Green rubber
cushion

Blue rubber
cushion

Note:

How to handle the pickup
To protect the pickup from electro-static damage,
make sure to hold it by the die-cast chassis (optical
base). And make sure that pickup lens do not touch
the top cover.

How to prepare a clamp

Remove the claws
from the 3 locations

Jig stud

Disassemble the clamp
and holder

Installing the
4 jig studs

Blue rubber
cushion

Combine the clamp
and holder to become
a jig clamp.

1-29

MX-DVA9/MX-DVA9R

Integrated wiring for adjustment

1. Place a board on top of the unit and put the
changer on it. Then carry out the wiring of the

main unit.

2. Connect a extension cable to the traverse
mechanism for adjustment and then connect
them to the changer.

3. Remove the solder of the short-circuited
flexible wire. Then remove the short-circuited
pin from the traverse mechanism

4. Connection is completed.

Adjustment preparation

1. The 3 adjustment locations

2. 1.4 mm hexagonal wrench

3. Set the VT-501 or the VT502 test disc.

FL jitter display

1. Connect the power cable while pressing the
(OPEN/CLOSE) button of DISC1 and
(PLAY) button simultaneously.

--- The DISC no. " " is displayed on
the FL indicator.

2. Press the 3D-PHONIC key button of remote
controller to commence initialization.

3. When the key (PLAY) is pressed the jitter
value is displayed.

4. Adjust the jitter value to minimum by using the
adjust screw.

a). Turn the adjustment screw ( A and B )

clockwise half.

b). Return the adjustment screw ( A and B ) to

former position.

c). Turn the adjustment screw ( A and B )

counterclockwise half.

d). Set the adjustment screw ( A and B ) to the

position of best jitter at three positions.

Next, do it similar to the above-mentioned in

adjustment screw A and C.

Extension cord
QUQ605-4040AJ

Adjustment location
(Adjust screw C )

Adjustment location
(Adjust screw A )

Jig ass'y clamp adjustment

Stud
JIGXVM555

Hexagonal wrench

(Adjust screw B )

Test disc

1-30

3 locations
for adjustment

Adjust by using
a hexagonal
wrench

Arrangement of adjusting positions

MX-DVA9/MX-DVA9R

Cassette mechanism section (Mechanism A section)

Head azimuth

adjusting screw

(Forward side)

Playback

head

Head azimuth

adjusting screw

(Reverse side)

Cassette mechanism section (Back side)

Head azimuth

adjusting screw

(Forward side)

Playback, recording and eraser

heads or playback head

Head azimuth

adjusting screw

(Reverse side)

Cassette Mechanism Unit Section

Tape speed ADJ

Bias ADJ L

Bias ADJ R

1-31

MX-DVA9/MX-DVA9R

Tape recorder section

Items Measurement

Confirmation
of head angle

Confirmation
of tape speed

conditions

Test tape
:VT703L(10kHz)
Measurement
output terminal
:Speaker terminal
Speaker R
(Load resistor:6 )
:Headphone terminal

Test tape
:VT712(3kHz)

Measurement
output terminal
:Headphone terminal

1.Playback the test tape VT703L(10kHz).

2.With the playback mechanism or recording &
playback mechanism, adjust the head azimuth
screw so that the forward and reverse output
levels become maximum.After adjustment,lock
the head azimuth at least by half a turn.

3.In either case,this adjustment should be
performed in both the forward and reverse
directions with the head azimuth screw.

<Constant speed>
Adjust VR301 so that the frequency counter reading
becomes 3,000Hz 60Hz when playing back the
test tape VT712(3kHz)with the playback mechanism
or playback and recording mechanism after ending
forward winding of the tape.

Reference values for confirmation items

Items Measurement

Double tape
speed

conditions

Test tape
:VT703L(10kHz)
Measurement
output terminal
:Speaker terminal
Speaker R
(Load resistance:6 )
measurement
output terminal
:Headphone terminal

After setting to the double speed motor, confirm
that the frequency counter reading becomes
4,800+400/-300Hz when the test tape VT712
(3kHz) has been play back with the playback
mechanism.

Measurement method

Measurement method

Standard

values

Maximum
output

Tape speed
of decks
(A and B)
:3,000Hz
60Hz

Standard

values

4,800+400/

-300Hz

Adjusting

positions

Adjust the head
azimuth screw
only when the
head has been
changed.

VR301

Adjusting

positions

Playback
mechanism side

Difference
between the
forward and
reverse speed.
P.mecha and
R/P mecha
speed

Wow & flutter

Test tape
:VT712(3kHz)
Measurement
output terminal
:Headphone terminal

When the test tape VT712(3kHz) has been played
back with the playback mechanism or recording and
playback mechanism at the beginning of forward
winding, the frequency counter reading of the
difference between both of the mechanisms should
be 6.0Hz or less.

When the test tape VT712(3kHz) has been played
back with the playback mechanism or recording and
playback mechanism at the beginning of forward
winding the frequency counter reading of wow &
flutter should be 0.25% or less(WRMS).

1-32

60Hz or
less

with in

0.25%
JIS(WTD)

Both the playback
and recording &
playback
mechanism

Both the playback
and recording &
playback
mechanism

Electrical performance

Items Measurement

Adjustment of
recording bias
current
(Reference
value)

conditions
*Mode : Forward or
reverse mode
*Recording mode
*Test tape
: AC-225
Measurement output
terminal
:Both recording and
headphone terminals

Measurement method

1.With the recording and playback mechanism,
load the test tapes(AC-225 to TYP ),and set the
mechanism to the recording and
pausing conditions in advance.

2.After connecting 100 in series to the recorder
head,measure the bias current with a valve
voltmeter at both of the terminals.

3.After resetting the [PAUSE] mode,start recording.
At this time,adjust VR101 for LcH and VR201 for
RcH so that the recording bias current values
become 4.0 A (TYP ).

Standard

values
AC-225
:4.20 A

MX-DVA9/MX-DVA9R

Adjusting
positions

LcH
:VR101
RcH
:VR201

Adjustment of
recording and
playback
frequency
characteristics

Reference frequency
:1kHz and 10kHz
(REF:-20dB)
Test tape
:TYP AC-225
Measurement input
terminal
:OSC IN

1.With the recording and playback mechanism,load
the test tape(AC-225 to TYP ),and set the
mechanism to the recording and pausing condition
in advance.

2.While repetitively inputting the reference frequency
signal of 1kHz and 10kHz from OSC IN, record and
playback the test tape.

3.While recording and playing back the test tape in
TYP ,adjust VR101 for LcH and VR201 for RcH
so that the output deviation between 1kHz and
10kHz becomes -1dB 2dB.

Reference values for electrical function confirmation items

Items Measurement

Recording
bias frequency

conditions

*Recording and
playback side forward
or reverse
*Test tape
:TYP AC-225
*Measurement
terminal BIAS TP on
P.C.board

1.While changing over to and from BIAS 1 and 2,
confirm that the frequency is changed.

2.With the recording and playback mechanism.
load the test tape (AC-225 to TYP ),and set the
mechanism to the recording and pausing
conditions in advance.

3.Confirm that the BIAS TP frequency on the
P.C.board is 100kHz 6kHz.

Measurement method

Output
deviation
between
1kHz and
10kH
:-1dB 2dB

Standard

values
100kHz
+9kHz

-7kHz

LcH
:VR101
RcH
:VR201

Adjusting

positions

Eraser current
(Reference
value)

*Recording and
playback side forward
or reverse
*Recording mode
*Test tape
:AC-225
Measurement terminal
Both of the eraser
head

1.With the recording and playback mechanism,
load the test tapes(AC-225 to TYP ),and set the
mechanism to the recording and pausing condition
in advance.

2.After setting to the recording conditions,connect
1M in series to the eraser head on the recording
and playback mechanism side,and measure the
eraser current from both of the eraser terminal.

TYP
:75mA

1-33

MX-DVA9/MX-DVA9R

Flow of functional operation until TOC read

Power ON

Play Key

Slider turns REST
SW ON.

Automatic tuning
of TE offset

Check Point

Confirm that the voltage at the pin5
of CN801 is "H"\"L"\"H".

Tracking error waveform at TOC reading

Approx.3sec

Tracking
servo
off states

Automatic measurement
of TE amplitude and
automatic tuning of
TE balance

VREF

pin 25 of
IC601(TE)

Approx

1.8V

Disc states
to rotate

Tracking
servo
on states

Disc to be
braked to stop

TOC reading
finishes

500mv/div
2ms/div

Fig.1

Laser ON

Detection of disc

Automatic tuning of
Focus offset

Automatic measurement of
Focus S-curve amplitude

Disc is rotated

Focus servo ON
(Tracking servo ON)

Automatic measurement of
Tracking error amplitude

Automatic tuning of
Tracking error balance

Check that the voltage at the
pin40 of IC651 is + 5V?

Confirm that the Focus error
S-cuve signal at the pin28 of
IC651 is approx.2Vp-p

Confirm that the signal from
pin24 IC651 is 0V as a
accelerated pulse during
approx.400ms.

Confirm the waveform of
the Tracking error signal.
at the pin 25 of IC601 (R604)
(See fig-1)

1-34

Automatic tuning of
Focus error balance

Automatic tuning of
Focus error gain

Automatic tuning of
Tracking error gain

TOC reading

Play a disc

Confirm the eys-pattern
at the lead of TP1

MX-DVA9/MX-DVA9R

Maintenance of laser pickup

(1) Cleaning the pick up lens
Before you replace the pick up, please try to
clean the lens with a alcohol soaked cotton
swab.

(2) Life of the laser diode
When the life of the laser diode has expired,
the following symptoms will appear.

1. The level of RF output (EFM output : ampli
tude of eye pattern) will below.

Is the level of

RFOUT under

1.25V 0.22Vp-p?

YES

O.K

NO

Replace it.

Replacement of laser pickup

Turn off the power switch and, disconnect the
power cord from the ac outlet.

Replace the pickup with a normal one.(Refer
to "Pickup Removal" on the previous page)

Plug the power cord in, and turn the power on.
At this time, check that the laser emits for
about 3seconds and the objective lens moves
up and down.
Note: Do not observe the laser beam directly.

Play a disc.

Check the eye-pattern at TP1.

Finish.

(3) Semi-fixed resistor on the APC PC board
The semi-fixed resistor on the APC printed circuit board which is attached to the pickup is used to adjust the laser
power. Since this adjustment should be performed to match the characteristics of the whole optical block, do not
touch the semi-fixed resistor.
If the laser power is lower than the specified value, the laser diode is almost worn out, and the laser pickup should
be replaced.
If the semi-fixed resistor is adjusted while the pickup is functioning normally, the laser pickup may be damaged
due to excessive current.

1-35

MX-DVA9/MX-DVA9R

Description of major ICs

MN102L62GEJ (IC401) : Unit CPU

1.Terminal layout
~

100 76

1

~

75

~

25

26 50

51

~

2.Pin function

Pin No. Pin No.

Symbol Symbol

1

WAIT
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

RE

SPMUTE

WEN

CS0

CS1
CS2
CS3

DRVMUTE

SPKICK

LSIRST

WORD

A0
A1
A2
A3

VDD

SYSCLK

VSS

XI

XO

VDD

OSCI

OSCO
MODE

A4
A5
A6
A7
A8

A9
A10
A11

VDD

A12
A13
A14
A15
A16
A17
A18
A19

VSS

A20

TXSEL

HAGUP

CD/DVD

ADPD

HMFON

TRVSW

I/O I/O

Micon wait signal input

I

Read enable

O

Spindle muting output to IC251

O

Write enable

O

Non connect

­Chip select for ODC

O

Chip select for ZIVA

O

Chip select for outer ROM

O

Driver mute

O

Spin kick (Non connect)

O

LSI reset

O

Bus selection input

O

Address bus 0 for CPU

O

Address bus 1 for CPU

O

Address bus 2 for CPU

O

Address bus 3 for CPU

O

Power supply

­System clock signal output

O

Ground

­Not use (Connect to vss)

­Non connect

­Power supply

­Clock signal input(13.5MHz)

I

Clock signal output(13.5MHz)

O

CPU Mode selection input

I

Address bus 4 for CPU

O

Address bus 5 for CPU

O

Address bus 6 for CPU

O

Address bus 7 for CPU

O

Address bus 8 for CPU

O

Address bus 9 for CPU

O

Address bus 10 for CPU

O

Address bus 11 for CPU

O

Power supply

­Address bus 12 for CPU

O

Address bus 13 for CPU

O

Address bus 14 for CPU

O

Address bus 15 for CPU

O

Address bus 16 for CPU

O

Address bus 17 for CPU

O

Address bus 18 for CPU

O

Address bus 19 for CPU

O

Ground

­Address bus 20 for CPU

O

TX Select

O
O

Foucs balance & leaser power select

O

Power up out put

O
O

Detection switch of traverse

I

inside

Function

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

FGIN

TRS

ADSCEN

VDD
FEPEN
SLEEP

BUSY

REQ

CIRCEN

HSSEEK

VSS

EPCS
EPSK

DPDI

EPDO

VDD
SCLKO
S2UDT
U2SDT

CPSCK

SDIN

SDOUT

-

-

NMI

ADSCIRQ

ODCIRQ
DECIRQ

WAKEUP

ODCIRQ2

ADSEP

RST

VDD

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
TEST8

VSS

D0
D1
D2
D3
D4
D5
D6
D7

Function

Serial enable signal for ADSC

O

Power supply

­Serial enable signal for FEP

O

Standby signal for FEP

O

Communication busy

I

Communication Request

O

CIRC command select

O

Non connect

­Ground

­EEPROM chip select

O

EEPROM clock

O

EEPROM data input

I

EEPROM data output

O

Power supply

­Communication clock

I

Communication input data

I

Communication output data

O

Clock for ADSC serial

O

ADSC serial data input

I

ADSC serial data output

O

Not use

­Not use

­Not use

­Interrupt input of ADSC

I

Interrupt input of ODC

I

Interrupt input of ZIVA

I

Not use

O

Interruption of system control

I

Address data selection input

I

Reset input

I

Power supply

­Test signal 1 input

I

Test signal 2 input

I

Test signal 3 input

I

Test signal 4 input

I

Test signal 5 input

I

Test signal 6 input

I

Test signal 7 input

I

Test signal 8 input

I

Ground

­Data bus 0 of CPU

I/O

Data bus 1 of CPU

I/O

Data bus 2 of CPU

I/O

Data bus 3 of CPU

I/O

Data bus 4 of CPU

I/O

Data bus 5 of CPU

I/O

Data bus 6 of CPU

I/O

Data bus 7 of CPU

I/O

1-36

AN8702FH(IC101):Frontend processor

1.Pin layout

HDTYPE

VIN12

646362616059585756555453525150

VIN11

GND1

VIN4

VIN3

VIN2

VIN1

VREF1

VCC1

VIN10

VIN9

VIN8

VIN7

VIN6

VIN5
49

MX-DVA9/MX-DVA9R

2.Pin function

Pin No.

1
2
3
4
5
6
7
8
9

10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

Symbol

PC1

PC01

PC2

PC02

TGBAL

TBAL
FBAL

POFLT

DTRD

IDGT

STANDBY

SEN
SCK

STDI
RSEL
JLINE

TEN

TEOUT

ASN

ASOUT

FEN

FEOUT

VSS

TG

VDD

GND2

VREF2

VCC2

VHALF
DFLTON
DFLTOP

DSFLT

GND3

1

PC1

2

PC01

3

PC2

4

PC02

5

TGBAL

6

TBAL

7

FBAL

8

POFLT

9

DTRD

10

IDGT

SEN
SCK

STDI

RSEL

JLINE

11
12
13
14
15
16

171819202122232425262728293031

TEN

TEOUT

STANDBY

I/O Description

Input for Laser current monitor

I

Laser power control output for DVD

O

Photo detector fo CD

I

Laser power control output for CD

O

Tangential phase balance control terminal

I

Tracking balance control terminal

I

Focus balance control terminal

I

Track detection threshold level terminal

O

Data slice part data read signal input terminal

I

(For RAM)
Data slice part address part gate signal input

I

terminal( For RAM)
Standby mode control terminal

I

SEN(Serial data input terminal)

I

SCK(Serial data input terminal)

I

STDI(Serial data input terminal)

I

I

DVD and CD selection
J-line setting output (FEP)

I

Tracking error output amplifier reversing input terminal

I

Tracking error signal output terminal

O

Off set adjustment terminal for DRC

I

All added signal output terminal

O

Focus error output amplifier reversing input terminal

I

Focus error signal output terminal

O

Connect to GND

-

Tangential phase error signal output terminal

O

Power supply terminal 3V

-

Connect to GND

-

VREF2 voltage output terminal

O

Power supply terminal 5V

-

VHALF voltage output terminal

O

Filter amplifier reversing output terminal

O

Filter amplifier output terminal

O

Connected capacitor terminal for filter output

O

Connect to GND

-

AN8702FH

FEN

ASN

FEOUT

ASOUT

VSS

TG

VDD

Pin No.

34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57

58

59

60

61
62
63
64

48

RFINN
RFINP

47

TESTSG

46

AGCO

45

AGCG

44
43

PEAK

42

BOTTOM

41

RFENV

40

BDO

39

OFTR

38

DCRF

37

RFC

36

VCC3

35

RFOUT

34

RFDIFO

33

GND3

32

VCC2

GND2

VREF2

VHALF

DFLTON

DSFLT

DFLTOP

Symbol I/O Description

RF operation output terminal

RFDIFO

RFOUT

VCC3

RFC
DCRF
OFTR

BDO

RFENV

BOTTOM

PEAK
AGCG
AGCO

TESTSG

RFINP

RFINN

VIN5
VIN6
VIN7
VIN8
VIN9

VIN10

VCC1

VREF1

VIN1

VIN2

VIN3

VIN4

GND1
VIN11
VIN12

HDTYPE

O

RF output terminal

O

Power supply terminal 5V

-

I Filter for RF amplifier

All addition amplifier capacitor terminal

O

OFTR output terminal

O

BDO output terminal

O

RF envelope output terminal

O

Bottom envelope detection filter terminal

O

Peak envelope detection filter terminal

O

AGC amplifier gain control terminal

O

AGC amplifier level control terminal

O

TEST signal input terminal

I

RF signal positive input terminal

I

RF signal negative input terminal

I

RF input of external division into 4 terminal for CD

I

RF input of external division into 4 terminal for CD

I
I

RF input of external division into 4 terminal for CD
RF input of external division into 4 terminal for CD

I
I

RF input of external division into 2 terminal for DVD

I

RF input of external division into 2 terminal for DVD

Power supply terminal 5V

-

VREF1 voltage output terminal

O

External division into four (DVD/CD) RF input

I

terminal1
External division into four (DVD/CD) RF input

I

terminal2
External division into four (DVD/CD) RF input

I

terminal3
External division into four (DVD/CD) RF input

I

terminal4
Connect to GND

-

3 beem sub input terminal for CD

I
I

3 beem sub input terminal for CD

HD type switching

I

1-37

MX-DVA9/MX-DVA9R

MN101C35DEG(IC810):System controller

Pin function

Pin No.

1
2
3

4~7

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

49~51
52~64
65~88
89~99

100

Symbol

D DATA

DCLK

DACOCS

DI/DO/CS/SK

VDD
OSC2
OSC1

VSS

XI

XO

MMOD

VREF-

POWER SW

NTSEL

RGB/YC SW

S/COMPO

AIN0

AIN2
TEST0
TEST1
VREF+

RGBSEL

RESET

AVCO

AVCI

POWERON

TCLOSE

YOPEN

/LMMUTE

SWOPEN
SWUPDN

REMO

NC

REQ

NC
S2UDT
U2SDT

SCLK

BUSY

CPURST

NC

VS3
VS1

MUTE

STANDBYIND

NC

1G~13G

S1~S24

NC

VPP

I/O

O
O
O

-

-

O

I

-

-

-

-

­I
I

-

­I
I

-

-

-

O

I

O

I
O
O
O
O

I

I

I

-

I

-

O

I
O
O
O

­O
O
O
O

­O
O

-

-

DAC control data
DAC control clock
DAC control chip select
Non connect
Power supply +B 5V
Oscillation terminal 8MHz
Oscillation terminal 8MHz
Connect to ground
Unused, Connect with ground
Unused
Connect to ground
Connect to ground
Key input (power)
NTSC/PAL switch input
Un used
Un used
Key input (S831~S835)
Key input (open/close)
Un used
Un used
Power supply +B 5V
RGB select control (H:RGB L:other)
Reset input
AV COMPULINK output
AV COMPULINK input
Power ON output
Tray close control output
Tray open control output
Tray muting output (L:muting)
Detection switch of tray open/close (L:open/close)
Detection switch of traverse mechanism up/down (H:UP L:DOWN)
Remote control interruption
Non connect
Communication between unit microcomputers request
Non connect
Communication between unit microcomputers DATA output
Communication between unit microcomputers DATA input
Communication between unit microcomputers CLK
Communication between unit microcomputers BUSY
Unit microcomputers reset
Non connect
S3 control (H:standby L:power ON)
S1 control
Muting output
LED control signal output (standby)
Non connect
FL grid control signal output
FL segment control signal output
Non connect

-VDISP (apply -35V)

Description

1-38

MN103S13BDA (IC301) : Optical disc controller

1.Terminal layout

DMARQ

NIOWR

VSS

NIORD

IORDY

NDMACK

VDD

INTRQ

NIOCS16

DA1

VSS

NPDIAG

DA0

DA2

VDD

NCS1FX

NCS3FX

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

HDD15

HDD0

HDD14

VDD

HDD1

HDD13

HDD2

VSS

HDD12

VDD

HDD3

HDD11

HDD4

HDD10

VDD
HDD5
HDD9

VSS
HDD6
HDD8
HDD7
VDDH

NRESET
MASTER

NINT0
NINT1

WAITDOC

NMRST

DASPST

VDD

OSCO2

OSCI2

UATASEL

VSS

PVSSDRAM
PVDDDRAM

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

3738394041424344454647484950515253545556575859606162636465666768697071

128

MN103S13BDA

NDASP

127

NTRYCL

126

VDD

NEJECT

125

124

VSS

123

MONI0

MONI1

122

121

MONI2

MONI3

120

119

SDATA

118

SCLOCK

VDD

DAT0

117

116

115

DAT1

114

DAT2

113

DAT3

112

CHCK40

NCLDCK

SUBC

111

110

109

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

72

SBCK
VSS
P0
P1
PVDD
PVSS
VDD
OSCO1
OSCI1
VSS
LRCK
BLKCK
IPFLAG
DACCLK
DACLRCK
DA C DATA
NTRON
LG
JMPINH
IDHOLD
SBCK/PLLOK
CLKOUT2
VDD
NRST
MMOD
VSS
CPDET1
CPDET2
BDO
IDGT
DTRD
TEHLD
VDD
CLKOUT1
CPUDT0
CPUDT1

MX-DVA9/MX-DVA9R

2.Block diagram

DVD-ROM
Formatter

CGEN

MODE

CPUADR17

CPUADR16

VSS

CPUADR15

CPUADR14

CPUADR13

CD-PRE

Instruction
memory
(40KB)

DATA

MEMORY

(6KB)

VDD

CPUADR9

CPUADR8

CPUADR11

CPUADR10

CPUADR7

CPUADR12

Formatter

General purpose IO bus

CPUADR6

CPUADR5

CPUADR4

CPUADR3

CPUADR2

i /t

High speed IO bus

32 bit

CPU core

GCAL

VSS

CPUADR1

CPUADR0

ECC

NCS

NWR

NRD

VDD

CPUDT7

CPUDT6

PVPPDRAM

PVDDDRAM

PTESTDRAM

Host i / f

MPEG i / t

DMA

BCU

DRAMC

CPUDT5

CPUDT4

CPUDT3

PVSSDRAM

VSS

CPUDT2

ATAPI

4Mbit

DRAM

WDT

16 bit

timer x 2

SYSTEM

i / f

INTC

1-39

MX-DVA9/MX-DVA9R

3.Pin function (1/3)

Pin No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Symbol

HDD15

HDD0

HDD14

VDD

HDD1

HDD13

HDD2

VSS

HDD12

VDD

HDD3

HDD11

HDD4

HDD10

VDD
HDD5
HDD9

VSS
HDD6
HDD8
HDD7
VDDH

NRESET

MASTER

NINT0
NINT1

WAITDOC

NMRST

DASPST

VDD

OSCO2

OSCI2

UATASEL

VSS

PVSSDRAM
PVDDDRAM

CPUADR17
CPUADR16

VSS

CPUADR15
CPUADR14
CPUADR13
CPUADR12

VDD
CPUADR11
CPUADR10

CPUADR9
CPUADR8
CPUADR7
CPUADR6

I/O
I/O
I/O
I/O

­I/O
I/O
I/O

­I/O

­I/O
I/O
I/O
I/O

­I/O
I/O

­I/O
I/O
I/O

I

I/O

O
O
O
O

I

-

O

I
I

-

I
I

-

I
I
I
I

-

I
I
I
I
I
I

Description
ATAPI Data
ATAPI Data
ATAPI Data
Power supply 3V
ATAPI Data
ATAPI Data
ATAPI Data
Connect to GND
ATAPI Data
Power supply 2.7V
ATAPI Data
ATAPI Data
ATAPI Data
ATAPI Data
Power supply 3V
ATAPI Data
ATAPI Data
Connect to GND
ATAPI Data
ATAPI Data
ATAPI Data

ATAPI Reset input
ATAPI Master/slave select
Interruption of system control 0
Interruption of system control 1
Wait control of system control
Reset of system control (Connect to TP302)
Setting of initial value of DASP signal
Power supply 3V
Non connect
Non connect
Connect to VSS
Connect to GND
Connect to VSS
Connect to VDD(2.7V)
System control address
System control address
Connect to GND
System control address
System control address
System control address
System control address
Power supply 2.7V
System control address
System control address
System control address
System control address
System control address
System control address

1-40

3.Pin function (2/3)

MX-DVA9/MX-DVA9R

Pin No.

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

Symbol
CPUADR5
CPUADR4
CPUADR3
CPUADR2
CPUADR1

VSS

CPUADR0

NCS
NWR
NRD

VDD

CPUDT7
CPUDT6

PVPPDRAM

PTESTDRAM

PVDDDRAM
PVSSDRAM

CPUDT5
CPUDT4
CPUDT3

VSS

CPUDT2
CPUDT1
CPUDT0

CLKOUT1

VDD

TEHLD

DTRD

IDGT
BDO

CPDET2
CPDET1

VSS

MMOD

NRST

VDD

CLKOUT2

SBCK/PLLOK

IDOHOLD

JMPINH

LG

NTRON

DA CD ATA

DACLRCK

DACCLK

IPFLAG

BLKCK

LRCK

VSS

OSCI1

I/O

I
I
I
I
I

­I
I
I
I

­I/O
I/O

O

I

I/O
I/O
I/O

­I/O
I/O
I/O

O

-

O
O
O

I
I
I

-

I
I

-

O
O
O
O
O

I
O
O

I

I

I

I

-

I

Description
System control address
System control address
System control address
System control address
System control address
Connect to GND
System control address
System control chip select
Writing system control
Reading system control
Power supply 3V
System control data
System control data
Connect to VSS
Connect to VSS
Connect to VDD(2.7V)
Connect to VSS
System control data
System control data
System control data
Connect to GND
System control data
System control data
System control data
Clock signal output (16.9/11.2/8.45MHz)
Power supply 3V
Mirror gate (Connect to TP141)
Data frequency control switch (Connect to TP304)
CAPA switch
RF Dropout/BCA data
Outer capacity detection
Inner capacity detection
Connect to GND
Connect to VSS
System reset
Power supply 3V
Clock 16.9MHz
Flame mark detection
ID gate for tracking holding
Jump prohibition
Land/group switch
Tracking ON
Serial data output (Connect to TP148)
Identification signal of L and R (Connect to TP149)
Clock for serial data output
Input of IP flag
Sub code/block/input clock
Identification signal of L and R (Connect to VSS)
Connect to GND
Oscillation input terminal 16.9MHz

1-41

MX-DVA9/MX-DVA9R

3.Pin function (3/3)

Pin No.

101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

Symbol
OSCO1

VDD

PVSS

PVDD

P1
P0

VSS
SBCK
SUBC

NCLDCK

CHCK40

DAT3
DAT2
DAT1
DAT0

VDD

SCLOCK

S DATA
MONI3
MONI2
MONI1
MONI0

VSS

NEJECT

VDD

NTRYCL

NDASP

NCS3FX
NCS1FX

VDD

DA2
DA0

NPDIAG

VSS
DA1

NIOCS16

INTRQ

VDD

NDMACK

IORDY
NIORD

VSS

NIOWR

DMARQ

I/O

O

-

-

­I/O
I/O

-

O

I
I
I
I
I
I
I

­I/O
I/O

O
O
O
O

-

I

-

I

I/O

I
I

­I/O
I/O
I/O

­I/O

O
O

-

I

O

I

­I/O

O

Description
Oscillation output terminal 16.9MHz
Power supply 3V
Connect to GND
Power supply 3V
Terminal master polarity switch input
CIRC-RAM,OVER/UNDER Interruption
Connect to GND
Clock output for sub code,serial input
Sub code,serial input
Sub code,flame clock input
Clock is read to DAT3~0 (Output of division frequency from ADSC)
Data is read from disc (Going side by side output from ADSC)
Data is read from disc (Going side by side output from ADSC)
Data is read from disc (Going side by side output from ADSC)
Data is read from disc (Going side by side output from ADSC)
Power supply 3V
Debug serial clock (270 ohm pull up)
Debug serial data (270 ohm pull up)
Internal good title monitor (Connect to TP150)
Internal good title monitor (Connect to TP151)
Internal good title monitor (Connect to TP152)
Internal good title monitor (Connect to TP153)
Connect to GND
Eject detection
Power supply 2.7V
Non connect (Tray close detection)
ATAPI drive active / slave connect I/O
Non connect (ATAPI host chip select)
Non connect (ATAPI host chip select)
Power supply 3V
ATAPI host address
Non connect (ATAPI host address)
ATAPI Slave master diagnosis input
Connect to GND
Non connect (ATAPI host address)
Output of selection of width of ATAPI host data bus
ATAPI Host interruption output
Power supply 3V
Non connect (ATAPI Host DMA characteristic)
ATAPI Host ready output (Connect to TP157)
Non connect (ATAPI host read)
Connect to GND
ATAPI Host write
ATAPI Host DMA request (Connect to TP159)

1-42

MN101C49GEH 1(IC500): AV decorder

1.Terminal layout
~

100 76

1

~

75

~

MX-DVA9/MX-DVA9R

25

26 50

51

~

2.Pinfunction

Pin No.

1 VREF I Reference voltage
2 NC - No connect
3 NC - No connect
4 NC - No connect
5 NTSEL I NTSC/PAL selection
6 POWER SW ­7 SHUT1 ­8 KEY1-5 -

9 KEY6-10 ­10 VREF+ I
11 VDD I Power supply
12 OSC2 O External terminal for connected oscirator
13 OSC1 I External terminal for connected oscirator
14 VSS - Connect to GND
15 XI I External terminal for sub oscirator (Supply to voltage)
16 XO O No connect
17 MMOD I connects with gnd
18 DADATA I/O Data bus for DAC
19 DACS1 I/O Serial bus S1 for DAC
20 DCLK I/O Clock for DAC
21 S2UDT O
22 U2SDT I
23 SCLK I/O Serial clock bus
24 BUSY I/O Busy bus
25 CPURST O Unit microcomputer reset
26 REQ I Commnication between unit microcomputers REQ
27 REMO I Remote control interrruption
28 TEST1 - Test terminal
29 TEST2 - Test terminal
30 TEST3 - Test terminal
31 DVDCS I Chip select for DVD
32 NC - No connect
33 DVDRST I DVD reset
34 NC - No connect
35 DACS2 I/O Serial bus S2 for DAC
36 DACS3 I/O Serial bus S3 for DAC
37 NC - No connect
38 NC - No connect
39 FS2 I Over sampling frequency
40 CHREQ I Changer commnication REQUEST
41 CHST O Changer commnication STROBE
42 CHDATA O Changer commnication DATA I/O
43 NC - No connect

Symbol

I/O

No connect
No connect
No connect
No connect
Reference voltage

Function

Communication between unit microcomputers DATA output
Communication between unit microcomputers DATA output

1-43

MX-DVA9/MX-DVA9R

Pin No.

44 CHCK I Channel clock
45 DVDOUT O DVD data output
46 DVDIN I DVD data input
47 DVDCLK I DVD clock
48 DVDBSY Busy bus for DVD
49 NC - No connect
50 NC - No connect
51 NC - No connect
52 NC - No connect
53 NC - No connect
54 VS1 O Fanction SW control
55 VS3 O Fanction SW control
56 SL/SRMUTE O No connect
57 CMUTE O Center signal output mute
58 SWMUTE O No connect
59 POB2 O No connect
60 DEMP2 O No connect
61 DEMP1 O No connect
62 DENA O No connect
63 KARAOKE O No connect
64 POWER ON O Power on control output
65 VS2 O Fanction SW control
66 NC - No connect
67 NC - No connect
68 NC - No connect
69 NC - No connect
70 NC - No connect
71 NC - No connect
72 NC - No connect
73 NC - No connect
74 NC - No connect
75 NC - No connect
76 NC - No connect
77 AVCI I Power supply
78 AVCO I/O AV compu link signal I/O port
79 RGB I RGB signal in
80 STD IND O Standby LED output
81 MPX1 I MPX1 signal input
82 MPX2 I MPX2 signal input
83 SRELAY O S. Relay control
84 MRELAY O M. Relay control
85 BASS1 O BASS1 switching
86 BASS2 O BASS2 switching
87 FCD O CD power supply control signal
88 PBMUTE O PB mute
89 AUXMUTE O AUX mute
90 SMUTE O System mute output
91 NC - No connect
92 NC - No connect
93 NC - No connect
94 NC - No connect
95 DAVSS - Connect to GND
96 NC - No connect
97 NC - No connect
98 NC - No connect
99 HPMUTE O Head phone mute

100 VREF- I

Symbol

I/O

Connected GND

Function

1-44

ZIVA-4.1-PA2 (IC501) : AV decoder

1.Terminal layout
~

208 157

1

~

156

~

MX-DVA9/MX-DVA9R

52

~

53 104

2.Pin function (1/5)

Pin No.

1
2
3
4

5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

30

31
32
33
34
35
36

Symbol

RD

R/W

VDD

WAIT

RESET

VSS
VDD

INT

NC
NC
NC

NC
VDD
VSS

NC

NC

NC

NC
VSS
VDD

V DATA 0
V DATA 1
V DATA 2
V DATA 3
V DATA 4
V DATA 5
V DATA 6
V DATA 7

VSYNC

HSYNC

VSS
VDD

NC

NC

NC
VDD

105

I/O

I
I

-

O

I

-

-

O

-

-

-

-

-

-

-

-

-

-

-

­O
O
O
O
O
O
O
O

I/O

I/O

-

-

-

-

-

-

Description
Read strobe input
Read/write strobe input
Power supply terminal 3.3V
Transfer not complete / data acknowledge.
Active LOW to indicate host initiated transfer is complete.
Active LOW : reset signal input
Connect to ground
Power supply terminal 3.3V
Host interrupt signal output
Non connect
Non connect
Non connect
Non connect
Power supply terminal 2.5V
Connect to ground
Non connect
Non connect
Non connect
Non connect
Connect to ground
Power supply 3.3V
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Video data bus output. Byte serial CbYCrY data synchronous with VCLK.
Vertical sync. Bi-directional, the decoder output the top border of a new
field on the first HSYNC after the falling edge of VSYNC.
Horizontal sync. The decoder begins outputting pixel data for a new
horizontal line after the falling (active) edge of HSYNC.
Connect to ground
Power supply terminal 3.3V
Non connect
Non connect
Non connect
Power supply terminal 2.5V

1-45

MX-DVA9/MX-DVA9R

2.Pin function (2/5)

Pin No.

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

Symbol

VSS

NC
NC
NC
NC
NC

PIO0

VSS

VDD
PIO1
PIO2
PIO3
PIO4
PIO5
PIO6
PIO7

M DATA 0
M DATA 1

VDD

VSS

M DATA 2
M DATA 3
M DATA 4
M DATA 5
M DATA 6
M DATA 7

MDATA15

VDD

VSS

MDATA14

VDD

VSS

MDATA13
MDATA12
MDATA11
MDATA10

M DATA 9

VDD

VSS

M DATA 8

LDQM

SD-CLK

CLKSEL
MADDR9
MADDR8

VDD
VSS

MADDR7

I/O

Connect to ground

­Non connect

­Non connect

­Non connect

­Non connect

­Non connect

­Programmable I/O terminal

I/O

Connect to ground

­Power supply terminal 3.3V

­Programmable I/O terminal

I/O

Programmable I/O terminal

I/O

Programmable I/O terminal

I/O

Programmable I/O terminal

I/O

Programmable I/O terminal

I/O

Programmable I/O terminal

I/O

Programmable I/O terminal

I/O

SDRAM data

I/O

SDRAM data

I/O

Power supply terminal 3.3V

­Connect to ground

­SDRAM data

I/O

SDRAM data

I/O

SDRAM data

I/O

SDRAM data

I/O

SDRAM data

I/O

SDRAM data

I/O

SDRAM data

I/O

Power supply terminal 3.3V

­Connect to ground

­SDRAM data

I/O

Power supply terminal 2.5

­Connect to ground

­SDRAM data

I/O

SDRAM data

I/O

SDRAM data

I/O

SDRAM data

I/O

SDRAM data

I/O

Power supply terminal 3.3V

­Connect to ground

­SDRAM data

I/O

SDRAM Lower or upper mask

O

SDRAM Clock

O

Selects SYSCLK or VCLK as clock source. Normal operation is to tie HIGH.

I

SDRAM address

O

SDRAM address

O

Power supply terminal 3.3V

­Connect to ground

­SDRAM address

O

Description

1-46

2.Pin function (3/5)

MX-DVA9/MX-DVA9R

Pin No.

85
86
87
88
89
90
91
92
93
94
95
96
97
98

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118

119

120

121

122
123
124
125
126
127
128

Symbol

MADDR6
MADDR5

VDD

VSS

MADDR4

MWE

SD-CAS

VDD

VSS

SD-RAS

SD-CS0

SD-CS1/MADDR11

SD-BS

MADDR10

MADDR0

VDD

VSS
MADDR1
MADDR2
MADDR3

RESERVED

NC
NC

RESERVED

NC
RESERVED
RESERVED
RESERVED

DAI-LRCK

DAI-BCK

VDD

VSS

DAI-DATA

DA-DATA3

DA-DATA2

DA-DATA1

DA-DATA0

DA-LRCK

VDD

VSS
DA-XCK
DA-BCK

DA-IEC

VDD

I/O

SDRAM address

O

SDRAM address

O

Power supply terminal 2.5V

­Connect to ground

­SDRAM address

O

SDRAM write enable

O

Active LOW SDRAM column address

O

Power supply terminal 3.3V

­Connect to ground

­Active LOW SDRAM row address

O

Active LOW SDRAM chip select 0

O

Active LOW SDRAM chip select 1 or use as MADDR11 for larger SDRAM

O

SDRAM bank select

O

SDRAM address

O

SDRAM address

O

Power supply terminal 3.3V

­Connect to ground

­SDRAM address

O

SDRAM address

O

SDRAM address

O

Tie to VSS or VDD_3.3 as specified in table1

I

Non connect

­Non connect

­Tie to VSS or VDD_3.3 as specified in table1

I

Non connect

­Tie to VSS or VDD_3.3 as specified in table1

I

Tie to VSS or VDD_3.3 as specified in table1

I

Tie to VSS or VDD_3.3 as specified in table1

I

PCM left/right clock

I

PCM input bit clock

I

Power supply 3.3V

­Connect to ground

­PCM data input

I

PCM data output. Eight channels. Serial audio samples relative to

O

DA_BCK and DA_LRCK
PCM data output. Eight channels. Serial audio samples relative to

O

DA_BCK and DA_LRCK
PCM data output. Eight channels. Serial audio samples relative to

O

DA_BCK and DA_LRCK
PCM data output. Eight channels. Serial audio samples relative to

O

DA_BCK and DA_LRCK
PCM left clock. Identifies the channel for each sample

O

Power supply terminal 3.3V

­Connect to ground

­Audio external frequency clock input or output

I/O

PCM bit clock output

O

PCM data out in IEC-958 format or compressed data out in IEC-1937 format

O

Power supply terminal 2.5V

-

Description

1-47

MX-DVA9/MX-DVA9R

2.Pin function (4/5)

Pin No.

129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162

163

164

165

166
167
168

169

Symbol

VSS

NC

VSS_DAC

VSS_VIDEO

CVBS

VDD_DAC

VDD_VIDEO

NC

VSS_DAC

VSS_VIDEO

CVBS/G/Y

VDD_DAC

VDD_VIDEO

NC

VSS_DAC

VSS_VIDEO

Y/B/U

VDD_DAC

VDD_VIDEO

NC

VSS_DAC

VSS_VIDEO

C/R/V

VDD_DAC

VDD_VIDEO

VSS_RREF

RREF

VDD_RREF

A_VSS

SYSCLK

VCLK

A_VDD

DVD-DATA0/CD-DATA

DVD-DATA1/CD-LRC

DVD-DATA2/CD-BCK

DVD-DATA3/CD-C2PO

DVD-DATA4/CDGSDATA

VSS
VDD

DVD-DATA5/CDG-VFSY

DVD-DATA6/CDG-SOS1

I/O

Connect to ground

­Non connect

­Connect to ground for analog video DAC

­Connect to ground for analog video

­DAC video output format : CVBS. Macrovision encoded

O

Power supply terminal for analog video DAC

­Power supply terminal for analog video

­Non connect

­Connect to ground for analog video DAC

­Connect to ground for analog video

­DAC video output format. Macrovision encoded

O

Power supply terminal for analog video DAC

­Power supply terminal for analog video

­Non connect

­Connect to ground for analog video DAC

­Connect to ground for analog video

­DAC video output format. Macrovision encoded

O

Power supply terminal for analog video DAC

­Power supply terminal for analog video

­Non connect

­Connect to ground for analog video DAC

­Connect to ground for analog video

­DAC video output format. Macrovision encoded

O

Power supply terminal for analog video DAC

­Power supply terminal for analog video

­Connect to ground for analog video

­Reference resistor. Connecting to pin 154

O

Power supply terminal for analog video 3.3V

­Power supply terminal for analog PLL 3.3V

­Optical system clock. Tie to A_VDD through a 1K ohm resistor

I

System clock input

I

Power supply terminal for analog PLL 3.3V

­Serial CD data. This pin is shared with DVD compressed data DVD-DATA0

I

Programmable polarity 16-bit word synchronization to the decoder.

I

Description

This pin is shared with DVD compressed data DVD-DATA1
CD bit clock. Decoder accept multiple BCK rates. This pin is shared with

I

DVD compressed DVD-DATA2
Asserted HIGH indicates a corrupted byte. This pin is shared with DVD

I

compressed data DVD-DATA3
DVD parallel compressed data from DVD DSP. or CD-G data indicating

I

serial subcode data input
Connect to ground

­Power supply terminal 3.3V

­DVD parallel compressed data from DVD DSP. or CD-G frame sync

I

indicating frame-start or composite synchronization input.
DVD parallel compressed data from DVD DSP. or CD-G block sync

I

indicating block-start synchronization input

1-48

2.Pin function (5/5)
Pin No.

170

171

172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197

198
199

200

201

202

203

204
205
206

207

208

Symbol

DVD-DATA7/CDG-SCLK

VDACK

VREQUEST

VSTROBE

ERROR

VDD

RESERVED

VDD

VSS

NC

RESERVED

NC
HADDR0
HADDR1
HADDR2

RESERVED
RESERVED
RESERVED

VSS

VDD

RESERVED

VSS

VDD
RESERVED
RESERVED
RESERVED
RESERVED

H DATA 7

VSS

H DATA 6

H DATA 5

H DATA 4

H DATA 3

H DATA 2

VDD

VSS

H DATA 1

H DATA 0

CS

MX-DVA9/MX-DVA9R

I/O

DVD parallel compressed data from DVD DSP. or CD-G clock indicating

I

sub code data clock input or output
In synchronous mode, bitstream data acknowledge. Asserted when DVD

I

data is valid.Polarity is programmable
Bitstream request

O

Bitstream strobe

I

Error in input data

I

Power supply terminal 3.3V

­Tie to VSS or VDD_3.3 as specified in table 1

I

Power supply terminal 3.3V

­Connect to ground

­Non connect

­Tie to VSS or VDD_3.3 as specified in table 1

I

Non connect

-

Host addressbus. 3-bit address bus selects one of eight host interface registers

I

Host addressbus. 3-bit address bus selects one of eight host interface registers

I

Host addressbus. 3-bit address bus selects one of eight host interface registers

I

Tie to VSS or VDD_3.3 as specified in table 1

I

Tie to VSS or VDD_3.3 as specified in table 1

I

Tie to VSS or VDD_3.3 as specified in table 1

I

Connect to ground

­Power supply terminal 2.5V

­Tie to VSS or VDD_3.3 as specified in table 1

I

Connect to ground

­Power supply terminal 3.3V

­Tie to VSS or VDD_3.3 as specified in table 1

I

Tie to VSS or VDD_3.3 as specified in table 1

I

Tie to VSS or VDD_3.3 as specified in table 1

I

Tie to VSS or VDD_3.3 as specified in table 1

I

The 8-bit bi-derectional host data through which the host writes data to

I/O

the decoder code.
Connect to ground

­The 8-bit bi-derectional host data through which the host writes data to

I/O

the decoder code.
The 8-bit bi-derectional host data through which the host writes data to

I/O

the decoder code.
The 8-bit bi-derectional host data through which the host writes data to

I/O

the decoder code.
The 8-bit bi-derectional host data through which the host writes data to

I/O

the decoder code.
The 8-bit bi-derectional host data through which the host writes data to

I/O

the decoder code.
Power supply terminal 3.3V

­Connect to ground

­The 8-bit bi-derectional host data through which the host writes data to

I/O

the decoder code.
The 8-bit bi-derectional host data through which the host writes data to

I/O

the decoder code.
Host chip select input

I

Description

1-49

MX-DVA9/MX-DVA9R

KM416S1120DT-G8 or W981616AH-7 (IC504,IC505) : 16M SDRAM

1.Terminal layout

1

VDD

DQ0

2

DQ1

3
4

VSSQ

5

DQ2

6

DQ3

7

VDDQ

8

DQ4

9

DQ5

10

VSSQ

11

DQ6

12

DQ7

13

VDDQ
LDQM

14
15

WE

16

CAS

17

RAS

18

CS

19

BA

VDD

20

A0

21

A1

22
23

A2
A3

24
25

A10/AP

2.Pin function

Pin No Symbol Function.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

VCC
DQ0
DQ1

VSSQ

DQ2
DQ3

VSSQ

DQ4
DQ5

VSSQ

DQ6

DQ7
VCCQ
LDQM

-WE

-CAS

-RAS
CS

A11
A10

A0
A1
A2
A3

VCC

50
49
48
47
46

45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

I/O

I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O

O

Vss
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
Vss

-

Power supply
Data input/output
Data input/output
Connect to GND

­Data input/output
Data input/output
Power supply

­Data input/output

Data input/output

-

Connect to GND
Data input/output
Data input/output
Power supply

­Data input/output mask
Write enable

I

Colum address strobe

I

Row addres strobe

I

Chip select

I

Bank select adress
Address input

I

Address input

I

Address input

I

Address input

I

Address input

I

Power supply

-

Pin No Symbol Function.

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

VSS

A4
A5
A6
A7
A8
A9

NC
CKE
CLK

UDQM

NC

VCCQ

DQ8
DQ9

VSSQ

DQ10

DQ11
VCCQ
DQ12
DQ13

VSSQ

DQ14
DQ15

VSS

I/O

O

I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O

Connect to GND

­Address input

I
I

Address input
Address input

I

Address input

I
I

Address input
Address input

I

No connect

­Clock enable

I

System clock input

I

Data input/output mask
No connect

­Power supply

­Data input/output
Data input/output
Connect to GND

­Data input/output
Data input/output
Power supply

­Data input/output
Data input/output

Connect to GND

­Data input/output
Data input/output

Connect to GND

-

1-50

MN67706ZY (IC201) : Auto digital servo controller

1.Terminal layout

33VDD

33VSS

TEST

MINTEST

NCLDCK/JUMP

SUBC

IPFLAG

DACCLK

NTRON

DACDATA/LG

DACLRCK/JMPINH

IDHOLD

SBCK/PLLOK

BLKCK/CPDET1

LRCK/CPDET2

IDGT/TEMUTE

DTRD

25VDD

25VSS

TILTN

75747372717069686766656463626160595857565554535251

CHCK40

DAT3
DAT2
DAT1
DAT0

33VSS

33VDD

XRESET

ENS

ENC

CPUIRQ

CPUCLK

CPUDTIN

CPUDTOUT

MONA
MONB
MONC

25VSS

25VDD
LDCUR(AD6)
TDOFS(AD5)

TG(AD4)

RFENV(AD3)

NC

TX

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

123456789

MN67706ZY

101112131415161718192021222324

TILT

TILTPFGSPDRV

TRSDRV

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

25

TSTSG
BDO
SYSCLK
OFTR
33VDD
33VSS
FBAL
TBAL
TGBAL
AVSS
ROUT
LOUT
AVDD
JLINE
DBALO
VCOF
TRCRS
CMPIN
LPFOUT
LPFIN
AVSS
HPFOUT
HPFIN
AVDD
VFOSHORT

MX-DVA9/MX-DVA9R

TE(AD1)

FE(AD0)

AS(AD2)

AVSS

AVDD

TRDRV(DA0)

FODRV(DA1)

ARF

NARF

IREF1

IREF2

DSLF1

AVDD

DSLF2

PLPG

VHALF

PLFG

2.Pin functions (1/3)

Pin No. Symbol I/O Function

O
O

I/O
I/O

I/O

O
O

I/O

I/O

I
I
I

-

AS : Full adder signal(FEP)
Phase difference/3 beam tracking error(FEP)
Focus error(FEP)
Apply 3.3V(For analog circuit)
Focus drive(DRVIC)
Tracking drive(DRVIC)

­I
I
I
I

Ground(For analog circuit)
Equivalence RF+(FEP)
Equivalence RF-(FEP)
Reference current1(For DBAL)
Reference current2(For DBAL)
Connect to capacitor1 for DSL
Connect to capacitor2 for DSL

­I

-

­I

Apply 3.3V(For analog circuit)
Reference voltage 1.65+-0.1V(FEP)
Not use(PLL phase gain setting resistor terminal)
Not use(PLL frequency gain setting resistor terminal)
Reference voltage 2.2V+-0.1V(FEP)
Connect to resistor for VREFH reference current source

-

Ground(For analog circuit)
Connect to capacitor1 for PLL
Connect to capacitor2 for PLL
Output for jitter signal monitor

I

Not use
Pull-up to VHALF

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

AS(AD2)
TE(AD1)
FE(AD0)
AVDD
FODRV(DA1)
TRDRV(DA0)
AVSS
ARF
NARF
IREF1
IREF2
DSLF1
DSLF2
AVDD
VHALF
PLPG
PLFG
VREFH
RVI
AVSS
PLFLT1
PLFLT2
JITOUT
RFDIF
CSLFL1

RVI

VREFH

AVSS

PLFLT1

RFDIF

JITOUT

PLFLT2

CSLFL1

1-51

MX-DVA9/MX-DVA9R

2.Pin function (2/3)

Pin No. Symbol I/O Function

VFOSHORT

26

AVDD

27

HPFIN

28

HPFOUT

29

AVSS

30

LPFIN

31

LPFOUT

32

CMPIN

33

TRCRS

34

VCOF

35

DBALO

36

JLINE

37

AVDD

38

LOUT

39

ROUT

40

AVSS

41

TGBAL

42

TBAL

43

FBAL

44

33VSS

45

33VDD

46

OFTR

47

SYSCLK

48

BDO

49

TSTSG

50

TRSDRV

51

SPDRV

52

FG

53

TILTP

54

TILT

55

TILTN

56

25VSS

57

25VDD

58

DTRD

59
60

IDGT/TEMUTE

61

LRCK/CPDET2

62

BLKCK/CPDET1

63

SBCK/PLLOK

64

IDHOLD

65

DACLRCK/JMPINH

66

DACDATA/LG

67

NTRON

68

DACCLK

69

IPFLAG

70

SUBC

71

NCLDCK/JUMP

72

MINTEST

73

TEST

74

33VSS

75

33VDD

76

CHCK40

77

DAT3

78

DAT2

79

DAT1

80

DAT0

O

O

O

I/O

O
O

O
O

O
O
O

O
O
O

O
O
O

O
O

O
O
O
O
O

O
O
O
O
O

VFO short output

­I

­I

I
I

-

-

-

­I
I
I

I

-

­I
I

I
I
I
I

I
I

-

-

Apply 3.3V(For analog circuit)
Pull-up to VHALF
Connect to TP208
Ground(For analog circuit)
Pull-up to VHALF
Not use
Connect to TP210
Input signal for track cross formation
JFVCO control voltage
DSL balance adjust output
J-line setting output(FEP)
Apply 3.3V(For analog circuit)
Connect to TP203 (Analog audio left output)
Connect to TP204 (Analog audio right output)
Ground(For analog circuit)
Tangential balance adjust(FEP)
Tracking balance adjust(FEP)
Focus balance adjust(FEP)
Ground(For I/O)
Apply 3.3V(For I/O)
Off track signal

16.9344MHz system clock input(ODC)
Drop out(FEP)
Calibration signal(FEP)
Traverse drive(DRVIC)
Spindle drive output(DRVIC)
FG signal input (Spindle motor driver)
Connect to TP205
Connect to TP206
Connect to TP207
Ground(For internal core)
Apply 2.5V(For internal core)
Data read control signal(ODC)
Pull-down to Ground
LR channel data strobe(ODC)/
CD sub code synchronous signal(ODC)/
CD sub code data shift clock(ODC)/PLL pull-in OK signal input
Pull-down to Ground
1bit DAC-LR channel data strobe(ODC)/
CD 1bit DAC channel data(ODC)
L : Tracking ON(ODC)
1bit DAC channel data shift clock(ODC)
CIRC error flag(ODC)
CD sub code(ODC)
CD sub code data frame clock(ODC)/DVD JUMP signal(ODC)
Pull-down to Ground(For MINTEST)
Pull-down to Ground(For TEST)
Ground(For I/O)
Apply 3.3V(For I/O)
Clock for SRDATA(ODC)
SRDATA3(ODC)
SRDATA2(ODC)
SRDATA1(ODC)
SRDATA0(ODC)

1-52

2.Pin function (3/3)

Pin No. Symbol I/O Function

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

33VSS
33VDD
TX
XRESET
ENS
ENC
CPUIRQ
CPUCLK
CPUDTIN
CPUDTOUT
MONA
MONB
MONC
NC
25VSS
25VDD
LDCUR(AD6)
TDOFS(AD5)
TG(AD4)
RFENV(AD3)

-

-

O

O

O
O
O
O
O

-

-

Ground(For I/O)
Apply 3.3V(For I/O)
Digital audio interface

I

Reset input (System control)

I

Servo DSC serial I/F chip select (System control)

I

CIRC serial I/F chip select (System control)
Interrupt request (System control)

I

Syscon serial I/F clock (System control)

I

Syscon serial I/F data input (System control)
Syscon serial I/F data output (System control)
Connect to TP226 (Monitor terminal A)
Connect to TP225 (Monitor terminal A)
Connect to TP224 (Monitor terminal A)
Connect to TP211
Ground(For internal core)

Apply 2.5V(For internal core)
I
I
I

Tangential phase difference(FEP)
I

RF envelope input(FEP)

MX-DVA9/MX-DVA9R

1-53

MX-DVA9/MX-DVA9R

AN7345K (IC302) : REC/PRE amp

1.Terminal layout & block diagram

24 23 22 21 20 19 18 17 16 15 14 13

123456789101112

2.Pin function

Pin No.

I/O
1
2
3
4

O
5
6

O
7
8
9

10
11

O

O

O

12
13
14

O

15
16

O

17
18
19

O

20
21

O

22
23
24

EQ

CTRL

Pre
Source
CTRL

REC
Amp

REC
Amp

ALC

REPPLE

REJ

Amp

Amp

PRE

PRE

Function
I
I
I

CH1 Playback amplifier input(1)
CH1 Playback amplifier input(2)
CH1 Playback amplifier negative feedback
CH1 Playback amplifier output

I

CH1 Equalizer input
Pre amplifier input control time constant

I
I

CH1 Recoding amplifier input
CH1 Recoding amplifier negative output
CH1 Recoding amplifier output
ALC low cut
ALC L.P.F

-

-

Connect to GND
Power supply
Repple filter

I

Equalizer control

CH2 Recoding amplifier output
I
I

CH2 Recoding amplifier negative output

CH2 Recoding amplifier input

Pre amplifier input control
I

CH2 Equalizer input

CH2 Playback amplifier output
I

I
I

CH2 Playback amplifier negative feedback

CH2 Playback amplifier input(2)

CH2 Playback amplifier input(1)

1-54

LA1838 (IC1) : FM AM IF AMP & Detector, FM MPX Decoder

1. Block diagram

MX-DVA9/MX-DVA9R

30

ALC

BUFF

FM
S-METER

FM IF

1

2. Pin function

Pin

Symbol

No.

FM IN

1

AM MIX

2

3

FM IF

AM IF

4

GND

5

6

TUNED

STEREO

7

8

VCC

9

FM DET

10

AM SD

FM VSM

11

AM VSM

12

13

MUTE

14

FM/AM

MONO/ST O

15

29

AM

OSC

SD
COMP

S-CLRVE

PM
DET

2

I/O

I

This is an input terminal of FM IF

28

REG

AM

MIX

AM/FM
IF-BUFF

3

27

FM

RF.AMP

AM IF

4

26

AGC

AM
S-METER

GND

Function

DET

5

signal.

This is an out put terminal for AM

O

mixer.

I

Bypass of FM IF

Input of AM IF Signal.

I

I

This is the device ground terminal.

When the set is tunning,this terminal

O

becomes "L".

O

Stereo indicator output. Stereo "L",
Mono: "H"

III

This is the power supply terminal.

I

FM detect transformer.

I

This is a terminal of AM ceramic filter.

O

Adjust FM SD sensitivity.

O

Adjust AM SD sensitivity.

I/O

When the signal of IF REQ of IC121(
LC72131) appear, the signal of FM/AM
IF output. //Muting control input.

Change over the FM/AM input.

I

"H" :FM, "L" : AM

Stereo : "H", Mono: "L"

25

TUNING
DRIVE

6

24

STEREO
DRIVE

7

22

23

P-DET

VCC

89

Pin

Symbol

No.

16

L OUT

17

R OUT

18

19

20

21

22

23

24

25

26

27

28

29

30

L IN

R IN

RO

LO

MPX IN

FM OUT

AM DET

AM AGC

AFC

AM RF

REG

AM OSC

OSC BUFFER

21

DECODER
ANIT-BIRDIE

VCO
384KHz

10

20

STEREO
5N
SW

FF
38k

11

I/O

O

Left channel signal output.

O

Right channel signal output.

Input terminal of the Left channel post

I

18

19

MUTE

FF

/

19k

2

12 13

FF
19k

/

LS

Function

17 16

PILOT
DET

14

AMP.

Input terminal of the Right channel

I

post AMP.

Mpx Right channel signal output.

O

O

Mpx Left channel signal output.

I

Mpx input terminal

FM detection output.

O

AM detection output.

O

This is an AGC voltage input terminal

I

for AM

I

This is an output terminal of voltage
for FM-AFC.

AM RF signal input.

I

Register value between pin 26 and pin28

O

besides the frequency width of the
input signal.

I

This is a terminal of AM Local
oscillation circuit.

AM Local oscillation Signal output.

O

15

1-55

MX-DVA9/MX-DVA9R

LC72136N (IC2) : PLL Frequency synthesizer

1. Pin layout

FM/AM

CLOCK

FM/ST/VCO

AM/FM

2. Block diagram

XT

CE

DI

DO

SDIN

1
2
3
4
5
6
7
8
9
10
11

22
21
20
19
18
17
16
15
14
13
12

XT
GND
LPFOUT
LPFIN
PD
VCC
FMIN
AMIN

IFCONT
IFIN

1

22

16

15

3

4

5

6

17

21

3. Pin function

Pin

Symbol

No.

1

2

3

4

5

6

7

8

9

10

11

XT

FM/AM

CE

DI

CLOCK

DO

FM/ST/VCO

AM/FM

LW

MW

SDIN

Reference

Driver

Swallow Counter

1/2

C

2

B

I/F

Powe r

on

Reset

Function

I/O

X'tal oscillator connect (75kHz)

I

LOW:FM mode

O

When data output/input for 4pin(input) and

I

Swallow Counter

1/16,1/17 4bit

1/16,1/17 4bit

12bit

Programmable

DriverS

Data Shift Register & Latch

7821113

6pin(output): H

Input for receive the serial data from

I

controller

Sync signal input use

I

Data output for Controller

O

Output port

"Low": MW mode

O

Open state after the power on reset

O

Input/output port

I/O

Input/output port

I/O

Data input/output

I/O

Phase

Detector

Charge Pump

Unlock

Detector

Universal

Counter

Pin
No.

12

IFCONT

13

14

15

16

17

18

19

LPFOUT

20

21

22

Symbol

IFIN

AMIN

FMIN

VCC

PD

LPFIN

GND

XT

18

19

20

12

I/O

Function
IF counter signal input

I

IF signal output

O

Not use

-

AM Local OSC signal output

I

FM Local OSC signal input

I

Power suplly(VDD=4.5-5.5V)

­When power ON:Reset circuit move

PLL charge pump output(H: Local OSC

O

frequency Height than Reference frequency.

L: Low Agreement: Height impedance)

Input for active lowpassfilter of PLL

I

Output for active lowpassfilter of PLL

O

Connected to GND

­X'tal oscillator(75KHz)

I

1-56

LC75342M-X (IC522,IC523) : E. volume

1. Terminal layout
30 16~

115~

10

9 8 8 7 5

11

MX-DVA9/MX-DVA9R

12

13

14
15
16
17

18

19

20

CONTROL

CIRCUIT

LOGIC

CIRCUIT

CONTROL

CIRCUIT

3. Pin function

Pin

Symbol Symbol

No.

DI

1
2
3
4
5
6
7
8

VSS
TEST
LOUT

LBASS2
LBASS1

LTRE

Serial data and clock input for IC control

CE

Chip enable
Connect to GND
Electric volume connection for test
Volume control and equalizer input
Connection for resistor and capacitor that

the bass band filter

from
Connection for capacitor that from the

Function

treble band filter
Volume control and equalizer input

LIN

9
10
11
12
13
14
15
16

LSEL0

Input selector output
Not used

L4

Input signal connections, not used

L3

Input signal connections

L2

Input signal connections

L1

Connect to GND

NC

Connect to GND

NC

Pin
No.

17
18
19
20
21

RSEL0
22
23

RBASS1

24

RBASS2

25
26
27
28

29
30

CCB

INTERFACE

R1
R2
R3
R4

RIN

RTRE

ROUT

NC

VREF

VDD

CL

4

LVref

RVref

262524232221

3

2

1

30

29

28

27

Function

Input signal connections
Input signal connections
Input signal connections, not used
Not used
Input selector output
Volume control and equalizer input
Connection for capacitor that from the treble
band filter
Connection for resistor and capacitor that from
the bass band filter
Volume control and equalizer input
Not used
Connection to the 0.5X VDD voltage generator
circuit used as the analog signal ground
Power supply
Serial data and clock input for IC control

1-57

MX-DVA9/MX-DVA9R

LC75345M-X (IC521) : Input selector

1.Terminal layout

36 19~

118~

2.Block diagram

13

12

11

LVref

RVref

CONTROL

CIRCUIT

LOGIC

CIRCUIT

CONTROL

CIRCUIT

10

9

8

7

CCB

INTERFACE

2423222120191817161514

25

26

27

28

29

30

3. Pin function

Pin

Symbol Symbol

No.

DI

1
2
3

LOPOUT

4

VSS

Serial data input

CE

Chip enable
Connect to GND
Output pin of genral purpose

Function

operation amplifier

LINM

5

Non-inverterd pin of general
purpose operation amplifier
No connect

NC

6
7
8

9
10
11

LOUT

LSB
LBASS2
LBASS1

LTRE

Att + equalizer output
Capacitor and resistor connection
pins comprising filters
for bass and super-bass band
Capacitor connection pin comprising
treble band filter
Volume input

LIN

12
13
14
15
16
17
18
19

LSEL0

AUXL

TUL

PBL

DVDL

Input selector output pin
No connect

NC

Aux Lch signal input pin
Tuner Lch signal input pin
Playback Lch signal input pin
DVD Lch signal input pin

0.5 X VDD voltag genration
block for analog ground

31

Pin
No.

19

20
21
22
23
24
25
26
27

28
29
30
31
32
33

34

35
36

VREF

DVDR

PBR
TUR

AUXR

NC

RSEL0

RIN

RTRE

RBASS1
RBASS2

RSB

ROUT

NC

RINM

ROPOUT

VDD

CL

3233343536123456

Function

0.5 X VDD voltage genration
block for analog ground
DVD Rch signal input pin
Playback Rch signal input pin
Tuner Rch signal input pin
Aux Rch signal input pin
No connect
Input selector output pin
Volume input
Capacitor connection pin
comprising terble band filter
Capacitor and resistor connection
pins comprising
filters for bass and superbass band
Att + equalizer output
No connect
Non-inverterd pin of general
purpose operation amplifier
Output pin of genral purpose
operation amplifier
Power supply
Clock input

1-58

LV1100M (IC550) : Karaoke mic echo surround amp.

1.Terminal layout

24 13~

112~

2.Block diagram

MX-DVA9/MX-DVA9R

24

OSC

5KX2
L.P.F.

SRAM 12K

D/A CONV.

PIN

1

3. Pin function

Pin No.

1 VSS
2
3
4
5
6
7

CLOCK

DATA

ENABLE

REV-OUT

REV-IN

VCC
8
9

IN-R

10
11
12

OUT-A

DC-OUT
13
14
15
16
17
18

VREF

OUT-R

OUT-L

AGND

DC-OUT
19
20
21
22

VDD

23
24

23

A/D CONV.

2

IN-L

IN-A

LPF

A/D
A/D
D/A

X2
X1

20PIN

22

REG

19PIN

DEC

21

DC-CUT

12PIN

18PIN

DC-CUT

3

4

I/OSymbol

­I
I
I

O

I

­I
I

I
O
O

I

I
O
O

-

O

I

I

I

-

O

I

20

5

EFECT VOL

7KHZ L.P.F

19

18

REF

REF

6

7

17

REF

REF

REF

8

16

REF

Function
Connect to GND
Clock for communicated data
Amp. control data
Control signal enable
Reverse signal output
Reverse signal input
Power supply
Analog signal input L
Analog signal input R
N.C.
N.C.
DC-output
External terminal for low pass filter
Reference voltage
Analog signal output R
Analog signal output L
Connect to GND
DC-output
External terminal for A/D
External terminal for A/D
External terminal for D/A
Power supply
External terminal for oscillator

External terminal for oscillator

15

REF

REF

REF

9

10

14

REF

REF

REF

REF

11

13

12

1-59

MX-DVA9/MX-DVA9R

M56788FP-W (IC271) : Traverse mechanism driver

1.Terminal layout

CH3IN

OUT3

VBS2

Vm2

GND

IN3+

VM3-

VM3+

GND

VM4+

VM4-

VM5+

VM5-

OUT5

IN5+
IN4+

OUT4

IN3-

N.C

IN5-

IN4-

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

REG+
REGB
IN1+
VBS1
Vm1
IN1­OUT1
VM1­VM1+
GND
VM2+
VM2­OUT2
GND
IN2­IN2+
MUTE1
MUTE2
SS.GND
VREF
VERFO

2.Block diagram

Vm1

IN1+

IN1-

OUT1

VM1(+)

VM1(-)

VM2(+)

VM2(-)

OUT2

IN2-

IN2+

VREF0

VREF

REGB
REG+

VBS2

VREG

CH1
X5

CH2
X5

VBS1

VREF

E1

E2

VBS1

VBS1

VBS1

VBS1

1.25V

VBS1 VBS2

R

RR

Vrefm1 Vrefm2

Vm1 Vm2

R

VREF0

BIAS

Low, Open
MUTE ON

1~4
CH

VBS1

Hi:Sleep

SLEEP

5CH

TSD

VBS2

VBS2

VBS2

VBS2

VBS2

VBS2

E3

CH3

X8

CH4

X8

E4

CH5

X8

E5

Vm2

IN3­IN3+
OUT3
CH3IN

VM3(+)

VM3(-)

VM4(+)

VM4(-)

IN4­IN4+
OUT4

VM5(+)

VM5(-)

IN5­IN5+
OUT5

SS.GND

1-60

MUTE1 MUTE2

GND (4PIN)

MN35505 (IC501,IC502,IC503) : DAC

1.Terminal layout

28 15~

114~

2. Pin function

MX-DVA9/MX-DVA9R

Pin No.

1M5
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

24
25 M7
26 M8
27 M4

28 M6

DIN

LRCK

BCK

M3

DVDD2

CKO

DVSS2

M2

M1
OUT1C
AVDD1
OUT1D

AVSS1

AVSS2
OUT2D
AVDD2
OUT2C

M9

DVSS2

XOUT

XIN

VCOF

DVDD1

I/OSymbol

I
I

I
I
I

-

-

­I
I

O

-

O

-

-

O

-

O

I

-

-

­I

-

-

­I

I

Control signal for DAC
Digital data input

L and R clock for DAC
Bit clock for DAC
Control signal for DAC
Power supply
No connect
Connect to GND
Control signal for DAC
Control signal for DAC
Analog output 1

Power supply
Analog output 1

Connect to GND
Connect to GND

Analog output 2
Power supply

Analog output 2
Control signal for DAC
Connect to GND
No connect
No connect
VCO frequency
Power supply D+5V

Connect to GND
Connect to GND
Control signal for DAC

Clock for control signal

Function

1-61

MX-DVA9/MX-DVA9R

MR27V1602E2JMAX (IC402) : 16M ROM

1.Terminal layout

1

NC

2

A18

3

A17

A7

4

5

A6

6

A5

7

A4

8

A3

9

A2

A1

10

11

A0

12

CE

Vss

13

14

OE

D0

15

D8

16

D1

17

D9

18

D2

19

D10

20

21

D3

D11

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

NC

A19

A8

A9

A10

A11

A12

A13

A14

A15

A16

BYTE/Vpp

Vss

D15/A-1

D7

D14

D6

D13

D5

D12

D4

Vcc

2.Pin function

Pin No Symbol Function.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

/WE

A19
A18

A8
A7
A6
A5
A4
A3
A2
A1

CE

VSS

DE
D0
D8
D1
D9

D2

D10

D3

D11

I/O

O
O
O
O
O
O
O
O
O

Pin No Symbol Function.

23
I
I
I
I
I
I
I

I
I
I
I

-

Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Chip enable
Connect to GND
Output enable
Data output
Data output
Data output
Data output
Data output
Data output
Data output
Data output

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

VCC

D4

D12

D5

D13

D6

D14

D7

A0/D15

VSS

BYTE

A17
A16
A15
A14
A13
A12
A11
A10

A9

A20

WP

I/O

­O
O
O
O
O
O
O

I/O

-

I
I

I
I
I
I
I
I

I
I
I

Power supply
Data output
Data output
Data output
Data output
Data output
Data output
Data output
Data output/address input
Connect to GND
Mode switch
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input

1-62

BA15218 (IC511~IC516, IC531~IC536) : Operation amplifier

MX-DVA9/MX-DVA9R

1OUT1

2-IN1

3+IN1

+

4

2. Block diagram

Vcc

-IN

+IN

­1

2

Q5

Q1

Q3 Q4

R1

Q2

CC

8

V

OUT2

7

-IN2

6

-

+IN2

5GND

+

Q8

Q18Q13

Q19

Q11

Q9

R6

OTHER

CH

Q17Q16

D1

C2

R5

Q6

Q10

R7

R8

Q12

Q7

C1

R3R2

R4

VEE

BA3126N (IC301) : R/P Switch

S W

R E C

G

123456789

P / B

S W

C O N T .

G N D

V c c

P / B

S W

G

NAX0393-001 (IC502) : 27MHz Oscilator

1.Terminal layout

43

VDD D

NC GND

12

OUTPUT

S W

R E C

Q14 Q15Q114

R9

1-63

MX-DVA9/MX-DVA9R

BU2092BC (IC811) : PORT EXPANDER

1. Terminal Layout

Vss

1

2

DATA

LCK

Q0

Q1

Q2

Q3

Q4

3

4

5

6

7

8

9

CLOCK

CONTROL

CIRCUIT

12BIT SHIFT RESISTER

12BIT STRAGE RESISTER

OUTPUT BUFFER (OPEN DRAIN)

2.Pin function

Pin No. Symbol I/O Function

Vdd

18

17

OE

16

Q11

Q10

15

Q9

14

Q8

13

Q7

12

11

Q6

10

Q5

5~16

17
18

Vss

1

DATA

2

CLOCK

3

LCK

4

Q0~Q11

OE
Vdd

-

Connect to GND

I

Serial data input

I

Shift clock of data

I

Latch clock of data

O

Parallel data output

Latch data L H

OUT PUT ON OFF

I

Output enable
Power supply

-

BA3835S (IC812) : SPIIC

1.Terminal layout

BIASC

VREFC

RREF

N. C.

N. C.

DIFOUT

CIN

AIN

1

2

3

4

105Hz
BPF

5

A-C

6

C

DIF

7

A

8

340Hz
BPF

1kHz
BPF

3.4kHz
BPF

10.5kHz
BPF

B I A S

V R E F

REFFERENCE CURRENT

PEAK
HOLD

PEAK
HOLD

PEAK
HOLD

PEAK
HOLD

PEAK
HOLD

RES

RES

RES

RES

RES

MPX

2.Pin function

Pin No. Symbol I/O Function

I

BIASC

18

GND

AOUT

17

16

TEST

15

N. C.

N. C.

14

SEL

13

C

12

B

11

1

2

3

4
5
6
7
8

9
10
11
13
14
15
16
17
18

VREFC

RREF

NC
NC
DIFOUT
CIN
AIN
VCC
A
B
SEL
NC
NC
TEST
AOUT
GND

Connection for decoupplig
capacitor that from reference
voltage linar section

I

Connection for decoupplig
capacitor that from reference
voltage logic section

I

Connection for reference
resistor that from band pass
filter fo

Non connect

-

-

Non connect

O

Differntial amplifier output pin
Differntial amplifier input pin2

I

Differntial amplifier input pin1

I

-

Power supply

I

Output select control pin
Output select control pin

I

Output select control pin

I

-

Non connect
Non connect

­I

TEST signal input

O

MPX output pin
Connect to GND

-

VCC

9

1-64

DEC

A

10

BA3838F-X (IC560) : Stero A/D converter

1.Terminal layout
16 ~ 9

1 ~ 8

2.Block diagram

Pin No. Symbol I/O Function

10
11
12
13
14
15
16

VCC

1

MICIN

2

LOUT

3

FK

4

TK

5

LIN

6

BIAS

7

GND

8

RIN

9

­I

O

LPF1
LPF2
LPF3
ROUT

O

O
CTRLA
CTRLB
CTRLC

I
I

Power supply
Microphone mixing input
Channel L output

I

Accepts signal from the key controller

I

Output signal to the key controller

I

Channel L input

I

Signal bias

-

Connect to GND

I

Channel R input

I

Connects to LPF time constant element

I

Connects to LPF time constant element
LPF output
Channel R output

I

Mode select input A
Mode select input B
Mode select input C

MX-DVA9/MX-DVA9R

BU4094BCF (IC303) : Serial to parallel port extension

1.Terminal layout 2.Block diagram

Vdd

16

DATA

Q1
Q2
Q3
Q4

Vss

1

15

2
3
4
5
6
7
8

OUTPUT ENABLE

14

Q5

13

Q6

12

Q7

11

Q8

10

Q`s

9

Qs

DATA

CLOCK

STROBE

OUTPUT

2

3

1

15

ENABLE

Q1 Q8

PARALLEL OUTPUT

STROBE

CLOCK

8-STAGE

SHIFT REGISTER

8-BIT

LATHES

3-STATE

OUTPUTS

10

9

Q`s

Qs

SERIAL
OUTPUT

1-65

MX-DVA9/MX-DVA9R

MM3023DN-X (IC1, IC102) : Switching regulator

1.Terminal layout

GND

V

V

OUT

DD

1

2

3

CE

4

NC

5

1.Block diagram

V

DD

2

CE

10k

5

3.Pin function

Pin No. Symbol I/O Function

GND

1

VDD

2

VOUT

3

NC

4

CE

5

-

-

O

­I

Connect to GND
Power supply
Regulator output
No connect
Output voltage on/off control

BR93LC66F-X or AK93C65AF-X (IC403) : EEPROM

1.Terminal layout

1

NC

2

VCC

3

CS

4

SK

2.Block diagram

8

NC

7

GND

6

DO

5

DI

2.Pin Functions
Symbol

VCC

GND

CS
SK

DI

DO

I/O

-

­I
I
I

O

Power supply
Connect to GND
Chip select input
Serial clock input
Start bit,OP-code,address,serial data input
Serial data output,
Internal state display output of READY/BUSY

Vref

Current Limit

Function

3

VOUT

1

GND

DI

CS

SK

PE

INSTRUCTION

REGISTER

INSTRUCTION

DECODE,

CONTROL

AND

CLOCK

GENERATION

1-66

DATA

REGISTER

ADD.

BUFFERS

16

VREF

R/W AMPS

AND

AUTO ERASE

DECODER

VPP SW

GENERATOR

DO

16

EEPROM

4096bit

256 x 16

VPP

STK412-090 (IC701) : Operation amplifier

1.Terminal layout

STK412-000

MX-DVA9/MX-DVA9R

1

18

2.Block diagram

13 18 17

14

15

16

TR1 TR2

TR3

TR5

R2

R3

D2

TG6

R1

C1

C2

R4

TR4

R5

D1

TR3

TR8

TR10

R6

TR7

R7

12 9

TR19

TR20

81110

TR18

R13

TR16

R16

TR17

R17

STK402-040 (IC752) : Operation amplifier

TR41

R41

D12

TR12

TR11

C11

C12

R14

R15

TR14

R11

TR13

TR15

R12

D41

D51

TR51

Compartor

D42

D43

SUB

D53

D52

Compartor

R51

1

3

2

7

5

4

6

1.Terminal layout

STK402-050

115

2.Block diagram

ch. 1 ch. 2

ch. 1

ch. 1

NF

IN

123456789101112131415

Pre.

N.C. +Vcc

ch 1
+VE

ch 1

-VE -Vcc

BIAS +Vcc

ch. 2
+VE

Pre.

ch. 2

-VE -Vcc

SUB

SUB
GND

NF

ch. 2

ch. 2
IN

1-67

MX-DVA9/MX-DVA9R

TC7WH74FU-X (IC321) : Clock buffer

1.Terminal layout

(TOP VIEW)

CK

1

D

2

Q

3

GND

4

2.Block diagram

PR

(7)

CK

(1)

D

(2)

CLR

(6)

S
C
D
R

Vcc

8

PR

7

CLR

6

Q

5

(5)

(3)QQ

TC7W125FU-X (IC412) : Buffer

1. Terminal layout

2. Block diagram

G1

A1

Y2

GND

1

2

3

4

8

Vcc

7

C2

6

Y1

5

A2

STK402-230 (IC321) : Power amp

1. Terminal layout

STK402-230

119

2.Block daiagram

PRE+Vcc

PRE–Vcc

CH1IN

CH1NF

BIAS

–Vcc

GND

4

R1

TR4

R3

R4

R6

TR7

TR8

TR5

R5

TR6

R7

C1

TR1

TR2

1

2

TR3

D1

R2

12

5

9

13

SUB

7 6 10 14 15 16 17 19 1811

CH1–VE

CH1+VE

CH2+VE

TR9

TR10

CH2–VE

R8

TR12

TR13

R9

TR11

R10

R11

R12

C2

TR14

TR16

R14

R13 R20

TR15

TR23

CH2IN

CH3IN

CH2NF

TR24

CH3NF

C3

R18

TR22

R19

TR21

R17

R15

TR19

R16R21

TR17

TR18

TR20

8+Vcc

CH3–VE

CH3+VE

1-68

MX-DVA9/MX-DVA9R

TC7SH08FU-X (IC311) : Timing control

1.Terminal layout

IN B

IN A

GND

1

2

3

5

4

VCC

OUT Y

TC7SH32FU-X (IC312) :

1.Terminal layout

TC74VHC00FT-X (IC322,IC503) : Write timing control

1.Terminal layout / Block diagram

2 Input Single OR Gate

Vcc

54

1

A B GND

Y

23

Vcc 4B 4A 4Y 3B 3A 3Y

14 13

1

12

11 10 9 8

2

6

543

7

1A 1B 1Y 2A 2B 2Y GND

TC74VHC125FT-X (IC411) :

Buffer

1. Pin layout & block diagram 2. Truth table

1G 1

1A 2

1Y 3

2G 4

14 Vcc

13 4G

12 4A

11 4Y

INPUTS OUTPUTS

G

H

L

L

A

X

L

H

Y

Z

L

H

2A 5

2Y 6

GND 7

10 3G

9 3A

8 3Y

X: Don't care
Z:High impedance

1-69

MX-DVA9/MX-DVA9R

NJM78M09FA/NJM78M12FA (IC270/IC271) : Regulator

1.Terminal layout

1 2 3

1.INPUT

2.GND

3.OUTPUT

2.Block diagram

KIA7805API-T (IC330) : Regulator

1.

Terminal

layout

INPUT

OUTPUT

GND

1 2 3

1.VCC

2.GND

3.OUTPUT

KIA7042AP-T (IC830) : Regulator

1.

Terminal

layout

1 2 3

1.VCC

2.GND

3.OUT

Block diagram2.

1-70

BU9253AS(IC902) : LPF&ECHO MIX.

1.Pin layout & block diagram

1

GND

ECHO VR

BIAS

DAINT IN

2

3

4

5

OSC

COUNTER

18

17

16

15

14

MX-DVA9/MX-DVA9R

CR

MUTE

VCC

ADINT IN

DAINT OUT

DALPF IN

DALPF OUT

MIX OUT

2.Pin function

Pin No. Symbol

1
2

ECHO VR
3
4
5
6
7
8
9

10
11
12
13
14

DAINT IN

DAINT OUT

DALPF IN

DALPF OUT

MIX OUT

MIX IN

ADLPF IN

ADLPF OUT

ADINT OUT

ADINT IN
15
16
17
18

6

7

8

9

GND

BIAS

VCC

NC2

MUTE

CR

- +

D/A

MIX

SRAM

I/O

­I

-

­I

O

I
O
O

I

I
O
O

I

-

-

I

-

A/D

13

ADINT OUT

12

ADLPF OUT

- +
11

ADLPF IN

10

MIX IN

Descriptions

Connect GND
Echo level control
Non connect
Analog part DC bias
DA side integrator input
DA side integrator output
DA side LPF input
DAside LPF output
Mix AMP output for original tone& echo tone
Mix AMP input pin for original tone
AD side LPF input
AD side LPF output
AD side integrator output
AD side integrator input
Power supply
Non connect
Mute control signal input
CR pin for oscillator

1-71

MX-DVA9/MX-DVA9R

TA8409S(IC802,IC803):Motor driver

1.Pin layout 2.Pin function

1

IN2

VCC

OUT 2

GND
GND

VS

OUT 1

VR

IN1

2
3
4
5
6
7
8
9

TA8409S

INPUT OUTPUT MODE

IN1

0

1

0

1

GP1U271X(IC951):Receiver for remote controller

IN2

0

0

1

1

OUT1

H

L

L

OUT2

L

H

L

MOTOR

STOP

CW/CCW

CCW/CW

BRAKE

+

–

Amp.

Limiter Integrator Comparator

B.P.F

Demodulator

GND

VCC Vout

1-72

MX-DVA9/MX-DVA9R

VICTOR COMPANY OF JAPAN, LIMITED

AUDIO & COMUNICATION BUSINESS DIVISION
PERSONAL & MOBILE NETWORK BUSINESS UNIT. 10-1,1chome,Ohwatari-machi,Maebashi-city,371-8543,Japan

(No.21040)

200110(V)