JVC GZ-MC200EK, GZ-MC200EX, GZ-MC200EY, GZ-MC200EZ Schematics
SCHEMATIC DIAGRAMS
DIGITAL MEDIA CAMERA
YF061200411
GZ-MC200EK, GZ-MC200EX, GZ-MC200EY, GZ-MC200EZ
CD-ROM No.SML200412
GZ-MC200EK, GZ-MC200EX,
GZ-MC200EY, GZ-MC200EZ [M4S527]
COPYRIGHT © 2004 Victor Company of Japan, Limited
No.YF061SCH
2004/11
CHARTS AND DIAGRAMS
NOTES OF SCHEMATIC DIAGRAM
Safety precautions
The Components indentified by the symbol are
critical for safety. For continued safety, replace safety
critical components only with manufacturer's recommended parts.
1. Units of components on the schematic diagram
Unless otherwise specified.
1) All resistance values are in ohm. 1/6 W, 1/8 W (refer to
parts list).
Chip resistors are 1/16 W.
K: KΩ(1000Ω), M: MΩ (1000KΩ)
2) All capacitance values are in µF, (P: PF).
3) All inductance values are in µH, (m: mH).
4) All diodes are 1SS133, MA165 or 1N4148M (refer to parts
list).
Note: The Parts Number, value and rated voltage etc. in
the Schematic Diagram are for references only.
When replacing the parts, refer to the Parts List.
2. Indications of control voltage
AUX : Active at high.
AUX or AUX(L) : Active at low.
!
4. Voltage measurement
1) Regulator (DC/DC CONV) circuits
REC : Colour bar signal.
PB : Alignment tape (Colour bar).
— : Unmeasurable or unnecessary to measure.
2) Indication on schematic diagram
Voltage indications for REC and PB mode on the schematic diagram are as shown below.
REC mode
12 3
2.5
(5.0)
PB mode
1.8
PB and REC modes
(Voltage of PB and REC modes
are the same)
Note: If the voltages are not indicated on the schematic
diagram, refer to the voltage charts.
5. Signal path Symbols
The arrows indicate the signal path as follows.
NOTE : The arrow is DVC unique object.
Playback signal path
Playback and recording signal path
CIRCUIT BOARD NOTES
1. Foil and Component sides
1) Foil side (B side) :
Parts on the foil side seen from foil face (pattern face)
are indicated.
2) Component side (A side) :
Parts on the component side seen from component face
(parts face) indicated.
rts location are indicated by guide scale on the circuit board.
2. Parts location guides
Parts location are indicated by guide scale on the circuit board.
REF No.
IC101 B C 6 A
(A : Component side)
D : Discrete component)
B : Foil side
C : Chip component
Note: For general information in service manual, please
refer to the Service Manual of GENERAL INFORMATION Edition 4 No. 82054D (January 1994).
LOCATION
IC
Category : IC
Horizontal “A” zone
Vertical “6” zone
3. Interpreting Connector indications
1
2
Removable connector
3
1
2
Wire soldered directly on board
3
1
Non-removable Board connector
2
3
1
2
4
Board to Board
3
Connected pattern on board
The arrows indicate signal path
Note: For the destination of each signal and further line
connections that are cut off from the diagram,
refer to "BOARD INTERCONNECTIONS"
Recording signal path
(including E-E signal path)
Capstan servo path
Drum servo path
(Example)
R-Y
Playback R-Y signal path
Y
Recording Y signal path
6. Indication of the parts for adjustments
The parts for the adjustments are surrounded with the circle
as shown below.
7. Indication of the parts not mounted on the circuit board
“OPEN” is indicated by the parts not mounted on the circuit
board.
R216
OPEN
2-1 2-2
BOARD INTERCONNECTION
CN5201
CN5103
5
H1
HL
RG
OV3
TG_VD
MCLKI
ACHI0
REG_3.1V
P_GYAMP
TG_ID
ACHI1
G_RST
REG_12V
TG_HD
ACHI3
ACHI2
GND
TG_CS
CCD-7.5V
CAM_OUT
CAM_CLK
FLSH_RST
TG_FLD
(Page2-31)
ACHI5
ACHI6
ACHI7
ACHI4
OV4
(Page2-33)
ACHI8
ACHI11
ACHI10
ACHI9
REG-7.5V
REG_3.1V
REG_4.8V
GND
CCDOUT1
CCDOUT2
REG_4.8V
REG_3.1V
4
(Page2-27)
CN5102
3
CN101
OV2
ACHI12
H2
CPOB2
CPOB2
ACHI13
OV1
TG_VCC
TG_VCC
BCHI0
SUB
CPOB
CPOB
BCHI1
PBLK
PBLK
BCHI2
ADCLK
ADCLK
BCHI3
DS1a
DS1a
BCHI4
DS2a
DS2a
BCHI5
DS1b
DS1b
BCHI6
DS2b
DS2b
BCHI7
BCHI8
BCHI9
BCHI10
BCHI11
(Page2-43)
GND
BCHI12
BCHI13
CDS_STBY
(Page2-50)
POWER UNIT
YTU94074-11
YTU94077-11
YTU94128A-4
CN201
CN202
CN209
MAIN_IF(Page2-35)
CN5101
REG_3.1V
REG_4.8V
DRV_4.8V
GND
MIC/L
MIC/R
SPKSPK+
DRIVE-IS
HGout+IS
HGVss-IS
DRIVE+IS
HGVcc+IS
AIBD
AOBD
S_SHUT
AOMCLK
AIOLRCK
(Page2-21)
PD_L
BUZZER
HGout-IS
AIOBCK
A_MUTE
L_MUTE
Z_LED
ZOOM02
GATE_PLS
ISO200
AUD_CLK
AUEE_CTL
ZOOM04
ZOOM03
IR_OUT
AUD_DATA
AUDIO_CS
YTU94129A-33
YTU94109-33
F_VCC
ZOOM01
FOCUS02
FOCUSO3
ASPECT_S
FOCUS01
FOCUS04
CAM_OUT
AU_SIG/L
AU_SIG/R
HP_SIG/L
HP_SIG/R
M_AUD/L
M_AUD/R
AC_AUD/L
AC_AUD/R
REG_4.8V
REG_3.1V
HGout-ND
DRIVE-ND
HGVcc+ND
HDIRS
VDIRS
GND
DRIVE+ND
LENS_LED
CN204
HGout+ND
HGVss-ND
(Page2-25)
F/Z_CS
CAM_VD
TG_RST
CLK1MO
CLK4M5
ND_O/C
NDHAL_LV
M_AUD/L
M_AUD/R
AC_AUD/L
AC_AUD/R
CN203
CN102
NDPWM
CAM_CLK
IRIS_CS
CAM_IN
IRIS_PS
(Page2-19)
IR_OUT
REG_4.8V
REG_3.1V
AUDIN
CLK27A
AUDOUT
AUDSYNC
ACPLLOFF
AUDBITCLK
nAUDRESET
(Page2-15)
GND
AL_3.3V
REG_3.1V
GND
REG_3.1V
LCD_R
GND
LCD_G
LCD_B
VDCVF
LIT_3V
LCD_OPEN
LCD_RVS
HDCVF
VIF_CLK
VIF_OUT
BLKB
BLKA
VIOCOUT
VIOYSOUT
BLKC
OUTV2
VC0
VIF_IN
VC2
VC1
DV2OUT0
DV2OUT1
VC3
DOT_CLK
DV2OUT3
DV2OUT2
VCO
VC1
VC2
VC3
BLKA
BLKB
BLKC
OSD_HD
OSD_VD
DOT_CLK
OSD_VD
OSD_HD
DV2OUT4
DV2OUT5
YTU94074-10
YTU94077-10
(Page2-23)
DV2OUT7
DV2CKOUT
VI6
VI7
DV2OUT6
MPGHSYNC
MPGFLD
MPGVSYNC
LIT_3V
AL_3.3V
REG_DATA
REG_CLK
BATT_L
ADP_L
HP_DET
REG_CS
P_DET
VI5
VI4
REG_3.1V
VI3
VI2
VI1
GND
CHRG_LED
STIL_LED
VOIC_LED
REG_2.5V
VI0
VENC_RST
L_MUTE
AUD_CLK
AUDIO_CS
AUEE_CTL
(Page2-17)
MODE_SW
POFF_SW
PLAY_SW
REC_SW
VIDE_LED
BUZZER
AUD_DATA
PD_L
A_MUTE
DC_CHEK
V_BATT
LCD_RVS
T_BATT
I_MTR
CN205
LCD_OPEN
CF_SLOT
KEY_C
CHRG_EVR
ZOOM_SW
KEY_A
KEY_B
ACES_LED
CN207
MD_THRMO
DSP_RST
SCPU_SO
SCPU_CS
SCPU_SI
SCPU_SCK
FLSH_RST
SJIG_TX
SJIG_RX
SJIG_RST
YTU94074-12
YTU94077-12
CN305
CN308
CN307
CN309
CN304
ZOOM UNIT
YTU94074-6
YTU94077-6
CN9904
(Page2-50)(Page2-50)
REAR UNIT
LCD MODULE
YTU94074-24
YTU94077-24
REG_4.8V
Y_GYAMP
G_RST
ANA_IN_H
GND
Y_OUT
V_OUT
C_OUT
REG_3.1V
GND
CN7801
LCD_BLK
VBB
GND
(Page2-27)
HP_GND
BATT_L
REG_14V
MLT_GND
BATT_+
TT_BATT
ADP_DC
V_OUT
INFO
GOMI
CENTER
RIGHTUP
HALF_PSH
LEFTDOWN
REG_3.1V
ADP_L
(Page2-37)
HP_SIG/R
ANA_IN_H
Y_OUT
AU_SIG/L
C_OUT
HP_SIG/L
AU_SIG/R
TL1
LEFTUP
HP_DET
CN310
TL2
P_DET
VCOM
VIOYSOUT
VIOCOUT
ASPECT_S
PS_CTL
(Page2-49)
(Page2-39)
SJIG_RST
REG_DATA
REG_CS
REG_CLK
CN7802
CN306
GND
PWR_CHEK
(Page2-41)
CN301
CN206
SC
CSH
DSD
DSG
XDSG
LCD_BLK
(Page2-29)
VHVDD
XSTH
CKH2
CKH1
STH
CSV
REG-7.5V
REG_8.5V
DRV_4.8V
ENB
XENB
LCD_R
LCD_G
REG_12V
REG_1.2V
TT_BATT
DRV_3.3V
ADP_DC
AL_3.3V
STV
XSTV
LCD_B
REG_1.5V
BATT_+
BATT_L
ADP_L
CKV1
CKV2
VDCVF
HDCVF
CN303
CN208
LCD_BL
LCD_CS
VIF_CLK
VIF_OUT
MON_RPD
MON_B
MON_R
MON_G
CN302
REG_14V
CHRG_EVR
I_MTR
V_BATT
T_BATT
DC_CHEK
REG_3.1V
REG_4.8V
VPP
REG_3.1V
REG_8.5V
REG_4.8V
GND
(Page2-50)
CN9802
CN9902
CN103
CN106
2
Z_PTR_AD
F_PTR_AD
OP_THRMO
STRB_SNS
STRB_AD
STRB_CHG
VDIRS
HDIRS
LENS_LED
F/Z_CS
CAM_VD
CLK1M0
CLK4M5
TG_RST
NDHAL_LV
ND_D/C
IRIS_PS
IRIS_CS
CAM_IN
Y_GYAMP
SCPU_CS
SCPU_SCK
SCPU_SI
SCPU_SO
S_SHUT
VENC_RST
VENC_CS
PS_CTL
VIF_CLK
VIF_OUT
VIF_IN
S2_DET
OUTV2
LCD_BL
LCD_CS
PMA1
PMA2
CAM_CLK
PMA3
PMA4
G_RST
CAM_OUT
PMA6
PMA5
PMA7
PMA8
MCLKI
P_GYAMP
PMA9
TG_CS
PMA10
TG_HD
PMA11
TG_ID
ACHI1
ACHI0
TG_VD
(Page2-13)
PMD3
PMD2
PMD0
PMD1
ACHI2
PMD4
ACHI3
PMD5
ACHI4
PMD6
PMD7
ACHI5
PMD8
ACHI6
PMD9
ACHI7
ACHI8
PMD10
ACHI9
PMD11
ACHI10
PMD12
ACHI11
PMD13
ACHI12
PMD14
ACHI13
PMD15
BCHI0
nPMWE
BCHI1
nPMDE
BCHI2
BCHI3
BCHI4
BCHI5
nCREQ
BCHI6
BCHI7
nCACK
BCHI8
CLK27B
BCHI9
BCHI10
S_IN_L
ANA_IN_H
BCHI13
BCHI12
BCHI11
REG_3.1V
REG_1.5V
PPRD0
PPRD1
PPRD2
PPRD3
PPRD4
PPRD5
PPRD6
PPRD7
PPRD8
PPRD9
PPRD10
PPRD11
VLD_PIX
VCLK
SSGFLD
DMACLR
DMABREQ
DMASREQ
nPMBLS1
nPMBLSO
nPMCS1
PMINT
FLDCPU
VDCPU
ID_LAT
AFE_RST
CLK27A
CDS_STBY
GND
SOF
PMA0
nPMWAIT
1
CN105
FLSH_RST PMA12
REG_3.1V
GND
SDR_DQ31
SDR_DQ30
SDR_DQ29
SDR_DQ28
SDR_DQ27
SDR_DQ26
SDR_DQ25
SDR_DQ27
SDR_DQ31
SDR_DQ26
SDR_DQ25
SDR_DQ30
SDR_DQ28
SDR_DQ29
TG_FLD
STRB_EVR
PPRD0
PPRD1
PPRD2
PPRD3
PPRD4
PPRD5
PPRD6
PPRD7
PPRD8
PPRD9
PPRD10
PPRD11
VLD_PIX
SOF
VCLK
SSGFLD
DMACLR
DMABREQ
DMASREQ
nPMBLS1
nPMBLS0
nPMCS1
PMINT
FLDCPU
VDCPU
ID_LAT
AFE_RST
CLK27A
DV2CKOUT
SDR_DQ24
SDR_DQ23
SDR_DQ22
SDR_DQ24
SDR_DQ22
SDR_DQ23
SDR_DQ21
SDR_DQ20
SDR_DQ19
SDR_DQ19
SDR_DQ20
SDR_DQ21
(Page2-11)
SDR_DQ15
SDR_DQ18
SDR_DQ17
SDR_DQ16
SDR_DQ14
SDR_DQ13
SDR_DQ18
SDR_DQ16
SDR_DQ15
SDR_DQ14
SDR_DQ17
SDR_DQ13
CFD3
CFD4
CFD11
nCFCD1
SDR_DQ12
SDR_DQ11
SDR_DQ11
SDR_DQ12
CFD5
CFD12
SDR_DQ10
SDR_DQ9
SDR_DQ8
SDR_DQ9
SDR_DQ8
SDR_DQ10
CFD6
CFD14
CFD13
SDR_DQ7
SDR_DQ6
SDR_DQ7
SDR_DQ6
CFD7
CFD15
SDR_DQ5
SDR_DQ4
SDR_DQ4
SDR_DQ5
nCFCE1
nCFCE0
SDR_DQ3
SDR_DQ2
SDR_DQ2
SDR_DQ3
CFA10
nCFOE
SDR_DQ1
SDR_DQ0
SDR_DQ1
SDR_DQ0
CFA9
nCFIORD
SDR_DQM2
SDR_DQM3
SDR_DQM3
SDR_DQM2
CFA8
nCFWE
nCFIOWR
SDR_DQM1
SDR_DQM0
SDR_WE
SDR_WE
SDR_DQM0
SDR_DQM1
CFA7
CFRDY
SDR_CAS
SDR_RAS
SDR_CAS
SDR_RAS
CFA6
CFCSEL
SDR_CSO
SDR_BA1
SDR_BA1
SDR_CSO
CFA5
CFA4
SDR_BA0
SDR_CKE
SDR_CKE
SDR_BAO
CFRESET
CFA3
SDR_CLK
SDR_CLK
nCFWAIT
SDR_A10
SDR_A9
SDR_A8
SDR_A7
SDR_A6
SDR_A5
SDR_A9
SDR_A8
SDR_A5
SDR_A6
SDR_A7
SDR_A10
(Page2-9)
nCFREG
CFD0
CFA0
CFBVD2
CFA2
CFA1
SDR_A4
SDR_A4
CFD1
CFBVD1
SDR_A3
SDR_A2
SDR_A3
SDR_A2
CFD8
SDR_A1
SDR_A1
CFD2
SDR_A0
SDR_A0
CFD9
SDR_A11
SDR_A11
CFWP
CFD10
SDR_A12
nPMCS7
nPMCS7
SDR_A12
nCFCD2
PMA16
PMA16
PMA17
PMA17
SDCMD
SDDAT3
PMA18
PMA18
PMA19
PMA19
SDCLK
PMA20
PMA20
SDDAT1
SDDAT0
PMA21
PMA21
SDCD
SDDAT2
PMA1
PMA1
SDWP
PMA2
PMA2
PMA3
PMA3
PMA4
PMA4
PMA5
PMA5
PMA6
PMA7
PMA7
PMA6
nPMWAIT
PMA0
PMA8
PMA8
PMA9
PMA9
PMA10
PMA10
PMA11
PMA11
PMD0
PMD0
PMD1
PMD1
ARMTDO
PMA2
PMD2
ARMTCK
PMD3
PMD3
ARMTMS
PMD4
PMD4
ARMTDI
PMD5
PMD6
PMD6
PMD5
nARMTRST
nJRESET
PMD7
PMD7
PMD8
PMD8
NU_RX
PMD9
PMD9
NU_TX
PMD10
PMD10
MOD0
PMD11
PMD11
PMD12
PMD12
REG_2.5V
PMD14
PMD13
PMD13
PMD14
PMA13
PMA14
PMA15
PMD15
PMD15
nPMWE
nPMWE
nPMOE
PMA15
nPMOE
DV1CLKIN
MPEG_RST
PLLSTOP
DV2OUT7
DV2OUT6
DV2OUT5
DV2OUT4
DV2OUT3
DV2OUT2
DV2OUT1
DV2OUT0
ACPLLOFF
AUDSYNC
AUDBITCLK
nAUDRESET
PWR_CHEK
DSP_RST
nUSBDP_PU
nUSB_DET
REG_2.5V
REG_3.1V
REG_1.2V
REG_4.8V
PMA14
DV1IN0
DV1IN1
DV1IN2
DV1IN3
DV1IN4
DV1IN5
DV1IN6
DV1INH
DV1INV
nCINT
nVOEN
nPMCS0
DV1IN7
AUDOUT
AUDIN
NDPWM
USBDP
USBDN
PMA13
GND
PMA12
PMD15
REG_1.5V
REG_2.5V
REG_3.1V
GND
PMA0
nPMWAIT
PMD14
MPGFLD
PMD13
nUSBDP_PU
nUSB_DET
USBDP
USBDN
S_PDIF
PMD10
PMD11
PMD12
VI0
MPGVSYNC
MPGHSYNC
PMD9
VI1
PMD7
PMD8
VI3
VI2
(Page2-5)
PMD6
PMD5
PMD4
PMD3
VI5
VI6
VI4
VI7
GND
PMA9
PMD0
PMD1
PMD2
PMA11
PMA10
(Page2-7)
AIOLRCK
AIBD
AOMCLK
AOBD
AIOBCK
REG_3.1V
PMA8
PMA7
DRV_3.3V
ANA_IN_H
S_IN_L
PMA6
PMA4
PMA5
PMA3
PMA1
PMA2
DV2CKOUT
nPMWE
nPMOE
CLK27B
nCREQ
PMA15
nCACK
PMA14
PMA12
PMA13
DV1IN0
DV1IN1
DV1IN2
DV1IN3
DV1IN4
DV1IN5
DV1IN6
DV1IN7
DV1INH
DV1INV
DV1CLKIN
nCINT
nVOEN
nPMCSO
MPEG_RST
PLLSTOP
S_PDIF
CN104
CN9803
CN9801
(Page2-47)
CN9903
CN9901
(Page2-45)
NOTE: The number of patch cords () are indicated by interconnected.
A
BCDEFG
y10480001a_rev0
2-3 2-4
DIGITAL(DIGI IF) SCHEMATIC DIAGRAM
TO CDS(CN5102)
CN101
QGF0309F1-51W
CN104
5
4
3
QGF0309F1-51W
TO CF SUB
(CN9803)
J101
QNZ0497-001
R657
0Ω
Q202
2SA2029/QRS/-X
TL103
47k
47k
R655
R656
L201L201
L201
L201
NQR0536-001X
R204
6.8k
47k
R644
47k
R645
R203
47K
47k
R646
47k
R647
R202
47k
R648
47k
R649
47k
R650
47k
R653
47k
R654
R201
47K
Q201
DTC144EM-X
C602
0.1
TO USB
2
CN106
NNZ0058-001X
TO SD CARD
R408
R409
C402
R412
R413
R405
R403
22k
22k
R404
22k
R402
22k
R401
22k
C401
/6.3
10
T
D401
RSA6.1J4-W
R406
22k
R407
22k
22
22
0.1
22
22
REG_3.1V
nUSBDP_PU
nUSB_DET
GND
USBDP
USBDN
D402
RSA6.1J4-W
MD_THRMO
nCFCD1
CFD3
CFD11
CFD4
CFD12
CFD5
CFD13
CFD6
CFD14
CFD7
CFD15
nCFCE0
nCFCE1
CFA10
nCFOE
nCFIORD
CFA9
nCFIOWR
CFA8
nCFWE
CFA7
CFRDY
CFA6
CFCSEL
CFA5
CFA4
CFRESET
CFA3
nCFWAIT
CFA2
CFA1
nCFREG
CFA0
CFBVD2
CFD0
CFBVD1
CFD1
CFD8
CFD2
CFD9
CFWP
CFD10
GND
nCFCD2
L401
NQR0129-002X
TO NUCORE
TO NUCORE
REG_3.1V
SDDAT2
SDDAT3
SDCMD
GND
SDCLK
SDDAT0
SDDAT1
SDCD
SDWP
TO NUCORE
TG_ID
MCLKI
TG_CS
CAM_CLK
TO P.PRCS
TG_VD
CAM_OUT
TG_HD
TG_FLD
FLSH_RST
TO NUCORE
TO MEMORY
ARMTDO
0Ω
R702
ACHI0
ACHI1
ARMTCK
ARMTMS
ACHI2
ACHI3
ACHI4
ACHI5
TO NUCORE
REG_3.1V
nARMTRST
nJRESET
ARMTDI
0Ω
R703
ACHI6
TO P.PRCS
NU_RX
ACHI7
NU_TX
0Ω
R704
ACHI8
AL_3.3V
ACHI9
ACHI10
ACHI11
TO NUCORE
TO CN102
MOD0
SJIG_TX
SJIG_RX
ACHI12
ACHI13
REG_3.1V
TO CN102
VPP
GND
SJIG_RST
REG_4.8V
REG_3.1V
VCOM
MON_B
BCHI0
BCHI1
REG_4.8V
TL101
TL102
TL104
TO CN102
MON_R
MON_G
GND
BCHI2
BCHI3
MON_RPD
BCHI4
BCHI5
BCHI6
BCHI7
TO P.PRCS
S_PDIF
ANA_IN_H
S_IN_L
BCHI8
BCHI9
BCHI10
BCHI11
TO MEMORY
TO P.PRCS
BCHI12
BCHI13
CDS_STBY
GND
G_RST
P_GYAMP
TO P.PRCS
DIGITAL(DIGI IF
10
TO REG(CN308)
CN103
QGA1002F1-07X
GND
REG_3.1V
REG_1.5V
REG_1.5V
REG_1.2V
GND
REG_3.1V
TO P.PRCS, LCD DRV, V I/O
TO P.PRCS, NUCORE, MPEG2, AC97
TO P.PRCS,OP DRV,MDA,V I/O
)
TO JIG, SUB CPU
TO NUCORE, SUB CPU
TO P.PRCS, LCD DRV
TO NUCORE, V I/O
TO NUCORE, MPEG2, V I/O
TO NUCORE, AC97
TO MPEG2, AUDIO
TO P.PRCS, AUDIO
TO MEMORY, SUB CPU
TO P.PRCS, SUB CPU
TO P.PRCS, GYRO
TO NUCORE, OP DRV
TO P.PRCS, OP DRV
TO NUCORE
P.PRCS
STROBE
TO CN104
TO JIG
LCD DRV
SJIG_RST
SJIG_RX
SJIG_TX
DSP_RST
PWR_CHEK
LCD_BL
LCD_CS
OUTV2
S2_DET
VIF_OUT
VIF_IN
VIF_CLK
PS_CTL
REG_2.5V
VENC_CS
DV2OUT0
DV2OUT1
DV2OUT2
DV2OUT3
DV2OUT4
DV2OUT5
DV2OUT6
DV2OUT7
MPGFLD
DV2CKOUT
MPGHSYNC
MPGVSYNC
CLK27A
VENC_RST
ACPLLOFF
AUDIN
AUDOUT
AUDSYNC
AUDBITCLK
nAUDRESET
AIBD
AOBD
AIOLRCK
AOMCLK
AIOBCK
S_SHUT
FLSH_RST
SCPU_CS
SCPU_SCK
SCPU_SI
SCPU_SO
G_RST
Y_GYAMP
NDPWM
NDHAL_LV
ND_O/C
CAM_IN
IRIS_CS
IRIS_PS
CLK1M0
VDIRS
HDIRS
Z_PTR_AD
F_PTR_AD
OP_THRMO
F/Z_CS
LENS_LED
CLK4M5
CAM_VD
CAM_CLK
CAM_OUT
TG_RST
STRB_CHG
STRB_EVR
STRB_AD
STRB_SNS
AL_3.3V
MD_THRMO
REG_4.8V
MON_G
MON_R
MON_B
MON_RPD
VCOM
CN102
GND
VPP
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
GND
QGB0402K2-B0X
TO ANALOG
(CN203)
1
CN105
QGB0512L1-30X
TO JIG CONNECTOR
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
A
BCD EFG
2-5 2-6
y10481001a_rev0
DIGITAL(MPEG2) SCHEMATIC DIAGRAM
R3043
VO0
VO1
VO2
VO3
VO4
VO5
VO6
VO7
VOCLK
nVOEN
VOHSYNC
VOVSYNC
0
IC3002
R3048
C3018
R3045
R3044
100
TO P.PRCS
TO NUCORE
CLK27B
MPEG_RST
PLLSTOP
5
REG_1.5V
REG_2.5V
TO REG
REG_3.1V
4
TO CN102
3
TO NUCORE
MPGFLD
MPGHSYNC
MPGVSYNC
DV2CKOUT
DV1IN0
DV1IN1
DV1IN2
DV1IN3
DV1IN4
DV1IN5
DV1IN6
DV1IN7
DV1CLKIN
nVOEN
DV1INH
DV1INV
GND
MPGFLD
MPGHSYNC
MPGVSYNC
VI0
VI0
VI1
VI1
VI2
VI2
VI3
VI3
VI4
VI4
VI5
VI5
VI6
VI6
VI7
VI7
#
R3049
#
R3050
#
R3051
#
R3052
#
R3053
#
R3054
#
R3055
#
R3056
#
R3057
R3058
R3059
2
L3001
NQR0129-002X
L3002
NQR0129-002X
L3006
L3003
NQR0129-002X
L3004
NQR0129-002X
C3001
C3003
T
C3004
T
L3005
NQR0006-001X
0
nCINT
nCACK
nCREQ
nPMWAIT
nPMOE
nPMWE
nPMCS0
PMD15
PMD14
PMD13
PMD12
PMD11
PMD10
PMD9
PMD8
PMD7
PMD6
PMD5
PMD4
PMD3
PMD2
PMD1
PMD0
PMA15
PMA14
PMA13
PMA12
PMA11
PMA10
PMA9
PMA8
PMA7
PMA6
PMA5
PMA4
PMA3
PMA2
PMA1
PMA0
TO NUCORE
TO P.PRCS
TO NUCORE, P.PRCS
TO NUCORE,
MEMORY, P.PRCS
TO NUCORE
TO
NUCORE
MEMORY
P.PRCS
TO
NUCORE
P.PRCS
TO
NUCORE
MEMORY
P.PRCS
TO NUCORE, P.PRCS
R3024
4.7k
47k
R3037
R3036
NDI/JTDI
NDO/JTDO
nNRST/nJTRST
SISYNC
SIVLD
SICLK/SISTB
OPEN
R3042
4.7k 4.7k
R3035 R3034
NMOD/JTMS
NCLK/JTCLK
SI0
SI1
R3033 R3041
JMOD
SI2
OPEN
4.7k
10k
10k
10k
R3032
R3031
R3029
R3030
PWM
nGNT
nREQ
nPME
IDSEL
SI7
nCLKRUN
nSOREQ
SOCLK/SOSTB
SOSYNC
SOVLD/SORDY
nCBE3
SO0
PSTOP
SI3
STCLK
PCICLK
SI4
SI5
SI6
10k
nCBE2
SO1
R3028
10k
nCBE1
SO2
R3027
10k
nCBE0
SO3
10k
R3026
nRESET
SO4
10k
10k
R3020
R3021
CB16
nCINT
nCACK1
SO5
SO6
SO7
10k
R3014
R3022
nCACK0
nCREQ1
nSOEN
MA0
R3023
nCREQ0
MA1
nCWAIT
MA2
nCRE
MA3
nCWE
MA4
4.7k
R3025
nCCS
MA5
CD15
MA6
CD14
MA7
CD13
MA8
CD12
MA9
CD11
MA10
CA15
CA14
CA13
CA12
CA11
CA10
HMODE2
HMODE1
HMODE0
MDQM
nMWE
nMCAS
nMRAS
nMCS
MCLKE
MCLK
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MA13
MA12
MA11 CD10
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
CA9
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
R3015
22
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
C3017
C3016
C3015
C3014
C3013
C3012
VDD1
VO5
C3011
0.1
0.1
0.1
10k
10k
4.7k
R3039
GPIO5
AIOBCK
GPIO4
AIOBD
GPIO0
GPIO1
GPIO2
GPIO3
IC3001
UPD61152F1-A03
ATX
AIMCLK
AOMCLK
SIREQ
R3008
0
R3038
R3040
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD1
VO6
VO7
VOCLK
nVOEN
VOHSYNC
VOVSYNC
AILRCK
AIBCK
AIBD
AIOLRCK
0
0
R3012
VOCLK
nVOEN
VOHSYNC
VOVSYNC
10k
R3003
R3004
R3013
10k
VO6
VO7
0.1
0.1
0.1
0.1
C3002
T
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PVDD
PVDD
PGND
PGND
CSCLK
CSDI
CSDO
VDD1
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
VIHSYNC
VIVSYNC
VICLK
VO0
VO1
VO2
VO3
VIFLD/VIVLD
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
MPGHSYNC
MPGVSYNC
MPGFLD
VO4
VO0
VO1
VO2
VO3
VO4
VO5
0.1
C3006
0.1
C3007
T
0.1
C3008
0.1
C3009
C3005
C3010
0.1
T
10
/6.3
R3001
10k
R3002
10k
C3019
MDQM
nMWE
nMCAS
nMRAS
nMCS
MMCLKE
MMCLK
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MA13
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
C3312
0.1
TL3301
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MDQM
TL3302
nMWE
TL3303
nMCAS
TL3304
nMRAS
TL3305
nMCS
TL3306
MA13
MA12
TL3307
MA10
TL3308
MA0
MA1
MA2
C3318
0.1
T
MA3
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23 MD24
MDQM
C3321
0.1
C3311
10
/6.3
R3016
R3017
R3018
R3019
IC3301
K4S283233F-HN75
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQM0
WE_
CAS_
RAS_
CS_
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD VSS
VDD
DQ16
VDDQ
DQ17
DQ18
VSSQ
DQ19
DQ20
VDDQ
DQ21
DQ22
VSSQ
DQ23
VDDQ
DQM2
NC
NC
VDDQ
IC3301
0Ω
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
VDDQ
DQM1
DQ31
VSSQ
DQ30
DQ29
VDDQ
DQ28
DQ27
VSSQ
DQ26
DQ25
VDDQ
DQ24
VSSQ
DQM3
VSSQ
2.2k
VSS
MD15
MD14
MD13
MD12
MD11
MD10
MD9
DQ9
DQ8
VSS
NC
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
NC
NC
MD8
MDQM
MMCLKE
MA11
MA9
MA8
MA7
MA6
MA5
MA4
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MDQM
R3301
0
C3316
0.1
C3322
0.1
MMCLK
R3009
R3010
R3011
10k
10k
10k
AIBD
AIOLRCK
TO CN105
AIOBCK
(TL101)
AOBD
AOMCLK
S_PDIF
1
TO DIGI IF
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
A
BCDEFG
2-7 2-8
# EXCHANGE PARTS LIST
R3012
GZ-MC200**
GZ-MC100**
0
1000100
R3013 R3048 R3049 R3050 R3051 R3052 R3053 R3054 R3055 R3056 R3057
0
100
0
10001000100010001000100010001000100
L3302
L3301
NQR0129-002X
DIGITAL(MPEG2
10
)
y10483001a_rev0
DIGITAL(NUCORE) SCHEMATIC DIAGRAM
VCLK
VLD_PIX
AFECLK
AFEVPIX
3CCDCLK
SCANE
TESTSCAN
TRACESYNC
47k
R4010
R4008
nJRESET
TO CN105
PPRO10
PPRO11
AFED10
AFED11
TRACECLK
DBGRQ
OPEN
TO P.PRCS
PPRO8
PPRO9
AFED8
AFED9
DBQACK
PMA0
TL4002
PMA0
P.PRCS
TO MPEG2
PPRO7
AFED7
PMA1
PMA1
PPRO6
AFED6
PMA2
PMA2
PPRO5
AFED5
PMA3
PMA3
PPRO3
PPRO4
AFED3
AFED4
PMA4
PMA5
PMA4
PMA5
TO MPEG2
PPRO0
PPRO1
PPRO2
AFED0
AFED1
AFED2
PMA6
PMA7
PMA8
PMA6
PMA7
PMA8
P.PRCS
MEMORY
SDR_CKE
SDR_DQ31
MCKE
PMA9
PMA9
SDR_DQ31
SDR_DQ29
SDR_DQ30
SDRAM_D30
SDRAM_D31
PMA10
PMA11
PMA10
PMA11
SDR_DQ29
SDR_DQ30
SDR_DQ31
SDR_DQ30
SDR_DQ29
SDR_DQ27
SDR_DQ28
SDRAM_D27
SDRAM_D28
SDRAM_D29
PMA12
PMA13
PMA14
PMA12
PMA13
PMA14
MEMORY
TO MPEG2
SDR_DQ27
SDR_DQ28
SDR_DQ28
SDR_DQ27
SDR_DQ25
SDR_DQ26
SDRAM_D25
SDRAM_D26
PMA15
PMA16
PMA15
PMA16
SDR_DQ25
SDR_DQ26
SDR_DQ26
SDR_DQ25
SDR_DQ23
SDR_DQ24
SDRAM_D23
SDRAM_D24
PMA17
PMA18
PMA17
PMA18
SDR_DQ22
SDR_DQ23
SDR_DQ24
SDR_DQ24
SDR_DQ23
SDR_DQ22
SDR_DQ21
SDR_DQ19
SDR_DQ20
SDR_DQ21
SDR_DQ22
SDRAM_D20
SDRAM_D21
SDRAM_D22
PMA19
PMA20
PMA21
TL4003
PMA21
PMA20
PMA19
TO MEMORY
SDR_DQ19
SDR_DQ20
SDR_DQ21
SDR_DQ20
SDR_DQ19
SDR_DQ17
SDR_DQ18
SDRAM_D17
SDRAM_D18
SDRAM_D19
PMD0
PMD1
PMD2
PMD2
PMD1
PMD0
SDR_DQ17
SDR_DQ18
SDR_DQ18
SDR_DQ17
SDR_DQ15
SDR_DQ16
SDRAM_D15
SDRAM_D16
PMD3
PMD4
PMD4
PMD3
SDR_DQ16
SDR_DQ16
SDR_DQ15
SDR_DQ13
SDR_DQ14
SDRAM_D14
PMD5
PMD5
SDR_DQ13
SDR_DQ14
SDR_DQ15
SDR_DQ14
SDR_DQ13
SDR_DQ11
SDR_DQ12
SDRAM_D11
SDRAM_D12
SDRAM_D13
PMD6
PMD7
PMD8
PMD8
PMD7
PMD6
P.PRCS
MEMORY
TO MPEG2
SDR_DQ11
SDR_DQ12
SDR_DQ12
SDR_DQ11
SDR_DQ9
SDR_DQ10
SDRAM_D9
SDRAM_D10
PMD9
PMD10
PMD9
PMD10
SDR_DQ10
SDR_DQ10
SDR_DQ8
SDRAM_D8
PMD11
PMD11
TO P.PRCS
TO MPEG2
TO CN105
nCINT
MOD0
VDCPU
PMINT
SOF
ID_LAT
5
R4081
47k
10k
0603
R4058
R4061
47k
0Ω
PLLSTOP
SSGFLD
nCFWE
nCFWAIT
CFRESET
nCFREG
CFRDY
nCFOE
nCFIOWR
nCFIORD
CFCSEL
CFD10
CFD11
CFD12
CFD13
CFD14
CFD15
nCFCE0
nCFCE1
nCFCD1
nCFCD2
CFBVD1
CFBVD2
CFA10
NDPWM
CLK27A
CFWP
CFD0
CFD1
CFD2
CFD3
CFD4
CFD5
CFD6
CFD7
CFD8
CFD9
CFA0
CFA1
CFA2
CFA3
CFA4
CFA5
CFA6
CFA7
CFA8
CFA9
R4062
R4063
R4064
R4065
R4066
R4101
R4102
R4103
R4104
R4105
R4106
R4107
RA4007
RA4008
RA4009
RA4010
R4110
R4111
R4112
RA4011
RA4012
RA4013
GPIO7
0Ω
GPIO26
0Ω
GPIO28
0Ω
GPIO25
GPIO27
0Ω
GPIO29
0Ω
CFWP
0Ω
nCFWE
0Ω
nCFWAIT
0Ω
CFRESET
0Ω
nCFREG
0Ω
CFRDY
0Ω
nCFOE
nCFIOWR
nCFIORD
CFCSEL
0Ω
CFD0
CFD1
CFD2
CFD3
0Ω
CFD4
CFD5
CFD6
CFD7
0Ω
CFD8
CFD9
CFD10
CFD11
0Ω
CFD12
CFD13
CFD14
CFD15
0Ω
nCFCE0
0Ω
nCFCE1
nCFCD1
0Ω
nCFCD2
CFBVD1
CFBVD2
0Ω
CFA0
CFA1
CFA2
CFA3
0Ω
CFA4
CFA5
CFA6
CFA7
0Ω
CFA8
CFA9
CFA10
PWM0
PWM1
TL4015
PWM2
TL4016
PWM3
TL4017
GPIO31
R4068
NC3
47k
NC4
GPIO39
R4001 D4001
0Ω
TO CN102
TO MPEG2
TO P.PRCS
TO MPEG2
PWR_CHEK
MPEG_RST
4
TO CN104
3
TO CN102
2
TO CN102
TO CN102
STRB_EVR
ACPLLOFF
P.PRCS
1
GPIO3
GPIO5
GPIO4
MCLKINNCAMBACLKIN
3.3k
R4005
GPIO6
GPIO2
nRESET
nRESETPERH
TL4001
DSP_RST
TO CN102
TO P.PRCS
AFESOF
47k
R4009
0Ω
R4006
AFE_RST
SDR_DQ9
SDR_DQ9
SDR_DQ8
SDR_DQ6
SDR_DQ7
SDRAM_D7
PMD12
PMD12
SDR_DQ7
SDR_DQ8
SDR_DQ7
SDR_DQ6
SDR_DQ4
SDR_DQ5
SDRAM_D5
SDRAM_D6
PMD13
PMD14
PMD14
PMD13
TO MEMORY
SDR_DQ4
SDR_DQ5
SDR_DQ6
SDR_DQ5
SDR_DQ4
SDR_DQ2
SDR_DQ3
SDRAM_D2
SDRAM_D3
SDRAM_D4
nPMCS7
nPMCS1
PMD15
R4012
R4011
PMD15
nPMCS1
nPMCS7
TO P.PRCS
TO MEMORY
SDR_DQ2
SDR_DQ3
SDR_DQ3
SDR_DQ2
SDR_DQ1
SDR_DQ0
SDR_DQ1
SDR_DQM3
SDRAM_D0
SDRAM_D1
nPMCS0
nPMWE
R4015
R4014
R4013
nPMWE
nPMCS0
TO MPEG2
TO MPEG2
SDR_DQ0
SDR_DQ1
SDR_DQM3
SDR_DQ0
SDR_DQM1
SDR_DQM2
DQM2
DQM3
nPMOE
nPMBLS0
R4017
R4016
nPMOE
nPMBLS0
P.PRCS
MEMORY
TO P.PRCS
SDR_DQM2
SDR_DQM3
SDR_DQM2
SDR_DQM1
SDR_WE
SDR_DQM0
DQM0
DQM1
nPMBLS1
nPMWAIT
R4018
nPMBLS1
nPMWAIT
P.PRCS
TO MPEG2
SDR_DQM0
SDR_DQM1
SDR_DQM0
SDR_WE
SDR_RAS
SDR_CAS
nCAS
nMWE
nARMTRST
TCK
0Ω0Ω0Ω0Ω0Ω0Ω0Ω0Ω0Ω
R4019
ARMTCK
nARMTRST
SDR_CAS
SDR_WE
SDR_CAS
SDR_RAS
SDR_CS0
SDR_BA1
nRAS
nMCS0
TMS
TDI
47k6847k
R4020
ARMTDI
ARMTMS
TO CN105
SDR_CS0
SDR_RAS
SDR_CS0
SDR_BA1
SDR_BA0
33
R4056
SDRAMBS0
SDRAMBS1
AMBATDO
SIO0
TL4026
R4021
R4069
1k
R4007
10k
ARMTDO
SDR_CKE
SDR_BA0
SDR_BA1
SDR_BA0
SDR_CKE
SDR_CLK
SDR_A12
R4055
SDRAMCLK
SDRAM_A12
SDRAMCLKR
SIO1
TL4027
47k
R4022
SDR_CLK
SDR_CLK
SDR_A10
SDR_A10
SDR_A11
SDRAM_A11
GPIO24
0Ω
R4023
nVOEN
TO MPEG2
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
A
BCD EFG
SDR_A11
SDR_A10
SDR_A9
SDR_A9
SDR_A8
SDR_A8
SDR_A9
SDRAM_A9
SDRAM_A10
DMASREQ
DMABREQ
0Ω
R4024
DMABREQ
DMASREQ
SDR_A8
SDR_A7
SDR_A7
SDR_A6
SDRAM_A8
DMACLR
L4010
NQR006-001X
47k
R4025
L4007
DMACLR
SDR_A6
SDR_A5
SDR_A4
SDR_A5
SDR_A4
L4011
T
/6.3
C4045
10
R4029
NQR0006-001X
SDR_A3
SDR_A2
SDR_A1
SDR_A3
SDR_A2
SDR_A1
SDR_A7
SDRAM_A7
SIP1280ISD-DVA2
0Ω
X4001
NAX0710-001X
C4043
SDR_A0
SDR_A0
SDR_A6
SDRAM_A6
IC4001
USBPHYCLK
0Ω
R4028
0.1
SDR_A12
SDR_A11
SDR_A4
SDR_A5
SDRAM_A5
USBVSS
SDR_A12
SDR_A2
SDR_A3
SDRAM_A4
SDRAM_A3
USBVSS
USBVDD
0.1
C4042
R4030
0Ω
SDR_A0
SDR_A1
SDRAM_A1
SDRAM_A2
USBVSS
USBVDD
0.1
6.8k
C4041
R4031
TO P.PRCS
2-9 2-10
22
R4054
SDRAM_A0
USB4XCLK
USBREXT
6.8k
R4032
SDCLK
SD_CLK
USBDp
USBDP
SDWP
SDCD
SD_CD
SD_WP
USBDn
USBVDD
C4040
USBDN
nUSB_DET
TO DIGI IF
TO CN106
SDCMD
22
R4053
SD_CMD
USBVSS
0.1
GND
(USB)
SDDAT2
SDDAT3
SD_DAT3
SD_DAT2
GPIO0
GPIO1
nUSBDP_PU
DV1INV
SDDAT0
SDDAT1
SD_DAT0
SD_DAT1
DV1VSYNC
AUDIN/GPIO13
AUDOUT/GPIO12
AUDSYNC/GPIO10
0Ω
R4036
AUDIN
AUDOUT
AUDSYNC
TO CN102
DV1INH
DV1IN6
DV1IN7
DV1CLKIN
DV1UV7
DV1UV6
DV1CLKIN
DV1HSYNC
AUDBITCLK/GPIO9
nAUDRESET/GPIO8
GPIO11
GPIO41
TL4008
AUDBITCLK
nAUDRESET
nAUDRESET
TO MPEG2
DV1IN3
DV1IN4
DV1IN5
DV1UV5
DV1UV4
DV1UV3
GPIO40
GPIO43
GPIO42
TL4010
TL4011
DV1IN0
DV1IN1
DV1IN2
TL4019
DV1UV0
DV1UV1
DV1UV2
UART2RXD
UART2TXD
VCLKIN
220
R4040
CLK27A
TG_FLD
FLDCPU
TO CN101
TO CN102
TO P.PRCS
R4050
R4051
R4052
VSS43
VSS44
DV1CLKOUT
GPIO32/PHASEERR
GPIO33/nVRESET
47k
R4042
47k
R4041
47k
47k
VSS38
VSS39
VSS40
VSS41
VSS42
GPIO34/ZEBRASKIN
GPIO35/CSYNC
GPIO36/HSYNC
GPIO37/VSYNC
FSADJp
47k
TL4013
R4044
VSS37
FSADJn
VSS36
TVOUTG
VSS35
TVOUTR
VSS34
TVOUTB
VSS32
VSS33
TVOUTY
TVOUTCHR
VSS31
DV2CLKIN
220
47k
R4046
R4045
VSS28
VSS29
VSS30
DV2CLKOUT
DV2HSYNC
DV2VSYNC
TL4005
TL4004
DV2CKOUT
VSS26
VSS27
DV2UV7
DV2UV6
DV2OUT6
DV2OUT7
DIGITAL(NUCORE
10
VSS11
VSS12
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
DV2UV5
DV2UV4
DV2UV3
DV2UV2
DV2UV1
DV2UV0
CVDD1
CVDD2
CVDD3
CVDD4
CVDD5
CVDD6
CVDD7
CVDD8
CVDD9
RA4001
RA4002
220
DV2OUT4
DV2OUT5
220
DV2OUT3
DV2OUT2
DV2OUT0
DV2OUT1
0.1 0.1
C4036 C4035
IC4002
SN74AHC1G04DC-X
C4018
TO NUCORE
VSS4
VSS5
VSS6
VSS8
VSS9
VSS10
CVDD10
CVDD11
CVDD12
CVDD13
CVDD14
CVDD15
CVDD16
0.1 0.1 0.1
C4034 C4033 C4032
0.1
R4071
4.7k
D4002
Q4001
R4070
4.7k
D4003
1SS376-X
R4072
NU_RX
VSS3
PLLDVDD2
PLLDVDD1
PLLAVDD2
PLLAVDD1
PLLDVSS2
PLLDVSS1
PLLAVSS2
PLLAVSS1
CVDD17
VSS2
nMCS3
nMCS2
nMCS1
MVDD11
MVDD10
MVDD9
MVDD8
MVDD7
MVDD6
MVDD5
MVDD4
MVDD3
MVDD2
MVDD1
VDD26
VDD25
VDD24
VDD23
VDD22
VDD21
VDD20
VDD19
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD
VDD10
VDD9
VDD8
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
AVDD5
AVDD4
AVDD3
AVDD2
AVDD1
AVDD0
AVSS10
AVSS9
AVSS8
AVSS7
AVSS6
AVSS5
AVSS4
AVSS3
AVSS2
AVSS1
AVSS0
PLLPVDD
PLLPVSS
NU_TX
TO CN108
)
C4028
C4031
T
0.01
C4021
2SC5658/QRS/-X
C4030
R4033
C4006
22
C4007
0.1
C4008
0.1
C4009
0.1
C4010
0.1
C4011
0.1
C4012
0.1
C4013
0.1
C4014
0.1
C4015
0.1
C4016
0.1
C4017
0.1
0Ω
C4027
0.1
C4029
0.1
0.1
/6.3
IC4003
MM1613DN-X
C4019
0.1
0.1
1
L4003
L4001
NQR0129-002X
C4001
T
10
/6.3
L4002
NQR0129-002X
C4002
T
10
/6.3
L4004
C4004
10
L4005
T
C4005
T
10
/6.3
R4049
0Ω
L4006
NQR0448-002X
C4020
1
R4057
0Ω
REG_2.5V
TO REG
REG_3.1V
NQR0006-001X
REG_1.2V
GND
TO REG
REG_4.8V
y10482001a_rev0
DIGITAL(MEMORY) SCHEMATIC DIAGRAM
10
DIGITAL(
5
MEMORY
)
L4301
10
C4301
T
/6.3
R4306
PMA17
A16
A15
PMA16
C4303
BYTE
A14
PMA15
47k
0.1
Vss
A13
PMA14
PMD15
DQ15/A-1
A12
PMA13
PMD7
PMD14
DQ7
A11
PMA12
PMD6
DQ14
A10
PMA11
PMD13
DQ6
A9
PMA10
R4301
PMA9
C4302
PMD5
PMD12
PMD4
Vcc
DQ4
DQ5
DQ12
DQ13
IC4301
MBPL32BM90PBB03
RESET
WE_
NC
A19
A8
nPMWE
nFLSHRST
PMA20
PMA21
0Ω
PMD11
0.1
DQ11
NC
R4302
PMD3
DQ3
NC
PMD10
DQ10
RY/BY
PMD2
DQ2
A18
PMA19
PMD9
DQ9
A17
PMA18
PMD1
DQ1
A7
PMA8
PMD8
DQ8
A6
PMA7
PMD0
DQ0
A5
PMA6
nPMOE
OE_
A4
PMA5
PMA4
nPMCS7
Vss
A3
PMA3
CE_
A2
PMA1
A0
A1
PMA2
100k
R4347R4348
100k
R4331R4332
100k
R4346 R4345
R4330
100k
R4343
R4328
100k
R4342
R4326
100k
R4340 R4339
100k
R4324
100k
R4338 R4337
100k
100k
R4321
100k
R4336 R4335
100k
R4320
R4334 R4333
100k
100k
SDR_DQ31
R4318 R4317
SDR_DQ30
100k
SDR_DQ29
SDR_DQ28
SDR_DQ27
SDR_DQ26
SDR_DQ25
SDR_DQ24
SDR_DQ23
100k
SDR_DQ22
SDR_DQ21
SDR_DQ20
SDR_DQ19
SDR_DQ18
SDR_DQ17
SDR_DQ16
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA19
PMA20
PMA21
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
nPMCS7
nPMWE
nPMOE
nFLSHRST
NQR0129-002X
TO MPEG2
NUCORE
P.PRCS
TO MPEG2
NUCORE
TO MPEG2
NUCORE
P.PRCS
TO MPEG2
NUCORE
P.PRCS
CN102
REG_2.5V
REG_3.1V
GND
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA19
PMA20
PMA21
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
nPMCS7
nPMWE
nPMOE
FLSH_RST
R4316
0Ω
TO REG
4
TO NUCORE
3
TO NUCORE
TO CN101
2
TL4302
TL4303
TL4304
TL4305
TL4306
TL4307
TL4308
NQR0129-002X
10
L4302L4303
C4326
T
/6.3
SDR_DQ0
SDR_DQ1
SDR_DQ2
SDR_DQ3
SDR_DQ4
C4314
SDR_DQ5
0.1
SDR_DQ6
SDR_DQ7
SDR_DQM0
SDR_WE
SDR_CAS
SDR_RAS
SDR_CS0
SDR_BA0
SDR_BA1
SDR_A10
SDR_A0
SDR_A1
SDR_A2
SDR_A3
C4321
0.1
SDR_DQ16
SDR_DQ17
SDR_DQ18
SDR_DQ19
SDR_DQ20
SDR_DQ21
SDR_DQ22
SDR_DQ23 SDR_DQ24
SDR_DQM2
C4323
0.1
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQM0
WE_
CAS_
RAS_
CS_
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD VSS
VDD
DQ16
VDDQ
DQ17
DQ18
VSSQ
DQ19
DQ20
VDDQ
DQ21
DQ22
VSSQ
DQ23
VDDQ
DQM2
NC
NC
VDDQ
IC4302
K4S563233F-HN75
VDDQ
VDDQ
DQM3
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
DQM1
CLK
CKE
A12
A11
VSS
DQ31
VSSQ
DQ30
DQ29
DQ28
DQ27
VSSQ
DQ26
DQ25
DQ24
VSSQ
VSSQ
SDR_DQ15
SDR_DQ14
SDR_DQ13
SDR_DQ12
SDR_DQ11
SDR_DQ10
SDR_DQ9
SDR_DQ8
NC
A9
A8
A7
A6
A5
A4
NC
NC
R4310
SDR_DQM1
SDR_CLK
SDR_CKE
SDR_A12
SDR_A11
SDR_A9
SDR_A8
SDR_A7
SDR_A6
SDR_A5
SDR_A4
SDR_DQ31
SDR_DQ30
SDR_DQ29
SDR_DQ28
SDR_DQ27
SDR_DQ26
SDR_DQ25
SDR_DQM3
C4318
0.1
C4325
0.1
SDR_A0
SDR_A1
SDR_A2
SDR_A3
SDR_A4
SDR_A5
SDR_A6
SDR_A7
SDR_A8
SDR_A9
SDR_A10
SDR_DQ0
SDR_DQ1
SDR_DQ2
SDR_DQ3
SDR_DQ4
SDR_DQ5
SDR_DQ6
SDR_DQ7
SDR_DQ8
SDR_DQ9
SDR_DQ10
SDR_DQ11
SDR_DQ12
SDR_DQ13
SDR_DQ14
SDR_DQ15
SDR_DQ16
SDR_DQ17
SDR_DQ18
SDR_DQ19
SDR_DQ20
SDR_DQ21
SDR_DQ22
SDR_DQ23
SDR_DQ24
SDR_DQ25
SDR_DQ26
SDR_DQ27
SDR_DQ28
SDR_DQ29
SDR_DQ30
SDR_DQ31
SDR_DQM0
SDR_DQM1
SDR_DQM2
SDR_DQM3
SDR_WE
SDR_CAS
SDR_RAS
SDR_CS0
SDR_BA0
SDR_BA1
SDR_CKE
SDR_CLK
SDR_A11
SDR_A12
TO NUCORE
SDR_A0
SDR_A1
SDR_A2
SDR_A3
SDR_A4
SDR_A5
SDR_A6
SDR_A7
SDR_A8
SDR_A9
SDR_A10
SDR_DQ0
SDR_DQ1
SDR_DQ2
SDR_DQ3
SDR_DQ4
SDR_DQ5
SDR_DQ6
SDR_DQ7
SDR_DQ8
SDR_DQ9
SDR_DQ10
SDR_DQ11
SDR_DQ12
SDR_DQ13
SDR_DQ14
SDR_DQ15
SDR_DQ16
SDR_DQ17
SDR_DQ18
SDR_DQ19
SDR_DQ20
SDR_DQ21
SDR_DQ22
SDR_DQ23
SDR_DQ24
SDR_DQ25
SDR_DQ26
SDR_DQ27
SDR_DQ28
SDR_DQ29
SDR_DQ30
SDR_DQ31
SDR_DQM0
SDR_DQM1
SDR_DQM2
SDR_DQM3
SDR_WE
SDR_CAS
SDR_RAS
SDR_CS0
SDR_BA0
SDR_BA1
SDR_CKE
SDR_CLK
SDR_A11
SDR_A12
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
A
BCDEFG
2-11 2-12
y20352001a_rev0
DIGITAL(P.PRCS) SCHEMATIC DIAGRAM
CLK1M0
CLK4M5
TO CN102
CAM_VD
5
TO CN101
4
ACHI10
ACHI11
ACHI12
ACHI13
TO CN101
BCHI10
BCHI11
BCHI12
3
TO CN102
TO CN101
TO CN102
TO CN102
TO CN101, CN102
TO CN102
TO TL104
TO TL102
2
TO CN102
TO CN101, CN102
TO CN102
TO CN101, CN102
TO CN102
TO NUCORE
TO CN102
TO MPEG2
TO CN102
TO NUCORE
BCHI13
CDS_STBY
TG_RST
F/Z_CS
IRIS_CS
IRIS_PS
ND_O/C
SCPU_CS
STRB_CHG
STRB_SNS
LENS_LED
VENC_CS
LCD_CS
VENC_RST
LCD_BL
ANA_IN_H
PS_CTL
CAM_CLK
CAM_IN
CAM_OUT
VIF_CLK
VIF_OUT
SCPU_SCK
SCPU_SI
SCPU_SO
VDCPU
FLDCPU
CLK27A
CLK27B
S_SHUT
AFE_RST
1
HDIRS
VDIRS
MCLKI
TG_HD
TG_VD
TG_ID
ACHI0
ACHI1
ACHI2
ACHI3
ACHI4
ACHI5
ACHI6
ACHI7
ACHI8
ACHI9
BCHI0
BCHI1
BCHI2
BCHI3
BCHI4
BCHI5
BCHI6
BCHI7
BCHI8
BCHI9
TG_CS
G_RST
S_IN_L
VIF_IN
ID_LAT
CLK1M0
CLK4M5
CAM_VD
HDIRS
VDIRS
TG_HD
TG_VD
TG_ID
ACHI0
ACHI1
ACHI2
ACHI3
ACHI4
ACHI5
ACHI6
ACHI7
ACHI8
ACHI9
ACHI10
ACHI11
ACHI12
ACHI13
BCHI0
BCHI1
BCHI2
BCHI3
BCHI4
BCHI5
BCHI6
BCHI7
BCHI8
BCHI9
BCHI10
BCHI11
BCHI12
BCHI13
TG_RST
F/Z_CS
IRIS_CS
IRIS_PS
ND_O/C
SCPU_CS
STRB_CHG
STRB_SNS
LENS_LED
VENC_CS
LCD_CS
G_RST
SCPU_SCK
ID_LAT
VDCPU
FLDCPU
CLK27A
CLK27B
S_SHUT
AFE_RST
TG_CS
CAM_CLK
CAM_IN
CAM_OUT
SCK2
SCPU_SI
SCPU_SO
10
ACHI0
ACHI1
ACHI2
ACHI3
ACHI4
ACHI5
ACHI6
ACHI7
ACHI8
ACHI9
ACHI10
ACHI11
ACHI12
ACHI13
BCHI0
BCHI1
BCHI2
BCHI3
BCHI4
BCHI5
BCHI6
BCHI7
BCHI8
BCHI9
BCHI10
BCHI11
BCHI12
BCHI13
SI2
SO2
ENCFLD
DIGITAL(P.PRCS
C4538
0.1
C4539
0.1
TG_RST
F/Z_CS
IRIS_CS
IRIS_PS
ND_O/C
SCPU_CS
TG_CS
STRB_CHG
STRB_SNS
LENS_LED
VENC_CS
LCD_CS
G_RST
R4558
R4559
R4563
R4564
R4566
R4568
R4569
R4578
R4571
R4572
R4573
R4580
470
470
22k
R4562
470
22k
470
R4565
0
22k
R4567
0
0
0
470
470
0
100
C4540
0.1
C4508
0.1
R4514
100
R4515
10k
)
C4537
0.1
3.3V_VDD
3.3V_GND
ACHI0
ACHI1
ACHI2
ACHI3
ACHI4
ACHI5
ACHI6
ACHI7
ACHI8
ACHI9
ACHI10
ACHI11
ACHI12
ACHI13
BCHI0
BCHI1
BCHI2
BCHI3
BCHI4
BCHI5
BCHI6
BCHI7
BCHI8
BCHI9
BCHI10
BCHI11
BCHI12
BCHI13
VDD
VDD
VDD
GND
GND
GND
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
PWMO0
PWMO1
PWMO2/TO0
PWMO3/TO1
PWMO4/TO2
3.3V_VDD
3.3V_GND
IC4502
M95320-WDW6-X
VDD
VDD
SO
HOLD
WP
VSS SI
0.1
C4507
VDD
VCCCS
SCK
TG_HD
HDAFE
TG_VD
100
100
R4557
R4556
VDAFESCK0
470
R4501
CAM_CLK
CAM_IN
TL4516
TL4515
OBCP
FLDAFE
SI0
SO0
470
R4502
CAM_OUT
TG_ID
470
R4503
ID
SCK1
470
R4504
L4501L4502
0
NQL38DK-100X
C4504
10
TL4517
TL4514
MCLKI
MSHUT1
SI1
SO1
SCK2
SI2
SO2
470
470
470
470
R4505
R4506
R4507
R4509
SI2
SCK2
SO2
SCPU_SCK
MSHUT2
HSCK
470
R4510
SCPU_SI
CLK1M0
STROB
CLK1M0
HSI
HSO
SCPU_SO
CAM_VD
CLK4M5
1K1K1K
R4555
R4554
CLK4M5
470
R4512
HDIRS
R4553
VDMDA
GND
HDIRS
GND
VDIRS
1K
R4552
VDIRS
GND
1K
R4551
C4535
10
C4536
0.1
TL4501
NQL38DK-100X
L4507
T
AVDDP1
AGNDP1
OMT0
OMT1
ID_LAT
PLLI1
VDCPU
R4518
VDCPU
PLLSEL1
FLDCPU
R4519
FLDCPU
ENCFLD
000
R4520
ENCFLD
3.3V_VDD
IC4501
JCY0209
3.3V_GND
3.3V_VDD
0.1
C4509
C4534
0.1
3.3V_VDD
R4521
CLK27A
R4548
R4547
SYSSEL0
3.3V_GND
CLK27A
CLK27B
INH
220
R4522
NQR0305-001X
C4510
0.01
CLK27B
0
TVSEL
SYSSEL1
INVKOCLR
S_SHUT
R4546
R4545
0
1k
R4524
R4523
AFE_RST
CTRI
ADHTEST
AVDDP2
L4505
NQL38DK-100X
TMC1
AGNDP2
C4512
0.1
T
C4511
10
TMC2
PLLREF2
PLLFB2
SSGFLD
0
R4544
JTEST0
PLLI2
OUTV2
000
R4543
JTEST1
JTEST2
PLLSEL2
ANA_IN_H
R4541
R4542
JTEST3
PMD0
PMD0
MODE
PMD1
PMD1
C4533
PMD2
0.1
PMD2
VDD
PMD3
PMD3
GND
PMD4
PMD4
GND
PMD5
PMD5
PMD6
PMD6
PPRO0
DOUT0
PMD7
PMD7
PPRO1
DOUT1
PMD8
PMD8
PPRO2
DOUT2
PMD9
PMD9
PPRO3
DOUT3
PMD10
PMD10
PPRO4
DOUT4
PMD11
PMD11
PPRO5
DOUT5
PMD12
PMD12
PPRO6
DOUT6
PMD13
PMD13
PPRO7
DOUT7
PMD14
PMD14
PPRO8
DOUT8
PMD15
PMD15
PPRO9
PPRO10
PPRO11
DOUT9
DOUT11
DOUT10
VDD
VDD
VDD
C4513 C4514
0.1 0.1
VLD_PIX
100
R4539
VPIX
SOF
VCLK
100
R4540
SOF
VCLK
DMAREQ_B
3.3V_VDD
3.3V_GND
100
R4538
3.3V_VDD
3.3V_GND
TRST
3.3V_VDD
3.3V_VDD
3.3V_GND
AVDDA
AGNDA
AVREFP
AVREFM
CREQ
CACK
PMCS
PMWE
PMOE
PMWAIT
PMINT
PMBLS0
PMBLS1
DMAREQ
DMACLR
PMA0
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
ANA_IN_H
C4525
0.01
R4525
0
C4526
0.01
PPRO0
PPRO1
PPRO2
PPRO3
PPRO4
PPRO5
PPRO6
PPRO7
PPRO8
PPRO9
PPRO10
PPRO11
VLD_PIX
SOF
VCLK
PMA0
R4576
39K
C4527
0.01
SSGFLD
OUTV2
R4537
R4536
R4535
R4534
R4533
R4532
R4531
R4530
nPMCS1
nPMWE
nPMOE
nPMWAIT
PMINT
nPMBLS0
nPMBLS1
DMASREQ
DMABREQ
DMACLR
PMA0
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
L4503
NQL38DK-100X
L4504
0
C4506
10
C4531
0.1
VDD
VDD
VDD
GND
TDI
TMS
TCK
TDO
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
VDD
GND
GND
VDD
VDD
GND
C4519
0.1
C4530
0.1
C4529
0.1
C4528
0.1
C4518
10
C4517
0.1
C4516
0.1
L4506
NQL38DK-100X
T
C4520
0.01
R4528
R4527
R4526
C4521
0.01
C4515
0
0
0
R4579
470k
C4522
0.01
TL4506
TL4505
TL4504
TL4503
TL4502
C4524
0.01
C4523
0.01
nPMCS1
nPMWE
nPMOE
nPMWAIT
PMINT
nPMBLS0
nPMBLS1
DMASREQ
DMABREQ
DMACLR
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
IC4503
TC7SH32FU-X
R4577
47K
R4575
22K
REG_3.1V
REG_1.5V
GND
ANA_IN_H
TO TL102
SSGFLD
TO NUCORE
OUTV2
TO CN102
PPRO0
PPRO1
PPRO2
PPRO3
PPRO4
PPRO5
PPRO6
PPRO7
TO NUCORE
PPRO8
PPRO9
PPRO10
PPRO11
VLD_PIX
SOF
VCLK
Z_PTR_AD
8.2K
F_PTR_AD
12K
OP_THRMO
0
0
0
0
0
0
TO CN102
NDHAL_LV
STRB_AD
P_GYAMP
TO CN101
Y_GYAMP
TO CN102
S2_DET
nCREQ
TO MEPG2
nCACK
nPMCS1
TO NUCORE
nPMWE
TO MPEG2, NUCORE, MEMORY
nPMOE
nPMWAIT
TO MPEG2, NUCORE
PMINT
nPMBLS0
nPMBLS1
TO NUCORE
DMASREQ
DMABREQ
DMACLR
PMA0
TO MPEG2, NUCORE
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMD0
TO MPEG2
PMD1
NUCORE
PMD2
MEMORY
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
A
BCD EFG
2-13 2-14
y10486001a_rev0
ANALOG(ANA IF) SCHEMATIC DIAGRAM
CN204
5
4
3
2
1
QGF0306F2-33X
TO OP DRV
CN209
QGF0532F2-11X
TO OPE1
DRIVE-IS
DRIVE+IS
HGVcc+IS
HGout+IS
HGVss-IS
HGout-IS
Z_LED
Z_PTR_AD
ZOOM02
ZOOM03
ZOOM04
ZOOM01
F_VCC
F_PTR_AD
OP_THRMO
GND
FOCUS02
FOCUS03
FOCUS04
FOCUS01
GND
HGVcc+ND
HGout-ND
GND
DRIVE-ND
DRIVE+ND
GND
HGVss-ND
HGout+ND
GND
MODE_SW
POFF_SW
REC_SW
PLAY_SW
VIDE_LED
STIL_LED
VOIC_LED
REG_3.1V
CHRG_LED
AL_3.3V
TO SUB CPU
CN205
QGF0532F2-10X
STRB_EVR
GATE_PLS
STRB_CHG
TO STROBE UNIT
GND
GND
ISO200
STRB_AD
DRV_4.8V
DRV_4.8V
STRB_SNS
DRV_4.8V
DRV_4.8V
L101
10Ω
REG_3.1V
REG_3.1V
REG_4.8V
REG_4.8V
R101
3k
REG_8.5V
AL_3.3V
TO SUB CPU
TO OP DRV
IR_OUT
C101
10
/6.3
T
Q101
RPM-22PB
GND
TL202 LCD_OPEN
TL203
TALY_LED
470
R6816
NRSA63J-102X
R6817
NRSA63J-471X
1k
D6801
RB706D-40-X
BT6801
QAB0040-001
PS_CTL
GND
GND
LCD_RVS
R1009
2.2k
D6802
RB715F-X
TO V I/O
TO OP DRV
ASPECT_S
VIOCOUT
GND
GND
D1003
SML-A12UT-X
TO V I/O
DC_CHEK
VIOYSOUT
TO SUB CPU
AL_3.3V
LIT_3V
GND
I_MTR
V_BATT
T_BATT
REG_3.1V
TO SUB CPU
CHRG_EVR
KEY_A
KEY_B
KEY_C
ZOOM_SW
ACES_LED
CF_SLOT
XSTH
STH
TO LCD DRV
CKH1
CKH2
VHVDD
VHVDD
TO MIC TO SPEAKER
GND
GND
MIC/L
MIC/R
TO AUDIO TO AUDIO
GND
GND
MON_G
MON_R
MON_B
CSH
SC
DSD
CN202CN201
QGA1001F1-02XQGA1001F1-04X
XDSG
DSG
SPK-
SPK+
ANALOG(
20
TO LCD DRV
STV
XSTV
ENB
XENB
CSV
CKV2
CKV1
VCOM
PWR_CHEK
LCD_BLK
ADP_L
SJIG_RST
BATT_L
ANA IF
TO SUB CPU
TO AUDIO
AU_SIG/R
P_DET
REG_DATA
REG_CLK
REG_CS
TO P.PRCS, LCD DRV, V I/O
TO NUCORE, MPEG2, V I/O
TO P.PRCS, NUCORE, MPEG2, AC97
TO P.PRCS, OP DRV, V I/O
TO P.PRCS, NUCORE, STROBE
)
TO SUB CPU
TO AUDIO
HP_SIG/L
HP_SIG/R
HP_DET
AU_SIG/L
TO JIG, SUB CPU
TO NUCORE, SUB CPU
TO P.PRCS, LCD DRV
TO NUCORE, V I/O
TO MPEG2, V I/O
TO NUCORE, AC97
TO MPEG2, AUDIO
TO P.PRCS, AUDIO
TO MEMORY, SUBCPU
TO P.PRCS, SUBCPU
TO P.PRCS, GYRO
TO NUCORE, OP DRV
TO P.PRCS, OP DRV
TO SUB CPU
TO JIG, LCD DRV
SJIG_RST
SJIG_RX
SJIG_TX
DSP_RST
PWR_CHEK
LCD_BL
LCD_CS
OUTV2
VIF_OUT
VIF_IN
VIF_CLK
PS_CTL
REG_2.5V
VENC_CS
DV2OUT0
DV2OUT1
DV2OUT2
DV2OUT3
DV2OUT4
DV2OUT5
DV2OUT6
DV2OUT7
MPGFLD
DV2CKOUT
MPGHSYNC
MPGVSYNC
CLK27A
VENC_RST
ACPLLOFF
AUDIN
AUDOUT
AUDSYNC
AUDBITCLK
nAUDRESET
AIBD
AOBD
AIOLRCK
AOMCLK
AIOBCK
S_SHUT
FLSH_RST
SCPU_CS
SCPU_SCK
SCPU_SI
SCPU_SO
G_RST
Y_GYAMP
NDPWM
NDHAL_LV
ND_O/C
CAM_IN
IRIS_CS
IRIS_PS
CLK1M0
VDIRS
HDIRS
Z_PTR_AD
F_PTR_AD
OP_THRMO
F/Z_CS
LENS_LED
CLK4M5
CAM_VD
CAM_CLK
CAM_OUT
TG_RST
STRB_CHG
STRB_EVR
STRB_AD
STRB_SNS
AL_3.3V
MD_THRMO
REG_4.8V
MON_G
MON_R
MON_B
MON_RPD
VCOM
GND
VPP
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
GND
CN203
QGB0402J2-B0X
TO DIGITAL
(CN102)
CN206
QGA1002F1-10X
TO REG(CN301) TO REG(CN302) TO REG(CN303)
CN207
QGA0401F1-25W
CN208
QGA0503F1-30X
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS". 2. The parts with marked () is not used.
A
BCDEFG
2-15 2-16
y10484001a_rev0
ANALOG(SUB CPU) SCHEMATIC DIAGRAM
TO REG
TO CN208
5
LIT_3V
BATT_L
ADP_L
AL_3.3V
REG_3.1V
GND
L1001
10µ
C1037
C1001
6.3V
10/
C1002
10/
6.3V VSS
IC1007
MB90097PFV155-X
SCLK
IC1003
L1002
10µ
C1003
0.1
IC1002
IC-PST3423U-X
100K
R1001
C1004
0.1
0.1
RS5C314-X
CLKCSXin
SIO
INTR
X1002
VDD
NAX0491-001X
Xout
C1005
8p
IC1004
SN74LV32ADGV-X
0.01
C1008
R1028
1K
0.1
C1036
CS
DATA
RST
VDD
SDR
BLKA
XD
EXD
BLKB
TEST
TST0
VSS BLKC
HD
VD
VC0
VC1
VC2
VC3
OSD_HD
OSD_VD
VC0
VC1
VC2
BLKA
VC3
BLKB
BLKC
DOT_CLK
TO V I/O
TO CN203, 208
4
TO AUDIO
TO CN209
TO CN207
TO ANA IF
3
2
TO CN203
TO CN208
TO CN209
TO TL202
TO CN203
TO CN208
TO CN203
SJIG_RST
BUZZER
VOIC_LED
STIL_LED
VIDE_LED
CHRG_LED
ACES_LED
TALY_LED
REG_DATA
REG_CLK
POFF_SW
LCD_OPEN
SCPU_SI
SCPU_SCK
SCPU_SO
REG_CS
FLSH_RST
DSP_RST
A_MUTE
100K
R1058
CHRG_EVR
P_DET
AUEE_CTL
HP_DET
100k
R1016
CF_SLOT
L_MUTE
LCD_RVS
PLAY_SW
REC_SW
MODE_SW
SJIG_RX
SJIG_TX
AUD_CLK
AUD_DATA
PD_L
AUDIO_CS
R1060
47K
MD_THRMO
KEY_B
KEY_A
ZOOM_SW
KEY_C
I_MTR
T_BATT
V_BATT
DC_CHEK
SCPU_CS
)
R1002
Q1001
2SC4617/QR/-X
UN9212J-X
10K
R1005
R1006
4.7K
VPP
100K
100K
R1051
R1050
R1052
R1053
R1054
100K
1K
100K
1K
R1055
C1018
DTC124EE-X
PDTC124EE-X
Q1002
R1039
R1025
R1015
R1008
R1049
IC1006
SN74LV86ADGV-X
C1019
0.1
0.1
C1020
0.01
18K
R1004
D1001
DA221-X
C1006
1
47K
R1007
470
470
470
2.2K
470
C1021
R1011
100K
0.1
C1011
C1012
C1013
C1014
C1015
C1016
C1017
2.2K
100K
2.2K
R1020
R1033
R1012
AVSS
TALLY
KEY_A
KEY_B
10K
R1027
C1007
C1010
R1048
2.2K
NAX0647-001X
X1001
0.01
0.01
0.01
0.01
0.01
0.01
0.01
V_BATT
T_BATT
I_MTR
KEY_C
VPP
AVDD
VDD
OSC2
OSC1
VSS
XI
XO
MMOD
RESET
REG_DATA
RTC_DATAIN
ZOOM_SW
REG_CLK
SUB_CPU_SO
CHRG_LED
MN101C77CJC
SUB_CPU_SI
SUB_CPU_SCK
REG_CS
FLSH_RST
ACCESS_LED
IC1001
RTC_CS
STILLLED
VIDEOLED
DSP_RST
OSD_CS
A_MUTE
VOICELED
P_DET
CF_SLOT
AUDIO_CLK
AUDIO_DATA
DC_CHEK
CHRG_WKUP
BZ_ENV
BZ_FREQ
CHRG_EVR
LCD_OPEN_SW
SUB_CPU_CS
REMOTE
OSD_VD
R1059
HP_DET
AUEE_CTL
SD_SLOT
L_MUTE
LCD_RVS_SW
PLAY_SW
POFF_SW
REC_SW
MODE_SW
PD_L
AUDIO_CS
JIG_CLK
JIG_DATA
KEY_WKUP
SYSTEM_SIG
470K
R1046
R1030
1K
1K
R1031
R1017
TL1002
1K
R1024
ANALOG(SUB CPU
20
100K
R1044
SN74AHC2G53T-X
C1038
IC1005
R1042
R1043
R1041
R1038
R1036
R1021
R1022
R1023
R1013
TL1001
0.01
1K
1K
100k
R1018
1K
1K
1K
1K
1K
1K
1K
R1003
150K 2.7K
TO AUDIO
TO CN207
TO CN208
TO AUDIO
TO CN208
TO CN207
TO AUDIO
TO TL203
TO CN209
TO CN203
TO AUDIO
TO CN203
TO CN207
TO CN207
TO CN203
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
A
BCD EFG
2-17 2-18
y20337001a_rev0
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