JVC GZ-MC100US Diagram
SCHEMATIC DIAGRAMS
DIGITAL MEDIA CAMERA
YF058200411
GZ-MC100US
CD-ROM No.SML200412
GZ-MC100US [M4S327]
COPYRIGHT © 2004 Victor Company of Japan, Limited
No.YF058SCH
2004/11
CHARTS AND DIAGRAMS
NOTES OF SCHEMATIC DIAGRAM
Safety precautions
The Components indentified by the symbol are
critical for safety. For continued safety, replace safety
critical components only with manufacturer's recommended parts.
1. Units of components on the schematic diagram
Unless otherwise specified.
1) All resistance values are in ohm. 1/6 W, 1/8 W (refer to
parts list).
Chip resistors are 1/16 W.
K: KΩ(1000Ω), M: MΩ (1000KΩ)
2) All capacitance values are in µF, (P: PF).
3) All inductance values are in µH, (m: mH).
4) All diodes are 1SS133, MA165 or 1N4148M (refer to parts
list).
Note: The Parts Number, value and rated voltage etc. in
the Schematic Diagram are for references only.
When replacing the parts, refer to the Parts List.
2. Indications of control voltage
AUX : Active at high.
AUX or AUX(L) : Active at low.
!
4. Voltage measurement
1) Regulator (DC/DC CONV) circuits
REC : Colour bar signal.
PB : Alignment tape (Colour bar).
— : Unmeasurable or unnecessary to measure.
2) Indication on schematic diagram
Voltage indications for REC and PB mode on the schematic diagram are as shown below.
REC mode
12 3
2.5
(5.0)
PB mode
1.8
PB and REC modes
(Voltage of PB and REC modes
are the same)
Note: If the voltages are not indicated on the schematic
diagram, refer to the voltage charts.
5. Signal path Symbols
The arrows indicate the signal path as follows.
NOTE : The arrow is DVC unique object.
Playback signal path
Playback and recording signal path
3. Interpreting Connector indications
1
2
Removable connector
3
1
2
Wire soldered directly on board
3
1
Non-removable Board connector
2
3
1
2
4
Board to Board
3
Connected pattern on board
The arrows indicate signal path
Note: For the destination of each signal and further line
connections that are cut off from the diagram,
refer to "BOARD INTERCONNECTIONS"
Recording signal path
(including E-E signal path)
Capstan servo path
Drum servo path
(Example)
R-Y
Playback R-Y signal path
Y
Recording Y signal path
6. Indication of the parts for adjustments
The parts for the adjustments are surrounded with the circle
as shown below.
7. Indication of the parts not mounted on the circuit board
“OPEN” is indicated by the parts not mounted on the circuit
board.
R216
2-1
OPEN
CIRCUIT BOARD NOTES
1. Foil and Component sides
1) Foil side (B side) :
Parts on the foil side seen from foil face (pattern face)
are indicated.
2) Component side (A side) :
Parts on the component side seen from component face
(parts face) indicated.
rts location are indicated by guide scale on the circuit board.
2. Parts location guides
Parts location are indicated by guide scale on the circuit board.
LOCATION
IC
Category : IC
Horizontal “A” zone
Vertical “6” zone
(A : Component side)
D : Discrete component)
B : Foil side
C : Chip component
REF No.
IC101 B C 6 A
Note: For general information in service manual, please
refer to the Service Manual of GENERAL INFORMATION Edition 4 No. 82054D (January 1994).
2-2
SDR DQ10
CFD13
SDR DQ10
2
5
BOARD INTERCONNENTION
(Page2-39)
YTU94074-10
YTU94077-10
YTU94129A-33
YTU94109-33
CN101
CN5201
CN102
5
FLSH_RST
REG_3.1V
GND
SDR_DQ30
SDR_DQ31
SDR_DQ30
TG_FLD
NDPWM
nUSBDP_PU
nUSB_DET
USBDP
USBDN
STRB_EVR
PPRD0
PPRD1
PPRD2
PPRD3
PPRD4
PPRD5
PPRD6
PPRD7
PPRD8
PPRD9
PPRD10
PPRD11
VLD_PIX
SOF
VCLK
SSGFLD
DMACLR
DMABREQ
DMASREQ
nPMBLS1
nPMBLS0
nPMCS1
PMINT
FLDCPU
VDCPU
ID_LAT
AFE_RST
CLK27A
DV2CKOUT
nPMWAIT SDR_DQ31
SDR_DQ29
SDR_DQ28
SDR_DQ27
SDR_DQ27
SDR_DQ28
SDR_DQ29
nUSBDP_PU
nUSB_DET
USBDP
USBDN
IR_OUT
S_PDIF
SDR_DQ26
SDR_DQ25
SDR_DQ24
SDR_DQ24
SDR_DQ26
SDR_DQ25
PWR_CHEK
ACPLLOFF
SDR_DQ23
SDR_DQ22
SDR_DQ22
SDR_DQ23
AUDOUT
AUDBITCLK
SDR_DQ21
SDR_DQ21
AUDIN
AUDSYNC
SDR_DQ20
SDR_DQ19
SDR_DQ18
SDR_DQ18
SDR_DQ19
SDR_DQ20
nAUDRESET
(Page
SDR_DQ17
SDR_DQ16
SDR_DQ16
SDR_DQ17
CFD3
nCFCD1
SDR_DQ15
SDR_DQ14
SDR_DQ13
SDR_DQ15
SDR_DQ14
SDR_DQ13
CFD4
CFD11
GND
SDR_DQ12
SDR_DQ12
CFD5
CFD12
REG_3.1V
SDR_DQ11
SDR_DQ11
H2
H1
HL
RG
DRIVE-IS
REG_3.1V
REG_4.8V
DRV_4.8V
GND
DRIVE+IS
HGVcc+IS
HGout+IS
HGVss-IS
Z_LED
HGout-IS
ISO200
GATE_PLS
ZOOM02
ZOOM03
IR_OUT
ZOOM01
ZOOM04
NDPWM
F_VCC
ASPECT_S
FOCUS02
FOCUS01
FOCUS04
HGout-ND
FOCUSO3
HGVcc+ND
(Page2-23)
LENS_LED
F/Z_CS
HDIRS
VDIRS
DRIVE-ND
CAM_VD
CLK1MO
HGVss-ND
DRIVE+ND
TG_RST
CLK4M5
HGout+ND
ND_O/C
NDHAL_LV
CAM_OUT
CAM_CLK
IRIS_CS
IRIS_PS
CAM_IN
REG-7.5V
REG_3.1V
REG_4.8V
GND
CCDOUTA
CCDOUTB
REG_4.8V
REG_3.1V
GND
4
PMA1
PMA9
PMA8
PMA7
PMA6
PMA2
PMA3
PMA4
PMD9
PMD7
PMD6
PMD5
PMD8
PMD4
PMD2
PMD10
PMD11
VI1
VI0
MPGVSYNC
VIF_CLK
VIOYSOUT
VI3
VI2
VIOCOUT
VI4
VI5
VI1
VI0
DV2OUT0
VI7
VI6
VI3
VI2
DV2OUT1
DV2OUT2
PMD3
(Page2-9)
VI4
DV2OUT4
DV2OUT3
PMD15
PMD13
PMD14
PMD12
REG_1.5V
REG_2.5V
REG_3.1V
GND
PMA0
MPGHSYNC
MPGFLD
LCD_B
LCD_R
LCD_G
VDCVF
HDCVF
3
REG_2.5V
REG_4.8V
REG_3.1V
GND
C_OUT
Y_OUT
VIF_OUT
V_OUT
PMD0
PMD1
PMA11
PMA10
AIOLRCK
AIBD
AOMCLK
AOBD
AIOBCK
VI5
VI6
VI7
MPGFLD
MPGVSYNC
MPGHSYNC
(Page2-11)
DV2OUT7
DV2OUT5
DV2OUT6
VC0
nCACK
VC1
nCREQ
VC2
PMA5
VC3
nPMWAIT
DV2CKOUT
BLKC
BLKB
BLKA
nPMOE
nPMWE
DV2CKOUT
OUTV2
VIF_IN
VENC_RST
VENC_CS
S_IN_L
S2_DET
OSD_VD
OSD_HD
CLK27B
DOT_CLK
PMA14
PMA15
DV1CLKIN
MPEG_RST
PMA12
PMA13
DV1IN0
DV1IN1
DV1IN2
DV1IN3
DV1IN4
DV1IN5
DV1IN6
DV1IN7
DV1INH
DV1INV
nCINT
nVOEN
nPMCSO
PLLSTOP
S_PDIF
STRB_AD
STRB_CHG
VDIRS
HDIRS
LENS_LED
F/Z_CS
CAM_VD
CLK1M0
CLK4M5
TG_RST
NDHAL_LV
ND_D/C
IRIS_PS
IRIS_CS
CAM_IN
LCD_CS
LCD_BL
VIF_OUT
VIF_CLK
nCREQ
nCACK
nPMWAIT
CLK27B
OUTV2
VIF_IN
VENC_RST
VENC_CS
S_IN_L
S2_DET
S_SHUT
G_RST
P_GYAMP
Y_GYAMP
ANA_IN_H
PS_CTL
PMA0
STRB_SNS
PMA3
PMA2
PMA1
PMA4
CAM_CLK
CAM_OUT
PMA6
PMA5
TG_ID
MCLKI
TG_VD
TG_CS
TG_HD
PMA10
PMA8
PMA9
PMA7
PMA11
PMD0
PMD1
REG_12V
TG_CS
TG_ID
TG_HD
MCLKI
TG_VD
FLSH_RST
ACHI0
ACHI3
ACHI5
ACHI2
ACHI6
ACHI1
ACHI4
ACHI3
ACHI5
ACHI2
ACHI6
ACHI1
ACHI0
ACHI4
(Page2-21)
PMD8
PMD3
PMD2
PMD7
PMD6
PMD5
PMD4
OV4
CAM_CLK
CAM_OUT
(Page2-17)
ACHI7
ACHI8
ACHI9
ACHI7
ACHI8
ACHI9
PMD10
PMD9
PMD12
PMD11
OV2
OV1
OV3
(Page2-25)
CPOB2
TG_VCC
CPOB2
TG_VCC
ACHI13
ACHI12
ACHI11
ACHI10
BCHI0
BCHI0
ACHI12
ACHI11
ACHI10
ACHI13
PMD15
PMD13
PMD14
nPMDE
nPMWE
SUB
CPOB
CPOB
BCHI1
BCHI1
CCD-7.5V
ADCLK
PBLK
PBLK
ADCLK
BCHI3
BCHI2
BCHI3
BCHI2
SCPU_CS
TG_FLD
DS1a
DS2a
DS1a
DS2a
BCHI5
BCHI4
BCHI5
BCHI4
SCPU_SCK
SCPU_SI
SCPU_SO
BCHI6
BCHI6
DS1b
DS1b
DS2b
DS2b
BCHI7
BCHI8
BCHI7
BCHI8
Z_PTR_AD
BCHI10
BCHI9
BCHI9
BCHI10
REG_3.1V
REG_1.5V
OP_THRMO
F_PTR_AD
BCHI12
BCHI11
BCHI12
BCHI11
PPRD0
PPRD1
PPRD2
PPRD3
PPRD4
PPRD5
PPRD6
PPRD7
PPRD8
PPRD9
PPRD10
PPRD11
VLD_PIX
SSGFLD
DMACLR
DMABREQ
DMASREQ
nPMBLS1
nPMBLSO
nPMCS1
PMINT
FLDCPU
VDCPU
ID_LAT
AFE_RST
CLK27A
BCHI13
CDS_STBY
BCHI13
CDS_STBY
GND
SOF
VCLK
2
YTU94128A-4
CN206
YTU94128A-4
CN302
CN303
1
(Page2-44)
REG_3.1V
GND
G_RST
P_GYAMP
CN301
(Page2-37)
NOTE: The number of patch cords () are indicated by interconnected.
2-3
A
CN201
YTU94128A-4
CN202
BCD
CN105
CN204
MIC/L
MIC/R
SPKSPK+
PD_L
S_SHUT
AIBD
AOBD
L_MUTE
BUZZER
A_MUTE
AUEE_CTL
(Page2-33)
AOMCLK
AIOLRCK
AIOBCK
AUD_CLK
AUDIO_CS
AU_SIG/L
AU_SIG/R
HP_SIG/L
HP_SIG/R
AUD_DATA
M_AUD/R
AC_AUD/L
AC_AUD/R
REG_4.8V
REG_3.1V
M_AUD/L
REG_14V
(Page2-37)
REG_3.1V
Y_GYAMP
M_AUD/L
M_AUD/R
AUDIN
AC_AUD/L
AC_AUD/R
AU_SIG/L
AU_SIG/R
HP_SIG/L
HP_SIG/R
GND
CLK27A
AUDOUT
AUDSYNC
AUDBITCLK
nAUDRESET
(Page2-31)
(Page2-29)
ACPLLOFF
BATT_L
REG_3.1V
TT_BATT
BATT_+
GND
P_DET
HP_DET
C_OUT
ADP_DC
V_BATT
ADP_L
V_OUT
GND
Y_OUT
G_RST
GND
CHRG_EVR
ADP_L
V_BATT
REG_4.8V
REG_14V
ADP_DC
REG_3.1V
GND
REG_CLK
SJIG_RST
REG_DATA
(Page2-3
I_MTR
REG_CS
T_BATT
LIT_3V
DC_CHEK
REG_1.2V
PWR_CHEK
REG_1.5V
D
_
_
A
CN304
S
G
S
AUDIN
CN305
(Page2-43)
YTU94074-24
YTU94077-24
LCD MODULE
CN103
P_PU
ET
_
SDR_DQ21
SDR_DQ20
SDR_DQ19
SDR_DQ18
_
SDR_DQ18
SDR_DQ19
SDR_DQ20
SDR_DQ21
GND
(Page2-19)
SDR_DQ15
SDR_DQ17
SDR_DQ16
SDR_DQ14
SDR_DQ13
SDR_DQ12
SDR_DQ11
SDR_DQ11
SDR_DQ12
SDR_DQ16
SDR_DQ15
SDR_DQ14
SDR_DQ17
SDR_DQ13
(Page2-5)
REG_3.1V
SDR_DQ10
SDR_DQ9
SDR_DQ8
SDR_DQ7
SDR_DQ9
SDR_DQ8
SDR_DQ7
SDR_DQ10
SDR_DQ6
SDR_DQ5
SDR_DQ5
SDR_DQ6
TALY_LED
SDR_DQ4
SDR_DQ3
SDR_DQ4
SDR_DQ3
SDR_DQ2
SDR_DQ1
SDR_DQ2
SDR_DQ1
SDR_DQ0
SDR_DQM3
SDR_DQ0
SDR_DQM3
SDR_DQM1
SDR_DQM0
SDR_DQM2
SDR_DQM0
SDR_DQM1
SDR_DQM2
SDR_WE
SDR_CAS
SDR_WE
SDR_CAS
SDR_RAS
SDR_CSO
SDR_RAS
SDR_CSO
SDR_BA1
SDR_BA0
SDR_BA1
SDR_BAO
VIOYSOUT
VIOCOUT
ASPECT_S
PS_CTL
ANA_IN_H
SDR_CKE
SDR_CKE
CN107
(Page2-13)
SDR_CLK
SDR_A10
SDR_A9
SDR_A8
SDR_A7
SDR_A6
SDR_A9
SDR_A8
SDR_A6
SDR_A7
SDR_A10
SDR_CLK
(Page2-15)
REG_4.8V
SDR_A4
SDR_A5
SDR_A4
SDR_A5
GND
SDR_A3
SDR_A3
Y_OUT
V_OUT
C_OUT
SDR_A2
SDR_A2
SDR_A0
SDR_A1
SDR_A0
SDR_A1
SDR_A11
SDR_A12
SDR_A11
SDR_A12
PMA16
nPMCS7
PMA16
nPMCS7
PMA17
PMA17
PMA18
PMA18
PMA19
PMA19
PMA20
PMA20
PMA21
PMA21
LCD_BLK
REG_3.1V
REG_8.5V
REG_4.8V
REG_14V
GND
PMA1
PMA2
PMA2
PMA1
VHVDD
PMA3
PMA3
CSV
DSG
VBB
CSHSCSTH
DSD
ENB
STV
XSTV
XENB
(Page2-27)
PMD0
PMD1
PMA2
PMD3
PMD4
PMD5
PMA11
PMD0
PMD5
PMD4
PMD3
PMD2
PMD1
PMA11
PMD6
PMD6
CKV1
CKV2
LCD_R
VDCVF
HDCVF
LCD_B
LCD_G
LCD_CS
LCD_BL
VIF_CLK
VIF_OUT
MON_B
MON_R
MON_G
VCOM
MON_RPD
PMA12
PMA13
PMA14
PMA15
REG_2.5V
PMD11
PMD7
PMD8
PMD9
PMD10
PMD15
nPMWE
nPMOE
PMD12
PMD14
PMD13
PMD9
PMD8
PMD7
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
nPMWE
nPMOE
PMA15
PMA14
DV1IN0
DV1IN1
DV1IN2
DV1IN3
DV1IN4
DV1IN5
DV1IN6
DV1INH
DV1INV
DV1CLKIN
nCINT
nVOEN
nPMCS0
MPEG_RST
PLLSTOP
DV1IN7
DV2OUT7
DV2OUT6
DV2OUT5
DV2OUT4
DV2OUT3
DV2OUT2
DV2OUT1
DV2OUT0
PMA13
PMA12
XDSG
XSTH
CKH2
CKH1
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA5
PMA8
PMA4
PMA7
PMA6
PMA9
PMA10
CN110
CN106
CN9901
CN9902
REG_2.5V
REG_3.1V
REG_1.2V
REG_4.8V
ARMTMS
ARMTDO
ARMTCK
ARMTDI
L_MUTE
BUZZER
PD_L
A_MUTE
AUD_DATA
KEY_C
CHRG_LED
nARMTRST
LCD_RVS
LCD_OPEN
CF_SLOT
nJRESET
NU_RX
SJIG_RST
POFF_SW
REC_SW
MOD0
NU_TX
PLAY_SW
MODE_SW
VIDE_LED
STIL_LED
SDCMD
SDCLK
nCFCD2
SCPU_SO
SDDAT3
I_MTR
LIT_3V
AUEE_CTL
SJIG_RX
SJIG_TX
VPP
SDDAT1
SDDAT0
V_BATT
DC_CHEK
SDCD
SDDAT2
REG_CS
REG_DATA
SDWP
REG_CLK
CHRG_EVR
ADP_L
P_DET
BATT_L
T_BATT
(Page2-7)
PMA0
HP_DET
AUD_CLK
AUDIO_CS
CFD10
CFD3
CFD7
CFD6
CFD5
CFD4
CFD11
CFD15
CFD14
CFD12
CFD13
nCFCD1
nAUDRESET
AUDSYNC
T
_R
I_MTR
LIT_3V
T_BATT
JI
REG_CS
REG_CLK
DC_CHEK
REG_DATA
PWR_CHEK
L
TT
_4.8V
_14V
(Page2-35)
DC
_3.1V
REG_1.5V
REG_1.2V
REG_12V
REG_8.5V
AL_3.3V
REG-7.5V
BATT_+
TT_BATT
BATT_L
nCFCE1
nCFCE0
CFA10
YTU94074-30
YTU94077-30
DRV_4.8V
DRV_3.3V
nCFOE
CFA9
nCFIORD
CFA5
CFA3
CFA4
CFA8
CFA6
CFA7
CFRESET
CFCSEL
nCFIOWR
nCFWE
nCFWAIT
CFRDY
CN104 CN111
CN203
CN205
CFD8
CFD9
CFD2
CFD0
CFD1
CFA0
CFBVD1
CFBVD2
CFA2
CFA1
nCFREG
CFWP
SCPU_CS
VCO
VC1
VC2
VC3
BLKA
BLKB
BLKC
OSD_HD
OSD_VD
DOT_CLK
FLSH_RST
SCPU_SI
SCPU_SCK
DSP_RST
KEY_A
VOIC_LED
MD_THRMO
ZOOM_SW
KEY_B
ACES_LED
TALY_LED
DSP_RST
AL_3.3V
REG_3.1V
GND
GND
CN108
CN113
(Page2-51)
YTU94074-20
YTU94077-20
(Page2-41)
OPE. UNIT
y10495001a_rev0
DE F G
2-4
TO NUCORE
DIGITAL(DIGI IF) SCHEMATIC DIAGRAM
TO OP DRV
CN101
QGF0306F2-33X
QGF0307F2-33W
Z_LED
ZOOM02
ZOOM03
DRIVE-IS
DRIVE+IS
HGout+IS
HGVcc+IS
HGout-IS
HGVss-IS
Z_PTR_AD
ZOOM04
F_VCC
ZOOM01
F_PTR_AD
OP_THRMO
GND
FOCUS03
FOCUS02
FOCUS01
FOCUS04
GND
HGout-ND
HGVcc+ND
GND
DRIVE-ND
DRIVE+ND
GND
HGout+ND
HGVss-ND
CN102
QGB0503M2-30X
TO CCD(CN5201)
GND
GND
GND
GND
CCDOUTB
CCDOUTA
CCDOUTB
CCDOUTA
GND
GND
CCD-7.5V
REG_12V
CCD-7.5V
SUB
REG_12V
GND
GND
GND
GND
GND
GND
GND
HL
H1
H2
OV3
OV2
OV1
5
TO SUB CPU
MD_THRMO
TO NUCORE
GND
nCFCD1
CFD3
CFD11
CFD4
CFD12
CFD5
CFD13
CFD6
CFD14
CFD7
CFD15
nCFCE0
nCFCE1
CFA10
nCFOE
4
3
nCFIORD
CFA9
nCFIOWR
CFA8
nCFWE
CFA7
CFRDY
DRV_3.3V
CFA6
CFCSEL
CFA5
CFA4
CFRESET
CFA3
nCFWAIT
CFA2
CFA1
nCFREG
CFA0
CFBVD2
CFD0
CFBVD1
CFD1
CFD8
CFD2
CFD9
CFWP
CFD10
nCFCD2
L601
NQR0339-001X
GND
C601
C602
0.1
T
47
/6.3
TO CF(CN9901)
CN106
QGB0404L1-60X
TO NUCORE
REG_3.1V
nUSBDP_PU
nUSB_DET
USBDP
USBDN
GND
TO CDS
R201
47K
DTC144EM-X
R203
R202
Q201
Q202
2SA2029/QRS/-X
R204
6.8k
TL103
L201
NQR0536-001X
47k
47k
47k
47k
47k
47k
47k
47k
47k
R649
R644
R645
R646
R647
R648
NQR0129-002X
L401
2
REG_3.1V
TO NUCORE
SDDAT2
SDDAT3
SDCMD
GND
SDCLK
SDDAT0
SDDAT1
SDCD
SDWP
D401
D402
47k
47k
R653
R654
R655
R656
R650
R405
R403
47k
47k
R406
R404
10k
47k
C401
10
T
/6.3
0.1
C402
R412
R401
R414
47k
R402
22k
47k
R413
R407
47k
R408
R409
TO SD CARD
CN113
NNZ0102-001X
22
22
22
22
SDDAT2
SDDAT3
SDCMD
VSS( GND)
VDD( DSC_3V)
SDCLK
VSS2/CD
SDDAT0
SDDAT1
SDOCD
SW_COM
SD_WP
GND
GND
GND
CN108
QGB0512L1-30X
ARMTCK
ARMTDO
0Ω
R702
ARMTMS
TO JIG CONNECTOR
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
2-5
A
BCD
TO NUCORE
ARMTDI
nARMTRST
REG_3.1V
nJRESET
0Ω
R703
TO NUCORE
NU_RX
NU_TX
0Ω
R704
AL_3.3V
TO SUB CPU
SJIG_TX
SJIG_RX
01X
OV1
REG_12V
REG_3.1V
nJRESET
0Ω
R703
H2
OV2
TO NUCORE
NU_RX
NU_TX
0Ω
R704
H1
AL_3.3V
HL
OV3
TO SUB CPU
SJIG_TX
SJIG_RX
RG
OV4
TO SUB CPU
TO NUCORE
MOD0
SJIG_RST
TO USB
J101
QNZ0616-001
MON_B
VPP
GND
CN103
QGF0532F2-10X
TO LCD DRV
VCOM
MON_R
GND
MON_G
TO STROBE UNIT
STRB_AD
DRV_4.8V
GATE_PLS
STRB_SNS
STRB_EVR
STRB_CHG
TO P.PRCS
TO P.PRCS
TO OP DRV
TO NUCORE
MON_RPD
GND
ISO200
DRV_4.8V
TO OP DRV
GND
TO LCD SUB(CN304)
CN107
QGA0503F1-30X
LCD_BLK
STH
GND
GND
GND
GND
XSTH
REG_14V
GND
TO MPEG2
TALY_LED
CKH2
CKH1
VHVDD
VHVDD
DIGITAL(DIGI IF
10
TL101 S_PDIF
TL104
SC
CSH
MON_B
TO SUB CPU
MON_G
MON_R
TO LCD HINGE
CN110
QGA1001F1-03X
XDSG
ENB
DSG
XSTV
CKV2
CKV1
XENB
IR_OUT
VCOM
R101
C101
10
/6.3
T
DSD
STV
VBB
CSV
TO NUCORE
TO NUCORE, P.PRCS
TO MPEG2, P.PRCS
TO SUB CPU
TO SUB CPU
TO SUB CPU
TO SUB CPU
)
TO NUCORE
TO SUB CPU
TO SUB CPU
TO SUB CPU
KEY_C
CHRG_LED
AL_3.3V
CF_SLOT
POFF_SW
REC_SW
PLAY_SW
GND
MODE_SW
VIDE_LED
STIL_LED
VOIC_LED
REG_3.1V
KEY_A
ZOOM_SW
ACES_LED
KEY_B
GND
LCD_OPEN
3k
Q101
RPM-22PB
TO P.PRCS
TO MPEG2
TO V OUT
TO V OUT
TO P.PRCS
TO P.PRCS
LCD_RVS
L101
10µ
REG_1.2V
REG_3.1V
DRV_4.8V
REG_4.8V
AL_3.3V
REG_14V
REG_12V
REG_8.5V
REG-7.5V
DRV_3.3V
REG_1.5V
S_SHUT
AIOLRCK
AOMCLK
AIOBCK
nAUDRESET
AUDSYNC
AUDIN
AUDBITCLK
AUDOUT
ACPLLOFF
CLK27A
CLK27B
A_MUTE
AUD_DATA
AUEE_CTL
BUZZER
L_MUTE
AUDIO_CS
AUD_CLK
HP_DET
P_DET
C_OUT
BATT_L
Y_OUT
V_OUT
T_BATT
ADP_L
P_GYAMP
Y_GYAMP
SJIG_RST
CHRG_EVR
REG_CLK
REG_DATA
REG_CS
DC_CHEK
PWR_CHEK
V_BATT
LIT_3V
G_RST
AUEE_CTL
AIBD
AOBD
PD_L
I_MTR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CN104
QGF0530F3-30W
TO ANALOG
(CN203)
CN105
QGF0306F2-45X
TO ANALOG
(CN204)
CN111
QGF0517F2-20X
TO OPE. UNIT
ONNECTOR
ONS".
y10492001a_rev0
DE F G
2-6
T
A
A
T
DIGITAL(SUB CPU) SCHEMATIC DIAGRAM
LIT_3V
TO CN105
5
TO CN111
TO CN105, 108
BATT_L
ADP_L
AL_3.3V
REG_3.1V
SJIG_RST
GND
L1001
10µ
C1037
C1001
6.3V
10/
C1002
10/
6.3V VSS
0.1
L1002
IC1003
10µ
C1003
0.1
IC1002
IC-PST3423U-X
100K
R1001
C1004
0.1
RS5C314-X
CLKCSXin
SIO
INTR
VDD
X1002
NAX0491-001X
Xout
C1005
8p
IC1004
SN74LV32ADGV-X
C1008
0.01
R1002
150K
Q1001
2SC4617/QR/-X
UN9212J-X
4
TO CN105
TO CN111
TO DIGI IF
(TL104)
3
TO CN108
TO CN105
TO CN111
2
TO CN110
TO P.PRCS
TO CN105
TO MEMORY
TG V.DR
TO NUDORE
BUZZER
VOIC_LED
STIL_LED
VIDE_LED
CHRG_LED
ACES_LED
TALY_LED
REG_DATA
REG_CLK
POFF_SW
LCD_OPEN
SCPU_SI
SCPU_SCK
SCPU_SO
REG_CS
FLSH_RST
DSP_RST
VPP
100K
100K
R1051
R1050
R1052
1K
R1053
1K
R1054
100K
100K
R1055
C1018
R1005
R1006
4.7K
0.1
10K
C1019
0.1
DTC124EE-X
PDTC124EE-X
Q1002
SN74LV86ADGV-X
IC1006
C1020
R1003
2.7K
R1004
D1001
18K
DA221-X
C1006
1
47K
R1007
R1039
470
R1025
470
R1015
470
R1008
2.2K
R1049
470
V_BAT
10K
R1027
C1007
C1010
R1048
2.2K
NAX0647-001X
X1001
R1011
100K
0.01
C1021
0.1
C1011
0.01
C1012
0.01
C1013
0.01
C1014
0.01
C1015
0.01
C1016
0.01
C1017
0.01
T_BAT
I_MTR
KEY_C
VPP
AVDD
VDD
OSC2
OSC1
VSS
XI
XO
MMOD
RESET
REG_D
RTC_D
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
2-7
A
BCD
IC1004
SN74LV32ADGV-X
C1008
0.01
R1028
IC1007
MB90097PFV155-X
SCLK
HD
CS
VD
DATA
VC0
RST
1K
0.1
C1036
VDD
SDR
BLKA
XD
EXD
BLKB
TEST
TST0
VSS BLKC
VC1
VC2
VC3
OSD_HD
OSD_VD
VC0
VC1
VC2
BLKA
VC3
BLKB
BLKC
DOT_CLK
TO V I/O
V_BATT
T_BATT
I_MTR
KEY_C
VPP
AVDD
VDD
OSC2
OSC1
VSS
XI
XO
MMOD
RESET
REG_DATA
RTC_DATAIN
KEY_B
KEY_A
AVSS
ZOOM_SW
REG_CLK
SUB_CPU_SO
TALLY
CHRG_LED
MN101C77CJC
SUB_CPU_SI
SUB_CPU_SCK
REG_CS
FLSH_RST
STILLLED
VIDEOLED
ACCESS_LED
IC1001
RTC_CS
DSP_RST
OSD_CS
A_MUTE
VOICELED
P_DET
CF_SLOT
AUDIO_CLK
AUDIO_DATA
DC_CHEK
CHRG_WKUP
BZ_ENV
BZ_FREQ
CHRG_EVR
LCD_OPEN_SW
SUB_CPU_CS
REMOTE
OSD_VD
HP_DET
AUEE_CTL
SD_SLOT
L_MUTE
LCD_RVS_SW
PLAY_SW
POFF_SW
REC_SW
MODE_SW
PD_L
AUDIO_CS
JIG_CLK
JIG_DATA
KEY_WKUP
SYSTEM_SIG
R1046
R1030
A_MUTE
CHRG_EVR
100K
R1058
R1042
1K
R1043
1K
2.2K
100K
2.2K
R1020
R1033
R1012
R1017
1K
1K
TL1002
100K
R1044
IC1005
SN74AHC2G53T-X
R1041
R1038
R1036
1K
TL1001
1K
1K
100k
R1018
100k
R1016
R1060
47K
P_DET
AUEE_CTL
HP_DET
CF_SLOT
L_MUTE
LCD_RVS
PLAY_SW
REC_SW
MODE_SW
SJIG_RX
SJIG_TX
AUD_CLK
AUD_DATA
PD_L
AUDIO_CS
MD_THRMO
TO CN105
TO CN105
TO CN111
TO CN105
TO CN110
TO CN111
TO CN108
TO CN105
TO CN106
R1059
470K
R1031
R1024
1K
DIGITAL(SUB CPU
10
C1038
R1021
R1022
R1023
R1013
0.01
1K
1K
1K
1K
KEY_B
KEY_A
ZOOM_SW
KEY_C
I_MTR
T_BATT
V_BATT
DC_CHEK
SCPU_CS
TO CN111
TO CN105
TO CN105
TO P.PRCS
)
ONS".
y20337001a_rev0
DE F G
2-8
DIGITAL(MPEG2) SCHEMATIC DIAGRAM
R3043
VO0
VO1
VO2
VO3
VO4
VO5
VO6
VO7
VOCLK
nVOEN
VOHSYNC
VOVSYNC
0
IC3002
R3048
C3018
R3045
R3044
100
CLK27B
TO CN105
MPEG_RST
TO NUCORE
PLLSTOP
5
REG_1.5V
REG_2.5V
TO REG
REG_3.1V
MPGFLD
MPGHSYNC
MPGVSYNC
DV2CKOUT
DV1IN0
DV1IN1
DV1IN2
DV1IN3
DV1IN4
DV1IN5
DV1IN6
DV1IN7
DV1CLKIN
nVOEN
DV1INH
DV1INV
GND
MPGFLD
MPGHSYNC
MPGVSYNC
VI0
VI0
VI1
VI1
VI2
VI2
VI3
VI3
VI4
VI4
VI5
VI5
VI6
VI6
VI7
VI7
#
R3049
#
R3050
#
R3051
#
R3052
#
R3053
#
R3054
#
R3055
#
R3056
#
R3057
R3058
R3059
4
TO V I/O
TO V I/O
NUCORE
3
TO NUCORE
L3001
NQR0129-002X
L3002
NQR0129-002X
L3006
L3003
NQR0129-002X
L3004
NQR0129-002X
C3001
C3003
T
C3004
T
L3005
NQR0006-001X
4.7k
47k
R3037
R3036
NDI/JTDI
NDO/JTDO
OPEN
R3042
R3035 R3034
4.7k 4.7k
R3033 R3041
NMOD/JTMS
NCLK/JTCLK
nNRST/nJTRST
JMOD
OPEN
4.7k
PWM
STCLK
PSTOP
PCICLK
C3017
C3016
C3015
C3014
C3013
C3012
VDD1
C3011
0.1
0.1
0.1
10k
10k
4.7k
VDD1
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
R3040
VDD3
VDD3
IC3001
UPD61152F1-A03
GPIO5
R3039
GPIO4
GPIO3
GPIO2
GPIO1
R3038
GPIO0
0.1
0.1
0.1
0.1
C3002
T
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDR
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PVDD
PVDD
PGND
PGND
CSCLK
CSDI
CSDO
VDD1
0.1
C3006
0.1
C3007
T
0.1
C3008
0.1
C3009
C3005
C3010
0.1
T
10
/6.3
R3001
10k
R3002
10k
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
VIHSYNC
VIVSYNC
VICLK
VO0
VO1
VO2
VO3
VO4
VO5
VO6
VO7
VOCLK
nVOEN
VOHSYNC
VOVSYNC
AILRCK
AIBCK
AIBD
AIOLRCK
AIOBCK
AIOBD
ATX
AIMCLK
AOMCLK
R3010
SIREQ
R3008
0
R3011
10k
10k
2
VI0
VI1
VI2
VI3
VI4
AIBD
AIOLRCK
TO CN105
AIOBCK
AOBD
AOMCLK
1
TO DIGI IF
(TL101)
S_PDIF
VIFLD/VIVLD
0
0
R3012
VI5
VI6
VI7
MPGHSYNC
VO0
VO1
VO2
VO3
VO4
VO5
MPGVSYNC
MPGFLD
VO6
R3013
VO7
VOCLK
nVOEN
VOHSYNC
VOVSYNC
10k
10k
R3003
R3004
R3009
10k
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
2-9
A
BCD
SISYNC
SIVLD
SICLK/SISTB
SI0
SI1
SI2
SI3
SI4
SI5
SI6
#
R3036
47k
OPEN
R3042
4.7k 4.7k
R3035 R3034
R3033 R3041
NMOD/JTMS
NCLK/JTCLK
nNRST/nJTRST
SIVLD
SI0
SI1
JMOD
SI2
0
nCINT
nCACK
nCREQ
nPMWAIT
nPMOE
nPMWE
nPMCS0
PMD15
PMD14
PMD13
PMD12
PMD11
PMD10
PMD9
PMD8
PMD7
PMD6
PMD5
PMD4
PMD3
PMD2
PMD1
PMD0
PMA15
PMA14
PMA13
PMA12
PMA11
PMA10
PMA9
PMA8
PMA7
PMA6
PMA5
PMA4
PMA3
PMA2
PMA1
PMA0
TO NUCORE
TO P.PRCS
TO NUCORE, P.PRCS
TO NUCORE,
MEMORY, P.PRCS
TO NUCORE
TO
NUCORE
MEMORY
P.PRCS
TO
NUCORE
P.PRCS
TO
NUCORE
MEMORY
P.PRCS
TO NUCORE, P.PRCS
R3024
OPEN
4.7k
10k
10k
10k
R3032
R3031
R3030
PWM
nGNT
nREQ
nPME
IDSEL
SI7
nSOREQ nCLKRUN
SOCLK/SOSTB
SOSYNC
SOVLD/SORDY
nCBE3
SO0
PSTOP
SI3
STCLK
PCICLK
SI4
SI5
SI6
R3029
10k
nCBE2
SO1
R3028
10k
nCBE1
SO2
R3027
10k
nCBE0
SO3
10k
R3026
nRESET
SO4
10k
10k
R3020
R3021
CB16
nCINT
nCACK1
SO5
SO6
SO7
10k
R3014
R3022
nCREQ1
nSOEN
R3023
nCACK0
MA0
nCREQ0
MA1
nCWAIT
MA2
nCRE
MA3
nCWE
MA4
4.7k
R3025
nCCS
MA5
CD11
CD12
CD13
CD14
CD15
MA6
CD9
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
CA15
CA14
CA13
CA12
CA11
CA10
CA9
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
HMODE2
HMODE1
HMODE0
MDQM
nMWE
nMCAS
nMRAS
nMCS
MCLKE
R3015
MCLK
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MA13
MA12
MA7
MA8
MA9
MA10
MA11 CD10
C3019
MDQM
nMWE
nMCAS
nMRAS
nMCS
MMCLKE
22
MMCLK
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MA13
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
C3312
0.1
C3318
0.1
T
MD0
TL3301
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MDQM
TL3302
nMWE
TL3303
nMCAS
TL3304
nMRAS
TL3305
nMCS
TL3306
MA13
MA12
TL3307
MA10
TL3308
MA0
MA1
MA2
MA3
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23 MD24
MDQM
C3321
0.1
C3311
/6.3
10
R3016
R3017
R3018
R3019
IC3301
K4S283233F-HN75
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQM0
WE_
CAS_
RAS_
CS_
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD VSS
VDD
DQ16
VDDQ
DQ17
DQ18
VSSQ
DQ19
DQ20
VDDQ
DQ21
DQ22
VSSQ
DQ23
VDDQ
DQM2
NC
NC
VDDQ
IC3301
0Ω
DQ31
VSSQ
DQ30
DQ29
VDDQ
DQ28
DQ27
VSSQ
DQ26
DQ25
VDDQ
DQ24
VSSQ
DQM3
VSSQ
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
VDDQ
DQM1
2.2k
VSS
MD15
MD14
MD13
MD12
MD11
MD10
MD9
DQ9
DQ8
VSS
NC
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
NC
NC
MD8
MDQM
MMCLKE
MA11
MA9
MA8
MA7
MA6
MA5
MA4
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MDQM
R3301
0
C3316
0.1
C3322
0.1
MMCLK
# EXCHANGE PARTS LIST
GZ-MC200**
GZ-MC100**
R3012
R3013 R3048 R3049 R3050 R3051 R3052 R3053 R3054 R3055 R3056 R3057
0
1000100
0
100
10001000100010001000100010001000100
0
L3302
L3301
NQR0129-002X
DIGITAL(MPEG2
10
)
ONS".
y10483001a_rev0
DE F G
2-10
C
C
C
V
B
O
A
R
1
1
V
S
O
A
C
DIGITAL(V I/O) SCHEMATIC DIAGRAM
DIGITAL(V I/O
10
)
5
DV2OUT0
DV2OUT1
DV2OUT2
TO MPEG2
NUDORE
TO MPEG2
TO P.PRCS
TO P.PRCS
LCD DRV
TO P.PRCS
DV2OUT3
DV2OUT4
DV2OUT5
DV2OUT6
DV2OUT7
DV2CKOUT
MPGHSYNC
MPGVSYNC
MPGFLD
OUTV2
VIF_IN
VIF_OUT
VIF_CLK
VENC_CS
VENC_RST
OSD_HD
OSD_VD
DOT_CLK
R3239
R3215
0
C3238
R3231
R3232
R3233
R3234
R3235
R3236
R3237
R3238
R3216
R3207
R3209
0
0
0
0
0
0
0
0
0
0Ω
R3217
TL3203
TL3204
OPEN
C3206
C3207
R3218
R3201
0.1
47k
0.01
100
IC3202
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
VC0
VC1
VC2
VC3
BLKA
BLKB
BLKC
R3213
R3214
0
0
C3236 C3233
0.1
YSI7
YSI6
YSI5
VSSQ
VCCQ
VDD(I/O)
NC
NC
VSS
RST
CS00
CS01
CS02
CS03
YS00
YS01
YS02
YS03
VDD(I/O)
OUTH
OUTV
OUTH2
OUTV2
ZCNT
SDOUT
VDD(CORE)
VSS
CLK
SDIN
SCLK
CS
VC0
VC1
VC2
VC3
BLK1
BLK2
BLK3
HDOUT
VDOUT
CLKOSD
HDCVF
VDCVF
VSS
NC
NC
NC
VDD(I/O)
CSYNC
SCANMODE
SCANEN
ADDATEST
VCC
C3201
10
/6.3
C3202
1
T
TL3202
0.1
C3209
YSI4
IPTEST
YSI3
VCCQ
VDD(I/O)
HRP1
YSI2
HRP2
0.01
C3211
C3234
YSI1
VSSQ
VDD( CORE)
VDD(CORE)
WYSI0
WYSI1
0.01
0.1
VSS
VSS
VCC
YSI0
VDD(I/O)
WYSI2
WYSI3
MONI1
MONI2
VDD(CORE)
OPEN
R3210
INV
VDD(CORE)
IC3201
JCP8075
VSS
WCLK
INH
WCSI0
CSI7
WCSI1
CSI6
WCSI2
VSSQ
WCSI3
C3230
CSI5
WINV
0.01
VSS
VDD(CORE)
WINH
SDR_ONH
0.1
C3213
CSI4
VDD(I/O)
VCCQ
VDD( I/O)
VSS
VDD(CORE)
0.01
C3214
CSI3
RESVD
CSI2
RESHD
VSSQ
AMUTE
CSI1
SCANI1
C3227
CSI0
SCANI2
0.1
VCCQ
VSS
NCNCNCNCNC
VSS
VDD
VDD
VSS
I
Y
C
Y
VSS(
VDD(
VSS
VDD
I
C
C
C
VDD
VSS
S
VDD(
NCNCNCNCNC
TO NUDORE
4
3
TO SUB CPU
2
L3201
NQR0129-002X
L3205
10µ
L3203
0
L3202
0
C3244
1
C3203
C3208
10
L3204
0
/6.3
T
C3204 C3205
TT
TO REG
REG_2.5V
REG_3.1V
IC3203
MM1612FN-X
C3240
C3241
GND
1
C3242
0.01
1
IC3204
MM1611JN-X
C3243
0.01
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
2-11
A
BCD
C3227
SCANI2 CSI0
0.1
VCCQ
VSS
NCNCNCNCNC
VSS(8AD)
VDD(8AD)
VDD(8AD)
VSS(8AD)
CLPY
IREF1
YCOUT
ABAR1
COMP1
YSOUT
VREF1
VSS(10DA)
VDD(10DA)
VSS(8DA)
VDD(8DA)
IREF2
CROUT
ABAR2
COMP2
CBOUT
VREF2
COUT
VDD(8DA)
VSS(8DA)
SCANI3
VDD(CORE)
NCNCNCNCNC
VIOYSOUT
TO V OUT
VIOCOUT
NC
NC
VSS
CIN
VRH
VRL
VRM
VYIN
NC
NC
NC
NC
NC
NC
NC
C3226
C3225
C3224
C3223
C3222
R3205
C3221
C3220
C3219
C3218
R3204
C3217
C3216
C3215
R3202 R3203
18k 12k
0.1
0.1
0.1
0.1
0.1
R3221
R3222
270
R3224
300
3.3k
Q3201
EMT1-W
R3223
3.3k
Q3201
820
1.0
0.1
0.1
0.1
820
1.0
0.1
0.01
VDCVF
HDCVF
LCD_R
TO LCD DRV
LCD_G
LCD_B
C3210
0.01
R3226
130
Q3203
EMT1-W
R3228
4.7k
R3225
4.7k
Q3202
2SA2029/QRS/-X
R3227
4.7k
R3229R3230
130130
ONS".
y10485001a_rev0
DE F G
2-12
DIGITAL(V OUT) SCHEMATIC DIAGRAM
5
TO REG
4
TO V I/O
REG_4.8V
GND
VIOYSOUT
VIOCOUT
L3701
10µ
C3701
/6.3
10
T
C3708
C3709
1
0.1
3
C3710
0.01
2
TO OP DRV
ASPECT_S
TO
P.PRCS
ANA_IN_H
PS_CTL
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
2-13
A
BCD
10
DIGITAL(V OUT)
R3709
0
IC3701
BH7612FV-X
C3702
100
C3704
100
/4
T
/4
T
C3706
0.01
C3703
22
/4
C3705
22
/4
R3703
68
R3701
68
R3702
68
TO CN105
Y_OUT
V_OUT
C_OUT
C3707
D3701
R3704
10k
Q3702
Q3703
y30295001a_rev0
ONS".
R3708
0
R3705
1Ω
Q3701
EMZ1-W
R3707
100k
R3706
82k
DE F G
2-14
C
8
1
DIGITAL(NUCORE) SCHEMATIC DIAGRAM
SDR_DQ9
SDR_DQ10
SDR_DQ9
SDR_DQ8
SDR_DQ7
SDR_DQ8
SDR_DQ7
SDR_DQ6
SDR_DQ6
SDR_DQ5
TO MEMORY
SDR_DQ3
SDR_DQ4
SDR_DQ5
SDR_DQ4
SDR_DQ3
SDR_DQ2
SDR_DQ2
SDR_DQ1
SDR_DQ1
SDR_DQ0
SDR_DQM3
SDR_DQ0
SDR_DQM3
SDR_DQM1
SDR_DQM2
SDR_DQM2
SDR_DQM1
SDR_WE
SDR_DQM0
SDR_DQM0
SDR_WE
SDR_CAS
SDR_CAS
SDR_RAS
SDR_CS0
SDR_RAS
SDR_CS0
SDR_BA1
SDR_BA1
SDR_BA0
SDR_BA0
SDR_CKE
SDR_CKE
SDR_CLK
SDR_CLK
SDR_A10
SDR_A10
SDR_A9
SDR_A9
SDR_A8
SDR_A8
SDR_A7
SDR_A7
SDR_A6
SDR_A6
SDR_A5
SDR_A5
SDR_A4
SDR_A4
SDR_A3
SDR_A3
SDR_A2
SDR_A2
SDR_A1
SDR_A1
SDR_A0
SDR A0
TO P.PRCS
TO MPEG2
nCINT
PMINT
ID_LAT
TO CN108
MOD0
VDCPU
TO P.PRCS
PPRO0
PPRO1
PPRO2
PPRO3
PPRO4
PPRO5
PPRO6
PPRO7
PPRO8
PPRO9
PPRO10
PPRO11
VCLK
VLD_PIX
SOF
SDR_DQ31
SDR_DQ30
SDR_DQ31
SDR_DQ30
SDR_DQ28
SDR_DQ29
SDR_DQ29
SDR_DQ28
SDR_DQ26
SDR_DQ27
SDR_DQ27
SDR_DQ26
SDR_DQ25
SDR_DQ25
SDR_DQ24
SDR_DQ23
SDR_DQ24
SDR_DQ23
SDR_DQ22
SDR_DQ21
SDR_DQ22
SDR_DQ21
SDR_DQ20
SDR_DQ19
SDR_DQ20
SDR_DQ19
SDR_DQ18
SDR_DQ18
SDR_DQ17
SDR_DQ16
SDR_DQ17
SDR_DQ16
SDR_DQ15
SDR_DQ14
SDR_DQ15
SDR_DQ14
SDR_DQ13
SDR_DQ12
SDR_DQ13
SDR_DQ12
SDR_DQ11
SDR_DQ11
SDR_DQ10
5
R4081
47k
10k
0603
R4058
R4061
47k
0Ω
R4062
TO CN106
PWR_CHEK
PLLSTOP
SSGFLD
MPEG_RST
CFWP
nCFWE
nCFWAIT
CFRESET
nCFREG
CFRDY
nCFOE
nCFIOWR
nCFIORD
CFCSEL
CFD0
CFD1
CFD2
CFD3
CFD4
CFD5
CFD6
CFD7
CFD8
CFD9
CFD10
CFD11
CFD12
CFD13
CFD14
CFD15
nCFCE0
nCFCE1
nCFCD1
nCFCD2
CFBVD1
CFBVD2
CFA0
CFA1
CFA2
CFA3
CFA4
CFA5
CFA6
CFA7
CFA8
CFA9
CFA10
NDPWM
STRB_EVR
R4063
R4064
R4065
R4066
R4101
R4102
R4103
R4104
R4105
R4106
R4107
RA4007
RA4008
RA4009
RA4010
R4110
R4111
R4112
RA4011
RA4012
RA4013
TO CN105
TO MPEG2
TO P.PRCS
TO MPEG2
4
3
TO OP DRV
TO CN103
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
TL4015
TL4016
GPIO7
0Ω
GPIO26
0Ω
GPIO28
0Ω
GPIO25
GPIO27
0Ω
GPIO29
0Ω
CFWP
0Ω
nCFWE
0Ω
nCFWAIT
0Ω
CFRESET
0Ω
nCFREG
0Ω
CFRDY
0Ω
nCFOE
nCFIOWR
nCFIORD
CFCSEL
CFD0
CFD1
CFD2
CFD3
CFD4
CFD5
CFD6
CFD7
CFD8
CFD9
CFD10
CFD11
CFD12
CFD13
CFD14
CFD15
nCFCE0
0Ω
nCFCE1
nCFCD1
0Ω
nCFCD2
CFBVD1
CFBVD2
CFA0
CFA1
CFA2
CFA3
CFA4
CFA5
CFA6
CFA7
CFA8
CFA9
CFA10
PWM0
PWM1
PWM2
PWM3
GPIO5
GPIO4
GPIO3
GPIO2
GPIO6
AFESOF
AFEVPIX
3CCDCLK
AFECLK
AFED11
AFED10
AFED9
AFED8
AFED7
AFED6
AFED5
AFED4
AFED3
AFED2
AFED1
SDR_CKE
AFED0
SDR_DQ31
MCKE
SDRAM_D31
SDR_DQ29
SDR_DQ30
SDRAM_D29
SDRAM_D30
SDR_DQ27
SDR_DQ28
SDRAM_D27
SDRAM_D28
SDR_DQ25
SDR_DQ26
SDRAM_D25
SDRAM_D26
SDR_DQ23
SDR_DQ24
SDRAM_D23
SDRAM_D24
SDR_DQ21
SDR_DQ22
SDRAM_D22
SDR_DQ19
SDR_DQ20
SDRAM_D19
SDRAM_D20
SDRAM_D21
SDR_DQ17
SDR_DQ18
SDRAM_D18
SDR_DQ16
SDRAM_D16
SDRAM_D17
SDR_DQ14
SDR_DQ15
SDRAM_D14
SDRAM_D15
SDR_DQ12
SDR_DQ13
SDRAM_D12
SDRAM_D13
SDR_DQ10
SDR_DQ11
SDRAM_D10
SDRAM_D11
SDR_DQ9
SDRAM_D9
SDR_DQ7
SDR_DQ8
SDRAM_D8
SDR_DQ6
SDRAM_D6
SDRAM_D7
SDR_DQ4
SDR_DQ5
SDRAM_D5
SDR_DQ2
SDR_DQ3
SDRAM_D3
SDRAM_D4
SDRAM_D2
SDR_DQ0
SDR_DQ1
SDRAM_D1
SDR_DQM2
SDR_DQM3
DQM3
SDRAM_D0
SDR_DQM1
DQM1
DQM2
SDR_WE
SDR_DQM0
nMWE
DQM0
SDR_RAS
SDR_CAS
nCAS
SDR_CS0
nRAS
nMCS0
SDR_BA1
SDR_BA0
SDRAMBS1
SDR_CLK
R4055
33
R4056
SDRAMBS0
SDRAMCLKR
SDR_A11
SDR_A12
SDRAMCLK
SDRAM_A12
SDR_A9
SDR_A10
SDRAM_A10
SDRAM_A11
SDR_A8
SDRAM_A8
SDRAM_A9
SDR_A6
SDR_A7
SDRAM_A7
SDRAM A6USBPHYCLK
I
SIP12
GPIO31
TL4017
R4068
NC3
47k
NC4
R4001
GPIO39
MCLKINNCAMBACLKIN
0Ω
nRESET
nRESETPERH
TL4001
3.3k
R4005
DSP_RST
AFE_RST
TO P.PRCS
TO SUB CPU
SCANE
47k
47k
R4009
R4010
0Ω
R4006
R4008
nJRESET
TO CN108
TESTSCAN
TRACESYNC
TRACECLK
DBGRQ
DBQACK
PMA0
TL4002
OPEN
PMA0
TO MPEG2, P.PRCS
nPMCS7
nPMCS1
nPMCS0
nPMWE
nPMOE
nPMBLS0
nPMBLS1
nPMWAIT
nARMTRST
TCK
TMS
TDI
0Ω0Ω0Ω0Ω0Ω0Ω0Ω0Ω0Ω
R4019
R4018
ARMTCK
ARMTMS
nPMBLS1
nPMWAIT
nARMTRST
TO CN108
TO MPEG2, P.PRCS
47k6847k
R4020
ARMTDI
AMBATDO
SIO0
TL4026
R4021
R4069
1k
R4007
ARMTDO
GPIO24
SIO1
TL4027
47k
R4022
10k
0Ω
R4023
nVOEN
TO MPEG2
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
PMA18
PMA19
PMA20
PMA21
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
R4017
R4016
R4015
R4014
R4013
R4012
R4011
TL4003
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
P.PRCS
MEMORY
TO MPEG2
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMA16
PMA17
MEMORY
TO MPEG2
PMA20
PMA19
PMA18
TO MEMORY
PMA21
PMD2
PMD1
PMD0
PMD9
PMD8
PMD7
PMD6
PMD5
PMD4
PMD3
P.PRCS
MEMORY
TO MPEG2
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
nPMWE
nPMCS0
nPMCS1
nPMCS7
TO MPEG2
TO MPEG2
TO P.PRCS
TO MEMORY
nPMOE
nPMBLS0
TO P.PRCS
PMA2
PMA1
MEMORY, P.PRCS
TO CN105
ACPLLOFF
2
TO CN105
CLK27A
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
2-15
A
BCD
DMASREQ
DMABREQ
0Ω
R4024
DMABREQ
DMASREQ
TO P.PRCS
DMACLR
NQR006-001X
47k
R4025
DMACLR
L4010
/6.3
C4045
10
R4029
L4007
NQR0006-001X
L4011
T
X4001
NAX0710-00
C4043
0Ω
R4028
0Ω
0.1
SDR_A8
_
SDRAM_A8DMACLR
DMACLR
SDR_A7
SDR_A6
SDR_A7
SDR_A6
L4010
NQR006-001X
47k
R4025
L4007
NQR0006-001X
SDR_A5
SDR_A5
/6.3
C4045
10
SDR_A4
SDR_A4
SDR_A3
L4011
T
R4029
NAX0710-001X
C4043
SDR_A3
SDR_A2
SDR_A1
SDR_A0
SDR_A11
SDR_A2
SDR_A1
SDR_A0_SDR_A12
SDR_A11
SDR_A5
SDR_A6
SDR_A7
SDRAM_A7
SDRAM_A6
SDRAM_A5
IC4001
SIP1280ISD-DVA2
USBPHYCLK
USBVSS
0Ω
R4028
0Ω
X4001
0.1
SDR_A12
SDR_A3
SDR_A4
SDRAM_A4
USBVDD
0.1
C4042
R4030
0Ω
SDR_A1
SDR_A2
SDRAM_A3
SDRAM_A2
USBVSS
USBVDD
0.1
C4041
SDR_A0
SDRAM_A1
SDRAM_A0
USBREXT
USBVSS
6.8k
R4031
SDCLK
22
R4054
SD_CLK
USB4XCLK
USBDp
6.8k
R4032
USBDP
SDWP
SDCD
SD_WP
SD_CD
USBDn
USBVDD
C4040
USBDN
nUSB_DET
TO DIGI IF
TO CN113
SDCMD
22
R4053
SD_CMD
USBVSS
0.1
GND
(USB)
SDDAT2
SDDAT3
SD_DAT3
SD_DAT2
GPIO0
GPIO1
nUSBDP_PU
SDDAT0
SDDAT1
DV1INV
SD_DAT0
SD_DAT1
DV1VSYNC
AUDIN/GPIO13
AUDOUT/GPIO12
AUDSYNC/GPIO10
AUDIN
AUDOUT
AUDSYNC
TO CN105
DV1INH
DV1IN6
DV1IN7
DV1CLKIN
DV1UV7
DV1UV6
DV1CLKIN
DV1HSYNC
AUDBITCLK/GPIO9
nAUDRESET/GPIO8
GPIO11
GPIO41
TL4008
0Ω
R4036
AUDBITCLK
nAUDRESET
TO MPEG2
DV1IN3
DV1IN4
DV1IN5
DV1UV5
DV1UV4
DV1UV3
GPIO40
GPIO43
GPIO42
TL4010
TL4011
DV1IN0
DV1IN1
DV1IN2
DV1UV0
DV1UV1
DV1UV2
UART2RXD
UART2TXD
VCLKIN
CLK27A
TG_FLD
FLDCPU
TO P.PRCS
TO P.PRCS
TO TG V.DR
R4050
R4051
R4052
TL4019
VSS43
VSS44
DV1CLKOUT
GPIO32/PHASEERR
GPIO33/nVRESET
47k
R4042
47k
220
R4041
R4040
CN105
47k
47k
VSS39
VSS40
VSS41
VSS42
GPIO34/ZEBRASKIN
GPIO35/CSYNC
GPIO36/HSYNC
GPIO37/VSYNC
47k
R4044
TL4013
VSS38
FSADJp
VSS37
FSADJn
VSS36
TVOUTG
VSS35
TVOUTR
VSS34
TVOUTB
VSS33
TVOUTY
VSS31
VSS32
TVOUTCHR
DV2CLKIN
220
47k
R4046
R4045
TO MPEG2
VSS29
VSS30
DV2CLKOUT
DV2HSYNC
TL4004
DV2CKOUT
V I/O
VSS27
VSS28
DV2VSYNC
DV2UV7
TL4005
DV2OUT7
DIGITAL(NUCORE
10
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
DV2UV6
DV2UV5
DV2UV4
DV2UV3
DV2UV2
DV2UV1
DV2UV0
CVDD1
CVDD2
CVDD3
CVDD4
CVDD5
CVDD6
RA4001
RA4002
220
DV2OUT5
DV2OUT6
220
DV2OUT3
DV2OUT4
DV2OUT2
DV2OUT0
DV2OUT1
0.1 0.1
C4036 C4035
IC4002
SN74AHC1G04DC-X
TO V I/O
VSS10
VSS11
VSS12
CVDD7
CVDD8
CVDD9
CVDD10
C4034 C4033 C4032
C4018
VSS4
VSS5
VSS6
VSS8
VSS9
CVDD11
CVDD12
CVDD13
CVDD14
CVDD15
CVDD16
0.1 0.1 0.1
0.1
R4072
R4071
4.7k
D4002
Q4001
R4070
4.7k
D4003
1SS376-X
VSS3
PLLDVDD2
PLLDVDD1
PLLPVDD
PLLAVDD2
PLLAVDD1
PLLDVSS2
PLLDVSS1
PLLPVSS
PLLAVSS2
PLLAVSS1
CVDD17
NU_RX
VSS2
nMCS3
nMCS2
nMCS1
MVDD11
MVDD10
MVDD9
MVDD8
MVDD7
MVDD6
MVDD5
MVDD4
MVDD3
MVDD2
MVDD1
VDD26
VDD25
VDD24
VDD23
VDD22
VDD21
VDD20
VDD19
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD
VDD10
VDD9
VDD8
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
AVDD5
AVDD4
AVDD3
AVDD2
AVDD1
AVDD0
AVSS10
AVSS9
AVSS8
AVSS7
AVSS6
AVSS5
AVSS4
AVSS3
AVSS2
AVSS1
AVSS0
D4001
2SC5658/QRS/-X
NU_TX
TO CN108
)
L4003
REG_2.5V
0.01
C4021
C4031
C4028
C4030
T
R4033
C4027
C4029
C4006
22
/6.3
C4007
0.1
C4008
0.1
C4009
0.1
C4010
0.1
C4011
0.1
C4012
0.1
C4013
0.1
C4014
0.1
C4015
0.1
C4016
0.1
C4017
0.1
0Ω
0.1
0.1
0.1
0.1
0.1
IC4003
MM1613DN-X
C4019
1
L4001
NQR0129-002X
C4001
T
10
/6.3
L4002
NQR0129-002X
C4002
T
10
/6.3
L4004
C4004
10
L4005
T
C4005
T
10
/6.3
R4049
0Ω
L4006
NQR0448-002X
C4020
1
R4057
0Ω
REG_3.1V
NQR0006-001X
REG_1.2V
GND
REG_4.8V
TO REG
TO REG
ONS".
y10482001a_rev0
DE F G
2-16
2
DIGITAL(CDS) SCHEMATIC DIAGRAM
B5_B
VDD
ACHI2
B2_B
AGND
NC
CLPDM
CLPOB
AGND
CPOB2
CDS_STBY
STB
SHD_B
NC
VCC
B2_A
IC4201
VSP2254GSJ
B0_B
B1_B
B4_B
BCHI2
BCHI5
B5_A
B7_B
BCHI9
B9_A
B9_B
BCHI10
AGND
B10_A
B12_B
AGND
0.1
0.1
0.1
C4226
C4225
C4224
AGND
COB_A
REFN_A
BYPCM_A
COB_BNCBYPCM_B
BYPM_B
4.7
C4206
VCC
AGND
CCDIN_B
CM_B
0.1
C4222
AGND
REFN_B
REFP_B
REFP_A
NC
BYPP_B
AGND
B11_B
B10_B
B6_B
B3_B
SHP_B
VCC
PBLK
DGND
DGND
AGND
B0_A
B1_A
B3_A
B6_A
B8_A
B11_A
B13_A
VCC
BYPM_A
CCDIN_A
CM_A
C42
NC
NC
NC
C421
C421
ACHI13
ACHI8
10
5
4
DIGITAL(CDS
C4202
C4203
C4231
BCHI12
BCHI7
BCHI4
4.7
4.7
1000p
3
)
NC
VCC
NC
NC
VCC
BYPP_A
AGND
B12_A
B7_A
B4_A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SHP_A
ACHI5
VCC
B8_B
B13_B
SHD_ANCADCCK
0.1
0.1
1000p
0.1
0.1
0.1
0.1
0.1
2
C4215
C4214
C4213
C4212
C4211
C4210
ACHI9
C4209
ACHI12
ADCLK
C4208
CPOB
ACHI0
ACHI1
ACHI4
ACHI7
1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked () is not used.
2-17
A
BCD
0.1
C4216
10
C4204
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