JVC GR-DVL500U, GR-DVA11/K, GR-DVL100U, GR-DVF10, GR-DVL505U Technical Manual

VIDEO TECHNICAL GUIDE

COPYRIGHT © 2000 VICTOR COMPANY OF JAPAN, LTD.

No. 86056

September 2000

2000 Basic DVC Models

DIGITAL VIDEO CAMERA

INDEX

INDEX-1

SECTION 1 OUTLINE OF THE PROCUCTS

1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR.............1-1

1.1.1 Comparison table of DV models specification by products year.....................................1-1

1.1.2 Specification of the DVC models....................................................................................1-3

SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT

2.1 CIRCUIT OUTLINE..............................................................................................................2-1

2.1.1 Basic block diagram.......................................................................................................2-1

2.2 CCD (ICX220AK/ICX221BK)................................................................................................2-2

2.2.2 CCD Image Sensor........................................................................................................2-3

2.2.3 Numbers of pixel for main models..................................................................................2-6

2.3 EXPLANATION OF CAMERA CIRCUIT...............................................................................2-7

2.3.1 Present AW / AE control system....................................................................................2-7

2.3.2 AF (Auto Focus) control.................................................................................................2-13

2.3.3 EIS (Electric Image Stabilizer) control............................................................................2-14

2.4 CAMERA SYSREM IC'S FUNCTION...................................................................................2-15

2.4.1 Camera DSP (IC4301: JCY0120) function.....................................................................2-15

2.5 EXPLANATION OF DECK CIRCUIT ....................................................................................2-22

2.5.1 Deck system overall structure........................................................................................2-22

2.5.2 PB equalizer and ATF....................................................................................................2-23

2.5.3 PLL operation................................................................................................................2-24

2.5.4 Basic principle of Viterbi detection .................................................................................2-25

2.5.5 Audio recording mode....................................................................................................2-26

2.5.6 Audio signal processing.................................................................................................2-27

2.5.7 Clock system for audio data...........................................................................................2-28

2.5.8 Deck DSP IC function....................................................................................................2-29

2.5.9 Audio AMP IC function...................................................................................................2-35

2.6 SYSCON CPU.....................................................................................................................2-38

2.6.1 Contents of SYSCON CPU processing..........................................................................2-38

2.6.3 System composition.......................................................................................................2-39

2.6.4 SYSCON CPU block diagram........................................................................................2-40

2.6.5 SYSCON CPU (IC1001: MN1021617HL) pin functions..................................................2-41

2.7 DECK CPU...........................................................................................................................2-44

2.7.1 Contents of DECK CPU processing...............................................................................2-44

2.7.2 DECK system composition.............................................................................................2-44

2.7.3 Tracking Error information..............................................................................................2-45

2.7.4 1394 interface control....................................................................................................2-46

2.7.5 JLIP Video Capture........................................................................................................2-46

2.7.6 DECK CPU block diagram.............................................................................................2-47

2.7.7 Deck CPU (IC1401: MN103004KRH) pin functions........................................................2-48

INDEX-2

SECTION 3 HEAD CLOG WARNING

3.1 HEAD CLOG WARNING OF DVC........................................................................................3-1

3.1.1 Structure of Sync Blocks and Error correction................................................................3-1

3.1.2 Error Rate of DVC..........................................................................................................3-3

3.1.3 Previous method of head clog detection ........................................................................3-4

3.1.4 New method of head clog detection...............................................................................3-5

SECTION 4 DOCTOR SYSTEM

4.1 WHAT IS DOCTOR PROGRAM?.........................................................................................4-1

4.1.1 Matching of Doctor Program with Microcomputer Program............................................4-1

4.1.2 Use of Doctor Program for Camcorder...........................................................................4-2

4.1.3 Revision of Service Support System Software for Doctor Program................................4-2

4.1.4 Procedure to Rewrite Doctor Program...........................................................................4-3

4.2 DOCTOR PROGRAM SYSTEM IN THE PRESENT CIRCUMSTANCES.............................4-5

4.2.1 ON/OFF address and Program address.........................................................................4-5

4.2.2 Writing function of EEPROM data..................................................................................4-7

4.2.3 Upgrade of the service support system..........................................................................4-7

SECTION 1

OUTLINE OF THE PROCUCTS

1-1

1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR

1.1.1 Comparison table of DV models specification by products year (1/2)

Model

Function

Battery BN-V11 Ni-Cd

(6V, 1100 mAh)
BN-V12 Ni-Cd
(6V, 1200 mAh)
BN-V20 Ni-MH
(6V, 2000 mAh)

Continuous shooting tim e:
when VF is used:
BN-V12: 1hr.10min.
BN-V20: 1hr.50min.

when LCD is used:
BN-V12: 1hr.
BN-V20: 1hr.40min.

BN-V207 Lithium-ion
(7.2V, 700 mAh)
BN-V214 Lithium-ion
(7.2V, 1400 mAh)

Continuous shooting tim e:
when VF is used:
BN-V207: 1hr.
BN-V214: 2hrs.20min.
BN-V856: 8hrs.30min.

when LCD is used:
BN-V207: 50min.
BN-V214: 1hr.55min.
BN-V856: 7hrs.

BN-V408 Lithium-ion
(7.2V, 800 mAh)
BN-V416 Lithium-ion
(7.2V, 1600 mAh)
BN-V428 Lithium-ion
(7.2V, 2800 mAh)

Continuous shooting tim e:
when VF is used:
BN-V408: 1hr.15min.
BN-V416: 2hrs.30min.
BN-V428: 4hrs.20min.
BN-V856: 8hrs.40min.

when LCD is used:

Charging the battery Charging time: AA-V15 us ed

70 min. (BN-V11)
70 min. (BN-V12)
110 min. (BN-V20)

Charging time: AA-V20 us ed
90 min. (BN-V207)
180 min. (BN-V214)

Charging time: AA-V40 us ed
90 min. (BN-V408)
120 min. (BN-V416)
200 min. (BN-V428)

Viewfinder Color LCD 0.55" 113k pixels

B/W CRT

Color LCD 0.55" 113k pixels
B/W LCD 0.24" 76k pi xels

Color LCD 0.44" 113k pixels
B/W LCD 0.24" 76k pi xels

LCD monitor Non

2.5" 480 × 234 = 112k pixels
3" 480 × 234 = 112k pixels
Horizontal resolution: 240 lines

Amorphous silicon transistor

2.5" 480 × 234 = 112k pixels
3" 480 × 234 = 112k pixels

3.5" 480 × 234 = 112k pixels
Horizontal resolution: 240 lines
Amorphous silicon transistor

←

Image device 1/4"

Total 766 × 596 = 460k pixels
(*799 × 711 = 540k pixels)
Effective aria 611 × 480 = 290k pixels
(*601 × 576 = 350k pixels)

1/4"
Total 998 × 677 = 680k pixels
(*998 × 797 = 800k pixels)
Effective aria 711 × 485 = 340k pixels
(*702 × 575 = 400k pixels)

←

Horizontal resolution 360 Lines 400 Lines

←

Electric image
stabilizer

Yes

←←

Sensitivity 10 lux (*12 lux)

50 IRE Level, Slow Shutter off

16 lux (*18 lux)
50 IRE Level, Slow Shutter off

18 lux
50 IRE Level, Slow Shutter off

Lens specification F1.6 f = 3.9 to 62.4 mm

←

F1.8 f = 3.6 to 36.0 mm

Tele macro Yes

←←

Zoom ratio

Optical zoom: 16

×

Digital zoom: 4×/10× or 8×/20

×

Max. zoom: 160× or 320

×

←

Optical zoom: 10

×

Digital zoom: 4×/10×,25× or 45

×

Max. zoom: 100× ,250× or 450

×

Snapshot 5 mode

With frame
Full
Pin-up
Pin-up 4-division
Pin-up 9-division

←←

Playback snapshot Yes

←←

Playback digital zoom

Yes 10

×

RM-V712U

Yes 4

×

RM-V711U

Yes 10× or 25

×

RM-V716U

2000 Fusion DV Model1998 Fusion DV Model 1999 Fusion DV Model

Table 1-1-1 Comparison table of DV models specification by products year (1/2)

1-2

••••

Comparison table of DV models specification by products year (2/2)

Model

Function

Slow motion Yes

RM-V712U

Yes (Frame Advance)
RM-V711U (optional: GR-DVF11U)

Yes (Frame Advance)
RM-V716U

Video auto li

g

ht Yes Yes ( /No

)

Yes

Audio 2ch

(

48kHz,16-bit) /4ch(32kHz,12-bit

)

←←

Snapshot search No

←←

Record end search No

←←

Audio dubbing No (Yes:PAL model,32kHz only,RCU

only)

Yes (32kHz only,RCU only)

←

V.insert editin

g

No

←

Yes (SP onl

y)

Time code Yes

←←

Headphone terminal No

←←

AV output terminal RCA

(Video Audio L/R)

←

Ø3.5 mini

S output terminal Yes

←←

JLIP terminal Yes

←←

PC terminal No Yes (No: GR-DVF11U) Yes

(No: GR-DVF10,DVL100U,DVL305U,
DVL307U)

Digital still image output
terminal

No Yes (No: GR-DVF11U) Yes

(No: GR-DVF10,DVL100U,DVL305U,
DVL307U)

DV terminal No Yes (EG/EK Model Output only) Yes

(Output only: GR-DVL100EG/EK,
DVL108EG/EK,DVL200EG/EK,
DVL300EG/EK,DVL308EG/EK)

JLIP related
software

GV-CB3 JLIP video capture box (optional)
JLIP video capture Ver.2.0
JLIP video producer Ver.1.13

Provided CD-ROM or optional HS-V4KIT
(No: GR-DVF11U)
JLIP video capture Ver.3.0
JLIP video producer Ver.1.16

Provided CD-ROM or optional HS-V14KIT
(No: GR-DVF10,DVL100U,DVL305U,
DVL307U)
JLIP video capture Ver.3.1
JLIP video producer Ver.2.0
Picture Navigator (DSC model only)

JLIP ID number 06

←←

Remote control sensor Yes

←←

Button battery
(only for clock backup)

Yes: CR-2025 type Yes: CR-2032 type (built-in)

←

2000 Fusion DV Model1998 Fusion DV Model 1999 Fusion DV Model

Table 1-1-1 Comparison table of DV models specification by products year (2/2)

1-3

1.1.2 Specification of the DVC models

MODEL

SIGNAL

FORMAT

CCD VF

LDC

MONIDVTERMINAL

DIGITAL

STILL

OUTPUT

DSC MMC

DIGITAL

ZOOM

GR-DVF10 NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 X
GR-DVA10 NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES - - 100 X
GR-DVA11/K NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES DSC

MMC

100 X
GR-DVL100U NTSC 1/4" 680K B/W 2.5 INCH IN/OUT - - - 250 X
GR-DVL300U NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 X
GR-DVL305U NTSC 1/4" 680K COLOR 2.5 INCH IN/OUT - - - 250 X
GR-DVL307U NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 X
GR-DVL500U NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES - - 250 X
GR-DVL505U NTSC 1/4" 680K B/W 3.0 INCH IN/OUT YES DSC - 250 X
GR-DVL507U NTSC 1/4" 680K B/W 3.5 INCH IN/OUT YES - - 250 X
GR-DVL805U NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 X
GR-DVL300UM NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 X
GR-DVL505UM NTSC 1/4" 680K B/W 3.0 INCH IN/OUT YES DSC - 250 X
GR-DVL805UM NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 X
GR-DVL300KR NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 X
GR-DVL805KR NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 X
GR-DVL100EG PAL 1/4" 800K B/W 2.5 INCH OUT

∗

OPTION

- - 100 X
GR-DVL107EG PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 100 X
GR-DVL108EG PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC

MMC

100 X

GR-DVL109EG PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES DSC

MMC

100 X
GR-DVL200EG PAL 1/4" 800K B/W 3.0 INCH OUT YES DSC - 100 X
GR-DVL300EG PAL 1/4" 800K COLOR 3.5 INCH OUT YES - - 100 X
GR-DVL307EG PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES - - 100 X
GR-DVL308EG PAL 1/4" 800K COLOR 3.5 INCH OUT YES DSC

MMC

100 X
GR-DVL309EG PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC

MMC

100 X
GR-DVL100EK PAL 1/4" 800K B/W 2.5 INCH OUT

∗

OPTION

- - 100 X

GR-DVL107EK PAL 1/4" 800K B/W 2.5 INCH IN/OUT

∗

OPTION

- - 100 X

GR-DVL108EK PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC

MMC

100 X
GR-DVL109EK PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES DSC

MMC

100 X
GR-DVL200EK PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC - 100 X
GR-DVL300EK PAL 1/4" 800K COLOR 3.5 INCH OUT YES - - 100 X
GR-DVL308EK PAL 1/4" 800K COLOR 3.5 INCH OUT YES DSC

MMC

100 X
GR-DVL105A PAL 1/4" 800K B/W 2.5 INCH IN/OUT

∗

OPTION

- - 450 X
GR-DVL300A PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 X
GR-DVL800A PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 X
GR-DVL105A-S PAL 1/4" 800K B/W 2.5 INCH IN/OUT

∗

OPTION

- - 450 X
GR-DVL300A-S PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 X
GR-DVL800A-S PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 X
GR-DVL100EA PAL 1/4" 800K B/W 2.5 INCH IN/OUT

∗

OPTION

- - 450 X
GR-DVL300EA PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES - - 450 X
GR-DVL300ED PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 X
GR-DVL400ED PAL 1/4" 800K B/W 3.0 INCH IN/OUT YES - - 450 X
GR-DVL500ED PAL 1/4" 800K COLOR 3.0 INCH IN/OUT YES - - 450 X
GR-DVL600ED PAL 1/4" 800K B/W 3.5 INCH IN/OUT YES - - 450 X
GR-DVL707ED PAL 1/4" 800K B/W 3.5 INCH IN/OUT YES DSC - 450 X
GR-DVL800ED PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 X

CC9370 NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 X

∗

OPTION: HS-V14KITE (CD-ROM and Cables)

Table 1-1-2 Specification of the DVC models

SECTION 2

EXPLANATION OF ELECTRICAL CIRCUIT

2-1

2.1 CIRCUIT OUTLINE

2.1.1 Basic block diagram

CCD

IC4301

CAMERA_DSP

IC4302

FIELD

MEMORY

TMY(8)
TMC(4)

TG

V.DRV

IC5501

FOCUS
DRIVER

&

ZOOM

DRIVER

IC4851

IRIS

DRIVER

&
HALL
AMP

IC4802-IC4805

SYSCON

CPU

IC1001

DYO(4),DCO(4)

BUS(16)

IRIS_O/C

DATA_OUT

IC3001

DECK_DSP

IC3002

16M

DRAM

IC3501

REC AMP

&

PB AMP

IC1401

DECK

CPU

IC3201

DVEQ

IC3301

DVANA

HSE

AUDIO

AMP

IC2201

RD(16)
RA(10)

MIC UNIT

INT_MIC / L

INT_MIC / R

A_OUT / R

A_OUT / L

MAIN

10

FMY(8)
FMC(4)

H1, H2, RG

XAVD, XAHD

IC1003

E2PROM

IC1004

RTC

32kHz

X1002

ANA_IO

S_DT_IN

AD(16)

S_DT_IN

S_DT_OUT

ON

SCREEN

IC1002

DRIVE+,-

FOCUS (4)

ZOOM (4)

IC1601

MDA

M

M

M

CAPSTAN

MOTOR

DRUM

MOTOR

LOADING

MOTOR

VIDEO
HEAD

IRIS PWM

AIDAT

DODAT

AIDAT

DODAT

MDA_IN

ATF_GAIN, M_VCOCTL, PBVCOCTL, FSPLLCTL

DV_C

LCD_R-Y

DATA_OUT

CLK27,CLK18,CLK13

OPTICAL

BLOCK

CCD_OUT

CDS/AGC

A/D

IC4201

CAM_AD(10)

54MHz
X5501

1394PHY

IC3101

TPA+,TPA­TPB+,TPB-

DATA_OUT

SUB

S_DT_OUT

LOAD_FWD
LOAD_REV

V1,V2,V3,V4

PD(4)

DYI(4),DCI(4)

HSE

PBDATA

ADDT(16)

ADDT(16)

ADDT(16)

ANA_IO

SPK+,SPK-

SP

PB_ENV

PB_ENV

IRIS PWM

RECC_ADJ

RECC_ADJ

H_GAIN,H_OFFSET

H_GAIN,H_OFFSET

MDA_IN

CCD

40

JUNCTION50

D_COIL_U
D_COIL_V
D_COIL_W

C_COIL_U
C_COIL_V
C_COIL_W

1F
1S
2F
2S

PBO

ATFO

IC5001

DATA_OUT

LCD

DRIVER

IC7601

MONI

LCD

R
G
B

SW

IC7604

VF

LCD

R
G
B

MONITOR20

LCD

DRIVER

IC7101

VF

LCD

EEP

ROM

RXD

TXD

SRV_TX

IF_RX

IC8001

DSC_IF

M32_R/D

CPU

IC8002

IC8003

16Mb
FLASH

DSC

01

REAR70

PC

RX

GND

J552

TX

JLIP

RX
TX

GND

EDIT

J553

IC1302

IC1014

IF_RX

IF_TX

TXD
RXD

EDIT_CTL

JLIP_L

M32_DTIN

PC_RX

PC_TX

JLIP_RX

JLIP_TX

32D(16)
32A(25) 32A(19)

JACK60

ATF_GAIN, M_VCOCTL
PBVCOCTL, FSPLLCTL

LCD_B-Y

LCD_Y

M32_DTOUT

TXD
RXD

M32_DTOUT

M32_DTIN

VIDEO

OUT

DV_Y

MY(8),MC(4)

DV_C

DV_Y

V_OUT
Y_OUT

C_OUT

S_OUT

AV

OUT

DV

AV_DET

MY(8),MC(4)

IC7603

A_OUT / R

A_OUT / L

DATA_OUT

VF_R, VF_G, VF_B, VBLK

VC1, BLK1

DRUM_REF

CAP_REF

DRUM_PG

DRUM_FG

CAP_FG

J501

J503

J502

*only for B/W VF model

DATA_OUT

JACK60

PD(4)

M14D2 Series

OSD_DATA

Fig. 2-1-1 Basic block diagram

2-2

2.2 CCD (ICX220AK/ICX221BK)

This IC functions as an interline CCD (Charge
Coupled Device = one of solid-state pickup
devices). Since this CCD conforms to the SD
mode of the DV standard, it has an optimum
number of vertical pixels for the MPEG2 main level
and it realizes a horizontal resolution of 450 TV
lines. As same as general CCD's currently in use,
this CCD is capable of camera shaking correction
and electronic panning and tilting owing to the
extension area of 33 percent extra in both the
vertical and horizontal directions.
Moreover, this CCD provides high quality wide
picture whose aspect ratio is exactly 16:9 without
vertical interpolation.
High sensitivity and low dark current are realized
thanks to adoption of the Super HAD CCD
technology with the color filters of yellow, cyan,
magenta and complementary green mosaic filters.
This CCD has an electronic shutter function that is
able to vary charge storage time by the field period
read system.
Frame period read system is realized by joint use
of the newly developed TG IC.

HØ1

HØ2

ØRG

ØSUB

VØ1

VØ2

VØ3

VDD

Photo
Sensor

VØ4

1

Ye

G

Ye

Mg

Ye

G

Cy

Mg

Cy

G

Cy

Mg

Ye

G

Ye

Mg

Ye

G

Horizontal-Register

Vertical-Register

14131211108 9

7 6 5 4 3 2

GND

VOUT

TEST

∗

Cy

Mg

Cy

G

Cy

Mg

GND

VL

∗

Fig. 2-2-1 CCD block diagram

ELEMENT STRUCTURE Int e rline type CCD image sensor

Optical size 1/4 inch size format
Total pixels NTSC: 998 (H) × 677 (V) approx. 680,000 pixels, PAL: 998×797 approx. 800,000 pixels
Effective pixels NTSC: 962 (H) × 654 (V) approx. 630,000 pixels, PAL: 962×774 approx. 740,000 pixels
4:3 NTSC NT SC: 711 (H) × 485 (V) approx. 340,000 pixels, PAL: 702×575 approx. 400,000 pixels
16:9 18MHZ NTSC: 948 (H) × 485 (V) approx. 460,000 pixels, PAL: 936×575 approx. 540,000 pixels
16:9 5fsc NTSC: 942 (H) × 485 (V) approx. 460,000 pixels, PAL: 922×575 approx. 530,000 pixels

H direction: Front 4 pixels, Rear 32 pixels
V direction: Front 11pixels, Rear 12 pixels

Board material Silicon

OB

Table 2-2-1 CCD functions

Pin No. Label In/Out Descript ion Pin No. Label In/Out Descript ion

1

V

φ

4

In Vertical register transfer clock 8 VOUT Out Video signal output

2

V

φ

3

In Vertical register transfer clock 9 GND - Ground

3

V

φ

2

In Vertical register transfer clock 10

φ

RG

In Reset gate clock

4

V

φ

1

In Vertical register transfer clock 11

Hφ1

In Horizontal register transfer clock

5 GND - Ground 12

H

φ

2

In Horizontal register transfer clock

6 T EST - Open 13

φ

SUB

In Su bstrate clo c k

7 VDD - Power supply 14 VL - Protect transistor bias

Table 2-2-2 CCD pin function

2-3

2.2.2 CCD Image Sensor

Main difference in CCD adopted with DVC and VHS-C.

(Pixel)

7.15µ m

5.55

µ

m

(Pixel)

3.80µ m

4.15

µ

m

33% EIS Area

962(H)

711(H)

485(V)

654(V)

Picture Area

13.5MHz
18MHz

510(H)

492(V)

9.54545MHz

(Pixel)

7.3µ m

4.7

µ

m

500(H)

582(V)

9.45833MHz

(Pixel)

4.85µ m

4.65

µ

m

752(H)

582(V)

14.1875MHz

(Pixel)

3.85µ m

3.50

µ

m

33% EIS Area

962(H)

702(H)

575(V)

774(V)

Picture Area

13.5MHz
18MHz

NTSC: effective 630,000 (Image 340,000) pixels PAL: effective 740,000 (Image 400,000) pixels

NTSC: effective250,000 pixels PAL: effective 290,000 pixels

PAL (760H-type): effective 440,000 pixels

510H-type/760H-type 1/4" CCD for VHS-C

960H-type 1/4" CCD (w/ EIS area) for DVC

(GR-DVX7, GR-DVF31/DVL40, GR-DVL300 etc.)

NTSC PAL NTSC PAL PAL (760H)

9.54545MHz
910fH × 2/3
910fH = 4 × fsc

Horizontal drive
frequency

9.45833MHz
908fH × 2/3

14.1875MHz
908fH

DVC VHS-C

18MHz: 1144fH
Picture area:13.5MHz: 858fH

13.5MHz = 18MHz × 3/4

13.5MHz: DVC format Y signal sampling frequency

f

H

= 15.734264KHz (PAL: 15.625KHz): Horizontal sync frequency

f

SC

= 3.579545MHz (PAL: 4.433618MHz): Color sub-carrier frequency

Fig. 2-2-2 Pixel number and pixel size of various CCD

2-4

1. Feature of CCD for this model

This CCD adopts the drive frequency and the number of pixels conforming to the DVC format. The
horizontal drive frequency is 18MHz based on 13.5MHz that is Y signal sampling frequency of the DVC
format. And the number of pixels secures the horizontal resolution of 400 lines that conforms to the high
resolution DVC format. Moreover, to keep resolution even if EIS is switched on, the CCD having EIS
(Electric Image Stabilizer) area (approx. 33% in area) is adopted.
Adoption of the usual 1/4”-type CCD realizes miniaturization of the lens unit with keep the zoom ratio of 10
times, and it also realizes miniaturization of whole body.
On the other hand, a pixel size gets smaller as the evil effect of miniaturization and large numbers of pixel.
It becomes unfavorable in the point of CCD sensitivity and dynamic range. For such reason, the minimum
object illumination is determined as 18 Lux EIA standard.

2. Improvement of the CCD for DVC

It is elaborated the following idea to make up for the decline of the sensitivity of CCD at all.

1) Optimization of the on-chip microlens
Loss of incident light is minimized by reduction of ineffective area between microlenses on the pixels.

Photo

shielding AI

Light

Ineffective

Effective

Transfer

section

On-chip microlens On-chip microlens

Sensor

Transfer

section

Ineffective

Light

Photo

shielding AI

Transfer

section

Transfer

section

Effective

Fig. 2-2-3 Structural drawing of CCD image sensor

2-5

2) Construction of internal lens
Since the internal lens is constructed between the color filter and gobo, the light condensation
efficiency is improved even for inclined incident light.

Sensor V. Register

On-chip

microlens

Color filter

Poly Si

Gobo

V. Register

Poly Si

Internal len

s

On-chip

microlens

Color filter

Gobo

Sensor

Fig. 2-2-4 Structural drawing of internal lens

2-6

2.2.3 Numbers of pixel for main models

Models Optical size Total pixels

Effective pixels

(EIS)

practical pixels

GR-DV1
GR-DVM1
GR-DVX

1/3” approx. 570,000

908H  616V

approx. 530,000
858H  614V

approx. 350,000
704H  499V

GR-DVL /DVL9000U
GR-DVL7 /DVL9600U

1/3”
Progressive
scan

approx. 380,000
758H  504V

–

approx. 360,000
724H  494V

GR-DVY
GR-DVM5U /DV3U
GR-DVF10U /20U

1/4” approx. 460,000

766H  596V

approx. 420,000
724H  582V

approx. 290,000
611H  480V

GR-DVX7
GR-DVM70U /50U
GR-DVA1 /F1
GR-DVF11 /21 /31U
GR-DVA10 /F10 /A11
GR-DVL100 /200 /300U

1/4” approx. 680,000

998H  677V

approx. 630,000
962H  654V

approx. 340,000
711H  485V

GR-DVL700
GR-DVL9800U

1/3”
Progressive
scan

approx. 680,000
1002H  662V

approx. 630,000
962H  654V

approx. 340,000
720H  480V
DSC XGA: 630,000
962H  654V

GR-DV1E
GR-DVM1E
GR-DVXE

1/3” approx. 670,000

908H  728V

approx. 620,000
858H  726V

approx. 420,000
704H  594V

GR-DVL9000E
GR-DVL9500E /9600E

1/3”
Progressive
scan

approx. 450,000
758H  592V

–

approx. 420,000
724H  582V

GR-DVM5E /DV3E
GR-DVF1E /DVF10E

1/4” approx. 540,000

766H  711V

approx. 500,000
724H  697V

approx. 530,000
601H  576V

GR-DVX4E /DVX7E
GR-DVL20 /30 /40E
GR-DVL100 /200 /300E
GR-DVL9200E

1/4” approx. 800,000

998H  797V

approx. 740,000
962H  774V

approx. 400,000
702H  575V

GR-DVL9700E /9800E 1/3”

Progressive
scan

approx. 800,000
1002H  782V

approx. 740,000
962H  774V

approx. 420,000
720H  576V
DSC XGA: 740,000
962H  774V

GR-SXM46 /SX41E
GR-SXM26 /SX21E

1/4” approx. 470,000

795H  596V

–

approx. 440,000
752H  582V

GR-FX11 /FXM16E
GR-FX102 /FXM106S

1/4” approx. 320,000

537H  597V

–

approx. 290,000
500H  582V

VHS-C
NTSC

GR-AXM220U
GR-SXM920U

1/4” approx. 270,000

537H  505V

–

approx. 250,000
510H  492V

DVC
PAL

DVC
NTSC

VHS-C
PAL

Table 2-2-3 Numbers of pixel for main models

2-7

2.3 EXPLANATION OF CAMERA CIRCUIT

2.3.1 Present AW / AE control system

The signal-processing block of the present camera system is composed as shown below ( Fig. 2-3-1)

CCD A/D

COLOR

SEPARATION

LPF

MATRIX

ENCODER

PROCESS

AGC

GCA

GCA

Y

R

G

B

Y

C

TG

DRIVE

IRIS DRIVE

CAMERA CPU

IR SENSOR

∗

1

∗

2

∗

3

∗

4

∗

5

∗

1 Iris control

∗

2 Shutter speed setting

∗

3 Analog amp gain (AGC gain)

∗

4 WB setting (RED gain, BLUE gain)

∗

5 Parameter for picture compensation (color reproducibility, S/N ratio…)

Fig. 2-3-1 Camera block configuration

2-8

1. AE (Auto Exposure) control

The luminance level of camera output picture is controlled to always be proper exposure regardless of the
brightness and illumination of the object.

1) AE input information

•

Average of luminance level divided a frame picture into 48 blocks passed through the LPF.

•

The area ratio of the sections having luminance components higher than a certain level to the

whole sections.

AE control

Weighting of

sectioned data

Caluculation of

evaluation value

Target > Evaluation?

AGC gain down

↓

Slow shutter OFF

↓

Iris close

Iris open

↓

AGC gain up

↓

Slow shutter ON

RET

Fig. 2-3-2 AE control flow chart

2) Weighting of data on sections
Though the respective data on 48 sections are weighted, the basic settin g is to weight the center part
high.

Low

Low

High

High LowLow

Fig. 2-3-3 Weighting of data on sections

2-9

3) AE control and output luminance signal level
Gain-up mode: AUTO (OFF and AGC modes are the same as the VHS-C camcorder)

100 IRE

Open

0 IRE

5000 lux 300 lux 40-50 lux 10 lux

Close

MAX

MIN

1/30

1/60

1/240

ON

OFF

50 IRE

LUMINANCE

IRIS

APERTURE

AGC

GAIN

SHUTTER

SPEED

AUTO
LIGHT

ILLUMINATIONBRIGHT DARK

(2)

(1)

(3)

(4)

(5)

(6)

Fig. 2-3-4 AE control and output luminance signal level

2-10

(1) When the intensity of illumination is high and iris aperture is stopped down, the iris is opened for

compensating drop of the signal level by changing the shutter speed to high (1/250 sec).

(2) Since raising the AGC gain deteriorates the S/N ratio, the E-E level is slightly lowered in the

exposure compensation by controlling the AGC as compared with the iris control mode.

(3) As the intensity of illumination becomes low and AGC gain rises to maximum, the camera enters

the slow shutter mode (1/30 sec).

(4) When the camera enters the slow shutter mode, the signal level r ises by 6 dB and the AGC gain

drops in inverse proportion to the signal level.

(5) The auto-light is turned on when the illumination turns down a little more after the camera entered

the slow shutter mode and AGC gain rose to the maximum. There is a hysteresis to prevent
hunting as the auto-light is switched on/off.

(6) The intensity of illumination shown in the f igure is just an example and it varies depending on the

object, angle of view, etc.

2-11

2. AW (Auto White balance) control

AW control compensates the Red component gain and Blue component gain shown in the camera block
diagram to keep the white balance in the camera picture under every kind of light source.
Basic input data for AW control are three of the following.

(1) R, G, B levels of sections divided a picture into 48 sections.
(2) Data on existence/absence of infrared rays in the light source. This data is used for judging the

sort of the light so urce.

(3) Illumination judged with the exposure compensation parameters (iris/ AGC gain/ shutter speed).

The white balance is controlled by the following setting referring to the R, G, B data on the section that is
judged as a white (uncolored) part of the picture according to the three kinds of data mentioned above.

Red component gain = Green level / Red level
Blue component gain = Green level / Blue level

Besides the white balance control, balance among color phases is controlled by the parameter control in
the color signal processing from RGB to C signal depending on the light source.

1) Light source judging process

IR FLICKER BRIGHT LIGHT

DC component AC component (Over 4000 Lx)

SOURCE

Yes Yes Yes HAROGEN
Yes Yes No

∗

Yes No Yes OUT DOOR
Yes No No OUT DOOR

No Yes Yes FL LIGHT
No Yes No FL LIGHT
No No Yes FL LIGHT
No No No FL LIGHT

∗

: OUT DOOR or HAROGEN (not FL LIGHT)

Table 2-3-1 Light source judging process

2-12

2) AWB cont rol algorithm

AWB control

Light source judgment

(Gain limiter setting)

Sunlight?

Gain calculation from white block data

(Calculation value = Target gain)

Gain setting (adjustment) for the sunlight

(Adjustment value = Target value)

Optimum time constant setting for gain

control

Is the WB deviating to

blue?

R-gain up / B-gain down

Is the WB deviating to

red?

R-gain down / B-gain up

RET

YES

NO

NO

NO

YES

YES

The upper and lower limits of each gain are set according to
the ratio between R and B components and judgment of the
light source by the infrared sensor.

Setting of the control time constant to avoid unnatural color
variation.

Fig. 2-3-5 AW control flow chart

The light source of the natural light (sunlight), halogen lamp (indoor) or fluorescent lamp is judged
according to data of the infrared sensor and data on the illumination.
Since the gain to be compensated by the white balance control greatly varies depending on the
device used (CCD, IR cut filter, lens, etc.) and parameter for color separation, settings of limiter,
control time constant and color reproducing parameters differ from model to model.

2-13

2.3.2 AF (Auto Focus) control

1. Auto Focus operation during slow shutter mode

Though the basic Auto Focus operation is the sam e as usual, the interval of Auto Focus operation varies
conforming to the timing of the picture data renewal when the camera is in the slow shutter mode. For
example, in case the Gain-up mode is set to Auto, the shutter speed is changed to 1/30(2V) according to
the illumination of the object. Therefore, the Auto Focus operation also works every 2V. The Auto focus
operation works every 4V in Slow-4X mode and every 10V in Slow-10X in the same way.

1/60

Data

Renewal/processing

1/30

VD

Focus

operation

2V

Fig. 2-3-6 AF operation timing in slow shutter mode

2. Improvement of the Low-contrast performance

To improve the AF performance in the low contrast subject (such as the man's face), a route that has low
stage filter (HPF1) is added newly. The low contrast subject contains the frequency element that is not
comparatively high.

BPF HPF2 Rectifier

Peak

Addition

HPF1 Rectifier

Peak

Addition

HPF2 Rectifier

Peak

Addition

AFE

HPE

HPF1

HPF2

BPF

HPF1 Rectifier

Peak

Addition

HPF1 Rectifier

Peak

Addition

HPF2 Rectifier

Peak

Addition

AFE1
HPE1

HPF1

HPF2

HPF2 Rectifier

Peak

Addition

AFE2
HPE2

HPF1: 500KHz
HPF2: 1.7MHz

Previous

New

Fig. 2-3-7 Addition of AFE low stage filter

2-14

2.3.3 EIS (Electric Image Stabilizer) control

The accurate compensation without picture quality deterioration is possible by using CCD with expansion
area and correcting it two times.

CCD

CDS / AGC /

ADC

IWD FMC

VRAM

TG/

V_DRIVER

CPU

13.5 MHz18 MHz

Vector

(1) (2)

(3)

(4)

DSP

Fig. 2-3-8 EIS system block diagram

962

654(*774)

800

240(*288)

720

245(*292)

(1) Cutting out at TG (2) Cutting out at IWD

(3) Cutting out at Field Memory (4) Camera output

2 lines mixing transfer

Fig. 2-3-9 EIS operation

2-15

2.4 CAMERA SYSTEM IC'S FUNCTION

2.4.1 Camera DSP (IC4301: JCY0120) function

1. Camera DSP (IC4301: JCY0120) internal block diagram

CLK45

ADIN [9:0]

YO

CLR

SSG1

EIS/FMC

VRAM Contol
Vector Detect

ID

CLKYCA

CLK13

CLK13X

YOUT

SSG for TG/YCA

SSG2

CLK13

Main SSG

AUTO

CLKYCA

Auto operation

process

CLK18I
CLK13I
CLK27I

CLKGEN

Clock generate

TVSEL0

Y/C

CLKYCA

Y/C signal

process

IWD

CLK14

Frequency

converter

KIZU

White noise

compensation

SELECT

CLK13

ANA I/F

CLK13

Analog input

interface

NTSC/PAL

Color Encoder

CLKENC2

ENC

CLKENC1

CVF

CLK13

Interface for Color

Viewfer

KASHA

CLK13

Shutter sound

occurrence

D/A Converter

CLKENC1

YDAC

CO

D/A Converter

CLKENC2

CDAC

D/A Converter

CLK13

Y2DAC

Y2O

D/A Converter

CLK13

RYDAC

D/A Converter

CLK13

BYDAC

D/A Converter

KDAC

RYO
RYO

KO

BEND

PWM

AFBEND

AYO [3:0]
ACO [3:0]

COUT

Y2OUT

RYOUT

BYOUT

KOUT

CLKYCA

IRSI

HDYCA
VDYCA

FLDYCA

VBDAT

VBSTART

Test signal generator / Wipe / OSD mix

Hadamard NR / Mix / Signal select

CSYNC

HDANA

VDANA

CSYNC1

DYI [3:0]
DCI [3:0]

EOUT1 EOUT5 EOUT9
EOUT2 EOUT6 EOUT10
EOUT3 EOUT7 EOUT11
EOUT4 EOUT8 EOUT12

CLK27

INHA

INVA

ANACNT

FMY [7:0]
FMC [3:0]

TMY [7:0]

TMC [3:0]

IE1 FMRE1 FMWE1
IE2 FMRE2 FMWE2

OMT

MCLK RAD
FMWR WAD
RAE1 WAE1
RAE2 WAE2

DSC I/F

CLK13

DSC interface

FLDDSC
CLKDSC

HDDSC

VDDSC

CLKYCA

DSYO [7:0]
DSCO [7:0]

DSYI [7:0]
DSCI [7:0]

EDAC

12ch EVR DAC

ESSG

CLK13

SSG for Encoder

CBLK
CSYNC
BF
LSW
HRST4T
VRST4T

VBGEN

CLK13

VBID/WSS

Generator

YCIN

LHFO

ADYC

CLKYCA

ADKZ

HDTG

VDTG

SLEN

OSD I/F

CLK13

CLK13X

OSD Interface

DVC I/F

CLK13

DVC Interface

CLK27

DVSL SLDV

SLCV

FMSLSLFMDSSLSLDS

VBLK0
BLK10
BLK20

OSY_V OSY_1
OSR_V OSY_2
OSB_V

DYO [3:0]
DCO [3:0]

INH
INV

OUTH

OUTV

VR VBLK
VG BLK1
VB BLK2

VC1
VC2

HDOSD
VDOSD

CLKOSD

HDANA13

VDANA13

HDFMC

VDFMC

FLDFMC

OUTH13
OUTV13

CLKYCA

CLK13

CLK13X
CLKENC1
CLKENC2

RE DSTB

LWE HWE
CS RWSEL
ALE USEL0

USEL1

BUS [15:0]

CPU I/F

CPU Interface

CONTROL SINGNAL
DBI[15:0]

VDMDA

HDCPU VDCPU

FRP FLDCPU

Fig. 2-4-1 Camera DSP (IC4301: JCY0120) internal block diagram

2-16

2. Camera DSP (IC4301: JCY0120) pin functions (1/6)

Pin No. Label In/Out Description

100 VDMDA Out Vertical reference signal output for MDA
158 PWM Out PWM output

20 CLK45 Out 4.5MHz output

1 VSS - Ground for Digital
251 VDDE - Power supply for Digital (I/O)
255 CSYNCI
191 HDANA
117 VDANA

36 ANACNT

33 AY00
113 AY01
186 AY02

32 AY03

35 AC00

34 AC01
187 AC02
114 AC03
188 INHA
115 INVA
138 ADDVSS - Ground for add Digital
256 VDDE - Power supply for Digital (I/O)

64 VSS - Ground for Digital

69 ADDVDDE - Power supply for add Digital (I/O)
137 DSYO0
208 DSYO1
270 DSYO2

61 DSYO3
136 DSYO4
207 DSYO5

60 DSYO6

59 DSYO7
140 DSCO0
210 DSCO1
272 DSCO2
142 DSCO3
139 DSCO4
209 DSCO5

63 DSCO6

62 DSCO7
211 CLKDSC Out Clock for DSC
141 HDDSC Out Horizontal reference pulse output for DSC
212 VDDSC
143 FLDDSC

70 ADDVSS - Ground for add Digital
271 VDDE - Power supply for Digital (I/O)
146 DSYI0
215 DSYI1
145 DSYI2

Not used-

Not used-

Out Vertical reference pulse output for DSC

In Digital luminance signal input for DSC

Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (1/6)

2-17

••••

Camera DSP (IC4301: JCY0120) pin functions (2/6)

Pin No. Label In/Out Description

65 DSYI3
276 DSYI4
214 DSYI5
144 DSYI6
213 DSYI7
217 DSCI0
148 DSCI1

68 DSCI2
278 DSCI3
216 DSCI4

67 DSCI5
147 DSCI6

66 DSCI7

30 TVSEL In TV system select (L: NTSC, H: PAL)
112 CPUSEL0 In CPU select (L: n, H: M)
185 CPUSEL1 In CPU select 1 (L: MN2_H: MN3)
273 VDDI - Power supply for Digital (I/O, internal)
275 ADDVDDE - Power supply for add Digital (I/O)
106 TCK
178 TMS
245 TRST In Test terminal (for JTAG with pull-up)
179 TDIN
105 TDOUT

31 ADDVSS - Ground for add Digital
252 VDDI - Power supply for Digital (I/O, internal)

21 ADDVSS - Ground for add Digital

22 VSS - Ground for Digital
125 DACTEST In Test terminal for DAC
184 AVDDA - Power supply for Analog sound
250 DVDDM - Power supply for DAC
248 AVDDV2 - Power supply Analog video
249 AVSSA - Ground for Analog sound

26 AVSSV2 - Ground for Analog video

28 VREFHK In Reference voltage input, top side (for shutter sound)
111 VREFLK In Reference voltage input, bottom side (for shutter sound)

29 K_OUT Out Shutter sound output

25 IREFVF In/Out Reference register terminal for current adjustment, (for VF signal)
110 VREFVF In Reference voltage input terminal for adjustment, (for VF signal)

27 B-Y_OUT Out B−Y signal output for VF
182 R-Y_OUT Out R−Y signal output for VF

24 IREFC In/Out Reference register terminal for current adjustment,(for chromatic signal)
247 VREFC In Reference voltage input terminal for adjustment,(for chromatic signal)
109 C_OUT Out Modulation color signal output

23 IREFY In/Out Reference register terminal for current adjustment,(for luminance signal)
107 VREFY In Reference voltage input terminal for adjustment,(for luminance signal)
181 Y_OUT Out Luminance signal output
183 Y2_OUT Out Luminance signal output for VF
108 AVSSV1 - Ground for Analog video

Not used-

In Digital luminance signal input for DSC

In Digital color difference signal input for DSC

Not used-

Not used-

Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (2/6)

2-18

••••

Camera DSP (IC4301: JCY0120) pin functions (3/6)

Pin No. Label In/Out Description

246 AVDDV1 - Power supply for Analog video
180 NC - Not used
222 AVSSE3 - Ground for EVR

79 VREFL3 In Reference voltage input for bottom side

75 VREFH3 - Power supply for EVR

78 AVDDE3 - Power supply for EVR
223 DVDDM - Power supply for DAC
220 AVSSE2 - Ground for EVR
221 VREFL2 In Reference voltage input for bottom side

74 VREFH2 In Reference voltage input for top side

75 AVDDE2 - Power supply for EVR
279 NC - Not used

71 AVSSE1 - Ground for EVR
150 VREFL1 In Reference voltage input for bottom side
218 VREFH1 In Reference voltage input for top side

72 AVDDE1 - Power supply for EVR
149 EOUT1 Out EVR output 1
280 EOUT2 Out EVR output 2
219 EOUT3 Out EVR output 3

73 EOUT4 Out EVR output 4
281 EOUT5 Out EVR output 5
151 EOUT6 Out EVR output 6
152 EOUT7 Out EVR output 7
282 EOUT8 Out EVR output 8

77 EOUT9 Out EVR output 9
153 EOUT10 Out EVR output 10
283 EOUT11 Out EVR output 11
154 EOUT12 Out EVR output 12
162 ADDVDDE - Power supply for add Digital (I/O)
126 ADDVSS - Ground for add Digital
167 ADDVDDE - Power supply for add Digital (I/O)
284 VSS - Ground for Digital
286 VDDE - Power supply for Digital (I/O)
269 VSS - Ground for Digital
266 VDDE - Power supply for Digital (I/O)
254 VSS - Ground for Digital
263 ADDVDDE - Power supply for add Digital (I/O)
192 ADDVSS - Ground for add Digital
177 ADDVDDE - Power supply for add Digital (I/O)
101 NAND2_O Out NAND 2 output
102 NAND2_B In NAND 2 input B
176 NAND2_A In NAND 2 input A
175 NAND1_O Out NAND 1 output
242 NAND1_B In NAND 1 input B
103 NAND1_A In NAND 1 input A

15 ADDVDDE - Power supply for add Digital (I/O)
274 VSS - Ground for Digital
267 VDDI - Power supply for Digital (I/O, internal)

Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (3/6)

2-19

••••

Camera DSP (IC4301: JCY0120) pin functions (4/6)

Pin No. Label In/Out Description

99 CSYNC Out Internal composite sync. Signal output
238 ADDVSS - Ground for add Digital
174 DYO0

18 DYO1

19 DYO2
240 DYO3
239 VSS - Ground for Digital
243 VDDI - Power supply for Digital (I/O, internal)

16 DCO0

17 DCO1

97 DCO2

98 DCO3
173 INH Out Horizontal reference pulse output for DVC REC
172 INV Out Vertical reference pulse output for DVC REC

13 DYI0

14 DYI1
169 DYI2

12 DYI3
277 VDDI - Power supply for Digital (I/O, internal)
244 VSS - Ground for Digital

95 DCI0
170 DCI1

94 DCI2

11 DCI3
171 OUTH In Horizontal reference pulse input for DVC PB

96 OUTV In Vertical reference pulse input for DVC PB
241 VDDE - Power supply for Digital (I/O)
203 MCLK Out Clock output for field memory

49 IE1 Out Input enable
130 FMWE1 Out Memory write enable

48 WAD Out Write address
200 RAD Out Read address
201 FMRE1 Out Memory read enable

50 RAE1 Out R ead address enable
129 FMWR Out Memory write transfer
265 WAE1 Out Write address enable
258 VDDI - Power supply for Digital (I/O, internal)
259 VSS - Ground for Digital
206 ADDVDDE - Power supply for add Digital (I/O)

51 IE2
131 FMWE2
202 FMRE2

52 RAE2

53 WAE2
134 TMY0
205 TMY1

56 TMY2

55 TMY3

Not used-

In Digital luminance signal input for DVC

In Digital colon difference signal input for DVC

Out D igital luminance signal output for DVC

Out D igital luminance signal output for field memory

Out D igital colon difference signal output for DVC

Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (4/6)

2-20

••••

Camera DSP (IC4301: JCY0120) pin functions (5/6)

Pin No. Label In/Out Description

204 TMY4
133 TMY5

54 TMY6
132 TMY7
135 TMC0

58 TMC1
268 TMC2

57 TMC3

47 ADDVDDE - Power supply for add Digital (I/O)
128 ADDVSS - Ground for add Digital
261 FMY0
197 FMY1
260 FMY2
196 FMY3
195 FMY4
194 FMY5
193 FMY6
257 FMY7
199 FMC0

46 FMC1
127 FMC2
198 FMC3
262 VDDI - Power supply for Digital (I/O, internal)
236 VDDE - Power supply for Digital (I/O)
237 VDDI - Power supply for Digital (I/O, internal)

43 VSS - Ground for Digital
190 ADDVDDE - Power supply for add Digital (I/O)

44 CLK27

42 CLK18

45 CLK13
123 ID In Line discriminate pulse input
189 VDTG Out Vertical reference pulse output for TG
116 HDTG Out Horizontal reference pulse output for TG
253 LHFO Out LHF signal output

86 ADDVDDE - Power supply for add Digital (I/O)
264 VSS - Ground for Digital
118 ADIN9

37 ADIN8
119 ADIN7

38 ADIN6
120 ADIN5

39 ADIN4
121 ADIN3

40 ADIN2
122 ADIN1

41 ADIN0
232 VDDI - Power supply for Digital (I/O, internal)

7 ADDVSS - Ground for add Digital

Digital colon difference signal input form field memory

Digital luminance signal intput form field memory

In

In Clock input

Out Digital colon difference signal output for field memory

In

In Digital signal input from A/D

Out Digital luminance signal output for field memory

Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (5/6)

2-21

••••

Camera DSP (IC4301: JCY0120) pin functions (6/6)

Pin No. Label In/Out Description

6 ADDVDDE - Power supply for add Digital (I/O)
9 RE In Read enable

235 HWE In High address write enable

8 LWE In Low address write enable
168 ALE In Address latch enable
230 BUS15

87 BUS14
163 BUS13
231 BUS12

2BUS11

88 BUS10
164 BUS9

89 BUS8

3BUS7

90 BUS6

4BUS5
165 BUS4
233 BUS3

5BUS2

91 BUS1
166 BUS0
234 VSS - Ground for Digital
124 CLR In Clear input
160 VDCPU Out Vertical reference pulse output for CPU
228 HDCPU Out Horizontal reference pulse output for CPU
159 FRP Out Frame detect pulse output
227 OMT Out EIS read-out data enable flag output

85 AFBEND Out CPU interrupt pulse output
161 FLDCPU Out Field discriminate pulse output for CPU
287 BEND Out Block average data interrupt pulse output
229 VSS - Ground for Digital

92 DSTB In Data strobe
104 VPD In Test pin for pull-up

10 CS In Chip select

93 RWSEL In Read write select
288 VDDI - Power supply for Digital (I/O, internal)
157 CLKOSD Out Clock output for OSD

84 HDOSD Out Horizontal reference signal for OSD
226 VDOSD Out Vertical reference signal for OSD
225 BLK1 In Blank signal 1
156 BLK2 In Blank signal 2

81 VC1 In Character signal 1
224 VC2 In Character signal 2
155 VR In Character signal 3R

82 VG In Character signal 3G
285 VB In Character signal 3B

80 VBLK In Blank signal 3

83 ADDVSS - Ground for add Digital

In/Out CPU bus I/O

Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (6/6)

2-22

2.5 EXPLANATION OF DECK CIRCUIT

2.5.1 Deck system overall structure

The DVC deck system has such the IC construction as shown in Fig. 2-5-1. The DV-MAIN IC (IC3001)
serves as the center IC of the deck system IC construction, and this system has been incorporated in the
models of the GR-DVX7 and after.
In recording, the deck system processes image data input from the camera section by shuffling and DV
compression and adds parity codes to it as well as the audio data and sub code data input to the deck
system, and saves those data as sync blocks.
The formatter inside the DV-MAIN IC serves as the 24-25 converter for generating A TF pilot signal and the
data column converter for adapting the data to the digital magnetic recording/playback system (scrambled
interleaved NRZI), and it outputs the processed data to the PRE/REC IC as recording data.
In playback the playback signal transmitted from the PRE/REC IC is input to the DV-ANA (IC3301) and
DV-EQ (IC3201) for waveform equalization, and then supplied to the DV-MAIN IC as playback data. The
DV-EQ IC takes charge of various functions such as playback clock generation, VITERBI decoding, ATF
detection, and so on. For details of its functions, refer to the next page.
The DV-MAIN IC processes playback data by the reverse p rocedure of recording and it transmits playback
data to the camera section and audio section. Since the DV-MAIN IC has the 1394 LINK function, it inputs
and outputs DV data from/to the camera through the 1394 PHY IC (IC3101).
The 16-Mbits DRAM (IC3002) is used as the memory for shuffling/de-shuffling and ECC error correction.

IC3001

DV_MAIN

Shuffling / De-shuffling

Compress / De-compress

ECC Encode / Decode
Formatter / Deformatter

1394 LINK

IC3201
DV_EQ

Auto EQ

Viterbi

PLL det

IC3301

DV_ANA

AGC

PB VCO

IC3501

PRE/REC

HEAD

CAMERA

AUDIO

IC3002

16M DRAM

IC3101

1394 PHY

DV

IN/OUT

Fig. 2-5-1 DVC deck IC structure

2-23

2.5.2 PB equalizer and ATF

LPFAGC

BPFGCA

AD1

AUTO

EQ

1+D

VITERBI

PLL
DET

2CH

DAC

PWM

AD2ATF

CPU

I/F

JIG CONN

PB_VCO

IC3202

PB_ENV

DISCRI

RECCLK

PB_DATA

PB_CLK

RECCTL

ADDT

0:15

To:

DECK

CPU

IC3301IC3201 DV_ANADV_EQ

41.85MHz

41.85MHz

+

-

PBO

ATFO

PLLO

CLK

VOA
VOB REFV

PLLE

AINAD2

AINAD1

ATF_GAIN

DISCR

CTL1

DTR

REC:H

SW

VCO

PB:H

VCOC
CLKO

To:
DV
MAIN

Fig. 2-5-2 PB equalizer and ATF block diagram

In the playback mode the PB ENV signal output from the PB amplif ier is branched into two in t he IC3301
DV ANA; one is the signal for playback data and the other is that for ATF. The PBO signal output through
the LPF and AGC is sent to the IC3201 DV EQ as that for playback data, while the ATFO signal output
through the BPF and GCA is also sent to the IC3201 DV EQ as that for ATF.
In the IC3201 DV EQ, the playback signal undergoes digitalization (AD1), waveform equalization (AUTO
EQ), SI-NRZI channel decoding (1+D), and Viterbi-decoding (VITERBI). The resultant signal processed as
mentioned above is output from the IC3201 as the playback data signal. At the same time, the PLL circuit
constructed in this circuitry controls phase correction in order to generate the PB clock synchronizing with
the playback signal. The 41.85MHz signal oscillated by the internal VCO of the IC3301 is outp ut as the PB
clock (PB CLK). Since the internal switch of the IC3301 varies the capacitance of the capacitor, the switch
is turned off to minimize the capacitance of the capacitor when the level of the REC CTL is H, namely, in
the Audio-Dubbing mode. As a result, the response time is shortened in that mode. The discriminator
(DISCRI) compares the 41.85MHz signal oscillated from the VCO with the other 41.85MHz signal
produced from the 81MHz of the main clock in order to detect a difference between the two frequencies. In
the general playback mode, the discriminator outputs a Low-level signal when the frequency difference is

+1%

or more or a High-level signal when the difference is −1% or more. In the other modes, a Low-level
signal is output when the frequency difference is +3% or more or a High-level signal is output when the
difference is −3% or more. When the frequency difference is within ±1% in the general playback mode or
within ±3% in the other modes, the output signal has high impedance. Therefore, a frequency difference, if
there is, is roughly corrected.
Regarding the signal for the ATF, the frequency component of the ATF pilot signal is extracted from t he
playback signal by the BPF and the ATF gain is adjusted by the GCA. Then, the ATF circuit in the IC3201
DV EQ detects a tracking difference using the pilot signals of F0, F1 and F2, and data on the detection
result is transmitted to the servo CPU.

2-24

2.5.3 PLL operation

X5501

54MHz

TG

V.DRV

IC5501

VCXO

VCO

X3301

81MHz

PHYCLK

PWM405

IC3001

CLK27

VCO

VCOAUDPWMAUD

VCOAUD

ANA_PD

X3001

24.576MHz

MAIN_VCO

MAIN_VCO

ADJ

FS_PLLADJ

JIG CONN

IC3301

FS_PLL

JIG CONN

CLK

OSC

PC

FRP

GEN

81MHz

41.85MHz

Serial I/F

From

DECK_CPU

12.288MHz

11.289MHz

8.192MHz

DVDSP

DVANA

FRP

GEN

MAIN CLK

1394
LINK

REF

1394
PHY

PC

REF

27MHz FRP

FRP

DOMCK

40.5MHz

Not used

REC CLK

IC3101

ANA_DATA

VCO405I

VCO405

IC3007

Fig. 2-5-3 PLL operation block diagram

The main clock for the deck section operates at a frequency of 40.5MHz, which is equivalent to 18MHz for
the previous models. Since two memories of the SHUFFLE memory and the ECC memory that are
needed for the previous models are integrated into one DRAM, the clock frequency is raised in order to
increase the processing speed. For setting the clock duty ratio exactly at 50%, 40.5MHz clock is produced
from the 81MHz clock. The PLL circuit of the main clock system produces 81MHz clock by the X'TAL
X3301 and VCXO, and sends the 81 MHz clock to the IC3001 DV DSP. Using the frame pulse produced
from the 81MHz pulse as the comparison signal of the PLL, the frame pulse (29.97Hz in NTSC or 25Hz in
PAL) is produced from the 27MHz pulse output from the camera and this frame pulse is used as the
reference signal of the PLL in the general recording and playback modes. However, the frame pulse
produced by decoding the input DV signal is used as the PLL reference signal for phase compa rison in the
1394 input mode. A phase error is output as the PWM405 sig nal, which passes through the filter circuit
and controls the VCXO. For PLL adjustment, the filter output voltage is set nearly at the center (1.2V

±

0.1V) of the tolerance in the condition that the PLL is locked.
There are three audio sampling frequencies (32kHz, 44.1kHz and 48kHz) provided, therefore, master
clocks (8.192MHz, 11.289MHz and 12.288MHz) are produced by the VCO in the IC3301 for the
respective sampling frequencies, and those master clocks are output to the IC3001 DV DSP. For adjusting
the FS-PLL, the respective frequencies are adjusted in the free-run status.

2-25

2.5.4 Basic principle of Viterbi detection

Recording
signal

1V

-1V

0V

Threshold level

"1"

"0"

"-1"

PB
signal

"1" "0" "0" "1" "0"

Usual detection
(Hard decision)

Viterbi decoder

0.01.0 -0.4 0.8 0.0 (V)

ERROR !!

A/D converter

"1" "0" "0" "1" "0"

"1" "0" "-1" "1" "0"

Select the most
reliable line

point A

Threshold level

Fig. 2-5-4 Basic principle of Viterbi detection

Fig. 2-5-4 is a conceptual chart showing the basic principle of Viterbi decoding method. Decoding means a
ternary decision that judges differential waveform at the identification point by the ternary criteria when
NRZI-recorded signal is played back.
The previous detection method is based on the ternary criteria of the preset identification level, and this
method is called the hard decision because of the fixed identification level. By this method, for example,
the identification value at the point "A" (in Fig.2-5-4) is "0", which represents an error occurrence.
On the other hand, the Viterbi decoding adopts the soft decision method. In the Viterbi decoding, playback
signal is converted from analog to digital data and then the signal level is read. If the signal level is 0.4V at
the point "A" by ways of example, the previous method judges it as "0", but the Viterbi decoding met hod
detects a possibility that it may be "0" or "1" and i t assu mes two kinds of bit strings of "10010" and "10110".
Next, the Viterbi method introduces another criterion in decision. In the NRZI recording, there is a
regularity in the recording signal and playback waveform. That is to say, there is a fall point between two
rise points in the recording signal. This means that there must be "−1" between "1" and "1". According to
this principle, the bit string of "10010" is theoretically non-existent, and "10110" is consequently selected.
As mentioned above, the Viterbi decoding method utilizes the regularity between bits or the redundancy of
NRZI-recorded signal for error correction. T he above explanation of the Viter bi decoding m ethod is just a
conceptual description, and a high degree of data processing system such as to select the most possible
bit string from a great deal of probabilities is introduced in the actual Viterbi decoding.

2-26

2.5.5 Audio recording mode

There are four basic modes in the DVC audio mode as shown in Table 2-5-1, and it is recommended that
the DVC can cover all of the four basic modes by the specifications.

Mode Channel Sampling frequency Quantiazation

48K mode 48kHz

44.1K mode 44.1kHz
32K mode 32kHz

32K-4ch mode 4 32kHz 12-bit non- linear

2 16-bit linear

Table 2-5-1 Audio basic modes

CH 1 CH 2

VIDEO

AUDIO

1 Frame (10 Tracks)

Tape travel

Head motion

CH 1 CH 2

VIDEO

AUDIO

1 Frame (12 Tracks)

Tape travel

Head motion

NTSC 525/60 system

PAL 625/50 system

Fig. 2-5-5 Audio track pattern

2-27

The audio recording system of this model is as follows. In the 2-channel mode, quantiazation is linearly
processed in a data unit of 16-bits and the sampling frequency is 48kHz. In regard to the recording pattern,
the first 5 tracks (6 tracks in PAL) of 10 tracks (12 tracks in PAL) in a frame is used for CH1 recording and
the second 5 tracks in a frame is used for CH2 recording. Since audio data for one channel is interleaved
extending over 5 tracks (6 tracks in PAL), it is possible to interpolate audio data by 1/5 (or 1/6 in PAL) if
there is a data error in a track.
In the 4-channel mode, quantiazation is non-linearly processed to convert 16-bits input data into 12-bit
data and the sampling frequency is 32kHz. In regard to the recording pattern, the CH1 is used for
recording sound-1 while the CH2 is used for recording sound-2 which is used for audio dubbing. The
previous models show the audio mode by the sa mpling frequency o f 48 kHz or 32 kHz, how ev er, the recent
models show it by 16-BIT or 12-BIT to meet the market trend.

Sound mode Sam p ling

(MENU) frequency

L ch

R ch

L ch Audio

R ch dubbing

L ch

R ch

Channel

16 BIT 48kH z

CH 1

CH 2

SOUND 1

SOUND 2

12 BIT 32kH z

CH1

CH2

Table 2-5-2 Channel format

2.5.6 Audio signal processing

This model adopts a new audio signal processing IC, which comes equipped with AD and DA converter.

Rch

Lch

PHASE

EQ

EQ

HPF

HPF

ALC

ALC

PHASE

ADC

AUDIO

I/F

DAC

MUTE

MUTE

VOL
VOL

MIX

MIX

MIX

AD

I/F

DA

I/F

CLK

MIX

MIX

16 → 12bits

CONVERT

12 → 16bits

CONVERT

FADER

DRAM

I/F

SP

SHUTTER

IC2201 Audio & A/D_D/A

IC3001 DECK DSP

MIC

CH1
CH2

CH1
CH2

AIDAT

DODAT

DOMCK
DOBCK

DOLRCK

OFF

ON

OFF

ON

EE/REC

PB

PB

EE/REC

A/V OUT

Fig. 2-5-6 Audio block diagram

2-28

2.5.7 Clock system for audio data

DOMCK (Master Clock)

Sampling frequency DOMCK

48kHz 256fs: 12.288MHz
32kHz 384fs: 12.288MHz
48kHz 256fs: 12.288MHz

44.1kHz 256fs: 11.2896MHz
32kHz 256fs: 8.192MHz

A. Dubbing 32kHz 256fs: 8.192MHz

REC

PLAY

DOBCK (Serial Clock)

Sampling frequency DOB C K

48kHz 36fs: 1.536MHz
32kHz 36fs: 1.024MHz
48kHz 36fs: 1.536MHz

44.1kHz 36fs: 1.4112MHz
32kHz 36fs: 1.024MHz

A. Dubbing 32k H z 36fs: 1.024MHz

REC

PLAY

DOLRCK (LR Clock)

Sampling frequency DOLRCK

48kHz 48kHz
32kHz 32kHz
48kHz 48kHz

44.1kHz 44.1kHz
32kHz 32kHz

A. Dubbing 32kHz 32kHz

REC

PLAY

Table 2-5-3 Clock frequencies

15 14 13 012 15 14 13 012

120131415120131415

L ch DATA R ch DATA

DOLRCK

DOBCK

DODAT

AIDAT

MSB LSB

Fig. 2-5-7 Timing chart

2-29

2.5.8 Deck DSP IC function

1. Deck DSP (IC3001: JCY0106-2) pin functions (1/6)

Pin No. Label In/Out Description

69 VDD - Power supply

1 GND - Ground

134 PWMAUDO Out Audio PLL control signal, (To DVANA: IC3301)

70 VDDS

2VDD

71 VCOAUDI In PB audio b PLL input, (From DVANA: IC3301)

3 VCOAUDO Out PB audio b PLL adjustment voltage output
135 GND - Ground
189 VDD - Power supply
226 OSC32I - L: Fixed (Not used)

72 - - Not used

4 OSC32O - Open (Not used)
136 OSC44I - L: Fixed (Not used)

73 OSC44O - Open (Not used)

190 OSC48I In 24.5MHz clock input

5 OSC48O Out 24.5MHz clock output
227 GND - Ground
137 AUDIOTESTI - L: Fixed

74 AUDIOTESTIO - H: Fixed

6 VDDS - Power supply
191 DILRCK
138 DIBCK

75 DIMCK

7DIDAT

8 AILRCK Out Serial I/O interface channel clock for ADC, (To ADC: IC2101)

76 AIBCK Out Audio serial data clock, (To ADC: IC2101)
139 AIMCK Out Audio master clock, (To ADC: IC2101)
192 PHYCLK Out IEEE 1394 crystal oscillator output (27MHz), (To 1394 PHY: IC3101)
228 GND - Ground

9 AIDAT [0]

77 AIDAT [1]
140 DOLRCK
193 DOBCK
229 DOMCK

10 DODAT

78 VDD - Power supply
141 AOLRCK
230 AOBCK
194 AOMCK

11 AODAT [0] Out Audio serial data output, (To ADC: IC2101)

79 AODAT [1] - Open (Not used)
142 VDDS - Power supply
231 GND - Ground

Open (Not used)-

L: Fixed (Not used)-

Audio serial data input, (From ADC: IC2101)In

- Power supply

Open (Not used)-

Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (1/6)

2-30

••••

Deck DSP (IC3001: JCY0106-2) pin functions (2/6)

Pin No. Label In/Out Description

195 - - Not used

12 YSO [0]

80 YSO [1]
143 YSO [2]
232 YSO [3]

13 BRSO [0]

81 BRSO [1]
196 BRSO [2]
144 BRSO [3]

14 - - Not used
233 VDDS - Power supply

82 YSI [0]
197 YSI [1]
145 YSI [2]

15 YSI [3]

83 BRSI [0]

16 BRSI [1]
146 BRSI [2]

84 BRSI [3]

17 VDD - Power supply
147 OUTH Out Horizontal reference pulse output for DVC PB, (To CAMERA DSP: IC4301)

85 OUTV Out Vertical reference pulse output for DVC PB, (To CAMERA DSP: IC4301)

18 INH In Horizontal reference pulse input for DVC REC, (From CAMERA DSP: IC4301, )
148 INV In Vertical reference pulse input for DVC REC, (From CAMERA DSP: IC4301)

86 GND - Ground

19 VDD - Power supply

87 OSC27I In 27MHz clock input, (From CAMERA DSP: IC4301)

20 OSC27O - Open (Not used)
149 GND - Ground
196 VDD - Power supply
234 - - Not used

88 RAMADRS [0]

21 RAMADRS [1]
150 RAMADRS [2]

89 RAMADRS [3]
199 VDDS - Power supply

22 RAMADRS [4]
235 RAMADRS [5]
151 RAMADRS [6]

90 RAMADRS [7]

23 GND - Ground
200 RAMADRS [8]
152 RAMADRS [9]

Out DRAM address output, (To 16M_DRAM: IC3002)

Out DRAM address output, (To 16M_DRAM: IC3002)

Out DRAM address output, (To 16M_DRAM: IC3002)

Out DVC playback digital luminance signal output, (To CAMERA_DSP: IC4301)

DVC playback digital color difference signal output, (To CAMERA_DSP: IC4301)Out

DVC record digital luminance signal input
(From CAMERA_DSP: IC4301, ANALOG VIDEO I/O: IC3801)

DVC record digital color difference signal input
(From CAMERA_DSP: IC4301, ANALOG VIDEO I/O: IC3801)

In

In

Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (2/6)

2-31

••••

Deck DSP (IC3001: JCY0106-2) pin functions (3/6)

Pin No. Label In/Out Description

91 - - Not used

24 VDD - Power supply

25 RAMWE Out Write enable output, (To 16M_DRAM: IC3002)

92 RAMRAS Out Lower address strobe, (To 16M_DRAM: IC3002)
153 RAMCAS [0] Out Address strobe (Lower bit), (To 16M_DRAM: IC3002)
201 RAMCAS [1] Out Address strobe (Upper bit), (To 16M_DRAM: IC3002)
235 RAMOE Out Output enable (L: active), (To 16M_DRAM: IC3002)

26 VDDS - Power supply

93 RAMDATA [0]
154 RAMDATA [1]
202 RAMDATA [2]
237 RAMDATA [3]

27 RAMDATA [4]

94 RAMDATA [5]
155 RAMDATA [6]
238 RAMDATA [7]
203 VDD - Power supply

28 - - Not used

95 RAMDATA [8]
156 RAMDATA [9]
239 RAMDATA [10]
204 RAMDATA [11]

29 RAMDATA [12]

96 RAMDATA [13]
157 RAMDATA [14]
240 RAMDATA [15]

30 GND - Ground

97 XRESET In Reset pulse input, (From DECK CPU: IC1401)
205 GND - Ground
158 CPUALE In Bus address strobe signal input, (From DECK CPU: IC1401)

31 XCPUDSTB [0] In Bus memory write enable signal input, (From DECK CPU: IC1401)
241 XCPUDSTB [1] In Bus memory read enable signal input, (From DECK CPU: IC1401)

98 XCPURW In Bus read/write select signal input, (From DECK CPU: IC1401)
206 XCPUCS In Chip select input, (From DECK CPU: IC1401)
159 - - Not used

32 XINT - Open (Not used)

99 CPUWAIT In Wait command, (From DECK_CPU: IC1401)

33 CPUAD [0]
160 CPUAD [1]
100 CPUAD [2]

34 CPUAD [3]
161 VDD - Power supply
101 CPUAD [4] In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)

In/Out Audio/Shuffle/ECC memory data I/O, (From/To 16M_DRAM: IC3002)

In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)

In/Out Audio/Shuffle/ECC memory data I/O, (From/To 16M_DRAM: IC3002)

Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (3/6)

2-32

••••

Deck DSP (IC3001: JCY0106-2) pin functions (4/6)

Pin No. Label In/Out Description

35 CPUAD [5]
162 CPUAD [6]
102 CPUAD [7]

36 GND - Ground
103 - - Not used

37 CPUAD [8]
163 CPUAD [9]
207 CPUAD [10]
242 CPUAD [11]
104 VDDS - Power supply

38 CPUAD [12]
164 CPUAD [13]
105 CPUAD [14]
208 CPUAD [15]

39 VDD - Power supply
243 CPUWAITH - H: Fixed (Not used)
165 VDD - Power supply
106 TESTIO [0]

40 TESTIO [1]
209 TESTIO [2]
166 TESTIO [3]
107 TESTIO [4]

41 TESTIO [5]

42 TESTIO [6]
108 TESTIO [7]
167 - - Not used
210 VDDS - Power supply
244 TESTIO [8]

43 TESTIO [9]
109 TESTIO [10]
168 TESTIO [11]
211 TESTIO [12]
245 TESTIO [13]

44 TESTIO [14]
110 TESTIO [15]
169 GND
246 GND
212 TESTIO [16]

45 TESTIO [17]
111 TESTIO [18]
170 TESTIO [19]
247 TESTIO [20]
213 TESTIO [21]

In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)

Open (Not used)-

In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)

In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401)

Ground -

Open (Not used)-

Open (Not used)-

Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (4/6)

2-33

••••

Deck DSP (IC3001: JCY0106-2) pin functions (5/6)

Pin No. Label In/Out Description

46 TESTIO [22]
112 TESTIO [23]
171 VDD - Power supply
248 - - Not used

47 SCANENABLE
113 SCANMODE
214 TRST In Reset signal input for boundary scan
172 TDI - H: Fixed (Not used)

48 TCK - L: Fixed (Not used)
249 TMS - H: Fixed (Not used)
114 TDO - Open (Not used)
215 TEST - L: Fixed (Not used)
173 VDD - Power supply

49 PHYDATA [3]
115 PHYDATA [2]

50 PHYDATA [1]
174 PHYDATA [0]
116 VDDS - Power supply

51 SCLK Out IEEE1394 system clock (49.152MHz), (To 1394PHY:IC3101)
175 LOCONT - H: Fixed
117 XPHYISO Out Link interface isolation status (H: Enable), (To 1394PHY: IC3101)

52 PHYCTL [1]
176 PHYCTL [0]
118 PHYLREQ - IEEE1394 link request signal output, (To 1394PHY:IC3101)

53 GND - Ground
119 VDD - Power supply

54 EXTCLKIN
177 EXREQ
216 EXRW - H: Fixed (Not used)
250 EXREADEMPTY
120 EXWRITEFULL

55 VDDS - Power supply
178 - - Not used
121 EXTDATA [0]
217 EXTDATA [1]

56 EXTDATA [2]
251 EXTDATA [3]
179 EXTDATA [4]
122 EXTDATA [5]

57 EXTDATA [6]
218 EXTDATA [7]
180 VDD - Power supply
123 GND - Ground

In/Out Link interface data input/output, (From/To 1394PHY: IC3101)

Open (Not used)-

L: Fixed (Not used)-

L: Fixed (Not used)-

Link interface control (H: output), (From/To 1394PHY: IC3101)In/Out

Open (Not used)-

Open (Not used)-

Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (5/6)

2-34

••••

Deck DSP (IC3001: JCY0106-2) pin functions (6/6)

Pin No. Label In/Out Description

58 PWM405O Out 40.5MHz (PLL control output) 1/2 frequency of VCO405I, (To DVANA: IC3301)

59 VDDS
124 VDD
181 VCO405I In 81MHz VCO reference clock input, (From DVANA: IC3301)
219 VCO405O - Open (Not used)
252 GND - Ground

60 VDD - Power supply
125 CLK81SEL In H: Fixed (Not used)
182 FRRES - L: Fixed
220 FRREF In Frame reference signal input, (From DECK CPU: IC1401)
253 SERVOFRREF - Open (Not used)

61 TRKREF In Drum servo reference signal input (150Hz), (From DECK CPU: IC1401)
126 SERVOTRKREF - Open (Not used)
183 GND - Ground
254 - - Not used
221 PF [0]

62 PF [1]
127 SBE Out Sync block error (Error pulse output)
184 HID
255 HSP
222 - - Not used

63 PBDATA In VITERBI processing termination playback data input, (From DVEQ: IC3201)
128 PBCLK In VITERBI processing termination playback clock input, (From DVEQ: IC3201)
185 VDDS - Power supply
256 TPNO [0]

64 TPNO [1]
129 TPNO [2]
223 RECDATA Out HSE (record data) output, (To PRE/REC: IC3501)
186 RECCTL Out Recording current control (H: ON), (To DVANA: IC3301)

65 SPA Out Pulse output for ATF sample, (To DVEQ: IC3201)
225 RECCLK Out Recording reference clock 41.85MHz
130 GND - Ground
224 VCCA - Power supply
187 VCO4185 - Constant for 41.85MHz VCO

66 GNDA
131 GND

67 OSC4185I - L: Fixed (Not used)
188 OSC4185O - Open (Not used)
132 VDD

68 VDD
133 GND - Ground

Head switch pulse (CH1: H, CH2: L), (To DECK CPU: IC1401)Out

Power supply-

Open (Not used)-

Ground-

Power supply-

Open (Not used)-

Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (6/6)

2-35

2.5.9 Audio AMP IC function

1. Audio AMP (IC2201: AK4560VQ) pin locations and block diagram

EQ_N_R
PRE_O_R
PRE_N_R

INT MIC Rch

MRF

MVCM 2V

GND (MVDD)

MVDD

INT MIC Lch

EXT MIC Lch

MA BIAS 2V

PRE_N_L
PRE_O_L

EQ_N_L

EQ_P_R

EQ_O_R

HPF_P_R

HPF_O_R

MIC_IN_R

MIC SEL

SPK-NDSPK+PDMCLK

LRCK

BCLK

CCLK

HPF_P_L

HPF_O_L

MIC_IN_L

VCOM 1.5V

VREF1.5V

GND (VA)

VA3V

LINE OUT2 Rch

OPGR

LINE OUT2 Lch

OPGL

BEEP

SHT

AVR OUT

CS
DATA
SDTI
SDTO
GND (VD)
VD 3V
A_MUTE
HP OUT Lch
HP OUT Rch
HVDD 4.8V
HVCM 2.4V
LINE OUT Rch
LINE IN Rch
LINE OUT Lch
LINE IN Lch
SP IN

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

48

47

46

45 44 43 42 41 40 39 38 37 36 35 34 33

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MPWR 3.3V

EXT MIC Rch

EQ_O_L

EQ_P_L

GND (SVDD)

SVDD 4.8V

Control

Register

I/F

MIX

Audio I/F

Controller

HPF

A/D Converter
D/A Converter

Clock

Divider

MIX

MIX

HPF
OFF

ON

EXT

INT

VOL.

VOL.

AVR

OUT

BEEP

SIG

BEEP

SIG

Lch ALC AMP

MIC

LINE

Rch ALC AMP

MIC

LINE

ON

HPF
OFF

INT
EXT

INT

EXT

EXT

INT

Fig. 2-5-8 Audio AMP (IC2201: AK4560VQ) pin locations and block diagram

2-36

2. Audio AMP (IC2201: AK4560VQ) pin functions (1/2)

Pin No. Label In/Out Description

1 EQ_P_L In L-ch EQ-Amp positive input
2 EQ_O_L Out L-ch EQ-Amp output
3 HPF_P_L In L-ch HPF-Amp positive input
4 HPF_O_L Out L-ch HPF output
5 MIC_IN_L In L-ch MIC input
6 VCOM (1.5V) Out Common voltage output, (1/2VA)
7 VREF (1.5V) Out ADC, DAC reference level, (1/2VA)
8 GND (VA) - Analog ground

9 VA (3V) - Analog power supply, (3.0V)
10 LINE OUT2 (Rch) Out R-ch No. 2 line output -5.5dBV×VA=2.8V
11 OPGR In R-ch analog volume input
12 LINE OUT2 (Lch) Out L-ch No. 2 line output , -5.5dBV´VA=2.8V
13 OPGL In L-ch analog volume input
14 BEEP In Beep signal input
15 SHT In Shutter signal input
16 AVR OUT Out Analog mixing output
17 SP IN In ALC2 input
18 LINE IN (Lch) In L-ch line input
19 LINE OUT (Lch) Out L-ch No. 1 line output, +2dBV×VA=2.8V, VOL=+7.5dB
20 LINE IN (Rch) In R-ch line input
21 LINE OUT (Rch) Out R-ch No. 1 line output, +2dBV×VA=2.8V, VOL=+7.5dB
22 HVCM (2.4V) Out LINEOUT & HP-Amp common voltage output, (1/2HVDD)
23 HVDD (4.8V) - LINEOUT & HP-Amp power supply, (4.8v)
24 HP OUT (Rch) Out R-ch Headphone-Amp output
25 HP OUT (Lch) Out L-ch Headphone-Amp output
26 A_MUTE In Mute control, (L: Normal operation, H: Mute)
27 VD (3V) - Digital power supply, (3.0V)
28 GND (VD) - Digital ground
29 SDTO Out Audio serial data output
30 SDTI In Audio serial data input
31 DATA

In/Out

Control data I/O

32 CS In Chip select

Table 2-5-5 Audio AMP (IC2201: AK4560VQ) pin functions (1/2)

2-37

••••

Audio AMP (IC2201: AK4560VQ) pin functions (2/2)

Pin No. Label In/Out Description

33 CCLK In Control clock input
34 BCLK In Audio serial data clock
35 LRCK In Input/Output channel clock
36 MCLK In Master clock input
37 PD In Power down & reset, (L: Power- down & reset, H: Normal operation)
38 SPK+ Out Speaker Amp positive output
39 ND In Noise decrease (L: Disable, H: Enable)
40 SPK- Out Speaker Amp negative output
41 MIC SEL In Internal/External MIC detect, (L: Internal MIC, L: External MIC)
42 GND (SVDD) - Speaker Amp ground
43 SVDD (4.8V) - Speaker Amp power supply, (4.8V)
44 MIC_IN_R In R-ch MIC input
45 HPF_O_R Out R-ch HPF output
46 HPF_P_R In R-ch HPF-Amp positive input
47 EQ_O_R Out R-ch EQ-Amp output
48 EQ_P_R In R-ch EQ-Amp positive input
49 EQ_N_R In R-ch EQ-Amp negative input
50 PRE_O_R Out R-ch Pre-Amp output
51 PRE_N_R In R-ch Pre-Amp negative input
52 MPER (3.3V) - Not used
53 EXT MIC (Rch) In External MIC Rch input
54 INT_MIC (Rch) In Internal MIC Rch input
55 MRF Out MIC power supply ripple filter
56 MVCM (2V) Out MIC block common voltage output
57 GND (MVDD) - MIC block ground
58 MVDD (4V) - MIC block power supply
59 INT_MIC (Lch) In Internal MIC Lch input
60 EXT_MIC (Lch) In External MIC Lch input
61 MA_BIAS (2V) In MIC-Amp bias
62 PRE_N_L In L-ch Pre-Amp negative input
63 PRE_O_L Out L-ch Pre-Amp output
64 EQ_N_L In L-ch EQ -Amp negative input

Table 2-5-5 Audio AMP (IC2201: AK4560VQ) pin functions (2/2)

2-38

2.6 SYSCON CPU

2.6.1 Contents of SYSCON CPU processing

1) User I/F control

•

Recognition of Operation Keys and Menu

•

Holding the User Configurations

2) Camera signal process control

•

TG/CDS IC

•

Camera DSP IC (Y/C Process, Special Effect, Encoder, OSD Mix, EVR etc.)

3) Camera Auto system control

•

Transferring Auto system data with Camera DSP IC

•

AF / AE / AW / EIS control

•

Lens MDA control

4) Audio control

5) VF / LCD Monitor control

6) Servo CPU control

7) PC I/F control (TCCS / JLIP)

8) Remote control

9) Power control (Power ON / OFF)

10) RTC, Auto Light, RAE and others

2.6.2 Power ON process

START

S W Stable ?

SW Position

DC/DC

Converter ON

CAMERA DSP

Reset relese

VD Pulse ?

Sleep mode

setting

END

1

1

Reset start ?

EEPROM

Data read

Prepherals

CPU

Initialize

VD Pulse ?

END

Yes

No

ON

OFF

Yes

No

No

Yes

No

Yes

Fig. 2-6-1 Power ON process flow chart

2-39

2.6.3 System composition

SYSCON CPU adopted with this m odel has five data communication systems and communicates with
each peripheral device using those ports. There are three synchronous serial communication systems;
one of these is used only for the model having DSC function. The communication with the Camera DSP is
required a high-speed performance for transferring the information and command of camera auto
processing. Therefore, it is adopted the 16-bit parallel bus communication. And the asynchronous serial
communication (UART) is used for communication with external (PC, etc.).

SYSCON

CPU

TG

V.DRV

CDS / AGC

ADC

FOCUS

ZOOM

MDA

AUDIO

VF / LCD

DRVER

CAMERA

DSP

POWER

SUPPLY

REMOTE

KEY

PC I/F

(TCCS / JLIP)

RTC EEPROM

DECK

CPU

DECK

DSP

MDA MECHA

16-bit

Multiplex bus

Synchronous Serial Communication

Back Up
Built-in Lithium
Battery

UART

DSC IF

M32 R/D

CPU

FRASH

ROM

*DSC model only

Synchronous Serial Communication Synchronous Serial Communication

Fig. 2-6-2 SYSCON CPU system structure

2-40

2.6.4 SYSCON CPU block diagram

IC1001 SYSCON CPU

CAMERA

DSP

IC4001

CDS/AGC

A/D

IC5601

TG

V.DRIVER

IC5502

IRIS DRV

&

HALL AMP

FOCUS/

ZOOM

DRIVER

IC4851

IC1004

EEPROM

IC1003

RTC

IC8001

DSC_IF

M32_R/D

CPU

IC8002

IC8003

16Mbits

(2MB)

FLASH

ROM

61 CLK_OUT
60 DATA_OUT
80 TG_CS

124 CDS_CS

28 F/Z_CS
114 F/Z_RST

120 IRIS_O/C

77 HOLE_AD

3-6,9-15
18-22

16

BUS0-15

94 CLWE
95 CHWE
96 CRE

115 RWSEL
117 KRST/CLR

S_DT_OUT 57

S_DT_IN 56

EEPROM_CS 49

RTC_CS 92

39 VD
33 MFLD
40 OMT

122 TG_RST

124 CCD_KIZU

IR_A/D 76

WB_IR_DET 27

M32_CLK 67

M32_DOUT 66

M32_CS 41

16

24

PC_IF

TXD 63

RXD 62

JLIP_INT 38

79 F_PTR_AD

OPTICAL

BLOCK

RTC_INT 44

ZOOM

UNIT

DECK_OPE

PHOTO_SW 36

DIAL_MN 102

DIAL_AUTO 103

DIAL_OFF 104

DIAL_PLAY 105

TRIG_SW 101

SEL_SW 100

108 MONITOR_SW

73 KEY_A

KEY_A

STOP
REW
FF
PLAY/PAUSE
DSC

KEY_B

LIGHT_SW

EEP

ROM

IC7603

59 DATA_IN

LIGHT_SW

LAMP_ON 2

REG

DC

LIGHT

Li +

LITHIUM

X1002

111 LCD_CS1

LCD

DRV

IC7601

47 LCD_LOAD

AUDIO

64 AUDIO_CS

CLK4M5

CAM_VD

IRIS_PWM

78 Z_PTR_AD
82 OP_THRMO

S_CLK 58

IC1401

DECK

CPU

SRV_CS 26

SRV_RST 89

DSC_IF

REG_4.8V

PWR_LED

MENU_SET_SW 91

MENU_P_B 110

MENU_P_A 42

ZOOM_SW 75

74 KEY_B

97 CALE

ODD_EVEN 125

JLIP

PC

EDIT_CTL 118

JLIP_L 93

SRV_RDY 17

M32_DIN 65

DSC_RST 81

DSC_PCTL 88

126 ND_H

127 PD_L
128 A_MUTE

123 S_MUTE

V_MUTE 37

MONITOR

85 MONI_RVS

1 EL_CTL

54 MONI_UD
53 MONI_CTL
46 VF_MONI

PWR_CTL 16

BATT_CHK 72

VF_CTL 48

V OUT

113 ASPECT1
116 ASPECT2

JUNCTION

EJECT_SW 106

CAS_SW 107

MECHA

RST

IC10103VIC1009

RST 35

REAR

BATT_SW 84

JACK

REMOTE 55

TALLY 52

AV_DET 45

S_DET 43

Fig. 2-6-3 SYSCON CPU block diagram

2-41

2.6.5 SYSCON CPU (IC1001: MN1021617HL) pin functions (1/3)

Pin No. Label In/Out Description

1 EL_CTL Out Strobe emission control (To EL driver: IC756)

2 LAMP_ON Out Video light ON/OFF

3BUS0

4BUS1

5BUS2

6BUS3

7 VDD - Power supply

8 VSS - GND

9BUS4
10 BUS5
11 BUS6
12 BUS7
13 BUS8
14 BUS9
15 BUS10
16 PWR_CTL Out Power control
17 SRV_RDY In Ready signal (From DECK_CPU: IC1401)
18 BUS11
19 BUS12
20 BUS13
21 BUS14
22 BUS15
23 MODE0 In L: Fixed
24 MODE1 In L: Fixed
25 MODE2 In H: Fixed (VDD)
26 SRV_CS Out Chip select (To DECK_CPU: IC1401)
27 WB_IR_DET In Flicker detect
28 F/Z_CS Out Chip select (To F/Z DRIVER: IC4851)
29 VDD - Power supply
30 OSCI In System clock (24MHz)
31 OSCO Out System clock (24MHz)
32 VSS - GND
33 MFLD In Field discrimination signal
34 NMI In H: Fixed
35 RST In Reset
36 PHOTO_SW In Snap shot switch input
37 V_MUTE Out Video mute
38 JLIP_INT In JLIP interrupt
39 VD In Vertical sync signal
40 OMT In EIS data readout timing
41 M32_CS In Chip select (From DSC_IF: IC800)
42 MENU_P_A In Menu dial pulse
43 S_DET In S terminal connection detect signal input

Address/Data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)

Address/data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)

In/Out

In/Out Address/Data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)

In/Out

Table 2-6-1 SYSCON CPU (IC1001: MN1021617HL) pin functions (1/3)

2-42

••••

SYSCON CPU (IC1001: MN1021617HL) pin functions (2/3)

Pin No. Label In/Out Description

44 RTC_INT In Clock 1 sec. Interrupt
45 AV_DET In AV plug connection detect signal input
46 VF_MONI Out VF/MONI select signal
47 LCD_LOAD Out LCD data load pulse
48 VF_CTL Out VF_REG4.8V ON/OFF control
49 EEPROM_CS Out Chip select signal (To EEPROM: IC1003)
50 VDD Out Power supply
51 TIMER_OUT - Not used
52 TALLY Out Tally lamp
53 MONI_CTL Out MONI_LCD back light control
54 MONI_UD Out MONI_LCD L/R UP/DOWN reverse control
55 REMOTE In Remote control input
56 S_DT_IN In Serial data input (From DECK_CPU EEPROM RTC)
57 S_DT_OUT Out Serial data output (To DECK_CPU TG/VDRIV CDS/AGC/ADC EEPROM RTC)
58 S_CLK Out Serial clock
59 DATA_IN In Serial data input (From: IC7603 LCD_SD)
60 DATA_OUT Out Serial data output
61 CLK_OUT Out Serial clock output
62 RXD Out RS232C data input
63 TXD In RS232C data output
64 AUDIO_CS Out Chip select signal to AUDIO IC2200
65 M32_DIN In Serial data input (From DSC_IF: IC8001)
66 M32_DOUT Out Serial data output (To DSC_IF: IC8001)
67 M32_CLK In Serial clock input (From DSC_IF: IC8001)
68 VDD - Power supply
69 VSS - GND
70 AVSS - GND
71 VRefL - Reference power supply
72 BATT_CHK In Battery DC input
73 KEY_A In Deck operation switch input
74 KEY_B In Camera operation switch input
75 ZOOM_SW In Zoom switch input
76 IR_AD In AWB IR sensor AD input
77 HALL_AD In Iris hall generator AS input
78 Z_PTR_AD In ZOOM position sensor AD input
79 F_PTR_AD In FOCUS position sensor AD input
80 TG_CS Out Chip select signal to TG/V.DRV IC5501
81 DSC_R_ST Out Reset signal output (To DSC_IF: IC8001)
82 OP_THRMO In OP thermo detect signal input
83 - - Not used
84 BATT_SW In DC pulg installation detect
85 MONI_RVS In LCD reverse switch input
86 VRefH - ADC power supply (REG3V)

Table 2-6-1 SYSCON CPU (IC1001: MN1021617HL) pin functions (2/3)

2-43

••••

SYSCON CPU (IC1001: MN1021617HL) pin functions (3/3)

Pin No. Label In/Out Description

87 AVDD - Power supply
88 DSC_PCTL Out Power control (To DSC_IF: IC8001)
89 SRV_RST Out Reset signal (To DECK_CPU: IC1401)
90 OEM_REG5_CTL Out Not used
91 MENU_SET_SW In Menu set switch input
92 RTC_CS Out Chip select signal (To RTC: IC1004)
93 JLIP_L Out PC connection terminal switch (L: JLIP terminal, H: PC terminal)
94 CLWE Out Write enable
95 CHWE Out Write enable
96 CRE In Read enable
97 CALE Out Address latch enable
98 VDD - Power supply
99 VSS - GND

100 SEL_SW In Snap shot mode switch
101 TRIG_SW In Trigger switch
102 DIAL_MANUAL In Dial MANUAL
103 DIAL_AUTO In Dial AUTO
104 DIAL_OFF In Dial OFF
105 DIAL_PLAY In Dial PLAY
106 EJECT_SW In EJECT switch detect
107 CAS_SW In Cassette switch detect
108 MONITOR_SW In Monitor OPEN/CLOSE switch detect
109 - - Not used
110 MENU_P_B In Menu dial pulse
111 LCD_CS1 Out Chip select signal (To LCD EEPROM: IC7603)
112 RESERVE - L: fixed
113 ASPECT1 Out S2 terminal output
114 F/Z_RST Out Reset signal (To F/Z DRIVER: IC4851)
115 RWSEL Out Read and write select (To CAMERA_DSP: IC4301)
116 ASPECT2 Out S2 terminal output
117 KRST/CLR Out Shutter sound reset/clear signal (To CAMERA_DSP: IC4301)
118 EDIT_CTL Out JLIP remote pause output terminal (Edit terminal)
119 VDD(VPP) - Power supply
120 IRIS_O/C Out Iris OPEN/CLOSE
121 CDS_CS Out Chip select signal (To CDS/AGC/AD: IC5601)
122 TG_RST Out Reset signal (To TG/V.DRV: IC5501)
123 S_MUTE Out Shutter sound mute
124 CCD_ KIZU Out Blanking ON/OFF control (at white noise adjustment)
125 ODD_EVEN In Odd/Even field discrimination signal at slow playback
126 ND_H Out Noise decreasing circuit control (L: OFF, H: ON)
127 PD_L Out Power down signal output (L: power down)
128 A_MUTE Out Audio mute

Table 2-6-1 SYSCON CPU (IC1001: MN1021617HL) pin functions (3/3)

2-44

2.7 DECK CPU

2.7.1 Contents of DECK CPU processing

1) Mechanism control

•

Loading motor control

•

Drum motor control

•

Capstan motor control

2) Deck LSI control

•

DV DSP IC control

•

PRE / REC IC control

3) OSD control

•

On screen process

4) 1394 control

5) Sensor control

•

Tape sensor

•

Reel sensor

•

DEW sensor

•

Emergency process

2.7.2 DECK system composition

SYSCON

CPU

MDA

MECHA

DECK

DSP

DV_EQ

ON

SCREEN

PC I/F

UART

DV_ANA

PRE / REC

1394

PHY

DV

Terminal

DECK

CPU

16M

DRAM

16-bit

Parallel bus

Synchronous Serial

Communication

Synchronous Serial

Communication

16-bit

Multiplex bus

Fig. 2-7-1 DECK CPU system structure

2-45

2.7.3 Tracking Error information

( 0 )( 9 ) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 0 ) ( 1 )

Flame Pulse

Track Pulse

(Track reference

Number)

HID

(HEAD SW)

Tape pattern

(Pilot signal)

( f1 ) ( f0 ) ( f2 ) ( f0 ) ( f1 ) ( f0 ) ( f2 ) ( f0 ) ( f1 ) ( f0 ) ( f2 ) ( f0 ) ( f1 )

HEAD

FFh

80h

00h

Tracking Error

Tracking is the

center

Tracking is off (1) Tracking is off (2)

(CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2)

Fig. 2-7-2 Tracking Error explanation (NTSC)

Fig. 2-7-2 shows the tracking error detection m ethod. The DVC multirecords three kinds of pilot signals of
f0 (0), f1 (465 kHz) and f2 (697.5 kHz) on each track. When the CH1 head traces the track on which the f0
pilot signal is recorded in playback, the crosstalk component of the pilot signals of f1 and f2 recorded on
the preceding and following tracks are detected and compared. When the tracking is well controlled, the
error rate is 80h that is the intermediate value between 00h and FFh. When the tracking deviates in the f1
track side, the error rate is lower than 80h. When the tracking deviates in the f2 track side, the error rate is
higher than 80h. When the CH2 head is tracing the track, the error rate is 00h or FFh because only the f1
or f2 component is detected.
Such the tracking error information is digitally processed by the ATF inside the DV-EQ IC and the
processed data is transmitted to the DECK CPU through the 16-bit bus. The DECK CPU controls the
capstan servo according to the data transmitted from the DV-EQ IC.

2-46

2.7.4 1394 interface control

The DECK CPU has the function of the host microcomputer of the 1394 interface. It mainly controls the
LINK IC, PHY IC and 1394 bus besides AV/C command processing. The AV/C command is classified into
the VCR control commands such as for PLAY, STOP, FF, REW, REC operations and for status information
such as time code, mode status, etc.
For details of the 1394 interface (i.LINK), refer to the Technical Guide to the i.LINK.

DECK

CPU

DECK_DSP

1394
PHY

DV

Terminal

1394
LINK

IC1401

IC3001

IC3101

Fig. 2-7-3 1394 interface block

2.7.5 JLIP Video Capture

The DECK CPU incorporates the asynchronous serial communication (UART) port for communication with
external equipment (personal computer, etc.). The UART port is used for image data transmission for
inputting DVC playback picture that is captured by use of the JLIP Video Capture into a personal computer .
When a DVC playback picture is captured, playback data for 1 frame is once held by the DRAM and then
transmitted to the DECK CPU through the 16-bit bus and it is finally output from the UART port to a
personal computer. The image data transmitted to a personal computer is formatted in the DV stream, and
the personal computer encodes the DV data with the software.

DECK

CPU

DECK_DSPPC IF

PC

Terminal

16M

DRAM

IC1401

IC3001

IC3002

16-bit

Parallel bus

UART

Fig. 2-7-4 JLIP Video Capture output

2-47

2.7.6 DECK CPU block diagram

IC1401 DECK CPU

IC3001

DECK_DSP

DV_EQ

IC3201

IC1601

MDA

IC3301

DV_ANA

ANA_CLK 109

ANA_OUT 93

ANA_CS 14

MDA_CS 195

MECHA

SENSOR

135 REC_SAFE

148 CAM0
132 CAM1
136 CAM2

230 S_REEL
189 T_REEL

134 REEL_LED
187 TAPE_LED

199 S_SENS
182 E_SENS

DRUM_FG 238

DRUM_PG 196

DRUM_REF 191

CAP_FG 173

CAP_REF 221

CAP_BRAKE 1

PRE/REC

IC3501

72 OSCI

DEW

SENSOR

200 DEW_SENS

A_REG_3V

16

DV_CS 104

ADM0-15

EQ_CS 85

WE0 12

RE 24

OK 37

RWSEL 5

AS 47

DV_RST 99

EQ_RST 120
EQ_TRST 83

IC3101

1394
PHY

PHY_PD 3

PHY_RST 61

PHY_CNA 15

DV

HID 207

FRP 190

TSR 218
TSR 231

SPA 174

HID_IN 219

42

PD0-3

PC0-1

ANA_IN 108

MDA_IN 94

MDA_CLK 91

DRUM_FG 201

DRUM_FG 229

LD_ON 27

TG

V.DRV

IC5501

SYSCON

CPU

IC1001

89 SYS_CLK
74 SYS_OUT
78 SYS_IN

180 MSELECT

237 SRV_RDY
55 RESET

100 ODD_EVEN
16 VMUTE_IN

CAMERA

DSP

IC4301

188 VD

ON

SCREEN

28 OSD_CS
75 OSD_CLK
58 OSD_DATA

IC1002

PBH 117
REC_I 116
HID_3 119

V_PB_L 84 REG_4.8V

184 BCID1
181 BCID2
183 BCID3

42 MIC_SDA
57 MIC_SCL

29 MIC_CTL

A_REG_3V

16M-DRAM

SYSCON

CAS_SW
EJT_SW

ROTARY

ENCODER

PC_IF

DSC_IF

JLIP

PC

59 RXD

77 TXD

16
10

JUNCTION

DV_INT 226
DV_INT 204

ANA_PD 45 VCOAUD

REG

65 D_GAIN

Fig. 2-7-5 DECK CPU block diagram

2-48

2.7.7 Deck CPU (IC1401: MN103004KRH) pin functions (1/5)

Pin No. Label In/Out

Description

1 CAP_BRK Out Capstan motor brake control
27 LD_ON Out Loading motor ON/OFF control
14 ANA_CS Out Chip select signal (To DV_ANA: IC3301)
28 OSD_CS Out Chip select signal (To OSD: IC1002)

2 VSS - GND
29 MIC_CTL Out Power supply control to MIC

3 PHY_PD Out Power down control (To PHY: IC3101)
61 PHY_RST Out Reset output (To PHY: IC3101)
15 PHY_CNA In IEEE1394 connection detect (Connect: L)
45 ANA_PD Out Power down control (To DV_ANA: IC3301)
16 VMUTE_IN In Video mute input
46 -

4­30 VDDH - Power supply (REG_3V)
31 ­62 -

5 RWSEL Out Read/write select signal of Bus
47 AS Out Address strobe signal of Bus
17 ­63 ­49 ­32 VSS - GND
18 ­79 -

6­48 ­64 -

7­65 D_GAIN Out Drum error gain control
19 VDDB - Power supply (REG_3V)
33 ADM15
20 ADM14
82 ADM13
50 ADM12
66 ADM11

8ADM10
67 ADM9
51 ADM8
34 VSS - GND

9ADM7
35 ADM6
21 ADM5
52 ADM4
10 ADM3
36 ADM2
22 ADM1
23 ADM0

In/Out

In/Out

Not used-

Not used-

Not used-

Not used-

Address/Data MPX BUS 16bits (From/To DECK_DSP: IC3001, DVEQ: IC3201)

Address/Data MPX BUS 16bits (From/To DECK_DSP: IC3001, DVEQ: IC3201)

Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (1/5)

2-49

••••

Deck CPU (IC1401: MN103004KRH) pin functions (2/5)

Pin No. Label In/Out

Description

11 VDDB - Power supply (REG_3V)
37 DK(L) In Servo CPU ready signal (Low: Deck mode)
24 RE(L) Out Read enable signal
38 WE1(L) - Test terminal (TL1401)
12 WE0(L) Out Write enable signal
40 PVDD - Power supply (REG_3V)
53 PVSS - GND
56 MMOD1 ­54 MMOD0 ­55 RESET(L) In Reset input (From SYSCON CPU: IC1001)
70 FRQS - L: fixed
71 VSS - GND
69 EXMOD1 - H: fixed
68 EXMOD0 - H: fixed
72 OSCI In 27MHz clock input (Form TG/V.DRV: IC5501)
88 OSCO - Test terminal (TL1423)
86 VDDH - Power supply (REG_3V)
87 SYSCLK - Test terminal (TL1433)
85 EQ_CS Out Chip select signal (To DV_EQ: IC3201)

104 DV_CS Out Chip select signal (To DECK_DSP: IC3001)
102 CS1(L) - Test terminal (TL1402)
103 CS0(L) - Test terminal (TL1403)
101 VDD - Power supply (REG_3V)
100 ODD_EVEN Out Odd/Even field discrimination signal at slow playback (FRAME ADVANCE)

84 V_PB_L Out Video track area recording off signal
99 DV_RST Out Reset signal output (To DECK_DSP: IC3001)
83 EQ_TRST Out Reset signal output (To DV_EQ: IC3201) (For Boundary scan)

120 EQ_RST Out Reset signal output (To DV_EQ: IC3201)
118 VSS - GND
119 HID_3 Out Head switch pulse (control of recording current measure circuit)
116 REC_I Out ON/OFF control for recording circuit (To PRE/REC IC)
117 PBH Out ON/OFF control for playback circuit (To PRE/REC IC)
134 REEL_LED Out Reel sensor LED control
135 REC_SAFE In REC safety switch
133 VDDH - Power supply (REG_3V)
136 CAM2
132 CAM1
148 CAM0
149 AVSS - GND
152 ­150 ­151 ­147 -

In

- Not used

Control port for FLASH CPU

Mechanism position detect from rotary encoder

Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (2/5)

2-50

••••

Deck CPU (IC1401: MN103004KRH) pin functions (3/5)

Pin No. Label In/Out

Description

164 ­166 ­167 ­163 ­168 ­165 ­183 BCID3
181 BCID2
184 BCID1
200 DEW_SENS In Dew sensor detect
182 E_SENS In End sensor detect
199 S_SENS In Start sensor detect
198 VREFH - Reference voltage
216 AVDD - Power supply (REG_3V)
214 ADTRG(L) In H: fixed
239 NMI(L) In H: fixed
213 VSS - GND
240 ­197 ­227 ­212 ­226 DV_INT In DV_DSP interrupt signal
196 DRUM_PG In Drum PG
238 DRUM_FG I n Drum FG
180 MSELECT In DECK_CPU chip select input (Form SYSCON CPU: IC1001)
225 VDD Power supply (REG_3V)
195 MDA_CS Out Chip select signal to MDA IC1601
237 SRV_RDY Out DECK_CPU ready signal output (To SYSCON CPU: IC1001)
179 AGC_RST Out Video output clamp control (To A/V OUT SECTION)
211 ­210 ­236 ­194 ­224 ­209 VSS - GND
235 ­178 ­223 ­193 ­208 -

- Not used

Not used-

-

In

- Not used

Cassette tape ID board information

Not used

Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (3/5)

2-51

••••

Deck CPU (IC1401: MN103004KRH) pin functions (4/5)

Pin No. Label In/Out

Description

162 ­222 ­177 ­234 ­192 VDDH - Power supply (REG_3V)
207 HID Out Head switch pulse output
176 - - Not used
233 - - Not used
191 DRUM_REF Out Drum offset voltage output (To MDA: IC1601)
221 CAP_REF Out Capstan offset voltage output (To MDA: IC1601)
175 ­232 ­159 ­220 ­206 VSS - GND
231 STR In HID reference (Drum 150Hz reference)
190 FRP In Frame pulse (From DECK_DSP: IC3001)
204 DV_INT In DV_DSP interrupt signal
174 SPA In Pulse for ATF sample
219 HID_IN In Head switch pulse input
205 VDD - Power supply (REG_3V)
230 S_REEL In SUP reel pulse
189 T_REEL In TU reel pulse
218 STR In HID reference (Drum 150Hz reference)
173 CAP_FG In Capstan FG
229 DRUM_FG I n Drum FG
203 - - Not used
201 DRUM_FG I n Drum FG
187 TAPE_LED Out Tape sensor LED control
185 VSS - GND
188 VD In Vertical reference pulse (Form CAMERA_DSP: IC4301)
186 ­171 ­169 ­172 ­170 VDD - Power supply (REG_3V)
158 ­154 ­156 ­153 ­157 ­155 VSS - GND

- Not used

Not used-

- Not used

Not used-

Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (4/5)

2-52

••••

Deck CPU (IC1401: MN103004KRH) pin functions (5/5)

Pin No. Label In/Out

Description

140 ­138 ­142 ­139 ­141 ­137 ­124 VDDH - Power supply (REG_3V)
122 ­123 ­121 ­125 ­106 VPP - Power supply (REG_3V)
107 BR(L) - H: fixed
105 VSS - GND
109 ANA_CLK Out Serial clock (To DV_ANA: IC3301)
108 ANA_IN Out Serial data bus output (To DV_ANA: IC3301)

93 ANA_OUT In Serial data bus input (From DV_ANA: IC3301)
91 MDA_CLK Out Serial clock (To MDA: IC1601)
94 MDA_IN Out Serial bus data output (To MDA: IC1601)
90 VDD Power supply (REG_3V)
92 MDA_OUT In Serial bus data input (From MDA: IC1601)
89 SYS_CLK In Serial clock (From SYSCON CPU: IC1001)
78 SYS_IN Out Serial bus data output (To SYSCON CPU: IC1001)
74 SYS_OUT In Serial bus data input (From SYSCON CPU: IC1001)
76 - - Not used
73 VSS - GND
77 TXD Out RS232C output
59 RXD In RS232C input
75 OSD_CLK Out Serial clock (To OSD: IC1002)
58 OSD_DATA Out Serial bus data (To OSD: IC1002)
60 - - Not used
57 MIC_SCL Out Serial clock for MIC
43 VDDH Power supply (REG_3V)
42 MIC_SDA In Serial data for MIC
44 ­41 -

- Not used

- Not used

Not used-

Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (5/5)

SECTION 3

HEAD CLOG WARNING

3-1

3.1 HEAD CLOG WARNING OF DVC

The method and criterion of DVC head clog detection have been changed from this DVC series.
Differently from the previous models which detect head clog in the recording mode only, the new system
incorporated in this series detects head clog in both the recording and playback modes based on the new
detection criterion that is much more strict with possible error as compared with the previous system.
When the head clog warning is occurred on the DVC with the previous detection system, it is impossible to
play back the data correctly rather than the recording data is deteriorated. On the other hand, the DVC
with the new detection system warns the user about deterioration in recording signal because of head
clog.

3.1.1 Structure of Sync Blocks and Error correction

The structure of sync blocks and error correction of the DVC will be explained first. In the digital magnetic
recording and playback system, there is a possibility that random er ror and burst error caused by signal
dropout in tape occur. Generally, the data transmission systems which quality is not so good adopt the
packet data transmission system for the necessity of frequent reproducing (playback) synchronization.
Therefore, the DVC records dat a in the form of sync blocks.
One sync block of the AUDIO/VIDEO sector consists of 2 bytes of sync area, 3 bytes of ID code to identify
the attribute of data, and 85 bytes of inner codes. A definite sync pattern is recorded in each sync area. If
the definite sync pattern is not detected in playback, the data in the sync block cannot be restored and
played back. An ID code consists of 3 bytes, namely, 2 bytes of ID and 1 byte of ID parity. The content of
the ID of the AUDIO/VIDEO sector is 4 bits of a sequence number showing the continuity of frames, 4 bit s
of track pair number showing the track number, and 8 bits of sync block number showing the row of sync
blocks.
Since the 8-bytes inner parity is added to the AUDIO/VIDEO sector, maximum four errors can be corrected
by this 8-bytes parity and considerable random errors can be corrected also.
Moreover, the 11-bytes outer parity is added to the VIDEO data and 5-bytes outer parity is added to the
AUDIO data. Therefore, burst error caused by signal dropout in tape can be corrected by those parities.
As mentioned above, the optimum error correction strategy with the inner and outer parities is constructed
for intermingled random errors and burst errors in consideration of the dropout characteristic of the tape
medium to be used.
Number of sync blocks in the AUDIO sector is 17 (14 in the data area besides 2 pre-sync blocks and 1
post-sync block). Number of sync blocks in the VIDEO sector is 152 (149 in the data area besides 2 pre­sync blocks and 1 post-sync block).

Sync Area

ID

Code

AUDIO

AUX

(AAUX)

AUDIO DATA

Inner

Parity

Outer Parity

Sync block

number

012345 9 81 89
0
1
2
3
4
5

9

6
7
8

10
11
12
13
14
15
16

Byte-position number

Pre-sync
block (2)

Data-sync
block (14)

Post-sync

block (1)

Sync Block length : 90 Byte

5728

Fig. 3-1-1 Structure of sync blocks in audio sector

3-2

Sync Area

ID

Code

VIDEO AUX (VAUX)

VIDEO DATA

Inner

Parity

Outer Parity

Sync block

number

012345 9 81 89

18
19
20

Byte-position number

Pre-sync
block (2)

Data-sync

block
(149)

Post-sync

block (1)

Sync Block length : 90 Byte

77 8

17

21

156
157

167
168

VIDEO AUX (VAUX)

Fig. 3-1-2 Structure of sync blocks in video sector

The length of sync blocks of the sub code is just 12 bytes. The sub code has the fast search function to
search the target point at a high speed. In the fast search mode, if the tape speed is increased, the angle
that the head scans the track is decreased and the form of signals that can be read by one scanning
becomes like beads on an abacus. If data of sig nals read by one scanning are not grouped as a sync
block, those data cannot be decoded and played back. Therefore, the length of a sync block is shortened
to secure the reproducibility of data. Since the probability to pick up the outer parity is very low in the fast
search mode, no outer parity is prepared in the sub code differently from the AUDIO/VIDEO sector. In
order to secure the reproducibility and reliability of playback data, the same data is not only written twice in
different parts of a track but also written in a half of a frame (in 5 or 6 t racks). In other words, the same
data is written over and over 10 times or 12 times in the tracks of the first half of a frame. The next data is
multiply written in the second half of the frame in the same manner, namely, written 10 times or 12 times
repeatedly.

Sync Area

ID

Code

Sub-code

DATA

Inner Parity

Sync block

number

012345
0
1
2
3

7

4
5
6

8
9

10
11

Byte-position number

Data-sync

block

Sync Block length : 12 Byte

67891011

Fig. 3-1-3 Structure of sync blocks in subcode sector

3-3

3.1.2 Error Rate of DVC

The error rate of the DVC is shown by the average number of error corrections by the inner parity in t he
AUDIO/VIDEO sector (A/V inner errors) per 1 second (300 tracks). Error correction is carried out by the
ECC inside the DV-DSP IC, and the ECC outputs Error Flag SBE (Sync Block Error). The SBE is
classified into 7 levels from 0T pulse to 12T pulse according to number of error connections, and it is
output for each of 14 sync blocks of the AUDIO sector and 149 sync blocks of the VIDEO sector. For
evaluating the error rate actually, all SBE pulses that were output in 1 second are weighted by a certain
method and the total of the weighted SBE's is used as the DVC error rate.

0T: Sync failuer

2T: Error free

4T: 1-error correction

6T: 2-error correction

8T: 3-error correction

10T: 4-error correction

12T: Correction-disabled

1T=18MHz 1clock

Weighting

for SBE

0

0

1

2

3

4

5

Fig. 3-1-4 Particulars of SBE

The error rate jig in its infancy shows the total of weighted data of input SBE's by a frequency counter.
However, the error rate of the recent DVC models (GR-DVM5 and after) is output by the TCCS and can be
shown on the display of a personal computer by use of the Service Support Software (SSS).

Graph showed a change in
the Error Rate visually
White line: CH1
Pink line: CH2
Green line: 500 reference

Percentage of sync block
counting in Audio/Video
sector

Numerical value of Error
Rate

Fig. 3-1-5 Error Rate window in SSS

3-4

3.1.3 Previous method of head clog detection

The previous head clog detection system (for the models of GR-DVL9800 and before) is based on the
count of sync blocks as the criterion. The count of sync blocks that a head plays back per frame is:

NTSC: ( Audio 17 + Video 152 ) × 5 Track = 845
PAL: ( Audio 17 + Video 152 ) × 6 Track = 1014

Strictly explaining, number of sync blocks of the ITI sector and sub code sector must be added to the
above count. However, these additional counts cannot be detected by the system of the third generation
models (GR-DVX7 and after).
If some sync block is not detected, the data in the sync block is treated as an error that is impossible to
correct. If the status that the count of sync blocks in the AUDIO/VIDEO sector per 1 frame is lower than
240 of the threshold level continues in the short-playback mode just after start of recording for a certain
period (more than 0.5 second), the system judges that t he head is clogged. In other words, the system
recognizes the head clog when the quantity of playback data is one-fourth as little as the normal.
Therefore, if the system detects head clog in recording, it recognizes the recording part as impossible for
playback (regards as no-signal recording).
The short-playback mode just after restart (resuming) of recording is the stat us that the tape is rewound
for 1.5 second (back-space) according to the absolute track number that is memorized as recording is
suspended (by pause operation). When recording is resumed (restarted), the tape is transported in the
play mode first and then recording is actually resumed with the point of the memorized track number. This
period is called the short-playback period (mode). Head clog detection is not started at the first start of
recording but done at every resuming of recording for the second time, third time, and so on.

REC

REC start

REC stop

REC

Short PB

1.5 sec

Back Space

Track No. Finding

Fig. 3-1-6 Short Play Back

3-5

3.1.4 New method of head clog detection

The new head clog detection system (for this DVC series and after) performs detection in the normal
(usual) playback mode besides the short-playback mode just after resuming of recording as well as the
previous system. The criterion of the new detection system is not the count of sync blocks but number of
A/V inner errors per frame.

1) Detection in normal playback
Only when sync data recorded on both channels or one channel is read in the normal playback mode
(after detection of non-signal part), the new system judges that the head is clogged and warns the
user about it if number of A/V inner errors per frame continuously exceeds the threshold level for 7
seconds (for 210 frames: 30 x 7).
If errors less than the threshold level are continuously detected f or 2 seconds after that, the system
judges the head as not clogged and cancels the war ning indication. If the playback is suspended or
discontinued in the head clog status, the warning indication remains as it was until the system
detects no clog, or Eject or Power Off operation is performed.

2) Detection in short playback
In the period of short-playback just after recording is resumed, the servo controls the track position
according to the self-recording just before recording is suspended and the detection system judges
the head clog and warns the user about it if the status that number of A/V inner errors per frame
exceeds the threshold level continues for 6 frames (for about 0.2 second) after the capstan phase
was locked.
If recording is suspended (by pause operation) as the head is clogged, the warning indication
remains until the system detects no clog in the short-playback mode or Eject or Power Off operat ion
is performed.

3) Setting of threshold level
The error threshold level is set by the EEPROM as follows.

5 low-order bits in 8 bits: Threshold level in normal playback (0 ~ 31)

3 high-order bits in 8 bits: Coefficient in short-playback (0 ~ 7)
The actual threshold level in the normal playback is 10 times as high as t he standard setting value,
and that in the short-playback is several times as high as the actual threshold level in the norm al
playback because of the short detection time. If this detection level is converted into number of A/V
inner errors per second (the error rate), it approximates to 10,000. In other words, the system judges
that the head is clogged when number of A/V inner errors per second exceeds 10,000. If the
threshold level of the previous sync block count system is converted into the error rate, it
approximates to 1,000,000. As compared with the sync block count system, the detection capacity o f
the new detection system is improved by 20 dB or so.

3-6

Previous method

(GR-DVL9800 and before)

Detection period

During Short PB

at recording start

Judgment element

The number of Sink block counts

par 1 frame

Normal PB Short PB

∗

Over 150

7 sec

∗

Over 600

0.2 sec

Error rate conversion Rough estimate: 1,000,000

Threshold level and
Continuation period

Below 240

0.5 sec
Rough estimate: 10,000

New method

(GR-DVL300 series)

During Normal PB and Short PB

at recording start

The value of A/V inner error par 1 frame

∗∗∗∗

Note:

The threshold level of new method is decoded by data in EEPROM.
EEPROM Address: 3AEh → Data: 8Fh “10001111”
Lower 5 bit s: Setting of thre shold level i n normal PB “01111” → 15
Value of t hreshold level in normal PB: 15 × 10 = 150
Upper 3 bits: Coefficient of short PB “100” → 4
Value of t hreshold level in short PB: 150 × 4 = 600
Above addresses and threshold levels are for GR-DVL300 series, and those may vary in the model.

Table 3-1-1 Difference of the head clog method

4) History of head clog warning
With detection of head clog, the EEPROM counts the data and the history of head clog warnings can
be checked on the display of a personal computer with the SSS (Service Support Software).
Other specifica tions are as f ollows.

•

If sync block data is read from neither of two channels for 10 continuous frames, the system

recognizes that no signal is recorded in the part and does not perform clog detection. (The cleaning
tape is recognized as a non-recorded tape.)

•

Head clog detection in the short-playback mode is not performed at the first start of recording.

•

Head clog detection is not performed in any mode other than the normal playback mode such as

the FF/REW, Special Playback, Audio-dubbing/Insert modes.

•

Method to display marks and messages conforms to the specifications of respective models.

SECTION 4

DOCTOR SYSTEM

4-1

4.1 WHAT IS DOCTOR PROGRAM?

The function and performance of a product (an electric/electronic appliance in this case) generally
depends on the program of the internal microcomputer. If there is som e fault in the electrical function and
performance of a product, the program of its microcomputer should be changed (upgraded) at the
expenses of the manufacturer. To prepare for an unexpected trouble, recently manufactured articles store
a part of the program data in the EEPROM coupled with the microcomputer so that the program of the
microcomputer can be easily revised. Such the program data written in the EEPROM coupled with the
microcomputer is called the "Doctor Program".
If the microcomputer of an article has no need of support of the Doctor Program, no program data is
written in the EEPROM. Even in such the case, the EEPROM of recent products prepares specific
addresses (several bytes to dozens of bytes) as the area to write the Doctor Program. The area
(addresses) differs from model to model. Since the Doctor Program must vary depending on the program
of the microcomputer and expected troubles, its matching with the microcomputer (program) is very
important.

4.1.1 Matching of Doctor Program with Microcomputer Program

The program of the microcomputer can be revised by rewriting the Doctor Program stored in the EEPROM
coupled with the microcomputer. However, if the program of the microcomputer is changed by upgr ading
or so, the Doctor Program conforming to the previous progr am stored in the EEPROM is useless. If the
microcomputer that is consistent with the Doctor Program stored in the EEPROM is replaced with a new
microcomputer of an upgraded one, continuous use of the Doctor Program to cope with a trouble may
develop an unexpected situation. An example of progress of revisions (upgrading) of the microcomputer
program and EEPROM Doctor Program is shown below.

Microcomputer A

No Doctor

Program

Microcomputer B

Doctor

Program A

Doctor

Program B

No Doctor

Program

Doctor

Program B

Fig. 4-1-1 Example of progress of revisions

If there is such the change in production of a series of products, matching of the microcomputer and
Doctor Program with each other is as follows.

Microcomputer A + No Doctor Program, Doctor Program A, or Doctor Program B = OK,
Microcomputer B + No Doctor Program or Doctor Program C = OK,
Microcomputer A + Doctor Program C = NG,
Microcomputer B + Doctor Program A or Doctor Program B = NG.

If the Doctor Program mismatches the microcomputer program, the product falls into troubles showing
various symptoms when the Doctor Program is rewritten and it is difficult to specify the cause of the
trouble, for example, the product fails in power supply or shows the picture abnormally depending on the
situation. Such being the case, pay careful attention to matching of the Doctor Program with the
micro computer program (vers ion).

4-2

4.1.2 Use of Doctor Program for Camcorder

Doctor Programs have been widely used for stationary video deck s, however, the function of the Doctor
Program is an obstacle to repair of the product, namely, it occasionally brings about secondary troubles if
the program data stored in the EEPROM mismatches the microcomputer program as mentioned
previously. Under the circumstances that most of stationary video decks are not backed up by service
support system software and there is no means to read and write data stored in the EEPROM's of them,
the only way to cope with mismatching between the microcomputer program and Doctor Pr ogram is to
replace the EEPROM with a new one conforming to the microcomputer program or to kill the Doctor
Program electrically (to remove the resistor or to add a resistor). Although it is easy to replace the
EEPROM, the manufacturer is burdened with severe inventory management of spare parts because it is
required to have a large stock of differently written EEPROM's to supply them properly to various
micro computer programs.
No Doctor Program had been adopted for camcorders until quite recently, however, late camcorder
models such as the GR-DVL9500 series and after adopt the Doctor Program. Fortunately such the
camcorders don't need to replace the EEPROM's with those which proper data are written in, because
data stored in the EEPROM can be rewritten by means of the service support system software. In such the
case servicemen are required to pay careful attention to matching between the microcomputer program
and the EEPROM data including the Doctor Program.

4.1.3 Revision of Service Support System Software for Doctor Program

To rewrite camcorder's Doctor Program in the field and to avoid trouble caused by mismatching between
the microcomputer program and Doctor Program, the Service Support System Software is reexamined
and revised as follows.

Doctor Load

Fig. 4-1-2 EEPROM Utility window

4-3

1. Specification of Doctor Program area

If there is a Doctor Program area in the EEPROM data, the area is specified by coloring (gray) the cell on
the EEPROM utility map.

2. Deletion of Data Editing Function in Doctor Program Area

To avoid trouble caused by data editing in the Doctor Program area, data editing is disabled for the
colored cell (Doctor Program area).

3. Addition of Data Rewriting Function in Doctor Program Area Only

If there is a need of rewriting of the Doctor Program in the field, the manufacturer announces it through the
MCI or Service Bulletin and supplies an EEPROM initial data file including revised Doctor Program data to
the dealers, service stations and others concerned. For rewriting the Doctor Program data, it is required to
use the "Doctor Load" (refer to "Procedure to Rewrite Doctor Program" to be mentioned later) that is the
special function to renew the Doctor Program area only without disturbing other data such as adjustment
data, fixed data and so on. In other words, this special function secures the productivity of the camcorder.

4. Deletion of Doctor Program from Initial Data File

Every service support system software is supplied together with the initial data file. The initial data f ile to
be used for servicing the model that is designed to be doctored by the Doctor Program from the first stage
of the production should contain the Doctor Program. However, the initial data file for service use is
supplied without the Doctor Program in order to avoid possible trouble caused by mismatching of the
Doctor Program with the microcomputer program as mentioned previously, because the initial dat a file is
prepared based on the initial data at the beginning of the production. Such being the case, the service
support system software may not demonstrate full of the original function in doctoring the product with the
Doctor Program, however, this demerit is ignored from a viewpoint that doctoring with the Doctor Program
is a simple and easy measures against trouble. In the case the microcomputer is replaced with new one
and it is programmed by the backup data, pay heed the Doctor Program whether it matches the
microcomputer program or not, because the aforementioned way of thinking does not apply to backup
data.

4.1.4 Procedure to Rewrite Doctor Program

The special function "Doctor Load" is newly added to the service support system software. The "Doctor
Load" function facilitates renewal of data in the Doctor Program area only and deletion of the Doctor
Program.

1. Data Renewal in Doctor Program Area Only

In case of necessity of field service to revise the Doctor Program, the manufacturer supplies a data file
necessary for the service. The revision data file is the same f ormat as the initial data file supplied with the
service support system software. If the initial data is rewritten in the EEPROM in the usual manner when
revising the Doctor Program, it brings about such a trouble as other data, for example adjustment data and
data to be fixed, are also rewritten at the same time. To avoid such a trouble, the new function "Doctor
Load" can be used.

1. Read out the EEPROM data.

2. Open the supplied data file (including Doctor Program data) using the "Doctor Load" function
After the data file is loaded, data only in the Doctor Program area is read in the map on the EEPROM

utility (data stored in the EEPROM of the camcorder is not yet rewritten at this stage).

3. Confirm that the Doctor data is read in the map.

4. Write the data in the EEPROM in the usual way.

It is possible that the data only in the Doctor Program is rewritten with this process.

4-4

2. Data Deletion from Doctor Program Area Only

If the microcomputer is replaced, it occasionally needs to delete the Doctor Program stored in the
EEPROM. Although the service support system software has no data deletion function like the emergency
utility, the Doctor Program can be deleted by the "Doctor Load" function.

1. Read out the EEPROM data.

2. Open the initial data file supplied with the service support system software by the "Doctor Load"
function.
Since nothing of the Doctor Program is written in the initial data file as mentioned pr eviously, all data
in the Doctor Program area are reset to "FEh" respectively as the initial data f ile is loaded, in other
words, all data are apparently deleted from the Doctor Program area (data stored in the EEPROM of
the camcorder is not yet rewritten at this stage).

3. Confirm that the Doctor data are reset to "FEh" in the map.

4. Write the data in the EEPROM in the usual way.

It is possible that the data only in the Doctor Program is deleted with this process.

4-5

4.2 DOCTOR PROGRAM SYSTEM IN THE PRESENT CIRCUMSTANCES

Though it explained about the outline of the Doctor Program and the doctor complying with of the service
support system software in the preceding clause, it explains here about the present circumstances of the
Doctor Program system.

4.2.1 ON/OFF address and Program address

The Doctor Program system is stored in the EEPROM. The system is divided into two blocks; one is the
ON/OFF address block and the other is the program address block. Each address varies in the model.
Moreover, those blocks may be away.
In case of this model, the ON/OFF addresses are (1ACh

~

1AFh), and program addresses are (2A4h

~

2F4h, 77h, DAh

~

DFh). For other models, refer to the “table 4-2-3. Address list of Doctor Program” of the

postscript.
The contents of the ON/OFF address and the program address are as mentioned in the following.

For the ON/OFF addresses, write as follows.

To answer to the Doctor system: 1ACh = “12h” / 1ADh = “34h” / 1AEh = “56h” / 1AFh = “78h”
Not to answer to the Doctor system: 1ACh to 1AFh = “00h”

For the program addresses, write as follows.

To answer to the Doctor system: Programmed data
Not to answer to the Doctor system: "FEh" or any data

It can be considered that there are four kinds of combinations in theory, and those combinations determine
ON or OFF of the Doctor Program system. As shown in the Table 4-2-1, t he combination that turns the
Doctor Program system on is the pattern (1) only. The pattern (2) turns the Doctor Program system off
because "FEh" is written for all the program addresses, in which "FEh" is a cancelable data even when the
ON/OFF address is in the ON status. The pattern (3) is invalid even when an optional data is written in,
because the ON/OFF address is in the OFF status. In practice there are two patterns of (1) and (4).
In case of the pattern (1), if “33h” is written for the address 1ADh for example, the Doctor Program system
turns off. When all aforementioned data are written in four addresses properly, and Doctor Program
system becomes on for the first time.

Programmed Data

"Feh"

or any data

1ACh = 12h
1ADh = 34h
1AEh = 56h
1AFh = 78h
(ON)
1ACh = 00h
1ADh = 00h
1AEh = 00h
1AFh = 00h
(OFF)

Program Address

ON/OFF Address

ON…(1) OFF…(2)

OFF…(3) OFF…(4)

Table 4-2-1 Combinations of ON/OFF Address and Program Address

4-6

As mentioning above, it is unacceptable by using the service support system software to edit the doctor
area directly at the time of the repair. Howe ver, when writing of the initial data or the backup data is done,
the doctor area is also rewritten at the same time. Also, it is possible to turn off or renew the Doctor
Program by using the "Doctor Load" function. Table 4-2-2 shows the combinations that may be probably
programmed in practice now.

ON/OFF
Address

Program
Address

ON/OFF

Address

Program

Address

ON Correct ON Correct Yes → Yes ∗1
ON Incorrect ON Correct No → Yes ∗2

OFF “ FEh ” Change ON Correct Yes → Yes ∗3

ON Correct OFF “ FEh ” Yes

→

Yes ∗4

ON Incorrect OFF “ FEh ” No → Yes ∗5

OFF “ FEh ” OFF “ FEh ” Yes → Yes ∗6

Writing Data

Yes: Normal

No: Locked

Original Data

Table 4-2-2 Changing situations of Doctor Program

The following explains each pattern from ∗1 to ∗6.

∗

1: For the camcorder that Doctor Program System has been turned on, but it is replaced with another

Doctor Program System for improvement of the performance.

∗

2: For the camcorder that has been locked because the data of the Doctor Program was broken for

some reason, the same Doctor Program is written again to release the set from the locked status.

∗

3: For the camcorder that Doctor Program System has been turned off, the Doctor Program is written

for improving the performance.

∗

4: For the camcorder that Doctor Program System has been turned on, the microcomputer is replaced

with an upgraded one.

∗

5: It is required to release the set temporarily from the same locked status as the case ∗2.

∗

6: For usual EEPROM data writing, which does not affect the Doctor Program System.

Under the locked condition such as ∗2 or ∗5, if the camera system fails in communication such as it
completely dead, the camera system cannot be recovered by rewriting the data of t he EEPROM. In such
the case, it needs to replace the EEPROM with a new one and to write original data in it or to adjust all
items after writing the initial data in the new EEPROM. However, the communication may be recovered by
turning on in the deck mode after disconnecting the DC power supply once and connecting it again if the
deck system does not affected by the trouble. If the communication is recovered by the above means, turn
off the Doctor Program System using the “Doctor Load” function.
Unless there occurs a trouble, don't use the “Doctor Load” function. Usual editing of the EEPROM and
rewriting the initial data don't bring on any trouble.

4-7

4.2.2 Writing function of EEPROM data

The writing function of the previous service support system software (before complying with the doctor
system) was the method which data are written in one after another as the turn of the address. If the
ON/OFF address is younger than the Program address, the dat a renewal process becomes the following.
A problem occurs when it tries to write the data that the Doctor Program system is on in this method.

Rewriting of ON/OFF address data first

↓

Rewriting of program address data next

The Doctor system becomes on the moment "78h" is written at the end of the ON/OFF address. There is
actually no problem at this moment if all program addresses are "FEh" that means cancellation. But after
that, the Doctor Program area begins to be written. The camera system becomes locked condition the
moment data were written in the first address. The Doctor Program handles the whole of the program
addresses as a lump. The locked condition happens because the program is destroyed by different data's
there being written.

So, the present service support system that is complying with the doctor system is programmed by the
following process to prevent the camera from such the trouble as mentioned above. This process does not
bring on such the trouble, because the Doctor Program System is turned on at the last stage of the
process.

Memorizing the ON/OFF address data from the EEPROM

↓

Writing "00h" in all the ON/OFF addresses

↓

Rewriting the data of the program addresses

↓

Writing the memorized data in the ON/OFF addresses

4.2.3 Upgrade of the service support system

At present, though the initial data attached to the service support system should turn off all the Doctor
Programs in consideration of the safety, that is not necessarily the best way. To make the initial data with
the Doctor Program, it is indispensable that the congeniality decision with the microcomputer’s version on
the camera can be done easily.
So, the function which congeniality is judged automatically now is being developed. The microcomputer’s
version is read at the time of writing, then it is checked whether the Doctor Program corresponds to the
microcomputer or not. For the purpose of this, the microcomputer’s version information corresponded with
the Doctor Program is included into the initial data file.
Also, it is possible to make the backup data containing the microcomputer’s version information. This is
convenient when data are returned after replacement of the circuit board.
If this is realized, the trouble that relates to Doctor Program will be dissolved. As for Upgrade, it will be able
to be released soon.

4-8

4.2.4 Address list of the doctor program area

Address Data

3ACh 12h
3ADh 34h
3AEh 56h

3AFh 78h
1C4h 12h
1C5h 34h
1C6h 56h
1C7h 78h
1C4h 12h
1C5h 34h
1C6h 56h
1C7h 78h
6F0h 12h
6F1h 34h
6F2h 56h

6F3h 78h
1ACh 12h
1ADh 34h
1AEh 56h

1AFh 78h

Doctor Program

Address

Models

GR-DVL7
GR-DVL9500U
GR-DVL9500EG/DVL9500EK
GR-DVL9600EG/DVL9600EK
GR-DVL9600EA/DVL9600A

3B0h to 3CFh

Doctor ON/OFF

GR-DVX7/DVM50U/DVM70U
GR-DVX4EG/DVX7EG/DVX4EK/DVX7EK
GR-DVX40A/DVX70A/DVX40SH/DVX70SH
GR-DVX4EA/DVX7EA
VMD8

1A0h to 1C3h

GR-DVA1/DVF1/DVF11U/DVF21U/DVF31U
GR-DVL40EG/DVL40EK/DVL30EG/DVL30EK
GR-DVL20EG/DVL20EK
GR-DVL25A/DVL20EA/DVL28ED/DVL33SH
GR-DVL45A/DVL40EA/DVL48ED/DVL38SH
VMD2/VMD3

290h to 2F4h

GR-DVL700
GR-DVL9800U
GR-DVL9800EG/DVL9800EK
GR-DVL9700EG/DVL9700EK
VMD10/VMD20

600h to 61Bh

GR-DVA10/DVF10 series
GR-DVL300U/DVL300UM series
GR-DVL300KR/DVL805KR series
GR-DVL300EG/DVL300EK series
GR-DVL300A/DVL300A-S series
GR-DVL300EA/DVL300ED series
CC9370

77h

DAh to DFh

2A4h to 2D6h

Table 4-2-3 Address list of the doctor program area

VICTOR COMPANY OF JAPAN, LIMITED

Printed in Japan

2000-09 (TM1)