JVC CY2907 Diagram
CY2907
Single-PLL General-Purpose
EPROM Programmable Clock Generator
Features Benefits
Single phase-locked loop architecture Generates a custom frequency from an external source
EPROM programmability Easy customization and fast turnaround
Factory-programmable (CY2907, CY2907I) or field-pro-
grammable (CY2907F & CY2907FI) device options
Up to two configurable outputs Provides clocking requirem en ts from a singl e devi ce
Low-skew, low-jitter, high-accuracy outputs Meets critical industry standard timing requirements
Power management (Power-Down, OE) Supports low-power applications
Frequency select option Up to 16 user-selectable frequencies
Configurable 5V or 3.3V operation Supports industry-standard design platforms
8-pin or 14-pin SOIC packages Industry-standard packaging saves on board space
Selector Guide
Part Number Outputs Input Frequency Range Output Frequency Range Specifics
CY2907 2 10 MHz–25 MHz (e xternal crystal)
CY2907I 2 10 MHz–25 MHz (external crystal)
CY2907F8
CY2907F14
CY2907F8I
CY2907F14I
1 MHz–30 MHz (reference clock)
1 MHz–30 MHz (reference clock)
210 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
210 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
Programming support available for all opportunities
500 kHz–130 MHz (5V)
500 kHz–100 MHz (3.3V)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
500 kHz–90 MHz (5V)
500 kHz–66.66 MHz (3.3V)
Factory Programmable
Commercial Temperature
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
Logic Block Diagram
OEA
OER
PD
XTALIN
OSC.
PLL
XTALOUT
EPROM
Table
S0
S1
S2
S3
CyClocks is a trademark of Cypress Semiconductor Corporation.
Output
Multiplexer
and
Dividers
Configuration
EPROM
Test Logic
and
REFCLK
CLKA
Pin Configurations
Top View
14-Pin SOIC
S1
S2
S3
V
SS
V
SS
PD
XTALIN
S0
V
SS
XTALIN
XTALOUT
1
2
3
4
5
6
7
8-Pin SOIC
1
2
3
4
14
13
12
11
10
9
8
8
7
6
5
S0
REFCLK
V
DD
CLKA
OEA
OER
XTALOUT
REFCLK
V
DD
CLKA
S1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07137 Rev. ** Revised September 26, 2001
CY2907
Pin Summary
Pin Number
Name
S1 1 5 Frequency Select (CLKA) (Internal pull-up resistor to VDD)
S2 2 NA Frequency Select (CLKA) (Internal pull-up resistor to VDD)
S3 3 NA Frequency Select (CLKA) (Internal pull-up resistor to VDD)
V
SS
V
SS
4 2 Ground
5 NA Ground
PD 6 NA Power-Down (active LOW) (Internal pull-up resistor to VDD)
XTALIN
XTALOUT
[1]
[1, 2]
7 3 Reference Crystal Input
8 4 Reference Crystal Feedback
OER 9 NA REFCLK Output Enable (active HIGH) (Internal pull-up resistor to VDD)
OEA 10 NA CLKA Output Enable (active HIGH) (Internal pull -up resistor to VDD)
CLKA 11 6 Clock Output
V
DD
12 7 Voltage Supply
REFCLK 13 8 Reference Clock Output (Default, can be driven by PLL if desired)
S0 14 1 Frequency Select (CLKA) (Internal pull-up resistor to VDD)
Notes:
1. For best accuracy, use a parallel-resonant crystal, C
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
LOAD
≈ 17 pF.
Description14-Pin SOIC 8-Pin SOIC
Functional Description
The CY2907 is a general-purpose Clock Generator designed
for use in a wide variety of applications—from graphics to PC
peripherals to dis k drives. It genera tes selectable sy stem clock
frequencies from a sing le re ference i nput (c rysta l or referenc e
clock). The CY2907 is co nfigured with an EPROM a rray , much
like the other devices in the Cypress EPROM Programmable
Clock Family, making it easily customizable for any application. Furthermore, the CY2907 is compatible with all industry-standard 9107 and 9108 clock synthesizers.
CyClocks™ Software
CyClocks is an easy-to-use software application that allows
you to configure any one of the EPROM Programmable Clocks
offered by Cypress . You may specify the input frequency, PLL
and output frequencies, and different functional options.
Please note the output frequency ranges in this data sheet
when specifying them in CyClocks to ensure that you stay
within the limits. Y ou can down load a copy of CyCloc ks free on
the Cypress Semiconductor website at www.cypress.com.
Consider using the CY2081, CY2291, or CY2292 for applications that require unrelated and multiple output frequencies.
Consider using the CY2071A for applications that require
more than one output clock.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmers are portable programmers designed to custom program
our family of EPROM Field Programmable Clock Devices.
The FTG programmers connect to a PC serial port and allow
users of CyClocks so ftware t o quickly and eas ily pro gram an y
of the CY2291F, CY2292F , CY2 071AF , and CY2 907F devices.
The ordering code for the Cypress FTG Programmer is
CY3670.
Maximum Ratings
(Beyond which the useful life may be impaired. For u ser guidelines, not tested.)
Supply Voltage .................................................–0.5 to +7.0V
Input Voltage ...........................................–0.5V to V
Storage Temperature (Non-Condensing)... –65°C to +150°C
Max. Soldering Temperature (10 sec)...................... +260°C
Junction Temperature............................................... +150°C
Static Discharge Voltage ...........................................>2000V
(per MIL-STD-883, Method 3015)
DD
+0.5V
Document #: 38-07137 Rev. ** Page 2 of 10
CY2907
Operating Conditions
[3]
Parameter Description Min. Max. Unit
V
DD
Supply Voltage, 5V Operation 4.5 5.5 V
Supply Voltage, 3.3V Operation 3.0 3.6 V
T
A
Commercial Operating Temperature, Ambient 0 70 °C
Industrial Operating Temperature, Ambient –40 85 °C
C
L
f
REF
Electrical Characteristics at 5.0 V Commercial V
Max. Capacitive Load 15 pF
External Reference Crystal 10.0 25.0 MHz
External Reference Clock
[4, 5]
= 4.5V to 5.5V, TA = 0°C to +70°C
DD
1.0 30.0 MHz
Parameter Description Test Conditions Min. Max. Unit
V
V
V
V
I
I
I
I
I
I
I
R
OH
OL
IH
IL
DD
DD
DD
IH
IL
OH
OL
PU
[4]
[4]
[4]
[4]
[5]
[4]
High-level Input Voltage Except Crystal Inputs 2.0 V
Low-level Input Voltage Except Crystal Inputs 0.8 V
High-level Output Voltage VDD = VDD Min. IOH = –30 mA CLKA 2.4 V
Low-level Output Voltage VDD = VDD Min. IOL = 10 mA CLKA 0.4 V
Output High Current VOH = 2.0V –35 mA
Output Low Current V
Input High Current VIH = V
= 0.8V 22 mA
OL
DD
–2 2 µA
Input Low Current VIL = 0V 20 µA
Power Supply Current PD HIGH, CLKA = 50 MHz 42 mA
Power Supply Current PD LOW, Logic Inputs LOW 100 µA
Power Supply Current PD LOW, Logic Inputs HIGH 40 µA
Pull-up Resistor V
IN = VDD
– 1.0 V 700 kΩ
Electrical Characteristics at 3.3 V Commercial V
= 3.0V to 3.6V, TA = 0°C to +70°C
DD
Parameter Description Test Conditions Min. Max. Unit
V
IH
V
IL
[4]
V
OH
[4]
V
OL
[4]
I
OH
[4]
I
OL
I
IH
I
IL
[5]
I
DD
I
DD
I
DD
[4]
R
PU
Notes:
3. Electrical parameters are guaranteed with these operating conditions.
4. Guaranteed by design, not 100% tested in production.
5. Load = max. typical configuration, f
I
(mA) = VDD * (6.25 + (0.055*F
DD
High-level Input Voltage Except Crystal Inputs 0.7*V
DD
Low-level Input Voltage Except Crystal Inputs 0.2*V
High-level Output Voltage CLKA, I
–5 mA 0.85*V
OH =
DD
Low-level Output Voltage CLKA, IOL = 6 mA 0.1*V
Output High Current V
Output Low Current V
Input High Current VIH = V
OH
OL
= 0.7*V
= 0.2*V
DD
DD
DD
–10 mA
15 mA
–2 2 µA
DD
DD
V
V
V
V
Input Low Current VIL = 0V 10 µA
Power Supply Current PD HIGH, CLKA = 50 MHz 40 mA
Power Supply Current PD LOW, Logic Inputs LOW 40 µA
Power Supply Current PD LOW, Logic Inputs HIGH 12 µA
Pull-up Resistor V
= 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula:
REF
) + (0.0017*C
REF
IN = VDD
LOAD
– 0.5V 900 kΩ
*(F
+ REFCLK))). C
CLKA
is specified in pF and F is specified in MHz.
LOAD
Document #: 38-07137 Rev. ** Page 3 of 10
CY2907
Electrical Characteristics at 5.0V Industrial V
= 4.5V to 5.5V, TA = –40°C to +85°C
DD
Parameter Description Test Conditions Min. Max. Unit
V
IH
V
IL
[4]
V
OH
[4]
V
OL
[4]
I
OH
[4]
I
OL
I
IH
I
IL
[5]
I
DD
I
DD
I
DD
[4]
R
PU
Electrical Characteristics at 3.3V Industrial V
High-level Input Voltage Except Crystal Inputs 2.0 V
Low-level Input Voltage Except Crystal Inputs 0.8 V
High-level Output Voltage VDD = VDD Min. IOH = –30 mA CLKA 2.4 V
Low-level Output Voltage VDD = VDD Min. IOL = 10 mA CLKA 0.4 V
Output High Current VOH = 2.0V –45 mA
Output Low Current V
Input High Current VIH = V
= 0.8V 20 mA
OL
DD
–2 2 µA
Input Low Current VIL = 0V 20 µA
Power Supply Current PD HIGH, CLKA = 50 MHz 54 mA
Power Supply Current PD LOW, Logic Inputs LOW 110 µA
Power Supply Current PD LOW, Logic Inputs HIGH 45 µA
Pull-up Resistor V
IN = VDD
– 1.0 V 700 kΩ
= 3.0V to 3.6V, TA = –40°C to +85°C
DD
Parameter Description Test Conditions Min. Max. Unit
V
V
V
V
I
I
I
I
I
I
I
R
OH
OL
IH
IL
DD
DD
DD
IH
IL
OH
OL
PU
[4]
[4]
[4]
[4]
[5]
[4]
High-level Input Voltage Except Crystal Inputs 0.7*V
Low-level Input Voltage Except Crystal Inputs 0.2*V
High-level Output Voltage CLKA, I
–5 mA 0.85*V
OH =
Low-level Output Voltage CLKA, IOL = 6 mA 0.1*V
Output High Current V
Output Low Current V
Input High Current VIH = V
OH
OL
= 0.7*V
= 0.2*V
DD
DD
DD
DD
DD
DD
DD
–12 mA
14 mA
–22µA
Input Low Current VIL = 0V 10 µA
Power Supply Current PD HIGH, CLKA = 50 MHz 50 mA
Power Supply Current PD LOW, Logic Inputs LOW 50 µA
Power Supply Current PD LOW, Logic Inputs HIGH 15 µA
Pull-up resistor V
IN = VDD
– 0.5V 900 kΩ
V
V
V
V
Document #: 38-07137 Rev. ** Page 4 of 10
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