IT8875F
PCI Parallel Port
Preliminary Specification V0.1
Copyright 2001 ITE, Inc.
This is Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous documentation issued for the related products
included herein. Please contact ITE, Inc. for the latest document(s). All sales are subject to ITE‘ s Standard
Terms and Conditions, a copy of which is included in the back of this document.
ITE, IT8875F is a trademark of ITE, Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
ITE, Inc. Phone: (02) 2657-9896
Marketing Department Fax: (02) 2657-8561, 2657-8576
7F, No. 435, Nei Hu District, Jui Kuang Rd.,
Taipei 114, Taiwan, R.O.C.
ITE (USA) Inc. Phone: (408) 530-8860
Marketing Department Fax: (408) 530-8861
1235 Midas Way
Sunnyvale, CA 94086
U.S.A.
ITE (USA) Inc. Phone: (512) 388-7880
Eastern U.S.A. Sales Office Fax: (512) 388-3108
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U.S.A.
If you have any marketing or sales questions, please contact:
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Fax: 886-2-26578561
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Fax: (408) 530-8861
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Contents
CONTENTS
1. Features................................................................................................................................................... 1
2. General Description..................................................................................................................................3
3. Block Diagram.......................................................................................................................................... 5
4. Pin Configuration...................................................................................................................................... 7
5. IT8875F Pin Descriptions..........................................................................................................................9
6. Power On Strapping Options ..................................................................................................................15
7. System Configuration .............................................................................................................................17
7.1 Overview........................................................................................................................................17
7.2 Features ........................................................................................................................................17
8. Functional Description............................................................................................................................19
8.1 PCI Slave Interface........................................................................................................................19
8.2 PCI Parity .....................................................................................................................................19
8.3 Positively Decode Spaces.............................................................................................................19
8.4 SMB Boot ROM Configuration.......................................................................................................19
8.5 4 Chip Selects...............................................................................................................................21
8.6 Parallel Port..................................................................................................................................21
9. Register Descriptions..............................................................................................................................23
9.1 Configuration Register Map..........................................................................................................23
9.2 Access Configuration Registers.....................................................................................................24
9.3 Configuration Register Descriptions...............................................................................................26
9.3.1 Device/Vendor ID Register (IDR) – Offset 00h...................................................................26
9.3.2 Status / Command Register (SCR) – Offset 04h...............................................................26
9.3.3 Class Code/ Revision ID Register (CCRIDR) – Offset 08h................................................27
9.3.4 Header Type/ MLT/ Cache Line Size Register (HMCR) – Offset 0Ch................................27
9.3.5 PCI Space_0 Base Address Register (PS0BAR) – Offset 10h..........................................28
9.3.6 PCI Space_1 Base Address Register (PS1BAR) – Offset 14h..........................................28
9.3.7 PCI Space_2 Base Address Register (PS2BAR) – Offset 18h..........................................29
9.3.8 PCI Space_3 Base Address Register (PS3BAR) – Offset 1Ch..........................................29
9.3.9 PCI Space_4 Base Address Register (PS4BAR) – Offset 20h..........................................30
9.3.10 PCI Space_5 Base Address Register (PS5BAR) – Offset 24h..........................................30
9.3.11 Sub-system Device ID / Sub-system Vendor ID – Offset 2Ch...........................................31
9.3.12 Interrupt Pin/Line Register (INTR) – Offset 3Ch................................................................31
9.3.13 Global Control_1 Register (GC1R) – Offset 40h...............................................................32
9.3.14 Global Control_2 Register (GC2R) – Offset 44h...............................................................33
9.3.15 PCI Space_1/0 Remap Register (RMP10R) – Offset 50h.................................................34
9.3.16 PCI Space_3/2 Remap Register (RMP32R) – Offset 54h.................................................35
9.3.17 PCI Space_5/4 Remap Register (RMP54R) – Offset 58h.................................................36
9.3.18 Positively Decoded I/O_Space_0 Register (POSIO0R) – Offset 60h.................................37
9.3.19 Positively Decoded I/O_Space_1 Register (POSIO1R) – Offset 64h.................................37
9.3.20 Positively Decoded I/O_Space_2 Register (POSIO2R) – Offset 68h.................................38
9.3.21 Positively Decoded I/O_Space_3 Register (POSIO3R) – Offset 6Ch................................38
9.3.22 Positively Decoded I/O_Space_4 Register (POSIO4R) – Offset 70h.................................39
9.3.23 INTC Base Address Register (INTCBAR) – Offset 78h.....................................................40
9.3.24 Internal Parallel Port Base Address Register (IPPBAR) – Offset 80h................................40
9.3.25 External Devices Base Address Register 1 (XDBA1R) – Offset 88h..................................40
9.3.26 Miscellaneous Control Register (MISCR) – Offset 9Ch.....................................................41
9.3.27 Undefined Register ..........................................................................................................41
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IT8875F
10.Interrupt Controller (INTC)......................................................................................................................43
10.1 Features.......................................................................................................................................43
10.2 Block Diagram..............................................................................................................................43
10.3 Register Descriptions...................................................................................................................44
10.3.1 Interrupt Request Register 1 (IRR1R) – Offset INTC_Base + 0h.......................................44
10.3.2 Interrupt Request Register 2 (IRR2R) – Offset INTC_Base + 1h.......................................44
10.3.3 Interrupt Request Register 3 (IRR3R) – Offset INTC_Base + 2h.......................................44
10.3.4 Interrupt Mask Register 1 (IMR1R) – Offset INTC_Base + 4h...........................................44
10.3.5 Interrupt Mask Register 2 (IMR2R) – Offset INTC_Base + 5h...........................................44
10.3.6 Interrupt Mask Register 3 (IMR3R) – Offset INTC_Base + 6h...........................................45
10.3.7 Interrupt Edge/Level Trigger Mode Register 1 (IER1R) – Offset INTC_Base + 8h.............45
10.3.8 Interrupt Edge/Level Trigger Mode Register 2 (IER2R) – Offset INTC_Base + 9h.............45
10.3.9 Interrupt Edge/Level Trigger Mode Register 3 (IER3R) – Offset INTC_Base + Ah.............45
10.3.10 S/W Interrupt Generate Register 1 (SIGR1R) – Offset INTC_Base + Ch.......................45
10.3.11 S/W Interrupt Generate Register 2 (SIGR2R) – Offset INTC_Base + Dh.......................45
10.3.12 S/W Interrupt Generate Register 3 (SIGR3R) – Offset INTC_Base + Eh .......................46
11.Parallel Port............................................................................................................................................47
11.1 Overview......................................................................................................................................47
11.2 SPP and EPP Modes...................................................................................................................47
11.3 EPP Mode Operation ..................................................................................................................49
11.4 ECP Mode Operation..................................................................................................................50
12.DC Characteristics..................................................................................................................................57
13.Package Information...............................................................................................................................59
14.Ordering Information...............................................................................................................................61
FIGURES
Figure 9-1. PCI Configuration Register Structure..........................................................................................24
Figure 9-2. PCI Configuration Access Mechanism #1...................................................................................25
Figure 10-1. Block Diagram of the Interrupt Controller..................................................................................43
TABLES
Table 4-1. Pins Listed in Numeric Order .........................................................................................................8
Table 5-1. Pin Descriptions of Supplies Signals..............................................................................................9
Table 5-2. Pin Descriptions of PCI Bus Interface Signals ................................................................................9
Table 5-3. Pin Descriptions of Partial ISA Bus Signals..................................................................................11
Table 5-4. Pin Descriptions of Parallel Port Signals......................................................................................12
Table 5-5. Pin Descriptions of Miscellaneous Signals...................................................................................13
Table 9-1. IT8875F Configuration Register Map...........................................................................................23
Table 10-1. List of INTC Registers ...............................................................................................................44
Table 11-1. Parallel Port Connector in Different Modes ................................................................................47
Table 11-2. Address Map and Bit Map for SPP and EPP Modes ..................................................................47
Table 11-3. Bit Map of the ECP Registers....................................................................................................50
Table 11-4. ECP Register Definitions...........................................................................................................50
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Contents
Table 11-5. ECP Mode Descriptions.............................................................................................................51
Table 11-6. ECP Pin Descriptions................................................................................................................51
Table 11-7. Extended Control Register (ECR) Mode and Description...........................................................53
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1. Features
Features
n PCI Interface
−
PCI Specification V2.1 compliant
−
Supports 32-bit PCI bus & up to 33 MHz PCI bus
frequency
−
Supports PERR# & SERR# Error Reporting
−
Supports Delayed Transaction
n Programmable PCI Address Decoders
−
Supports 6 programmable, size configurable,
I/O and memory spaces
−
Provides 5 positively decoded I/O blocks
n Compact Bus Interface
−
Supports a compact bus structure to hook up an
external I/O device
−
Supports maximum 4 decoding chip selects
n IEEE 1284 Parallel Port
−
Standard mode—Bi-directional SPP compliant
−
Enhanced mode—EPP V. 1.7 and V. 1.9
compliant
−
High speed mode—ECP, IEEE 1284 compliant
−
Back-drive current reduction
−
Printer power-on damage reduction
n SM Bus
−
Compliant with System Management Bus
Specification R. 1.0
−
Supports single master mode
−
Interfaced to Serial E
2
PROM
n Power-on Serial Bus Configuration
−
Power-on auto configuration through SM bus
−
Patent pending on auto-start and auto-stop
scheme
n Miscellanies
−
Supports 24 MHz Oscillator circuit
n +3.3V PCI I/F with +5V tolerant I/O buffers, +5V
ISA I/F and core Power Supply
n Package: 128-pin PQFP
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Specifications subject to Change without Notice By P.C. Lin, 03/13/2001
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General Description
2. General Description
The IT8875F is a PCI interface to a parallel port chip. The IT8875F’ s 32-bit PCI bus interface is compliant with
PCI Specification V2.1.
The parallel port in IT8875F supports standard mode (SPP), EPP V.17 and V.19 and ECP mode. Due to the
variation of system platform, DMA mode is NOT supported in IT8875F. The IT8875F also provides a compact
bus structure to connect an external device. The compact bus structure facilitates the system engineers to hook
an 8-bit external device by programming the INTC base address register and positive decoding registers.
Overall, the IT8875F provides a simple solution to build a parallel port on PCI bus.
In addition, the IT8875F also integrates one SM bus (single master mode) which can be connected to a Serial
E2PROM for automatic power-on configuration and providing customers with maximum design flexibility.
The IT8875F is available in 128-pin PQFP package.
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3. Block Diagram
Block Diagram
PCI Bus
INTA#
IT8875F
(PCI to Parallel Port Chip)
Configuration
Registers
PCI
Slave
Conversion
Internal PCI bus
Interrupt
Controller
CS# Decoder
PCI
PIO Cycle
Testing Circuit
Power_on
Configuring
Central Interface Bus
ISA Bus Data
/ Control Logic
Oscillator &
Clock Dividers
SM Bus
Master
Parallel Port
24 MHz
Crystal
Serial
E2PROM
Parallel Port
Device
External I/O Devices
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Sub_ISA Bus
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4. Pin Configuration
VCC3
AD28
AD27
AD26
AD25
AD24
CBE3#
IDSEL
AD23
AD22
AD21
AD20
VCC3
AD19
AD18
AD17
AD16
CBE2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
VCC3
PAR
CBE1#
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
GND
CBE0#
PD0
SLIN#
INIT#
ALFD#
STB#
PERROR#
INTA#/SERIRQ
ISAGNT#
ISAREQ#
AD31
AD30
AD29
PCIRST#
PCICLK
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IT8875F
17
18
19
20
21
22
23
24
128-PQFP
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39404142434445464748495051525354555657
PD1
114
PD2
113
PD3
112
PD4
111
VCC
110
ACK#
PD7
PD6
PD5
109
106
107
108
58
5960616263
Pin Configuration
SLCT
PE
BUSY
104
105
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
GND
GND
GND
GND
GND
NC
VCC
IOW#
IOR#
CSA0#
SD7
SD6
SD5
GND
SD4
VCC
SD3
SD2
SD1
SD0
CSA1#
CSA2#
GND
CK24M
CK24ME
VCC
CSA3#
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
GND
NC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
VCC3
SDA
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7
GND
NC
VCC
GND
SA2
SA1
SA0
RSTDRV
NC
NC
NC
NC
TESTIN#
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IT8875F
Table 4-1. Pins Listed in Numeric Order
Pin Signal Pin Signal Pin Signal Pin Signal
1 VCC3 33 AD11 65 GND 97 NC
2 AD28 34 AD10 66 GND 98 GND
3 AD27 35 AD9 67 GND 99 GND
4 AD26 36 AD8 68 GND 100 GND
5 AD25 37 GND 69 NC 101 GND
6 AD24 38 CBE0# 70 NC 102 GND
7 CBE3# 39 VCC3 71 NC 103 SLCT
8 IDSEL 40 GND 72 NC 104 PE
9 AD23 41 AD7 73 NC 105 BUSY
10 AD22 42 AD6 74 NC 106 ACK#
11 AD21 43 AD5 75 NC 107 PD7
12 AD20 44 AD4 76 CSA3# 108 PD6
13 VCC3 45 AD3 77 VCC 109 PD5
14 AD19 46 AD2 78 CK24ME 110 VCC
15 AD18 47 AD1 79 CK24M 111 PD4
16 AD17 48 AD0 80 GND 112 PD3
17 AD16 49 SDA 81 CSA2# 113 PD2
18 CBE2# 50 SCL 82 CSA1# 114 PD1
19 FRAME# 51 GND 83 SD0 115 PD0
20 IRDY# 52 NC 84 SD1 116 SLIN#
21 TRDY# 53 NC 85 SD2 117 INIT#
22 DEVSEL# 54 NC 86 SD3 118 ALFD#
23 STOP# 55 NC 87 VCC 119 STB#
24 PERR# 56 VCC 88 SD4 120 PERROR#
25 SERR# 57 GND 89 GND 121 INTA#/SERIRQ
26 VCC3 58 SA2 90 SD5 122 ISAGNT#
27 PAR 59 SA1 91 SD6 123 ISAREQ#
28 CBE1# 60 SA0 92 SD7 124 AD31
29 AD15 61 RSTDRV 93 CSA0# 125 AD30
30 AD14 62 TESTIN# 94 IOR# 126 AD29
31 AD13 63 NC 95 IOW# 127 PCIRST#
32 AD12 64 NC 96 VCC 128 PCICLK
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IT8875F Pin Descriptions
5. IT8875F Pin Descriptions
Table 5-1. Pin Descriptions of Supplies Signals
Pin(s) No. Symbol Attribute Power Description
56, 77 ,87,
96, 110
1, 13, 26, 39 VCC3 PWR - +3.3V Power Supply.
37, 40, 51,
57, 65, 66,
67, 68, 80,
89, 98, 99,
100, 101,
102
Pin(s) No. Symbol Attribute Power Description
124-126,
2-6, 9-12,
14-17, 29-36,
41-48
7, 18, 28, 38 CBE[3:0]# I/O16 VCC3
22 DEVSEL# I/O16 VCC3 Device Select #.
21 TRDY# I/O16 VCC3 Target Ready #.
20 IRDY# I/O16 VCC3 Initiator Ready #.
VCC PWR - +5V Power Supply.
GND GND - Ground.
Table 5-2. Pin Descriptions of PCI Bus Interface Signals
AD[31:0] I/O16 VCC3 PCI Multiplexed Address / Data 31 – 0.
32-bit bi-directional address/data multiplexed lines. AD31
is the MSB and AD0 is the LSB. The direction of these
pins are defined below:
PHASE Bus Master Target
Address Phase Output Input
Read Data Phase Input Output
Write Data Phase Output Input
Command/Byte Enable 3 - 0 #.
Multiplexed bus command and byte enables.
When driven active low, the signal indicates the driving
device has decoded its address as the target of the
current access. This pin acts as an output pin when the
IT8875F (including ISA slave) is the slave of the PCI bus
cycle transaction. Otherwise, it is an input pin.
This signal indicates that the target of the current data
phase of the transaction is ready to be completed. This
pin acts as an output pin when the IT8875F (including ISA
slave) is the slave of the PCI bus cycle transaction.
Otherwise, it is an input pin.
This signal indicates that the initiator is ready to complete
the current data phase of the transaction.
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IT8875F
Table 5-2. Pin Descriptions of PCI Bus Interface Signals (cont‘ d)
Pin(s) No. Symbol Attribute Power Description
19 FRAME# I/O16 VCC3 FRAME #.
This signal is driven by the initiator to indicate the
beginning and duration of a PCI access.
8 IDSEL
27 PAR
24 PERR# I/O16 VCC3 Parity Error #.
25 SERR# I/O16_OD VCC3 System Error #.
23 STOP# I/O16 VCC3 Stop #.
121 INTA# /
SERIRQ
123 ISAREQ# I/O8 VCC3 PCI Bus Request #.
122 ISAGNT# I VCC3 PCI Bus Grant #.
128 PCICLK I VCC3 33 MHz PCI Clock.
127 PCIRST# I VCC3 PCI Bus Reset #.
I
I/O16
I/O16_OD VCC3 PCI Bus Interrupt Request A # / Serialized IRQ.
VCC3 Initialization Device Select.
This signal is used as a chip select during PCI
Configuration read / write transactions.
VCC3 Parity.
This signal is used for the even parity check on both
AD[31:0] & CBE[3:0]# lines. The PAR input/output
direction follows the AD[31:0] input/output direction.
This signal is used for reporting data parity errors during
all PCI transactions, except in a Special Cycle. PERR# is
an output when it detects a parity error in receiving data
as a PCI Target.
This signal is used for reporting address parity errors,
data parity errors on the Special Cycle command, or any
other system error where the result will be catastrophic.
(input for IC test only)
This signal indicates that the current target is requesting
the initiator to stop the current transaction. This pin acts
as an output pin when the IT8875F (including ISA slave)
is the slave of the PCI bus cycle transaction. Otherwise, it
is an input pin.
Interrupt Request A# of PCI bus.
Serialized IRQ (for on board testing only).
This request signal is asserted to request the host bridge.
This acknowledge (grant) signal is asserted from the host
bridge.
PCIRST# is used to reset PCI bus devices.
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IT8875F Pin Descriptions
Table 5-3. Pin Descriptions of Partial ISA Bus Signals
Pin(s) No. Symbol Attribute Power Description
58-60 SA[2:0] I_SC_PU/O
83-86, 88,
90-92
94 IOR#
SD[7:0]
I_SC_PU/
O8
I_SC_PU/
O8
95 IOW#
I_SC_PU/
O8
61 RSTDRV
I_SC_PU/
O8
8
VCC ISA Address 2 - 0.
SA[2:0] are ISA address outputs. They are also testing
inputs.
VCC ISA Data 7 - 0.
8-bit bi-directional data lines. SD7 is the MSB.
VCC I/O Read #.
Active low output asserted by the CPU to read data or
status information from the ISA device. This pin acts as
input when the chip is being tested.
VCC I/O Write #.
Active low output asserted by the CPU to write data or
control information to the ISA device. This pin acts as an
input when the chip is being tested.
VCC ISA Reset.
A high level on this output resets the ISA bus. This signal
asynchronously terminates any activity and places the
ISA device in the reset state.
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IT8875F
Table 5-4. Pin Descriptions of Parallel Port Signals
Pin(s) No. Symbol Attribute Power Description
103 SLCT I_SC_PU VCC Printer Being Selected Indicator.
The SLCT is the input status to indicate the printer is
being selected to respond to the Parallel port transaction.
104 PE I_SC_PU VCC Printer Paper End Indicator.
The PE is the input status to indicate the printer has run
out of paper.
105 BUSY I_SC_PU VCC Printer Busy Indicator.
The BUSY is the input status to indicate the printer has a
local operation in progress and can not accept data.
106 ACK# I_SC_PU VCC Printer Acknowledge Indicator#.
The ACK# is the input status to indicate the printer has
already received a character and ready to accept another
one.
120 PERROR# I_SC_PU VCC Printer ERROR#.
Printer Error input for Parallel Port I/F.
116 SLIN# I_SC_PU/O
117 INIT# I_SC_PU/O
118 ALFD# I_SC_PU/O
119 STB# I_SC_PU/O
107-109,
111-115
PD[7:0] I_SC_PU/O
24
24
24
24
24
VCC Printer SLIN #.
Printer Selecting output for Parallel Port I/F.
VCC Printer INIT#.
Printer initializing output for Parallel Port I/F.
VCC Printer ALFD#.
Printer Auto Line Feed output for Parallel Port I/F.
VCC Printer STB#.
Printer STROBE output for Parallel Port I/F.
VCC Parallel Port Data Bus: PD7~PD0.
Printer Data bus for Parallel Port I/F.
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IT8875F Pin Descriptions
Table 5-5. Pin Descriptions of Miscellaneous Signals
Pin(s) No. Symbol Attribute Power Description
49 SDA I_SC_PU/O
4_OD
50 SCL I_SC_PU/O
4_OD
62 TESTIN# I_PU VCC Chip Test Mode.
78, 79 CK24ME/
CK24M
76, 81, 82,93CSA[3:0]# I_SC_PU/O
52-55 NC - - Not Connected.
63-64 NC - - Not Connected.
69-75 NC - - Not Connected.
97 NC - - Not Connected.
I/O_OSC/
I_OSC
4
Attributes:
I: Input
I/O8: 8mA Input/Output
I/O16: 16mA Input/Output
I/O16_OD: 16mA Input/Open Drain Output
I_SC_PU: Schmitt Input with 50K Pull Down
I_SC_PU/O8: 8 mA Schmitt input with 50K Pull Up/Output
I_SC_PU/O24: 24 mA Schmitt input with 50K Pull Up/Output
VCC Serial Bus Data.
System Management Bus data for Serial E2PROM.
VCC Serial Bus Clock.
System Management Bus clock output for Serial
E2PROM. (input for IC test only)
For Chip testing only, and should be left unconnected or
P/U.
VCC 24 MHz Oscillator.
Connected to 24 MHz Crystal.
VCC Chip Select Group_A[3:0] #.
Chip Select Group_A[3-0] output which shares the same
high base address.
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Power On Strapping Options
6. Power On Strapping Options
Symbol Pin # Jumper Description
(P/Up) INTA#.CSA0# 93
P/Down SERIRQ#.
CSA2# 81
(P/Up) Enable SM Bus Boot ROM Configuration. It will set Cfg_50h<4>, but will be auto-
cleared when finishing download configure code.
P/Down Disable SM Bus Boot ROM Configuration.
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