ITE IT8712F Schematics

IT8712F

Environment Control – Low Pin Count Input / Output

(EC - LPC I/O)

Preliminary Specification V0. 81

ITE TECH. INC.

Specification subject to Change without notice, AS IS and for reference only. For purchasing, please
contact sales representatives.

Please note that the IT8712F V0.81 is applicable to I version and future versions.

Copyright  2004 ITE Tech. Inc.
This is Preliminary document release. All specifications are subject to change without notice.

The material contained in this document supersedes all previous documentation issued for the related
products included herein. Please contact ITE Tech. Inc. for the latest docum ent(s). All sales are subject to
ITE’s Standard Terms and Conditions, a copy of which is included in the back of this document.

All sales are subject to IT E’s Standard Term s and Conditions, a copy of which is included in the bac k of this
document.

ITE, IT8712F is a trademark of ITE Tech. Inc.
Intel is claimed as a trademark by Intel Corp.
Microsoft and Windows are claimed as trademarks by Microsoft Corporation.
PCI is claimed as a trademark by the PCI Special Interest Group.
IrDA is claimed as a trademark by the Infrared Data Association.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.

Additional copies of this manual or other ITE literature may be obtained from:
ITE Tech. Inc. Phone: [phone]

Marketing Department Fax: [phone]
8F, No. 233-1, Bao Chiao RD., Hsin Tien,
Taipei County 231, Taiwan, R.O.C.

If you have any marketing or sales questions, please contact:

P.Y. Chang, at ITE Taiwan: E-mail: [e-mail], Tel: [phone] X6052,
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y

Revision Histor

Revision History

Section Revision Page No.

5
9  In section 9.5.2.1.11, the description of bit 7 and 6 was revised. 77

 In section 9.5.2.1.13, the description of bit 7-3 was revised. 78

 In table 5-5, JP5 was revised to JP6.

 Added a paragraph in the end of section 9.5.3.6: “Enhanced interrupt

mode”. When the enhanced interrupt mode is enabled…

 Figure 9-5 was revised.

12, 13

90

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Contents

CONTENTS

1. Features ................................................................................................................................................1

2. General Description ....................................................................................................................................... 3

3. Block Diagram................................................................................................................................................5

4. Pin Configuration............................................................................................................................................7

5. IT8712F Pin Descriptions...............................................................................................................................9

6. List of GPIO Pins .........................................................................................................................................21

7. Power On Strapping Options and Special Pin Routings .............................................................................. 23

8. Configuration ..............................................................................................................................................25

8.1 Configuring Sequence Description....................................................................................................25

8.2 Description of the Configuration Registers........................................................................................ 27

8.2.1 Logical Device Base Address............................................................................................... 32

8.3 Global Configuration Registers (LDN: All).........................................................................................34

8.3.1 Configure Control (Index=02h).............................................................................................34

8.3.2 Logical Device Number (LDN, Index=07h)...........................................................................34

8.3.3 Chip ID Byte 1 (Index=20h, Default=87h)............................................................................. 34

8.3.4 Chip ID Byte 2 (Index=21h, Default=12h)............................................................................. 34

8.3.5 Configuration Select and Chip Version (Index=22h, Default=07h).......................................34

8.3.6 Clock Selection Register (Index=23h, Default=00h) ............................................................34

8.3.7 Software Suspend (Index=24h, Default=00h, MB PnP) ....................................................... 35

8.3.8 GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=01h) ..................... 35

8.3.9 GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h) ..................... 36

8.3.10 GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h) .....................36

8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=40h) .....................37

8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h) .....................37

8.3.13 Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h) ..................... 38

8.3.14 Logical Block Lock Register (Index=2Bh, Default=00h)....................................................... 39

8.3.15 Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=1Fh)..................... 39

8.3.16 Test 1 Register (Index=2Eh, Default=00h)........................................................................... 40

8.3.17 Test 2 Register (Index=2Fh, Default=00h)...........................................................................40

8.4 FDC Configuration Registers (LDN=00h) .........................................................................................41

8.4.1 FDC Activate (Index=30h, Default=00h)............................................................................... 41

8.4.2 FDC Base Address MSB Register (Index=60h, Default=03h).............................................. 41

8.4.3 FDC Base Address LSB Register (Index=61h, Default=F0h) .............................................. 41

8.4.4 FDC Interrupt Level Select (Index=70h, Default=06h) .........................................................41

8.4.5 FDC DMA Channel Select (Index=74h, Default=02h)..........................................................41

8.4.6 FDC Special Configuration Register 1 (Index=F0h, Default=00h) .......................................41

8.4.7 FDC Special Configuration Register 2 (Index=F1h, Default=00h) .......................................42

8.5 Serial Port 1 Configuration Registers (LDN=01h) ............................................................................. 43

8.5.1 Serial Port 1 Activate (Index=30h, Default=00h) .................................................................. 43

8.5.2 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h) ...................................43

8.5.3 Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h) .................................... 43

8.5.4 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h).............................................43

8.5.5 Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h)...........................43

8.5.6 Serial Port 1 Special Configuration Register 2 (Index=F1h, Default=50h)...........................44

8.5.7 Serial Port 1 Special Configuration Register 3 (Index=F2h, Default=00h)...........................44

8.5.8 Serial Port 1 Special Configuration Register 4 (Index=F3h, Default=7Fh)........................... 44

8.6 Serial Port 2 Configuration Registers (LDN=02h) ............................................................................. 45

8.6.1 Serial Port 2 Activate (Index=30h, Default=00h) .................................................................. 45

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8.6.2 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h) ...................................45

8.6.3 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h) .................................... 45

8.6.4 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h).............................................45

8.6.5 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h)...........................45

8.6.6 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h)...........................46

8.6.7 Serial Port 2 Special Configuration Register 3 (Index=F2h, Default=00h)...........................46

8.6.8 Serial Port 2 Special Configuration Register 4 (Index=F3h, Default=7Fh)........................... 46

8.7 Parallel Port Configuration Registers (LDN=03h) ............................................................................. 47

8.7.1 Parallel Port Activate (Index=30h, Default=00h) ..................................................................47

8.7.2 Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h) ...................... 47

8.7.3 Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h) ..................... 47

8.7.4 Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h) .................47

8.7.5 Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h) ................ 47

8.7.6 Parallel Port Interrupt Level Select (Index =70h, Default=07h)............................................47

8.7.7 Parallel Port DMA Channel Select (Index=74h, Default=03h)..............................................47

8.7.8 Parallel Port Special Configuration Register (Index=F0h, Default=03h) .............................. 48

8.8 Environment Controller Configuration Registers (LDN=04h)............................................................49

8.8.1 Environment Controller Activate Register (Index=30h, Default=00h)................................... 49

8.8.2 Environment Controller Base Address MSB Register (Index=60h, Default=02h) .................. 49

8.8.3 Environment Controller Base Address LSB Register (Index=61h, Default=90h) ................... 49

8.8.4 PME Direct Access Base Address MSB Register (Index=62h, Default=02h) ........................ 49

8.8.5 PME Direct Access Base Address LSB Register (Index=63h, Default=30h) ......................... 49

8.8.6 Environment Controller Interrupt Level Select (Index=70h, Default=09h)............................49

8.8.7 APC/PME Event Enable Register (PER) (Index=F0h, Default=00h).................................... 49

8.8.8 APC/PME Status Register (PSR) (Index=F1h, Default=00h)...............................................50

8.8.9 APC/PME Control Register 1 (PCR 1) (Index=F2h, Default=00h) .......................................50

8.8.10 Environment Controller Special Configuration Register (Index=F3h, Default=00h).............51

8.8.11 APC/PME Control Register 2 (PCR 2) (Index=F4h, Default=00h) ....................................... 51

8.8.12 APC/PME Special Code Index Register (Index=F5h) ..........................................................51

8.8.13 APC/PME Special Code Data Register (Index=F6h) ........................................................... 51

8.9 KBC (keyboard) Configuration Registers (LDN=05h) .......................................................................52

8.9.1 KBC (keyboard) Activate (Index=30h, Default=01h or 00h) ................................................. 52

8.9.2 KBC (keyboard) Data Base Address MSB Register (Index=60h, Default=00h)................... 52

8.9.3 KBC (keyboard) Data Base Address LSB Register (Index=61h, Default=60h).................... 52

8.9.4 KBC (keyboard) Command Base Address MSB Register (Index=62h, Default=00h).......... 52

8.9.5 KBC (keyboard) Command Base Address LSB Register (Index=63h, Default=64h)........... 52

8.9.6 KBC (keyboard) Interrupt Level Select (Index=70h, Default=01h) ....................................... 52

8.9.7 KBC (keyboard) Interrupt Type (Index=71h, Default=02h)................................................... 53

8.9.8 KBC (keyboard) Special Configuration Register (Index=F0h, Default=00h)............................. 53

8.10 KBC (mouse) Configuration Registers (LDN=06h)...........................................................................53

8.10.1 KBC (mouse) Activate (Index=30h, Default=00h) ................................................................ 53

8.10.2 KBC (mouse) Interrupt Level Select (Index=70h, Default=0Ch).............................................. 53

8.10.3 KBC (mouse) Interrupt Type (Index=71h, Default=02h)....................................................... 53

8.10.4 KBC (mouse) Special Configuration Register (Index=F0h, Default=00h)............................54

8.11 GPIO Configuration Registers (LDN=07h)........................................................................................ 55

8.11.1 SMI# Normal Run Access Base Address MSB Register (Index=60h, Default=00h)............ 55

8.11.2 SMI# Normal Run Access Base Address LSB Register (Index=61h, Default=00h)............. 55

8.11.3 Simple I/O Base Address MSB Register (Index=62h, Default=00h) .................................... 55

8.11.4 Simple I/O Base Address LSB Register (Index=63h, Default=00h) ..................................... 55

8.11.5 Panel Button De-bounce Base Address MSB Register (Index=64h, Default=00h)..............55

8.11.6 Panel Button De-bounce Base Address LSB Register (Index=65h, Default=00h)...............55

8.11.7 Panel Button De-bounce Interrupt Level Select Register (Index=70h, Default=00h)........... 55

8.11.8 Watch Dog Timer Control Register (Index=71h, Default=00h) ............................................55

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8.11.9 Watch Dog Timer Configuration Register (Index=72h, Default=00h)................................... 56

8.11.10 Watch Dog Timer Time-Out Value Register (Index=73h, Default=00h)............................... 56

8.11.11 GPIO Pin Set 1, 2, 3, 4 and 5 Polarity Registers (Index=B0h, B1h, B2h, B3h and B4h,

Default=00h)......................................................................................................................... 56

8.11.12 GPIO Pin Set 1, 2, 3, 4 and 5 Pin Internal Pull-up Enable Registers (Index=B8h, B9h, BAh,

BBh and BCh, Default=00h).................................................................................................56

8.11.13 Simple I/O Set 1, 2, 3, 4 and 5 Enable Registers (Index=C0h, C1h, C2h, C3h and C4h,

Default=01h, 00h, 00h, 40h, and 00h).................................................................................. 56

8.11.14 Simple I/O Set 1, 2, 3, 4 and 5 Output Enable Registers (Index=C8h, C9h, CAh, CBh and

CCh, Default=01h, 00h, 00h, 40h, and 00h)......................................................................... 57

8.11.15 Panel Button De-bounce Control Register (Index=D0h, Default=00h)................................. 57

8.11.16 Panel Button De-bounce Set 1, 2, 3, 4 and 5 Enable Registers (Index=D1h, D2h, D3h, D4h

and D5h, Default=00h) ......................................................................................................... 57

8.11.17 IRQ3-7, 9-12 and 14-15 External Routing Input Pin Mapping Registers (Index=E3h-E7h,

E9h-ECh and EEh-EFh, Default=00h)..................................................................................57

8.11.18 SMI# Control Register 1 (Index=F0h, Default=00h).............................................................57

8.11.19 SMI# Control Register 2 (Index=F1h, Default=00h).............................................................58

8.11.20 SMI# Status Register 1 (Index=F2h, Default=00h)...............................................................58

8.11.21 SMI# Status Register 2 (Index=F3h, Default=00h)...............................................................58

8.11.22 SMI# Pin Mapping Register (Index=F4h, Default=00h)........................................................ 58

8.11.23 Hardware Monitor Thermal Output Pin Mapping Register (Index=F5h, Default=00h) .........59

8.11.24 Hardware Monitor Alert Beep Pin Mapping Register (Index=F6h, Default=00h).................. 59

8.11.25 Keyboard Lock Pin Mapping Register (Index=F7h, Default=00h) ........................................ 59

8.11.26 GP LED Blinking 1 Pin Mapping Register (Index=F8h, Default=00h) .................................. 59

8.11.27 GP LED Blinking 1 Control Register (Index=F9h, Default=00h)........................................... 59

8.11.28 GP LED Blinking 2 Pin Mapping Register (Index=FAh, Default=00h).................................... 59

8.11.29 GP LED Blinking 2 Control Register (Index=FBh, Default=00h) .......................................... 60

8.11.30 VID Input Register (Index=FCh, Default=--h).......................................................................60

8.11.31 VID Output Register (Index=FDh, Default=00h)................................................................... 60

8.12 MIDI Port Configuration Registers (LDN=08h).................................................................................. 61

8.12.1 MIDI Port Activate (Index=30h, Default=00h).......................................................................61

8.12.2 MIDI Port Base Address MSB Register (Index=60h, Default=03h)........................................ 61

8.12.3 MIDI Port Base Address LSB Register (Index=61h, Default=00h)......................................... 61

8.12.4 MIDI Port Interrupt Level Select (Index=70h, Default=0Ah).................................................61

8.12.5 MIDI Port Special Configuration Register (Index=F0h, Default=00h)................................... 61

8.13 Game Port Configuration Registers (LDN=09h) ............................................................................... 62

8.13.1 Game Port Activate (Index=30h, Default=00h) ....................................................................62

8.13.2 Game Port Base Address MSB Register (Index=60h, Default=02h)...................................... 62

8.13.3 Game Port Base Address LSB Register (Index=61h, Default=01h)....................................... 62

8.14 Consumer IR Configuration Registers (LDN=0Ah) ........................................................................... 63

8.14.1 Consumer IR Activate (Index=30h, Default=00h)................................................................. 63

8.14.2 Consumer IR Base Address MSB Register (Index=60h, Default=03h).................................. 63

8.14.3 Consumer IR Base Address LSB Register (Index=61h, Default=10h)................................... 63

8.14.4 Consumer IR Interrupt Level Select (Index=70h, Default=0Bh)...........................................63

8.14.5 Consumer IR Special Configuration Register (Index=F0h, Default=00h)............................. 63

9. Functional Description..................................................................................................................................65

9.1 LPC Interface....................................................................................................................................65

9.1.1 LPC Transactions.................................................................................................................65

9.1.2 LDRQ# Encoding..................................................................................................................65

9.2 Serialized IRQ...................................................................................................................................65

9.2.1 Continuous Mode .................................................................................................................65

9.2.2 Quiet Mode...........................................................................................................................66

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9.2.3 Waveform Samples of SERIRQ Sequence.......................................................................... 66

9.2.4 SERIRQ Sampling Slot......................................................................................................... 67

9.3 General Purpose I/O ......................................................................................................................... 68

9.4 Advanced Power Supply Control and Power Management Event (PME#).......................................70

9.5 Environment Controller .....................................................................................................................71

9.5.1 Interfaces..............................................................................................................................71

9.5.2 Registers .............................................................................................................................. 71

9.5.2.1 Address Port (Base+05h, Default=00h):.................................................................. 71

9.5.2.2 Register Description ................................................................................................75

9.5.2.2.1 Configuration Register (Index=00h, Default=18h)............................ 75

9.5.2.2.2 Interrupt Status Register 1 (Index=01h, Default=00h) ..................... 76

9.5.2.2.3 Interrupt Status Register 2 (Index=02h, Default=00h) ..................... 76

9.5.2.2.4 Interrupt Status Register 3 (Index=03h, Default=00h) ..................... 76

9.5.2.2.5 SMI# Mask Register 1 (Index=04h, Default=00h)............................76

9.5.2.2.6 SMI# Mask Register 2 (Index=05h, Default=00h)............................76

9.5.2.2.7 SMI# Mask Register 3 (Index=06h, Default=00h)............................76

9.5.2.2.8 Interrupt Mask Register 1 (Index=07h, Default=00h).......................77

9.5.2.2.9 Interrupt Mask Register 2 (Index=08h, Default=00h).......................77

9.5.2.2.10 Interrupt Mask Register 3 (Index=09h, Default=00h).......................77

9.5.2.2.11 VID Register (Index=0Ah) ................................................................ 77

9.5.2.2.12 Fan Tachometer Divisor Register (Index=0Bh, Default=09h).......... 77

9.5.2.2.13 Fan Tachometer 16-bit Counter Enable Register (Index=0Ch,

Default=00h) .....................................................................................................78

9.5.2.2.14 Fan Tachometer 1-3 Reading Registers (Index=0Dh-0Fh).............. 78

9.5.2.2.15 Fan Tachometer 1-3 Limit Registers (Index=10h-12h) .................... 78

9.5.2.2.16 Fan Controller Main Control Register (Index=13h, Default=00h).....78

9.5.2.2.17 FAN_CTL Control Register (Index=14h, Default=50h) .................... 79

9.5.2.2.18 FAN_CTL1 PWM Control Register (Index=15h, Default=00h or 40h).

.....................................................................................................79

9.5.2.2.19 FAN_CTL2 PWM Control Register (Index=16h, Default=00h or 40h).

.....................................................................................................80

9.5.2.2.20 FAN_CTL3 PWM Control Register (Index=17h, Default=00h or 40h).

.....................................................................................................80

9.5.2.2.21 Fan Tachometer 1-3 Extended Reading Registers (Index=18h-1Ah)..

.....................................................................................................80

9.5.2.2.22 Fan Tachometer 1-3 Extended Limit Registers (Index=1Bh-1Dh)... 80

9.5.2.2.23 VIN7-VIN0 Voltage Reading Registers (Index=27h-20h)................. 80

9.5.2.2.24 VBAT Voltage Reading Register (Index=28h)..................................80

9.5.2.2.25 TMPIN3-1 Temperature Reading Registers (Index=2Bh-29h)......... 81

9.5.2.2.26 VIN7-0 Low Limit Registers (Index=3Fh, 3Dh, 3Bh, 39h, 37h, 35h,

33h, 31h) .....................................................................................................81

9.5.2.2.27 TMPIN3-1 High Limit Registers (Index=44h, 42h, 40h) ................... 81

9.5.2.2.28 TMPIN3-1 Low Limit Registers (Index=45h, 43h, 41h)....................82

9.5.2.2.29 ADC Voltage Channel Enable Register (Index=50h, Default=00h).. 82

9.5.2.2.30 ADC Temperature Channel Enable Register (Index=51h,

Default=00h) .....................................................................................................82

9.5.2.2.31 TMPIN3-1 Thermal Output Limit Registers (Index=54h-52h,

Default=7Fh) ..................................................................................................... 82

9.5.2.2.32 Thermal Diode Zero Degree Adjust 1 Register (Index=56h,

Default=56h) .....................................................................................................82

9.5.2.2.33 Thermal Diode Zero Degree Adjust 2 Register (Index=57h,

Default=56h) .....................................................................................................82

9.5.2.2.34 Vendor ID Register (Index=58h, Default=90h).................................82

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9.5.2.2.35 Thermal Diode Zero Degree Adjust 3 Register (Index=59h,

Default=56h) .....................................................................................................83

9.5.2.2.36 Code ID Register (Index=5Bh, Default=12h) ................................... 83

9.5.2.2.37 Beep Event Enable Register (Index=5Ch, Default=00h).................. 83

9.5.2.2.38 Beep Frequency Divisor of Fan Event Register (Index=5Dh,

Default=00h) .....................................................................................................83

9.5.2.2.39 Beep Frequency Divisor of Voltage Event Register (Index=5Eh,

Default=00h) .....................................................................................................83

9.5.2.2.40 Beep Frequency Divisor of Temper ature Event Register (I ndex=5Fh,

Default=00h) .....................................................................................................83

9.5.2.2.41 FAN_CTL3-1 SmartGuar dian Automatic Mode Temperature Lim it of

OFF Registers (Index=70h, 68h, 60h, Default=7Fh) .............................................83

9.5.2.2.42 FAN_CTL3-1 SmartGuar dian Automatic Mode Temperature Lim it of

Fan Start Registers (Index=71h, 69h, 61h, Default=7Fh)......................................84

9.5.2.2.43 FAN_CTL3-1 SmartGuar dian Automatic Mode Temperature Lim it of

Full Speed Registers (Index=72h, 6Ah, 62h, Default=7Fh) ................................... 84

9.5.2.2.44 FAN_CTL3-1 SmartGuar dian Automatic Mode Start PW M Registers

(Index=73h, 6Bh, 63h, Default=00h)...................................................................... 84

9.5.2.2.45 FAN_CTL3-1 SmartGuardian Automatic Mode Control Registers

(Index=74h, 6Ch, 64h, Default=00h)...................................................................... 84

9.5.2.2.46 FAN_CTL3-1 SmartGuar dian Automatic Mode Temperature Lim it of

Full-Speed-OFF Registers (Index=75h, 6Dh, 65h, Default=7Fh)..........................85

9.5.2.2.47 Fan Tachometer 4-5 Reading LSB Registers (Index=80h,82h)....... 85

9.5.2.2.48 Fan Tachometer 4-5 Reading MSB Registers (Index=81h,83h)...... 85

9.5.2.2.49 Fan Tachometer 4-5 Limit LSB Registers (Index=84h,86h)............. 85

9.5.2.2.50 Fan Tachometer 4-5 Limit MSB Registers (Index=85h,87h)............ 85

9.5.2.2.51 FAN_CTL4 PWM Control Register (Index=88h, Default=00h) ........85

9.5.2.2.52 FAN_CTL5 PWM Control Register (Index=89h, Default=00h) ........85

9.5.2.2.53 FAN_CTL5-4 SmartGuar dian Automatic Mode Temperature Lim it of

OFF Registers (Index=98h, 90h, Default=7Fh) .....................................................86

9.5.2.2.54 FAN_CTL5-4 SmartGuar dian Automatic Mode Temperature Lim it of

Fan Start Registers (Index=99h, 91h, Default=7Fh)..............................................86

9.5.2.2.55 FAN_CTL5-4 SmartGuar dian Automatic Mode Temperature Lim it of

Full Speed Registers (Index=9Ah, 92h, Default=7Fh) ........................................... 86

9.5.2.2.56 FAN_CTL5-4 SmartGuar dian Automatic Mode Start PW M Registers

(Index=9Bh, 93h, Default=00h).............................................................................. 86

9.5.2.2.57 FAN_CTL5-4 SmartGuardian Automatic Mode Control Registers

(Index=9Ch, 94h, Default=00h).............................................................................. 86

9.5.2.2.58 FAN_CTL5-4 SmartGuar dian Automatic Mode Temperature Lim it of

Full-Speed-OFF Registers (Index=9Dh, 95h, Default=7Fh) ..................................87

9.5.3 Operation..............................................................................................................................87

9.5.3.1 Power On RESET and Software RESET................................................................. 87

9.5.3.2 Starting Conversion ................................................................................................. 87

9.5.3.3 Voltage and Temperature Inputs.............................................................................88

9.5.3.4 Layout and Grounding ............................................................................................. 89

9.5.3.5 Fan Tachometer ......................................................................................................89

9.5.3.6 Interrupt of the EC ...................................................................................................89

9.5.3.7 FAN Controller FAN_CTL’s ON-OFF and SmartGuardian Modes .......................... 91

9.6 Floppy Disk Controller (FDC)............................................................................................................92

9.6.1 Introduction........................................................................................................................... 92

9.6.2 Reset....................................................................................................................................92

9.6.3 Hardware Reset (LRESET# Pin)..........................................................................................92

9.6.4 Software Reset (DOR Reset and DSR Reset).....................................................................92

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9.6.5 Digital Data Separator ..........................................................................................................92

9.6.6 Write Precompensation........................................................................................................92

9.6.7 Data Rate Selection.............................................................................................................. 92

9.6.8 Status, Data and Control Registers......................................................................................93

9.6.8.1 Digital Output Register (DOR, FDC Base Address + 02h) ...................................... 93

9.6.8.2 Tape Drive Register (TDR, FDC Base Address + 03h)...........................................93

9.6.8.3 Main Status Register (MSR, FDC Base Address + 04h).........................................93

9.6.8.4 Data Rate Select Register (DSR, FDC Base Address + 04h)................................. 95

9.6.8.5 Data Register (FIFO, FDC Base Address + 05h) ....................................................96

9.6.8.6 Digital Input Register (DIR, FDC Base Address + 07h)...........................................96

9.6.8.7 Diskette Control Register (DCR, FDC Base Address + 07h)................................... 96

9.6.9 Controller Phases.................................................................................................................97

9.6.9.1 Command Phase.....................................................................................................97

9.6.9.2 Execution Phase......................................................................................................97

9.6.9.3 Result Phase............................................................................................................ 97

9.6.9.4 Result Phase Status Registers................................................................................97

9.6.10 Command Set ....................................................................................................................100

9.6.11 Data Transfer Commands..................................................................................................110

9.6.11.1 Read Data.............................................................................................................. 110

9.6.11.2 Read Deleted Data ................................................................................................111

9.6.11.3 Read a Track .........................................................................................................111

9.6.11.4 Write Data.............................................................................................................. 111

9.6.11.5 Write Deleted Data ................................................................................................ 111

9.6.11.6 Format A Track...................................................................................................... 111

9.6.11.7 SCAN.....................................................................................................................112

9.6.11.8 VERIFY..................................................................................................................113

9.6.12 Control Commands ............................................................................................................113

9.6.12.1 READ ID ................................................................................................................114

9.6.12.2 Configure ...............................................................................................................114

9.6.12.3 RE-CALIBRATE..................................................................................................... 114

9.6.12.4 SEEK .....................................................................................................................115

9.6.12.5 RELATIVE SEEK...................................................................................................115

9.6.12.6 DUMPREG............................................................................................................. 115

9.6.12.7 LOCK..................................................................................................................... 115

9.6.12.8 VERSION............................................................................................................... 115

9.6.12.9 SENSE INTERRUPT STATUS.............................................................................. 116

9.6.12.10 SENSE DRIVE STATUS .......................................................................................116

9.6.12.11 SPECIFY................................................................................................................ 116

9.6.12.12 PERPENDICULAR MODE..................................................................................... 117

9.6.12.13 INVALID.................................................................................................................118

9.6.13 DMA Transfers ...................................................................................................................118

9.6.14 Low Power Mode................................................................................................................ 118

9.7 Serial Port (UART) Description ....................................................................................................... 119

9.7.1 Data Registers....................................................................................................................119

9.7.2 Control Registers: IER, IIR, FCR, DLL, DLM, LCR and MCR............................................119

9.7.3 Status Registers: LSR and MSR ........................................................................................ 125

9.7.4 Reset..................................................................................................................................127

9.7.5 Programming...................................................................................................................... 127

9.7.6 Software Reset................................................................................................................... 127

9.7.7 Clock Input Operation......................................................................................................... 127

9.7.8 FIFO Interrupt Mode Operation..........................................................................................128

9.8 Smart Card Reader.........................................................................................................................129

9.8.1 Features ............................................................................................................................. 129

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Contents

9.8.2 Operation............................................................................................................................129

9.8.3 Connection of IFD to ICC Socket ....................................................................................... 129

9.8.4 Baud Rate Relationship Between UART and Smart Card Interface .................................. 130

9.8.5 Waveform Relationship......................................................................................................130

9.8.6 Clock Divider ......................................................................................................................130

9.8.7 Waveform Example of Activation/Deactivation Sequence ................................................. 131

9.8.8 ATR and PTS Structure...................................................................................................... 132

9.8.9 Smart Card Operating Sequence Example........................................................................133

9.9 Parallel Port..................................................................................................................................... 134

9.9.1 SPP and EPP Modes .........................................................................................................134

9.9.2 EPP Mode Operation.......................................................................................................... 136

9.9.3 ECP Mode Operation .........................................................................................................137

9.10 Keyboard Controller (KBC)..............................................................................................................143

9.10.1 Host Interface .....................................................................................................................144

9.10.2 Data Registers and Status Register ................................................................................... 144

9.10.3 Keyboard and Mouse Interface ..........................................................................................145

9.10.4 KIRQ and MIRQ .................................................................................................................145

9.11 Consumer Remote Control (TV Remote) IR (CIR)......................................................................... 146

9.11.1 Overview............................................................................................................................. 146

9.11.2 Features ............................................................................................................................. 146

9.11.3 Block Diagram .................................................................................................................... 146

9.11.4 Transmit Operation............................................................................................................. 147

9.11.5 Receive Operation.............................................................................................................. 147

9.11.6 Register Descriptions and Address....................................................................................147

9.11.6.1 CIR Data Register (DR).........................................................................................148

9.11.6.2 CIR Interrupt Enable Register (IER) ......................................................................148

9.11.6.3 CIR Receiver Control Register (RCR) ................................................................... 149

9.11.6.4 CIR Transmitter Control Register 1 (TCR1) ..........................................................150

9.11.6.5 CIR Transmitter Control Register (TCR2) .............................................................151

9.11.6.6 CIR Baud Rate Divisor Low Byte Register (BDLR)................................................ 154

9.11.6.7 CIR Baud Rate Divisor High Byte Register (BDHR)..............................................154

9.11.6.8 CIR Transmitter Status Register (TSR).................................................................154

9.11.6.9 CIR Receiver FIFO Status Register (RSR)............................................................155

9.11.6.10 CIR Interrupt Identification Register (IIR)............................................................... 155

9.12 Game Port Interface........................................................................................................................156

9.12.1 Game Port (Base+0h) ........................................................................................................156

9.13 MIDI Interface.................................................................................................................................. 156

9.13.1 MPU-401 Register Interface...............................................................................................156

9.13.2 Operation............................................................................................................................ 157

10. DC Electrical Characteristics .....................................................................................................................158

11. AC Characteristics (VCC = 5V ± 5%, Ta = 0°C to + 70°C)........................................................................161

11.1 Clock Input Timings ........................................................................................................................161

11.2 LCLK (PCICLK) and LRESET Timings ........................................................................................... 161

11.3 LPC and SERIRQ Timings..............................................................................................................162

11.4 Serial Port, ASKIR, SIR and Consumer Remote Control Timings..................................................163

11.5 Modem Control Timings..................................................................................................................163

11.6 Floppy Disk Drive Timings ..............................................................................................................164

11.7 EPP Address or Data Write Cycle Timings..................................................................................... 165

11.8 EPP Address or Data Read Cycle Timings..................................................................................... 166

11.9 ECP Parallel Port Forward Timings ................................................................................................166

11.10 ECP Parallel Port Backward Timings.............................................................................................167

11.11 RSMRST#, PWROK1/2, and ACPI Power Control Signals Timings..............................................167

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IT8712F

12. Package Information.................................................................................................................................. 169

13. Ordering Information..................................................................................................................................171

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viii

Contents

FIGURES

Figure 7-1. IT8712F Special Applications Circuitry for Intel ICH.......................................................................23

Figure 9-1. Start Frame Timing ......................................................................................................................... 66

Figure 9-2. Stop Frame Timing .........................................................................................................................66

Figure 9-3. General Logic of GPIO Function..................................................................................... ................69

Figure 9-4. Application Example. Resistor should provide approximately 2V at the Analog Inputs.................. 88

Figure 9-5. Temperature Interrupt Response Diagram.....................................................................................90

Figure 9-6. SmartGuardian Automatic Mode.....................................................................................................91

Figure 9-7. Smart Card Reader Application ....................................................................................................129

Figure 9-8. 9600 Baud Rate Example.............................................................................................................130

Figure 9-9. Waveform Example of IFD ...........................................................................................................131

Figure 9-10. Keyboard and Mouse Interface...................................................................................................143

Figure 9-11. CIR Block Diagram .....................................................................................................................146

Figure 11-1. Clock Input Timings .................................................................................................................... 161

Figure 11-2. LCLK (PCICLK) and LRESET Timings....................................................................................... 161

Figure 11-3. LPC and SERIRQ Timings..........................................................................................................162

Figure 11-4. Serial Port, ASKIR, SIR and Consumer Remote Control Timings.............................................. 163

Figure 11-5. Modem Control Timings..............................................................................................................163

Figure 11-6. Floppy Disk Drive Timings .......................................................................................................... 164

Figure 11-7. EPP Address or Data Write Cycle Timings.................................................................................165

Figure 11-8. EPP Address or Data Read Cycle Timings................................................................................. 166

Figure 11-9. ECP Parallel Port Forward Timings ............................................................................................ 166

Figure 11-10. ECP Parallel Port Backward Timings........................................................................................167

TABLES

Table 4-1. Pins Listed in Numeric Order.............................................................................................................8

Table 5-1. Pin Description of Supplies Signals....................................................................................................9

Table 5-2. Pin Description of LPC Bus Interface Signals....................................................................................9

Table 5-3. Pin Description of MIDI Interface Signals......................................................................................... 10

Table 5-4. Pin Description of Game Port Signals.............................................................................................. 10

Table 5-5. Pin Description of Hardware Monitor Signals

Table 5-6. Pin Description of Fan Controller Signals ........................................................................................13

Table 5-7. Pin Description of Infrared Port Signals ........................................................................................... 14

Table 5-8. Pin Description of Serial Port 1 Signals............................................................................................14

Table 5-9. Pin Description of Serial Port 2 Signals............................................................................................15

Table 5-10. Pin Description of Parallel Port Signals..........................................................................................16

Table 5-11. Pin Description of Floppy Disk Controller Signals.......................................................................... 17

Table 5-12. Pin Description of Smart Card Reader Interface Signals...............................................................17

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Note1

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ix ix

IT8712F

Table 5-13. Pin Description of Keyboard Controller Signals .............................................................................19

Table 5-14. Pin Description of Miscellaneous Signals ......................................................................................19

Table 6-1. General Purpose I/O Group 1 (Set 1) .............................................................................................. 21

Table 6-2. General Purpose I/O Group 2 (Set 2) .............................................................................................. 21

Table 6-3. General Purpose I/O Group 3 (Set 3) .............................................................................................. 21

Table 6-4. General Purpose I/O Group 4 (Set 4) .............................................................................................. 22

Table 6-5. General Purpose I/O Group 5 (Set 5) .............................................................................................. 22

Table 7-1. Power On Strapping Options............................................................................................................ 23

Table 8-1. Global Configuration Registers ........................................................................................................27

Table 8-2. FDC Configuration Registers ........................................................................................................... 27

Table 8-3. Serial Port 1 Configuration Registers...............................................................................................27

Table 8-4. Serial Port 2 Configuration Registers...............................................................................................28

Table 8-5. Parallel Port Configuration Registers...............................................................................................28

Table 8-6. Environment Controller Configuration Registers.............................................................................. 28

Table 8-7. KBC(Keyboard) Configuration Registers.......................................................................................... 29

Table 8-8. KBC(Mouse) Configuration Registers..............................................................................................29

Table 8-9. GPIO Configuration Registers..........................................................................................................30

Table 8-10. GPIO Configuration Registers........................................................................................................31

Table 8-11. MIDI Port Configuration Registers .................................................................................................32

Table 8-12. Game Port Configuration Registers ............................................................................................... 32

Table 8-13. Consumer IR Configuration Registers ........................................................................................... 32

Table 8-14. Base Address of Logical Devices................................................................................................... 32

Table 9-1. Address Map on the LPC Bus.......................................................................................................... 71

Table 9-2. Environment Controller Registers .................................................................................................... 72

Table 9-3. Digital Output Register (DOR)..........................................................................................................93

Table 9-4. Tape Drive Register (TDR) .............................................................................................................. 93

Table 9-5. Main Status Register (MSR) ............................................................................................................94

Table 9-6. Data Rate Select Register (DSR).....................................................................................................95

Table 9-7. Data Register (FIFO)........................................................................................................................ 96

Table 9-8. Digital Input Register (DIR) ..............................................................................................................96

Table 9-9. Diskette Control Register (DCR)......................................................................................................96

Table 9-10. Status Register 0 (ST0)..................................................................................................................97

Table 9-11. Status Register 1 (ST1)..................................................................................................................98

Table 9-12. Status Register 2 (ST2)..................................................................................................................99

Table 9-13. Status Register 3 (ST3)..................................................................................................................99

Table 9-14. Command Set Symbol Descriptions ............................................................................................ 100

Table 9-15. Command Set Summary..............................................................................................................102

Table 9-16. Effects of MT and N Bits .............................................................................................................. 110

Table 9-17. SCAN Command Result .............................................................................................................. 112

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Contents

Table 9-18. VERIFY Command Result ...........................................................................................................113

Table 9-19. Interrupt Identification................................................................................................................... 116

Table 9-20. HUT Values.................................................................................................................................. 116

Table 9-21. SRT Values..................................................................................................................................116

Table 9-22. HLT Values ..................................................................................................................................117

Table 9-23. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands....................... 117

Table 9-24. Effects of Drive Mode and Data Rate on FORMAT A TRACK and WRITE DATA Commands ..117

Table 9-25. Serial Channel Registers.............................................................................................................. 119

Table 9-26. Interrupt Enable Register Description ..........................................................................................120

Table 9-27. Interrupt Identification Register ....................................................................................................121

Table 9-28. FIFO Control Register Description...............................................................................................122

Table 9-29. Receiver FIFO Trigger Level Encoding........................................................................................122

Table 9-30. Baud Rates Using (24 MHz ÷ 13) Clock ...................................................................................... 123

Table 9-31. Line Control Register Description ................................................................................................124

Table 9-32. Stop Bits Number Encoding.........................................................................................................124

Table 9-33. Modem Control Register Description...........................................................................................125

Table 9-34. Line Status Register Description..................................................................................................125

Table 9-35. Modem Status Register Description............................................................................................. 126

Table 9-36. Reset Control of Registers and Pinout Signals............................................................................127

Table 9-37. SCRCLK Selections.....................................................................................................................130

Table 9-38. Parallel Port Connector in Different Modes.................................................................................. 134

Table 9-39. Address Map and Bit Map for SPP and EPP Modes ...................................................................134

Table 9-40. Bit Map of the ECP Registers ......................................................................................................137

Table 9-41. ECP Register Definitions..............................................................................................................137

Table 9-42. ECP Mode Descriptions...............................................................................................................138

Table 9-43. ECP Pin Descriptions...................................................................................................................138

Table 9-44. Extended Control Register (ECR) Mode and Description............................................................140

Table 9-45. Data Register READ/WRITE Controls.........................................................................................144

Table 9-46. Status Register.............................................................................................................................144

Table 9-47. List of CIR Registers .................................................................................................................... 147

Table 9-48. Modulation Carrier Frequency......................................................................................................152

Table 9-49. Receiver Demodulation Low Frequency (HCFS = 0)...................................................................153

Table 9-50. Receiver Demodulation High Frequency (HCFS = 1)..................................................................154

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xi xi

1. Features

 Low Pin Count Interface

− Comply with Intel Low Pin Count Interface

Specification Rev. 1.0

− Supports LDRQ#, SERIRQ protocols

− Supports PCI PME# Interfaces

 ACPI & LANDesk Compliant

− ACPI V. 1.0 compliant

− Register sets compatible with “Plug and Play

ISA Specification V. 1.0a”

− LANDesk 3.X compliant

− Supports 12 logical devices

 Enhanced Hardware Monitor

− Built-in 8-bit Analog to Digital Converter

− 3 thermal inputs from remote thermal resistor

or thermal diode or diode-connected transistor

− 8 voltage monitor inputs (VBAT is measured

internally.)

− 1 chassis open detection input with low power

Flip-Flop backed by the battery

− Watch Dog comparison of all monitored values

− Provides VID0 – VID5 support for the CPU

 Fan Speed Controller

− Provides fan on-off and PWM control

− Supports 5 programmable Pulse Width

Modulation (PWM) outputs

− 128 steps of PWM modes

− Monitors 5 fan tachometer inputs

 SmartGuardian Controller

− Provides programmable fan speed automatic

control

− Supports mix-and-match for temperature inputs

and fan speed control outputs

− Overrides fan speed controller during

catastrophic situations

− Provides over temperature beep tone warning

 Two 16C550 UARTs

− Supports two standard Serial Ports

− Supports IrDA 1.0/ASKIR protocols

− Supports Smart Card Reader protocols

Features

 Smart Card Reader

− Compliant with Personal Computer Smart Card

(PC/SC) Working Group standard

− Compliant with smart card (ISO 7816) protocols

− Supports card present detect

− Supports Smart Card insertion power-on

feature

− Supports one programmable clock frequency,

and 7.1 MHz and 3.5 MHz (Default) card clocks

 Consumer Remote Control (TV remote) IR

with power-up feature

 IEEE 1284 Parallel Port

− Standard mode -- Bi-directional SPP compliant

− Enhanced mode -- EPP V. 1.7 and V. 1.9

compliant

− High speed mode -- ECP, IEEE 1284 compliant

− Back-drive current reduction

− Printer power-on damage reduction

− Supports POST (Power-On Self Test) Data

Port

 Floppy Disk Controller

− Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M

floppy disk drives

− Enhanced digital data separator

− 3-Mode drives supported

− Supports automatic write protection via

software

 Keyboard Controller

− 8042 compatible for PS/2 keyboard and mouse

− 2KB of custom ROM and 256-byte data RAM

− GateA20 and Keyboard reset output

− Supports any key, or 2-5 sequential keys, or 1-

3 simultaneous keys keyboard power-on events

− Supports mouse double-click and/or mouse

move power on events

− Supports Keyboard and Mouse I/F hardware

auto-swap

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1

ITPM-PN-200415
Specifications subject to Change without Notice By Joseph, 4/20/2004

IT8712F

 Game Port

− Built-in 558 quad timers and buffer chips

− Supports direct connection of two joysticks

 Dedicated MIDI Interface

− MPU-401 UART mode compatible

 38 General Purpose I/O Pins

− Input mode supports either switch de-bounce or

programmable external IRQ input routing

− Output mode supports 2 sets of programmable

LED blinking periods

 External IRQ Input Routing Capability

− Provides IRQ input routing through GPIO input

mode

− Programmable registers for IRQ routing

 ITE innovative automatic power-failure

resume and power button de-bounce

 Dedicated Infrared pins

 VCCH and Vbat S upported

 Built-in 32.768 KHz Oscillator

 Single 24/48 MHz Clock Input

 +5V Power Supply

 128-pin QFP

 Watch Dog Timer

− Time resolution 1 minute or 1 second,

maximum 255 minutes or 255 seconds

− Output to KRST# when expired

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2

General Description

2. General Description

The IT8712F is a Low Pin Count Interfac e-based highly integrated Super I/O. The IT 8712F provides the m ost
commonly used legacy Super I/O functionality plus the latest Environm ent Control initiatives, such as H/W
Monitor, Fan Speed Controller, ITE’s “SmartGuardian” function and Smart Card Reader Interface. The
device’s LPC interface complies with Intel “LPC Interface Specification Rev. 1.0”. The IT8712F is ACPI &
LANDesk compliant.

The IT8712F features the enhanced hardware monitor providing 3 thermal inputs from remote thermal
resistors, or thermal diode or diode-connected transistor (2N3094). The device also provides the ITE
innovative intelligent automatic Fan ON/OFF & speed control functions (SmartGuardian) to protect the system,
reducing the system noise and power consum ption. It also features a PC/SC and ISO 7816 compliant Sm art
Card Reader.

The IT8712F contains one gam e port which supports 2 joysticks, 1 MIDI port, and 1 Fan Speed Contr oller.
The fan speed controller is responsible to control 5 fan speeds through three 128 steps of Pulse Width
Modulation (PWM) output pins and to monitor five FANs’ Tachometer inputs. It also features two 16C550
UARTs, one IEEE 1284 Parallel Port, one Floppy Disk Controller and one 8042 Keyboard Controller.

The IT8712F has integrated 12 logical devices. One high-performance 2.88MB floppy disk controller, with
digital data separator, supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy disk drives. One multi-mode high­performance parallel port featur es the bi-directional Standard Parallel Por t (SPP), the Enhanced Parallel Port
(EPP V. 1.7 and EPP V. 1.9 are supported), and the IEEE 1284 com pliant Extended Capabilities Port (ECP).
Two 16C550 standard compatible enhanced UART s perf orm asynchronous comm unication, and als o support
either IR or MIDI interfaces. One game port with built-in 558 quad timers and buffer chips supports direct
connection of 2 joysticks. T he device also features one MPU-401 UART m ode compatible MIDI port, one f an
speed controller responsible for controlling / monitor ing 5 f ans and 5 G PIO por ts (38 G PIO pins ) . T he IT8712F
also has an integrated 8042 compatible Keyboard Controller with 2KB of programmable RO M for customer
application.

These 12 logical devices can be individually enabled or disabled via software configuration registers. The
IT8712F utilizes power-saving circuitry to reduce power consumption, and once a logical device is disabled the
inputs are gated inhibit, the outputs are tri-state, and the input c lock is disabled. T he device requires a single
24/48 MHz clock input and operates with +5V power supply. The IT8712F is available in 128- pin QFP (Quad
Flat Package).

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4

3. Block Diagram

F

/

I

SERIRQ

C
P

L

CLKRUN#

LDRQ#

Block Diagram

24 / 48 MHz

OSC.

Serial Port I/F

IR I/F

SCR I/F

Serial Port I/F

Parallel Port

I/F

Floppy

Drive I/F

Clock

Gen.

16C550
UART 1

IrDA 1.0 /

ASKIR

Smart Card

Reader

16C550

UART 2

IEEE1284

Parallel

Port

Floppy

Disk

Controller

LPC Interface

& Plug-and-Play

Registers

s

u
B

e

c

a

f

r

e

t

n

I

l

a

r

t

n

e
C

Keyboard
Controller

MPU-401

UART

mode

Consumer

I/R

Game

Port

General

Purpose

I/O

Fan

Speed

Controller

PME#

Mouse I/F

Keyboard I/F

MIDI I/F

CIR I/F

Joystick I/F

I/O Ports

Fan I/F

8-bit

ADC

Monitored

Voltages

Environment Controller

Fan

Tachometers

Thermal
Resistor

Thermal

Diode

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4. Pin Configuration

DTR2#/JP4

RTS2/JP5

DSR2#

VCC

SOUT2/JP6

SIN2
FAN_TAC1
FAN_CTL1

FAN_TAC2/GP52

FAN_CTL2/GP51

FAN_TAC3/GP37

FAN_CTL3/GP36

VID5/GP35
VID4/GP34

GNDD

VID3/GP33
VID2/GP32
VID1/GP31

FAN_CTL4/JSBB2/GP27

FAN_CTL5/JSBB1/GP26
FAN_TAC4/JSBCY/GP25
FAN_TAC5/JSBCX/GP24

RESETCON#/CIRTX/GP15

PCIRST1#/SCRRST/GP14

PWROK1/SCRPFET#/GP13

PCIRST2#/SCRIO/GP12

PCIRST3#/SCRCLK/GP11

VID0/GP30

JSAB2/GP23

JSAB1/GP22
JSACY/GP21
JSACX/GP20

MIDI_OUT/GP17

MIDI_IN/GP16

VCC

VIDVCC

LRESET#

LDRQ#

PD6

PD7

GNDD

DCD1#

RI1#

CTS1#

DTR1#/JP1

RTS1#/JP2

DSR1#

SOUT1/JP3

SIN1

DCD2#

RI2#

CTS2#

115

116

117

118

119

120

121

122

123

124

125

126

127

128

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39404142434445464748495051525354555657

IT8712F

128-QFP

PD5

114

PD4

113

PD3

112

PD2

111

PD1

110

ERR#

AFD#

STB#

PD0

109

106

107

108

58

5960616263

Pin Configuration

ACK#

SLIN#

INIT#

104

105

103

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

64

BUSY
PE
SLCT
VCC
VIN0
VIN1
VIN2
VIN3/ATXPG
VIN4
VIN5
VIN6
VIN7/PCIRSTIN#
VREF
TMPIN1
TMPIN2
TMPIN3
GNDA

RSMRST#/CIRRX/GP55
PCIRST4#/SCRPSNT#/GP10

MCLK
MDAT
KCLK
KDAT
GP40
PWROK2/GP41
GP53
PSON#/GP42
PANSWH#/GP43
GNDD
PME#/GP54
PWRON#/GP44

PSIN/GP45
IRRX/GP46
VBAT
COPEN#
VCCH
IRTX/GP47
DSKCHG#

LAD0

LAD1

LAD2

LAD3

GA20

CLKIN

PCICLK

GNDD

MTRA#

DENSEL#

MTRB#/THRMO#

PCIRST5#/CLKRUN#/GP50

SERIRQ

LFRAME#

KRST#

DRVA#

DRVB#

DIR#

STEP#

HDSEL#

WDATA#

WGATE#

RDATA#

TRK0#

WPT#

INDEX#

Top View

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IT8712F

Table 4-1. Pins Listed in Numeric Order

Pin Signal Pin Signal Pin Signal Pin Signal

1 DTR2#/JP4 33
2 RTS2#/JP5 34

PCIRST2#/SCRIO
/GP12
PCIRST3#/SCRC
LK/GP11

65 DSKCHG# 97 VIN1
66 IRTX/GP47 98 VIN0

3 DSR2# 35 VCC 67 VCCH 99 VCC
4 VCC 36 VIDVCC 68 COPEN# 100 SLCT
5 SOUT2/JP6 37 LRESET# 69 VBAT 101 PE
6 SIN2 38 LDRQ# 70 IRRX/GP46 102 BUSY
7 FAN_TAC1 39 SERIRQ 71 GP45 103 ACK#
8 FAN_CTL1 40 LFRAME# 72 PWRON#/GP44 104 SLIN#

9 FAN_TAC2/GP52 41 LAD0 73 PME#/GP54 105 INIT#
10 FAN_CTL2/GP51 42 LAD1 74 GNDD 106 ERR#
11 FAN_TAC3/GP37 43 LAD2 75 PANSWH#/GP43 107 AFD#
12 FAN_CTL3/GP36 44 LAD3 76 PSON#/GP42 108 STB#
13 VID5/GP35 45 KRST# 77 GP53 109 PD0
14 VID4/GP34 46 GA20 78 PWROK2/GP41 110 PD1
15 GNDD 47 PCICLK 79 GP40 111 PD2

16 VID3/GP33 48

PCIRST5#/CLKR
UN#/GP50

80 KDAT 112 PD3

17 VID2/GP32 49 CLKIN 81 KCLK 113 PD4
18 VID1/GP31 50 GNDD 82 MDAT 114 PD5
19 VID0/GP30 51 DENSEL# 83 MCLK 115 PD6

FAN_CTL4/JSBB

20

2/GP27
FAN_CTL5/JSBB

21

1/GP26
FAN_TAC4/JSBC

22

Y/GP25
FAN_TAC5/JSBC

23

X/GP24

52 MTRA# 84

53 MTRB#/THRMO# 85
54 DRVA# 86 GNDA 118 DCD1#
55 DRVB# 87 TMPIN3 119 RI1#

PCIRST4#/

SCRPSNT#/GP1

0
RSMRST#/CIRRX
/GP55

116 PD7

117 GNDD

24 JSAB2/GP23 56 WDATA# 88 TMPIN2 120 CTS1#
25 JSAB1/GP22 57 DIR# 89 TMPIN1 121 DTR1#/JP1
26 JSACY/GP21 58 STEP# 90 VREF 122 RTS1#/JP2
27 JSACX/GP20 59 HDSEL# 91 VIN7/PCIRSTIN# 123 DSR1#
28 MIDI_OUT/GP17 60 WGATE# 92 VIN6 124 SOUT1/JP3
29 MIDI_IN/GP16 61 RDATA# 93 VIN5 125 SIN1

RESETCON#/CIR

30

TX/GP15
PCIRST1#/SCRR

31

ST/GP14
PWROK1/SCRPF

32

ET#/GP13

62 TRK0# 94 VIN4 126 DCD2#
63 INDEX# 95 VIN3/ATXPG 127 RI2#
64 WPT# 96 VIN2 128 CTS2#

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Pin Descriptions

5. IT8712F Pin Descriptions

Table 5-1. Pin Description of Supplies Signals

Pin(s) No. Symbol Attribute Power Description

4, 35, 99 VCC

67 VCCH
69 VBAT
36 VIDVCC

15, 50,

GNDD

PWR ­PWR ­PWR ­PWR ­GND -

74, 117

86 GNDA

GND -

Table 5-2. Pin Description of LPC Bus Interface Signals

Pin(s) No. Symbol Attribute Power Description

37 LRESET#
38 LDRQ#

39 SERIRQ
40 LFRAME#

41 – 44 LAD[0:3]

47 PCICLK

48 PCIRST5#/CLK

RUN#/GP50

DI VCC

DO16 VCC

DIO16 VCC

DI VCC

DIO16 VCC

DI VCC

DO16/DIO

D16/

VCC

DIOD16

73 PME#/GP54

DOD8/

VCCH

DIOD8

+5V Power Supply.
+5V VCC Help Supply.
+3.3V Battery Supply.
VID power supply. (1.2 or 3.3V)
Digital Ground.

Analog Ground.

LPC RESET #.
LPC DMA Request #.

An encoded signal for DMA channel select.

Serial IRQ.
LPC Frame #.

This signal indicates the start of LPC cycle.

LPC Address/Data 0 - 3.

4-bit LPC address/bi-directional data lines. LAD0 is the LSB
and LAD3 is the MSB.

PCI Clock.

33 MHz PCI clock input for LPC I/F and SERIRQ.

PCI Reset 5 # / Clock Run # / General Purpose I/O 50.

• The first function of this pin is PCI Reset 5 #. It is a
buffer output of LRESET# if bit1 of Index 2Ch is 0. It
will be (LRESET# AND PCIRSTIN#) if bit1 of Index
2Ch is 1.

• The second function of this pin is the clock run #.
This is an open-drain output and also an input. The
IT8712F uses this signal to request starting (or speed
up) the clock. CLKRUN# also indicates the clock
status.

• The third function of this pin is the General Purpose
I/O 50.

• The function configuration of this pin is decided by
the software configuration registers.

Power Management Event # / General Purpose I/O 54.

• The first function of this pin is the power
management event #. It supports the PCI PME#
interface. This signal allows the peripheral to request
the system to wake up from the D3 (cold) state.

• The second function of this pin is the General
Purpose I/O Port 5 Bit 4.

• The function configuration of this pin is determined by
programming the software configuration registers.

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IT8712F

Table 5-3. Pin Description of MIDI Interface Signals

Pin(s) No. Symbol Attribute Power Description

28 MIDI_OUT/

GP17

DO8/

DIOD8

VCC

MIDI Output / General Purpose I/O 17.

• The first function of this pin is MIDI Output.

• The second function of this pin is the General

Purpose I/O Port 1 Bit 7.

• The function configuration of this pin is determined by
programming the software configuration registers.

29 MIDI_IN/

GP16

DI/

DIOD8

VCC

MIDI Input / General Purpose I/O 16.

• The first function of this pin is MIDI Input.

• The second function of this pin is the General

Purpose I/O Port 1 Bit 6.

• The function configuration of this pin is determined by
programming the software configuration registers.

Table 5-4. Pin Description of Game Port Signals

Pin(s) No. Symbol Attribute Power Description

27 JSACX/

GP20

DIOD8/

DIOD8

VCC

Joystick A Coordinate X / General Purpose I/O 20.

• The first function of this pin is Joystick A Coordinate
X.

• The second function of this pin is the General
Purpose I/O Port 2 Bit 0.

• The function configuration of this pin is determined by
programming the software configuration registers.

26 JSACY/

GP21

DIOD8/

DIOD8

VCC

Joystick A Coordinate Y / General Purpose I/O 21.

• The first function of this pin is Joystick A Coordinate
Y.

• The second function of this pin is the General
Purpose I/O Port 2 Bit 1.

• The function configuration of this pin is determined by
programming the software configuration registers.

25 JSAB1/

GP22

DI/

DIOD8

VCC

Joystick A Button 1 / General Purpose I/O 22.

• The first function of this pin is Joystick A Button 1.

• The second function of this pin is the General

Purpose I/O Port 2 Bit 2.

• The function configuration of this pin is determined by
programming the software configuration registers.

24 JSAB2/

GP23

DI/

DIOD8

VCC

Joystick A Button 2 / General Purpose I/O 23.

• The first function of this pin is Joystick A Button 2.

• The second function of this pin is the General

Purpose I/O Port 2 Bit 3.

• The function configuration of this pin is determined by
programming the software configuration registers.

23 FAN_TAC5/

JSBCX/

GP24

DI/

DIOD8/

DIOD8

VCC

Joystick B Coordinate X / General Purpose I/O 24.

• The first function of this pin is Fan Tachometer Input

5. 0 to +5V amplitude fan tachometer input.

• The second function of this pin is Joystick B
Coordinate X.

• The third function of this pin is the General Purpose
I/O Port 2 Bit 4.

• The function configuration of this pin is determined by
programming the software configuration registers.

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10

Pin Descriptions

Pin(s) No. Symbol Attribute Power Description

22 FAN_TAC4/

JSBCY/

GP25

DI/

DIOD8/

DIOD8

VCC

Joystick B Coordinate Y / General Purpose I/O 25.

• The first function of this pin is Fan Tachometer Input

4. 0 to +5V amplitude fan tachometer input.

• The second function of this pin is Joystick B
Coordinate Y.

• The third function of this pin is the General Purpose
I/O Port 2 Bit 5.

• The function configuration of this pin is determined by
programming the software configuration registers.

21 FAN_CTL5/

JSBB1/

GP26

DOD8

DI/

DIOD8

VCC

Joystick B Button 1 / General Purpose I/O 26.

• The first function of this pin is Fan Control Output 5.
(PWM output signal to Fan’s FET.)

• The second function of this pin is Joystick B Button 1.

• The third function of this pin is the General Purpose

I/O Port 2 Bit 6.

• The function configuration of this pin is determined by
programming the software configuration registers.

20 FAN_CTL4/

JSBB2/

GP27

DOD8/

DI/

DIOD8

VCC

Joystick B Button 2 / General Purpose I/O 27.

• The first function of this pin is Fan Control Output 4.
(PWM output signal to Fan’s FET.)

• The second function of this pin is Joystick B Button 2.

• The third function of this pin is the General Purpose

I/O Port 2 Bit 7.

• The function configuration of this pin is determined by
programming the software configuration registers.

Table 5-5. Pin Description of Hardware Monitor Signals

Pin(s) No. Symbol Attribute Power Description

98 – 96 VIN[0:2]

95 ATXPG/

VIN3

AI VCC

DI/AI VCC

Voltage Analog Inputs [0:2].

0 to 4.096V FSR Analog Inputs.

Voltage Analog Input 3 / ATX Power Good.

• The first function of this pin is ATX Power Good.

Note1

PWROK1/2 will be (VCC power-level-detect AND
RESETCON# AND PSIN AND ATXPG) if bit0 of
Index 2Ch is 1, or (VCC power-level-detect AND
RESETCON# AND PSIN) if the bit is 0.

• The second function of this pin is 0 to 4.096V FSR
Analog Inputs.

• The function configuration of this pin is determined by
programming the software configuration registers.

94 – 92 VIN[4:6]

91 PCIRSTIN#/

VIN7

AI VCC

DI/AI

VCC

Voltage Analog Inputs [4:6].

0 to 4.096V FSR Analog Inputs.

Voltage Analog Input 7 / PCI Reset Input #.

• The first function of this pin is PCI Reset Input #.

• The second function of this pin is 0 to 4.096V FSR

Analog Inputs.

• The function configuration of this pin is determined by
programming the software configuration registers.

90 VREF

89 – 87 TMPIN[1:3]

AO VCC

AI VCC

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Reference Voltage Output.

Regulated and referred voltage for 3 external temperature
sensors and negative voltage monitor.

External Thermal Inputs [1:3].

Connected to thermistors [1:3] or thermal temperature
sensors.

11

IT8712F

Pin(s) No. Symbol Attribute Power Description

7 FAN_TAC1

DI VCC

Fan Tachometer Input 1.

0 to +5V amplitude fan tachometer input.

9 FAN_TAC2/

GP52

DI/

DIOD8

VCC

Fan Tachometer Input 2 / General Purpose I/O 52.

• The first function of this pin is Fan Tachometer Input

2. 0 to +5V amplitude fan tachometer input.

• The second function of this pin is the General
Purpose I/O Port 5 Bit 2.

• The function configuration of this pin is determined by
programming the software configuration registers.

11 FAN_TAC3/

GP37

DI/

DIOD8

VCC

Fan Tachometer Input 3 / General Purpose I/O 37.

• The first function of this pin is Fan Tachometer Input

3. 0 to +5V amplitude fan tachometer input.

• The second function of this pin is the General
Purpose I/O Port 5 Bit 2.

• The function configuration of this pin is determined by
programming the software configuration registers.

19 VID0/GP30

DIO8/

DIOD8

VCC

Voltage ID 0 / General Purpose I/O 30.

• The first function of this pin is Voltage ID Input 0. The
Voltage ID is the voltage supply readouts from the
CPU. This value is read in the VID register. The input
threshold can be selected by the power-on strapping
of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when
JP6=0)

• The second function of this pin is the General
Purpose I/O 30.

• The function configuration of this pin is decided by the
software configuration registers.

18 VID1/GP31

DIO8/

DIOD8

VCC

Voltage ID 1 / General Purpose I/O 31.

• The first function of this pin is Voltage ID Input 1. The
Voltage ID is the voltage supply readouts from the
CPU. This value is read in the VID register. The input
threshold can be selected by the power-on strapping
of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when
JP6=0)

• The second function of this pin is the General
Purpose I/O 31.

• The function configuration of this pin is decided by the
software configuration registers.

17 VID2/GP32

DIO8/

DIOD8

VCC

Voltage ID 2 / General Purpose I/O 32.

• The first function of this pin is Voltage ID Input 2. The
Voltage ID is the voltage supply readouts from the
CPU. This value is read in the VID register. The input
threshold can be selected by the power-on strapping
of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when
JP6=0)

• The second function of this pin is the General
Purpose I/O 32.

• The function configuration of this pin is decided by the
software configuration registers.

16 VID3/GP33

DIO8/

DIOD8

VCC

Voltage ID 3 / General Purpose I/O 33.

• The first function of this pin is Voltage ID Input 3. The
Voltage ID is the voltage supply readouts from the
CPU. This value is read in the VID register. The input
threshold can be selected by the power-on strapping

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Pin Descriptions

Pin(s) No. Symbol Attribute Power Description

of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when
JP6=0)

• The second function of this pin is the General
Purpose I/O 33.

• The function configuration of this pin is decided by the
software configuration registers.

14 VID4/GP34

DIO8/

DIOD8

VCC

Voltage ID 4 / General Purpose I/O 34.

• The first function of this pin is Voltage ID Input 4. The
Voltage ID is the voltage supply readouts from the
CPU. This value is read in the VID register. The input
threshold can be selected by the power-on strapping
of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when
JP6=0)

• The second function of this pin is the General
Purpose I/O 34.

• The function configuration of this pin is decided by the
software configuration registers.

13 VID5/GP35

DIO8/

DIOD8

VCC

Voltage ID 5 / General Purpose I/O 35.

• The first function of this pin is Voltage ID Input 5. The
Voltage ID is the voltage supply readouts from the
CPU. This value is read in the VID register. The input
threshold can be selected by the power-on strapping
of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when
JP6=0)

• The second function of this pin is the General
Purpose I/O 35.

• The function configuration of this pin is decided by the
software configuration registers.

68 COPEN#

DIOD8 VCCH

or VBAT

Case Open Detection #.

• The Case Open Detection is connected to a specially
designed low power CMOS flip-flop backed by the
battery for case open state preservation during power
loss.

Table 5-6. Pin Description of Fan Controller Signals

Pin(s) No. Symbol Attribute Power Description

8 FAN_CTL1

DOD8 VCC

Fan Control Output 1.

(PWM output signal to Fan’s FET.)

10 FAN_CTL2/

GP51

DOD8/
DIOD8

VCC

Fan Control Output 2 / General Purpose I/O 51.

• The first function of this pin is Fan Control Output 2.
(PWM output signal to Fan’s FET.)

• The second function of this pin is the General
Purpose I/O Port 5 Bit 1.

• The function configuration of this pin is determined by
programming the software configuration registers.

12 FAN_CTL3/

GP36

DOD8/
DIOD8

VCC

Fan Control Output 3 / General Purpose I/O 36.

• The first function of this pin is Fan Control Output 3.
(PWM output signal to Fan’s FET.)

• The second function of this pin is the General
Purpose I/O Port 3 Bit 6.

• The function configuration of this pin is determined by
programming the software configuration registers.

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IT8712F

Table 5-7. Pin Description of Infrared Port Signals

Pin(s) No. Symbol Attribute Power Description

30 RESETCON#/

CIRTX/

GP15

DI/
DOD8/
DIOD8

VCC

Reset Connect # / Consumer Infrared Transmit Output /
General Purpose I/O 15.

• The first function of this pin is Reset Connect #. It
connects to reset button, and also other reset source
on the motherboard.

• The second function of this pin is Consumer Infrared
Transmit Output.

• The Third function of this pin is the General Purpose
I/O Port 1 Bit 5.

• The function configuration of this pin is determined by
programming the software configuration registers.

85 RSMRST#/

CIRRX/

GP55

DOD8/

DI/

DIOD8

VCCH

Resume Reset # / Consumer Infrared Receive Input /
General Purpose I/O 55.

• The first function of this pin is Resume Reset #. It is
power good signal of VCCH. The high threshold is 4V
± 0.2V, and the low threshold is 3.5V ± 0.2V

• The second function of this pin is Consumer Infrared
Receive Input.

• The Third function of this pin is the General Purpose
I/O Port 5 Bit 5.

• The function configuration of this pin is determined by
programming the software configuration registers.

70 IRRX/

GP46

DI/

DIOD8

VCCH

Infrared Receive Input / General Purpose I/O 46.

• The first function of this pin is Infrared Receive Input.

• The second function of this pin is the General

Purpose I/O Port 4 Bit 6.

• The function configuration of this pin is determined by
programming the software configuration registers.

66 IRTX/

GP47

DO8/

DIOD8

VCC

Infrared Transmit Output / General Purpose I/O 47.

• The first function of this pin is Infrared Transmit
output.

• The second function of this pin is the General
Purpose I/O Port 4 Bit 7.

• The function configuration of this pin is determined by
programming the software configuration registers.

Table 5-8. Pin Description of Serial Port 1 Signals

Pin(s) No. Symbol Attribute Power Description

125 SIN1

DI VCC

Serial Data Input 1.

This input receives serial data from the communications link.

124 SOUT1/

JP3

DO8/

DI

VCC

Serial Data Output 1.

This output sends serial data to the communications link.
This signal is set to a marking state (logic 1) after a Master
Reset operation or when the device is in one of the Infrared
communications modes.
During LRESET#, this pin is input for JP3 power-on strapping
option

123 DSR1#

DI VCC

Data Set Ready 1 #.

When the signal is low, it indicates that the MODEM or data
set is ready to establish a communications link. The DSR#
signal is a MODEM status input whose condition can be
tested by reading the MSR register.

122 RTS1#/

JP2

DO8/

DI

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VCC

Request to Send 1 #.

When this signal is low, this output indicates to the MODEM

14

Pin Descriptions

Pin(s) No. Symbol Attribute Power Description

or data set that the device is ready to send data. RTS# is
activated by setting the appropriate bit in the MCR register to

1. After a Master Reset operation or during Loop mode,

RTS# is set to its inactive state.

During LRESET#, this pin is input for JP2 power-on strapping
option

121 DTR1#/

JP1

DO8/

DI

VCC

Data Terminal Ready 1 #.

DTR# is used to indicate to the MODEM or data set that the
device is ready to exchange data. DTR# is activated by
setting the appropriate bit in the MCR register to 1. After a
Master Reset operation or during Loop mode, DTR# is set to
its inactive state.

During LRESET#, this pin is input for JP1 power-on strapping
option

120 CTS1#

DI VCC

Clear to Send 1 #.

When the signal is low, it indicates that the MODEM or data
set is ready to accept data. The CTS# signal is a MODEM
status input whose condition can be tested by reading the
MSR register.

119 RI1#

DI VCC

Ring Indicator 1 #.

When the signal is low, it indicates that a telephone ring
signal has been received by the MODEM. The RI# signal is a
MODEM status input whose condition can be tested by
reading the MSR register.

118 DCD1#

DI VCC

Data Carrier Detect 1 #.

When the signal is low, it indicates that the MODEM or data
set has detected a carrier. The DCD# signal is a MODEM
status input whose condition can be tested by reading the
MSR register.

Table 5-9. Pin Description of Serial Port 2 Signals

Pin(s) No. Symbol Attribute Power Description

6 SIN2

5 SOUT2/JP6

3 DSR2#

2 RTS2#/JP5

1 DTR2#/

JP4

DI VCC

DO8/DI VCC

DI VCC

DO8/DI VCC

DO8/DI VCC

Serial Data In 2.

This input receives serial data from the communications link.

Serial Data Out 2.

This output sends serial data to the communications link.
This signal is set to a marking state (logic 1) after a Master
Reset operation or when the device is in one of the Infrared
communications modes. During LRESET#, this pin is input
for JP6 power-on strapping option

Data Set Ready 2 #.

When low, indicates that the MODEM or data set is ready to
establish a communications link. The DSR# signal is a
MODEM status input whose condition can be tested by
reading the MSR register.

Request to Send 2 #.

When low, this output indicates to the MODEM or data set
that the device is ready to send data. RTS# is activated by
setting the appropriate bit in the MCR register to 1. After a
Master Reset operation or during Loop mode, RTS# is set to
its inactive state. During LRESET#, this pin is input for JP5
power-on strapping option

Data Terminal Ready 2 #.

DTR# is used to indicate to the MODEM or data set that the
device is ready to exchange data. DTR# is activated by
setting the appropriate bit in the MCR register to 1. After a
Master Reset operation or during Loop mode, DTR# is set to
its inactive state.

During LRESET#, this pin is input for JP4 power-on strapping

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15

IT8712F

Pin(s) No. Symbol Attribute Power Description

option

128 CTS2#

DI VCC

Clear to Send 2 #.

When low, indicates that the MODEM or data set is ready to
accept data. The CTS# signal is a MODEM status input
whose condition can be tested by reading the MSR register.

127 RI2#

DI VCC

Ring Indicator 2 #.

When low, indicates that a telephone ring signal has been
received by the MODEM. The RI# signal is a MODEM status
input whose condition can be tested by reading the MSR
register.

126 DCD2#

DI VCC

Data Carrier Detect 2 #.

When low, indicates that the MODEM or data set has
detected a carrier. The DCD# signal i s a MODEM status input
whose condition can be tested by reading the MSR register.

Table 5-10. Pin Description of Parallel Port Signals

Pin(s) No. Symbol Attribute Power Description

100 SLCT

DI VCC

Printer Select.

This signal goes high when the line printer has been
selected.

101 PE

DI VCC

Printer Paper End.

This signal is set high by the printer when it runs out of paper.

102 BUSY

DI VCC

Printer Busy.

This signal goes high when the line printer has a local
operation in progress and cannot accept data.

103 ACK#

DI VCC

Printer Acknowledge #.

This signal goes low to indicate that the printer has already
received a character and is ready to accept another one.

104 SLIN#

DIO24 VCC

Printer Select Input #.

When the signal is low, the printer is selected. This signal is
derived from the complement of bit 3 of the printer control
register.

105 INIT#

DIO24 VCC

Printer Initialize #.

When the signal is low, the printer is selected. This signal is
derived from the complement of bit 3 of the printer control
register.

106 ERR#

DI VCC

Printer Error #.

When the signal is low, it indicates that the printer has
encountered an error. The error message can be read from
bit 3 of the printer status register.

107 AFD#

DIO24 VCC

Printer Auto Line Feed #.

When the signal is low, it is derived from the complement of
bit 1 of the printer control register and is used to advance one
line after each line is printed.

108 STB#

DI VCC

Printer Strobe #.
When the signal is low, it is the complement of bit 0 of the
printer control register and is used to strobe the printing data
into the printer.

109 – 116 PD[0:7]

DIO24 VCC

Parallel Port Data [0:7].

This bus provides a byte-wide input or output to the system.
The eight lines are held in a high impedance state when the
port is deselected.

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Pin Descriptions

Table 5-11. Pin Description of Floppy Disk Controller Signals

Pin(s) No. Symbol Attribute Power Description

51 DENSEL#

52 MTRA#

53 MTRB#/THR

MO#

DO40 VCC

DO40 VCC
DO40 VCC

FDD Density Select #.
DENSEL# is high for high data rates (500 Kbps, 1 Mbps).
DENSEL# is low for low data rates (250 Kbps, 300 Kbps).
FDD Motor A Enable #.
This signal is active low.
FDD Motor B Enable # / Thermal Output #.

• The first function of this pin is FDD Motor B #. This
signal is active low.

• The second function of this pin is Thermal Output #.

• The function configuration of this pin is determined by

programming the software configuration registers.

54 DRVA#

55 DRVB#

56 WDATA#

57 DIR#

58 STEP#

59 HDSEL#

60 WGATE#

61 RDATA#

62 TRK0#

63 INDEX#

64 WPT#

65 DSKCHG#

DO40 VCC
DO40 VCC
DO40 VCC
DO40 VCC

DO40 VCC
DO40 VCC
DO40 VCC

DI VCC
DI VCC

DI VCC

DI VCC

DI VCC

FDD Drive A Enable #.
This signal is active low.
FDD Drive B Enable #.
This signal is active low.
FDD Write Serial Data to the Drive #.
This signal is active low.
FDD Head Direction #.
Step in when this signal is low and step out when high during
a SEEK operation.
FDD Step Pulse #.
This signal is active low.
FDD Head Select #.
This signal is active low.
FDD Write Gage Enable #.
This signal is active low.
FDD Read Disk Data #.
This signal is active low. It is serial data input from FDD.
FDD Track 0 #.
This signal is active low. It indicates that the head of the
selected drive is on track 0.
FDD Index #.
This signal is active low. It indicates the beginning of a disk
track.
FDD Write Protect #.
This signal is active low. It indicates that the disk of the
selected drive is write-protected.
FDD Disk Change #.
This signal is active low. It senses whether the drive door has
been opened or a diskette has been changed.

Table 5-12. Pin Description of Smart Card Reader Interface Signals

Pin(s) No. Symbol Attribute Power Description

31 PCIRST1#/

SCRRST/

GP14

DOD8

DOD8/
DIOD8

Note2

/

VCC

PCI Reset 1 # / Smart Card Reset / General Purpose I/O

13.

• The first function of this pin is PCI Reset 1 #. It is a
buffer of LRESET#.

• The second function of this pin is Smart Card Reset.

• The third function of this pin is the General Purpose

I/O Port 1 Bit 4.

• The function configuration of this pin is determined by
programming the software configuration registers.

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17

IT8712F

Pin(s) No. Symbol Attribute Power Description

32 PWROK1/

SCRPFET#/

GP13

DOD8/
DOD8/
DIOD8

VCC

Power OK 1 of VCC / Smart Card Power FET Control
Output # / General Purpose I/O 13.

• The first function of this pin is Power OK 1 of VCC.

• The second function of this pin is Smart Card Power

FET Control Output #. The Smart Card Reader
interface requires this pin to drive an external Power
FET to supply the current for the Smart Card.

• The third function of this pin is the General Purpose
I/O Port 1 Bit 3.

• The function configuration of this pin is determined by
programming the software configuration registers.

PCI Reset 2 # / Smart Card Serial Data I/O / General
Purpose I/O 12.

• The first function of this pin is PCI Reset 2 #. It is a

33 PCIRST2#/

SCRIO /

GP12

DOD8

DIOD8/

DIOD8

Note2

/

VCC

buffer of LRESET#.

• The second function of this pin is Smart Card Serial
Data I/O.

• The third function of this pin is the General Purpose
I/O Port 1 Bit 2.

• The function configuration of this pin is determined by
programming the software configuration registers.

PCI Reset 3 # / Smart Card Clock / General Purpose I/O

11.

• The first function of this pin is PCI Reset 3 #. It is a

34 PCIRST3#/

SCRCLK /

GP11

DOD8

DOD8/
DIOD8

Note2

/

VCC

buffer of LRESET#. It is a buffer output of LRESET#
if bit1 of Index 2Ch is 0. It will be (LRESET# AND
PCIRSTIN#) if bit1 of Index 2Ch is 1.

• The second function of this pin is Smart Card Clock.
Three different card clocks are selectable from this
pin: high speed (7.1 MHz), low speed (Default: 3.5
MHz) and a programmable card clock.

• The third function of this pin is the General Purpose
I/O Port 1 Bit 1.

• The function configuration of this pin is determined by
programming the software configuration registers.

Table5-12. Pin Description of Smart Card Reader Interface Signals[cont’d]

Pin(s) No. Symbol Attribute Power Description

84 PCIRST4#/

SCRPSNT#/

GP10

DOD8

DI/

DIOD8

Note2

/

VCCH

PCI Reset 4 # / Smart Card Present Detect # / General
Purpose I/O 10.

• The first function of this pin is PCI Reset 4 #. It is a
buffer of LRESET#.

• The second function of this pin is Smart Card
Present Detect #. This pin provides the Smart Card
insertion detection for the Smart Card Reader
interface. Upon detecting the insertion of the Smart
Card, this pin will trigger the power-on event.

• The third function of this pin is the General Purpose
I/O Port 1 Bit 0.

• The function configuration of this pin is determined by
programming the software configuration registers.

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Pin Descriptions

Table 5-13. Pin Description of Keyboard Controller Signals

Pin(s) No. Symbol Attribute Power Description

80 KDAT
81 KCLK
82 MDAT
83 MCLK
45 KRST#
46 GA20

DIOD24 VCCH
DIOD24 VCCH
DIOD24 VCCH
DIOD24 VCCH

DO16 VCC
DO16 VCC

Keyboard Data.
Keyboard Clock.
PS/2 Mouse Data.
PS/2 Mouse Clock.
Keyboard Reset #.
Gate Address 20.

Table 5-14. Pin Description of Miscellaneous Signals

Pin(s) No. Symbol Attribute Power Description

49 CLKIN
72 PWRON#/

GP44

DI VCC

DOD8/
DIOD8

VCCH

24 or 48 MHz Clock Input.
Power On Request Output # / General Purpose I/O 34.

• The first function of this pin is Power On Request
Output #.

• The second function of this pin is the General
Purpose I/O Port 4 Bit 4.

• The function configuration of this pin is determined by
programming the software configuration registers.

75 PANSWH#/

GP43

DI/

DIOD8

VCCH

Main Power Switch Button Input # / General Purpose I/O

43.

• The first function of this pin is Main Power Switch
Button Input #.

• The second function of this pin is the General
Purpose I/O Port 4 Bit 3.

• The function configuration of this pin is determined by
programming the software configuration registers.

76 PSON#/

GP42

DOD8/
DIOD8

VCCH

Power Supply On-Off Output # / General Purpose I/O 42.

• The first function of this pin is Power Supply On-Off
Control Output #.

• The second function of this pin is the General
Purpose I/O Port 4 Bit 2.

• The function configuration of this pin is determined by
programming the software configuration registers.

71 PSIN/

GP45

DI/

DIOD8

VCCH

PSIN Input / General Purpose I/O 45.

• The first function of this pin is PSIN Input.

• The second function of this pin is the General

Purpose I/O Port 4 Bit 5.

• The function configuration of this pin is determined by
programming the software configuration registers.

77 GP53

DIOD8 VCCH

General Purpose I/O 53.

• The first function of this pin is the General Purpose
I/O Port 5 Bit 3.

• The function configuration of this pin is determined by
programming the software configuration registers.

78 PWROK2/

GP41

DOD8/
DIOD8

VCCH

Power OK 2 of VCC / General Purpose I/O 41.

• The first function of this pin is Power OK 2 of VCC.

• The second function of this pin is the General

Purpose I/O Port 4 Bit 1.

• The function configuration of this pin is determined by
programming the software configuration registers.

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IT8712F

Pin(s) No. Symbol Attribute Power Description

79 GP40

DIOD8 VCCH

General Purpose I/O 40.

• The first function of this pin is the General Purpose
I/O Port 4 Bit 0.

• The function configuration of this pin is determined by
programming the software configuration registers.

Note 1: In addition to providing a highly integrated chip, ITE has also implem ented a “SmartGuardian Utility”
for hardware monitor application, providing a total s olution for cus tomer s. The “ SmartG uardian Utility” and the
application circuit of hardware m onitor f unc tion ( the f unc tion arr angement of VIN0-7, T M PIN1-3, F AN_T AC1-3
and FAN_CTL1-3) are interdependent. That is to say, the “ SmartGuardian Utility” is programm ed acc or ding to
the application circuit of hardware monitor function. ITE strongly recommends customers to follow the
referenced application circuit of IT8712F to reduce the “time-to-market” schedule.

Pin No. Symbol Recommended function arrangement

98 VIN0 2 Volt for VCORE1 of CPU
97 VIN1 2 Volt for VCORE2 of CPU
96 VIN2 3.3 Volt for system
95 VIN3 5 Volt for system
94 VIN4 +12 Volt for system
93 VIN5 -12 Volt for system
92 VIN6 -5 Volt for system
91 VIN7 5 Volt for VCCH

Note 2: If the power-on strapping input JP4 is low, the output attributes of these pins will be push-pull.
IO Cell:

DO8: 8mA Digital Output buffer
DOD8: 8mA Digital Open-Drain Output buffer
DO16: 16mA Digital Output buffer
DO24: 24mA Digital Output buffer
DO40: 48mA Digital Output buffer

DIO8: 8mA Digital Input/Output buffer
DIOD8: 8mA Digital Open-Drain Input/Output buffer
DIO16: 16mA Digital Input/Output buffer
DIOD16: 16mA Digital Open-Drain Input/Output buffer
DIO24: 24mA Digital Input/Output buffer
DIOD24: 24mA Digital Open-Drain Input/Output buffer

DI: Digital Input
AI: Analog Input
AO: Analog Output

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List of GPIO Pins

6. List of GPIO Pins

Table 6-1. General Purpose I/O Group 1 (Set 1)

Pin(s) No. Symbol Attribute Description

84 PCIRST4#/

SCRPSNT#/

DOD8/

DI/DIOD8

GP10

34 PCIRST3#/

SCRCLK/

GP11

33 PCIRST2#/

SCRIO/GP12

32 PWROK1/

SCRPFET#/

GP13

31 PCIRST1#/

SCRRST/

GP14

30 RESETCON#

/CIRTX/GP15

29 MIDI_IN/

DOD8/
DOD8/
DIOD8

DOD8/DIO

D8/DIOD8

DOD8/
DOD8/
DIOD8

DOD8/
DOD8/
DIOD8

DI/DOD8/

DIOD8

DI/DIOD8

GP16

28 MIDI_OUT/

GP17

DO8/

DIOD8

Table 6-2. General Purpose I/O Group 2 (Set 2)

Pin(s) No. Symbol Attribute Description

27 JSACX/

GP20

26 JSACY/

GP21

25 JSAB1/

DIOD8/

DIOD8

DIOD8/

DIOD8

DI/DIOD8

GP22

24 JSAB2/

DI/DIOD8

GP23

23 FAN_TAC5/

JSBCX/

GP24

22 FAN_TAC4/

JSBCY/

GP25

21 FAN_CTL5/

JSBB1/

GP26

20 FAN_CTL4/

JSBB2/

GP27

DI/

DIOD8/

DIOD8

DI/

DIOD8/

DIOD8
DOD8/

DI/

DIOD8
DOD8/

DI/

DIOD8

Table 6-3. General Purpose I/O Group 3 (Set 3)

Pin(s) No. Symbol Attribute Description

19 VID0/GP30

DIO8/DIO

D8

18 VID1/GP31

DIO8/DIO

D8

17 VID2/GP32

DIO8/DIO

D8

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PCI Reset 4 # / Smart Card Present Detect # / General Purpose I/O

10.

PCI Reset 3 # / Smart Card Clock / General Purpose I/O 11.

PCI Reset 2 # / Smart Card Serial Data I/O / General Purpose I/O 12.

Power OK 1 of VCC / Smart Card Power FET Control Output # /
General Purpose I/O 13.

PCI Reset 1 # /Smart Card Reset / General Purpose I/O 14.

Reset Connect # /Consumer Infrared Transmit Output / General
Purpose I/O 15.

MIDI Input / General Purpose I/O 16.

MIDI Output / General Purpose I/O 17.

Joystick A Coordinate X / General Purpose I/O 20.

Joystick A Coordinate Y / General Purpose I/O 21.

Joystick A Button 1 / General Purpose I/O 22.

Joystick A Button 2 / General Purpose I/O 23.

Joystick B Coordinate X / General Purpose I/O 24.

Joystick B Coordinate Y / General Purpose I/O 25.

Joystick B Button 1 / General Purpose I/O 26.

Joystick B Button 2 / General Purpose I/O 27.

Voltage ID 0 / General Purpose I/O 30.

Voltage ID 1 / General Purpose I/O 31.
Voltage ID 2 / General Purpose I/O 32.

21

IT8712F

Pin(s) No. Symbol Attribute Description

16 VID3/GP33

DIO8/DIO

Voltage ID 3 / General Purpose I/O 33.

D8

14 VID4/GP34

DIO8/DIO

Voltage ID 4 / General Purpose I/O 34.

D8

13 VID5/GP35

DIO8/DIO

Voltage ID 5 / General Purpose I/O 35.

D8

12 FAN_CTL3/G

P36

11 FAN_TAC3/G

DOD8/
DIOD8

DI/DIOD8

Fan Control Output 3 / General Purpose I/O 36.

Fan Tachometer Input 3 / General Purpose I/O 37.

P37

Table 6-4. General Purpose I/O Group 4 (Set 4)

Pin(s) No. Symbol Attribute Description

79 GP40
78 PWROK2/

GP41

76 PSON#/

GP42

75 PANSWH#/G

DIOD8

DOD8/DIO

D8

DOD8/
DIOD8

DI/DIOD8

General Purpose I/O 40.
Power OK 2 of VCC / General Purpose I/O 41.

Power Supply On-Off Control Output # / General Purpose I/O 42.

Main Power Switch Button Input # / General Purpose I/O 43.

P43

72 PWRON#/

GP44
71 PSIN/GP45
70 IRRX/GP46
66 IRTX/GP47

DOD8/

DIOD8
DI/DIOD8
DI/DIOD8

DO8/

Power On Request Output # / General Purpose I/O 44.

PSIN Input / General Purpose I/O 45.
Infrared Receive Input / General Purpose I/O 46.
Infrared Transmit Output / General Purpose I/O 47.

DIOD8

Table 6-5. General Purpose I/O Group 5 (Set 5)

Pin(s) No. Symbol Attribute Description

48 PCIRST5#/

CLKRUN#/

GP50

10 FAN_CTL2/G

P51

9 FAN_TAC2/G

DO8/
DIOD16/
DIOD16

DOD8/
DIOD8

DI/DIOD8

PCIRST5#/Clock Run # / General Purpose I/O 50.

Fan Control Output 2 / General Purpose I/O 51.

Fan Tachometer Input 2 / General Purpose I/O 52.

P52
77 GP53
73 PME#/GP54

DIOD8
DOD8/

General Purpose I/O 53.
Power Management Event # / General Purpose I/O 54.

DIOD8

85 RSMRST#/

CIRRX /GP55

DOD8/ DI /

DIOD8

Resume Reset # / Consumer Infrared Receive Input / General
Purpose I/O 55.

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L

Power on Strapping Options

7. Power On Strapping Options and Special Pin Routings

Table 7-1. Power On Strapping Options

Symbol Value Description

1 KBC is enabled. JP1 KBCEN
0 KBC is disabled.
1 KBC’s ROM is built in. JP2 KBC_IROM
0 KBC’s ROM is external. This is used f o r c us tom code verification. A spec ial

application circuit is required.

JP3 CHIP_SEL -- Chip selection in Configuration.
JP4 BUF_SEL

1 The output buffers of PCIRST1#, PCIRST2#, PCIRST3#, PCIRST4# and

PCIRST5# are enhanced open-drain. It drives high about 10~20 ns when
the signal transits from low to high, and then Hi-Z.

0 The output buffers are push-pull.

AN_CTL_SE

1 The default value of EC Index 15h/16h/17h is 00h. JP5
0 The default value of EC Index 15h/16h/17h is 40h.
1 The threshold voltage of VID is 2.0/0.8V. JP6 VID_ISEL
0 The threshold voltage of VID is 0.8/0.4V.

Intel

ICH

PWBTN#

SUSB#

VCCH

PWRON#

(72)

System

IT8712F

On-Off

Button

PANSWH#

(75)

Figure 7-1. IT8712F Special Applications Circuitry for Intel ICH

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PSIN

(71)

PSON#(76)

ATX

Power Supply

PSON#

This page is intentionally left blank.

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Configuration

8. Configuration

8.1 Configuring Sequence Description

After the hardware reset or power-on reset, the IT8712F enters the normal mode with all logical devices
disabled except KBC. The initial state (enable bit) of this logical device ( KBC) is deter m ined by the state of pin
121 (DTR1# ) at the falling edge of the system reset during power-on reset.

Hardware Reset

Any other I/O transition cycle

Wait for key string

I/O write to 2Eh

N

Is the data

"87h" ?

Y

Any other I/O transition cycle

Check Pass key

I/O write to 2Eh

N

Next Data?

Y

N

Last Data?

Y

MB PnP Mode

There are three steps to com pleting the configur ation setup: (1) Enter the MB PnP Mode; (2) Modify the data

of configuration register s; (3) Exit the MB PnP Mode. Undesir ed result m ay occur if
the MB PnP Mode is not exited normally.

(1) Enter the MB PnP Mode

To enter the MB PnP Mode, four special I/O write operations are to be performed during Wait for Key state. To

ensure the initial state of the key-check logic, it is necessary to perform four write
operations to the Special Address port (2Eh). Two different enter k eys are provided
to select configuration ports (2Eh/2Fh or 4Eh/4Fh) of the next step.

87h, 01h, 55h, 55h; 2Eh 2Fh

Address port Data port

or 87h, 01h, 55h, AAh; 4Eh 4Fh

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IT8712F

(2) Modify the Data of the Registers

All configuration registers can be accessed after entering the MB PnP Mode. Before accessing a selected

register, the content of Index 07h m ust be c hanged to the LDN to which the r egister
belongs, except some Global registers.

(3) Exit the MB PnP Mode

Set bit 1 of the configure control register (Index=02h) to “1” to exit the MB PnP Mode.

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Configuration

8.2 Description of the Configuration Registers

All the registers except APC/PME’ registers will be reset to the default state when RESET is activated.

Table 8-1. Global Configuration Registers

LDN Index R/W Reset Configuration Register or Action

All 02h W NA Configure Control
All 07h R/W NA Logical Device Number (LDN)
All 20h R 87h Chip ID Byte 1
All 21h R 12h Chip ID Byte 2
All 22h W-R 07h Configuration Select and Chip Version
All 23h R/W 00h Clock Selection Register
All 24h R/W 00h Software Suspend

Note1

07h
07h
07h
07h
07h
07h

25h R/W 01h GPIO Set 1 Multi-Function Pin Selection Register

Note1

26h R/W 00h GPIO Set 2 Multi-Function Pin Selection Register

Note1

27h R/W 00h GPIO Set 3 Multi-Function Pin Selection Register

Note1

28h R/W 40h GPIO Set 4 Multi-Function Pin Selection Register

Note1

29h R/W 00h GPIO Set 5 Multi-Function Pin Selection Register

Note1

2Ah R/W 00h Extended 1 Multi-Function Pin Selection Register

All 2Bh R/W 00h Logical Block Configuration Lock Register

Note1

07h
F4h
F4h

2Ch R/W 00h Extended 2 Multi-Function Pin Selection Register

Note1

2Eh R/W 00h Test 1 Register

Note1

2Fh R/W 00h Test 2 Register

Table 8-2. FDC Configuration Registers

LDN Index R/W Reset Configuration Register or Action

00h 30h R/W 00h FDC Activate
00h 60h R/W 03h FDC Base Address MSB Register
00h 61h R/W F0h FDC Base Address LSB Register
00h 70h R/W 06h FDC Interrupt Level Select
00h 74h R/W 02h FDC DMA Channel Select
00h F0h R/W 00h FDC Special Configuration Register 1
00h F1h R/W 00h FDC Special Configuration Register 2

Table 8-3. Serial Port 1 Configuration Registers

LDN Index R/W Reset Configuration Regis ter or Action

01h 30h R/W 00h Serial Port 1 Activate
01h 60h R/W 03h Serial Port 1 Base Address MSB Register
01h 61h R/W F8h Serial Port 1 Base Address LSB Register
01h 70h R/W 04h Serial Port 1 Interrupt Level Select
01h F0h R/W 00h Serial Port 1 Special Configuration Register 1

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IT8712F

LDN Index R/W Reset Configuration Regis ter or Action

01h F1h R/W 50h Serial Port 1 Special Configuration Register 2
01h F2h R/W 00h Serial Port 1 Special Configuration Register 3
01h F3h R/W 7Fh Serial Port 1 Special Configuration Register 4

Table 8-4. Serial Port 2 Configuration Registers

LDN Index R/W Reset Configuration Register or Action

02h 30h R/W 00h Serial Port 2 Activate
02h 60h R/W 02h Serial Port 2 Base Address MSB Register
02h 61h R/W F8h Serial Port 2 Base Address LSB Register
02h 70h R/W 03h Serial Port 2 Interrupt Level Select
02h F0h R/W 00h Serial Port 2 Special Configuration Register 1
02h F1h R/W 50h Serial Port 2 Special Configuration Register 2
02h F2h R/W 00h Serial Port 2 Special Configuration Register 3
02h F3h R/W 7Fh Serial Port 2 Special Configuration Register 4

Table 8-5. Parallel Port Configuration Registers

LDN Index R/W Reset Configuration Register or Action

03h 30h R/W 00h Parallel Port Activate
03h 60h R/W 03h Parallel Port Primary Base Address MSB Register
03h 61h R/W 78h Parallel Port Primary Base Address LSB Register
03h 62h R/W 07h Parallel Port Secondary Base Address MSB Register
03h 63h R/W 78h Parallel Port Secondary Base Address LSB Register
03h 70h R/W 07h Parallel Port Interrupt Level Select
03h 74h R/W 03h Parallel Port DMA Channel Select
03h F0h R/W 03h

Note3

Parallel Port Special Configuration Register

Note2

Table 8-6. Environment Controller Configuration Registers

LDN Index R/W Reset Configuration Register or Action

04h 30h R/W 00h Environment Controller Activate
04h 60h R/W 02h Environment Controller Base Address MSB Register
04h 61h R/W 90h Environment Controller Base Address LSB Register
04h 62h R/W 02h PME Direct Access Base Address MSB Register
04h 63h R/W 30h PME Direct Access Base Address LSB Register
04h 70h R/W 09h Environment Controller Interrupt Level Select
04h F0h R/W 00h APC/PME Event Enable Register
04h F1h R/W 00h APC/PME Status Register
04h F2h R/W 00h APC/PME Control Register 1

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Configuration

LDN Index R/W Reset Configuration Register or Action

04h F3h R/W 00h Environment Controller Special Configuration Register
04h F4h R-R/W 00h APC/PME Control Register 2
04h F5h R/W - APC/PME Special Code Index Register
04h F6h R/W - APC/PME Special Code Data Register

Table 8-7. KBC(Keyboard) Configuration Registers

LDN Index R/W Reset Configuration Register or Action

05h 30h R/W

Note4

KBC Activate
05h 60h R/W 00h KBC Data Base Address MSB Register
05h 61h R/W 60h KBC Data Base Address LSB Register
05h 62h R/W 00h KBC Command Base Address MSB Register
05h 63h R/W 64h KBC Command Base Address LSB Register
05h 70h R/W 01h KBC Interrupt Level Select
05h 71h R-R/W 02h KBC Interrupt Type

Note5

05h F0h R/W 00h KBC Special Configuration Register

Table 8-8. KBC(Mouse) Configuration Registers

LDN Index R/W Reset Configuration Register or Action

06h 30h R/W 00h KBC (Mouse) Activate
06h 70h R/W 0Ch KBC (Mouse) Interrupt Level Select
06h 71h R-R/W 02h KBC (Mouse) Interrupt Type

Note5

06h F0h R/W 00h KBC (Mouse) Special Configuration Register

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IT8712F

Table 8-9. GPIO Configuration Registers

LDN Index R/W Reset Configuration Register or Action

07h 60h R/W 00h SMI# Normal Run Access Base Address MSB Register
07h 61h R/W 00h SMI# Normal Run Access Base Address LSB Register
07h 62h R/W 00h Simple I/O Base Address MSB Register
07h 63h R/W 00h Simple I/O Base Address LSB Register
07h 64h R/W 00h Panel Button De-bounce Base Address MSB Register
07h 65h R/W 00h Panel Button De-bounce Base Address LSB Register
07h 70h R/W 00h Panel Button De-bounce Interrupt Level Select Register
07h 71h R/W 00h Watch Dog Timer Control Register
07h 72h R/W 00h Watch Dog Timer Configuration Register
07h 73h R/W 00h Watch Dog Timer Time-out Value Register
07h B0h R/W 00h GPIO Set 1 Pin Polarity Register
07h B1h R/W 00h GPIO Set 2 Pin Polarity Register
07h B2h R/W 00h GPIO Set 3 Pin Polarity Register
07h B3h R/W 00h GPIO Set 4 Pin Polarity Register
07h B4h R/W 00h GPIO Set 5 Pin Polarity Register
07h B8h R/W 00h GPIO Set 1 Pin Internal Pull-up Enable Register
07h B9h R/W 00h GPIO Set 2 Pin Internal Pull-up Enable Register
07h BAh R/W 00h GPIO Set 3 Pin Internal Pull-up Enable Register
07h BBh R/W 00h GPIO Set 4 Pin Internal Pull-up Enable Register
07h BCh R/W 00h GPIO Set 5 Pin Internal Pull-up Enable Register
07h C0h R/W 01h Simple I/O Set 1 Enable Register
07h C1h R/W 00h Simple I/O Set 2 Enable Register
07h C2h R/W 00h Simple I/O Set 3 Enable Register
07h C3h R/W 40h Simple I/O Set 4 Enable Register
07h C4h R/W 00h Simple I/O Set 5 Enable Register
07h C8h R/W 01h Simple I/O Set 1 Output Enable Register
07h C9h R/W 00h Simple I/O Set 2 Output Enable Register
07h CAh R/W 00h Simple I/O Set 3 Output Enable Register
07h CBh R/W 40h Simple I/O Set 4 Output Enable Register
07h CCh R/W 00h Simple I/O Set 5 Output Enable Register

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Configuration

Table 8-10. GPIO Configuration Registers

LDN Index R/W Reset Configuration Register or Action

07h D0h R/W 00h Panel Button De-bounce Control Register
07h D1h R/W 00h Panel Button De-bounce Set 1 Enable Register
07h D2h R/W 00h Panel Button De-bounce Set 2 Enable Register
07h D3h R/W 00h Panel Button De-bounce Set 3 Enable Register
07h D4h R/W 00h Panel Button De-bounce Set 4 Enable Register
07h D5h R/W 00h Panel Button De-bounce Set 5 Enable Register
07h E3h R/W 00h IRQ3 External Routing Input Pin Mapping Register
07h E4h R/W 00h IRQ4 External Routing Input Pin Mapping Register
07h E5h R/W 00h IRQ5 External Routing Input Pin Mapping Register
07h E6h R/W 00h IRQ6 External Routing Input Pin Mapping Register
07h E7h R/W 00h IRQ7 External Routing Input Pin Mapping Register
07h E9h R/W 00h IRQ9 External Routing Input Pin Mapping Register
07h EAh R/W 00h IRQ10 External Routing Input Pin Mapping Register
07h EBh R/W 00h IRQ11 External Routing Input Pin Mapping Register
07h ECh R/W 00h IRQ12 External Routing Input Pin Mapping Register
07h EEh R/W 00h IRQ14 External Routing Input Pin Mapping Register
07h EFh R/W 00h IRQ15 External Routing Input Pin Mapping Register
07h F0h R/W 00h SMI# Control Register 1
07h F1h R/W 00h SMI# Control Register 2
07h F2h R/W 00h SMI# Status Register 1
07h F3h R/W 00h SMI# Status Register 2
07h F4h R/W 00h SMI# Pin Mapping Register
07h F5h R/W 00h Hardware Monitor Thermal Output Pin Mapping Register
07h F6h R/W 00h Hardware Monitor Alert Beep Pin Mapping Register
07h F7h R/W 00h Keyboard Lock Pin Mapping Register
07h F8h R/W 00h GP LED Blinking 1 Pin Mapping Register
07h F9h R/W 00h GP LED Blinking 1 Control Register
07h FAh R/W 00h GP LED Blinking 2 Pin Mapping Register
07h FBh R/W 00h GP LED Blinking 2 Control Register
07h FCh R/W-R --h VID Input Register
07h FDh R/W 00h VID Output Register

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IT8712F

Table 8-11. MIDI Port Configuration Registers

LDN Index R/W Reset Configuration Register or Action

08h 30h R/W 00h MIDI Port Activate
08h 60h R/W 03h MIDI Port Base Address MSB Register
08h 61h R/W 00h MIDI Port Base Address LSB Register
08h 70h R/W 0Ah MIDI Port Interrupt Level Select
08h F0h R/W 00h MIDI Port Special Configuration Register

Table 8-12. Game Port Configuration Registers

LDN Index R/W Reset Configuration Register or Action

09h 30h R/W 00h Game Port Activate
09h 60h R/W 02h Game Port Base Address MSB Register
09h 61h R/W 01h Game Port Base Address LSB Register

Table 8-13. Consumer IR Configuration Registers

LDN Index R/W Reset Configuration Register or Action

0Ah 30h R/W 00h Consumer IR Activate
0Ah 60h R/W 03h Consumer IR Base Address MSB Register
0Ah 61h R/W 10h Consumer IR Base Address LSB Register
0Ah 70h R/W 0Bh Consumer IR Interrupt Level Select
0Ah F0h R/W 00h Consumer IR Special Configuration Register

Note 1: All these registers can be read from all LDNs.
Note 2: When the ECP mode is not enabled, this register is read only as “04h”, and cannot be written.
Note 3: When the bit 2 of the Primary Base Address LSB Register of Parallel Port is set to 1, the EPP mode

cannot be enabled. Bit 0 of this register is always 0.

Note 4: The initial value of the activate bit of KBC is determined by the latched state of DTR1# at the rising

edge of the LRESET# signal.

Note 5: These registers are read only unless the write enable bit (Index=F0h) is asserted.

8.2.1 Logical Device Base Address

The base I/O range of logical devic es shown below is located in the base I/O address range of each logical
device.

Table 8-14. Base Address of Logical Devices

Logical Devices Address Notes

LDN=0 FDC Base + (2 - 5) and + 7
LDN=1 SERIAL PORT 1 Base + (0 -7)
LDN=2 SERIAL PORT 2 Base1 + (0 -7) COM port

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Logical Devices Address Notes

LDN=3
PARALLEL PORT

LDN=4
Environment Controller

Base1 + (0 -3)
Base1 + (0 -7)
Base1 + (0 -3) and Base2 + (0 -3)
Base1 + (0 -7) and Base2 + (0 -3)
Base3
Base1 + (0 -7)
Base2 + (0 -3)

SPP
SPP+EPP
SPP+ECP
SPP+EPP+ECP
POST data port
Environment Controller

PME#
LDN=5 KBC Base1 + Base2 KBC
LDN=8 MIDI port Base + (0 -1)
LDN=9 Game Port Base
LDN=A Consumer IR Base + (0 -7)

Configuration

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8.3 Global Configuration Registers (LDN: All)

8.3.1 Configure Control (Index=02h)

This register is w rite only. Its values are not sticky; that is to say, a hardware res et will automatically clear the
bits, and does not require the software to clear them.

Bit Description

7-2

Reserved

1 Returns to the “Wait for Key” state. This bit is used when the configuration sequence is completed.
0 Resets all logical devices and restores configuration registers to their power-on states.

8.3.2 Logical Device Number (LDN, Index=07h)

This register is us ed to s elec t the c urr ent logic al devic es . By reading from or writing to the conf iguration of I/O ,
Interrupt, DMA and other special functions, all registers of the logical devic es can be accessed. In addition,
ACTIVATE command is only effective for the selected logical devices. This register is read/write.

8.3.3 Chip ID Byte 1 (Index=20h, Default=87h)
This register is the Chip ID Byte 1 and is read only. Bits [7:0]=87h when read.

8.3.4 Chip ID Byte 2 (Index=21h, Default=12h)
This register is the Chip ID Byte 2 and is read only. Bits [7:0]=12h when read.

8.3.5 Configuration Select and Chip Version (Index=22h, Default=07h)

Bit Description

7

Configuration Select

This bit is used to select the chip, which needs to be configured. When there are two IT8712F
chips in a system, and a “1” is written, this bit will select JP3=1 (power-on strapping value of
SOUT1) to be configured. The chip with JP3=0 will exit the configuration mode. To write “0”, the
chip with JP3=0 will be configured and the chip with JP3=0 will exit. If no write operations occur on
this register, both chips will be configured.

6-4
3-0

Reserved
Version

4h = Version D
5h = Version G
6h = Version H
7h = Version I
See Application Note that shows how to built a single design which accepts any versions of this
chip.

8.3.6 Clock Selection Register (Index=23h, Default=00h)

Bit Description

7-6

XLOCK select

These two bits determine XLOCK function.
00: Software XLOCK (default)
01: Reserved
10: Pin 48 (GP50)

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Configuration

Bit Description

11: Pin 11 (GP37)

5
4

Reserved
Clock Source Select of Watch Dog Timer

0: Internal oscillating clock (default)
1: External CLKIN

3 Selects the delay of PWROK1/2.

0: POWOK1/2 will be delayed 300 ~600ms from VCC5V > 4.0V.
1: POWOK1/2 will be delayed 150 ~300ms from VCC5V > 4.0V.

2-1

0

Reserved
CLKIN Frequency

0: 48 MHz.
1: 24 MHz.

8.3.7 Software Suspend (Index=24h, Default=00h, MB PnP)

This register is the Software Suspend register. When the bit 0 is set, the IT8712F enters the “Software
Suspend” state. All the devices, except KBC, remain inactive until this bit is cleared or when the wake-up
event occurs. The wake-up event occurs at any transition on signals RI1# (pin 119) and Rl2# (pin 127).

8.3.8 GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=01h)

If the enabled bits are not set, the multi-function pins will perform the original functions . On the other hand, if
they are set, they will perform the GPIO functions. This r egister can be read from any LDN, but can only be
written if LDN=07h.

Bit Description

7

Function Selection of pin 28

0: MIDI Output (MIDI_OUT)
1: General Purpose I/O 17 (GP17)

6

Function Selection of pin 29

0: MIDI Input (MIDI_IN)
1: General Purpose I/O 16 (GP16)

5

Function Selection of pin 30, if bit5 of index 2A is 1.

0: Consumer Infrared Transmit Output (CIRTX)
1: General Purpose I/O 15 (GP15)

4

Function Selection of pin 31, if bit4 of index 2A is 1.

0: Smart Card Reset (SCRRST)
1: General Purpose I/O 14 (GP14)

3

Function Selection of pin 32, if bit3 of index 2A is 1.

0: Smart Card Power FET Control Output #
1: General Purpose I/O 13 (GP13)

2

Function Selection of pin 33, if bit2 of index 2A is 1.

0: Smart Card Serial Data I/O (SCRIO)
1: General Purpose I/O 12 (GP12)

1

Function Selection of pin 34, if bit1 of index 2A is 1.

0: Smart Card Clock (SCRCLK)
1: General Purpose I/O 11 (GP11)

0

Function Selection of pin 84, if bit0 of index 2A is 1.

0: Smart Card Present Detect# (SCRPSNT#)
1: General Purpose I/O 10 (GP10)

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IT8712F

8.3.9 GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h)

If the enabled bits are not set, the multi-function pins will perform the original functions . On the other hand, if
they are set, they will perform the GPIO functions. This r egister can be read from any LDN, but can only be
written if LDN=07h.

Bit Description

7

Function Selection of pin 20

0: Joystick B Button 2 (JSBB2)
1: General Purpose I/O 27 (GP27)

6

Function Selection of pin 21

0: Joystick B Button 1 (JSBB1)
1: General Purpose I/O 26 (GP26)

5

Function Selection of pin 22

0: Joystick B Coordinate Y (JSBCY)
1: General Purpose I/O 25 (GP25)

4

Function Selection of pin 23

0: Joystick B Coordinate X (JSBCX)
1: General Purpose I/O 24 (GP24)

3

Function Selection of pin 24

0: Joystick A Button 2 (JSAB2)
1: General Purpose I/O 23 (GP23)

2

Function Selection of pin 25

0: Joystick A Button 1 (JSAB1)
1: General Purpose I/O 22 (GP22)

1

Function Selection of pin 26

0: Joystick A Coordinate Y (JSACY)
1: General Purpose I/O 21 (GP21)

0

Function Selection of pin 27

0: Joystick A Coordinate X (JSACX)
1: General Purpose I/O 20 (GP20)

8.3.10 GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h)

If the enabled bits are not set, the multi-function pins will perform the original functions . On the other hand, if
they are set, they will perform the GPIO functions. This r egister can be read from any LDN, but can only be
written if LDN=07h.

Bit Description

7

Function Selection of pin 11

0: Fan Tachometer Input 3 (FAN_TAC3)
1: General Purpose I/O 37 (GP37)

6

Function Selection of pin 12

0: Fan Control Output 3 (FAN_CTL3)
1: General Purpose I/O 36 (GP36)

5

Function Selection of pin 13

0: Voltage ID5 (VID5)
1: General Purpose I/O 35 (GP35)

4

Function Selection of pin 14

0: Voltage ID4 (VID4)
1: General Purpose I/O 34 (GP34)

3

Function Selection of pin 16

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Configuration

Bit Description

0: Voltage ID3 (VID3)
1: General Purpose I/O 33 (GP33)

2

Function Selection of pin 17

0: Voltage ID2 (VID2)
1: General Purpose I/O 32 (GP32)

1

Function Selection of pin 18

0: Voltage ID1 (VID1)
1: General Purpose I/O 31 (GP31)

0

Function Selection of pin 19

0: Voltage ID0 (VID0)
1: General Purpose I/O 30 (GP30)

8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=40h)

If the enabled bits are not set, the multi-function pins will perform the original functions . On the other hand, if
they are set, they will perform the GPIO functions. This r egister can be read from any LDN, but can only be
written if LDN=07h.

Bit Description

7

Function Selection of pin 66

0: Infrared Transmit Output (IRTX).
1: General Purpose I/O 47 (GP47).

6

Function Selection of pin 70

0: Infrared Receive Input (IRRX).
1: General Purpose I/O 46 (GP46).

5

Function Selection of pin 71

0: PSIN (SUSB#)
1: General Purpose I/O 45 (GP45).

4

Function Selection of pin 72

0: Power On Request Output # (PWRON#).
1: General Purpose I/O 44 (GP44).

3

Function Selection of pin 75

0: Main Power Switch Button Input # (PANSWH#).
1: General Purpose I/O 43 (GP43).

2

Function Selection of pin 76

0: Power Supply ON-Off Control Output # (PSON#).
1: General Purpose I/O 42 (GP42).

1

Function Selection of pin 78

0: PWROK2.
1: General Purpose I/O 41 (GP41).

0

Function Selection of pin 79

0: Reserved.
1: General Purpose I/O 40 (GP40).

8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h)

If the enabled bits are not set, the multi-function pins will perform the original functions . On the other hand, if
they are set, they will perform the GPIO functions. This r egister can be read from any LDN, but can only be
written if LDN=07h.

Bit Description

7

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Reserved

37

IT8712F

Bit Description

6

Reserved
Function Selection of pin 85.

5

0: Consumer Infrared Receive Input (CIRRX) or RSMRST#. RSMRST# is an open-drain output
function, which is active low about 16ms when VCCH5V is power-on.
1: General Purpose I/O 55 (GP55).

Function Selection of pin 73.

4

0: Power Management Event # (PME#).
1: General Purpose I/O 54 (GP54).

Function Selection of pin 77.

3

0: Reserved.
1: General Purpose I/O 53 (GP53).

Function Selection of pin 9.

2

0: Fan Tachometer Input 2 (FAN_TAC2).
1: General Purpose I/O 52 (GP52).

Function Selection of pin 10.

1

0: Fan Control Output 2 (FAN_CTL2).
1: General Purpose I/O 51 (GP51).

Function Selection of pin 48.

0

0: Clock Run # (CLKRUN#) or PCIRST5#, selected by bit2 of index 2C.
1: General Purpose I/O 50 (GP50).

8.3.13 Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h)

This register can be read from any LDN, but can only be written if LDN=07h.

Bit Description

7
6

Reserved.
Multi-function selection of pin 53.

0: MTRB#.
1: Thermal Output #.

5

Extended multi-function selection of 30.

0: RESETCON#.
1: Determined by bit5 of GPIO Set 1 Multi-function Selection Register (Index 25h).

4

Extended multi-function selection of pin 31.

0: PCIRST1#.
1: Determined by bit4 of GPIO Set 1 Multi-function Selection Register (Index 25h).

3

Extended multi-function selection of pin 32.

0: PWROK1.
1: Determined by bit3 of GPIO Set 1 Multi-function Selection Register (Index 25h).

2

Extended multi-function selection of pin 33.

0: PCIRST2#.
1: Determined by bit2 of GPIO Set 1 Multi-function Selection Register (Index 25h).

1

Extended multi-function selection of pin 34.

0: PCIRST3#.
1: Determined by bit1 of GPIO Set 1 Multi-function Selection Register (Index 25h).

0

Extended multi-function selection of pin 84.

0: PCIRST4#.
1: Determined by bit0 of GPIO Set 1 Multi-function Selection Register (Index 25h).

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Configuration

8.3.14 Logical Block Lock Register (Index=2Bh, Default=00h)

When loc k f unction is enabled (bit7=1 or X LOCK# is low), conf iguration registers of the selected logical block
and Clock Selection register (index = 23h), and this register will be read-only.

Bit Description

7

Software Lock Enable. Once this bit is set to 1 by software, it can be only cleared by
hardware reset.

0: Configuration lock is controlled by XLOCK#. (Default)
1: Configuration registers Logic Blocks selected by bits 6-0 and this register is read-only.

6

GPIO Select. (LDN7)

0: GPIO Configuration registers are programmable.
1: GPIO Configuration registers are read-only if LOCK is enabled.

5

KBC (Keyboard) and KBC (Mouse) Select. (LDN5 and LDN6)

0: KBC (Keyboard) and KBC (Mouse) Configuration registers are programmable.
1: KBC (Keyboard) and KBC (Mouse) Configuration registers are read-only if LOCK is enabled.

4

EC Select. (LDN4)

0: EC Configuration registers are programmable.
1: EC Configuration registers are read-only if LOCK is enabled.

3

Parallel Port Select. (LDN3)

0: Parallel Port Configuration registers are programmable.
1: Parallel Port Configuration registers are read-only if LOCK is enabled.

2

Serial Port 2 Select. (LDN2)

0: Serial Port 2 Configuration registers are programmable.
1: Serial Port 2 Configuration registers are read-only if LOCK is enabled.

1

Serial Port 1 Select. (LDN1)

0: Serial Port 1 Configuration registers are programmable.
1: Serial Port 1 Configuration registers are read-only if LOCK is enabled.

0

FDC Select. (LDN0) The lock function will not affect bit0 of FDC Special Configuration
register (software write protect).

0: FDC Configuration registers are programmable.
1: FDC Configuration registers are read-only (except Software Write Protect bit) if LOCK is
enabled.

8.3.15 Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=1Fh)

This register can be read from any LDN, but can only be written if LDN=07h.

Bit Description

7-5

4

Reserved
Extended multi-function selection of pin 21, 23.

0: Disable FAN_CTL/FAN_TAC set 5.
1: Enable FAN_CTL/FAN_TAC set 5. (Game port should disable.)

3

Extended multi-function selection of pin 20, 22.

0: Disable FAN_CTL/FAN_TAC set 4.
1: Enable FAN_CTL/FAN_TAC set 4. (Game port should disable.)

2

Extended multi-function selection of pin 48 if bit0 of Index 29h is 0.

0: Clock Run # (CLKRUN#).
1: PCIRST5#.

1

Enables PCIRSTIN# (pin 91), and switches VIN7 function to internal voltage divider for
VCCH5V.

0: Disable.

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IT8712F

Bit Description

1: Enable.

0

Enables ATXPG (pin 95), and switches VIN3 function to internal voltage divider for VCC5V.

0: Disable.
1: Enable.

8.3.16 Test 1 Register (Index=2Eh, Default=00h)

This register is the Test 1 Register and is reserved for ITE. It should not be set.

8.3.17 Test 2 Register (Index=2Fh, Default=00h)

This register is the Test 2 Register and is reserved for ITE. It should not be set.

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8.4 FDC Configuration Registers (LDN=00h)

8.4.1 FDC Activate (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved
FDC Enable

1: Enabled.
0: Disabled.

8.4.2 FDC Base Address MSB Register (Index=60h, Default=03h)

Bit Description

7-4

Read only, with “0h” for Base Address [15:12].

3-0 Mapped as Base Address [11:8].

8.4.3 FDC Base Address LSB Register (Index=61h, Default=F0h)

Bit Description

7-3
2-0

Read/write, mapped as Base Address [7:3].
Read only as “000b.”

8.4.4 FDC Interrupt Level Select (Index=70h, Default=06h)

Bit Description

7-4
3-0 Select the interrupt level

Reserved with default “0h.”

Note1

for FDC.

8.4.5 FDC DMA Channel Select (Index=74h, Default=02h)

Bit Description

7-3
2-0 Select the DMA channel

Reserved with default “00h.”

Note2

for FDC.

8.4.6 FDC Special Configuration Register 1 (Index=F0h, Default=00h)

Bit Description

7-4

Reserved with default “00h.”

3 1: IRQ sharing.

0: Normal IRQ.

2 1: Swap Floppy Drives A, B.

0: Normal.

1 1: 3-mode.

0: AT-mode.

0 1: Software Write Protect.

0: Normal.

Configuration

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IT8712F

8.4.7 FDC Special Configuration Register 2 (Index=F1h, Default=00h)

Bit Description

7-4

Reserved with default “00h.”
3-2 FDD B Data Rate Table Select (DRT1-0).
1-0 FDD A Data Rate Table Select (DRT1-0).

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8.5 Serial Port 1 Configuration Registers (LDN=01h)

8.5.1 Serial Port 1 Activate (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved

Serial Port 1 Enable

1: Enabled.

0: Disabled.

8.5.2 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address[15:12].

Read/write, mapped as Base Address[11:8].

8.5.3 Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h)

Bit Description

7-3
2-0

Read/write, mapped as Base Address[7:3].

Read only as “000b.”

8.5.4 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h)

Bit Description

7-4
3-0 Select the interrupt level

Reserved with default “0h.”

Note1

for Serial Port 1.

8.5.5 Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h)

Bit Description

7

6-4

Reserved

Serial Port 1 Mode

Note3

000: Standard (default)

001: IrDA 1.0 (HP SIR)

010 : ASKIR

100 : Smart Card Reader (SCR)

else : Reserved

3

2-1

Reserved with default “0.”

Clock Source.

00: 24 MHz/13 (Standard)

01: 24 MHz/12 (MIDI)

10: Reserved

11: Reserved

0 1: IRQ sharing.

0: Normal.

Configuration

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IT8712F

8.5.6 Serial Port 1 Special Configuration Register 2 (Index=F1h, Default=50h)

Bit Description

7 1: No transmissions delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX

mode.

0: Transmission delays (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode.

6 1: No receptions delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode.

0: Reception delays (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode.
5 Single Mask Mode: When set, the RX of UART is masked under TX transmission.
4 1: Half Duplex (default).

0: Full Duplex.
3

SIR RX polarity

1: Active low

0: Active high

2-0

Reserved

8.5.7 Serial Port 1 Special Configuration Register 3 (Index=F2h, Default=00h)

This register is valid only when Serial Port 1’s Mode is Smart Card Reader.

Bit Description

7-3

2

Reserved
SCRPFET# polarity

1: Active high

0: Active low

1-0

SCR_CLKSEL1-0

00: Stop
01: 3.5 MHz
10: 7.1 MHz
11: Special Divisor (96 MHz/DIV96M)

8.5.8 Serial Port 1 Special Configuration Register 4 (Index=F3h, Default=7Fh)

This register is valid only when Serial Port 1’s Mode is Smart Card Reader.

Bit Description

7

SCRPSNT# Active Phase Control

1: Active high

0: Active low

6-0

SCR DIV96M6-0

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8.6 Serial Port 2 Configuration Registers (LDN=02h)

8.6.1 Serial Port 2 Activate (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved
Serial Port 2 Enable

1: Enabled
0: Disabled

8.6.2 Serial Port 2 Base Address MSB Register (Index=60 h, Default=02h)

Bit Description

7-4
3-0

Read only with “0h” for Base Address [15:12].
Read/write, mapped as Base Address[11:8].

8.6.3 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h)

Bit Description

7-3
2-0

Read/write, mapped as Base Address [7:3].
Read only as “000b.”

8.6.4 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h)

Bit Description

7-4
3-0 Select the interrupt level

Reserved with default “0h.”

Note1

for Serial Port 2.

8.6.5 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h)

Bit Description

7

6-4

Reserved
Serial Port 2 Mode

Note3

000: Standard (default)
001: IrDA 1.0 (HP SIR)
010 : ASKIR
100 : Smart Card Reader (SCR)
else : Reserved

3

2-1

Reserved with default “0.”
Clock Source

00: 24 MHz/13 (Standard)
01: 24 MHz/12 (MIDI)
10: Reserved
11: Reserved

0 1: IRQ sharing

0: Normal

Configuration

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IT8712F

8.6.6 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h)

Bit Description

7 1: No transmission delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode.

0: Transmission delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode.

6 1: No reception delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode.

0: Reception delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode.
5 Single Mask Mode: When set, the RX of UART is masked under TX transmission.
4 1: Half Duplex (default).

0: Full Duplex.
3

SIR RX polarity

1: Active low

0: Active high

2-0

Reserved

8.6.7 Serial Port 2 Special Configuration Register 3 (Index=F2h, Default=00h)

This register is valid only when Serial Port 2’s Mode is Smart Card Reader.

Bit Description

7-3

2

Reserved

SCRPFET# polarity.

1: Active high

0: Active low

1-0

SCR_CLKSEL1-0.

00: Stop

01: 3.5 MHz

10: 7.1 MHz

11: Special Divisor ( 96 MHz/DIV96M)

8.6.8 Serial Port 2 Special Configuration Register 4 (Index=F3h, Default=7Fh)

This register is valid only when Serial Port 2’s Mode is Smart Card Reader.

Bit Description

7

SCRPSNT# Active Phase Control

1: Active high

0: Active low

6-0

SCR DIV96M6-0

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Configuration

8.7 Parallel Port Configuration Registers (LDN=03h)

8.7.1 Parallel Port Activate (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved

Parallel Port Enable

1: Enabled

0: Disabled

8.7.2 Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address[15:12]

Read/write, mapped as Base Address[11:8]

8.7.3 Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h)

If the bit 2 is set to 1, the EPP mode is disabled automatically.

Bit Description

7-2
1-0

Read/write, mapped as Base Address[7:2]

Read only as “00b.”

8.7.4 Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address[15:12]

Read/write, mapped as Base Address[11:8]

8.7.5 Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h)

Bit Description

7-2
1-0

Read/write, mapped as Base Address[7:2]

Read only as “00b.”

8.7.6 Parallel Port Interrupt Level Select (Index =70h, Default=07h)

Bit Description

7-4
3-0

Reserved with default “0h.”

Select the interrupt level

Note1

for Parallel Port

8.7.7 Parallel Port DMA Channel Select (Index=74h, Default=03h)

Bit Description

7-3
2-0

Reserved with default “00h.”

Select the DMA channel

Note2

for Parallel Port.

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8.7.8 Parallel Port Special Configuration Register (Index=F0h, Default=03h)

Bit Description

7-4

Reserved

3 1: POST Data Port Disable

0: POST Data Port Enable
2 1: IRQ sharing

0: Normal

1-0

Parallel Port Modes

00 : Standard Parallel Port mode (SPP)

01 : EPP mode

10 : ECP mode

11 : EPP mode & ECP mode

If the bit 1 is set, ECP mode is enabled. If the bit 0 is set, EPP mode is enabled. These two bits are
independent. However, according to the EPP spec., when Parallel Port Primary Base Address LSB
Register bit 2 is set to 1, the EPP mode cannot be enabled.

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Configuration

8.8 Environment Controller Configuration Registers (LDN=04h)

8.8.1 Environment Controller Activate Register (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved

Environment Controller Enable.

1: Enabled

0: Disabled

This is a read/write register.

8.8.2 Environment Controller Base Address MSB Register (Index=60h, Default=02h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address[15:12].

Read/write, mapped as Base Address[11:8].

8.8.3 Environment Controller Base Address LSB Register (Index=61h, Default=90h)

Bit Description

7-3
2-0

Read/write, mapped as Base Address[7:3].

Read only as “000b.”

8.8.4 PME Direct Access Base Address MSB Register (Index=62h, Default=02h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address[15:12]

Read/write, mapped as Base Address[11:8]

8.8.5 PME Direct Access Base Address LSB Register (Index=63h, Default=30h)

Bit Description

7-3
2-0

Read/write, mapped as Base Address[7:3]

Read only as “000b.”

8.8.6 Environment Controller Interrupt Level Select (Index=70h, Default=09h)

Bit Description

7-4
3-0

Reserved with default “0h.”

Select the interrupt level

Note1

for Environment Controller

8.8.7 APC/PME Event Enable Register (PER) (Index=F0h, Default=00h)

Bit Description

7 It is set to 1 when VCCH is off. Write 1 to clear this bit. This bit is ineffective if a 0 is written to this

bit.
6 0: Smart Card Reader card detect event disabled.

1: Smart Card Reader card detect event enabled.
5

Reserved with default “0h.”

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Bit Description

4 0: PS/2 Mouse event disabled.

1: PS/2 Mouse event enabled.
3 0: Keyboard event disabled.

1: Keyboard event enabled.
2 0: RI2# event disabled.

1: RI2# event enabled.
1 0: RI1# event disabled.

1: RI1# event enabled.
0 0:CIR event disabled.

1:CIR event enabled.

8.8.8 APC/PME Status Register (PSR) (Index=F1h, Default=00h)

Bit Description

7 It is set to 1 when VCC is ON at previous AC power failure and 0 when VCC is OFF.
6 0: No Smart Card Reader card detect event Detected.

1: Smart Card Reader card detect event Detected.
5 Reserved
4 0: No PS/2 Mouse Event Detected.

1: PS/2 Mouse Event Detected.
3 0: No Keyboard Event Detected.

1: Keyboard Event Detected.
2 0: No RI2# Event Detected.

1: RI2# Event Detected.
1 0: No RI1# Event Detected.

1: RI1# Event Detected.
0 0: No CIR event Detected.

1: CIR event Detected.

8.8.9 APC/PME Control Register 1 (PCR 1) (Index=F2h, Default=00h)

Bit Description

7 PER and PSR normal run access enable
6

PME# output control

0: Enabled

1: Disabled
5 This bit is restored automatically to the previous VCC state before power failure occurs
4 Disables all APC events after the power failure occurs, excluding PANSWH#
3

Keyboard event mode selection when VCC is ON

1: Determined by PCR 2

0: Pulse falling edge on KCLK
2

Mouse event when VCC is OFF

1: Click Key twice sequentially

0: Pulse falling edge on MCLK
1

Mouse event when VCC is ON

1: Click Key twice sequentially

0: Pulse falling edge on MCLK
0 Reserved

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Configuration

8.8.10 Environment Controller Special Configuration Register (Index=F3h, Default=00h)

Bit Description

7-1

Reserved

0 1: IRQ sharing.

0: Normal.

8.8.11 APC/PME Control Register 2 (PCR 2) (Index=F4h, Default=00h)

Bit Description

7

Disable KCLK/KDAT and MCLK/MDAT auto-swap

0: Enabled.

1: Disabled.
6 Reserved.
5

PSON# state when VCCH is switched from OFF to ON

0: High-Z (default power OFF).

1: Inverting of PSIN.
4 Masks PANSWH# power-on event.

3-2

Key Number of the Keyboard power-up event

00: 5 (Key string mode), 3 (Stroke keys at same time mode)

01: 4 (Key string mode), 2 (Stroke keys at same time mode)

10: 3 (Key string mode), 1 (Stroke keys at same time mode)

11: 2 (Key string mode), Reserved (Stroke keys at same time mode)

1-0

Keyboard power-up event mode selection

00: KCLK falling edge

01: Key string mode

10: Stroke keys at same time mode

11: Reserved

8.8.12 APC/PME Special Code Index Register (Index=F5h)

Bit Description

7-6 Reserved (should be “00”).
5-0 Indicate which Identification Key Code or CIR code register is to be read/written via 0xF6.

8.8.13 APC/PME Special Code Data Register (Index=F6h)

There are 5 bytes for Key String mode, 3 bytes for Stroke Keys at same time mode and CIR event codes.

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8.9 KBC (keyboard) Configuration Registers (LDN=05h)

8.9.1 KBC (keyboard) Activate (Index=30h, Default=01h or 00h)

Bit Description

7-1

0

Reserved

KBC (keyboard) Enable

1: Enabled

0: Disabled

This is a read/write register. The default value depends on the state of the DTR1# when

LRESET# is activated. The default value is 1b for the High state of DTR1# when LRESET# is

activated. It is 0b for the low state of DTR1# when LRESET# is activated.

8.9.2 KBC (keyboard) Data Base Address MSB Register (Index=60h, Default=00h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address [15:12].

Read/write, mapped as Base Address [11:8].

8.9.3 KBC (keyboard) Data Base Address LSB Register (Index=61h, Default=60h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0]

8.9.4 KBC (keyboard) Command Base Address MSB Register (Index=62h, Default=00h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address[15:12]

Read/write, mapped as Base Address[11:8]

8.9.5 KBC (keyboard) Command Base Address LSB Register (Index=63h, Default=64h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0]

8.9.6 KBC (keyboard) Interrupt Level Select (Index=70h, Default=01h)

Bit Description

7-4
3-0

Reserved with default “0h.”

Select the interrupt level

Note1

for KBC (keyboard)

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Configuration

8.9.7 KBC (keyboard) Interrupt Type (Index=71h, Default=02h)

This register indicates the type of interrupt set f or KBC (k eyboard) and is read o nly as “02h” when bit 0 of the
KBC (keyboard) Special Configuration Register is cleared. When bit 0 is set, this type of interrupt can be
selected as level or edge trigger.

Bit Description

7-2

Reserved

1 1: High Level

0: Low Level
0 1: Level Type

0: Edge Type

8.9.8 KBC (keyboard) Special Configuration Register (Index=F0h, Default=00h)

Bit Description

7-5

Reserved
4 1: IRQ sharing.

0: Normal.
3 1: KBC’s clock 8 MHz.

0: KBC’s clock 12 MHz.
2 1: Key lock enabled.

0: Key lock disabled.
1 1: Type of interrupt of KBC (keyboard) can be changed.

0: Type of interrupt of KBC (keyboard) is fixed.
0 1: Enables the External Access ROM of 8042.

0: Internal built-in ROM is used.

8.10 KBC (mouse) Configuration Registers (LDN=06h)

8.10.1 KBC (mouse) Activate (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved

KBC (mouse) Enable

1: Enabled

0: Disabled

8.10.2 KBC (mouse) Interrupt Level Select (Index=70h, Default=0Ch)

Bit Description

7-4
3-0

Reserved with default “0h.”

Select the interrupt level

Note1

for KBC (mouse).

8.10.3 KBC (mouse) Interrupt Type (Index=71h, Default=02h)

This register indicates the type of interrupt used for KBC (mous e) and is read on ly as “02h” when bit 0 of the
KBC (mouse) Special Configuration Register is cleared. When bit 0 is set, the type of interrupt can be selected
as level or edge trigger.

Bit Description

7-2

Reserved

1 1: High Level

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Bit Description

0: Low Level
0 1: Level Type

0: Edge Type

8.10.4 KBC (mouse) Special Configuration Register (Index=F0h, Default=00h)

Bit Description

7-2

Reserved with default “00h.”
1 1: IRQ sharing.

0: Normal.
0 1: Type of interrupt of KBC (mouse) can be changed.

0: Type of interrupt of KBC (mouse) is fixed.

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Configuration

8.11 GPIO Configuration Registers (LDN=07h)

8.11.1 SMI# Normal Run Access Base Address MSB Register (Index=60h, Default=00h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address [15:12].

Read/write, mapped as Base Address [11:8].

8.11.2 SMI# Normal Run Access Base Address LSB Register (Index=61h, Default=00h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0].

8.11.3 Simple I/O Base Address MSB Register (Index=62h, Default=00h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address [15:12].

Read/write, mapped as Base Address [11:8].

8.11.4 Simple I/O Base Address LSB Register (Index=63h, Default=00h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0].

8.11.5 Panel Button De-bounce Base Address MSB Register (Index=64h, Default=00h)

Bit Description

7-4
3-0

Read only as “0h” for Base Address [15:12].

Read/write, mapped as Base Address [11:8].

8.11.6 Panel Button De-bounce Base Address LSB Register (Index=65h, Default=00h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0].

8.11.7 Panel Button De-bounce Interrupt Level Select Register (Index=70h, Default=00h)

Bit Description

7-4
3-0 Select the interrupt level

Reserved

Note1

for Panel Button De-bounce.

8.11.8 Watch Dog Timer Control Register (Index=71h, Default=00h)

Bit Description

7
6
5
4

3-2

1

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WDT is reset upon a CIR interrupt

WDT is reset upon a KBC (mouse) interrupt

WDT is reset upon a KBC (keyboard) interrupt

WDT is reset upon a read or a write to the Game Port base address

Reserved

Force Time-out

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Bit Description

This bit is self-clearing
0

WDT Status

1: WDT value reaches 0.

0: WDT value is not 0.

8.11.9 Watch Dog Timer Configuration Register (Index=72h, Default=00h)

Bit Description

7

WDT Time-out value select 1

1: Second

0: Minute
6

WDT output through KRST (pulse) enable

1: Enable.

0: disable

5 WDT Time-out value Extra select.

1: 64 ms.

0: Determine by WDT Time-out value select 1 (bit 7 of this register).
4 WDT output through PWROK1/PWROK2 (pulse) enable.

1: Enable.

3-0

0: disable

Select the interrupt level

Note1

for WDT

8.11.10 Watch Dog Timer Time-Out Value Register (Index=73h, Default=00h)

Bit Description

7-0

WDT time-out value 7-0

8.11.11 GPIO Pin Set 1, 2, 3, 4 and 5 Polarity Registers (Index=B0h, B1h, B2h, B3h and B4h,
Default=00h)

These registers are used to program the GPIO pin type as polarity inverting or non-inverting.

Bit Description

7-0 1: Inverting

0: Non-inverting

8.11.12 GPIO Pin Set 1, 2, 3, 4 and 5 Pin Internal Pull-up Enable Registers (Index=B8h, B9h, BAh,
BBh and BCh, Default=00h)

These registers are used to enable the GPIO pin internal pull-up.

Bit Description

7-0 1: Enabled.

0: Disabled.

8.11.13 Simple I/O Set 1, 2, 3, 4 and 5 Enable Registers (Index=C0h, C1h, C2h, C3h and C4h,
Default=01h, 00h, 00h, 40h, and 00h)

These registers are used to select the function as the Simple I/O function or the Alternate function.

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Configuration

Bit Description

7-0 1: Simple I/O function

0: Alternate function

8.11.14 Simple I/O Set 1, 2, 3, 4 and 5 Output Enable Registers (Index=C8h, C9h, CAh, CBh and CCh,
Default=01h, 00h, 00h, 40h, and 00h)

These registers are used to determine the direction of the Simple I/O.

Bit Description

7-0 0: Input mode

1: Output mode

8.11.15 Panel Button De-bounce Control Register (Index=D0h, Default=00h)

Bit Description

7-5

4
3
2

Reserved
IRQ Sharing Enable
IRQ Output Type
IRQ Output Enable

1: Enabled

0: Disabled

1-0

De-bounce Time Selection

00: 8 ms (6 ms ignored, 8 ms passed)
01: 16 ms (12 ms ignored, 16 ms passed)
10: 32 ms (24 ms ignored, 32 ms passed)
11: 64 ms (48 ms ignored, 64 ms passed)

8.11.16 Panel Button De-bounce Set 1, 2, 3, 4 and 5 Enable Registers (Index=D1h, D2h, D3h, D4h and
D5h, Default=00h)

These registers are used to enable Panel Button De-bounce for each pin.

Bit Description

7-0 1: Enabled

0: Disabled

8.11.17 IRQ3-7, 9-12 and 14-15 External Routing Input Pin Mapping Registers (Index=E3h-E7h, E9h­ECh and EEh-EFh, Default=00h)

These registers are used to determine the external routing input pin mappings of IRQ3-7, 9-12 and 14-15.

Bit Description

7
6

5-0

Reserved
IRQ Sharing Enable
Input pin Location. Please see Location mapping table

Note4

8.11.18 SMI# Control Register 1 (Index=F0h, Default=00h)

Bit Description

7 Enables the generation of an SMI# due to MIDI’s IRQ (EN_MIDI).
6 Enables the generation of an SMI# due to KBC (Mouse)’s IRQ (EN_MIRQ).
5 Enables the generation of an SMI# due to KBC (Keyboard)’s IRQ (EN_KIRQ).

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Bit Description

4 Enables the generation of an SMI# due to Environment Controller’s IRQ (EN_ECIRQ).
3 Enables the generation of an SMI# due to Parallel Port’s IRQ (EN_PIRQ).
2 Enables the generation of an SMI# due to Serial Port 2’s IRQ (EN_S2IRQ).
1 Enables the generation of an SMI# due to Serial Port 1’s IRQ (EN_S1IRQ).
0 Enables the generation of an SMI# due to FDC’s IRQ (EN_FIRQ).

8.11.19 SMI# Control Register 2 (Index=F1h, Default=00h)

Bit Description

7 Forces to clear all the SMI# status register bits, non-sticky.
6 0: Edge trigger

1: Level trigger.

5-3

Reserved

2 Enables the generation of an SMI# due to WDT’s IRQ (EN_WDT).
1 Enables the generation of an SMI# due to CIR’s IRQ (EN_CIR).
0 Enables the generation of an SMI# due to PBD’s IRQ (EN_PBD).

8.11.20 SMI# Status Register 1 (Index=F2h, Default=00h)

This register is used to read the status of SMI# inputs.

Bit Description

7
6
5
4
3
2
1
0

MIDI’s IRQ
KBC (PS/2 Mouse)’s IRQ
KBC (Keyboard)’s IRQ
Environment Controller’s IRQ
Parallel Port’s IRQ
Serial Port 2’s IRQ
Serial Port 1’s IRQ
FDC’s IRQ

8.11.21 SMI# Status Register 2 (Index=F3h, Default=00h)

This register is used to read the status of SMI# inputs.

Bit Description

7-3

2
1
0

Reserved
WDT’s IRQ
CIR’s IRQ
PBD’s IRQ

8.11.22 SMI# Pin Mapping Register (Index=F4h, Default=00h)

Bit Description

7-6
5-0

Reserved
SMI# Pin Location

Please see Location mapping table

Note4

.

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Configuration

8.11.23 Ha rdware Monitor Thermal Output Pin Mapping Register (Index=F5h, Default=00h)

Bit Description

7-6
5-0

Reserved
Thermal Output Pin Location

Please see Location mapping table

Note4

.

8.11.24 Hardware Monitor Alert Beep Pin Mapping Register (Index=F6h, Default=00h)

Bit Description

7-6
5-0

Reserved
Alert Beep Pin Location

Please see Location mapping table

Note4

.

8.11.25 Ke yboard Lock Pin Mapping Register (Index=F7h, Default=00h)

Bit Description

7-6
5-0

Reserved
Keyboard Lock Pin Location

Please see Location mapping table

Note4

.

8.11.26 GP LED Blinking 1 Pin Mapping Register (Index=F8h, Default=00h)

Bit Description

7-6
5-0

Reserved
GP LED Blinking 1 Location

Please see Location mapping table

Note4

.

8.11.27 GP LED Blinking 1 Control Register (Index=F9h, Default=00h)

Bit Description

7-4

3

2-1

Reserved
GP LED Blinking 1 short low pulse enabled
GP LED 1 Frequency Control.

00: 4 Hz
01: 1 Hz
10: 1/4 Hz
11: 1/8 Hz

0

GP LED Blinking 1 Output low enabled

8.11.28 GP LED Blinking 2 Pin Mapping Register (Index=FAh, Default=00h)

Bit Description

7-6
5-0

Reserved
GP LED Blinking 2 Location

Please see Location mapping table

Note4

.

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8.11.29 GP LED Blinking 2 Control Register (Index=FBh, Default=00h)

Bit Description

7-4

3

2-1

Reserved
GP LED Blinking 2 short low pulse enabled.

GP LED 2 Frequency Control.

00: 4 Hz
01: 1 Hz
10: 1/4 Hz
11: 1/8 Hz

0

GP LED Blinking 2 Output low enabled.

8.11.30 VID Input Register (Index=FCh, Default=--h)

Bit Description

7-6
5-0

Reserved
VID 5-0 inputs

They are read-only. The inputs’ thresholds for VID inputs are not TTL level (0.4V for low, 2.2V for
high), but special CMOS level (1.5V for low, 2.5V for high)

8.11.31 VID Output Register (Index=FDh, Default=00h)

Bit Description

7

VID_OE. VID output enable

1: output
0: input

6

5-0

Reserved
VID 5-0 output values

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8.12 MIDI Port Configuration Registers (LDN=08h)

8.12.1 MIDI Port Activate (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved
MIDI Port Enable

1: Enabled
0: Disabled

8.12.2 MIDI Port Base Address MSB Register (Index=60h, D efault=03h)

Bit Description

7-4
3-0

Read only with “0h” for Base Address[15:12].
Read/write, mapped as Base Address[11:8].

8.12.3 MIDI Port Base Address LSB Register (Index=61h, Default=00h)

Bit Description

7-3
2-0

Read/write, mapped as Base Address[7:3].
Read only as “000b.”

8.12.4 MIDI Port Interrupt Level Select (Index=70h, Default=0Ah)

Bit Description

7-4
3-0

Reserved with default “0h.”
Select the interrupt level

Note1

for MIDI Port.

8.12.5 MIDI Port Special Configuration Register (Index=F0h, Default=00h)

Bit Description

7-1

Reserved with default “00h.”

0 1: IRQ sharing.

0: Normal.

Configuration

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8.13 Game Port Configuration Registers (LDN=09h)

8.13.1 Game Port Activate (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved
Game Port Enable

1: Enabled. (If enable, the multi function pin20, 21,22,23 will change to Game port function.)
0: Disabled.

8.13.2 Game Port Base Address MSB Register (Index=60h, Default=02h)

Bit Description

7-4
3-0

Read only with “0h” for Base Address[15:12].
Read/write, mapped as Base Address[11:8].

8.13.3 Game Port Base Address LSB Register (Index=61h, Default=01h)

Bit Description

7-0

Read/write, mapped as Base Address[7:0].

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Configuration

8.14 Consumer IR Configuration Registers (LDN=0Ah)

8.14.1 Consumer IR Activate (Index=30h, Default=00h)

Bit Description

7-1

0

Reserved
Consumer IR Enable

1: Enabled.
0: Disabled.

8.14.2 Consumer IR Base Address MSB Register (Index=60h, Default=03h)

Bit Description

7-4
3-0

Read only with “0h” for Base Address[15:12].
Read/write, mapped as Base Address[11:8].

8.14.3 Consumer IR Base Address LSB Register (Index=61h, Default=10h)

Bit Description

7-3
2-0

Read/write, mapped as Base Address[7:3].
Read only as “000b.”

8.14.4 Consumer IR Interrupt Level Select (Index=70h, Default=0Bh)

Bit Description

7-4
3-0

Reserved with default “0h.”
Select the interrupt level

Note1

for Consumer IR.

8.14.5 Consumer IR Special Configuration Register (Index=F0h, Default=00h)

Bit Description

7-1

Reserved with default “00h.”

0 1: IRQ sharing.

0: Normal.

Note 1:

Interrupt level mapping
Fh-Dh: not valid
Ch: IRQ12

3h: IRQ3
2h: not valid
1h: IRQ1
0h: no interrupt selected

Note 2:

DMA channel mapping
7h-5h: not valid
4h: no DMA channel selected
3h: DMA3
2h: DMA2
1h: DMA1
0h: DMA0

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Note 3:

Except the standard mode, COM1 and COM2 cannot be selected in the same mode.

Note 4: The Location mapping table

Location Description

001 000 GP10 (pin 84). Powered by VCCH.
001 001 GP11 (pin 34).
001 010 GP12 (pin 33).
001 011 GP13 (pin 32).
001 100 GP14 (pin 31).
001 101 GP15 (pin 30).
001 110 GP16 (pin 29).
001 111 GP17 (pin 28).
010 000 GP20 (pin 27).
010 001 GP21 (pin 26).
010 010 GP22 (pin 25).
010 011 GP23 (pin 24).
010 100 GP24 (pin 23).
010 101 GP25 (pin 22).
010 110 GP26 (pin 21).
010 111 GP27 (pin 20).
011 000 GP30 (pin 19).
011 001 GP31 (pin 18).
011 010 GP32 (pin 17).
011 011 GP33 (pin 16).
011 100 GP34 (pin 14).
011 101 GP35 (pin 13).
011 110 GP36 (pin 12).
011 111 GP37 (pin 11).
100 000 GP40 (pin 79). Powered by VCCH.
100 001 GP41 (pin 78). Powered by VCCH.
100 010 GP42 (pin 76). Powered by VCCH.
100 011 GP43 (pin 75). Powered by VCCH.
100 100 GP44 (pin 72). Powered by VCCH.
100 101 GP45 (pin 71). Powered by VCCH.
100 110 GP46 (pin 70). Powered by VCCH.
100 111 GP47 (pin 66).
101 000 GP50 (pin 48).
101 001 GP51 (pin 10).
101 010 GP52 (pin 9).
101 011 GP53 (pin 77). Powered by VCCH.
101 100 GP54 (pin 73). Powered by VCCH.
101 101 GP55 (pin 85). Powered by VCCH.

else

Reserved

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Functional Description

9. Functional Description

9.1 LPC Interface

The IT8712F supports the peripheral site of the LPC I/F as described in the LPC Interface Specification
Rev.1.0 (Sept. 29, 1997). In addition to the required signals (LAD3-0, LFRAME#, LRESET#, LCLK (LCLK is
the same as PCICLK.)), the IT8712F also supports LDRQ#, SERIRQ and PME#.

9.1.1 LPC Transactions

The IT8712F supports some parts of the cycle types described in the LPC I/F specif ication. Mem ory read and
Memory write cycles are used for the Flash I/F. I/O read and I/O write cycles are used f or the pr ogrammed I/O
cycles. DMA read and DMA write cycles are used for DMA cycles. All of these cycles are c haracteristic of the
single byte transfer.

For LPC host I/O read or write transactions, the Super I/O module processes a positive decoding, and the
LPC interface can respond to the result of the current trans action by sending out SYNC values on LAD[3:0]
signals or leave LAD[3:0] tri-state depending on its result.

For DMA read or write transactions, the LPC interface will make reactions according to the DMA requests
from the DMA devices in the Super I/O modules, and decides whether to ignore the current transaction or not.

The FDC and ECP are 8-bit DMA devices, so if the LPC Host initializes a DMA transaction with data size of
16/32 bits, the LPC interface will process the f irst 8-bit data and r esponse with a SYNC ready (0000b) which
will terminate the DMA burst. The LPC interf ace will then re- issue another LDRQ# m es sage to as sert DREQn
after finishing the current DMA transaction.

9.1.2 LDRQ# Encoding

The Super I/O module provides two DMA devices : the FDC and the ECP. T he LPC Interf ace provides LDRQ#
encoding to reflect the DREQ[3:0] status. Two LDRQ# messages or different DMA channels m ay be issued
back-to-back to trace DMA requests quickly. But, four PCI clocks will be inserted between two LDRQ#
messages of the s am e DMA channel to guarantee that there is at least 10 PCI c lock s for one DMA request to
change its status. (The LPC host will decode these LDRQ# m essages, and send those decoded DREQn to
the legacy DMA controller which runs at 4 MHz or 33/8 MHz).

9.2 Serialized IRQ

The IT8712F follows the specification of Serialized IRQ Support for PCI System, Rev. 6.0, September 1, 1995,
to support the serialized IRQ feature, and is able to interface mos t PC chipsets. The IT8712F encodes the
parallel interrupts to an SERIRQ which will be decoded by the chipset with built-in Interrupt Controller s (two
8259 compatible modules).

9.2.1 Continuous Mode

When in the Continuous mode, the SIRQ host initiates the Start frame of each SERIRQ sequence after
sending out the Stop frame by itself. (The next Start fram e may or may not begin immediately after the turn­around state of current Stop fr ame.) The SERIRQ is always activated and SIRQ host k eeps polling all the
IRQn and system events, even though no IRQn status is c hanged. The SERIRQ enter the Continuous mode
following a system reset.

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9.2.2 Quiet Mode

In the Quiet mode, when one SIRQ Slave detects its input IRQn/events have been changed, it may initiate the
first clock of Start frame. The SIRQ host can then follow to complete the SERIRQ sequence. In the Quiet
mode, the SERIRQ has no activity following the Stop frame until it is initiated by SIRQ Slave, which implies low
activity = low mode power consumption.

9.2.3 Waveform Samples of SERIRQ Sequence

PCICLK

SERIRQ

PCICLK

SERIRQ

Start Frame

S/H H

(4/6/8)T

S: Slave drive H: Host drive R: Recovery T: Turn-around S/H: Slave drive when in Quiet mode, Host drive when in Continuous mode

R

IRQ0 Frame

TSRTSRTSRTSRT

IRQ1 Frame SMI# Frame IRQ3 Frame

IRQ4 Frame

SRT

Figure 9-1. Start Frame Timing

Last Frame Start Frame

Stop Frame

0~n Tclk idle state

S: Slave drive H: Host drive R: Recovery T: Turn-around I: Idle W: Waiting

(Quiet)

RTWS H SRT H RTH1SRT HI

2 Tclk

Last Frame Stop Frame

0~n T, depends on master

(Continuous)

3 Tclk

Figure 9-2. Stop Frame Timing

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9.2.4 SERIRQ Sampling Slot

Slot

Number

IRQn/

Events

#of Clocks

Past Start

1 IRQ0 2 ­2 IRQ1 5 Y
3 SMI# 8 Y
4 IRQ3 11 Y
5 IRQ4 14 Y
6 IRQ5 17 Y
7 IRQ6 20 Y
8 IRQ7 23 Y

9 IRQ8 26 Y
10 IRQ9 29 Y
11 IRQ10 32 Y
12 IRQ11 35 Y
13 IRQ12 38 Y
14 IRQ13 41 ­15 IRQ14 44 Y
16 IRQ15 47 Y
17 IOCHCK# 50 ­18 INTA# 53 ­19 INTB# 56 ­20 INTC# 59 ­21 INTD# 62 -

32:22 Unassigned 95 / 65 -

Functional Description

IT8712F

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9.3 General Purpose I/O

The IT8712F provides five sets of f lexible I/O control and spec ial functions f or the system designers via a s et
of multi-functional General Purpose I/O pins (GPIO). The GPIO functions will not be perform ed unless the
related enable bits of the GPIO Multi-func tion Pin Select ion regis ter s ( Index 25h, 26h, 27h, 28h and 29h of the
Global Configuration Registers) are set. The GPIO functions include the simple I/O function and alternate
function, and the function selection is determined by the Simple I/O Enable Register s (LDN=07h, Index=C0h,
C1h, C2h, C3h and C4h).

The Simple I/O function includes a set of registers, which correspond to the GPIO pins. All control bits ar e
divided into five registers. The accessed I/O ports are program m able and ar e five c onsecutive I/O ports (Bas e
Address+0, Base Address+1, Base Address+2, Base Address+3, Base Address+4). Base Address is
programmed on the registers of GPIO Simple I/O Base Address LSB and MSB registers (LDN=07h,
Index=60h and 61h).

The Alternate Function provides sever al special functions for users , including W atch Dog Tim er, SMI# output
routing, External Interrupt routing, Panel Button De-bounce, Keyboard Lock input routing, LED Blinking,
Thermal output routing, and Beep output routing. The last two are the sub-functions of Hardware Monitor.

The Panel Button De-bounce is an input function. After the panel button de-bounce is enabled, a related
status bit will be set when an active low pulse is detected on the GPIO pin. The status bits will be cleared by
writing 1’s to them. Panel Button De-bounce Interrupt will be issued if any one of the status bit is set. However,
the new setting status will not issue another interrupt unless the previous status bit is cleared before being set.

The Key Lock function locks the keyboard to inhibit the keyboard interface. T he progr amming method is to s et
bit 2 on the register Index F0h of KBC (keyboard) (LDN=5). T he pin loc ation mapping, Index F7h must als o be
programmed correctly.

The Blinking function provides a low frequency blink output. By connecting to some ex ternal components, it
can be used to control a power LED. There are several frequencies that can be selected.

The W atch Dog Timer (WDT ) function is constituted by a time counter, a time-out status register, and the
timer reset control logic. The time-out status bit m ay be mapped to an interrupt or KRST# through the W DT
Configuration register. The W DT has a programmable time-out range from 1 to 255 minutes or 1 to 255
seconds. The units are also pr ogrammable, either a m inute or a second, via bit7 of the W DT Configuration
register. W hen the W DT Time-out Value register is set to a non-zero value, the W DT loads the value and
begin counting down from the value. W hen the value r eaches to 0, the WDT s tatus register will be s et. Ther e
are many system events that can reload the non-zero value into the W DT, which include a CIR interrupt, a
Keyboard Interrupt, a Mouse Interrupt, or I/O reads/writes to the Game Port base address. The effect on the
WDT for each of the events may be enabled or disabled through bits in the W DT control register. No m atter
what value in the time counter is, the host may force a time-out to occur by writing a “1” to the bit 1 of the WDT
Configuration register.

The External Interrupt routing function provides a useful feature for motherboard designers. Through this
function, the parallel interrupts of other on-board devices can be easily re-routed into the Serial IRQ.

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Functional Description

The SMI# is a non-maskable interrupt dedicated to the transparent power management. It consists of dif f er ent
enabled interrupts generated from each of the f unctional blocks in the IT 8712F. The interrupts are r edirected
as the SMI# output via the SMI# Control Register 1 and SMI# Control Register 2. The SMI# Status Registers 1
and 2 are used to read the status of the SMI input events. All the SMI# Status Register bits can be cleared
when the corresponding source events become invalidated. These bits can also be cleared by writing 1 to bit 7
of SMI# Control Register 2, whether the events of the corresponding sources are invalidated or not. The SMI#
events can be programmed as pulse mode or level mode whenever an SMI# event occurs. The logic equation
of the SMI# event is described below:

SMI# event = (EN_FIRQ and FIRQ) or (EN_S1IRQ and S1IRQ) or (EN_S2IRQ and S2IRQ) or (EN_PIRQ and
PIRQ) or (EN_EC and EC_SMI) or (EN_PBDIRQ or PBDIRQ).

Thermal Output

LED Blinking 1
LED Blinking 2

Beep#

SMI#

Simple I/O Register Bit-n

1
2

3
4

5

Simple I/O

enable

Polarity

Pull-up
enable

SD-bus

WR#

D-

TYPE

Output

0
1

enable

1
0

GPIO

PIN

RD_

Interrupt

SD-bus

RD_(IDX=64h, 65h)

status

Panel Button De-bounce Bit-n

De-bounce

enable

De-bounce circuit

External IRQ Routing

(Level 3 - 7, 9 - 11, 14-15)

Keyboard lock

Figure 9-3. General Logic of GPIO Function

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9.4 Advanced Power Supply Control and Power Management Event (PME#)

The circuit for advanc ed power supply control (APC) provides five power-up events, Keyboard, Mouse, CIR,
and Smart Card Reader card detect. When any of these five events is true, PWRON# will per form a low state
until VCC is switched to ON state. The five events include the followings:

1. Detection of KCLK edge or special pattern of KCLK and KDAT. The special pattern of KCLK means

pressing pre-set key string sequentially, and KDAT means pressing pre-set keys simultaneously

2. Detection of MCLK edge or special pattern of MCLK and MDAT. The special pattern of MCLK and MDAT

means clicking on any mouse button twice sequentially.

3. Receiving CIR patterns are matched the previous stored pattern stored at the APC/PME Special Code

Index and Data Register

4. Detection of the Smart Card Reader Card Detect pulse on the SCRPSNT# input pin
The PANSWH# and PSON# are especially designed for the system. PANSW H# serves as a main power

switch input which is wire-AND to the APC output PWRON#. PSON# is the ATX Power c ontrol output, which
is a power-failure gating circuit. T he power-failure gating circuit is res ponsible for gating the PSIN input until
PANSWH# becomes active when the VCCH is switched from OFF to ON.

The power-failure gating circuit c an be disabled by setting the APC/PME Control Register 2 (LDN=04h, index
F4h, bit 5). The gating circuit also provides an auto-restore function. W hen the bit 5 of PCR1 is set, the
previous PSON# state will be restored when the VCCH is switched from OFF to ON.

The Mask PW RON# Activation bit (bit 4 of PCR 1) is used to mas k all Power-up events except Switch on
event when the VCCH state is just switched from FAIL to OFF. In other words, when this bit is set and the
power state is switched from FAIL to OFF, the only validated function is PANSWH#.

The PCR2 register is respons ible for determ ining the Keyboard power up events and APC conditions. Bit 4 is
used to mask the PANSWH# power-on event on the PWRON# pin. T o enable this bit, the k eyboard power-up
event should be enabled and set by (1) pressing pre-set key string sequentially or (2) strok ing pre-set keys
simultaneously. The APC/PME# special code index and data registers are used to specify the special key
codes in the special power-up events of (1) pressing pre-set key string sequentially or (2) stroking pre-set keys
simultaneously.

A CIR event is generated if the input CIR RX pattern is the same as the previous stored pattern stored at PME
Special Code Index and Data Registers (LDN=04h, Index=F5h and F6h). The total maxim um physical codes
are nineteen bytes (from Index 20h to 32h). T he firs t byte (Index 20h) is used to s pecif y the pattern length (in
bytes). Bits[7:4] are used when VCC is on; and Bits[3:0] when VCC goes OFF. The length represented in each
4 bits will be incremented by 3 internally as the actual length to be compared. For m ost of the CIR protocols,
the first several bytes are always the same for each k ey (or pattern). The diff erenc es are always placed in the
last several bytes. Thus, the system designer can program the IT8712F to generate a CIR PME# event as any
keys when VCC is ON and a special key (i.e. POWER-ON) when VCC is OFF.

The Smart Card Reader Card Detec t event is used to power on the system when any Integrated Circuit Card
is inserted in the Smart Card Reader. When inserted, a pulse will be generated on the SCRPSNT# input pin. If
the relative enabled bit is enabled, the power-up event will be also generated.

All APC registers (Index=F0h, F2h, F4h, F 5h and F6h) ar e powered by back-up power (VBAT ) when VCCH is
OFF.
PME# is used to wake up the system from low-power states (S1-S5). Except the five events of the APC’s,
there will be another events to generate PME#: RI1# and RI2# events. RI1# and RI2# are Ring Indicator of
Modem status at ACPI S1 or S2 state. A falling edge on thes e pins issues PME# events if the enable bits ar e
set.

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Functional Description

9.5 Environment Controller

The Environment Controller ( EC), built in the IT8712F, includes eight voltage inputs, thr ee temperature sensor
inputs, three FAN Tachometer inputs, and three sets of advanced FAN Controllers. The EC monitors the
hardware environment and implements environmental control for personal computers.

The IT8712F contains an 8-bit ADC (Analog-to-Digital Converter) which is responsible for monitoring the
voltages and temperatures. T he ADC converts the analog inputs, ranging from 0V to 4.096V, to 8-bit digital
bytes. Thanks to the additional external com ponents, the analog inputs are able to monitor different voltage
ranges, in addition to monitoring the fixed input range of 0V to 4.096V. Through the external therm istors, the
temperature sensor inputs can be converted to 8-bit digital bytes, enabling the sensor inputs, and monitor ing
the temperature around the therm istors or thermal diode. A built-in ROM is also pr ovided to adjust the non­linear characteristics of thermistors.

FAN Tachometer inputs are digital inputs with an acceptable input r ange of 0V to 5V, and are responsible f or
measuring the FAN’s T achometer pulse periods. FAN_T AC1 and FAN_TAC2 inc lude program mable divisor s,
and can be used to measure different fan speed ranges. FAN_TAC3 also includes programmable divisors, but
can be used to measure two fan speed ranges only.

The EC of the IT8712F provides multiple internal registers and an interrupt generator for programmers to
monitor the environment and c ontrol the FANs. Both the LPC Bus and Serial Bus interfaces are suppor ted to
accommodate the needs for various applications.

9.5.1 Interfaces
LPC Bus: The Environment Controller of the IT8712F decodes two addresses.

Table 9-1. Address Map on the LPC Bus

Registers or Ports Address

Address register of the EC Base+05h

Data register of the EC Base+06h

Note 1: The Base Address is determ ined by the Logical Device configuration registers of the Envir onment
Controller (LDN=04h, registers index=60h, 61h).

To access an EC register , the address of the regis ter is written to the addres s por t (Bas e+05h). Read or write
data from or to that register via data port (Base+06h).

9.5.2 Registers

9.5.2.1 Address Port (Base+05h, Default=00h):

Bit Description

7

Outstanding; Read only

This bit is set when a data write is performed to Address Port via the LPC Bus.

6-0 Index: Internal Address of RAM and Registers.

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Table 9-2. Environment Controller Registers

Index R/W Default Registers or Action

00h R/W 18h Configuration
01h R 00h Interrupt Status 1
02h R 00h Interrupt Status 2
03h R 00h Interrupt Status 3
04h R/W 00h SMI# Mask 1
05h R/W 00h SMI# Mask 2
06h R/W 00h SMI# Mask 3
07h R/W 00h Interrupt Mask 1
08h R/W 00h Interrupt Mask 2

09h R/W 00h Interrupt Mask 3
0Ah R - VID Register
0Bh R/W 09h Fan Tachometer Divisor Register
0Ch R/W 00h Fan Tachometer 16-bit Counter Enable Register
0Dh R - Fan Tachometer 1 Reading Register
0Eh R - Fan Tachometer 2 Reading Register

0Fh R - Fan Tachometer 3 Reading Register

10h R/W - Fan Tachometer 1 Limit Register

11h R/W - Fan Tachometer 2 Limit Register

12h R/W - Fan Tachometer 3 Limit Register

13h R/W 00h Fan Controller Main Control Register

14h R/W 50h FAN_CTL Control Register

15h R/W 00h or 40h FAN_CTL1 PWM Control Register

16h R/W 00h or 40h FAN_CTL2 PWM Control Register

17h R/W 00h or 40h FAN_CTL3 PWM Control Register

18h R - Fan Tachometer 1 Extended Reading Register

19h R - Fan Tachometer 2 Extended Reading Register
1Ah R - Fan Tachometer 3 Extended Reading Register
1Bh R/W - Fan Tachometer 1 Extended Limit Register
1Ch R/W - Fan Tachometer 2 Extended Limit Register
1Dh R/W - Fan Tachometer 3 Extended Limit Register

20h R - VIN0 Voltage Reading Register

21h R - VIN1 Voltage Reading Register

22h R - VIN2 Voltage Reading Register

23h R - VIN3 Voltage Reading Register

24h R - VIN4 Voltage Reading Register

25h R - VIN5 Voltage Reading Register

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Functional Description

Index R/W Default Registers or Action

26h R - VIN6 Voltage Reading Register

27h R - VIN7 Voltage Reading Register

28h R - VBAT Voltage Reading Register

29h R - TMPIN1 Temperature Reading Register
2Ah R - TMPIN2 Temperature Reading Register
2Bh R - TMPIN3 Temperature Reading Register

30h R/W - VIN0 High Limit Register

31h R/W - VIN0 Low Limit Register

32h R/W - VIN1 High Limit Register

33h R/W - VIN1 Low Limit Register

34h R/W - VIN2 High Limit Register

35h R/W - VIN2 Low Limit Register

36h R/W - VIN3 High Limit Register

37h R/W - VIN3 Low Limit Register

38h R/W - VIN4 High Limit Register

39h R/W - VIN4 Low Limit Register
3Ah R/W - VIN5 High Limit Register
3Bh R/W - VIN5 Low Limit Register
3Ch R/W - VIN6 High Limit Register
3Dh R/W - VIN6 Low Limit Register
3Eh R/W - VIN7 High Limit Register

3Fh R/W - VIN7 Low Limit Register

40h R/W - TMPIN1 High Limit Register

41h R/W - TMPIN1 Low Limit Register

42h R/W - TMPIN2 High Limit Register

43h R/W - TMPIN2 Low Limit Register

44h R/W - TMPIN3 High Limit Register

45h R/W - TMPIN3 Low Limit Register

48h R/W - Reserved

50h R/W 00h ADC Voltage Channel Enable Register

51h R/W 00h ADC Temperature Channel Enable Register

52h R/W 7Fh TMPIN1 Thermal Output Limit Register

53h R/W 7Fh TMPIN2 Thermal Output Limit Register

54h R/W 7Fh TMPIN3 Thermal Output Limit Register

56h R/W 56h Thermal Diode 1 Zero Degree Adjust Register

57h R/W 56h Thermal Diode 2 Zero Degree Adjust Register

58h R 90h ITE Vendor ID Register

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Index R/W Default Registers or Action

59h R/W 56h Thermal Diode 3 Zero Degree Adjust Register
5Bh R 12h Core ID Register
5Ch R/W 00h Beep Event Enable Register
5Dh R/W 00h Beep Frequency Divisor of Fan Event Register
5Eh R/W 00h Beep Frequency Divisor of Voltage Event Register

5Fh R/W 00h Beep Frequency Divisor of Temperature Event Register

60h R/W 7Fh FAN_CTL1 SmartGuardian Automatic Mode Temperature Limit of OFF Register

61h R/W 7Fh

62h R/W 7Fh

FAN_CTL1 SmartGuardian Automatic Mode Temperature Limit of Fan Start
Registers

FAN_CTL1 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

ON Registers
63h R/W 00h FAN_CTL1 SmartGuardian Automatic Mode Start PWM Registers
64h R/W 00h FAN_CTL1 SmartGuardian Automatic Mode Control Registers

65h R/W 7Fh

FAN_CTL1 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

OFF Registers
68h R/W 7Fh FAN_CTL2 SmartGuardian Automatic Mode Temperature Limit of OFF Register

69h R/W 7Fh

6Ah R/W 7Fh

FAN_CTL2 SmartGuardian Automatic Mode Temperature Limit of Fan Start

Registers

FAN_CTL2 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

ON Registers

6Bh R/W 00h FAN_CTL2 SmartGuardian Automatic Mode Start PWM Registers
6Ch R/W 00h FAN_CTL2 SmartGuardian Automatic Mode Control Registers

6Dh R/W 7Fh

FAN_CTL2 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

OFF Registers
70h R/W 7Fh FAN_CTL3 SmartGuardian Automatic Mode Temperature Limit of OFF Register

71h R/W 7Fh

72h R/W 7Fh

FAN_CTL3 SmartGuardian Automatic Mode Temperature Limit of Fan Start

Registers

FAN_CTL3 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

ON Registers
73h R/W 00h FAN_CTL3 SmartGuardian Automatic Mode Start PWM Registers
74h R/W 00h FAN_CTL3 SmartGuardian Automatic Mode Control Registers

75h R/W 7Fh

FAN_CTL3 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

OFF Registers
80h R - Fan Tachometer 4 Reading LSB Register
81h R - Fan Tachometer 4 Reading MSB Register
82h R - Fan Tachometer 5 Reading LSB Register
83h R - Fan Tachometer 5 Reading MSB Register
84h R/W - Fan Tachometer 4 Limit LSB Register
85h R/W - Fan Tachometer 4 Limit MSB Register
86h R/W - Fan Tachometer 5 Limit LSB Register

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Functional Description

Index R/W Default Registers or Action

87h R/W - Fan Tachometer 5 Limit MSB Register
88h R/W 00h FAN_CTL4 PWM Control Register
89h R/W 00h FAN_CTL5 PWM Control Register
90h R/W 7Fh FAN_CTL4 SmartGuardian Automatic Mode Temperature Limit of OFF Register

91h R/W 7Fh

92h R/W 7Fh

FAN_CTL4 SmartGuardian Automatic Mode Temperature Limit of Fan Start

Registers

FAN_CTL4 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

ON Registers
93h R/W 00h FAN_CTL4 SmartGuardian Automatic Mode Start PWM Registers
94h R/W 00h FAN_CTL4 SmartGuardian Automatic Mode Control Registers

95h R/W 7Fh

FAN_CTL4 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

OFF Registers
98h R/W 7Fh FAN_CTL5 SmartGuardian Automatic Mode Temperature Limit of OFF Register

99h R/W 7Fh

9Ah R/W 7Fh

FAN_CTL5 SmartGuardian Automatic Mode Temperature Limit of Fan Start

Registers

FAN_CTL5 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

ON Registers

9Bh R/W 00h FAN_CTL5 SmartGuardian Automatic Mode Start PWM Registers
9Ch R/W 00h FAN_CTL5 SmartGuardian Automatic Mode Control Registers

9Dh R/W 7Fh

FAN_CTL5 SmartGuardian Autom atic Mode Temperature Limit of Full-Speed-

OFF Registers

9.5.2.2 Register Description

9.5.2.2.1 Configuration Register (Index=00h, Default=18h)

Bit R/W Description

7 R/W Initialization. A “1” restores all registers to their individual default values, except the Serial

Bus Address register. This bit clears itself when the default value is “0.”

6 R/W
5 R/W
4 R

Update VBAT Voltage Reading
COPEN# cleared; Write “1” to clear COPEN#
Read Only, Always “1.”

3 R/W INT_Clear. A “1” disables the SMI# and IRQ outputs with the contents of interrupt status

bits remain unchanged.

2 R/W

IRQ enables the IRQ Interrupt output

1 R/W SMI# Enable. A “1” enables the SMI# Interrupt output.
0 R/W Start. A “1” enables the startup of monitoring operations while a “0” sends the monitoring

operation in the STANDBY mode.

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9.5.2.2.2 Interrupt Status Register 1 (Index=01h, Default=00h)

Reading this register will clear itself following a read access.

Bit R/W Description

7-5 R

Reserved

4 R A “1” indicates a Case Open event has occurred.
3 R

Reserved

2-0 R A “1” indicates the FAN_TAC3-1 Count limit has been reached.

9.5.2.2.3 Interrupt Status Register 2 (Index=02h, Default=00h)

Reading this register will clear itself after the read operation is completed.

Bit R/W Description

7-0 R A “1” indicates a High or Low limit of VIN7-0 has been reached.

9.5.2.2.4 Interrupt Status Register 3 (Index=03h, Default=00h)

Reading this register will clear itself following a read access.

Bit R/W Description

7-3 R

Reserved

2-0 R A “1” indicates a High or Low limit of Temperature 3-1 has been reached.

9.5.2.2.5 SMI# Mask Register 1 (Index=04h, Default=00h)

Bit R/W Description

7-6 R/W

Reserved

4 R/W A “1” disables the Case Open Intrusion interrupt status bit for SMI#.
3 R/W

Reserved

2-0 R/W A “1” disables the FAN_TAC3-1 interrupt status bit for SMI#.

9.5.2.2.6 SMI# Mask Register 2 (Index=05h, Default=00h)

Bit R/W Description

7-0 R/W A “1” disables the VIN7-0 interrupt status bit for SMI#.

9.5.2.2.7 SMI# Mask Register 3 (Index=06h, Default=00h)

Bit R/W Description

7-3 R/W

Reserved

2-0 R/W A “1” disables the Temperature 3-1 interrupt status bit for SMI#.

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Functional Description

9.5.2.2.8 Interrupt Mask Register 1 (Index=07h, Default=00h)

Bit R/W Description

7-5 R/W

Reserved

4 R/W A “1” disables the Case Open Intrusion interrupt status bit for IRQ.
3 R/W

Reserved

2-0 R/W A “1” disables the FAN_TAC3-1 interrupt status bit for IRQ.

9.5.2.2.9 Interrupt Mask Register 2 (Index=08h, Default=00h)

Bit R/W Description

7-0 R/W A “1” disables the VIN7-0 interrupt status bit for IRQ.

9.5.2.2.10 Interrupt Mask Register 3 (Index=09h, Default=00h)

Bit R/W Description

7-3 R/W

Reserved

2-0 R/W A “1” disables the Temperature 3-1 interrupt status bit for IRQ.

9.5.2.2.11 VID Register (Index=0Ah)

Bit R/W Description

7 R/W

Pseudo-EOC (end of conversion of ADC)

A Pseudo-EOC bit can speed up the FAN speed setup time in SmartGuardian automatic
mode. (Write the bit to 1 then write 0)

6 -

5-0 R

Reserved
VID5-0 Inputs

9.5.2.2.12 Fan Tachometer Divisor Register (Index=0Bh, Default=09h)

Bit R/W Description

7 ­6 R/W

Reserved
FAN_TAC3 Counter Divisor

0: divided by 2
1: divided by 8

5-3 R/W

2-0 R/W

FAN_TAC2 Counter Divisor

000: divided by 1
001: divided by 2
010: divided by 4
011: divided by 8

100: divided by 16
101: divided by 32
110: divided by 64
111: divided by 128

FAN_TAC1 Counter Divisor

000: divided by 1
001: divided by 2
010: divided by 4
011: divided by 8

100: divided by 16
101: divided by 32
110: divided by 64
111: divided by 128

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9.5.2.2.13 Fan Tachometer 16-bit Counter Enable Register (Index=0Ch, Default=00h)

Bit R/W Description

7 R/W

TMPIN3 Enhanced Interrupt Mode Enable

0: Original mode
1: The interrupt will be generated when the TMPIN3 is higher than the high limit or lower
than the low limit.

6 R/W

TMPIN2 Enhanced Interrupt Mode Enable

0: Original mode
1: The interrupt will be generated when the TMPIN2 is higher than the high limit or lower
than the low limit.

5 R/W

FAN_TAC5 Enable

0: disable
1: enable.

4 R/W

FAN_TAC4 Enable

0: disable
1: enable

3 R/W

TMPIN1 Enhance Interrupt Mode Enable

0: Original mode.
1: The interrupt will be generated when the TMPIN1 is higher than the high limit or lower
than the low limit.

2 R/W

FAN_TAC3, 4, 5 16-bit Counter Divisor Enable
0: disable
1: enable

1 R/W

FAN_TAC2 16-bit Counter Divisor Enable
0: disable
1: enable

0 R/W

FAN_TAC1 16-bit Counter Enable
0: disable
1: enable

9.5.2.2.14 Fan Tachometer 1-3 Reading Registers (Index=0Dh-0Fh)

Bit R/W Description

7-0 R The number of counts of the internal clock per revolution.

9.5.2.2.15 Fan Tachometer 1-3 Limit Registers (Index=10h-12h)

Bit R/W Description

7-0 R/W

Limit Value

9.5.2.2.16 Fan Controller Main Control Register (Index=13h, Default=00h)

Bit R/W Description

7 R

6-4 R/W

Reserved
FAN_TAC3-1 Enable

0: disable

1: enable.

3 R/W

FAN_CTL Automa tic mode full speed control.

0: Full speeds of FAN_CTL1-3 automatic mode are independent.

1: All FAN_CTL1-3 will enter full speed when any temperature exceeds full Speed

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Functional Description

Bit R/W Description

Temperature Limit.

2-0 R/W

FAN_CTL3-1 Output Mode Selection

0: ON/OFF mode.
1: SmartGuardian mode.

9.5.2.2.17 FAN_CTL Control Register (Index=14h, Default=50h)

Bit R/W Description

7 R/W

FAN_CTL Polarity

0: Active Low.

1: Active High.

6-4 R/W

PWM base clock select.

000: 48Mhz (PWM Frequency=375Khz).
001: 24Mhz(PWM Frequency=187.5Khz).
010: 12Mhz(PWM Frequency=93.75Khz)
011: 8Mhz(PWM Frequency=62.5Khz)
100: 6Mhz(PWM Frequency=46.875Khz)

101: 3Mhz(PWM Frequency=23.43Khz)

110: 1.5Mhz(PWM Frequency=11.7Khz)
111: 0.75Mhz(PWM Frequency=5.86Khz).

3 R/W PWM Minimum Duty Select.

0: 0 %. For a given PWM value, the actual duty is PWM/128 X 100%.

1: 20 %. For a given PWM value (not 00h), the actual duty is (PWM+32)/160 X
100%. If the given PWM value is 00h, the actual duty will be 0%.

2-0 R/W

FAN_CTL3-1 ON/OFF Mode Control

These bits are only available when the relative output modes are selected in ON/OFF
mode.
0: OFF.
1: ON.

9.5.2.2.18 FAN_CTL1 PWM Control Register (Index=15h, Default=00h or 40h)

This default value of this register is selected by JP5.

Bit R/W Description

7 R/W

FAN_CTL1 PWM mode Automatic/Software Operation Selection

0: Software operation. 1: Automatic operation.

6-0 R/W 128 steps of PWM control when in Software operation (bit 7=0), or

Temperature input selection when in Automatic operation (bit 7=1).

Bits[1:0]:

00: TMPIN1
01: TMPIN2
10: TMPIN3
11: Reserved

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9.5.2.2.19 FAN_CTL2 PWM Control Register (Index=16h, Default=00h or 40h)

This default value of this register is selected by JP5.

Bit R/W Description

7 R/W

FAN_CTL2 PWM mode Automatic/Software Operation Selection

0: Software Operation
1: Automatic Operation

6-0 R/W 128 steps of PWM control when in Software operation (bit 7=0), or

Temperature input selection when in Automatic operation (bit 7=1).

Bits[1:0]:

00: TMPIN1
01: TMPIN2
10: TMPIN3
11: Reserved

9.5.2.2.20 FAN_CTL3 PWM Control Register (Index=17h, Default=00h or 40h)

This default value of this register is selected by JP5.

Bit R/W Description

7 R/W

FAN_CTL3 PWM mode Automatic/Software Operation Selection

0: Software Operation
1: Automatic Operation

6-0 R/W 128 steps of PWM control when in Software operation (bit 7=0), or

Temperature input selection when in Automatic operation (bit 7=1).

Bits[1:0]:

00: TMPIN1
01: TMPIN2
10: TMPIN3
11: Reserved

9.5.2.2.21 Fan Tachometer 1-3 Extended Reading Registers (Index=18h-1Ah)

Bit R/W Description

7-0 R

The number of counts of the internal clock per revolution. [15:8]

9.5.2.2.22 Fan Tachometer 1-3 Extended Limit Registers (Index=1Bh-1Dh)

Bit R/W Description

7-0 R

Limit Value. [15:8]

9.5.2.2.23 VIN7-VIN0 Voltage Reading Registers (Index=27h-20h)

Bit R/W Description

7-0 R

Voltage Reading Values

9.5.2.2.24 VBAT Voltage Reading Register (Index=28h)

Bit R/W Description

7-0 R

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VBAT Voltage Reading Value

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Functional Description

9.5.2.2.25 TMPIN3-1 Temperature Reading Registers (Index=2Bh-29h)

Bit R/W Description

7-0 R

Temperature Reading Values

9.5.2.2.25.1 VIN7-0 High Limit Registers (Index=3Eh, 3Ch, 3Ah, 38h, 36h, 34h, 32h, 30h)

Bit R/W Description

7-0 R/W

High Limit Value

9.5.2.2.26 VIN7-0 Low Limit Registers (Index=3Fh, 3Dh, 3Bh, 39h, 37h, 35h, 33h, 31h)

Bit R/W Description

7-0 R/W

Low Limit Value

9.5.2.2.27 TMPIN3-1 High Limit Registers (Index=44h, 42h, 40h)

Bit R/W Description

7-0 R/W

High Limit Value

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9.5.2.2.28 TMPIN3-1 Low Limit Registers (Index=45h, 43h, 41h)

Bit R/W Description

7-0 R/W

Low Limit value

9.5.2.2.29 ADC Voltage Channel Enable Register (Index=50h, Default=00h)

Bit R/W Description

7-0 R/W

ADC VIN7-VIN0 Scan Enable

9.5.2.2.30 ADC Temperature Channel Enable Register (Index=51h, Default=00h)

TMPIN3-1 cannot be enabled in both Thermal Resistor mode and Thermal Diode (Diode connected Transistor)
mode.

Bit R/W Description

7-6 R/W

Reserved

5-3 R/W TMPIN3-1 are enabled in Thermal Resistor mode.
2-0 R/W TMPIN3-1 are enabled in Thermal Diode (or Diode-connected Transistor) mode.

9.5.2.2.31 TMPIN3-1 Thermal Output Limit Registers (Index=54h-52h, Default=7Fh)

Bit R/W Description

7-0 R/W

Thermal Output Limit Value

9.5.2.2.32 Thermal Diode Zero Degree Adjust 1 Register (Index=56h, Default=56h)
This register is read only unless the bit 7 of 5Ch is set.

Bit R/W Description

7-0 R/W

Thermal Diode 1 Zero Degree Voltage Value (default: 0.664V 156h)

9.5.2.2.33 Thermal Diode Zero Degree Adjust 2 Register (Index=57h, Default=56h)
This register is read only unless the bit 7 of 5Ch is set.

Bit R/W Description

7-0 R/W

Thermal Diode 2 Zero Degree Voltage Value (default: 0.664V 156h)

9.5.2.2.34 Vendor ID Register (Index=58h, Default=90h)

Bit R/W Description

7-0 R

ITE Vendor ID. Read Only

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