ITE IT8510E, IT8510G, IT8510TE Schematics

IT8510E/TE/G

Embedded Controller

Preliminary Specification 0.7.2

ITE TECH. INC.

Specification subject to Change without notice, AS IS a nd for reference only. For purchasing, please contact sales
representatives.

Copyright © 2005 ITE Tech. Inc.

This is Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous documentation issued for the related products
included herein. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to ITE’s Standard
Terms and Conditions, a copy of which is included in the back of this document.

ITE, IT8510E/TE/G is a trademark of ITE Tech. Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.

Additional copies of this manual or other ITE literature may be obtained from:

ITE Tech. Inc. Phone: [phone]
Marketing Department Fax: [phone]

8F, No. 233-1, Bao Chiao RD., Hsin Tien,
Taipei County 231, Taiwan, R.O.C.

If you have any marketing or sales questions, please contact:

P.Y. Chang, at ITE Taiwan: E-mail: [e-mail], Tel: [phone] X6052,

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y

Revision Histor

Revision History

Section Revision Page No.

6

 In section 6.2.2.4, the value of Chip Version (CHIPVER) was changed. 48

6  In section 6.3.4.1 FBIU Configuration Register (FBCFG), OVRSHBM

and OVRBADDR fields were added.

6  In section 6.3.4.2 Flash Programming Configuration Register (FPCFG),

HSPD field was added.

7  In section 7.4.3.5 Keyboard Scan In Control Register (KSICTRLR),

OVRPPEN field was added.

7  In section 7.5.3.1 General Control Register (GCR), GFLE field was

added.

7  In section 7.11.4.5 Prescaler Clock Frequency Select Register

(PCFSR), its table was revised.

7

4, 11

12

 In section 7.14.4.10, Chip Version (ECHIPVER) was added 247

 TFBGA package information was added. 263

 In section 12 Ordering Information, lead-free information was added. 267

76

77

174

176

222

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CONTENTS

1. Features ....................................................................................................................................................... 1

2. General Description ....................................................................................................................................... 3

3. System Block Diagram................................................................................................................................... 5

3.1 Block Diagram..................................................................................................................................... 5

3.2 Host/EC Mapped Memory Space ....................................................................................................... 6

3.3 EC Mapped Memory Space................................................................................................................ 9

3.4 Register Abbreviation........................................................................................................................ 10

4. Pin Configuration ......................................................................................................................................... 11

5. Pin Descriptions ........................................................................................................................................... 17

5.1 Pin Descriptions ................................................................................................................................ 17

5.2 Chip Power Planes and Power States..............................................................................................23

5.3 Pin Power Planes and States ........................................................................................................... 24

5.4 PWRFAIL# Interrupt to INTC ........................................................................................................... 28

5.5 Reset Sources and Types................................................................................................................. 29

5.5.1 Relative Interrupts to INTC................................................................................................... 29

5.6 Chip Power Mode and Clock Domain............................................................................................... 30

5.7 Pins with Pull, Schmitt-Trigger or Open-Drain Function ................................................................... 34

5.8 Power Consumption Consideration .................................................................................................. 36

6. Host Domain Functions................................................................................................................................ 39

6.1 Low Pin Count Interface.................................................................................................................... 39

6.1.1 Overview............................................................................................................................... 39

6.1.2 Features ............................................................................................................................... 39

6.1.3 Accepted LPC Cycle Type ................................................................................................... 39

6.1.4 Debug Port Function ............................................................................................................ 40

6.1.5 Serialized IRQ (SERIRQ) ..................................................................................................... 40

6.1.6 Relative Interrupts to INTC/WUC ......................................................................................... 41

6.1.7 LPCPD# and CLKRUN#....................................................................................................... 42

6.1.8 Check Items.......................................................................................................................... 43

6.2 Plug and Play Configuration (PNPCFG)........................................................................................... 44

6.2.1 Logical Device Assignment .................................................................................................. 47

6.2.2 Super I/O Configuration Registers ....................................................................................... 48

6.2.2.1 Logical Device Number (LDN)................................................................................. 48

6.2.2.2 Chip ID Byte 1 (CHIPID1)........................................................................................ 48

6.2.2.3 Chip ID Byte 2 (CHIPID2)........................................................................................ 48

6.2.2.4 Chip Version (CHIPVER)......................................................................................... 48

6.2.2.5 Super I/O Control Register (SIOCTRL) ................................................................... 48

6.2.2.6 Super I/O IRQ Configuration Register (SIOIRQ)..................................................... 49

6.2.2.7 Super I/O General Purpose Register (SIOGP)........................................................ 49

6.2.2.8 Super I/O Power Mode Register (SIOPWR) ........................................................... 50

6.2.3 Standard Logical Device Configuration Registers................................................................ 50

6.2.3.1 Logical Device Activate Register (LDA)................................................................... 51

6.2.3.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 51

6.2.3.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 51

6.2.3.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 51

6.2.3.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 52

6.2.3.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 52

6.2.3.7 Interrupt Request Type Select (IRQTP) .................................................................. 52

6.2.3.8 DMA Channel Select 0 (DMAS0) ............................................................................ 53

6.2.3.9 DMA Channel Select 0 (DMAS1) ............................................................................ 53

6.2.4 System Wake-Up Control (SWUC) Configuration Registers ............................................... 53

6.2.4.1 Logical Device Activate Register (LDA)................................................................... 53

6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 53

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6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 54

6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 54

6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 54

6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 54

6.2.4.7 Interrupt Request Type Select (IRQTP) .................................................................. 54

6.2.5 KBC / Mouse Interface Configuration Registers .................................................................. 54

6.2.5.1 Logical Device Activate Register (LDA)................................................................... 55

6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 55

6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 55

6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 55

6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 55

6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 56

6.2.5.7 Interrupt Request Type Select (IRQTP) .................................................................. 56

6.2.6 KBC / Keyboard Interface Configuration Registers.............................................................. 56

6.2.6.1 Logical Device Activate Register (LDA)................................................................... 56

6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 56

6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 56

6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 57

6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 57

6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 57

6.2.6.7 Interrupt Request Type Select (IRQTP) .................................................................. 57

6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers ........................................ 57

6.2.7.1 Logical Device Activate Register (LDA)................................................................... 58

6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 58

6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 58

6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 58

6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 58

6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 58

6.2.7.7 Interrupt Request Type Select (IRQTP) .................................................................. 59

6.2.7.8 Shared Memory Configuration Register (SHMC) .................................................... 59

6.2.7.9 Shared Memory Base Address High Byte Register (SHMBAH).............................. 59

6.2.7.10 Shared Memory Base Address Low Byte Register (SHMBAL) ............................... 59

6.2.7.11 Shared Memory Size Configuration Register (SHMSZ) .......................................... 60

6.2.7.12 LPC Memory Control (LPCMCTRL) ........................................................................ 60

6.2.8 Real Time Clock (RTC) Configuration Registers ................................................................. 60

6.2.8.1 Logical Device Activate Register (LDA)................................................................... 61

6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 61

6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 61

6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 61

6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 62

6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 62

6.2.8.7 Interrupt Request Type Select (IRQTP) .................................................................. 62

6.2.8.8 RAM Lock Register (RLR) ....................................................................................... 62

6.2.8.9 Date of Month Alarm Register Offset (DOMAO) ..................................................... 62

6.2.8.10 Month Alarm Register Offset (MONAO) .................................................................. 63

6.2.9 Power Management I/F Channel 1 Configuration Registers................................................ 63

6.2.9.1 Logical Device Activate Register (LDA)................................................................... 63

6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 63

6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 63

6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 64

6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 64

6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 64

6.2.9.7 Interrupt Request Type Select (IRQTP) .................................................................. 64

6.2.10 Power Management I/F Channel 2 Configuration Registers................................................ 64

6.2.10.1 Logical Device Activate Register (LDA)................................................................... 65

6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 65

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6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 65

6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 65

6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0]) ............................ 65

6.2.10.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 65

6.2.10.7 Interrupt Request Type Select (IRQTP) .................................................................. 65

6.2.11 Programming Guide ............................................................................................................. 67

6.3 Shared Memory Flash Interface Bridge (SMFI) ................................................................................ 69

6.3.1 Overview............................................................................................................................... 69

6.3.2 Features ............................................................................................................................... 69

6.3.3 Function Description............................................................................................................. 69

6.3.3.1 Flash Requirement .................................................................................................. 69

6.3.3.2 Host to M Bus Translation ....................................................................................... 69

6.3.3.3 Memory Mapping ..................................................................................................... 69

6.3.3.4 Indirect Memory Read/Write Transaction ................................................................ 70

6.3.3.5 Locking Between Host and EC Domains................................................................. 70

6.3.3.6 Host Access Protection............................................................................................ 71

6.3.3.7 Response to a Forbidden Access............................................................................ 71

6.3.3.8 Scratch SRAM ......................................................................................................... 71

6.3.3.9 No-wait Mode........................................................................................................... 72

6.3.3.10 Flash Interface ......................................................................................................... 72

6.3.4 EC Interface Registers ......................................................................................................... 76

6.3.4.1 FBIU Configuration Register (FBCFG) .................................................................... 76

6.3.4.2 Flash Programming Configuration Register (FPCFG)............................................. 77

6.3.4.3 Memory Zone Configuration Register (MZCFG) ..................................................... 77

6.3.4.4 Static Memory Zone Configuration Register (SMZCFG)......................................... 78

6.3.4.5 Flash EC Code Banking Select Register (FECBSR)............................................... 79

6.3.4.6 Flash Memory Size Select Register (FMSSR) ........................................................ 79

6.3.4.7 Flash Memory Prescaler Register (FMPSR) ........................................................... 80

6.3.4.8 Shared Memory EC Control and Status Register (SMECCS)................................. 80

6.3.4.9 Shared Memory Host Semaphore Register (SMHSR) ............................................ 81

6.3.4.10 Shared Memory EC Override Read Protect Registers 0-9 (SMECORPR 0-9) ....... 81

6.3.4.11 Shared Memory EC Override Write Protect Registers 0-9 (SMECOWPR0-9) ....... 82

6.3.5 Host Interface Registers....................................................................................................... 83

6.3.5.1 Shared Memory Indirect Memory Address Register 0 (SMIMAR0) ........................ 84

6.3.5.2 Shared Memory Indirect Memory Address Register 1 (SMIMAR1) ........................ 84

6.3.5.3 Shared Memory Indirect Memory Address Register 2 (SMIMAR2) ........................ 84

6.3.5.4 Shared Memory Indirect Memory Address Register 3 (SMIMAR3) ........................ 84

6.3.5.5 Shared Memory Indirect Memory Data Register (SMIMDR) ................................... 84

6.3.5.6 Shared Memory Host Access Protect Register 1-4 (SMHAPR1-4)........................ 84

6.3.5.7 Shared Memory Host Semaphore Register (SMHSR) ............................................ 85

6.4 System Wake-Up Control (SWUC) ...................................................................................................86

6.4.1 Overview............................................................................................................................... 86

6.4.2 Features ............................................................................................................................... 86

6.4.3 Functional Description..........................................................................................................86

6.4.3.1 Wake-Up Status....................................................................................................... 86

6.4.3.2 Wake-Up Events...................................................................................................... 87

6.4.3.3 Wake-Up Output Events.......................................................................................... 88

6.4.3.4 Other SWUC Controlled Options............................................................................. 88

6.4.4 Host Interface Registers....................................................................................................... 90

6.4.4.1 Wake-Up Event Status Register (WKSTR) ............................................................. 90

6.4.4.2 Wake-Up Event Enable Register (WKER)............................................................... 91

6.4.4.3 Wake-Up Signals Monitor Register (WKSMR) ........................................................ 91

6.4.4.4 Wake-Up ACPI Status Register (WKACPIR) .......................................................... 92

6.4.4.5 Wake-Up SMI Enable Register (WKSMIER)........................................................... 92

6.4.4.6 Wake-Up IRQ Enable Register (WKIRQER)........................................................... 93

6.4.5 EC Interface Registers ......................................................................................................... 93

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6.4.5.1 SWUC Control Status 1 Register (SWCTL1) .......................................................... 93

6.4.5.2 SWUC Control Status 2 Register (SWCTL2) .......................................................... 94

6.4.5.3 SWUC Control Status 3 Register (SWCTL3) .......................................................... 95

6.4.5.4 SWUC Host Configuration Base Address Low Byte Register (SWCBALR)............ 95

6.4.5.5 SWUC Host Configuration Base Address High Byte Register (SWCBAHR) .......... 95

6.4.5.6 SWUC Interrupt Enable Register (SWCIER)........................................................... 95

6.4.5.7 SWUC Host Event Status Register (SWCHSTR).................................................... 96

6.4.5.8 SWUC Host Event Interrupt Enable Register (SWCHIER) ..................................... 97

6.5 Keyboard Controller (KBC) ............................................................................................................... 98

6.5.1 Overview............................................................................................................................... 98

6.5.2 Features ............................................................................................................................... 98

6.5.3 Functional Description..........................................................................................................98

6.5.4 Host Interface Registers....................................................................................................... 99

6.5.4.1 KBC Data Input Register (KBDIR)......................................................................... 100

6.5.4.2 KBC Data Output Register (KBDOR) .................................................................... 100

6.5.4.3 KBC Command Register (KBCMDR) .................................................................... 100

6.5.4.4 KBC Status Register (KBSTR) .............................................................................. 100

6.5.5 EC Interface Registers ....................................................................................................... 101

6.5.5.1 KBC Host Interface Control Register (KBHICR).................................................... 101

6.5.5.2 KBC Interrupt Control Register (KBIRQR)............................................................. 102

6.5.5.3 KBC Host Interface Keyboard/Mouse Status Register (KBHISR) ......................... 103

6.5.5.4 KBC Host Interface Keyboard Data Output Register (KBHIKDOR) ...................... 103

6.5.5.5 KBC Host Interface Mouse Data Output Register (KBHIMDOR) .......................... 103

6.5.5.6 KBC Host Interface Keyboard/Mouse Data Input Register (KBHIDIR) ................. 104

6.6 Power Management Channel (PMC).............................................................................................. 105

6.6.1 Overview............................................................................................................................. 105

6.6.2 Features ............................................................................................................................. 105

6.6.3 Functional Description........................................................................................................ 105

6.6.3.1 General Description ............................................................................................... 105

6.6.3.2 Compatible Mode................................................................................................... 106

6.6.3.3 Enhanced PM mode .............................................................................................. 107

6.6.4 Host Interface Registers..................................................................................................... 108

6.6.4.1 PMC Data Input Register (PMDIR)........................................................................ 109

6.6.4.2 PMC Data Output Register (PMDOR) ................................................................... 109

6.6.4.3 PMC Command Register (PMCMDR) ................................................................... 109

6.6.4.4 Status Register (PMSTR) ...................................................................................... 109

6.6.5 EC Interface Registers ....................................................................................................... 110

6.6.5.1 PM Status Register (PMSTS)................................................................................ 110

6.6.5.2 PM Data Out Port (PMDO) .................................................................................... 111

6.6.5.3 PM Data Out Port with SCI (PMDOSCI)................................................................ 111

6.6.5.4 PM Data Out Port with SMI (PMDOSMI)............................................................... 111

6.6.5.5 PM Data In Port (PMDI)......................................................................................... 111

6.6.5.6 PM Data In Port with SCI (PMDISCI) .................................................................... 112

6.6.5.7 PM Control (PMCTL) ............................................................................................. 112

6.6.5.8 PM Interrupt Control (PMIC).................................................................................. 113

6.6.5.9 PM Interrupt Enable (PMIE) .................................................................................. 113

6.7 Real-Time Clock (RTC)................................................................................................................... 115

6.7.1 Overview............................................................................................................................. 115

6.7.2 Feature ............................................................................................................................... 115

6.7.3 Functional Description........................................................................................................ 115

6.7.4 Host Interface Registers..................................................................................................... 116

6.7.4.1 RTC Bank 0 Register............................................................................................. 118

6.7.4.1.1 Seconds Register (SECREG) ....................................................... 118

6.7.4.1.2 Seconds Alarm 1 Register (SECA1REG) ...................................... 118

6.7.4.1.3 Minutes Register (MINREG) ......................................................... 119

6.7.4.1.4 Minutes Alarm 1 Register (MINA1REG) ........................................ 119

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6.7.4.1.5 Hours Register (HRREG)............................................................... 119

6.7.4.1.6 Hours Alarm 1 Register (HRA1REG)............................................. 119

6.7.4.1.7 Day Of Week Register (DOWREG) ............................................... 119

6.7.4.1.8 Date Of Month Register (DOMREG).............................................. 120

6.7.4.1.9 Month Register (MONREG) ........................................................... 120

6.7.4.1.10 Year Register (YRREG)................................................................. 120

6.7.4.1.11 RTC Control Register A (CTLREGA)............................................. 120

6.7.4.1.12 RTC Control Register B (CTLREGB)............................................. 121

6.7.4.1.13 RTC Control Register C (CTLREGC) ............................................ 122

6.7.4.1.14 RTC Control Register D (CTLREGD) ............................................ 123

6.7.4.1.15 Date of Month Alarm 1 Register (DOMA1REG)............................. 123

6.7.4.1.16 Month Alarm 1 Register (MONA1REG) ......................................... 123

6.7.4.2 RTC Bank 1 Register............................................................................................. 123

6.7.4.2.1 Seconds Alarm 2 Register (SECA2REG) ...................................... 123

6.7.4.2.2 Minutes Alarm 2 Register (MINA2REG) ........................................ 123

6.7.4.2.3 Hours Alarm 2 Register (HRA2REG)............................................. 124

6.7.4.2.4 Date of Month Alarm 2 Register (DOMA2REG)............................. 124

6.7.4.2.5 Month Alarm 2 Register (MONA2REG) ......................................... 124

6.7.4.3 RTC I/O Register ................................................................................................... 124

6.7.4.3.1 RTC Index Register of Bank 0 (RIRB0) ......................................... 124

6.7.4.3.2 RTC Data Register of Bank 0 (RDRB0)......................................... 124

6.7.4.3.3 RTC Index Register of Bank 1 (RIRB1) ......................................... 125

6.7.4.3.4 RTC Data Register of Bank 1 (RDRB1)......................................... 125

7. EC Domain Functions ................................................................................................................................ 127

7.1 8032 Embedded Controller (EC)..................................................................................................... 127

7.1.1 Overview............................................................................................................................. 127

7.1.2 Features ............................................................................................................................. 127

7.1.3 General Description............................................................................................................ 127

7.1.4 Functional Description....................................................................................................... 127

7.1.5 Memory Organization ......................................................................................................... 128

7.1.6 On-Chip Peripherals........................................................................................................... 129

7.1.7 Timer / Counter................................................................................................................... 131

7.1.8 Idle and Doze/Sleep Mode ................................................................................................. 142

7.1.9 EC Internal Register Description........................................................................................ 143

7.1.9.1 Port 0 Register (P0R) ............................................................................................ 143

7.1.9.2 Stack Pointer Register (SPR) ................................................................................ 143

7.1.9.3 Data Pointer Low Register (DPLR)........................................................................ 143

7.1.9.4 Data Pointer High Register (DPHR) ...................................................................... 144

7.1.9.5 Data Pointer 1 Low Register (DP1LR)................................................................... 144

7.1.9.6 Data Pointer 1 High Register (DP1HR) ................................................................. 144

7.1.9.7 Data Pointer Select Register (DPSR).................................................................... 144

7.1.9.8 Power Control Register (PCON)............................................................................ 144

7.1.9.9 Timer Control Register (TCON)............................................................................. 146

7.1.9.10 Timer Mode Register (TMOD) ............................................................................... 146

7.1.9.11 Timer 0 Low Byte Register (TL0R) ........................................................................ 147

7.1.9.12 Timer 1 Low Byte Register (TL1R) ........................................................................ 147

7.1.9.13 Timer 0 High Byte Register (TH0R)....................................................................... 147

7.1.9.14 Timer 1 Low Byte Register (TH1R) ....................................................................... 147

7.1.9.15 Clock Control Register (CKCON) .......................................................................... 147

7.1.9.16 Port 1 Register (P1R) ............................................................................................ 148

7.1.9.17 Serial Port Control Register (SCON) ..................................................................... 148

7.1.9.18 Serial Port Buffer Register (SBUFR) ..................................................................... 149

7.1.9.19 Port 2 Register (P2R) ............................................................................................ 149

7.1.9.20 Interrupt Enable Register (IE) ................................................................................ 149

7.1.9.21 Port 3 Register (P3R) ............................................................................................ 149

7.1.9.22 Interrupt Priority Register (IP)................................................................................ 150

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7.1.9.23 Status Register (STATUS) ................................................................................... 150

7.1.9.24 Timer 2 Control Register (T2CON)........................................................................ 150

7.1.9.25 Timer Mode Register (T2MOD) ............................................................................. 151

7.1.9.26 Timer 2 Capture Low Byte Register (RCAP2LR) ..................................................151

7.1.9.27 Timer 2 Capture High Byte Register (RCAP2HR) ................................................. 151

7.1.9.28 Timer 2 Low Byte Register (TL2R) ........................................................................ 151

7.1.9.29 Timer 2 High Byte Register (TH2R)....................................................................... 152

7.1.9.30 Program Status Word Register (PSW) .................................................................. 152

7.1.9.31 Watch Dog Timer Control Register (WDTCON).................................................... 152

7.1.9.32 Accumulator Register (ACC) ................................................................................. 153

7.1.9.33 Power Down Control Register (PDCON)............................................................... 153

7.1.9.34 B Register (BR)...................................................................................................... 153

7.1.10 Programming Guide ........................................................................................................... 154

7.2 Interrupt Controller (INTC) .............................................................................................................. 155

7.2.1 Overview............................................................................................................................. 155

7.2.2 Features ............................................................................................................................. 155

7.2.3 Functional Description........................................................................................................ 155

7.2.3.1 Power Fail Interrupt ............................................................................................... 155

7.2.3.2 Programmable Interrupts....................................................................................... 155

7.2.4 EC Interface Registers ....................................................................................................... 156

7.2.4.1 Interrupt Status Register 0 (ISR0) ......................................................................... 157

7.2.4.2 Interrupt Status Register 1 (ISR1) ......................................................................... 157

7.2.4.3 Interrupt Status Register 2 (ISR2) ......................................................................... 158

7.2.4.4 Interrupt Status Register 3 (ISR3) ......................................................................... 158

7.2.4.5 Interrupt Enable Register 0 (IER0) ........................................................................ 158

7.2.4.6 Interrupt Enable Register 1 (IER1) ........................................................................ 159

7.2.4.7 Interrupt Enable Register 2 (IER2) ........................................................................ 159

7.2.4.8 Interrupt Enable Register 3 (IER3) ........................................................................ 159

7.2.4.9 Interrupt Edge/Level-Triggered Mode Register 0 (IELMR0).................................. 159

7.2.4.10 Interrupt Edge/Level-Triggered Mode Register 1 (IELMR1).................................. 159

7.2.4.11 Interrupt Edge/Level-Triggered Mode Register 2 (IELMR2).................................. 160

7.2.4.12 Interrupt Edge/Level-Triggered Mode Register 3 (IELMR3).................................. 160

7.2.4.13 Interrupt Polarity Register 0 (IPOLR0)................................................................... 160

7.2.4.14 Interrupt Polarity Register 1 (IPOLR1)................................................................... 160

7.2.4.15 Interrupt Polarity Register 2 (IPOLR2)................................................................... 162

7.2.4.16 Interrupt Polarity Register 3 (IPOLR3)................................................................... 162

7.2.4.17 Interrupt Vector Register (IVCT)............................................................................ 162

7.2.4.18 8032 INT0# Status (INT0ST)................................................................................. 162

7.2.4.19 Power Fail Register (PFAILR) ............................................................................... 163

7.2.5 INTC Interrupt Assignments ............................................................................................... 164

7.2.6 Programming Guide ........................................................................................................... 166

7.3 Wake-Up Control (WUC) ................................................................................................................ 167

7.3.1 Overview............................................................................................................................. 167

7.3.2 Features ............................................................................................................................. 167

7.3.3 Functional Description........................................................................................................ 167

7.3.4 EC Interface Registers ....................................................................................................... 167

7.3.4.1 Wake-Up Edge Mode Register (WUEMR1) .......................................................... 167

7.3.4.2 Wake-Up Edge Mode Register (WUEMR2) .......................................................... 168

7.3.4.3 Wake-Up Edge Mode Register (WUEMR3) .......................................................... 168

7.3.4.4 Wake-Up Edge Mode Register (WUEMR4) .......................................................... 168

7.3.4.5 Wake-Up Edge Sense Register (WUESR1).......................................................... 168

7.3.4.6 Wake-Up Edge Sense Register (WUESR2).......................................................... 169

7.3.4.7 Wake-Up Edge Sense Register (WUESR3).......................................................... 169

7.3.4.8 Wake-Up Edge Sense Register (WUESR4).......................................................... 169

7.3.4.9 Wake-Up Enable Register (WUENR1) .................................................................. 170

7.3.4.10 Wake-Up Enable Register (WUENR2) .................................................................. 170

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7.3.4.11 Wake-Up Enable Register (WUENR3) .................................................................. 170

7.3.4.12 Wake-Up Enable Register (WUENR4) .................................................................. 170

7.3.5 WUC Input Assignments .................................................................................................... 171

7.3.6 Programming Guide ........................................................................................................... 172

7.4 Keyboard Matrix Scan Controller .................................................................................................... 173

7.4.1 Overview............................................................................................................................. 173

7.4.2 Features ............................................................................................................................. 173

7.4.3 EC Interface Registers ....................................................................................................... 173

7.4.3.1 Keyboard Scan Out Low Byte Data Register (KSOLR)......................................... 173

7.4.3.2 Keyboard Scan Out High Byte Data Register (KSOHR) ....................................... 173

7.4.3.3 Keyboard Scan Out Control Register (KSOCTRLR) ............................................. 173

7.4.3.4 Keyboard Scan In Data Register (KSIR) ............................................................... 174

7.4.3.5 Keyboard Scan In Control Register (KSICTRLR).................................................. 174

7.5 General Purpose I/O Port (GPIO) ................................................................................................... 175

7.5.1 Overview............................................................................................................................. 175

7.5.2 Features ............................................................................................................................. 175

7.5.3 EC Interface Registers ....................................................................................................... 175

7.5.3.1 General Control Register (GCR) ........................................................................... 176

7.5.3.2 Port Data Registers A-I (GPDRA-GPDRI)............................................................. 176

7.5.3.3 Port Control n Registers (GPCRn, n = A0-I7)........................................................ 177

7.5.3.4 Output Type Registers A-I (GPOTA-GPOTI)......................................................... 177

7.5.4 Alternate Function Selection .............................................................................................. 179

7.5.5 Programming Guide ........................................................................................................... 181

7.6 EC Clock and Power Management Controller (ECPM) .................................................................. 182

7.6.1 Overview............................................................................................................................. 182

7.6.2 Features ............................................................................................................................. 182

7.6.3 EC Interface Registers ....................................................................................................... 182

7.6.3.1 Clock Frequency Select Register (CFSELR) ........................................................ 182

7.6.3.2 Clock Gating Control 1 Register (CGCTRL1R) ..................................................... 182

7.6.3.3 Clock Gating Control 2 Register (CGCTRL2R) ..................................................... 183

7.6.3.4 PLL Control (PLLCTRL) ........................................................................................ 183

7.7 SM Bus Interface (SMB) ................................................................................................................. 184

7.7.1 Overview............................................................................................................................. 184

7.7.2 Features ............................................................................................................................. 184

7.7.3 Functional Description........................................................................................................ 184

7.7.3.1 SMBUS Master Interface....................................................................................... 184

7.7.3.2 SMBUS Slave Interface ......................................................................................... 185

7.7.3.3 SMBUS Porting Guide ........................................................................................... 186

7.7.4 EC Interface Registers ....................................................................................................... 190

7.7.4.1 Host Status Register (HOSTA).............................................................................. 191

7.7.4.2 Host Control Register (HOCTL)............................................................................. 191

7.7.4.3 Host Command Register (HOCMD) ...................................................................... 192

7.7.4.4 Transmit Slave Address Register (TRASLA) ........................................................ 192

7.7.4.5 Data 0 Register (D0REG)...................................................................................... 192

7.7.4.6 Data 1 Register (D1REG)...................................................................................... 193

7.7.4.7 Host Block Data Byte Register (HOBDB) .............................................................. 193

7.7.4.8 Packet Error Check Register (PECERC)............................................................... 193

7.7.4.9 Receive Slave Address Register (RESLADR) ...................................................... 193

7.7.4.10 Slave Data Register (SLDA) .................................................................................. 193

7.7.4.11 SMBUS Pin Control Register (SMBPCTL) ............................................................ 194

7.7.4.12 Slave Status Register (SLSTA) ............................................................................. 194

7.7.4.13 Slave Interrupt Control Register (SICR) ................................................................ 195

7.7.4.14 Notify Device Address Register (NDADR)............................................................. 195

7.7.4.15 Notify Data Low Byte Register (NDLB).................................................................. 195

7.7.4.16 Notify Data High Byte Register (NDHB) ................................................................ 195

7.7.4.17 Host Control Register 2 (HOCTL2)........................................................................ 196

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7.7.4.18 4.7 µs Register (4P7USREG) ................................................................................ 196

7.7.4.19 4.0 µs Register (4P0USREG) ................................................................................ 196

7.7.4.20 300 ns Register (300NSREG) ............................................................................... 196

7.7.4.21 250 ns Register (250NSREG) ............................................................................... 197

7.7.4.22 25 ms Register (25MSREG).................................................................................. 197

7.7.4.23 45.3 µs Low Register (45P3USLREG) .................................................................. 197

7.7.4.24 45.3 µs High Register (45P3USHREG)................................................................. 197

7.8 PS/2 Interface ................................................................................................................................. 198

7.8.1 Overview............................................................................................................................. 198

7.8.2 Features ............................................................................................................................. 198

7.8.3 Functional Description........................................................................................................ 198

7.8.3.1 Hardware Mode Selected ...................................................................................... 198

7.8.3.2 Software Mode Selected ....................................................................................... 199

7.8.4 EC Interface Registers ....................................................................................................... 199

7.8.4.1 PS/2 Control Register 1-4 (PSCTL1-4) ................................................................. 200

7.8.4.2 PS/2 Interrupt Control Register 1-4 (PSINT1-4)................................................... 200

7.8.4.3 PS/2 Status Register 1-4 (PSSTS1-4)................................................................... 201

7.8.4.4 PS/2 Data Register 1-4 (PSDAT1-4) ..................................................................... 201

7.9 Digital To Analog Converter (DAC)................................................................................................. 202

7.9.1 Overview............................................................................................................................. 202

7.9.2 Feature ............................................................................................................................... 202

7.9.3 Functional Description........................................................................................................ 202

7.9.4 EC Interface Registers ....................................................................................................... 202

7.9.4.1 DAC Control Register (DACCTRL)........................................................................ 202

7.9.4.2 DAC Data Channel 0~3 Register (DACDAT0~3) .................................................. 203

7.10 Analog to Digital Converter (ADC) .................................................................................................. 204

7.10.1 Overview............................................................................................................................. 204

7.10.2 Features ............................................................................................................................. 204

7.10.3 Functional Description........................................................................................................ 204

7.10.3.1 ADC General Description ...................................................................................... 205

7.10.3.2 Voltage Measurement............................................................................................ 205

7.10.3.3 ADC Operation ...................................................................................................... 206

7.10.4 EC Interface Registers ....................................................................................................... 207

7.10.4.1 ADC Status Register (ADCSTS) ........................................................................... 207

7.10.4.2 ADC Configuration Register (ADCCFG)................................................................ 208

7.10.4.3 ADC Clock Control Register (ADCCTL) ................................................................ 208

7.10.4.4 ADC Delay Control Register (ADCDCTL) ............................................................. 209

7.10.4.5 Calibration Data Control Register (KDCTL) .......................................................... 209

7.10.4.6 Voltage Channel 1 Control Register (VCH1CTL) .................................................. 210

7.10.4.7 Volt Channel 1 Data Buffer LSB (VCH1DATL)...................................................... 212

7.10.4.8 Volt Channel 1 Data Buffer MSB (VCH1DATM).................................................... 212

7.10.4.9 Voltage Channel 2 Control Register (VCH2CTL) .................................................. 212

7.10.4.10 Volt Channel 2 Data Buffer LSB (VCH2DATL)...................................................... 212

7.10.4.11 Volt Channel 2 Data Buffer MSB (VCH2DATM).................................................... 212

7.10.4.12 Voltage Channel 3 Control Register (VCHN3CTL) ............................................... 213

7.10.4.13 Volt Channel 3 Data Buffer LSB (VCH3DATL)...................................................... 213

7.10.4.14 Volt Channel 3 Data Buffer MSB (VCH3DATM).................................................... 213

7.10.4.15 Volt High Scale Calibration Data Buffer LSB (VHSCDBL) .................................... 213

7.10.4.16 Volt High Scale Calibration Data Buffer MSB (VHSCDBM) .................................. 213

7.10.4.17 Volt High Scale Gain-Error Calibration Data Buffer LSB (VHSGCDBL) ............... 214

7.10.4.18 Volt High Scale Gain-Error Calibration Data Buffer MSB (VHSGCDBM) ............. 215

7.10.5 ADC Programming Guide................................................................................................... 215

7.11 PWM and SmartAuto Fan Control (PWM) ...................................................................................... 218

7.11.1 Overview............................................................................................................................. 218

7.11.2 Features ............................................................................................................................. 218

7.11.3 Functional Description........................................................................................................ 218

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7.11.3.1 General Description ............................................................................................... 218

7.11.3.2 SmartAuto Fan Control Mode................................................................................ 219

7.11.3.3 Manual Fan Control Mode ..................................................................................... 219

7.11.4 EC Interface Registers ....................................................................................................... 221

7.11.4.1 Channel 0 Clock Prescaler Register (C0CPRS) ................................................... 221

7.11.4.2 Cycle Time Register (CTR) ................................................................................... 222

7.11.4.3 PWM Duty Cycle Register 0 to 7(DCRi) ................................................................ 222

7.11.4.4 PWM Polarity Register (PWMPOL) ....................................................................... 222

7.11.4.5 Prescaler Clock Frequency Select Register (PCFSR) .......................................... 222

7.11.4.6 Prescaler Clock Source Select Group Low(PCSSGL) .......................................... 223

7.11.4.7 Prescaler Clock Source Select Group High(PCSSGh) ......................................... 224

7.11.4.8 Fan 1 Configuration Register (FAN1CNF)............................................................. 225

7.11.4.9 Fan 2 Configuration Register (FAN2CNF)............................................................. 225

7.11.4.10 SmartAuto Fan 1 Speed Range Register (AF1SRR) ............................................ 226

7.11.4.11 SmartAuto Fan 2 Speed Range Register (AF2SRR) ............................................ 226

7.11.4.12 Min/Off PWM Limit Register (MOPL)..................................................................... 226

7.11.4.13 Fan 1 Minimum PWM Duty Cycle Register (F1MPDCR) ...................................... 228

7.11.4.14 Fan 2 Minimum PWM Duty Cycle Register (F2MPDCR) ...................................... 228

7.11.4.15 Fan 1 Temperature LIMIT Register (F1TLIMITR) ................................................. 228

7.11.4.16 Fan 2 Temperature LIMIT Register (F2TLIMITR) ................................................. 228

7.11.4.17 Fan 1 Absolute Temperature LIMIT Register (F1ATLIMITR)................................ 229

7.11.4.18 Fan 2 Absolute Temperature LIMIT Register (F2ATLIMITR)................................ 229

7.11.4.19 Zone Hysteresis Register (ZHYSR)....................................................................... 229

7.11.4.20 Fan 1 Temperature Record Register (F1TRR)...................................................... 230

7.11.4.21 Fan 2 Temperature Record Register (F2TRR)...................................................... 230

7.11.4.22 Fan 1 Tachometer LSB Reading Register (F1TLRR) ........................................... 230

7.11.4.23 Fan 1 Tachometer MSB Reading Register (F1TMRR) ......................................... 230

7.11.4.24 Fan 2 Tachometer LSB Reading Register (F2TLRR) ........................................... 231

7.11.4.25 Fan 2 Tachometer MSB Reading Register (F2TMRR) ......................................... 231

7.11.4.26 Zone Interrupt Status Control Register (ZINTSCR)............................................... 231

7.11.4.27 Zone Temperature Interrupt Enable Register (ZTIER).......................................... 231

7.11.4.28 Channel 4 Clock Prescaler Register (C4CPRS) ................................................... 232

7.11.4.29 Channel 4 Clock Prescaler MSB Register (C4MCPRS)........................................ 232

7.11.4.30 Channel 6 Clock Prescaler MSB Register (C6MCPRS)........................................ 232

7.11.4.31 Channel 6 Clock Prescaler Register (C6CPRS) ................................................... 233

7.11.4.32 Channel 7 Clock Prescaler MSB Register (C7MCPRS)........................................ 233

7.11.4.33 Channel 7 Clock Prescaler Register (C7CPRS) ................................................... 233

7.11.5 PWM Programming Guide ................................................................................................. 234

7.12 EC Access to Host Controlled Modules (EC2I Bridge) ................................................................... 236

7.12.1 Overview............................................................................................................................. 236

7.12.2 Features ............................................................................................................................. 236

7.12.3 Functional Description........................................................................................................ 236

7.12.4 EC Interface Registers ....................................................................................................... 236

7.12.4.1 Indirect Host I/O Address Register (IHIOA)........................................................... 237

7.12.4.2 Indirect Host Data Register (IHD).......................................................................... 237

7.12.4.3 Lock Super I/O Host Access Register (LSIOHA) .................................................. 237

7.12.4.4 Super I/O Access Lock Violation Register (SIOLV)............................................... 238

7.12.4.5 EC to I-Bus Modules Access Enable Register (IBMAE)........................................ 238

7.12.4.6 I-Bus Control Register (IBCTL).............................................................................. 238

7.12.5 EC2I Programming Guide .................................................................................................. 239

7.13 Hardware Strap (HWS) ................................................................................................................... 242

7.13.1 Overview............................................................................................................................. 242

7.13.2 EC Interface Registers ....................................................................................................... 242

7.13.2.1 Hardware Strap Register (HWSR)......................................................................... 242

7.14 External Timer and External Watchdog (ETWD) ............................................................................ 243

7.14.1 Overview............................................................................................................................. 243

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7.14.2 Features ............................................................................................................................. 243

7.14.3 Functional Description........................................................................................................ 243

7.14.3.1 External Timer Operation ...................................................................................... 243

7.14.3.2 External WDT Operation ....................................................................................... 244

7.14.4 EC Interface Registers ....................................................................................................... 244

7.14.4.1 External Timer/WDT Configuration Register (ETWCFG) ...................................... 244

7.14.4.2 External Timer Prescaler Register (ETPSR) ......................................................... 245

7.14.4.3 External Timer Counter High Byte (ETCNTLHR) .................................................. 245

7.14.4.4 External Timer Counter Low Byte (ETCNTLLR) ................................................... 245

7.14.4.5 External Timer/WDT Control Register (ETWCTRL) .............................................. 245

7.14.4.6 External WDT Counter High Byte (EWDCNTLHR) ............................................... 246

7.14.4.7 External WDT Counter (EWDCNTLLR)................................................................. 246

7.14.4.8 External WDT Key Register (EWDKEYR)............................................................. 246

7.14.4.9 Reset Scratch Register (RSTSCR) ....................................................................... 246

7.14.4.10 Chip Version (ECHIPVER) .................................................................................... 247

7.15 Print Port (PP) ................................................................................................................................. 248

7.15.1 Overview............................................................................................................................. 248

7.15.2 Features ............................................................................................................................. 248

7.15.3 Functional Description........................................................................................................ 248

7.15.3.1 KBS Connection with Printer Port Connector........................................................ 248

7.15.3.2 In-System Programming Operation ....................................................................... 248

8. DC Characteristics ..................................................................................................................................... 251

Applied Voltage of VSTBY, VCC, AVCC, VBAT………….. 0.3V to +3.6V .................................................. 251

9. AC Characteristics ..................................................................................................................................... 253

10. Analog Device Characteristics................................................................................................................... 261

11. Package Information.................................................................................................................................. 263

12. Ordering Information.................................................................................................................................. 267

FIGURES

Figure 3-1. Host/Flash and EC/Flash Mapping (General)................................................................................... 6

Figure 3-2. Host/Flash and EC/Flash Mapping (Flash Size = 512k, EC Code = 64k, No User-Defined, a specific

example) ..................................................................................................................................................... 7

Figure 3-3. EC 8032 Data/Code Memory Map.................................................................................................... 9

Figure 5-1. Power State Transitions.................................................................................................................. 23

Figure 5-2. Clock Tree....................................................................................................................................... 31

Figure 5-3. LED connection............................................................................................................................... 37

Figure 6-1. Host View Register Map via Index-Data Pair ................................................................................. 47

Figure 6-2. Program Flow Chart for PNPCFG .................................................................................................. 68

Figure 6-3. Late Write and Early Write.............................................................................................................. 73

Figure 6-4. Fast Read and Normal Read .......................................................................................................... 73

Figure 6-5. Minimum Latency Timing of Flash Memory Read Cycle ................................................................ 74

Figure 6-6. Minimum Latency Timing of Flash Memory Read Cycle in LPC Burst........................................... 75

Figure 6-7. Minimum Latency Timing of Flash Memory Write Cycle ................................................................ 75

Figure 6-8. Wakeup Event and Gathering Scheme .......................................................................................... 86

Figure 6-9. KBRST# Output Scheme................................................................................................................ 89

Figure 6-10. GA20 Output Scheme................................................................................................................... 89

Figure 6-11. KBC Host Interface Block Diagram............................................................................................... 98

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Figure 6-12. IRQ Control in KBC Module.......................................................................................................... 99

Figure 6-13. PMC Host Interface Block Diagram............................................................................................ 105

Figure 6-14. EC Interrupt Request for PMC.................................................................................................... 106

Figure 6-15. IRQ/SCI#/SMI# Control in PMC Compatible Mode .................................................................... 107

Figure 6-16. IRQ/SCI#/SMI# Control in PMC Enhanced Mode ...................................................................... 108

Figure 6-17. Register Map of RTC .................................................................................................................. 117

Figure 7-1. Interrupt Control System Configuration ........................................................................................ 129

Figure 7-2. Interrupt Response Time .............................................................................................................. 131

Figure 7-3. Timer 0/1 in Mode 0 and Mode 1.................................................................................................. 131

Figure 7-4. Timer 0/1 in Mode 2, Auto-Reload................................................................................................ 132

Figure 7-5. Timer 0 in Mode 3 Two 8-bit Timers ............................................................................................. 132

Figure 7-6. Timer 2: Capture Mode................................................................................................................. 134

Figure 7-7. Timer 2: Auto Reload (DECN = 0) ................................................................................................ 135

Figure 7-8. Timer 2: Auto Reload Mode (DECN = 1) ...................................................................................... 135

Figure 7-9. Timer 2: Clock Out Mode.............................................................................................................. 136

Figure 7-10. Watchdog Timer.......................................................................................................................... 137

Figure 7-11. Serial Port Block Diagram........................................................................................................... 138

Figure 7-12. Mode 0 Timing ............................................................................................................................ 139

Figure 7-13. Data Frame (Mode 1, 2 and 3) ................................................................................................... 140

Figure 7-14. Timer 2 in Baud Rate Generator Mode ...................................................................................... 142

Figure 7-15. INTC Simplified Digram .............................................................................................................. 165

Figure 7-16. Program Flow Chart for INTC ..................................................................................................... 166

Figure 7-17. WUC Simplified Digram .............................................................................................................. 172

Figure 7-18. Program Flow Chart for WUC..................................................................................................... 172

Figure 7-19. GPIO Simplified Diagram............................................................................................................ 181

Figure 7-20. ADC Channels Control Diagram................................................................................................. 204

Figure 7-21. ADC Software Calibration Flow .................................................................................................. 216

Figure 7-22. ADC Software Calibration Flow in a Special Case ..................................................................... 217

Figure 7-23. SmartAuto Fan PWM output vs Temperature Reading .............................................................. 219

Figure 7-24. Program Flow Chart for PWM Channel Output .......................................................................... 234

Figure 7-25. Program Flow Chart for SmartAuto Fan Channel Output........................................................... 235

Figure 7-26. Program Flow Chart for EC2I Read............................................................................................ 240

Figure 7-27. Program Flow Chart for EC2I Write............................................................................................ 241

Figure 7-28. Simplified Diagram...................................................................................................................... 243

Figure 7-29. Parallel Port Female 25-Pin Connector ...................................................................................... 248

Figure 9-1. Reset Timing................................................................................................................................. 253

Figure 9-2. Warm Reset Timing ...................................................................................................................... 253

Figure 9-3. Wakeup from Doze Mode Timing ................................................................................................. 253

Figure 9-4. Wake Up from Sleep Mode Timing............................................................................................... 254

Figure 9-5. Asynchronous External Wakeup/Interrupt Source Edge Detected Timing................................... 254

Figure 9-6. LPC and SERIRQ Timing ............................................................................................................. 254

Figure 9-7. SWUC Wake Up Timing .............................................................................................................. 255

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Figure 9-8. Flash Read Cycle Timing............................................................................................................. 255

Figure 9-9. Flash Write Cycle Timing............................................................................................................. 256

Figure 9-10. PWM Output Timing .................................................................................................................. 257

Figure 9-11. PMC SMI#/SCI# Timing............................................................................................................. 257

Figure 9-12. PMC IBF/SCI# Timing ............................................................................................................... 258

Figure 9-13. PS/2 Receive/Transmit Timing .................................................................................................. 258

Figure 9-14. SMBUS Timing .......................................................................................................................... 259

TABLES

Table 3-1. Host/Flash Mapping ........................................................................................................................... 8

Table 3-2. EC/Flash Mapping ............................................................................................................................. 8

Table 3-3. Flash Read/Write Protection Controlled by EC Side ......................................................................... 8

Table 3-4. Flash Read/Write Protection Controlled by Host Side....................................................................... 8

Table 4-1. Pins Listed in Numeric Order (176-pin LQFP) ................................................................................. 14

Table 4-2. Pins Listed in Numeric Order (176-pin TFBGA) .............................................................................. 15

Table 4-3. Pins Listed in Alphabetical Order (176-pin LQFP/TFBGA).............................................................. 16

Table 5-1. Pin Descriptions of LPC Bus Interface............................................................................................. 17

Table 5-2. Pin Descriptions of External Flash Interface.................................................................................... 18

Table 5-3. Pin Descriptions of Keyboard Matrix Scan Interface ....................................................................... 18

Table 5-4. Pin Descriptions of SM Bus Interface .............................................................................................. 18

Table 5-5. Pin Descriptions of PS/2 Interface ................................................................................................... 18

Table 5-6. Pin Descriptions of PWM Interface .................................................................................................. 19

Table 5-7. Pin Descriptions of Wake Up Control Interface ............................................................................... 19

Table 5-8. Pin Descriptions of UART Interface ................................................................................................. 19

Table 5-9. Pin Descriptions of Parallel Port Interface ....................................................................................... 19

Table 5-10. Pin Descriptions of GPIO Interface ................................................................................................ 20

Table 5-11. Pin Descriptions of Hardware Strap............................................................................................... 21

Table 5-12. Pin Descriptions of NC................................................................................................................... 21

Table 5-13. Pin Descriptions of ADC Input Interface ........................................................................................ 21

Table 5-14. Pin Descriptions of DAC Output Interface ..................................................................................... 21

Table 5-15. Pin Descriptions of Clock ............................................................................................................... 22

Table 5-16. Pin Descriptions of Power/Ground Signals.................................................................................... 22

Table 5-17. Power States.................................................................................................................................. 23

Table 5-18. Quick Table of Power Plane for Pins ............................................................................................. 24

Table 5-19. Pin States of LPC Bus Interface .................................................................................................... 24

Table 5-20. Pin States of External Flash Interface............................................................................................ 25

Table 5-21. Pin States of Keyboard Matrix Scan Interface ............................................................................... 25

Table 5-22. Pin States of SM Bus Interface ...................................................................................................... 25

Table 5-23. Pin States of PS/2 Interface........................................................................................................... 25

Table 5-24. Pin States of PWM Interface.......................................................................................................... 26

Table 5-25. Pin States of Wake Up Control Interface ....................................................................................... 26

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Table 5-26. Pin States of UART Interface......................................................................................................... 26

Table 5-27. Pin States of GPIO Interface.......................................................................................................... 26

Table 5-28. Pin States of ADC Input Interface.................................................................................................. 26

Table 5-29. Pin States of DAC Output Interface ............................................................................................... 27

Table 5-30. Pin States of Clock......................................................................................................................... 27

Table 5-31. Reset Sources................................................................................................................................ 29

Table 5-32. Reset Types and Applied Module.................................................................................................. 29

Table 5-33. Clock Types ................................................................................................................................... 30

Table 5-34. Power Saving by EC Clock Operation Mode ................................................................................. 32

Table 5-35. Module Status in Each Power State/Clock Operation ...................................................................33

Table 5-36. Pins with Pull Function................................................................................................................... 34

Table 5-37. Pins with Schmitt-Trigger Function ................................................................................................ 35

Table 5-38. Signals with Open-Drain Function ................................................................................................. 35

Table 6-1. LPC/FWH Response........................................................................................................................ 40

Table 6-2. Host View Register Map, PNPCFG ................................................................................................. 44

Table 6-3. Host View Register Map, Logical Devices ....................................................................................... 45

Table 6-4. Host View Register Map via Index-Data I/O Pair, Standard Plug and Play Configuration Registers46

Table 6-5. Interrupt Request (IRQ) Number Assignment, Logical Device IRQ via SERIRQ ............................ 46

Table 6-6. Logical Device Number (LDN) Assignments ................................................................................... 47

Table 6-7. Host View Register Map via Index-Data I/O Pair, SWUC Logical Device ....................................... 53

Table 6-8. Host View Register Map via Index-Data I/O Pair, KBC / Mouse Interface Logical Device.............. 55

Table 6-9. Host View Register Map via Index-Data I/O Pair, KBC / Keyboard Interface Logical Device ......... 56

Table 6-10. Host View Register Map via Index-Data I/O Pair, SMFI Interface Logical Device ........................ 57

Table 6-11. Host View Register Map via Index-Data I/O Pair, RTC Logical Device......................................... 61

Table 6-12. Host View Register Map via Index-Data I/O, PM1 Logical Device ................................................ 63

Table 6-13. Host View Register Map via Index-Data I/O, PM2 Logical Device ................................................ 64

Table 6-14. Mapped Host Memory Address ..................................................................................................... 70

Table 6-15. M-bus Grant Behavior.................................................................................................................... 72

Table 6-16. EC View Register Map, SMFI ........................................................................................................ 76

Table 6-17. Host View Register Map, SMFI...................................................................................................... 83

Table 6-18. Host View Register Map, SWUC ................................................................................................... 90

Table 6-19. EC View Register Map, SWUC...................................................................................................... 93

Table 6-20. Host View Register Map, KBC ....................................................................................................... 99

Table 6-21. EC View Register Map, KBC ....................................................................................................... 101

Table 6-22. Host View Register Map, PMC .................................................................................................... 108

Table 6-23. EC View Register Map, PMC....................................................................................................... 110

Table 6-24. Host View Register Map, RTC ..................................................................................................... 116

Table 6-25. Host View Register Map via Index-Data I/O Pair, RTC Bank 0 ................................................... 118

Table 6-26. Host View Register Map via Index-Data I/O Pair, RTC Bank 1 ................................................... 118

Table 7-1. 8032 Port Usage ........................................................................................................................... 127

Table 7-2. System Interrupt Table................................................................................................................... 129

Table 7-3. Timer 2 Modes of Operation .......................................................................................................... 136

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IT8510E

Table 7-4. Serial Port Signals.......................................................................................................................... 138

Table 7-5. Selecting the Baud Rate Generator(s)........................................................................................... 141

Table 7-6. Internal RAM Map .......................................................................................................................... 143

Table 7-7. EC View Register Map, INTC ........................................................................................................ 156

Table 7-8. INTC Interrupt Assignments........................................................................................................... 164

Table 7-9. EC View Register Map, WUC ........................................................................................................ 167

Table 7-10. WUC Input Assignments.............................................................................................................. 171

Table 7-11. EC View Register Map, KB Scan................................................................................................. 173

Table 7-12. EC View Register Map, GPIO...................................................................................................... 175

Table 7-13. GPIO Alternate Function.............................................................................................................. 179

Table 7-14. EC View Register Map, ECPM .................................................................................................... 182

Table 7-15. EC View Register Map, SMBUS.................................................................................................. 190

Table 7-16. EC View Register Map, PS/2 ....................................................................................................... 199

Table 7-17. EC View Register Map, DAC ....................................................................................................... 202

Table 7-18. EC View Register Map, ADC ....................................................................................................... 207

Table 7-19. Detail Step of ADC Channel Conversion ..................................................................................... 215

Table 7-20. EC View Register Map, PWM ...................................................................................................... 221

Table 7-21. EC View Register Map, EC2I....................................................................................................... 237

Table 7-22. EC View Register Map, HWS ...................................................................................................... 242

Table 7-23. EC View Register Map, ETWD .................................................................................................... 244

Table 8-1. Power Consumption....................................................................................................................... 252

Table 9-1. Reset AC Table.............................................................................................................................. 253

Table 9-2. Warm Reset AC Table ................................................................................................................... 253

Table 9-3. Wakeup from Doze Mode AC Table .............................................................................................. 254

Table 9-4. Wake Up from Sleep Mode AC Table............................................................................................ 254

Table 9-5. Asynchronous External Wakeup/Interrupt Source Edge Detected AC Table................................ 254

Table 9-6. LPC and SERIRQ AC Table .......................................................................................................... 255

Table 9-7. SWUC Wake Up AC Table ............................................................................................................ 255

Table 9-8. Flash Read Cycle AC Table........................................................................................................... 256

Table 9-9. Flash Write Cycle AC Table........................................................................................................... 256

Table 9-10. PWM Output AC Table ................................................................................................................ 257

Table 9-11. PMC SMI#/SCI# AC Table........................................................................................................... 257

Table 9-12. PMC IBF/SCI# AC Table ............................................................................................................. 258

Table 9-13. PS/2 Receive/Transmit AC Table ................................................................................................ 258

Table 9-14. SMBUS AC Table ........................................................................................................................ 259

Table 10-1. ADC Characteristics..................................................................................................................... 261

Table 10-2. DAC Characteristics..................................................................................................................... 261

www.ite.com.tw IT8510E/TE/G V0.7.2

xiv

s

Feature

1. Features

 8032 Embedded Controller

− Twin Turbo version

− 1 instruction at 1 machine cycle

− Maximum 10 MHz for EC domain and 8032

− Instruction set compatible with standard 8051

 LPC Bus Interface

− Compatible with the LPC specification v1.1

− Supports I/O read/write

− Supports Memory read/write

− Supports FWH read/write

− Serial IRQ

 External Flash Interface

− Up to 4M bytes Flash space shared by the host

and EC side

− 8-bit data bus

 SM Bus Controller

− SM Bus spec. 2.0

− SM Bus host and slave

 System Wake Up Control

− Modem RI# wake up

− Telephone RING# wake up

− IRQ/SMI routing

 EC Wake Up Control

− 32 external/internal wake up events

 Interrupt Controller

− 32 interrupt events to EC

− Fixed priority

 Timer / Watch Dog Timer

− 3 16-bit multi-function timers inside 8032, which

is based on EC clock

− 1 watch dog timer inside 8032, which is based

on EC clock

− 1 external timer in ETWD module, which is

based on RTC clock

− 1 external WDT in ETWD module, which is

based on RTC clock

 UART

− Full duplex UART

− Supports power-switch circuit

− Supports two alarms

 GPIO

− Supports 71-bit GPIO

− Programmable pull up/pull down

− Schmitt trigger for input

 KBC Interface

− 8042 style KBC interface

− Legacy IRQ1 and IRQ12

− Fast A20G and KB reset

 ADC

− 14 ADC channels (10 external)

− 10-bit ADC resolution (accuracy ±4LSB)

− Digital filter for noise reduction

− Conversion time for 14 channels within 100 ms

 DAC

− 4 DAC channels

− 8-bit DAC

 PWM with SmartAuto Fan Control

− 8 PWM channels

− SmartAuto Fan control

− Base clock frequency is 32.768KHz

− 2 Tachometers for measuring fan speed

 PS/2 Interface

− 4 PS/2 interface

− Hardware/Software mode selection

 KB Matrix Scan

− Hardware keyboard scan

− 16x8 keyboard matrix scan

 In-System Programming

− ISP via parallel port interface on existing KBS

connector

− Fast flash programming with software provided

by ITE

 Power Consumption

− Standby with Sleep mode current: 50 µA

 Package

− 176 pin LQFP

 ACPI Power Management Channel

− 2 Power Management channels

− Compatible and enhanced mode

 RTC

− Supports 2 lockable memory areas

www.ite.com.tw IT8510E/TE/G V0.7.2

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ITPM-PN-200514
Specifications subject to Change without Notice By Jimmy Hou, 5/6/2005

This page is intentionally left blank.

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General Description

2. General Description

The IT8510 is a highly integrated embedded controller with system functions suitable for mobile system
applications. The IT8510 directly interfaces to the LPC bus and provides ACPI embedded controller function,
keyboard controller (KBC) and matrix scan, external flash interface for system BIOS and EC code, PWM, ADC
and SmartAuto Fan control for hardware monitor, PS/2 interface for external keyboard/mouse devices, RTC
and system wake up functions for system power management. It also supports the external flash ( or EPROM)
to be shared by the host and EC side.

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4

3. System Block Diagram

3.1 Block Diagram

LPC to I Bus / SERIRQ

Expansion Memory

M Bus

SMFI

Memory Bus

M Bus MUX

PNPCFG Regs

System Block Diagram

I Bus Arbiter RTC

Internal Bus(I Bus)

Print Port

PP

Internal SRAM

(Scratch)

GPIO

Smart-Fan

PWM

PS/2

signaling

EC (8032)

Digital Filter

ADC

EC2IINTC

EC Dedicated Bus (EC Bus)

DAC

EC

Wake-Up Ctrl

SM Bus

KBC SWUC PCM I/F

KB Scan

EC PMU

Clock Gen

ECPM

ETWD

• Host Domain:

LPC, PNPCFG, RTC logic device, host parts of SMFI/SWUC/KBC/PMC logical devices and host parts of
EC2I.

• EC Domain:

EC 8032, INTC, WUC KB Scan, GPIO, ECPM, SMB, PS/2, DAC, ADC, PWM, HWS, ETWD, PP, EC2I, EC
parts of SMFI/SWUC/KBC/PMC and EC parts of EC2I.

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IT8510E

3.2 Host/EC Mapped Memory Space

EC

Code Memory Space

Common Bank

32k
32k

(byte) (byte)

FFFF_FFFFh
FFFF_0000h

FFFE_FFFFh
FFFE_0000h

FFFD_FFFFh

Variable, not necessary
on 32k boundary

1_0000_0000h - Flash_Size

FFFF_FFFFh - Flash_Size

SHMBA+User_Defined_Size-1

SHMBA

000F_FFFFh
000F_0000h

000E_FFFFh
000E_0000h

000D_FFFFh

0000_0000h

Host Memory Space

4G Top Flash Space Top

RANGE 1
RANGE 2

64k

64k

RANGE 3

EC Code:

RANGE 4

Max 160k

Flash_Size

Flash_Size - 1
Flash_Size - 01_0000h

Flash_Size - 01_0001h
Flash_Size - 02_0000h

Flash_Size - 02_0001h

Variable, not necessary
on 32k boundary

00_0000h

Out of Range

These five banks are arragned in order and totally 160K mappe d.

RANGE 1
RANGE 2

RANGE 3

RANGE 4

User_Defined_Size
( Max Flash_Size )

If User_Defined_Size < Flash_Size,
only top of the flash space is mapped,
and the bottom is truncated.

Each bank is always mapped but it is only valid if it is used by EC code.
If EC code size <= 64K, Bank 0 is valid to be selected.
If EC code size <= 96K, Bank 0-1 are valid to be selected.
If EC code size <= 128K, Bank 0-2 are valid to be selected.
If EC code size <= 160K, Bank 0-3 are valid to be selected.
If EC code size is not mutiple of 32K, the remainder can be
used by host memory.

Out of Range

RANGE 1
RANGE 2

64k

64k

Out of Range

Expansion Flash Space

RANGE 1
RANGE 2

RANGE 3

RANGE 4

The range 4 shows space used by EC code and five banks are
all used.
The interface line will be lower if EC code size is smaller than 160K.

(byte)

Bank 3 (32k)
Bank 2 (32k)
Bank 1 (32k)
Bank 0 (32k)
Common Bank (32k)

FFFFh

Bank 0 Bank 1 Bank 3Bank 2
8000h
7FFFh

0000h

Bank 0, 1, 2 and 3 occupy the same code memory space.
Only one of these four banks can be selected at once time.
It is selected by ECBB or P1 register.

Figure 3-1. Host/Flash and EC/Flash Mapping (General)

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System Block Diagram

EC

Code Memory Space

Bank 0

Common Bank

32k
32k

FFFF_FFFFh
FFFF_0000h

FFFE_FFFFh
FFFE_0000h

FFFD_FFFFh

FFF8_FFFFh

FFF8_0000h
FFF7_FFFFh

Host Memory Space

4G Top Flash Space Top

RANGE 1
RANGE 2

RANGE 3

RANGE 4

Out of Range

64k

64k

512k

64k

(byte)(byte)
07_FFFFh
07_0000h

06_FFFFh
06_0000h

05_FFFFh

01_0000hFFF9_0000h
00_FFFFh

00_0000h

Expansion Flash Space

RANGE 1
RANGE 2

RANGE 3

RANGE 4

(byte)

Bank 0 (32k)
Common Bank (32k)

Bank 1-3 are not valid to be selected and are not shown.

FFFFh
8000h

7FFFh
0000h

000F_FFFFh
000F_0000h

000E_FFFFh
000E_0000h

000D_FFFFh

0000_0000h

RANGE 1
RANGE 2

Out of Range

64k

64k

Figure 3-2. Host/Flash and EC/Flash Mapping (Flash Size = 512k, EC Code = 64k, No User-Defined, a
specific example)

The flash memory space is shared between the host side and EC side, and it is shown in Figure 3-1.
An example of 512k flash size, 64k EC code size and no user-defined is shown in Figure 3-2.

The host memory 4G byte top is always mapped into the top of flash space and the host processor fetches the
first instruction after reset at FFFF_FFF0h in the host memory, which is 16 bytes below the uppermost flash
space.

The bottom of EC code is always mapped into the bottom of flash space and EC R8032TT micro-controller
fetches the first instruction after reset at 00_0000h in the EC code memory, which is 1 byte in the lowermost
flash space.

The interface line of host memory and EC code is variable and not necessary on 32k boundary.

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IT8510E

Table 3-1. Host/Flash Mapping

Host Memory Space

on LPC Bus (byte)

(1_0000_0000h–Flash_Size)~
FFFF_FFFFh
SHMBA ~
(SHMBA+User_Defined_Size-1)
000F_0000h ~
000F_FFFFh
000E_0000h ~
000E_FFFFh

Note: The host side can map all flash range regardless of EC code space.
Note: All host mappings are controlled by LPCMEN and FWHEN bit in SHMC register.
Note: Flash Size is defined in FMSSR register, and it may be 128k, 256k, 512k, 1M, 2M and the maximum 4M bytes.
Note: User_Defined_Size is defined in SHMUSZ register.

Expansion Flash Space (byte)

00_0000h~
(Flash_Size-1)
(Flash_Size-User_Defined_Size)~
(Flash_Size-1)
(Flash_Size-01_0000h)~
(Flash_Size-1)
(Flash_Size-02_0000h)~
(Flash_Size-01_0001h)

Mapped

Size

(byte)

Flash_Size

User_Defined_Size

( <= Flash_Size )

64k

64k

Mapping

Condition

Always

USRMEM=1

Always

BIOSEXTS=1

Table 3-2. EC/Flash Mapping

EC Code

Memory Space (byte)

Flash Address Range (byte)

Bank 3: 8000h ~ FFFFh 02_0000h ~ 02_7FFFh 32k Always
Bank 2: 8000h ~ FFFFh 01_8000h ~ 01_FFFFh 32k Always
Bank 1: 8000h ~ FFFFh 01_0000h ~ 01_7FFFh 32k Always
Bank 0: 8000h ~ FFFFh 00_8000h ~ 00_FFFFh 32k Always
Common Bank: 0000h ~ 7FFFh 00_0000h ~ 00_7FFFh 32k Always

Note: EC code can use the maximum 160k by banking.
Note: All EC code memory space is mapped to both EC and host side at the same time. The EC size is not necessary on

32k boundary.

Note: If BSO=1, ECBB is replaced with P1 register of 8032.

ECBB means ECBB field in FECBSR register.
BSO means BSO bit in FPCFG register.

Mapped

Size

(byte)

Mapping

Condition

Bank Selected

Condition

ECBB=11
ECBB=10
ECBB=01
ECBB=00

Always

Table 3-3. Flash Read/Write Protection Controlled by EC Side

Flash Address

Range (byte)

38_0000h ~ 3F_FFFFh ORP56 ~ 63 in SMECORPR9 ORP56 ~ 63 in SMECOWPR9
30_0000h ~ 37_FFFFh ORP48 ~ 55 in SMECORPR8 ORP48 ~ 55 in SMECOWPR8
28_0000h ~ 2F_FFFFh ORP40 ~ 47 in SMECORPR7 ORP40 ~ 47 in SMECOWPR7
20_0000h ~ 27_FFFFh ORP32 ~ 39 in SMECORPR6 ORP32 ~ 39 in SMECOWPR6
18_0000h ~ 1F_FFFFh ORP24 ~ 31 in SMECORPR5 ORP24 ~ 31 in SMECOWPR5
10_0000h ~ 17_FFFFh ORP16 ~ 23 in SMECORPR4 ORP16 ~ 23 in SMECOWPR4
08_0000h ~ 0F_FFFFh ORP8 ~ 15 in SMECORPR3 ORP8 ~ 15 in SMECOWPR3
02_0000h ~ 07_FFFFh ORP2 ~ 7 in SMECORPR2 ORP2 ~ 7 in SMECOWPR2
01_0000h ~ 01_FFFFh ORPLA8~15 in SMECORPR1 ORPLA8 ~ 15 in SMECOWPR1
00_0000h ~ 00_FFFFh ORPLA0 ~ 7 in SMECORPR0 ORPLA0 ~ 7 in SMECOWPR0
All ranges are write-control by

Read Control
Register Bits

Write Control

Register Bits

Note

Each bit controls

64K bytes

Each bit controls

8K bytes

HOSTWA, too.

Table 3-4. Flash Read/Write Protection Controlled by Host Side

Flash Address

Range (byte)

30_0000h ~ 3F_FFFFh HRP in SMHAPR4 HRW in SMHAPR4
20_0000h ~ 2F_FFFFh HRP in SMHAPR3 HRW in SMHAPR3
10_0000h ~ 1F_FFFFh HRP in SMHAPR2 HRW in SMHAPR2
00_0000h ~ 0F_FFFFh HRP in SMHAPR1 HRW in SMHAPR1

Read Control
Register Bits

Write Control

Register Bits

Note

Each index

controls

64K bytes

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3.3 EC Mapped Memory Space

EC Internal EC External EC

Data Memory Space Data Memory Space Code Mem o ry Space

FFFFh

System Block Diagram

(byte)

FFFFh

Scratch ROM 2KB

F800h

FFh

7fh

Direct & Indirect

00h

Indirect SF R

8000h

1F00h

1E00h

1D00h

1C00h

1B00h

1A00h

1900h

1800h

1700h

1600h

1500h

1400h

1300h

1200h

1100h

1000h

0800h

0000h

Reserved

Bank

HW S, ETW D 0,1,2 or 3

ECPM

KB Scan

SM Bus

WUC

DAC

ADC

PW M

PS/2

Be a RAM or ROM

at one time

GPIO

PMC

SW UC

KBC Comm on

EC2I Bank

INT C

SMFI

Reserved

Scratch RAM 2KB

corresponging move corresponging read/write corresponging read

instruction: MOV instruction: MOVX instruction: MOVC

Figure 3-3. EC 8032 Data/Code Memory Map

There is an internal Scratch SRAM which can be located at data space or code space but cannot be located at
both spaces at the same time. Where it is located depends on Scratch SRAM Map Control bit (SSMC) in
FBCFG register. It is called Scratch RAM when being located at data space (default after reset) and called
Scratch ROM when being located at code space.
The EC code space is 64k bytes and physically occupies the maximum 160 k bytes at the bottom of the flash
space. Refer to Figure 3-1 on page 6 for the details.

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IT8510E

3.4 Register Abbreviation

The register abbreviations and access rules are listed as follows:

R READ ONLY. If a register is read only, writing to this register has no effect.
W WRITE ONLY. If a register is write only, reading to this register returns all zero.
R/W READ/WRITE. A register with this attribute can be read and written.
RC READ CLEAR. If a register is read clear, reading to this register clears the register to ‘0’.
R/WC READ/WRITE CLEAR. A register bit with this attribute can be read and written. However,

writing 1 clears the corresponding bit and writing 0 has no effect.

BFNAME@REGNAME This abbreviation may be shown in figures to represent one bit in a register or one

field in a register.

The used radix indicator suffixes in this specification are listed below
Decimal number: "d" suffix or no suffix
Binary number: "b" suffix
Hexadecimal number: "h" suffix

www.ite.com.tw IT8510E/TE/G V0.7.2

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4. Pin Configuration

GPC5

TMRI1/WUI3/GPC6

GPI6

FCS#

176

175

174

45

46

VSS

VSTBY

173

4847505453

GPH0

CLKOUT/GPC0

CK32KOUT/GPC7

LPCPD#/WUI6/GPE6

CLKRUN#/WUI7/GPE7

LPCRST#/WUI4/GPD2

PWRSW/GPE4

FA20/GPG4
FA21/GPG5

GA20/GPB5

KBRST#/GPB6

SERIRQ

LFRAME#

LAD3

LAD2
LAD1

LAD0

VCC
VSS

LPCCLK

WRST#

ECSMI#

PWUREQ#

RI1#/WUI0/GPD0

LPC80HL/GPG6
LPC80LL/GPG7

RI2#/WUI1/GPD1

ECSCI#/GPD3

PWM0/GPA0
PWM1/GPA1

VSTBY

VSS
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/GPA6

GPD4

GINT/GPD5

PWM7/GPA7

WUI5/GPE5

1
2
3
4
5
6
7
8

NC

9
10
11

NC

12

NC

13
14
15
16
17
18
19
20

NC

21

NC

22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

TMRI0/WUI2/GPC4

SMDAT1/GPC2

GPC3

SMCLK1/GPC1

VSS

GPI5

RING#PWRFAIL#/LPCRST#/GPB7

VSTBY

SMDAT0/GPB4

GPB2

SMCLK0/GPB3

CK32KE

VBAT

VSS

VSTBY

CK32K

GP13

GP14

TXD/GPB1

GP12

RXD/GPB0

FRD#

FWR#

GPI1

FD7

GPI0

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

IT8510

E

Pinout

Top View

52

51

49

KSO2/PD2

KSO0/PD0

KSO1/PD1

56

55

GPH1

GPH2

KSO6/PD6

KSO5/PD5

KSO4/PD4

KSO3/PD3

59

585760

KSO7/PD7

KSO8/ACK#

62

61

646366

65

KSO14

KSO10/PE

KSO9/BUSY

KSO13

KSO12/SLCT

KSO11/ERR#

TACH1/GPD7

TACH0/GPD6

69

686770

GPH3

KSO15

72

71

747376

GPH4

KSI2/INIT#

KSI0/STB#

KSI1/AFD#

KSI3/SLIN#

Pin Configuration

FD5

FD6

FD4

FA9

FA8

FD2

FD3

FD1

VSS

FD0

VSTBY

FA11

FA10

FA7

146

145

144

143

142

141

140

139

138

137

136

135

134

133

82

81

79

787780

75

KSI6

KSI7

KSI4

KSI5

GPH6

GPH5

8483868887

85

NC

ADC3NCADC1

ADC2

ADC0

ADC4/GPE0

ADC5/GPE1

132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89

FA6
FA5/SHBM
FA12
FA13
FA4/PPEN
FA3/BADDR1
FA2/BADDR0
FA1
FA0
VSTBY
VSS
FA14
FA15
PS2DAT3/GPF7
PS2CLK3/GPF6
PS2DAT2/GPF5
PS2CLK2/GPF4
PS2DAT1/GPF3
PS2CLK1/GPF2
FA16/GPG0
FA17/GPG1
PS2DAT0/GPF1
PS2CLK0/GPF0
NC
NC
NC
NC
GPH7
FA18/GPG2
FA19/GPG3
DAC3
DAC2
DAC1
DAC0
NC
NC
AVSS
AVCC
ADC9
ADC8
NC
NC
ADC7/GPE3
ADC6/GPE2

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IT8510E

IT8510G Top View

12345678910111213141516

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

TMRI1/

WU I3/G P C 6

CK32KOUT/

GPC7

FA2 0/GPG 4

CLKRUN#/

WU I7/G P E 7

LPC80LL/

GPG7

ECSCI#/

GPD3

PWM1/

GPA1

PWM3/

GPA3

PWM6/

GPA6

PWM7/

GPA7

WU I5/G P E 5

GPI6

GPC5 FA11FD1FD3 FA6GPC3FCS #

PWRSW/

GPE4

LAD3SERIRQ

LAD2LFRAME#

LAD0LAD1

VCCVCC

ECSMI#NC

RI1#/WUI0/

GPD0

RI2#/WUI1/

GPD1

PWM0/

GPA0

PWM2/

GPA2

PWM5/

GPA5

GINT/GPD5

GPH0

CLKOUT/

GPC0

TMRI0/

WU I2 /GP C4

SMDAT1/

GPC2

RING#/PWRFAIL#/

LPC RS T#/GPB 7

GPI5

FA2 1/GPG 5

KBRST#/

GPB6

LPCPD#/

WU I6/G P E 6

LPCRST#/

WU I4 /GP D2

PWM4/

GPA4

SMDAT0/

GPB4

SMCLK1/

GPC1

LPC80H L/

GPG6

KSO9/BUSYGPD4

KSO6/PD6KSO4/PD4

KSO7/PD7GPH2KSO3/PD3KSO0/PD0

SMCLK0/

GPB3

KSO11/

ERR#

TACH1/

GPD7

TACH0/

GPD6

KSO12/

SLCT

GPI1TXD/GPB1GP I4GPB2

FWR#GP I2GP I3

GPI0VSTBYVSTBYLPCCLKGA20/GPB5

PS2DAT3/

VSSVSTBYVSBTBYVSTBYPWUREQ#WRS T#

VSSVSSVSSVSTBY

FA1 7/GPG 1

VSSVSSVSSVSTBYKSO5/PD5

PS2CLK0/

VSSVSSVSSVSTBYVSTBY

KSI5KSI3/SLIN#KSO15

GPH6KSI0/STB#KSO14

KSI2/INIT# KSI4

KSI1/AFD#

FD7

FD6

FD4

GPF7

VSS

GPF0

GPH5

FA8

FA9

FA12FD5

FA3/

BADDR1

PS2CLK3/

GPF6

PS2DAT1/

GPF3

PS2DAT0/

GPF1

GPH7

FA1 9/GPG 3FA 18/GP G2

KSI7KSI6

FA10FD0FD2 FA7FRD#RXD/GPB0CK32KCK32KEVBAT

FA13FA5/SHBM

FA2FA4/PPEN

FA0FA 1

FA15FA 14

PS2CLK2/

PS2DAT2/

GPF4

GPF5

PS2CLK1/

FA16 /GPG0

GPF2

DAC3DAC2

DAC1DAC0

AVSSAVSS

AVCCAVCC

ADC8ADC9

NCNC

NCADC3ADC1 ADC6/GPE2GPH4KSO13KSO10/PEKSO8/ACK#GPH1KSO2/PD2KSO1/PD1

NCADC2ADC0 ADC4/GPE0GPH3

ADC7/GPE3

ADC5/GPE1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

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12

IT8510G Bottom View

Pin Configuration

12345678910111213141516

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

FA10 FD0 FD2FA7 FRD# RXD/GPB0 CK32K CK32KE VBAT

FA1 3 FA5/S HB M

FA2 FA4/PPEN

FA0 FA 1

FA1 5 FA 14

PS2CLK2/

PS2DAT2/

GPF4

GPF5

PS2CLK1/

FA1 6/GPG 0

GPF2

DAC3 DAC2

DAC1 DAC0

AVSS AVSS

AVCC AVCC

ADC8 ADC9

NC NC

ADC7/GPE3

ADC5/GPE1

NC ADC3 ADC1ADC6/GPE2 GPH4 KSO13 KSO10/PE KSO8/ACK# GPH1 KSO2/PD2 KSO1/PD1

NC ADC2 ADC0ADC4/GPE0 GPH3

FA8

FD7

FA9

FD6

FA12 FD5

FA3 /

FD4

BADDR1

PS2CLK3/

PS2DAT3/

GPF6

GPF7

PS2DAT1/

VSS

GPF3

PS2DAT0/

FA1 7/GPG 1

GPF1

PS2CLK0/

GPH7

GPF0

FA19/GPG3FA18/GPG2

KSI7 KSI6

GPH5

GPI1 TX D/GPB1 GPI4 GP B2

FWR# GPI2 GP I3

GPI0 VSTBY VSTBY LPCCLK GA20/GPB5

VSS VSTBY VSBTBY VSTBY PWUREQ# WRST#

VSS VSS VSS VSTBY

VSS VSS VSS VSTBY KSO5/PD5

VSS VSS VSS VSTBY VSTBY

KSI5 KSI3/SLIN# KSO15

GPH6 KSI0/STB# KSO14

KSI2/INIT#KSI4

KSI1/AFD#

KSO12/

SLCT

SMCLK0/

GPB3

KSO11/

ERR#

TACH1/

GPD7

TACH0/

GPD6

RING#/PWRFAIL#/

LPC RS T#/GPB 7

SMDAT0/

GPI5

GPB4

SMCLK1/

FA2 1/GPG 5

GPC1

KBRST#/

GPB6

LPC80H L/

LPCPD#/

GPG6

WU I6/G P E 6

LPCRST#/

WU I4/G P D 2

PWM4/

GPA4

KSO9/BUSY GPD4

KSO6/PD6 KSO4/PD4

KSO7/PD7 GPH2 KSO3/PD3 KSO0/PD0

SMDAT1/

GPC2

TMRI0/

WU I2/G P C 4

GPI6

WU I3 /GP C6

CK32KOUT/

GPC5FA11 FD1 FD3FA6 GPC3 FCS#

PWRSW/

FA20 /GPG4

GPE4

LAD3 SERIRQ

LAD2 LFRAME#

LAD0 LA D1

VCC VCC

ECSMI# NC

RI1#/WUI0/

CLKRUN#/

GPD0

WU I7 /GP E7

RI2#/WUI1/

GPD1

PWM0/

GPA0

PWM2/

GPA2

PWM5/

GPA5

GINT/GPD5

GPH0

CLKOUT/

WU I5 /GP E5

GPC0

TMRI1/

GPC7

LPC80LL/

GPG7

ECSCI#/

GPD3

PWM1/
GPA1

PWM3/

GPA3

PWM6/

GPA6

PWM7/

GPA7

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

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IT8510E

Table 4-1. Pins Listed in Numeric Order (176-pin LQFP)[u5]

Pin Signal Pin Signal Pin Signal Pin Signal

CK32KOUT/GPC

1

7

45 VSTBY 89 ADC6/GPE2 133 FA7

2 PWRSW/GPE4 46 VSS 90 ADC7/GPE3 134 FA11
3 FA20/GPG4 47 CLKOUT/GPC0 91 NC 135 FA10
4 FA21/GPG5 48 GPH0 92 NC 136 VSTBY
5 GA20/GPB5 49 KSO0/PD0 93 ADC8 137 VSS
6 KBRST#/GPB6 50 KSO1/PD1 94 ADC9 138 FD0
7 SERIRQ 51 KSO2/PD2 95 AVCC 139 FD1
8 NC 52 KSO3/PD3 96 AVSS 140 FD2

9 LFRAME# 53 KSO4/PD4 97 NC 141 FD3
10 LAD3 54 GPH1 98 NC 142 FA9
11 NC 55 GPH2 99 DAC0 143 FA8
12 NC 56 KSO5/PD5 100 DAC1 144 FD4
13 LAD2 57 KSO6/PD6 101 DAC2 145 FD5
14 LAD1 58 KSO7/PD7 102 DAC3 146 FD6
15 LAD0 59 KSO8/ACK# 103 FA19/GPG3 147 FD7
16 VCC 60 KSO9/BUSY 104 FA18/GPG2 148 GPI0
17 VSS 61 KSO10/PE 105 GPH7 149 GPI1
18 LPCCLK 62 TACH0/GPD6 106 NC 150 FRD#
19 WRST# 63 TACH1/GPD7 107 NC 151 FWR#
20 NC 64 KSO11/ERR# 108 NC 152 GPI2
21 NC 65 KSO12/SLCT 109 NC 153 RXD/GPB0
22 ECSMI# 66 KSO13 110 PS2CLK0/GPF0 154 TXD/GPB1
23 PWUREQ# 67 KSO14 111 PS2DAT0/GPF1 155 GPI3

LPCPD#/WUI6/

24

GPE6
CLKRUN#/WUI7/

25

GPE7

68 KSO15 112 FA17/GPG1 156 GPI4

69 GPH3 113 FA16/GPG0 157 VSTBY

26 RI1#/WUI0/GPD0 70 GPH4 114 PS2CLK1/GPF2 158 CK32K
27 LPC80HL/GPG6 71 KSI0/STB# 115 PS2DAT1/GPF3 159 VSS
28 LPC80LL/GPG7 72 KSI1/AFD# 116 PS2CLK2/GPF4 160 CK32KE
29 RI2#/WUI1/GPD1 73 KSI2/INIT# 117 PS2DAT2/GPF5 161 VBAT

LPCRST#/WUI4/

30

GPD2

74 KSI3/SLIN# 118 PS2CLK3/GPF6 162 GPB2

31 ECSCI#/GPD3 75 GPH5 119 PS2DAT3/GPF7 163 SMCLK0/GPB3
32 PWM0/GPA0 76 GPH6 120 FA15 164 SMDAT0/GPB4

RING#/

33 PWM1/GPA1 77 KSI4 121 FA14 165

PWRFAIL#/

LPCRST#/GPB7
34 VSTBY 78 KSI5 122 VSS 166 VSTBY
35 VSS 79 KSI6 123 VSTBY 167 VSS
36 PWM2/GPA2 80 KSI7 124 FA0 168 GPI5
37 PWM3/GPA3 81 ADC0 125 FA1 169 SMCLK1/GPC1
38 PWM4/GPA4 82 ADC1 126 FA2/BADDR0 170 SMDAT1/GPC2
39 PWM5/GPA5 83 ADC2 127 FA3/BADDR1 171 GPC3

40 PWM6/GPA6 84 ADC3 128 FA4/PPEN 172

TMRI0/WUI2/

GPC4
41 GPD4 85 NC 129 FA13 173 FCS#
42 GINT/GPD5 86 NC 130 FA12 174 GPI6
43 PWM7/GPA7 87 ADC4/GPE0 131 FA5/SHBM 175 GPC5

44 WUI5/GPE5 88 ADC5/GPE1 132 FA6 176

TMRI1/WUI3/

GPC6

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s

Pin Description

Table 4-2. Pins Listed in Numeric Order (176-pin TFBGA)

Pin Signal Pin Signal Pin Signal Pin Signal

TMRI1/WUI3/GPC

A1

6
A10 FRD# E16 FA0 J10 VSS M7 TACH1/GPD7
A11 FD7 E2 LAD2 J11 FA17/GPG1 M8 KSO14
A12 FA8 E5 FA21/GPG5 J12 PS2DAT0/GPF1 M9 KSI0/STB#
A13 FD2 E6 SMCLK1/GPC1 J15 DAC2 N1 PWM3/GPA3
A14 FD0 E7 SMCLK0/GPB3 J16 DAC3 N15 ADC9
A15 FA10 E8 GPI3 J2 RI1#/WUI0/GOD0 N16 ADC8

A16 FA7 E9 GPI2 J5

A2 GPI6 F1 LAD1 J6 KSO5/PD5 P1 PWM6/GPA6

TMRI0/WUI2/GPC

A3

4

A4 SMDAT1/GPC2 F11 FD4 J8 VSS P16 NC

RING#/PWRFAIL/

A5

#/LPCRST#/GPB7 F12 FA3/BADDR1 J9 VSS P2 GINT/GPD5

A6 VBAT F15 FA14 K1 LPC80LL/GPG7 R1 PWM7/GPA7
A7 CK32KE F16 FA15 K10 VSS R10 KSI2/INT#
A8 CK32KE F2 LAD0 K11 PS2CLK0/GPF0 R11 KSI4
A9 RXD/GPB0 F5 KBRST#/GPB6 K12 GPH7 R12 ADC1

CK32KOUT/GPC

B1

7
B10 GPI1 F7 LPCCLK K16 DAC1 R14 NC
B11 FD6 F8 VSTBY K2 RI2#/WUI1/GPD1 R15 ADC6/GPE2
B12 FA9 F9 VSTBY K5 PWM4/GPA4 R16 ADC7/GPE3
B13 FD3 G1 VCC K6 VSTBY R2 GPH0
B14 FD1 G10 VSS K7 VSTBY R3 KSO1/PD1
B15 FA11 G11 PS2DAT3/GPF7 K8 VSS R4 KSO2/PD2
B16 FA6 G12 PS2CLK3/GPF6 K9 VSS R5 GPH1

B2 GPC5 G15 PS2DAT2/GPF5 L1 ECSCI#/GPD3 R6 KSO8/ACK#
B3 FCS# G16 PS2CLK2/GPF4 L10 KSI5 R7 KSO10/PE
B4 GPC3 G2 VCC L11 FA18/GPG2 R8 KSO13
B5 GPI5 G5 WRST# L12 FA19/GPG3 R9 GPH4
B6 SMDAT0/GPB4 G6 PWUREQ# L15 AVSS T1 WUI5/GPE5
B7 GPB2 G7 VSTBY L16 AVSS T10 KSI1/AFD#
B8 GPI4 G8 VSTBY L2 PWM0/GPA0 T11 GPH5
B9 TXD/GPB1 G9 VSTBY L5 GPD4 T12 ADC0

C1 FA20/GPG4 H1 NC L6 KSO9/BUSY T13 ADC2
C15 FA5/SHBM H10 VSS L7 KSO11/ERR# T14 NC
C16 FA13 H11 VSS L8 KSO15 T15 ADC4/GPE0

C2 PWRSW/GPE4 H12 PS2DAT1/GPF3 L9 KSI3/SLIN# T16 ADC5/GPE1

D1 SERIRQ H15 PS2CLK1/GPF2 M1 PWM1/GPA1 T2 CLKOUT/GPC0
D15 FA4/PPEN H16 FA16/GPG0 M10 GPH6 T3 KSO0/PD0
D16 FA2 H2 ECSMI# M11 KSI6 T4 KSO3/PD3

D2 LAD3 H5

E1 LFRAME# H6 LPC80HL/GPG6 M15 AVCC T6 KSO7/PD7
E10 FWR# H7 VSTBY M16 AVCC T7 TACH0/GPD6
E11 FD5 H8 VSS M2 PWM2/GPA2 T8 KSO12/SLCT
E12 FA12 H9 VSS M5 KSO4/PD4 T9 GPH3

E15 FA1 J1

F10 GPI0 J7 VSTBY P15 NC

F6 GA20/GPB5 K15 DAC0 R13 ADC3

LPCPD#/WUI6/G
PE6

M12 KSI7 T5 GPH2

CLKRUN#/WUI7/
GPE7

LPCRST#/WUI4/
GPD2

M6 KSO6/PD6

N2 PWM5/GPA5

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IT8510E

Table 4-3. Pins Listed in Alphabetical Order (176-pin LQFP/TFBGA)

Signal Pin Signal Pin Signal Pin Signal Pin

ADC0 81/T12 FA9 142/B12 KSI5 78/L10 PS2DAT1/GPF3 115/H12
ADC1 82/R12 FCS# 173/B3 KSI6 79/M11 PS2DAT2/GPF5 117/G15
ADC2 83/T13 FD0 138/A14 KSI7 80/M12 PS2DAT3/GPF7 119/G11
ADC3 84/R13 FD1 139/B14 KSO0/PD0 49/T3 PWM0/GPA0 32/L2
ADC4/GPE0 87/T15 FD2 140/A13 KSO1/PD1 50/R3 PWM1/GPA1 33/M1

ADC5/GPE1 88/T16 FD3 141/B13 KSO10/PE 61/R7 PWM2/GPA2 36/M2

ADC6/GPE2 89/R15 FD4 144/F11 KSO11/ERR# 64/L7 PWM3/GPA3 37/N1
ADC7/GPE3 90/R16 FD5 145/E11 KSO12/SLCT 65/T8 PWM4/GPA4 38/K5
ADC8 93/N16 FD6 146/B11 KSO13 66/R8 PWM5/GPA5 39/N2
ADC9 94/N15 FD7 147/A11 KSO14 67/M8 PWM6/GPA6 40/P1

AVCC

AVSS

CK32K 158/A8 GA20/GPB5 5/F6 KSO3/PD3 52/T4 PWUREQ# 23/G6
CK32KE 160/A7 GINT/GPD5 42/P2 KSO4/PD4 53/M5 RI1#/WUI0/GPD0 26/J2
CK32KOUT/GP
C7

CLKOUT/GPC0 47/T2 GPC3 171/B4 KSO6/PD6 57/M6

CLKRUN#/WUI7
/GPE7
DAC0 99/K15 GPD4 41/L5 KSO8/ACK# 59/R6 SERIRQ 7/D1
DAC1 100/K16 GPH0 48/R2 KSO9/BUSY 60/L6 SMCLK0/GPB3 163/E7
DAC2 101/J15 GPH1 54/R5 LAD0 15/F2 SMCLK1/GPC1 169/E6
DAC3 102/J16 GPH2 55/T5 LAD1 14/F1 SMDAT0/GPB4 164/B6
ECSCI#/GPD3 31/L1 GPH3 69/T9 LAD2 13/E2 SMDAT1/GPC2 170/A4
ECSMI# 22/H2 GPH4 70/R9 LAD3 10/D2 TACH0/GPD6 62/T7
FA0 124/E16 GPH5 75/T11 LFRAME# 9/E1 TACH1/GPD7 63/M7
FA1 125/E15 GPH6 76/M10 LPC80HL/GPG6 27/H6 TMRI0/WUI2/GPC4 172/A3
FA10 135/A15 GPH7 105/K12 LPC80LL/GPG7 28/K1 TMRI1/WUI3/GPC6 176/A1
FA11 134/B15 GPI0 148/F10 LPCCLK 18/F7 TXD/GPB1 154/B9

FA12 130/E12 GPI1 149/B10

FA13 129/C16 GPI2 152/E9

FA14 121/F15 GPI3 155/E8 NC 91/P16
FA15 120/F16 GPI4 156/B8 NC 92/P15
FA16/GPG0 113/H16 GPI5 168/B5 NC 21/H1
FA17/GPG1 112/J11 GPI6 174/A2 NC 85/T14
FA18/GPG2 104/L11 GPJ0 8/ NC 86/R14
FA19/GPG3 103/L12 GPJ1 11/

FA2/BADDR0 126/D16 GPJ2 12/

FA20/GPG4 3/C1 GPJ3 20/
FA21/GPG5 4/E5 GPJ4 21/

FA3/BADDR1 127/F12

FA4/PPEN 128/D15 KSI0/STB# 71/M9 PS2CLK0/GPF0 110/K11
FA5/SHBM 131/C15 KSI1/AFD# 72/T10 PS2CLK1/GPF2 114/H15
FA6 132/B16 KSI2/INIT# 73/R10 PS2CLK2/GPF4 116/G16 VSTBY 157/F8
FA7 133/A16 KSI3/SLIN# 74/L9 PS2CLK3/GPF6 118/G12 WRST# 19/G5
FA8 143/A12 KSI4 77/R11 PS2DAT0/GPF1 111/J12 WUI5/GPE5 44/T1

95/

M15,M16

96/

L15,L16

FRD# 150/A10 KSO15 68/L8 PWM7/GPA7 43/R1

FWR# 151/E10 KSO2/PD2 51/R4 PWRSW/GPE4 2/C2

1/B1 GPB2 162/B7 KSO5/PD5 56/J6 RI2#/WUI1/GPD1 29/K2

RING#/PWRFAIL#/
LPCRST#/GPB7

165/A5

25/J1 GPC5 175/B2 KSO7/PD7 58/T7 RXD/GPB0 153/A9

LPCPD#/WUI6/G
PE6
LPCRST#/WUI4/
GPD2

24/H5 VBAT 161/A6

30/J5 VCC

G1,G2
122,137,
159,167,
17,35,46

VSS

/G10,H1
0,H11,H

8,H9,J10

,J8,J9,K

10,K8,K9

123,136,
166,34,4
5/F9,G7,
G8,G9,H

KBRST#/GPB
6

6/F5

NC

98,

106-109

VSTBY

7,J7,K6,

16/

K7

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5. Pin Descriptions

5.1 Pin Descriptions
Table 5-1. Pin Descriptions of LPC Bus Interface

Pin(s) No. Signal Attribute Description

LPC Bus Interface (3.3V CMOS I/F, 5V tolerant)

165 or 30 LPCRST#

18 LPCCLK

10, 13-15 LAD[3:0]

9 LFRAME#
24 LPCPD#
25 CLKRUN#

7 SERIRQ
22 ECSMI#

31 ECSCI#

5 GA20

6 KBRST#

19 WRST#

23 PWUREQ#

27 LPC80HL

28 LPC80LL

IK LPC Hardware Reset

LPC hardware reset will reset LPC interface and host side modules. The
source is determined by EC side register bit LPCRSTEN.
This pin can be omitted if external LPC reset is not required.

PI LPC Clock

33 MHz clock for LPC domain functions.

PIO LPC Address Data

PI LPC LFRAME# Signal
IO2 LPC LPCPD# Signal
IO6 LPC CLKRUN# Signal
PIO SERIRQ Signal

O8 EC SMI# Signal

This is SMI# signal driven by SWUC module.

O8 EC SCI# Signal

This is SCI# signal driven by PMC module.

IO2 Gate A20 Signal

This is GA20 signal driven by SWUC module.

IO2 KB Reset Signal

This is KBRST# signal driven by SWUC module.

IK Warm Reset

For EC domain function reset after power up.

O2 System Power On Request

This is PWUREQ# signal driven by SWUC module.

O4 LPC I/O Port 80, High-nibble LAD Latch

An active high signal to latch Port 80 high-nibble for the debug
purpose.

O4 LPC I/O Port 80, Low-nibble LAD Latch

An active high signal to latch Port 80 low-nibble for the debug
purpose.

Pin Description

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IT8510E

Table 5-2. Pin Descriptions of External Flash Interface

Pin(s) No. Signal Attribute Description

Flash Interface (3.3V CMOS I/F, 5V tolerant)

120-121,
129-130,
134-135,
142-143,
133-131,

128-124

3-4,

103-104,

112-113

147-144,

141-138

150 FRD#

151 FWR#

173 FCS#

FA[15:0]

FA[21:16]

FD[7:0]

O4 Flash Address [15:0]

These are dedicated external Flash address pins. In addition to being the
Flash address output, FA[5:2] serve as hardware strap pins described
below.
FA[5] : SHBM, shared BIOS mode enable.
FA[4] : PPEN, enable in-system programming via parallel port interface
FA[3] : BADDR[1], used in PNPCFG base address.
FA[2] : BADDR[0], used in PNPCFG base address.

IOK4 Flash Address [21:16]/Alternate GPIO

These pins can be used as GPIO pins depending on the external Flash
size.

IOK4 Flash Data [7:0]

Flash data bus.

O4 Flash Read

Flash read control.

O4 Flash Write

Flash write control.

O4 Flash Chip Select

FCS# is the external Flash chip select.

Table 5-3. Pin Descriptions of Keyboard Matrix Scan Interface

Pin(s) No. Signal Attribute Description

KB Matrix Interface (3.3V CMOS I/F, 5V tolerant)

68-64,
61-56,

53-49

80-77,

74-71

KSO[15:0]

KSI[7:0]

O8 Keyboard Scan Output

Keyboard matrix scan output.

IK Keyboard Scan Input

Keyboard matrix scan input for switch based keyboard.

Table 5-4. Pin Descriptions of SM Bus Interface

Pin(s) No. Signal Attribute Description

SM Bus Interface (3.3V CMOS I/F, 5V tolerant)

169, 163 SMCLK[1:0]

170, 164 SMDAT[1:0]

IOK2 SM Bus CLK

2 SM bus interface provided.
SMCLK0-1 correspond to channel A and B, respectively.

IOK2 SM Bus Data

2 SM bus interface provided.
SMDAT0-1 correspond to channel A and B, respectively.

Table 5-5. Pin Descriptions of PS/2 Interface

Pin(s) No. Signal Attribute Description

PS/2 Interface (3.3V CMOS I/F, 5V tolerant)

118, 116,
114, 110,

119, 117
115, 111

PS2CLK[3:0]

PS2DAT[3:0]

IOK8 PS/2 CLK

4 sets of PS/2 interface, alternate function of GPIO.
PS2CLK0-3 correspond to channel 1-4, respectively.

IOK8 PS/2 Data

4 sets of PS/2 interface, alternate function of GPIO.
PS2DAT0-3 correspond to channel 1-4, respectively.

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Table 5-6. Pin Descriptions of PWM Interface

Signal Pin(s) No. Attribute Description

PWM Interface (3.3V CMOS I/F, 5V tolerant)

43, 40-36,

33-32

63-62 TACH[1:0]

176,172 TMRI[1:0]

PWM[7:0]

IOK8 Pulse Width Modulation Output

Two of the eight PWM outputs can be selected as SmartAuto fan control if
enabled. Others are general-purpose PWM signals.
PWM0-7 correspond to channel 0-7, respectively.

IOK2 Tachometer Input

TACH[1:0] are tachometer inputs from external fans. They are used for
measuring the external fan speed.

IOK2 Counter Input

TMRI[1:0] are timer/counter input signals connected to timer2 and timer1 of

8032. Notice that the frequency must be slower than 8032 clock to be
sampled.

Table 5-7. Pin Descriptions of Wake Up Control Interface

Pin(s) No. Signal Attribute Description

Wake Up Control Interface (3.3V CMOS I/F, 5V tolerant)

25-24,

44, 30,

176, 172,

29, 26

2 PWRSW

29,26 RI[2:1]#

165 RING#

WUI[7:0]

IOK2-8 EC Wake Up Input

Supplied by VSTBY, used for EC wake up.

IOK2 Power Switch Input

Supplied by VSTBY, used to indicate the status of power switch.

IOK4 Ring Indicator Input

Supplied by VSTBY, used for system wake up.

IOK2 Telephone Line Ring Input

Supplied by VSTBY, used for system wake up.

Table 5-8. Pin Descriptions of UART Interface

Pin(s) No. Signal Attribute Description

UART Interface (3.3V CMOS I/F, 5V tolerant)

154 TXD

153 RXD

IOK2 UART TX Output

UART TX Output from 8032

IOK2 UART RX Input

UART RX Input from 8032

Table 5-9. Pin Descriptions of Parallel Port Interface

Pin(s) No. Signal Attribute Description

ADC Interface (3.3V CMOS I/F)

65 SLCT
61 PE
60 BUSY
59 ACK#
74 SLIN#
73 INIT#
64 ERR#
72 AFD#
71 STB#

58-56,53-4

9

PD[7:0]

O8 Printer Select
O8 Printer Paper End
O8 Printer Busy
O8 Printer Acknowledge

IK Printer Select Input

IK Printer Initialize

O8 Printer Error

IK Printer Auto Line Feed

IK Printer Strobe

O8 Parallel Port Data[7:0]

Pin Description

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IT8510E

Table 5-10. Pin Descriptions of GPIO Interface

Pin(s) No. Signal Attribute Description

GPIO Interface (3.3V CMOS I/F, 5V tolerant)

A: 43,

40-36,

33-32

B: 165

6-5,

164-162,

154-153

C: 1,
176-175,
172-169,

47

D: 63-62,

42-41,

31-29, 26

E: 25-24,

44, 2,

90-87

F:

119-114,

111-110

G: 28-27,

4-3,

103-104,

112-113

H: 105,

76-75,
70-69,

55-54, 48

I: 174,

168,

156-155,

152,

149-148

42 GINT

GPA[7:0],
GPB[7:0],
GPC[7:0],
GPD[7:0],
GPE[7:0],
GPF[7:0],
GPG[7:0],
GPH[7:0],

GPI[6:0]

IOK

Refer to

Table 7-13

on page

179 for

output

driving

capability

IK General Purpose Interrupt

GPIO Signals

The 71 GPIO pins are divided into 9 groups. Each of them contains 8 GPIO
pins. Some GPIO pins have alternative function.

GPI5 may be used by power supply control and it is only reset by VSTBY
Power-Up Reset and Watchdog Reset.

General Purpose Interrupt directly input to INT28 of INTC.

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Table 5-11. Pin Descriptions of Hardware Strap

Pin(s) No. Signal Attribute Description

Hardware Strap (3.3V CMOS I/F, 5V tolerant)

131 SHBM

128 PPEN

127,126 BADDR[1:0]

I Share Host BIOS Memory Configuration

Sampled at VSTBY power up reset.
No pull resistor: disable shared memory with host BIOS
External 10K ohm pull up resistor: enable shared memory with host BIOS

I Parallel Port Enable

Sampled at VSTBY power up reset.
No pull resistor:

Normal.

External 10K ohm pull up resistor:

KBS interface pins are switched to parallel port interface for in-system

programming.

I I/O Base Address Configuration

Sampled at VSTBY power up reset.
No pull resistor:

The register pair to access PNPCFG is 002Eh and 002Fh.

10K ohm external pull-up resistor on BADDR0:

The register pair to access PNPCFG is 004Eh and 004Fh.

10K ohm external pull-up resistor on BADDR1:

The register pair to access PNPCFG is determined by EC domain

registers SWCBALR and SWCBAHR.

Table 5-12. Pin Descriptions of NC

Pin(s) No. Signal Attribute Description

NC (3.3V CMOS I/F, 5V tolerant)

8, 11, 12,

85,

86, 91, 92,

97,

98,106-10

9

NC

- NC

Don’t connect it to any nets, or tie to digital ground.
For IT8510G, it’s recommend to reserve test pads on PCB for pin H1, R14,
T14, P15 and P16.

Table 5-13. Pin Descriptions of ADC Input Interface

Pin(s) No. Signal Attribute Description

ADC Interface (3.3V CMOS I/F)

84-81 ADC[3:0]

90-87 ADC[7:4]

93 ADC[8]
94 ADC[9]

AI ADC Input

Dedicated ADC input pins.

AIO2 ADC Input/Alternate GPIO

These 4 ADC inputs can be used as GPIO pins depending on the ADC
channels required.

AI ADC Input
AI ADC Input

Table 5-14. Pin Descriptions of DAC Output Interface

Pin(s) No. Signal Attribute Description

DAC Interface (3.3V CMOS I/F)

102-99 DAC[3:0]

O DAC Output

Pin Description

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IT8510E

Table 5-15. Pin Descriptions of Clock

Pin(s) No. Signal Attribute Description

Clock Interface (3.3V CMOS I/F)

158 CK32K

OSCI 32.768K Hz Crystal X1

It is connected to internal crystal oscillator.

160 CK32KE

OSCIO 32.768K Hz Crystal X2

It is connected to internal crystal oscillator.

1 CK32KOUT

47 CLKOUT

O4 32.768K Hz Oscillator Output

32.768 KHz clock output.

O2 EC Clock Output

EC domain clock output.

Table 5-16. Pin Descriptions of Power/Ground Signals

Pin(s) No. Signal Attribute Description

Power Ground Signals

167, 159,
137, 122,

46, 35, 17

16 VCC

166, 157,
136, 123,

45, 34

161 VBAT

96 AVSS
95 AVCC

VSS

VSTBY

I Ground

Digital ground.

I System Power Supply of 3.3V

The power supply of LPC and related functions, which is main power of
system.

I Standby Power Supply of 3.3V

The power supply of EC domain functions, which is standby power of
system.
Note that the power of PLL is sourced by pin 157 only. (pin F8 for IT8510G)

I Battery Power Supply of 3.3V

The power supply for RTC, 32.768KHz oscillator and some system wake
up function. Internal VBS power is supplied by VSTBY when it is valid and
is supplied by VBAT when VSTBY is not supplied. If VBAT is not used, tie
this pin to ground.

I Analog Ground for Analog Component
I Analog VCC for Analog Component

Notes: I/O cell types are described below:

I: Input PAD.
AI: Analog Input PAD.
IK: Schmitt Trigger Input PAD.
IKD: Schmitt Trigger Input PAD (integrated one pull-down resistor).
PIU: PCI Bus Specified Input PAD (integrated one pull-up resistor).
OSCI: Oscillator Input PAD.
O2: 2 mA Output PAD.
O4: 4 mA Output PAD.
O6: 6 mA Output PAD.
O8: 8 mA Output PAD.
PIO: PCI Bus Specified Bidirectional PAD.
OSCIO: Oscillator Bidirectional PAD.
AIO2: 2 mA Bidirectional PAD with Analog Input PAD.
IOK2: 2 mA Bidirectional PAD with Schmitt Trigger Input PAD.
IOK4: 4 mA Bidirectional PAD with Schmitt Trigger Input PAD.
IOK6: 6 mA Bidirectional PAD with Schmitt Trigger Input PAD.
IOK8: 8 mA Bidirectional PAD with Schmitt Trigger Input PAD.

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Pin Description

5.2 Chip Power Planes and Power States
Table 5-17. Power States

Power State VCC pin VSTBY/AVCC pin VBAT pin Internal VBS

Active
Active with Power Saving

Supplied Supplied Supplied or Not Switched from VSTBY
Supplied Supplied

Supplied or Not Switched from VSTBY
EC is in Idle, Doze or
Sleep Mode

Standby
Standby with Power Saving

Not Supplied Supplied Supplied or Not Switched from VSTBY
Not Supplied Supplied

Supplied or Not Switched from VSTBY
EC is in Idle, Doze or
Sleep Mode

Power Fail
Battery Fail

Not Supplied Not Supplied Supplied Switched from VBS
Not Supplied Not Supplied Not Supplied Not Supplied

Note:

(1) The AVCC should be derived from VSTBY.
(2) All other combinations of VCC / VSTBY / VBAT are invalid.
(3) In Power Saving mode, 8032 program counter is stopped and no instruction will be executed no

matter EC Clock is running or not.

(4) VBS is the battery-backed power. When VSTBY is valid, VBS is supplied by VSTBY. When VSTBY is

not valid, VBS is supplied by VBAT.

EC firmware sets PCON bit

Active with

Power Saving

Standby with

Power Saving

VSTBY On VSTBY Off

Active

Reset or INT0#, INT1# asserted

VCC On VCC Off

Standby (S3, S4, S5)

Reset or INT0#, INT1# asserted

VSTBY On VSTBY Off

EC firmware sets PCON bit

Power Fail

VBAT On VBAT Off

Battery Fail

VBAT Off

VSTBY Off

VCC Off

Figure 5-1. Power State Transitions

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IT8510E

5.3 Pin Power Planes and States
Table 5-18. Quick Table of Power Plane for Pins

Power Plane Pins No.

VCC 7-18

VSTBY 1-6, 19-157, 162-176

VBS 158-161

In the following tables of this section, Standby means that the VCC is not valid but VSTBY is supplied (S3, S4 or
S5) and EC is in normal operation. Standby with Sleep means that 8032 and most of its functions are out of
work due to PLL power-down while VSTBY is still supplied. Power Fail means only battery-backed power is
supplied.

The abbreviations used in the following tables are described below:
H means EC drives high or driven high.
L means EC drives low or driven to low or output pin power off.
Z means EC tri-stated the I/O pin or output pin with enable.
RUN means that Output or I/O pins are in normal operation.
Driven means that the input pin is driven by connected chip or logic.
STOP means that the output pin keeps its logical level before the clock is stopped.
OFF means I/O pin power off.

Note that reset sources of ‘Reset Finish’ columns depend on Reset Types and Applied Module Table and it
means the reset is finished when its corresponding power plane is supplied.
Note that GPIO pins listed in different functional tables except GPIO table indicate their pin status of
corresponding alternative function.

Table 5-19. Pin States of LPC Bus Interface

Signal

(Alt Func of GPIO ?)

LPCRST# (Y) VSTBY Driven L L L

LPCCLK VCC Driven L L L
LAD[3:0] VCC RUN OFF OFF OFF

LFRAME# VCC Driven L L L

SERIRQ VCC Z OFF OFF OFF

LPCPD# (Y) VSTBY Driven L L L

CLKRUN# (Y) VSTBY Driven OFF L OFF

ECSMI# VSTBY RUN RUN Z OFF

ECSCI# (Y) VSTBY Driven RUN Z OFF

GA20 (Y) VSTBY Driven RUN STOP OFF

KBRST# (Y) VSTBY H RUN STOP OFF

WRST# VSTBY Driven Driven Driven L

PWUREQ# VSTBY Z RUN STOP OFF

LPC80HL (Y) VSTBY Driven L L OFF

LPC80LL (Y) VSTBY Driven L L OFF

Power

Plane

Reset

Finish

Standby Standby with

Sleep

Power Fail

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Signal

(Alt Func of GPIO ?)

FA[15:0] VSTBY RUN RUN AFSTBY=1:

FA16 (Y)
FA17 (Y)
FA18 (Y)
FA19 (Y)
FA20 (Y)
FA21 (Y)

FD[7:0] VSTBY RUN RUN AFSTBY=1:

FRD# VSTBY L RUN L OFF
FWR# VSTBY H RUN H OFF
FCS# VSTBY L RUN AFSTBY=1: H

Signal

(Alt Func of GPIO ?)

KSO[15:0] VSTBY L RUN STOP OFF

KSI[7:0] VSTBY Driven Driven Driven L

Signal

(Alt Func of GPIO ?)

SMCLK0 (Y)
SMCLK1 (Y)
SMDAT0 (Y)
SMDAT1 (Y)

Signal

(Alt Func of GPIO ?)

PS2CLK0 (Y)
PS2CLK1 (Y)
PS2CLK2 (Y)
PS2CLK3 (Y)
PS2DAT0 (Y)
PS2DAT1 (Y)
PS2DAT2 (Y)
PS2DAT3 (Y)

Pin Description

Table 5-20. Pin States of External Flash Interface

Power

Plane

VSTBY L

Reset

Finish

(pull-down)

Standby Standby with

Sleep

Z with pull-down

AFSTBY=0

STOP

RUN AFSTBY=1:

Z with pull-down

AFSTBY=0

STOP

Z with pull-down

AFSTBY=0:

STOP

AFSTBY=0: L

Table 5-21. Pin States of Keyboard Matrix Scan Interface

Power

Plane

Reset

Finish

Standby Standby with

Sleep

Table 5-22. Pin States of SM Bus Interface

Power

Plane

VSTBY Driven RUN Z OFF

VSTBY Driven RUN Z OFF

Reset

Finish

Standby Standby with

Sleep

Table 5-23. Pin States of PS/2 Interface

Power

Plane

VSTBY Driven RUN Z OFF

VSTBY Driven RUN Z OFF

Reset

Finish

Standby Standby with

Sleep

Power Fail

OFF

OFF

OFF

OFF

Power Fail

Power Fail

Power Fail

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IT8510E

Table 5-24. Pin States of PWM Interface

Signal

(Alt Func of GPIO ?)

PWM0 (Y)
PWM1 (Y)
PWM2 (Y)
PWM3 (Y)
PWM4 (Y)
PWM5 (Y)
PWM6 (Y)

PWM7 (Y)
TACH0 (Y)
TACH1 (Y)

TMRI0 (Y)

TMRI1 (Y)

Power

Plane

VSTBY Driven RUN STOP OFF

VSTBY Driven Driven Driven OFF

VSTBY Driven Driven Driven OFF

Reset

Finish

Standby Standby with

Sleep

Power Fail

Table 5-25. Pin States of Wake Up Control Interface

Signal

(Alt Func of GPIO ?)

WUI0 (Y)
WUI1 (Y)
WUI2 (Y)
WUI3 (Y)
WUI4 (Y)
WUI5 (Y)
WUI6 (Y)
WUI7 (Y)

PWRSW (Y) VSTBY Driven Driven Driven OFF

RI1# (Y)
RI2# (Y)

RING# (Y) VSTBY Driven Driven Driven OFF

PWRFAIL# (Y) VSTBY Driven Driven Driven OFF

Power

Plane

VSTBY Driven Driven Driven OFF

VSTBY Driven Driven Driven OFF

Reset

Finish

Standby Standby with

Sleep

Power Fail

Table 5-26. Pin States of UART Interface

Signal

(Alt Func of GPIO ?)

RXD (Y) VSTBY Driven Driven Driven OFF

TXD (Y) VSTBY Driven RUN STOP OFF

Power

Plane

Reset

Finish

Standby Standby with

Sleep

Power Fail

Table 5-27. Pin States of GPIO Interface

Signal

(Alt Func of GPIO ?)

GPA0-GPI6 VSTBY Driven Z or by

Power

Plane

Reset

Finish

Standby Standby with

Sleep

STOP OFF

alternative

function.

Power Fail

Table 5-28. Pin States of ADC Input Interface

Signal

(Alt Func of GPIO ?)

ADC[3:0] AVCC Driven Driven Driven L
ADC4 (Y)
ADC5 (Y)
ADC6 (Y)

ADC7
ADC8 AVCC Driven RUN RUN L
ADC9 AVCC Driven Driven Driven L

Power

Plane

AVCC Driven Driven Driven L

Reset

Finish

Standby Standby with

Sleep

Power Fail

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Pin Description

Table 5-29. Pin States of DAC Output Interface

Signal

(Alt Func of GPIO ?)

DAC[3:0] AVCC L RUN RUN OFF

Power

Plane

Reset

Finish

Standby Standby with

Sleep

Table 5-30. Pin States of Clock

Signal

(Alt Func of GPIO ?)

CK32K VBS Driven RUN RUN RUN

CK32KE VBS Driven RUN RUN RUN

CK32KOUT/GPC7 VSTBY Driven RUN RUN OFF

CLKOUT/GPC0 VSTBY Driven RUN STOP OFF

Power

Plane

Reset

Finish

Standby Standby with

Sleep

Power Fail

Power Fail

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IT8510E

5.4 PWRFAIL# Interrupt to INTC

The firmware may use the PWRFAIL# to do some necessary response if VSTBY is being lost. Corresponded
INT0# has higher priority than INT1#.

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Pin Description

5.5 Reset Sources and Types
Table 5-31. Reset Sources

Reset Sources Description

VBS Power-Up Reset
VSTBY Power-Up Reset

Activated after VBS is power up
Activated after VSTBY is power up and 10 MHz PLL is stable

It takes t

for PLL stabling, and the external flash must be ready before

PLLS

VSTBY Power-Up Reset finish

VCC Power-Up Reset
Warm Reset
LPC Hardware Reset
Super I/O Software Reset
Watch Dog Reset

Activated after VCC is power up
Activated if WRST# is asserted
Activated if LPCRST# is asserted
Activated if SIOSWRST of PNPCFG is writing 1
Activated if 8032 WDT or External WDT time-out

Table 5-32. Reset Types and Applied Module

Reset Types Sources Applied Module

VBS Region Reset
Host Domain Hardware Reset

VBS Power-Up Reset RTC, SWUC
Warm Reset, VCC Power-Up Reset or
LPC Hardware Reset

LPC, PNPCFG, Logical Devices and
EC2I

LPC Hardware Reset may be unused

Host Domain Software Reset
EC Domain Reset

Super I/O Software Reset PNPCFG, Logical Devices and EC2I
Warm Reset, VSTBY Power-Up Reset

EC Domain

or Watch Dog Reset

The WRST# should be driven low for at least t

before going high (Refer to Table 9-2. Warm Reset AC

WRSTW

Table on page 253)
.
If the firmware wants to assert an EC Domain Reset, start an internal of external watchdog without clearing its
counter or write invalid data to EWDKEYR register (refer to EWDKEYEN and EWDKEYR registers).
If the firmware wants to determine the source of the last EC Domain Reset, use the Reset Scratch Register
(RSTSCR).

5.5.1 Relative Interrupts to INTC

• Interrupt to INTC

LPCRST# may come from pin LPCRST#/WUI4/GPD2 or RING#/PWRFAIL#/LPCRST#/GPB7, both pins have
another interrupt relative alternative function. LPCRST# can be treated as an orthogonal input and LPCRST#
event can be handled in the same interrupt routine of another alternative function.

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IT8510E

5.6 Chip Power Mode and Clock Domain

Table 5-33. Clock Types

Types Description

RTC Clock
EC Clock

32.768 KHz generated by internal oscillator
10 MHz generated by internal PLL which feds RTC Clock and applied on EC
Domain. The EC Clock may be divided by CFSELR of ECPM module
Default EC Clock is divided into 5 MHz, and should be programmed to 10 MHz.

LPC Clock

33 MHz or slower from LPCCLK pin and applied on Host Domain

The 8032 can enter Idle/Doze/Sleep mode to reduce some power consumption. After entering the Idle mode,
timers and the Watch Dog timer of 8032 still work. After entering Doze/Sleep mode, clock of 8032 is stopped
and internal timers are stopped but external timer still works. After entering Doze mode, EC domain clock is
stopped and all internal timers are stopped. Also see Table 5-35 on page 33 for the details.
The way to wake up 8032 from the Idle mode is to enable internal or external interrupts, or hardware reset. The
way to wake up 8032 from Doze/Sleep mode is to enable external interrupts or hardware reset. Firmware may
set PLLCTRL bit before setting PD bit to enter the Sleep mode, since stopping PLL can reduce more power
consumption, but it takes more time to wake up from Sleep mode due to waiting for PLL being stable. The steps
to enter and exit Idle/Doze/Sleep are listed below:

(a) Set relative bits of IE register if they are cleared.
(b) Set channels of WUC which wants to wake up 8032 and disable unwanted channels.
(c) Set channels of INTC which wants to wake up 8032 and disable unwanted channels.
(d) Set PLLCTRL bit for Doze mode, or clear it for Doze mode.
(e) Set IDL bit in PCON to enter the Idle mode, or set PD bit in PCON to enter the Doze/Sleep mode.
(f) 8032 waits for an interrupt to wake up.
(g) After an interrupt is asserted, 8032 executes the corresponding interrupt routine and return the next

instruction after setting PCON. Notice that 8032 will not execute the interrupt routine if PDC bit in PDCON
is set before PCON is set and the interrupt is de-asserted.

The following figure describes the drivers and branches of the three clocks.
In this figure, clk_32khz represents RTC Clock; clk_src and its branches represent EC Clock; clk_ibus
represents LPC Clock.

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Pin Description

CK32K

CK32KE

Test Pin

LPCCLK

clk_src

Internal Oscillator

Gating

Operation

Gating

ADCCG@CGCTRL1R

Gating

PS2CG@CGCTRL1R

Gating

PWMCG@CGCTRL1R

Gating

KBSCG@CGCTRL1R

Gating

SMBCG@CGCTRL1R

Gating

DACCG@CGCTRL1R

Gating

GPIOCG@CGCTRL1R

Gating

ETWDCG@CGCTRL1R

Gating

EC2ICG@CGCTRL2R

Gating

KBCCG@CGCTRL2R

Gating

SMFIG@CGCTRL2R

Gating

PMCCG@CGCTRL2R

Gating

SWUCCG@CGCTRL2R

clk_ibus
33 MHz

Internal PLL

POWEN@DACCTRL

clk_32khz

32.768 Hz
10 MHz

Gating

RTC

clk_10mhz

CDNUM@CFSELR

8032

ADC

Divider

SCLKDIV@ADCCTL

PS2

PWM

clk_10mhz

KB Scan

SMB

DAC

DAC Analog Circuit

GPIO

ETWD

EC2I

ETWD

KBC

SMFI

Divider

FTDIV@FMPSR

PMC

SWUC

LPC, PNPCFG, EC2I, SMFI,

SWUC, KBC, PMC

Divider

Divider

Divider

ADCEN@ADCCFG

Gating

PWMCG@CGCTRL1R

clk_32khz

clk_1mhz

clk_32hz

1 kHz
32 Hz

CFSEL@CFSELR

Gating

clk_pwm_10mhz

clk_pwm_78khz

clk_pwm_10mhz

clk_32hz

clk_pwm_78khz

clk_32khz

clk_pwm

ETPS@ETPSR

SMFI

clk_1khz

clk_32hz

clk_32khz

1

clk_src

0

0
1

PWMTM@ZTIER

0
1

PWMTM@ZTIER

0
1

PWMTM@ZTIER

External Timer

Counter

clk_10mhz

clk_32khz

ADC Operation
ADC Operation
ADC Analog Circuit

clk_pwm

clk_pwm_78khz

Divider

78.125KHz

Tachometer

SmartAuto Fan

PWM Prescaler

External Watchdog

0
1

EWDSRC@ETWCFG

Counter

CLKOUT/GPC0

CK32KOUT/GPC7

Figure 5-2. Clock Tree

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IT8510E

Table 5-34. Power Saving by EC Clock Operation Mode

Mode Item Description

Normal

Enter VSTBY is supplied and hardware reset done
Exit Enter other modes
RTC Clock On
10 MHz PLL On
EC Domain Clock Driven by PLL or divided clock (refer to CFSELR of ECPM module)
8032 Clock The same as EC Domain Clock
Comment Power consumption can be reduced by selectively disabling modules

(refer to ECPM module)

Enter Set IDL bit in PCON of 8032
Exit Interrupt from INTC, interrupt from 8032 timer, watchdog reset or

hardware reset

Idle

RTC Clock On
10 MHz PLL On
EC Domain Clock Driven by PLL or divided clock (refer to CFSELR of ECPM module)
8032 Clock The same as EC Domain Clock
Comment Power consumption can be reduced by selectively disabling modules,

refer to ECPM module.

Doze

Enter Set PD bit in PCON of 8032
Exit Interrupt from INTC or hardware reset
RTC Clock On
10 MHz PLL On, clearing PLLCTRL of ECPM module is required
EC Domain Clock Driven by PLL or divided clock (refer to CFSELR of ECPM module)
8032 Clock Off
Comment Power consumption can be reduced by selectively disabling modules

(refer to ECPM module)

Sleep

Enter Set PD bit in PCON of 8032
Exit Interrupt from INTC or hardware reset
RTC Clock On
10 MHz PLL Off, setting PLLCTRL of ECPM module is required
EC Domain Clock Driven by PLL or divided clock (refer to CFSELR of ECPM module)
8032 Clock Off
Comment Power consumption can be reduced by selectively disabling modules

(refer to ECPM module)

Note:

The PD bit in PCON register may trigger the Doze or Sleep mode of EC Domain.

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Pin Description

Table 5-35. Module Status in Each Power State/Clock Operation

Power State and/or

Clock Operation

Active
Active with Power Saving

LPC, PNPCFG, EC2I,
host parts of SMFI/

Running

Module

Stopped

Module

SWUC/ KBC/ PMC/
RTC

Standby
Standby with Power Saving

LPC, PNPCFG, EC2I,

host parts of SMFI/
SWUC/ KBC/ PMC/
RTC

Active with Idle Mode
Standby with Idle Mode

All other EC modules 8032 code-fetch (but

internal timer/WDT are
still running)

Active with Doze Mode

All other EC modules 8032 List EC

Standby with Doze Mode
Active with Sleep Mode

Standby with Sleep Mode

GPIO, WUC and its
sources, INTC and its

All other EC modules List EC

sources from running
modules, SWUC
wakeup logic, PWM
channel outputs, KBS,
ETWD, RTC

Power Fail
Battery Fail

RTC All others List all

All List all

Note: Running module means this module works well.

Stopped module means this module is frozen because its clock is stopped.
Off module means this module is turned off due to power lost.

Off

Module

Note

List host
relative
modules
only
List host
relative
modules
only
List EC
modules
only

modules
only

modules
only

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IT8510E

5.7 Pins with Pull, Schmitt-Trigger or Open-Drain Function
Table 5-36. Pins with Pull Function

Pin Pull Function Note

KSI[7:0] Programmable 75k pull-up resistor Default off
KSO[15:0] Programmable 75k pull-up resistor Default off
GPE4-E7
and their alternative functions

Programmable 75k pull-up resistor GPE0-E3 have no pull function

Default on/off refer to Table 7-13

on page 179 .
GPG0-G7
and their alternative functions
All other GPIO pins
and their alternative functions
FA[21:0], FD[7:0],

Programmable 75k pull-down resistor Default on/off refer to Table 7-13

on page 179 .

Programmable 75k pull-up resistor Default on/off refer to Table 7-13

on page 179 .

Operational 75k pull-down resistor Pull-down if power-saving
FCS#, FRD#, FWR#
FA[5:2] Operational 75k pull-down resistor Pull-down after VSTBY power on

until its pin state is sampled for
hardware strap function

Note: 75k ohm is typical value. Refer to section 8 DC Characteristics on page 251 for details

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Pin Description

Table 5-37. Pins with Schmitt-Trigger Function

Pin Pull Function Note

All GPIO pins except GPE0-E3

Fixed Schmitt-Trigger Input
and their alternative functions
KSI[7:0] Fixed Schmitt-Trigger Input
WARMRST# Fixed Schmitt-Trigger Input
FD[7:0] Fixed Schmitt-Trigger Input

Table 5-38. Signals with Open-Drain Function

Signal Open-Drain Function Note

SERIRQ Open-drain bi-directional signal
CLKRUN# Open-drain output signal
KSO[15:0] Programmable open-drain output signal Default is push-pull
PS2CLK0, PS2DAT0

Open-drain bi-directional signal
PS2CLK1, PS2DAT1
PS2CLK2, PS2DAT2
PS2CLK3, PS2DAT3
SMCLK0, SMDAT0

Open-drain bi-directional signal
SMCLK1, SMDAT1
SCI#, SMI#, PWUREQ# Open-drain output signal
All GPIO signals except GPE0-E3

Programmable open-drain output signal Default is push-pull
and their alternative functions

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IT8510E

5.8 Power Consumption Consideration

• Each input pin should be driven or pulled
Input floating causes leakage current and should be prevented.
Pins can be pulled by an external pull resistor or internal pull for a pin with programmable pull.
GPE0-~GPE3 have analog inputs as their alternative function, and these four pins can prevent leakage current
by switching to the alternative function, too.

• Each output-drain output pin should be pulled
If an output-drain output pin is not used and is not pulled by an external pull resistor or internal pull for a pin with
programmable pull, make it drive low by the firmware.

• Each input pin which belongs to VSTBY power plane is connected or pulled up to VCC power plane
Such cases may cause leakage current when VCC is not supplied and a diode may be used to isolate leakage
current from VSTBY to VCC. For example, use diodes for KBRST# and GA20 if they are connected to VCC
logic of South-Bridge.

• Any pin which belongs to VSTBY power plane should not be pulled to VCC in most cases.
It may cause a leakage current path when VCC is shut down. Refer to the above consideration.

• Program GPIO ports as output mode as soon as possible
Any GPIO port used in output mode should be programmed as soon as possible since this pin may not be
driven (be floating) if its default value of pull is off.

• Disable unnecessary pull in power saving mode
Prevent from driving a pin low or let a pin be driven low but its pull high function is enabled in power saving
mode.
Prevent from driving a pin high or let a pin be driven high but its pull low function is enabled in power saving
mode.

• Handle the connector if no cable is plugged into it
The firmware or the hardware should prevent the wire connected to the connector from no driving if no cable is
plugged into the connector such as PS/2 mouse and so on.

• Disable unnecessary pull for a programmable pull pin
Pull control may be enabled for an input pin or an open-drain output pin and should be disabled for a push-pull
output pin.
Pull control should be disabled if an external pull resistor exists.
External pull resistor can control the pull current precisely since the register value of the internal pull has large
tolerance. Refer to section 8 DC Characteristics on page 251 for details

• Flash standby mode
Make flash enter standby mode to reduce power consumption if it is not used.
It's controlled by AFSTBY bit in FPCFG register.
It may be an EMI option.

• Prevent accessing Scratch RAM before entering power-saving mode
There is unnecessary power consumption after Scratch RAM is accessed in data space. Reading any other
registers of external data memory once to prevent this condition.

• Use Doze mode rather than Idle mode
Doze mode has less power consumption than Idle mode because 8032 clock is gated (stopped) in Doze mode.
Firmware design using Idle mode should be replaced with Doze mode by replacing internal timer and watchdog
by external timer and watchdog.

• Use Sleep mode rather than Doze mode

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Pin Description

Sleep mode has less power consumption than Doze mode because PLL is power-down and EC clock is
stopped in Sleep mode, although most EC modules are not available.
Refer to Table 5-35 on page 33 for the details.

• Divide EC clock by module
After reset, EC clock is 5 MHz and the firmware sets to 10 MHz as normal operation. Divided EC clock makes
less power consumption and it’s controlled by CFSELR register.

• Gate clock by module in EC domain
All modules in EC domain are not clock gated in default but can be gated by module to get less power
consumption.
It’s controlled by CGCTRL1R and CGCTRL2R registers.

• Power-down ADC/DAC analog circuit if it is unnecessary
ADC/DAC analog circuits are power-down in default and should be activated only if necessary.
ADC analog circuit power-down is controlled by ADCEN bit in ADCCFG register.
DAC analog circuit power-down is controlled by POWDN bit in DACCTRL register.

• Connect LED cathode to output pin
It doesn’t reduce total power consumption although it reduces power consumption of IT8510.
The advantage is to reduce the temperature of IT8510 and prevent the output pad from driving large current.

T

V

S

B

Y

i

n

I

O

G

P

p

n

p

O

I

i

G

P

d

a

d

o

o

G

B

Figure 5-3. LED connection

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6. Host Domain Functions

6.1 Low Pin Count Interface

6.1.1 Overview

The Low Pin Count (LPC) is an interface for modern ISA-free system. It is defined in Intel’s LPC Interface
Specification, Revision 1.1. There are seven host-controlled modules that can be accessed by the host via the
LPC interface. These host-controlled modules are “Logical Devices” defined in Plug and Play ISA Specification,
Version 1.0a.

6.1.2 Features

 Complies with Intel’s LPC Interface Specification, Revision 1.1
 Supports SERIRQ and complies with Serialized IRQ Support for PCI Systems, Revision 6.0
 Supports LPCPD#, CLKRUN#
 Supports Plug and Play ISA registers

6.1.3 Accepted LPC Cycle Type

The supported LPC cycle types are listed below:
* LPC I/O Read (16-bit address, 8-bit data)
* LPC I/O Write (16-bit address, 8-bit data)
* LPC Memory Read (32-bit address, 8-bit data)
* LPC Memory Write (32-bit address, 8-bit data)
* FWH Read (32-bit address, 8-bit data)
* FWH Write (32-bit address, 8-bit data)

I/O cycles are used to access PNPCFG and Logical Devices. Memory or FWH is used to access Flash content
through SMFI module Indirect memory cycles based on I/O cycles can also access Flash. Refer to SMFI
Module for details about indirect memory access.

The following table describes how LPC module responds the I/O, Memory and FWH cycles from Host side in
different conditions.

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Table 6-1. LPC/FWH Response

Cycle Type/Condition Read Response Write Response

All Cycles before 10 MHz PLL Stable
I/O Cycle to PNPCFG or Logical Devices
I/O Cycle but Address Out Of Range
I/O Cycle to Locked PNPCFG/RTC by EC2I
Indirect Memory Address

NOTE 3

Memory Cycle, FWH Cycle or

Long-Wait Long-Wait
Ready Ready
Cycle Ignored Cycle Ignored
Returns 00h Cycle Ignored
Ready Ready
Long-Waits until Ready Long-Waits until Ready

NOTE 1

Indirect Memory Data
Memory Cycle, FWH Cycle or HERES=00*
Indirect Memory Data HERES=01
but Address Protected by SMFI HERES=10
HERES=11
Memory Cycle or Indirect Memory Data

Long-Wait Cycle Ignored
Returns 00h Cycle Ignored
Error-SYNC Error-SYNC
Long-Wait Error-SYNC
Cycle Ignored Cycle Ignored

but Address Out of Range
FWH Cycle but Address Out of Range
FWH Cycle but FWH ID is unmatched
LPC Cycle or Indirect Memory Data but

NOTE 2

Ready Ready
Cycle Ignored Cycle Ignored
Cycle Ignored Cycle Ignored

LPCMEN bit in SHMC register cleared
FWH Cycle but

Cycle Ignored Cycle Ignored

FWHEN bit in SHMC register cleared

Note 1:

After reset, IT8510 responses Long-Waits before Ready for FWH Write Cycle.

If LPC host (South-Bridge) fails to recognize Long-Wait SYNC during FWH Write Cycle, it is recommended to
use Indirect Memory.

Note 2:

FWH ID is defined in FWHID field in SHMC register.

Note 3:

Indirect Memory Cycles access the flash via LPC I/O Cycle. Indirect Memory Address is combined with
SMIMAR0, SMIMAR1, SMIMAR2 and SMIMAR3 registers. Indirect Memory Data is SMIMDR register.

6.1.4 Debug Port Function

LPC module implements two latch signals for Main-Board debug purpose. LPC I/O write cycles with address
equal to 80h will cause the LPC module to assert LPC80HL and LPC80LL signals which provide a simple
external logic to latch it in order to display on LED, even though I/O port 80h is not recognized by PNPCFG or
any Logical Device. LPC80HL goes high when it is time to latch the high-nibble of the data written to port 80h,
and LPC80LL means the low-nibble.

6.1.5 Serialized IRQ (SERIRQ)

IT8510 has programmable IRQ number for each logical device. Available IRQ numbers are 1, 2, 3, 4 5, 6, 7, 8,
9, 10, 11, 12, 14, and 15.

Different logical devices inside IT8510 can share the same IRQ number if they have the same IRQPS bit in
IRQTP register and are configured as the same triggered mode (all level-triggered or all edge triggered) in their
EC side registers.

But it is not allowed to share an IRQ number with a logical device outside IT8510. Note that edge-triggered
interrupts are not suitable for sharing in most cases.

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6.1.6 Relative Interrupts to INTC/WUC

• Interrupt to WUC

If the LPC address of an I/O, LPC Memory or FWH Cycle on LPC bus is accepted, WU42 interrupt will be
asserted.

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6.1.7 LPCPD# and CLKRUN#

• LPCPD#

LPCPD# is used as internal “power good” signal to indicate the status of VCC. It is recommend to be

implemented.

• CKRUN#

CLKRUN# is used to make sure that SERIRQ status is entirely translated to host side.

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6.1.8 Check Items

If the IT8510 fails in LPC memory or I/O cycles at boot, check the following recommended items first.

• LPC/FWH memory cycles

Check whether corresponding GPIO ports of necessary FA21-17 are switched to their alternative function.
Check whether LPCRST# reset source from GPD2 or GPB7 is logic low if it is in alternative function.
Check whether LPCPD# signal from GPE6 is logic low if it is in alternative function.
Check whether hardware strap SHBM is enabled or set FWHEN/LPCMEN bit in SHMC register.
Check whether the firmware doesn’t change the read protection control.

• LPC I/O cycles

Check whether LPCRST# reset source from GPD2 or GPB7 is logic low if it is in alternative function.
Check whether LPCPD# signal from GPE6 is logic low if it is in alternative function.
Check whether hardware strap BADDR1-0 are in correct setting.

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6.2 Plug and Play Configuration (PNPCFG)

The host interface registers of PNPCFG (Plug and Play Configuration) are listed below. The base address can
be configured via hardware strap BADDR1-0. Note that bit 0 of SWCBALR must be zero.
To access a register of PNPCFG, write target index to address port and access this PNPCFG register via data
port. If accessing the data port without writing index to address port, the latest value written to address port is
used as the index. Reading the address port register returns the last value written to it.

Table 6-2. Host View Register Map, PNPCFG

BADDR1-0

=00b

BADDR1-0

=01b

BADDR1-0

=10b

BADDR1-0

=11b

7 0 I/O Port Address

Address Port 2Eh 4Eh (SWCBAHR, SWCBALR) Reserved

Data Port 2Fh 4Fh (SWCBAHR, SWCBALR+1) Reserved

Note 1: SWCBALR should be on boundary = 2, which means bit 0 must be 0.
Note 2: Only use BADDR1-0=10b if the port pair is not 2Eh/2Fh or 4Eh/4Fh.

The host interface registers for Logic Device Control are listed below. The base address can be configured via
the following Plug and Play Configuration Registers. Note that if a logical device is activated but with base
address equal to 0000h, the host side cannot access this logical device since 0000h means I/O address range
is disabled.

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Table 6-3. Host View Register Map, Logical Devices

7 0 I/O Port Address

System Wake-Up Control (SWUC)

Depend on PnP SW
Used Addr: (IOBAD0+00h,+02h,+06h,+07h,13h,15h)
Base address boundary = 32

KBC / Mouse Interface Unused

KBC / Keyboard Interface

Depend on PnP SW
Used Addr: (IOBAD0+00h), (IOBAD1+00h)
Base address boundary = none, none
Legacy Address = 60h,64h

Shared Memory/Flash Interface (SMFI)

Depend on PnP SW
Used Addr: (IOBAD0+0h, …+8h,+0Ch)
Base address boundary = 16

Real Time Clock (RTC)

Depend on PnP SW
Used Addr: (IOBAD0+0h,+1h), (IOBAD1+0h,+1h)
Base address boundary = 2, 2
Legacy Address = 70h-73h

Power Management I/F Channel 1 (PM1)

Depend on PnP SW
Used Addr: (IOBAD0+0h), (IOBAD1+0h)
Base address boundary = none, none
Legacy Address = 62h,66h

Power Management I/F Channel 2 (PM2)

Depend on PnP SW
Used Addr: (IOBAD0+0h), (IOBAD1+0h)
Base address boundary = none, none
Legacy Address = 68h,6Ch

Note: The boundary number means the address must be the multiple of this number.

The host interface registers for Standard Plug and Play Configuration of PNPCFG are listed below. These
registers are accessed via the Index-Data I/O ports defined in Table 6-3 on page 45. Note PNPCFG registers
are not allowed to be accessed if LKCFG bit in LSIOHA register of EC2I module is set. They are divided into two
parts, Super I/O Configuration Registers and Logical Device Registers.

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Table 6-4. Host View Register Map via Index-Data I/O Pair, Standard Plug and Play Configuration

Registers

7 0 Index

Register Name

Logical Device Number (LDN) 07h
Chip ID Byte 1(CHIPID1) 20h
Chip ID Byte 2(CHIPID2) 21h
Chip Version (CHIPVER) 22h
Super I/O Control (SIOCTRL) 23h

Super I/O Reserved 24h

Configuration Super I/O IRQ Configuration (SIOIRQ) 25h

Registers Super I/O General Purpose (SIOGP) 26h

Reserved 27h
Reserved 28h
Reserved 29h
Reserved 2Ah
Reserved 2Bh
Super I/O Power Mode (SIOPWR) 2Dh
Reserved 2Eh
Logical Device Activate Register (LDA) 30h

Logical Device I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) 60h

Configuration I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) 61h

Registers I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) 62h

I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) 63h

Selected by Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) 70h

LDN Register Interrupt Request Type Select (IRQTP) 71h

DMA Channel Select 0 (DMAS0) 74h
DMA Channel Select 0 (DMAS1) 75h
Device Specific Logical Device Configuration 1 to 10 F0h-F9h

The IRQ numbers for Logic Device IRQ via LPC/SERIRQ are listed below. The IRQ numbers can be configured
via the above Plug and Play Configuration Registers.

Table 6-5. Interrupt Request (IRQ) Number Assignment, Logical Device IRQ via SERIRQ

Logical Device

IRQ number

System Wake-Up Control (SWUC) Depend on PnP SW

KBC / Mouse Interface Depend on PnP SW, Legacy IRQ Num=12

KBC / Keyboard Interface Depend on PnP SW, Legacy IRQ Num=01

Shared Memory/Flash Interface (SMFI) Unused

Real Time Clock (RTC) Depend on PnP SW, Legacy IRQ Num=08
Power Management I/F Channel 1 (PM1) Depend on PnP SW, Legacy IRQ Num=01
Power Management I/F Channel 2 (PM2) Depend on PnP SW, Legacy IRQ Num=01

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6.2.1 Logical Device Assignment

Table 6-6. Logical Device Number (LDN) Assignments
LDN Functional Block

04h System Wake-Up Control (SWUC)

05h KBC/Mouse Interface

06h KBC/Keyboard Interface

0Fh Shared Memory/Flash Interface (SMFI)

10h Real Time Clock (RTC)

11h Power Management I/F Channel 1 (PM1)

12h Power Management I/F Channel 2 (PM1)

The following figure indicates the PNPCFG registers is combined with Super I/O Configuration Registers and
Logical Device Configuration Registers. Logical Device Configuration Registers of a specified Logical Device is
accessable only when Logical Device Number Register is filled with corresponding Logical Device Number
listed in Table 6-6 on page 47 .

07h
20h

2Fh

30h
60h

Logical Device Number Register

Super I/O Configuration Registers

Logical Device Control Register

Select Logical Device

(04h,05h,06h,0Fh,10h,11h,12h)

Standard Logical Device

Configuration Registers

75h
F0h

FEh

Special (Vendor-Defined)

Logical Device

Configuration Registers

Figure 6-1. Host View Register Map via Index-Data Pair

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6.2.2 Super I/O Configuration Registers

Registers with index from 07h to 2Eh contain Super I/O configuration settings.

6.2.2.1 Logical Device Number (LDN)

This register contains general Super I/O configurations.

Index: 07h

Bit R/W Default Description

7-0 R/W 04h

Logical Device Number (LDN)

This register selects the current logical device.
Valid values are 04h, 05h, 06h, 0Fh, 10h, 11h and 12h. All other values are
reserved.

6.2.2.2 Chip ID Byte 1 (CHIPID1)
Index: 20h

Bit R/W Default Description

7-0 R 85h

Chip ID Byte 1 (CHIPID1)

This register contains the Chip ID byte 1.

6.2.2.3 Chip ID Byte 2 (CHIPID2)
Index: 21h

Bit R/W Default Description

7-0 R 10h

Chip ID Byte 2 (CHIPID2)

This register contains the Chip ID byte 2.

6.2.2.4 Chip Version (CHIPVER)

This register contains revision ID of this chip

Index: 22h

Bit R/W Default Description

7-0 R 21h

Chip Version (CHIPVER)

6.2.2.5 Super I/O Control Register (SIOCTRL)

This register contains general Super I/O configurations.

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Index: 23h

Bit R/W Default Description

7-6 - 0h
5-4 - 0h
3-2 - 0h

1 W 0b

Reserved
Reserved
Reserved
Software Reset (SIOSWRST)

Read always returns 0.

0: No action.
1: Software Reset the logical devices.

0 R/W 1b

Super I/O Enable (SIOEN)

0: All Super I/O logical devices are disabled, except SWUC and

SMFI.

1: Each Super I/O logical device is enabled according to its Activate

register. (Index 30h)

6.2.2.6 Super I/O IRQ Configuration Register (SIOIRQ)

This register contains general Super I/O configurations.

Index: 25h

Bit R/W Default Description

7-5 - 0h

4 R/W 0b

Reserved
SMI# to IRQ2 Enable (SMI2IRQ2)

This bit enables using IRQ number 2 in the SERIRQ protocol as a SMI#
interrupt.
This bit is similar to LDACT bit in LDA register.

0: Disabled
1: Enabled

3-0 - 0h

Reserved

6.2.2.7 Super I/O General Purpose Register (SIOGP)

This register contains general Super I/O configurations.

Index: 26h

Bit R/W Default Description

7 R/W 0b

SIOGP Software Lock (SC6SLK)

0: Writing to bits 0-6 of SIOGP is allowed.
Other bits in this register can be cleared by Hardware and Software

reset (SIOSWRST).
1: Not allowed. Bits 6-0 of this register are read-only.
All bits in this register can be cleared by Hardware reset only.

6-5 R/W 00b

General-Purpose Scratch (GPSCR)

Reading returns the value that was previously written. Note that the EC
side can access whole PNPCFG registers via EC2I.

4 R/W 0b

RTC Disabled (RTCDE)

0: RTC is enabled according to its Activate register and SIOEN bit

in SIOCTRL register.

1: Disabled

3-0 - 0h

Reserved

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6.2.2.8 Super I/O Power Mode Register (SIOPWR)

This register is a battery-backed register used by the EC side. See also 6.4.5.2.

Index: 2Dh

Bit R/W Default Description

7-2 - 0h

1 R/W 0b

Reserved
Power Supply Off (PWRSLY)

It indicates the EC side that the host requests to shut down the power in
legacy mode. Refer to SCRDPSO bit in SWCTL2 register on page 94

0: No action
1: It indicates power shut down if PWRSLY is Legacy mode.

Note: It always returns 0 when read.

0 R/W 0h

Power Button Mode (PWRBTN)

This bit controls the power button mode in the SWUC. Refer to SCRDPBM
bit in SWCTL2 register on page 94

0: Legacy
1: ACPI

6.2.3 Standard Logical Device Configuration Registers

Registers with index from 30h to F9h contain Logical Device configuration settings. LDN of the wanted logical
device should be written to LDN register before accessing these registers.
This section lists a standard description of these registers. Some default values for each register and more
detailed information for each logical device should be referred in each section.

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6.2.3.1 Logical Device Activate Register (LDA)
Index: 30h

Bit R/W Default Description

7-1 - 0h

0 R/W 0b

Reserved
Logical Device Activation Control (LDACT)

0: Disabled
The registers (Index 60h-FEh) are not accessible.
Refer to SIOEN bit in SIOCTRL
1: Enabled

6.2.3.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])

This register will be read-only if it is unused by a logical device.
The 16-bit base address must not be 0000h and might have the boundary limit for each logical device.

Index: 60h

Bit R/W Default Description

7-0 R/W Depend on

Logical

Device

I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBA[15:8])

This register indicates selected I/O base address bits 15-8 for I/O
Descriptor 0.

6.2.3.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])

This register will be read-only if it is unused by a logical device.
The 16-bit base address must not be 0000h and might have the boundary limit for each logical device.

Index: 61h

Bit R/W Default Description

7-0 R/W Depend on

Logical

Device

I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBA[7:0])

This register indicates selected I/O base address bits 7-0 for I/O Descriptor

0.

6.2.3.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])

This register will be read-only if it is unused by a logical device.
The 16-bit base address must not be 0000h and might have the boundary limit for each logical device.

Index: 62h

Bit R/W Default Description

7-0 R/W Depend on

Logical

Device

I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBA[15:8])

This register indicates selected I/O base address bits 15-8 for I/O
Descriptor 1.

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6.2.3.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0])

This register will be read-only if it is unused by a logical device
The 16-bit base address must not be 0000h and might have the boundary limit for each logical device.

Index: 63h

Bit R/W Default Description

7-0 R/W Depend on

Logical

Device

I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBA[7:0])

This register indicates selected I/O base address bits 7-0 for I/O Descriptor

1.

6.2.3.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)

This register will be read-only if it is unused by a logical device.

Index: 70h

Bit R/W Default Description

7-5 - 0h

4 R/W 0

Reserved
Wake-Up IRQ Enable (WKIRQEN)

Allow this logical device to trigger a wake-up event to SWUC. This bit
should not be set in SWUC Logical Device since it is used to collect IRQ
sources for SWUC.

0: Disabled
1: Enabled

3-0 R/W Depend on

Logical

Device

IRQ Number (IRQNUM)

Select the IRQ number (level) asserted by this logical device via SERIRQ.

00d: This logical device doesn’t use IRQ.
01d-012d: IRQ1-12 are selected correspondingly.
14d-15d: IRQ14-15 are selected correspondingly.
Otherwise: Invalid IRQ routing configuration.

6.2.3.7 Interrupt Request Type Select (IRQTP)

This register will be read-only if it is unused by a logical device.

Index: 71h

Bit R/W Default Description

7-2 - 0h

1 R/W Depend on

Logical

Device

Reserved
Interrupt Request Polarity Select (IRQPS)

This bit indicates the polarity of the interrupt request.

0: IRQ request is buffered and applied on SERIRQ.
1: IRQ request is inverted before being applied on SERIRQ.

This bit should be configured before the logical device is activated.

0 R/W Depend on

Logical

Device

Interrupt Request Triggered Mode Select (IRQTMS)

This bit indicates that edge or level triggered mode is used by this logical
device and should be updated by EC firmware via EC2I since the triggered
mode is configured in EC side registers. This bit is just read as previously
written (scratch register bit) and doesn’t affect SERIRQ operation.

0: edge triggered mode
1: level triggered mode

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6.2.3.8 DMA Channel Select 0 (DMAS0)
Index: 74h

Bit R/W Default Description

7-3 - 0h
2-0 R 4h

Reserved
DMA Channel Select 0

A value of 4 indicates that no DMA channel is active.

6.2.3.9 DMA Channel Select 0 (DMAS1)
Index: 75h

Bit R/W Default Description

7-3 - 0h
2-0 R 4h

Reserved
DMA Channel Select 1

A value of 4 indicates that no DMA channel is active.

6.2.4 System Wake-Up Control (SWUC) Configuration Registers

This section lists default values for each register and more detailed information for this logical device. Some
register bits will be read-only if unused.

Table 6-7. Host View Register Map via Index-Data I/O Pair, SWUC Logical Device

7 0 Index

Register Name

Super I/O Control Reg Logical Device Number (LDN = 04h) 07h

Logical Device Activate Register (LDA) 30h

Logical Device Control I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) 60h

And Configuration I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) 61h

Registers I/O Port Base Address Bits [15:8] for Descriptor 1

62h

(IOBAD1[15:8])-Unused

I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) -Unused 63h

Selected if Interrupt Request Number and Wake-Up on IRQ Enabled (IRQNUMX) 70h

LDN Register=04h Interrupt Request Type Select (IRQTP) 71h

6.2.4.1 Logical Device Activate Register (LDA)
Index: 30h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.1 on page 51.

6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
Index: 60h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.2 on page 51.

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6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
Index: 61h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.3 on page 51.

Bits 4-0 (IOBAD0[4:0]) are forced to 00000b and can’t be written.
It means the base address is on the 32-byte boundary.

6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])

This register is unused and read-only.

Index: 62h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.4 on page 51.

6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0])

This register is unused and read-only.

Index: 63h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.5 on page 52.

6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
Index: 70h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.6 on page 52.

6.2.4.7 Interrupt Request Type Select (IRQTP)
Index: 71h

Bit R/W Default Description

7-0 R/W 03h

Refer to section 6.2.3.7 on page 52.

6.2.5 KBC / Mouse Interface Configuration Registers

This section lists default values for each register and more detailed information for this logical device. Some
register bits will be read-only if unused.

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Table 6-8. Host View Register Map via Index-Data I/O Pair, KBC / Mouse Interface Logical Device

7 0 Index

Register Name

Super I/O Control Reg Logical Device Number (LDN = 05h) 07h

Logical Device Activate Register (LDA) 30h

Logical Device Control I/O Port Base Address Bits [15:8] for Descriptor 0

(IOBAD0[15:8]) –Unused

And Configuration I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) –Unused 61h

Registers I/O Port Base Address Bits [15:8] for Descriptor 1

(IOBAD1[15:8]) –Unused

I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) –Unused 63h

Selected if Interrupt Request Number and Wake-Up on IRQ Enabled (IRQNUMX) 70h

LDN Register=05h Interrupt Request Type Select (IRQTP) 71h

6.2.5.1 Logical Device Activate Register (LDA)
Index: 30h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.1 on page 51.

6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])

This register is unused and read-only.

Index: 60h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.2 on page 51.

6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])

This register is unused and read-only.

Index: 61h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.3 on page 51.

6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])

This register is unused and read-only.

Index: 62h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.4 on page 51.

6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0])

This register is unused and read-only.

Index: 63h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.5 on page 52.

60h

62h

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6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
Index: 70h

Bit R/W Default Description

7-0 R/W 0Ch

Refer to section 6.2.3.6 on page 52.

6.2.5.7 Interrupt Request Type Select (IRQTP)
Index: 71h

Bit R/W Default Description

7-0 R/W 03h

Refer to section 6.2.3.7 on page 52.

6.2.6 KBC / Keyboard Interface Configuration Registers

This section lists default values for each register and more detailed information for this logical device. Some
register bits will be read-only if unused.

Table 6-9. Host View Register Map via Index-Data I/O Pair, KBC / Keyboard Interface Logical Device

7 0 Index

Register Name

Super I/O Control Reg Logical Device Number (LDN = 06h) 07h

Logical Device Activate Register (LDA) 30h

Logical Device Control I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) 60h

And Configuration I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) 61h

Registers I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) 62h

I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) 63h

Selected if Interrupt Request Number and Wake-Up on IRQ Enabled (IRQNUMX) 70h

LDN Register=06h Interrupt Request Type Select (IRQTP) 71h

6.2.6.1 Logical Device Activate Register (LDA)
Index: 30h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.1 on page 51.

6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
Index: 60h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.2 on page 51.

Bits 7-3 (IOBAD0[15:11]) are forced to 00000b and can’t be written.

6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
Index: 61h

Bit R/W Default Description

7-0 R/W 60h

Refer to section 6.2.3.3 on page 51.

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6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
Index: 62h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.4 on page 51.

Bits 7-3 (IOBAD1[15:11]) are forced to 00000b and can’t be written.

6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0])
Index: 63h

Bit R/W Default Description

7-0 R/W 64h

Refer to section 6.2.3.5 on page 52.

6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
Index: 70h

Bit R/W Default Description

7-0 R/W 01h

Refer to section 6.2.3.6 on page 52.

6.2.6.7 Interrupt Request Type Select (IRQTP)
Index: 71h

Bit R/W Default Description

7-0 R/W 03h

Refer to section 6.2.3.7 on page 52.

6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers

This section lists default values for each register and more detailed information for this logical device. Some
register bits will be read-only if unused.

Table 6-10. Host View Register Map via Index-Data I/O Pair, SMFI Interface Logical Device

7 0 Index

Register Name

Super I/O Control Reg Logical Device Number (LDN = 0Fh) 07h

Logical Device Activate Register (LDA) 30h

Logical Device Control I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) 60h

And Configuration I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) 61h

Registers I/O Port Base Address Bits [15:8] for Descriptor 1

62h

(IOBAD1[15:8])-Unused

I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0])-Unused 63h

Selected if Interrupt Request Number and Wake-Up on IRQ Enabled

70h

(IRQNUMX) –Unused

LDN Register=0Fh Interrupt Request Type Select (IRQTP) -Unused 71h

Shared Memory Configuration Register (SHMC) F4h
Shared Memory Base Address High Byte Register (SHMBAH) F5h
Shared Memory Base Address Low Byte Register (SHMBAL) F6h
Shared Memory Size Configuration Register (SHMSZ) F7h
LPC Memory Control (LPCMCTRL) F8h

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6.2.7.1 Logical Device Activate Register (LDA)
Index: 30h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.1 on page 51.

6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
Index: 60h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.2 on page 51.

6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
Index: 61h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.3 on page 51.

Bits 3-0 (IOBAD0[3:0]) are forced to 0000b and can’t be written.
It means the base address is on the 16-byte boundary.

6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])

This register is unused and read-only.

Index: 62h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.4 on page 51.

6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0])

This register is unused and read-only.

Index: 63h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.5 on page 52.

6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)

This register is unused and read-only.

Index: 70h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.6 on page 52.

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6.2.7.7 Interrupt Request Type Select (IRQTP)

This register is unused and read-only.

Index: 71h

Bit R/W Default Description

7-0 R 00h

Refer to section 6.2.3.7 on page 52.

6.2.7.8 Shared Memory Configuration Register (SHMC)
Index: F4h

Bit R/W Default Description

7-4 R/W 0h

BIOS FWH ID (FWHID)

These bits correspond to the 4-bit ID which is part of a FWH transaction.

3 R/W Strap

BIOS FWH Enable (FWHEN)

It enables this chip to respond to FWH access.

0: Disabled (default as SHBM = 0)
1: Enabled (default as SHBM = 1)

2 R/W 0b

User-Defined Memory Space Enable (USRMEM)

It enables this chip to respond to LPC or FWH transactions to the
user-defined memory space.
Note: User-defined memory is specified by SHMBAH and SHMBAL
registers.

1 R/W 0b

BIOS Extended Space Enable (BIOSEXTS)

This bit expands the BIOS address space to make this chip response the
Extended BIOS address range.

0 R/W Strap

BIOS LPC Enable (LPCMEN)

It enables this chip to respond to LPC Memory and Indirect Memory
accesses.

0: Disabled (default as SHBM = 0)
1: Enabled (default as SHBM = 1)

6.2.7.9 Shared Memory Base Address High Byte Register (SHMBAH)

This register indicates the base address of the user-defined memory block mapped to the shared memory.

Index: F5h

Bit R/W Default Description

7-0 R/W 00h

Shared Memory Base Address High Byte (SHMBA[15:8])

It contains the high 8 bits of the base address of the user-defined memory
block.

6.2.7.10 Shared Memory Base Address Low Byte Register (SHMBAL)

This register indicates the base address of the user-defined memory block mapped to the shared memory.

Index: F6h

Bit R/W Default Description

7-0 R/W 00h

Shared Memory Base Address Low Byte (SHMBA[7:0])

It contains the low 8 bits of the base address of the user-defined memory
block.

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6.2.7.11 Shared Memory Size Configuration Register (SHMSZ)
Index: F7h

Bit R/W Default Description

7-4 - 00h
3-0 R/W 00h

Reserved
User-Defined Memory Block Size (SHMUSZ)

It defines the size of zone window. Size = 2

(SHMUZE + 16)

bytes, and maximum

size = 2M bytes.

Exp:
SHMUSZ Size

0000b 64K
0001b 128K
…
0101b 2M
0110b 4M
Others Reserved

6.2.7.12 LPC Memory Control (LPCMCTRL)

Normally the M-bus grant parks on 8032 side for code fetch and switches to LPC side if memory transactions on
LPC bus. To improve the host memory access performance, the M-bus grant parks on LPC side temporarily
during LPC Burst Window.

LPC Burst Window starts from the time when CLPCBT counts of “Continuous” LPC memory cycles are seen by
IT8510 and stops at the time when a “Non-continuous” LPC memory cycles are detected.

LPC memory cycles are “Continuous” if the Idle count between two LPC memory cycles is smaller than LPCIT
clocks.

Index: F8h

Bit R/W Default Description

7-6 - ­5-4 R/W 01b

Reserved
Continuous LPC Burst Threshold (CLPCBT)

Define the threshold count to start LPC Burst Window.

00b: 1 Continuous LPC cycle
01b: 5 Continuous LPC cycles
10b: 9 Continuous LPC cycles
11b: 13 Continuous LPC cycles

3-0 R/W 1000b

LPC Idle Threshold (LPCIT)

Define the threshold count to be a “Continuous” LPC memory access.

0000b: Disable LPC Burst
Otherwise: LPCIT*4 + 3 clocks (7 ~ 59 clocks)
Default value is 35 clock

Note LPC Burst is controlled by DLPCB bit in FPCFG register, too.

6.2.8 Real Time Clock (RTC) Configuration Registers

This section lists default values for each register and more detailed information for this logical device. Some
register bits will be read-only if unused.

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Table 6-11. Host View Register Map via Index-Data I/O Pair, RTC Logical Device

7 0 Index

Super I/O Control

Reg

Logical Device Activate Register (LDA) 30h

Logical Device

Control

And Configuration I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) 61h

Registers I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) 62h

I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) 63h

Selected if Interrupt Request Number and Wake-Up on IRQ Enabled (IRQNUMX) 70h

LDN Register=10h Interrupt Request Type Select (IRQTP) 71h

RAM Lock Register (RLR) F0h
Date of Month Alarm Register Offset (DOMAO) F1h
Month Alarm Register Offset (MONAO) F2h

I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) 60h

Logical Device Number (LDN = 10h) 07h

Register Name

6.2.8.1 Logical Device Activate Register (LDA)
Index: 30h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.1 on page 51.

Refer to SIOEN bit in SIOCTRL and SIOEN bit in SIOCTRL Register.

6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])
Index: 60h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.2 on page 51.

6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])
Index: 61h

Bit R/W Default Description

7-0 R/W 70h

Refer to section 6.2.3.3 on page 51.

Bit 0 (IOBAD0[0]) is forced to 0b and can’t be written.
It means the base address is on the 2-byte boundary.

6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])
Index: 62h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.4 on page 51.

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6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0])
Index: 63h

Bit R/W Default Description

7-0 R/W 72h

Refer to section 6.2.3.5 on page 52.

Bit 0 (IOBAD0[0]) is forced to 0b and can’t be written.
It means the base address is on the 2-byte boundary.

6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
Index: 70h

Bit R/W Default Description

7-0 R/W 08h

Refer to section 6.2.3.6 on page 52.

6.2.8.7 Interrupt Request Type Select (IRQTP)
Index: 71h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.7 on page 52.

6.2.8.8 RAM Lock Register (RLR)
Index: F0h

Bit R/W Default Description

7 R/W 0b

Block Standard RAM R/W (CMOSSRW)

0: R/W to 38h-3Fh of the Standard RAM is allowed.
1: Not allowed. Writes are ignored and reads return FFh.

6 R/W 0b

Block RAM Write (CMOSW)

0: Write to Standard and Extended RAM is allowed.
1: Not allowed. Writes are ignored.

5 R/W 0b

Block Extended RAM Write (CMOSEW)

0: Write to bytes 00h-1Fh of the Extended RAM is allowed.
1: Not allowed. Writes are ignored.

4 R/W 0b

Block Extended RAM Read (CMOSER)

0: Read from bytes 00h-1Fh of the Extended RAM is allowed.
1: Not allowed. Reads return FFh.

3 R/W 0b

Block Extended RAM R/W (CMOSERW)

0: R/W to the Extended RAM 128 bytes is allowed.
1: Not allowed. Writes are ignored and reads return FFh

2-0 - 0h

Reserved

6.2.8.9 Date of Month Alarm Register Offset (DOMAO)
Index: F1h

Bit R/W Default Description

7 - 0b

6-0 R/W 49h

Reserved
Date of Month Alarm Register Offset (DOMAO)

It contains the index offset of “date of month alarm”.

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6.2.8.10 Month Alarm Register Offset (MONAO)
Index: F2h

Bit R/W Default Description

7 - 0b

6-0 R/W 4Ah

Reserved
Month Alarm Register Offset (MONAO)

It contains the index offset of “month alarm”.

6.2.9 Power Management I/F Channel 1 Configuration Registers

This section lists default values for each register and more detailed information for this logical device. Some
register bits will be read-only if unused.

Table 6-12. Host View Register Map via Index-Data I/O, PM1 Logical Device

7 0 Index

Register Name

Super I/O Control Reg Logical Device Number (LDN = 11h) 07h

Logical Device Activate Register (LDA) 30h

Logical Device Control I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) 60h

And Configuration I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) 61h

Registers I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) 62h

I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) 63h

Selected if Interrupt Request Number and Wake-Up on IRQ Enabled (IRQNUMX) 70h

LDN Register=11h Interrupt Request Type Select (IRQTP) 71h

6.2.9.1 Logical Device Activate Register (LDA)
Index: 30h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.1 on page 51.

6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])

It contains Data Register Base Address Register.

Index: 60h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.2 on page 51.

Bits 7-3 (IOBAD0[15:11]) are forced to 00000b and can’t be written.

6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])

It contains Data Register Base Address Register.

Index: 61h

Bit R/W Default Description

7-0 R/W 62h

Refer to section 6.2.3.3 on page 51.

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6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])

It contains Command/Status Register Base Address Register.

Index: 62h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.4 on page 51.

Bits 7-3 (IOBAD1[15:11]) are forced to 00000b and can’t be written.

6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0])

It contains Command/Status Register Base Address Register.

Index: 63h

Bit R/W Default Description

7-0 R/W 66h

Refer to section 6.2.3.5 on page 52.

6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
Index: 70h

Bit R/W Default Description

3-0 R/W 01h

Refer to section 6.2.3.6 on page 52.

6.2.9.7 Interrupt Request Type Select (IRQTP)
Index: 71h

Bit R/W Default Description

7-2 R/W 03h

Refer to section 6.2.3.7 on page 52.

6.2.10 Power Management I/F Channel 2 Configuration Registers

This section lists default values for each register and more detailed information for this logical device. Some
register bits will be read-only if unused.

Table 6-13. Host View Register Map via Index-Data I/O, PM2 Logical Device

7 0 Index

Register Name

Super I/O Control Reg Logical Device Number (LDN = 12h) 07h

Logical Device Activate Register (LDA) 30h

Logical Device Control I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) 60h

And Configuration I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) 61h

Registers I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) 62h

I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) 63h

Selected if Interrupt Request Number and Wake-Up on IRQ Enabled (IRQNUMX) 70h

LDN Register=12h Interrupt Request Type Select (IRQTP) 71h

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6.2.10.1 Logical Device Activate Register (LDA)
Index: 30h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.1 on page 51.

6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8])

It contains Data Register Base Address Register.

Index: 60h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.2 on page 51.

Bits 7-3 (IOBAD0[15:11]) are forced to 00000b and can’t be written.

6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0])

It contains Data Register Base Address Register.

Index: 61h

Bit R/W Default Description

7-0 R/W 68h

Refer to section 6.2.3.3 on page 51.

6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8])

It contains Command/Status Register Base Address Register.

Index: 62h

Bit R/W Default Description

7-0 R/W 00h

Refer to section 6.2.3.4 on page 51.

Bits 7-3 (IOBAD1[15:11]) are forced to 00000b and can’t be written.

6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD0[7:0])

It contains Command/Status Register Base Address Register.

Index: 63h

Bit R/W Default Description

7-0 R/W 6Ch

Refer to section 6.2.3.5 on page 52.

6.2.10.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)
Index: 70h

Bit R/W Default Description

7-0 R/W 01h

Refer to section 6.2.3.6 on page 52.

6.2.10.7 Interrupt Request Type Select (IRQTP)
Index: 71h

Bit R/W Default Description

7-0 R/W 03h

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Refer to section 6.2.3.7 on page 52.

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6.2.11 Programming Guide

To read or write the target register (TR)

at target address(TA) of PNPCFG

Host Side

Approach 1

Host Domain Function

Host Side

To read or write the target register (TR)

at target address(TA) of PNPCFG

Approach 2

To read or write the target register (TR)

Host Side

at target address(TA) of PNPCFG

Approach 3

Hw strap BADDR=00

Write TA to IO port

2Eh

by LPC IO cycle

Read or write TR

at IO port 2Fh

by LPC IO cycle

To read or write the target register (TR)

Host Side

at target Index (TI) of PNPCFG

TI = 00h~2Eh

(Assume BADDR=00)

Hw strap BADDR=01

Write TA to IO port

4Eh

by LPC IO cycle

Read or write TR

at IO port 4Fh

by LPC IO cycle

Hw strap BADDR=03

Write TA to IO port

(SWCBAHR,SWXBALR)

by LPC IO cycle

Read or write TR

at

(SWCBAHR,SWXBALR+1)

by LPC IO cycle

Host Side

To read or write the target register (TR)

at target Index(TI) of PNPCFG

TI=30h~FEh, belongs to target logical device (TLD)

(Assume BADDR=00)

Write 07h to IO port 2Eh

by LPC IO cycle

Write TLD to IO port 2Fh

by LPC IO cycle

Write TI to IO port 2Eh

by LPC IO cycle

Read or write TR

at IO port 2Fh

by LPC IO cycle

Write TI to IO port 2Eh

by LPC IO cycle

Read or write TR

at IO port 2Fh

by LPC IO cycle

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To active the target logical device (TLD)

of PNPCFG

Write 07h to IO port 2Eh

by LPC IO cycle

Write TLD to IO port 2Fh

by LPC IO cycle

Write 61h to IO port 2Eh

Write a new value to IO port 2Fh

if the default value is not wanted

Write 63h to IO port 2Eh
Write a new value to IO port 2Fh
if the default value is not wanted

Write 71h to IO port 2Eh

Write a new value to IO port 2Fh

if the default value is not wanted

LDA

IOBAD0

IOBAD1

IRQNUMX

Write 60h to IO port 2Eh
Write a new value to IO port 2Fh
if the default value is not wanted

Write 62h to IO port 2Eh

Write a new value to IO port 2Fh

if the default value is not wanted

Write 70h to IO port 2Eh
Write a new value to IO port 2Fh

if the default value is not wanted

RTC and SMFI logical device have

more special registers to be filled

Write 30h to IO port 2Eh
Write 01h to IO port 2Fh

to active this logical device

Note: To enable an interrupt to host side through

SERIRQ, the firmware enables it in registers at

PNPCFG and relative registers in EC side.

Figure 6-2. Program Flow Chart for PNPCFG

See also section 7.12.5 on page 239 for accessing PNPCFG through EC2I.

IOBAD0

IOBAD1

IOBAD0

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Host Domain Function

6.3 Shared Memory Flash Interface Bridge (SMFI)

6.3.1 Overview

The bridge provides the host to access the shared memory. It also provides EC code address space mapped
into host domain address space, and locking mechanism for read/write protection.

6.3.2 Features

 Supports memory mapping between host domain and EC domain
 Supports read/write/erase flash operations and locking mechanism
 Supports two shared memory access paths: host and EC
 Supports two flash contents protection: different access paths and different memory block
 Supports timing control for memory device (flash)

6.3.3 Function Description

6.3.3.1 Flash Requirement

“Read Cycle Time” and “Write Cycle Time” of the flash/EPROM have to be faster than or equal to t

FRDD

(Refer

to Table 9-8. Flash Read Cycle AC Table).

6.3.3.2 Host to M Bus Translation

The SMFI provides an interface between the host bus and the M bus, the flash is mapped into the host memory
address space for host accesses, the flash is also mapped into the EC memory address space for EC
accesses.
An M bus transaction is generated by the host bus translations and has the following three types:

• 8-bit LPC Memory Read/Write

• 8-bit FWH Read/Write

• 8-bit Indirect Memory Read/Write

After the LPC address translation is done, the host memory transaction is forwarded to M-bus (flash interface) if
it is accessing an unprotected region. The host side can’t issue a write transaction until the firmware write 1 to
HOSTWA bit SMECCS register. See also Table 3-3 on page 8 and Table 3-4 on page 8.

Note: The flash bus doesn’t have the highest performance until writing 00h to MZCFG register and 08h to

SMZCFG register.

6.3.3.3 Memory Mapping

The host memory addresses are mapped into the following regions shown in the following table. Some regions
are always mapped and some are mapped only when the corresponding register is active. And these regions
may be mapped into the same range in the flash space. See also Table 3-1 on page 8.

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Table 6-14. Mapped Host Memory Address

Memory Address Range

(byte)

FFC0_0000h-FFFF_FFFFh

386 Mode BIOS Range

Region Description

This is the memory space whose maximum value is up to
4M bytes.
If the flash size defined in FMSSR register is smaller than
4M bytes, the remaining space is treated as “Out of
Range”

000F_0000h-000F_FFFFh

Legacy BIOS Range

The total is 64K inside lower 1M legacy BIOS range.

000E_0000h-000E_FFFFh

Extended Legacy BIOS Range

The total is 64K inside lower 1M legacy BIOS range.

Following memory transactions are based on LPC, FWH or I/O Cycles which are valid only when corresponding
LPCMEN/FWHEN bit in SHMC register is enabled.

Legacy BIOS Range

Always handle.

Extended Legacy BIOS Range

Handle only when BIOSEXTS bit in SHMC register is active. Otherwise, transactions are ignored.

386 Mode BIOS Range

Always handle.

User-Defined Shared Memory Space

Handle only when USRMEM bit in SHMC register is active. Otherwise, transactions are ignored.

Indirect Memory Address

Indirect Memory Cycles are memory transactions based on LPC I/O Cycles.
This address specified in SMIMAR3-0 is used as follows:
Translated 32-bit host address = { SMIMAR3[7:0], SMIMAR2[7:0], SMIMAR1[7;0], SMIMAR0[7:0]}

6.3.3.4 Indirect Memory Read/Write Transaction

The following I/O mapped registers can be used to perform an M bus transaction using an LPC I/O transaction:

• Indirect Memory Address registers (SMIMAR 3-0)

Stand for host address bit 31 to 0.

• Indirect Memory Data register (SMIMDR)

Stand for read or write data bit 7 to 0.

When LPC I/O writes to IMD register, SMFI begins a flash read with SMIMAR3-0 as the addresses. IT8510
responses Long-Waits until the transaction on M-bus (flash interface) is completed.
When LPC I/O read cycle from SMIMDR register begins a flash write with using the SMIMAR3-0 as the address.
The data back from SMIMDR register is used to complete the LPC I/O read cycle.
The indirect memory read/write transactions use the same memory mapping and locking mechanism as the
LPC memory read/write transactions.

6.3.3.5 Locking Between Host and EC Domains

A hardware arbiter handles flash read/write translation between the host and EC side. Normally the grant is
parked on the EC side and switches to the host side when the memory transaction on LPC bus (see also section

6.2.7.12 and 6.3.3.9).

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Host Domain Function

If the EC side is code fetching, any host access will be deferred or aborted depending on HERES bit in
SMECCS register.
If the host side is accessing, the EC side is pending to code fetch.
When the host wants to erase or program the flash, the signaling interface (Semaphore Write or KBC/PMC
extended command) notifies the firmware to write 1 to HOSTWA bit in SMECCS register and relative register
listed in Table 3-3 on page 8. EC 8032 should fail to code fetch due to flash busying for erasing/programming
and Scratch ROM should be applied (see also section 6.3.3.8). Once the host accessing to the flash is
completed, the host should indicate this to the EC, allowing EC to clear HOSTWA bit and resume normal
operation. The EC can clear HOSTWA bit at any time, and prevent the host from issuing any erase or program
operations.

6.3.3.6 Host Access Protection

The software can use a set of registers to control the host read/write protection functionality. The protection
block can be divided into two types: 8k size and 64k size; the block’s read/write protection flags may be set
individuality. A Lock Protect flag may prevent read/write protection flag from changing in the future.

Once locked, the lock bit and the read/write enable bits may be restored only after host domain hardware reset.
The EC can override the host settings and prevent host access to certain regions of the shared memory. The
override may be set individuality for read and write. In the first 128 Kbytes of address space, each EC-controlled
block is 8 Kbytes. For the rest of the memory space, the blocks are 64 Kbytes each.

See Table 3-4 on page 8 for the details.

After reset, all memory ranges are allowed host read but inhibited to write (erase/program).

6.3.3.7 Response to a Forbidden Access

A forbidden access is generated by a translated host address which is protected.
The EC responds to a forbidden access by generating an interrupt INT23 (if enabled by HERRIEN bit in
SMECCS register). HWERR and HRERR in the SMECCS register indicate the forbidden access to write or read
respectively .The response on the host bus is according to the HERES set in the SMECSS.

BIT(HERES):

00: Drive Long Wait for read; ignore write
01: Read back 00h; ignore write
10: Drive error SYNC for both read and write
11: Read back long sync; write back error sync

6.3.3.8 Scratch SRAM

This SRAM is scratch SRAM, which can be located at data space or code space (BUT not the same time).
Where it is located depends on Scratch SRAM Map Control (SSMC) in FBCFG register. It is called Scratch
RAM when being located at data space and called Scratch ROM when being located at code space.
Scratch ROM is mapped to the top of 2KB of EC code size, that is, 62K ~ 64K.
Code space of 0K ~ 62K is always mapped into the external flash space.
Code space of 62K ~ 64K may be mapped into the external flash space or Scratch ROM.
Refer to
Figure 3-3 on page 9 for the details.

Application:
When programming flash is processing, the flash will be busy and code fetch from flash by 8032 and will be
invalid and cause 8032 fail to execute instructions. It means the firmware must copy necessary instructions from
code space (by MOVC instruction) to Scratch SRAM, switch Scratch SRAM to Scratch ROM, and jump to
Scratch ROM before programming flash.

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Flash Programming Steps:
(a) The host side communicates to EC side via KBC/PMC extended or semaphore registers
(b) EC side: Write 1 to HOSTWA bit in SMECCS register
(c) EC side: Write 0 to SMECOWPR0-9 (for example, 4-M bytes range)

(Write is allowed in host side, and read is allowed in default.)

(Refer to Table 3-3. Flash Read/Write Protection Controlled by EC Side on page 8)
(d) EC side: Copy necessary code to Scratch RAM
(e) EC side: Make the host processor enter SMM mode if necessary
(f) EC side: Switch to Scratch ROM by SSMC bit in FBCFG register
(g) EC side: Jump instruction to Scratch ROM
(h) Host side: Remove protection in the host side

(Refer to Table 3-4. Flash Read/Write Protection Controlled by Host Side on page 8)
(i) Host side: Set relative memory-write registers in South-Bridge
(j) Host side: Start flash programming
(k) End flash programming and reset EC domain if necessary.

(Refer to section 5.5 on page 29)

6.3.3.9 No-wait Mode

Normally the M-bus grant parks on the 8032 side for code fetch and switches to the LPC side if memory
transactions on LPC bus. No-wait mode and Wait mode defines how M-bus grants to LPC side. IT8510 drives
Long-Wait sync until flash data is ready.

No-wait mode: All is hardware implemented and flash access switch to LPC Memory/FWH access immediately
if requested regardless of firmware. The firmware must enter No-wait mode before entering Idle/Doze/Sleep
mode.

Table 6-15. M-bus Grant Behavior

M-bus Grant

Status

Interleave M-bus grant parks on EC side

and switches to host side (LPC)
back and forth if the host side
issues memory access.

LPC Burst Host side (LPC) owns the

M-bus for a while and EC side
cannot access at the same

Description Register Configuration Note

To prevent entering “LPC Burst”
status, assign the value of LPCIT
field in LPCMCTRL register as
0000b.

The value of LPCIT field in
LPCMCTRL register is greater
than 0000b.

time.

If host side (LPC) starts
memory access, this status will
be entered from “EC Occupy”
status with Idle/Doze mode or
Interleave status and it
automatically exists when host
side stops memory access.

Concurrent Host side owns the M-bus and

EC executes code-fetch from
Scratch ROM at the same time.

SSMC bit in FBCFG register is
1b. (Scratch ROM)

Scratch RAM is not
available when Scratch
ROM mode.

6.3.3.10 Flash Interface

• Late Write and Early Write

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La te Write

Flash Clock

FA[21:0]

FRD#

FWR#

FCS#

FD[7:0]

*NOTE1 *NOTE2

Tidle T1 T

insert 1T

WAITN

=7 to 0 T2 T

Host Domain Function

HOLDN

=3 to 0 Tdone Tidle

Tidle T1 T

Early Write

Flash Clock

FA[21:0]

FRD#

FWR#

FCS#

FD[7:0]

insert 1T

• Fast Read and Normal Read

*NOTE1 *NOTE2

Tidle T1 T

Normal Read

Flash Clock

FA[21:0]

FWR#

FRD#

FCS#

FD[7:0]

Fast Read

insert 1T

*NOTE3

Tidle T1 T

WAITN

=7 to 0 T2 T

Figure 6-3. Late Write and Early Write

WAITN

=7 to 0 T2 T

WAITN

=7 to 0 T

HOLDN

=3 to 0 Tdone Tidle

HOLDN

=3 to 0 Tdone Tidle

HOLDN

=3 to 0 Tdone Tidle

Flash Clock

FA[21:0]

FWR#

FRD#

FCS#

FD[7:0]

insert 1T

Figure 6-4. Fast Read and Normal Read

Note 1: Tidle cycle inserted when ICBBC = 1 in SMZCFG register.
Note 2: Tidle cycle inserted when ICABC = 1 in SMZCFG register.
Note 3: Fast Read cycles represent when FRE = 1 in SMZCFG register
Note 4:

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Flash Clock Frequency = (EC Clock Frequency) / (FTDIV +1)
T

= WAITN value in MZCFG register

WAITN

T

= HOLDN value in MZCFG register

HOLDN

• Host Memory Read/Write Minimum Latency
The followings are the performance of host memory access, which is based on 10 MHz EC clock.
The firmware should detect the host side status by LPCRST# or others, and switch EC clock to the highest 10
MHz to get the best performance of host memory access.

LPC Bus T1 T2 T3 T11 T12 T27 T28 T29 T30 Trou Trou T1

LPCCLK (33Mhz)
LFRAME#
LAD[3:0]

FDCF 0F D

M Bus Tidle

Flash Clock (e.g. 10 Mhz)
FA[21:0]

Tf2cs = 23 ~24 T

FCS#
FRD#
FWR#
FD[7:0]

Note : 1. Tf2a denote lpc frame assert to lpc memory address ready, need 10 ~11 T ( LPC Clock)

2. Tf2cs denote lpc frame assert to flash chip select active, need 23 ~24 T ( LPC Clock)

3. To2r denote flash read data output to first LPC nibble read data output, need 1 ~2 T ( LPC Clock)

4. Clk_fls is programmed into clk_ec (FMPSR register set to 0 ) ;

t1 t2 Tidle

To2r

Hold time/Wait time is set to 0 (FBCFG=02h; MZCFG=0h; SMZCFG=08H); in no-wai t mode;

Figure 6-5. Minimum Latency Timing of Flash Memory Read Cycle

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LPC Bus T1 T2 T3 T11 T12 T19 T20 Trou Trou

LPCCLK (33Mhz)
LFRAME#
LAD[3:0]

FDCF 0F

M Bus Tidle

Flash Clock (e.g. 10 Mhz)
FA[21:0]

FCS#
FRD#
FWR#
FD[7:0]

Note : 1. Tf2a denote lpc frame assert to lpc m emory address ready, need 10 ~11 T ( LPC Clock)

Tf2cs = 12 ~13 T

2. Tf2cs denote lpc frame assert to flash chip select active, need 12~13T ( LPC Clock)

3. To2r denote flash read data output to first LPC nibble read data output, need 1 ~2 T ( LPC Clock)

4. Clk_fls is programmed into clk_ec (FMPSR register set to 0 ) ;

old time/Wait time

H

set to 0 (FBCFG=02h; MZCFG=0h; SMZCFG=08H); in no-wait mode;

is

t1 t2

To2r

Figure 6-6. Minimum Latency Timing of Flash Memory Read Cycle in LPC Burst

LPC Bus T1 T2 T3 T11 T12 T32 T33 T34 T35 T36 Trou Trou T1

LPCCLK (33Mhz)
LFRAME#
LAD[3:0]

FECF 0F 6 0F D

M Bus

Flash Clock (e.g. 10 Mhz)
FA[21:0]

Tf2cs = 26 ~27 T

FCS#
FWR#
FRD#
FD[7:0]

Tf2wh = 33 ~34 T

Note : 1. Tf2a denote lpc frame assert to lpc memory address ready, need 10 ~11 T ( LPC Clock)

2. Tf2cs denote lpc frame assert to flash chip select active, need 26 ~27 T ( LPC Clock)

3. Tf2wh denote lpc frame assert to flash write go high, need 33 ~34 T ( LPC Clock)

4. Clk_fls is programmed into clk_ec (FMPSR register set to 0 ) ;

t1 t2 t3 Tidle

Hold time/Wait time is set to 0 (FBCFG=02h; MZCFG=0h; SMZCFG=08H); in no-wai t mode;

Figure 6-7. Minimum Latency Timing of Flash Memory Write Cycle

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6.3.4 EC Interface Registers

The registers of SMFI can be divided into two parts: Host Interface Registers and EC Interface Registers and
this section lists the EC interface. The EC interface can only be accessed by the internal 8032 processor. The
base address for SMFI is 1000h.

These registers are listed below.

Table 6-16. EC View Register Map, SMFI

7 0 Offset

FBIU Configuration (FBCFG) 00h

Flash Programming Configuration Register (FPCFG) 01h

Memory Zone Configuration (MZCFG) 02h

State Memory Zone Configuration (SMZCFG) 03h

Flash EC Code Banking Select Register (FECBSR) 05h

Flash Memory Size Select Register (FMSSR) 07h

Flash Memory Prescaler (FMPSR) 10h

Shared Memory EC Control and Status (SMECCS) 20h

Shared Memory Host Semaphore (SMHSR) 22h
Shared Memory EC Override Read Protect (SMECORPR0-5) 23h-28h
Shared Memory EC Override Read Protect (SMECORPR6-9) 11h-14h
Shared Memory EC Override Write Protect (SMECOWPR0-5) 29h-2Eh
Shared Memory EC Override Write Protect (SMECOWPR6-9) 15h-18h

6.3.4.1 FBIU Configuration Register (FBCFG)

The FBIU (Flash Bus Interface Unit) directly interfaces with the flash device. The FBIU also defines the access
time to the flash base address from 00_0000h to 3F_FFFFh (4M bytes). EWR bit controls memory cycles on
M-bus (flash interface).

Address Offset: 00h

Bit R/W Default Description

7 - 0b

Scratch SRAM Map Control (SSMC)

0: Scratch RAM (data space).
1: Scratch ROM (code space).

6 - 0h

Override Hardware Strap SHBM (OVRSHBM)

Override hardware strap SHBM and always treat its result as 1.

5 - 0h

Override Hardware Strap BADDR1-0 (OVRBADDR)

Override hardware strap BADDR1-0 and always treat its result as 10b.

4-2 - 0h

1 R/W 1b

Reversed
Reversed

Always writing 1 to this bit.

0 R/W 1b

Early Write (EWR)

0: Late write.
1: Early write.

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6.3.4.2 Flash Programming Configuration Register (FPCFG)

This register provides general control on banking and flash standby.

Address Offset: 01h

Bit R/W Default Description

7 R/W 1b

Banking Source Option (BSO)

0: Use 8032 P1[0] and P1[1] as code banking source.
1: Use ECBB[1:0] in FECBSR register as code banking source.
Using P1 as banking source has less instruction count since only

“MOV” is invoked rather than “MOVX”, although T2 and T2EX are

used in other bits in P2.

6 R/W 1b

Auto Flash Standby (AFSTBY)

1: Make the flash enter the standby mode by driving FCS# high when

EC is in the Idle/Doze/Sleep mode

0: Prevent the flash from entering the standby mode

5 R/W 1b
4 R/W 1b

Reserved
Disable LPC Burst (DLPCB)

0: LPC Burst mode is dependent on LPCMCTRL register in the host

side.

1: LPC Burst mode is disabled. (default)

3-1 R/W 1111b

0 R/W 1b

Reserved
Host Side Protection Disable(HSPD)

0: Host side protection disabled, all read and write protection bits are

ignored in SMHAPR1~4 register.

1: Host side protection enabled, all read and write protection bits can

protect their memory block in SMHAPR1~4 register

6.3.4.3 Memory Zone Configuration Register (MZCFG)

The MZCFG register controls the configuration of the memory cycles on M-bus (flash interface).

Note: The flash bus doesn’t have the highest performance until writing 00h to MZCFG register and 08h to

SMZCFG register.

Address Offset: 02h

Bit R/W Default Description

7 - 0b
6 R/W 1b

Reserved
Wait on Burst Read (WBR)

When set 1, one wait state (TBW) is added on a burst read cycle.

0: No TBW
1: TBW

5 R/W 0b

4-3 R/W 11b

Reserved
Hold Number (HOLDN)

Number of Thold clock cycles.

4-3 Number
000 : none
001 : One
010 : Two
011 : Three(default)

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Bit R/W Default Description

2-0 R/W 111b

Wait Number (WAITN)

Number of TIW clock cycles
The following bits are invalid when the FRE bit in SMZCFG register is set to1.

2-0 Number
000 : none
001 : One
010 : Two
011 : Three
100 : Four
101 : Five
110 : Six
111 : Seven(default)

6.3.4.4 Static Memory Zone Configuration Register (SMZCFG)

The SMZCFG register also controls the configuration of the memory cycles on M-bus (flash interface).

Note: The flash bus doesn’t have the highest performance until writing 00h to MZCFG register and 08h to

SMZCFG register.

Address Offset: 03h

Bit R/W Default Description

7-4 - 0h

3 R/W 0b

Reserved
Fast Read Enable (FRE)

0: Normal read cycle takes at least two clock cycles
1: Normal read cycle takes one clock cycles

2 R/W 1b

Idle Clock Before Bus Cycle (ICBBC)

Inserts an idle clock before the current cycle when the next cycle is in a
different zone.

0: No idle cycle inserted
1: idle cycle inserted

1 R/W 1b

Idle Clock After Bus Cycle (ICABC)

Insert an idle clock followed the current cycle when the next cycle is in a
different zone.

0: No idle cycle inserted
1: Idle cycle inserted

0 - 0b

Reserved

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6.3.4.5 Flash EC Code Banking Select Register (FECBSR)

The register is used to select EC banking area Bank 0~3 when BSO =1 in FPCFG register.

Address Offset: 05h

Bit R/W Default Description

7-2 - 0h
1-0 R/W 00b

Reserved
EC Banking Block (ECBB)

When ECBB is set to 00, EC code uses conventional code area (maximum
64k) as code memory.
Common Bank 32k-byte flash mapping range is from 00_0000h to 00_7FFFh.
Bank 0 32k-byte flash mapping range is from 00_8000h to 00_FFFFh.
Bank 1 32k-byte flash mapping range is from 01_0000h to 01_7FFFh.
Bank 2 32k-byte flash mapping range is from 01_8000h to 01_FFFFh.
Bank 3 32k-byte flash mapping range is from 02_0000h to 02_7FFFh.
See also Figure 3-1 on page 6.
Bits 1-0:

00: Select Common Bank + Bank 0
01: Select Common Bank + Bank 1
10: Select Common Bank + Bank 2
11: Select Common Bank + Bank 3

If A15 of 8032 code memory equals to 0, select Common Bank, otherwise
select Bank 0, 1, 2 or 3.

6.3.4.6 Flash Memory Size Select Register (FMSSR)

The register provides the selection for the external flash memory size and the minimum size of the flash is
defined as 128K byte.

Address Offset: 07h

Bit R/W Default Description

7-6 - 0h
5-0 R/W 111111b

Reserved
Flash Memory Size Select (FMSS)

These bits select the external flash memory size and the maximum memory
size is 4M bytes.

Bits
5 4 3 2 1 0 Memory Size

1 1 1 1 1 1: 4M
0 1 1 1 1 1: 2M
0 0 1 1 1 1: 1M
0 0 0 1 1 1: 512K
0 0 0 0 1 1: 256K
0 0 0 0 0 1: 128K

Other: Reserved

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6.3.4.7 Flash Memory Prescaler Register (FMPSR)

This register selects the prescaler divider ratio. The value of the register is used to divide the EC clock.

Address Offset: 10h

Bit R/W Default Description

7-4 - 0h
3-0 R/W 0h

Reserved
Prescaler Divider Value (FTDIV)

This register value divides the EC clock into flash clock Frequency.
Flash Clock Frequency = (EC Clock Frequency) / (FTDIV +1)
Normally the EC clock frequency is 10 MHz and may be divided by CFSELR
register.
The valid FTDIV range is 0 to 15.

6.3.4.8 Shared Memory EC Control and Status Register (SMECCS)

The following set of registers is accessible only by the EC. The registers are applied to VSTBY.

This register provides the flash control and status of a restricted access.

Address Offset: 20h

Bit R/W Default Description

7 R/W 0b

Host Semaphore Interrupt Enable (HSEMIE)

It enables interrupt to 8032 via INT22 of INTC.

0: Disable the host semaphore (write) interrupt to the EC.
1: The interrupt is set (level high) if HSEMW bit is set.

6 R/WC 0b

Host Semaphore Write (HSEMW)

0: Host has not written to HSEM3-0 field in SMHSR register.
1: Host has written to HSEM3-0 field in SMHSR register. Writing 1 to

this bit to clear itself and clear internal detect logic. Writing 0 has no
effect.

5 R/W 0b

Host Write Allow (HOSTWA)

0: The SMFI does not generate write transactions on the M bus.
1: The SMFI can generate write transactions on the M bus.

4-3 R/W 00b

Host Error Response (HERES)

These bits control response types on read/write translation from/to a
protected address.

1-0 Number
00 : Drive Long Wait for read; ignore write
01 : Read back 00h; ignore write
10 : Drive error SYNC for both read and write
11 : Read back long sync; write back error sync

2 R/W 0b

Host Error Interrupt Enable (HERRIEN)

It enables interrupt to 8032 via INT23 of INTC.

0: Disable
1: The interrupt is set (level high) if HRERR or HWERR bit is set.

1 R/WC 0b

Host Write Error (HWERR)

0: No error is detected during a host-initiated write.
1: It represents the host write to a write-protected address. Writing 1 to

this bit clears it to 0. Writing 0 has no effect.

0 R/WC 0b

Host Read Error (HRERR)

0: No error is detected during a host-initiated read.
1: It represents the host reads to a read-protected address. Writing 1 to

this bit clears it to 0. Writing 0 has no effect.

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Host Domain Function

6.3.4.9 Shared Memory Host Semaphore Register (SMHSR)

This register provides eight semaphore bits between the EC and the host. Bits 3-0 may be set by the host and
Bits 7-4 may be set by the EC. The register is reset on host domain hardware reset.

This is the register the same as the one in section 6.3.5.7 but they are in different views.

Address Offset: 22h

Bit R/W Default Description

7-4 R/W 0h

EC Semaphore (CSEM3-0)

These four bits may be written by the EC and read by both the host and the
EC

3-0 R 0h

Host Semaphore (HSEM3-0)

These four bits may be written by the host and read by both the host and the
EC.

6.3.4.10 Shared Memory EC Override Read Protect Registers 0-9 (SMECORPR 0-9)

SMECORPR 0-9 are 8-bit registers that permit EC to override on the host read protection bits. To allow the host
to read a memory location, both the Host Read Protection bit controlled through the SMHAPR (1-2) and the
associated bit in SMECORPR 0-9 should be cleared. Each bit in this register is related with a memory block.
Bits in these registers may be Read Only or RW accroding to their position and the size of the EC and host boot
blocks.

Address Offset: 23h

Bit R/W Default Description

7-0 R/W 00h

Override Read Protect Low Address (ORPLA7-0)

Address Offset: 24h

Bit R/W Default Description

7-0 R/W 00h

Override Read Protect Low Address (ORPLA15-8)

Address Offset: 25h

Bit R/W Default Description

7-2 R/W 00h
1-0 - 0h

Override Read Protect (ORP7-2)
Reserved

Address Offset: 26h

Bit R/W Default Description

7-0 R/W 00h

Override Read Protect (ORP15-8)

Address Offset: 27h

Bit R/W Default Description

7-0 R/W 00h

Override Read Protect (ORP23-16)

Address Offset: 28h

Bit R/W Default Description

7-0 R/W 00h

Override Read Protect (ORP31-24)

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Address Offset: 11h

Bit R/W Default Description

7-0 R/W 00h

Override Read Protect (ORP39-32)

Address Offset: 12h

Bit R/W Default Description

7-0 R/W 00h

Override Read Protect (ORP47-40)

Address Offset: 13h

Bit R/W Default Description

7-0 R/W 00h

Override Read Protect (ORP55-48)

Address Offset: 14h

Bit R/W Default Description

7-0 R/W

00h

Override Read Protect (ORP63-56)

ORPLA15-0 (Override Read Protect Low Addresses 15 through 0).
ORP63-2 (Override Read Protect 63 through 2).
Each bit affects the host’s read capacity from one block. The block size is 8
Kbytes on the first low address (ORPLAi). For the other blocks, it is 64 Kbytes.
The block address is intended as follows:
Low Address Blocks, ORPLAi: from i*8K to (i+1)*8K-1
Other Blocks, ORPj: from j*64K to (j+1)*64K
Refer to Table 3-3 on page 8 for the details.

0: no override the host read
1: Host Read for this block is disabled regardless of the setting of

others.

The default values make all the flash ranges readable.

6.3.4.11 Shared Memory EC Override Write Protect Registers 0-9 (SMECOWPR0-9)

SMECOWPR0-9 are 8-bit registers that permit EC to override on the host write protection bits. For the host to
be able to write a memory location, both the Host Write Protection bit (controlled through the SMHAPR (1-2)
and the related bit in SMECOWPR0-9 should be cleared. Each bit in this register is related with a memory block.

Bits attribute in these registers may be Read Only or RW according to their positions, and all blocks and sizes.

Address Offset: 29h

Bit R/W Default Description

7-0 R/W 11111111b

Override Write Protect Low Address (OWPLA7-0)

Address Offset: 2Ah

Bit R/W Default Description

7-0 R/W 11111111b

Override Write Protect Low Address (OWPLA15-8)

Address Offset: 2Bh

Bit R/W Default Description

7-2 R/W 111111b
1-0 - 0h

Override Write Protect (OWP7-2)
Reserved

Address Offset: 2Ch

Bit R/W Default Description

7-0 R/W 11111111b

Override Write Protect (OWP15-8)

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Host Domain Function

Address Offset: 2Dh

Bit R/W Default Description

7-0 R/W 11111111b

Override Write Protect (OWP23-16)

Address Offset: 2Eh

Bit R/W Default Description

7-0 R/W 11111111b

Override Write Protect (OWP31-24)

Address Offset: 15h

Bit R/W Default Description

7-0 R/W 11111111b

Override Write Protect (OWP39-32)

Address Offset: 16h

Bit R/W Default Description

7-0 R/W 11111111b

Override Write Protect (OWP47-40)

Address Offset: 17h

Bit R/W Default Description

7-0 R/W 11111111b

Override Write Protect (OWP55-48)

Address Offset: 18h

Bit R/W Default Description

7-0 R/W

FFh

Override Write Protect (OWP63-56)

OWPLA15-0 (Override Write Protect Low Addresses 15 through 0).
OWP63-2 (Override Write Protect 63 through 2).
Each bit affects the host’s write capacity from one block. The block size is 8
Kbytes on the first low address ( OWPLAi). The other blocks are 64 Kbytes.
The block address is intended as follows:
Low Address Blocks, OWPLAi: from i*8K to (i+1)*8K-1
Other Blocks, OWPj: from j*64K to (j+1)*64K
Refer to Table 3-3 on page 8 for the details.

0: No override the host Write Protect
1: Host Write for this block is disabled regardless of the setting of

others

The default values make all the flash ranges readonly.

6.3.5 Host Interface Registers

The registers of SMFI can be divided into two parts: Host Interface Registers and EC Interface Registers and
this section lists the host interface. The host interface registers can only be accessed by the host processor.
The SMFI resides at LPC I/O space and the base address can be configured through LPC PNPCFG registers.
The SMFI logical device number is 0Fh (LDN=0Fh).
These registers are listed below

Table 6-17. Host View Register Map, SMFI

7 0 Offset

Shared Memory Indirect Memory Address (SMIMAR0-3) 00h-03H

Shared Memory Indirect Memory Data (SMIMDR) 04h

Shared Memory Host Access Protect (SMHAPR1-4) 07-Ah

Shared Memory Host Semaphore (SMHSR) 0Ch

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