ITE IT6605 Programming Manual
深圳市金合讯科技有限公司，0755-36853282，18664341585
IT6605 HDMI 1.4 3D Receiver
Programming Guide
Ver 1.00
Tseng, Jau-Chih
ITE T ech.
Last Update Date: 2010/12/07
深圳市金合讯科技有限公司，0755-36853282，18664341585
History
2010/08/10 – Created by Tseng, Jau-chih
2010/08/1 1 – Added Audio Part.
2010/12/07 – Added HDCP part.
深圳市金合讯科技有限公司，0755-36853282，18664341585
Index
Chap 1 Introduction..................................................................................................................1
Chap 2 Initial Progress .............................................................................................................2
Initial Progress..............................................................................................................................................2
Initial Value List ...........................................................................................................................................2
Chap 3 Video Output.................................................................................................................4
Video Output Flow .......................................................................................................................................4
Video Path....................................................................................................................................................5
Video Input Selection ...................................................................................................................................5
Video Output Configuration .........................................................................................................................6
Color Space Matrix.......................................................................................................................................7
Video I/O and Video Data I/O Tristate..........................................................................................................8
Event of Video Process.............................................................................................................................9
Video input mode resolution.......................................................................................................................10
Video CDR Reset........................................................................................................................................ 10
Chap 4 Audio Output...............................................................................................................11
Audio Control Registers.............................................................................................................................11
HDMI Audio Input Status...........................................................................................................................12
Audio Output Configure.............................................................................................................................13
Default Setting .......................................................................................................................................13
I2S mode and word length......................................................................................................................13
Output LPCM Audio on I2S Channel.........................................................................................................14
Output LPCM Audio on SPDIF Channel....................................................................................................14
Output NLPCM Audio on I2S Channel ......................................................................................................14
Output NLPCM Audio on SPDIF Channel.................................................................................................15
Output High Bit Rate on I2S Channel ........................................................................................................15
Output High Bit Rate on SPDIF Channel...................................................................................................15
Output LPCM/NLPCM Audio with Force Fs setting..................................................................................15
Error Handling ................................................................................................................. ........................... 16
Chap 5 HDMI Infoframe.........................................................................................................17
Chap 6 HDCP Support............................................................................................................19
HDCP Repeater setting...............................................................................................................................19
HDCP registers for repeater function .....................................................................................................21
HDCP Debug Status...............................................................................................................................22
Chap 7 3D Support..................................................................................................................23
Part 2 – Software Release Code Reference.....................................................................................26
Chap 8 Introduce.....................................................................................................................26
Chap 9 Flow............................................................................................................................27
Chap 10 Data T ype....................................................................................................................30
Chap 11 Sample Code Required Interface................................................................................31
Chap 12 Software Interface.......................................................................................................32
-i
深圳市金合讯科技有限公司，0755-36853282，18664341585
IT6605 PROGRAMMING GUIDE
Chap 1 Introduction
The IT6605 is a dual-port HDMI 1.4 receiver. The IT6605 with its Deep Color capability (up to 36-bit)
ensures robust reception of high-quality uncompressed video content, along with state-of-the-art
uncompressed and compressed digital audio content such as DTS-HD and Dolby TrueHD in digital
televisions and projectors.
Aside from the various video output formats supported, the IT6605 also receives and provides up to 8
channels of I
facilitating direct connection to industry-standard low-cost audio DACs. Also, an S/PDIF output is
provided to support up to compressed audio of 192kHz frame rate. Super Audio Compact Disc (SACD)
is supported at up to 8 channels and 88.2kHz through DSD (Direct Stream Digital ports) ports.
Each IT6605 comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.2
standard so as to provide secure transmission of high-definition content. Users of the IT6605 need not
purchase any HDCP key s or ROM s .
To program IT6605 need using I
under 100KHz. The I
PCADR (pin105) value.
To access the IT6605 internal registers should by the following protocol:
Read:
<I2C start>-<0x90|w >-<register index>-<I2C repeater start>-<0x90|r>-<data>(-…-<data>)-<I2C Stop>
Write:
<I2C start>-<0x90|w >-<register index>-<data>(-…-<data>)-<I2C Stop>
In the following document, the register with index will present as Reg<idx>.
Eg: Reg05 means the register with index 0x05.
2
S digital audio outputs, with sampling rate up to 192kHz and sample size up to 24 bits,
2
2
C address for accessing internal registers are 0x90 or 0x92 depends on the
C access the PCSDA (pin26) and PCSCL (pin27) with the frequency
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IT6605 PROGRAMMING GUIDE
Chap 2 Initial Progress
The first step of initial IT6605 is to reset the chip.
Activate SYSRSTN (pin100) with low voltage or write reg05[4] = ‘1’, will reset the chip.
When SYSRSTN is high voltage and reg05[4] = ‘0’, IT6605 is under normal operating mode.
Initial Progress
Set HPD (HDMI Connection Pin19) to low (if possible).
Reg06 = 0x00 to power on all modules.
Reg07[3:2] = ‘11’ to turn off the termination.
Reg05 = 0xA1
Reg16 = 0x0F
Reg17 = 0x07
Reg18 = 0x07
Reg8C = 0x00 (5~8 is for initial interrupt mask setting)
Load the default value.
Configure the HDCP repeater setting
Receiver mode, reg73[7:4] = ‘0000’
Repeater mode, reg73[7:4] = ‘1000’
Delay about 500ms to make sure the HPD off enough.
Reg07[3:2] = ‘00’
Set HPD to high (if possible).
Initial Value List
reg05 = 0x20
reg08 = 0xAE
reg1D = 0x20
reg3B=0x40
reg56=0x01
reg68=0x03
reg6B=0x11
Reg6C=0x00
Reg93=0x43
Reg94=0x4F
Reg95=0x87
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Reg96=0x33
Reg97=0x0E
Reg9B=0x01
IT6605 PROGRAMMING GUIDE
Reg1A/Reg1B/Reg1C/R eg 3 D[7:6] for the output video format, refer to
Reg75/Reg76/Reg78 for the output audio format, refer to
Audio Output.
Video Output.
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IT6605 PROGRAMMING GUIDE
Chap 3 Video Output
IT6605 receive the HDMI or DVI video input, and output up to 30 bit TTL with numerous format, this
chapter describe how to configure the video path and video output.
Video Output Flow
IT6605 output video when it got a valid video input.
10 Sys_state RO
7 RXPLL_LOCK HDMI PLL locked
6 RXCK_Speed ‘1’ – Lower than 80MHz
‘0’ – Higher than 80MHz
5 RXCK_VALID ‘1’ – RX CLK Valid
4 HDMI_MODE ‘1’ – HDMI Mode
‘0’ – DVI Mode
Only reliable when SCDT on.
3 P1_PWR5V_DET (For CAT6023/IT6605)
‘1’ for HDMI input port 1 with
5V presented
2 SCDT ‘1’ – Sync Detected.
‘0’ – Otherwise.
1 VCLK_DET ‘1’ – VCLK Detect
‘0’ – Otherwise
0 PWR5V_DET ‘1’ - HDMI input port 0 with 5V
present.
The following steps are for getting the valid vi deo output:
IT6605 should detect 5V in corresponding HDMI port.
IT6605 gets valid SCDT (with SCDT status bit present and no SCDT off interrupt present).
Configure the video path of IT6605.
Reset video FIFO (reg1C[1] = ‘1’ → ‘0’).
Turn off the video I/O and video data tri-state.
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IT6605 PROGRAMMING GUIDE
Video Path
The video path of IT6605 are defined with video input, color space converting, and video output signal
format, as the figure:
Force Indicate
RGB 444
Input Color mode
DVI
Input
HDMI
Input
to RGB444
422 to 444
converting
Up/Down
Filter
Color
Space
Convert
Up/Down
Filter
444 to 422
converting
YCbCr444
YCbCr422
YCbCr422
Embedded
Sync
YCbCr422
Embedded
Sync
CCIR656
HDMI input contain up to 36 bits (which IT6605 su pported) RGB444, YCbCr444, or YCbCr422
TMDS input with AVI infoframe indicated. DVI input supports only RGB444 video input. The input
color are indicated by reg20 or AVI infoframe, and convert to output color space by color space
converting matrix (CSC Matrix), then output by color mapping registers and output format controls
registers
1B Video_map W/R
6
5
4
3
2
1
0
1C Video_Ctrl1 W/R 7
6
5
4
3
2
1
0
chSyncpol
Swap_O16b
Swap_Ch422
Swap_OutRB
Swap_ML
Swap_Pol
Swap_RB
DNFreeGo
SyncEmb
EN_Dither
EnUdFilt
OutDDR
2x656CLK
656FFRst
EnAVMuteRst
0000000 Referring to the map table of Emily.
0x00 Default: dithering and up/dn filter is enabled
2x656CLK:
1:an 2x 656CLK is generated by PLL
0:no 2x656 CLK
The detail step are describe in following section.
Video Input Selection
When SCDT and RXCK_Valid are both present, the video input is reliable. If the HDMI_MODE bit is
‘0’, the input is an DVI input mode and default treated as 24bit RGB444 video input, otherwise the
input mode should be explained as an HDMI mode with AVI infoframe supported. If the AVI infoframe
is not presented, some testing case ask HDMI Rx to receive the input video as an RGB444 mode.
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IT6605 PROGRAMMING GUIDE
Forcecolmod:
20 CSC_CTRL W/R 7
6
5
4
3:2
1:0
VDGatting
VDIOLDisable
VIOSel
ForceColMod
ColMod_Set
CSCSel
For DVI mode, the register setting should be reg20[4] = ‘1’ to ignore the AVI Infoframe bit value, and
set reg20[3:2] = ‘00’ as RGB444 mode.
For HDMI mode, to refer the AVI infoframe color mode, reg20[4] should be ‘0’ that IT6605 will refer
the AVI infoframe PB[1][6:5] as input color mode.
The received AVI infoframe of IT6605 is stored in regAD ~ regBA with 13 bytes.
AB AVI_leng RO
AC AVI_VER RO
AD AVI_DB0 RO
AE AVI_DB1 RO
AF AVI_DB2 RO
B0 AVI_DB3 RO
B1 AVI_DB4 RO
B2 AVI_DB5 RO
B3 AVI_DB6 RO
B4 AVI_DB7 RO
B5 AVI_DB8 RO
B6 AVI_DB9 RO
B7 AVI_DB10 RO
B8 AVI_DB11 RO
B9 AVI_DB12 RO
BA AVI_DB13 RO
0x00
0:color mode auto adjusted according to AVI
info
1: color mode is forced by register
Where Y1/Y0 are defined in CEA861/B spec, as following figure:
IT6605 will refer the input color space by regAE[6:5] or reg20[3:2] by reg20[4] selection, to decid e the
decoding of input colors.
Video Output Configuration
The video output format are controlled by reg1B and reg1C, and the output selection are controlled as
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following table:
IT6605 PROGRAMMING GUIDE
1B Video_map W/R
1C Video_Ctrl1 W/R 7
Reg1B
Video_map
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Sync separated
RGB444
XX X
chSyncpol
6
Swap_O16b
5
Swap_Ch422
4
Swap_OutRB
3
Swap_ML
2
Swap_Pol
1
Swap_RB
0
DNFreeGo
SyncEmb
6
EN_Dither
5
EnUdFilt
4
OutDDR
3
2x656CLK
2
656FFRst
1
EnAVMuteRst
0
chSyncpol
Swap_O16b
0000000 Referring to the map table of Emily.
0x00 Default: dithering and up/dn filter is enabled
Swap_Ch422
Swap_OutRB
Swap_ML
Swap_Pol
2x656CLK:
1:an 2x 656CLK is generated by PLL
0:no 2x656 CLK
Reg1C
Video_Ctrl1
Swap_RB
DNFreeGo
SyncEmb
EN_Dither
EnUdFilt
OutDDR
2x656CLK
656FFRst
EnAVMuteRst
Sync separated
YCbCr444
Sync separated
24 bit YCbCr422
Sync separated
16 bit YCbCr422
Sync Embedded
16 bit YCbCr 422
Sync Embedded
8 bit YCbCr 422
(CCIR656)
XX X
X X
√ X X √ √ √
√ X X √ √ √ √
√ X X √ √ √ √ √
√ : Must set
X : Depends on the output mapping.
The above setting only decide the output signal format, the output color space are defined in the reg3D,
for determining the output:
Reg Name Type Bit Name Default value Description.
3D PG_CTRL2 W/R 7:6 OutColMod 10 ‘00’ – RGB444
‘01’ – YCbCr422
‘10’ – YCbCr444
To set RGB444, YCbCr422, or YCbCr444 also need to set reg3D[7:6] value.
Usually the output configuration is fixed in one type, thus the setting could be th e initial value.
Color Space Matrix
The color space register are defined in reg21~reg35, as following:
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IT6605 PROGRAMMING GUIDE
20 CSC_CTRL W/R 7
21 CSC_YOFF W/R 7:0 0x10
22 CSC_COFF W/R 7:0 0x80
23 CSC_RGBOFF W/R 7:0 0x00
24 CSC_MTX11_L W/R 7:0 0xb2
25 CSC_MTX11_H W/R 5:0 000100
26 CSC_MTX12_L W/R 7:0 0x64
27 CSC_MTX12_H W/R 5:0 000010
28 CSC_MTX13_L W/R 7:0 0xE9
29 CSC_MTX13_H W/R 5:0 000000
2A CSC_MTX21_L W/R 7:0 0x93
2B CSC_MTX21_H W/R 5:0 011100
2C CSC_MTX22_L W/R 7:0 0x16
2D CSC_MTX22_H W/R 5:0 000100
2E CSC_MTX23_L W/R 7:0 0x56
2F CSC_MTX23_H W/R 5:0 011111
30 CSC_MTX31_L W/R 7:0 0x49
31 CSC_MTX31_H W/R 5:0 011101
32 CSC_MTX32_L W/R 7:0 0x9f
33 CSC_MTX32_H W/R 5:0 011110
34 CSC_MTX33_L W/R 7:0 0x16
35 CSC_MTX33_H W/R 5:0 000100
6
5
4
3:2
1:0
VDGatting
VDIOLDisable
VIOSel
ForceColMod
ColMod_Set
CSCSel
0x00
Forcecolmod:
0:color mode auto adjusted according to AVI info
1: color mode is forced by register
And the value of color space converting setting are as following table:
RGB to YUV YUV to RGB Color space converting table
RGB to YUV
601
reg 16~ 235 0 ~ 255 16~ 235 0 ~ 255 16~ 235 0 ~ 255 16~ 235 0 ~ 255
Reg_CSCSel[1:0] 20[1:0] 10 10 10 10 11 11 11 11
Reg_YoffSet[7:0] reg21 0x00 0x10 0x00 0x10 0x00 0x10 0x00 0x10
Reg_CoffSet[7:0] reg22 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80
Reg_RGBOffSet[7:0] reg23 0x00 0x10 0x00 0x10 0x00 0x10 0x00 0x10
Reg_Matrix11V[13:0] reg24 0xB2 0x09 0xB8 0xE5 0x00 0x4F 0x00 0x4F
reg25 0x04 0x04 0x05 0x04 0x08 0x09 0x08 0x09
Reg_Matrix12V[13:0] reg26 0x64 0x0E 0xB4 0x78 0x6A 0x81 0x53 0xBA
reg27 0x02 0x02 0x01 0x01 0x3A 0x39 0x3C 0x3B
Reg_Matrix13V[13:0] reg28 0xE9 0xC8 0x93 0x81 0x4F 0xDF 0x89 0x4B
reg29 0x00 0x00 0x00 0x00 0x3D 0x3C 0x3E 0x3E
Reg_Matrix21V[13:0] reg2A 0x93 0x0E 0x49 0xCE 0x00 0x4F 0x00 0x4F
reg2B 0x3C 0x3D 0x3C 0x3C 0x08 0x09 0x08 0x09
Reg_Matrix22V[13:0] reg2C 0x18 0x84 0x18 0x84 0xF7 0xC2 0x51 0x56
reg2D 0x04 0x03 0x04 0x03 0x0A 0x0C 0x0C 0x0E
Reg_Matrix23V[13:0] reg2E 0x56 0x6E 0x9F 0xAE 0x00 0x00 0x00 0x00
reg2F 0x3F 0x3F 0x3F 0x3F 0x00 0x00 0x00 0x00
Reg_Matrix31V[13:0] reg30 0x49 0xAC 0xD9 0x49 0x00 0x4F 0x00 0x4F
reg31 0x3D 0x3D 0x3C 0x3D 0x08 0x09 0x08 0x09
Reg_Matrix32V[13:0] reg32 0x9F 0xD0 0x10 0x33 0x00 0x00 0x00 0x00
reg33 0x3E 0x3E 0x3F 0x3F 0x00 0x00 0x00 0x00
Reg_Matrix33V[13:0] reg34 0x18 0x84 0x18 0x84 0xDB 0x1E 0x87 0xE7
reg35 0x04 0x03 0x04 0x03 0x0D 0x10 0x0E 0x10
RGB to YUV 709 YUV to RGB
601
YUV to RGB
709
Video I/O and Video Data I/O Tristate
The video output I/O and video data I/O have tristate control to disable the video output. Whenever the
AV mute detected, video output should be disabled.
IT6605 implement the automatic mute mechanism, as the following registers:
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IT6605 PROGRAMMING GUIDE
Forcecolmod:
20 CSC_CTRL W/R 7
89 TriState_Ctrl W/R 7
6
5
4
3:2
1:0
6
5
4
3:0
VDGatting
VDIOLDisable
VIOSel
ForceColMod
ColMod_Set
CSCSel
DisVAutomute
TriVdIO
Tri_vdo
Tri_SPDIF
Tri_I2S
If reg89[6] = ‘1’, all video clock, H/V sync and data are tri-stated. When reg89[7] = ‘1’, AVMute will
not affect the video output, other wi se when AVMute = ‘1’, the video output is tri-stated automatically.
If reg89[7] = ‘1’, and AVMute (reg65[2] represent the AVMute status transmit by HDMI general packet)
switched from ‘1’ to ‘0’, the video enable should following the procedure:
reg1B[1] = ‘1’
reg1B[1] = ‘0’
reg89[6] = ‘1’
reg89[6] = ‘0’
reg20[7] = ‘1’
0x00
0:color mode auto adjusted according to AVI info
1: color mode is forced by register
0x80 Would be removed if not necessary
reg20[7] = ‘0’
Then the video output will not be tri-stated and the output is available.
Event of Video Process
There are several flags about video status, defined in reg15(interrupt status 0) and reg8B(interrupt
status 3), as following:
Reg
Offset
0x13 Interrupt0 RO 5
0x14 Interrupt
0x8B Interrupt3 RO 7
0x8C Interrupt
Reg_Name W/R Bits Status Description
Video mode change
HDMI/DVI mode swap change
Video stable is off
Video stable is on
Selected port 5V is off
Selected port 5V is on
1 : enable the int signal by the event.
Rx clock change detect Int
Rx clock on detect Int
1 : enable the int signal by the event.
Mask 0
mask 3
4
3
2
1
0
R/W 5
4
3
2
1
0
6
5
4
3
2
1
0
R/W 7
6
5
4
3
2
1
0
VidMode_Chg
HDMIMode_Chg
SCDTOFF
SCDTON
Pwr5VOff
Pwr5Von
VidMode_Chg
HDMIMode_Chg
SCDTOFF
SCDTON
Pwr5VOff
Pwr5Von
CLKCHG_DET
rxckon_Det
HDCPoff_det
Symerr_det
CD_det
Genpkt_det
ISRC2_Det
ISRC1_Det
CLKCHG_DET
HDCPoff_det_mask
rxckon_Det_mask
Symerr_det
CD_det
Genpkt_det
ISRC2_Det
ISRC1_Det
When the bit in reg13 or reg8B[7:6] raised, set reg19[0] = ‘1’ → ‘0’ will clear it include the INT signal.
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